1

E-CAD LABORATORY
MANUAL
 2

EXPERIMENT-1

AIM: To Design all gates using Verilog and Simulate the design.

Tools: Xilinx Vivado

VERILOG CODE:

module all_gates(a, b, and_out, or_out, notA_out, notB_out,nand_out, nor_out, xor_out,

xnor_out);
input a;
input b;
output and_out;
output or_out;
output notA_out;
output notB_out;

output nand_out;
output nor_out;
output xor_out;
output xnor_out;
not g1(notA_out,a);
not g2(notB_out,b);

and g3(and_out,a,b);
or g4(or_out,a,b);
nand g5(nand_out,a,b);
nor g6(nor_out,a,b);
xor g7(xor_out,a,b);
xnor g8(xnor_out,a,b);

endmodule
 3

RESULT:
 4

EXPERIMENT-2

AIM: To Design the 2x4 Decoder using Verilog and Simulate the design.

Tools: Xilinx Vivado

VERILOG CODE:

module decoder2x4(i1, i2, O0, O1, O2, O3);

input i1;
input i2;
output O0;
output O1;
output O2;
output O3;

wire not_i1,not_i2;

assign not_i1=~i1;
assign not_i2=~i2;

assign O0= not_i1 & not_i2;

assign O1= i1 & not_i2;
assign O2= not_i1 & i2;
assign O3= i1 & i2;

endmodule

RESULT:
 5

EXPERIMENT-3

AIM: To Design the 4x2 encoder (with and without priority) using Verilog and Simulate the
design.

Tools: Xilinx Vivado

VERILOG CODE:

Without Priority:

module encoder4x2(in,reset,clock,out);
input [3:0] in;
input clock,reset;
output [1:0] out;
reg [1:0] out;
always @(posedge clock)
if (reset)
out <= 2'b00;
else
case (in)
4'b0001 : out <= 2'b00;
4'b0010 : out <= 2'b01;
4'b0100 : out <= 2'b10;
4'b1000 : out <= 2'b11;
default : out <= 2'b00;
endcase
endmodule
 6

With Priority:

module priority_encoder4x2(in,reset,clock,out);

input [3:0] in;

input clock,reset;

output [1:0] out;

reg [1:0] out;

always @(posedge clock)

if (reset)

out <= 2'b00;

else

casex (in)

4'b0001 : out <= 2'b00;

4'b001X : out <= 2'b01;

4'b01XX : out <= 2'b10;

4'b1XXX : out <= 2'b11;

default : out <= 2'b00;

endcase

endmodule

RESULT:
Encoder

Priority Encoder
 7

EXPERIMENT-4

AIM: To Design the 8x1 Multiplexer using Verilog and Simulate the design.

Tools: Xilinx Vivado

VERILOG CODE:

module Mux8x1(in1,in2,in3,in4,in5,in6,in7,in8,sel3,out);

input in1,in2,in3,in4,in5,in6,in7,in8;
input [2:0] sel3;
output out;

reg out;

always @(sel3,in1,in2,in3,in4,in5,in6,in7,in8)
case (sel3)
3'b000: out = in1;
3'b001: out = in2;
3'b010: out = in3;
3'b011: out = in4;
3'b100: out = in5;
3'b101: out = in6;
3'b110: out = in7;
3'b111: out = in8;
endcase

endmodule
RESULT:
 8

EXPERIMENT-5

AIM: To Design the 4-bit binary to gray code using Verilog and Simulate the Design.

Tools: Xilinx Vivado

VERILOG CODE:

module bin_to_gray_4bit(bin_in, gray_out);

input [3:0] bin_in;

output [3:0] gray_out;

assign gray_out[3]=bin_in[3];

assign gray_out[2]=bin_in[3]^bin_in[2];

assign gray_out[1]=bin_in[2]^bin_in[1];

assign gray_out[0]=bin_in[1]^bin_in[0];

endmodule

RESULT:
 9

EXPERIMENT-6

AIM: To Design the comparator using Verilog and Simulate the design.

Tools: Xilinx Vivado

VERILOG CODE:

Comparator

module comparator(A, B, Comp);

input [7:0] A;

input [7:0] B;

output Comp;

assign Comp = A >= B ? 1'b1 : 1'b0;

endmodule

RESULT:
 10

EXPERIMENT-7

AIM: To Design the fulladder using Verilog and Simulate the Design.

Tools: Xilinx Vivado

VERILOG CODE:

module fulladder(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

assign sum = a ^ b ^ c;

assign carry = (a & b)|( b & c) | (c & a);

endmodule

RESULT:
 11

EXPERIMENT-8

AIM: To Design all the SR, D, T, JK flipflops using Verilog and Simulate the Design.

Tools: Xilinx Vivado

VERILOG CODE:

SR Flipfloop:

module SRFF(S, R, clock, reset,Q,Qbar);

input S, reset;

input R;

input clock;

output Q,Qbar;

reg Q,Qbar;

always@(posedge clock)

if (reset)

begin

Q<=1'b0;

Qbar<=1'b1;

end else

if (S==1'b0 && R==1'b0)

begin

Q<=Q;

Qbar<=Qbar;

end else

if (S==1'b1 && R==1'b0)

begin

Q<=1'b1;

Qbar<=1'b0;

end else
 E-CAD & VLSI LAB 12

if (S==1'b0 && R==1'b1)

begin

Q<=1'b0;

Qbar<=1'b1;

end else

if (S==1'b1 && R==1'b1)

begin

Q<=1'bx;

Qbar<=1'bx;

end

endmodule

D Flipfloop:

module DFF(D, Q, reset, clock);

input D;
output Q;
input reset;
input clock;
reg Q;
always@(posedge clock)
if(reset)

Q<=1'b0;
else
Q<=D;
endmodule
 E-CAD & VLSI LAB 13

JK Flipfloop:

module JKFF(j, k, clock, reset, Q, Qbar);

input j;
input k;
input clock;
input reset;

output Q;
output Qbar;
reg Q, Qbar;
always@(posedge clock)
if (reset)
begin

Q<=1'b0;
Qbar<=1'b1;
end else
if (j==1'b0 && k==1'b0)
begin
Q<=Q;

Qbar<=Qbar;
end else
if (j==1'b1 && k==1'b0)
begin
Q<=1'b1;
Qbar<=1'b0;

end else
if (j==1'b0 && k==1'b1)
begin
 E-CAD & VLSI LAB 14

Q<=1'b0;
Qbar<=1'b1;
end else
if (j==1'b1 && k==1'b1)

begin
Q<=~Q;
Qbar<=~Qbar;
end
endmodule

T Flipfloop:

module TFF(T, Q, clock, reset);

input T;

output Q;

input clock;

input reset;

reg Q;

always@(posedge clock)

if(reset)

Q<=1'b0;

else

if (!T)

Q<=Q;

else

Q<=~Q;

endmodule
 E-CAD & VLSI LAB 15

RESULT:

SR FlipFlop

D FlipFlop

JK FlipFlop

T FlipFlop
 VLSI LAB 1

EXPERIMENT- 1

AIM: To design and simulate the CMOS inverter and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

PROCEDURE:
 VLSI LAB 2

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

LAYOUT:
 VLSI LAB 3
RESULT:
 VLSI LAB 4

EXPERIMENT- 2

AIM: To design and simulate the CMOS NAND gate and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:
 VLSI LAB 5

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.
 VLSI LAB 6

LAYOUT:

RESULT:
 VLSI LAB 7

EXPERIMENT- 3

AIM: To design and simulate the CMOS NOR gate and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:
 VLSI LAB 8

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.
 VLSI LAB 9

LAYOUT:

RESULT:
 VLSI LAB 10

EXPERIMENT- 4

AIM: To design and simulate the CMOS AND gate and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:
 VLSI LAB 11

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.
 VLSI LAB 12

LAYOUT:

RESULT: