Multicycle Mips Architecture

Arquitectura de Computador
Módulo 1
Introduction
• Datapath
• Datapath and Control signals
• Control unit
• How to determine the clock period or clock rate?
• Performance
Multicycle Mips Architecture
• Microarchitecture
• How the architecture is implemented in hardware

Processor Memory

Input/Output
devices
Multicycle Mips Architecture
• Microarchitecture
• How the architecture is implemented in hardware

Control: control signals

Processor

Datapath: functional blocks

Multicycle Mips Architecture
• Microarchitecture
• How the architecture is implemented in hardware
Interprets the instructions
-Enables the signals to generate the
following address of the next instruction
Control: control signals (PC)
-Responsible of generating the correct
sequence for the execution of instructions
Processor

Functional units (ALU, Full Adders)

Datapath: functional blocks Registers
Support units (Multiplexers, buses,
decoders,etc)
 Multicycle Mips Architecture
Microarchitecture Instruction Fetch:
Steps for a generic implementation PC (instruction
address) –>
Memory
PC+4
Decode: Control
unit

Read registers
• Arithmetic/logical result
• Memory address for load/store
• Branch target address
Execution
Depending on
instruction class

Write /Read • Write Register

Depending on • Read Memory
instruction class • Write Memory

Write
RF
Multicycle Mips Architecture

•Type R
•Type I
•Type J
Datapath
Multicycle Mips Architecture
31-26 25-21 20-16 15-11 10-6 5-0
Opcode rs rt rd shamt function

•Type R 31-26 25-21 20-16 15-0

•Type I Opcode rs rt Immediate/offset

31-26 25-0
•Type J Opcode Target=Address

Datapath
Multicycle Mips Architecture
Datapath

31
Multicycle Mips Architecture
Datapath and Control signals

[25..0]

6
Single-Cycle Mips Architecture
• ALU Control
Multicycle Mips Architecture
• ALU Control
 Multicycle Mips Architecture
Datapath and Control signals

31
Multicycle Mips Architecture

31
Multicycle Mips Architecture
Branch
instructions

Instruction
Fetch Jump instructios

Decode and Memory access

Start instructions
Register fetch

R-type
instructions
 Multicycle Mips Architecture
Memory
Unit Control Write
Address
computation

Memory Writeback
Read Memory-RF

Write
execute
ALU-RF
Decode and
Instruction
register
fetch
fetch

Completion
Branch

Completion
Jump
 Multicycle Mips Architecture
Memory
Unit Control Write
Address
computation
OP=0x23 or 0x2B
Memory Writeback
Read Memory-RF

OP=0x00 Write
execute
ALU-RF
Decode and
Instruction
register
fetch
fetch
OP=0x04

Completion
OP=0x02 Branch

Completion
Jump
 Memory Write

Multicycle Mips Architecture Address Computation

IorD=1
MemWrite=1
OP=0x2B
Unit Control
ALUSrcA=1 Memory Read Writeback Mem-RF
ALUSrcB=10 OP=0x23
OP=0x23 or 0x2B ALUOP=000
IorD=1 RegDst=00
MemRead=1 MemtoReg=01
Execute RegWrite=1
Decode OP=0x00
ALUSrcA=1
Fetch ALUSrcA=0 ALUSrcB=00 Writeback ALU-RF
IorD=0
ALUSrcB=11 ALUOP=010
MemRead=1 RegDst=01
ALUOP=000
ALUSrcA=0 MemtoReg=00
ALUSrcB=01
ALUOP=000
OP=0x04 Completion Branch RegWrite=1

PCSrc=00
ALUSrcA=1
PCWrite=1
ALUSrcB=00
IRWrite=1
OP=0x02 ALUOP=001
PCSrc=01
Branch=1

Completion Jump

PCSrc=10
PCWrite=1
 Multicycle Mips Architecture
Performance

31

Clock Period > max (tpcq_PC + tmux + tmem+ tsetup_IR, tpcq_IR+ tRFread + tsetup_AB, tpcq_AB + max(tmux +tALU +tmux+ tsetup_PC, tmem), tpcq_ALUout+ tmux + tmem)
Multicycle Mips Architecture
• Performance
Main:
Lui $S1, 0x1000
Ori $S1, $S1, 0x0000
Addi $S4, $0, 5
Addi $S5, $0, 0
For:
Beq $S4,$S5, Exit
Sll $t1, $S5,2
Add $t1, $St1,$S1
Lw $S2, 0($t1)
Lw $S3, 4($t1)
Sub $S3, $S3,$S4
Sw $S3, 100($t1)
Addi $S5,$S5,1
J for
Exit :
Jr $ra
Tex=203cycles/1GHz=203ns
 Multicycle Mips Architecture
• Performance
Main:
4 Lui $S1, 0x1000
4 Ori $S1, $S1, 0x0000
4 Addi $S4, $0, 5
4 Addi $S5, $0, 0
For:
3 Beq $S4,$S5, Exit
4 Sll $t1, $S5,2
4 Add $t1, $St1,$S1
5 Lw $S2, 0($t1)
5 Lw $S3, 4($t1)
4 Sub $S3, $S3,$S4
4 Sw $S3, 100($t1)
4 Addi $S5,$S5,1
3 J for
Exit :
4 Jr $ra
Tex=203cycles/1GHz=203ns
Multicycle Mips Architecture
• Performance
Main:
Lui $S1, 0x1000
Ori $S1, $S1, 0x0000
Addi $S4, $0, 5 16
Addi $S5, $0, 0
For:
Beq $S4,$S5, Exit
Sll $t1, $S5,2
Add $t1, $St1,$S1
Lw $S2, 0($t1)
Lw $S3, 4($t1) (36*5)+3
Sub $S3, $S3,$S4
Sw $S3, 100($t1)
Addi $S5,$S5,1
J for
Exit :
Jr $ra
4 Tex=203cycles/1GHz=203ns
31
Reference
Hennessy, John L. and Patterson, David A., Computer architecture : a
quantitative approach, 6th Edition. Morgan Kaufmann, 2017. Chapter
4.