SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005

D 2-V to 5.5-V VCC Operation SN54LV10A . . . J OR W PACKAGE

SN74LV10A . . . D, DB, DGV, NS, OR PW PACKAGE
D Max tpd of 7 ns at 5 V (TOP VIEW)
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C 1A 1 14 VCC
D Typical VOHV (Output VOH Undershoot) 1B 2 13 1C
>2.3 V at VCC = 3.3 V, TA = 25°C 2A 3 12 1Y
2B 4 11 3C
D Ioff Supports Partial-Power-Down Mode
5 10
2C 3B
Operation
2Y 6 9 3A
D Latch-Up Performance Exceeds 100 mA Per GND 7 8 3Y
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A) SN54LV10A . . . FK PACKAGE
(TOP VIEW)
− 200-V Machine Model (A115-A)

VCC
− 1000-V Charged-Device Model (C101)

NC

1C
1B
1A
description/ordering information 3 2 1 20 19
2A 4 18 1Y
These triple 3-input positive-NAND gates are NC 5 17 NC
designed for 2-V to 5.5-V VCC operation. 2B 6 16 3C
The ’LV10A devices perform the Boolean function NC 7 15 NC
Y = A • B • C or Y = A + B + C in positive logic. 2C 8 14 3B
9 10 11 12 13
These devices are fully specified for

2Y

3Y
3A
GND
NC
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices NC − No internal connection
when they are powered down.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube of 50 SN74LV10AD
SOIC − D LV10A
Reel of 2500 SN74LV10ADR
SOP − NS Reel of 2000 SN74LV10ANSR 74LV10A
SSOP − DB Reel of 2000 SN74LV10ADBR LV10A
−40°C to 85°C
Tube of 90 SN74LV10APW
TSSOP − PW Reel of 2000 SN74LV10APWR LV10A
Reel of 250 SN74LV10APWT
TVSOP − DGV Reel of 2000 SN74LV10ADGVR LV10A
CDIP − J Tube of 25 SNJ54LV10AJ SNJ54LV10AJ
−55°C
−55 C to 125
125°C
C CFP − W Tube of 150 SNJ54LV10AW SNJ54LV10AW
LCCC − FK Tube of 55 SNJ54LV10AFK
SNJ54LV10AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.



 
   !"#$ $%$  & Copyright  2005, Texas Instruments Incorporated
  $'("%$ !((#$ % ' )!*+%$ %#, (! $'(" 
)#'%$ )#( # #(" ' #-% $(!"#$ %$%( .%((%$/,
(!$ )(#$0 # $ $##%(+/ $+!# #$0 ' %++
)%(%"##(,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





   
   
SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005

FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B C Y
H H H L
L X X H
X L X H
X X L H

logic diagram, each gate (positive logic)

A
B Y
C

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





   
   
SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005

recommended operating conditions (see Note 4)

SN54LV10A SN74LV10A
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VIL Low-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 µA
VCC = 2.3 V to 2.7 V −2 −2
IOH High-level output current
VCC = 3 V to 3.6 V −6 −6 mA
VCC = 4.5 V to 5.5 V −12 −12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current
VCC = 3 V to 3.6 V 6 6 mA
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 200 200
∆t/∆v Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
VCC = 4.5 V to 5.5 V 20 20
TA Operating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54LV10A SN74LV10A
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN TYP MAX
IOH = −50 µA 2 V to 5.5 V VCC−0.1 VCC−0.1
IOH = −2 mA 2.3 V 2 2
VOH V
IOH = −6 mA 3V 2.48 2.48
IOH = −12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
VOL V
IOL = 6 mA 3V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 µA
Ioff VI or VO = 0 to 5.5 V 0 5 5 µA
Ci VI = VCC or GND 3.3 V 1.9 1.9 pF

 &   $'("%$ $#($ )(! $ # '("%1# (

#0$ )%# ' #1#+)"#$, &%(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0 
%$0# ( $$!# ## )(! .! $#,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3





   
   
SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005

switching characteristics over recommended operating free-air temperature range,

VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD TA = 25°C SN54LV10A SN74LV10A
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tpd A, B, or C Y CL = 15 pF 7.1* 13* 1* 15.5* 1 15.5 ns
tpd A, B, or C Y CL = 50 pF 10.3 17.1 1 20.5 1 20.5 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD TA = 25°C SN54LV10A SN74LV10A
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tpd A, B, or C Y CL = 15 pF 5.2* 8.4* 1* 10* 1 10 ns
tpd A, B, or C Y CL = 50 pF 7.4 11.9 1 13.5 1 13.5 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD TA = 25°C SN54LV10A SN74LV10A
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tpd A, B, or C Y CL = 15 pF 3.9* 5.9* 1* 7* 1 7 ns
tpd A, B, or C Y CL = 50 pF 5.4 7.9 1 9 1 9 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.

noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)

SN74LV10A
PARAMETER UNIT
MIN TYP MAX
VOL(P) Quiet output, maximum dynamic VOL 0.2 0.8 V
VOL(V) Quiet output, minimum dynamic VOL 0 −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3.2 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 5: Characteristics are for surface-mount packages only.

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS VCC TYP UNIT
3.3 V 14
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz pF
5V 16.7

 &   $'("%$ $#($ )(! $ # '("%1# (

#0$ )%# ' #1#+)"#$, &%(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0 
%$0# ( $$!# ## )(! .! $#,

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





   
   
SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005

PARAMETER MEASUREMENT INFORMATION

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

VOH Output ≈VCC
In-Phase 50% VCC 50% VCC Waveform 1 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ

VOH Output
VOH
Out-of-Phase Waveform 2 VOH − 0.3 V
50% VCC 50% VCC 50% VCC
Output S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LV10AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A

& no Sb/Br)
SN74LV10ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A
& no Sb/Br)
SN74LV10ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A
& no Sb/Br)
SN74LV10ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV10A
& no Sb/Br)
SN74LV10APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A
& no Sb/Br)
SN74LV10APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A
& no Sb/Br)
SN74LV10APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV10ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LV10ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV10APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV10ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LV10ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LV10APWR TSSOP PW 14 2000 367.0 367.0 35.0

Pack Materials-Page 2
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated