1

STANDARD COMBINATIONAL MODULES

• DECODERS

• ENCODERS

• MULTIPLEXERS (Selectors)

• DEMULTIPLEXERS (Distributors)

• SHIFTERS

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BINARY DECODERS

HIGH-LEVEL DESCRIPTION:
Inputs: x = (xn−1, . . . , x0), xj ∈ {0, 1}
Enable E ∈ {0, 1}
Outputs: y = (y2n−1, . . . , y0), yi ∈ {0, 1}


 1 if (x = i) and (E = 1)
Function: yi = 


0 otherwise

n−1
x= xj 2 j
X

j=0

and
i = 0, . . . , 2n − 1

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E
y
En 0
0
y

n-Input Binary Decoder

1
1
y
x 2
0 0 2

Outputs
Inputs

x 1
1

x n-1
n-1

y n
n 2 -1
2 -1

Figure 9.1: n-INPUT BINARY DECODER.

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EXAMPLE 9.1: 3-INPUT BINARY DECODER

E x2 x1 x0 x y7 y6 y5 y4 y3 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 1 0 0 0 0 0 0 1 0
1 0 1 0 2 0 0 0 0 0 1 0 0
1 0 1 1 3 0 0 0 0 1 0 0 0
1 1 0 0 4 0 0 0 1 0 0 0 0
1 1 0 1 5 0 0 1 0 0 0 0 0
1 1 1 0 6 0 1 0 0 0 0 0 0
1 1 1 1 7 1 0 0 0 0 0 0 0
0 - - - - 0 0 0 0 0 0 0 0
BINARY SPECIFICATION:
Inputs: x = (xn−1, . . . , x0), xj ∈ {0, 1}
E ∈ {0, 1}
Outputs: y = (y2n−1, . . . , y0), yi ∈ {0, 1}

Function: yi = E · mi(x) , i = 0, . . . , 2n − 1

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EXAMPLE 9.2: IMPLEMENTATION OF 2-INPUT DECODER

y0 = x01x00E y1 = x01x0E y2 = x1x00E y 3 = x 1 x0 E

y
0

x0 y1

y
x 2
1
y3

Figure 9.2: GATE NETWORK IMPLEMENTATION OF 2-INPUT BINARY DECODER.

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DECODER USES

OPCODE field

Instruction Other fields

4-Input Binary
E=1 En Decoder
15 . . . 4 3 2 1 0

LOAD
STORE
ADD Decoded
operations
JUMP

Figure 9.3: OPERATION DECODING.

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DECODER USES

Cell referenced when

address is
Data input Data input
00000000000010 Binary cell

E=1

Binary Decoder
Address 1
14 2
14
RAM Module Address

14
(2 x 1)
16383

Read/write

Read/write
Data output

(a) (b) Data output

Figure 9.4: RANDOM ACCESS MEMORY (RAM): a) MODULE; b) ADDRESSING OF BINARY CELLS.

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BINARY DECODER AND or GATE

• UNIVERSAL

Example 9.5:
x2 x1 x0 z2 z1 z0
000 0 1 0
001 1 0 0
010 0 0 1
011 0 1 0
100 0 0 1
101 1 0 1
110 0 0 0
111 1 0 0

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(y7, . . . , y0) = dec(x2, x1, x0, 1)

z2(x2, x1, x0) = y 1 y5 y7
z1(x2, x1, x0) = y 0 y3
z0(x2, x1, x0) = y 2 y4 y5

E=1

y0
En 0
y1
Binary Decoder 1
y2 z2
2
x0 0 y3
3
x1 y4 z1
1
4
x2 2 y5
5
y z
6 0
6
y
7
7

Figure 9.5: NETWORK IN EXAMPLE 9.5

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DECODER NETWORKS: COINCIDENT DECODING

x = (xleft, xright)

xleft = (x7, x6, x5, x4)

xright = (x3, x2, x1, x0)
x = 24 × xleft + xright

y = DEC(xleft)
w = DEC(xright)
zi = AN D(ys, wt)

i = 24 × s + t

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x3 x2 x1 x0
0 1 0 0
4-Input Binary
1 En Decoder
15 . . .4 3 2 1 0

w 1
4

z0

x4 0
2 1 0
4-Input Binary

1 y
Decoder

x5 2

x6 0 1
...

0 z 36
x7
15

En
1
E

z 255

Figure 9.6: 8-INPUT COINCIDENT DECODER.

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n-INPUT COINCIDENT DECODER

y = dec(xleft, E)

w = dec(xright , 1)

z = (and(y2n/2−1, w2n/2−1), . . . , and(ys, wt), . . . , and(y0, w0))

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x n/2-1 x0

1 En DECODER W

w n/2 w0
2 -1
wt

z0
y0
DECODER Y

x n/2

ys
x n-1

En
z n/2
y n/2 2 s+t
2 -1
E

z n
2 -1

Figure 9.7: n-INPUT COINCIDENT DECODER.

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TREE DECODING

x = (xleft, xright)

xleft = (x3, x2)

xright = (x1, x0)

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4-INPUT TREE DECODER

x3 x2 x1 x0

x=6: 0 1 1 0

1 0

Level 1 E En DEC

3 2 1 0

0 0 1 0

1 0 En 1 0 En 1 0 En 1 0 En
Level 2 DEC 3 DEC 2 DEC 1 DEC 0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

z 15 z 12 z8 z 6 =1 z4 z0

Figure 9.8: 4-INPUT TREE DECODER.

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n-INPUT TREE DECODERr

w = dec(xleft, E)

z = (dec(xright, w2n/2−1), . . . , dec(xright , wt), . . . , dec(xright , w0))

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x x
left right
x n-1 x n/2 x n/2-1 x0

Level 1 E En
DEC

w n/2
2 -1 w0
wt

En En En
Level 2 n/2
DEC 2 -1 DEC t DEC 0

z n z 2 (n/2)t+s z0
2 -1

Figure 9.9: n-INPUT TWO-LEVEL TREE DECODER.

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COMPARISON OF DECODER NETWORKS

Coincident Tree
Decoder modules 2 2k + 1
and gates 22k –
Load per network input 1 decoder input 2k decoder inputs (max)
Fanout per decoder output 2k and inputs 1 enable input
Number of module inputs 2k + 2 + 22k+1 1 + k + 2k + k2k
(related to number of
connections)
Delay tdecoder + tAND 2tdecoder

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EXAMPLE 9.6: 6-INPUT DECODER

x0 0
Decoder

z0
x1 1
x0 0 z0

Decoder
x2 z1 1 z1
7 x1
E
x2
7 z7

x3 0

Decoder
1
1 x4
x5 7
x3 0
Decoder

1 0 z 56

Decoder
x4
1 z 57
x5 z 63
7
7 z 63

(a) (b)

Figure 9.10: IMPLEMENTATION OF 6-INPUT DECODER. a) COINCIDENT DECODER. b) TREE DECODER.

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EXAMPLE 9.6 (cont.)

Coincident Tree
Decoder modules 2 9
and gates 64 –
Load per network input 1 decoder input 8 decoder inputs (max)
Fanout per decoder output 8 and inputs 1 enable input
Number of module inputs 136 36
Delay 3d 4d

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Decoder Cell array

Data input
Binary cell

E=1
0

0 1

Tree Decoder
1
12 2
2

Address
4095

4096 lines
from decoder
to cell array 4095

Read/write
Data output
(a)

Figure 9.11: a) SYSTEM WITH TREE DECODER.

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Decoder E=1 Cell array Data input

Decoder
Binary
6 0

63 1

12

Address E=1

0
Decoder
Binary
6

63 4095

Read/write 128 lines

from decoder Modified binary cell Data output
to cell array

equivalent to coincident decoder

(b)

Figure 9.11: b) SYSTEM WITH COINCIDENT DECODER.

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BINARY ENCODERS

En

-Input Binary Encoder

x 0
0
x y
1 1 0
0
y

Outputs
Inputs 1
1

y n-1
n-1

n
2
x n n
2 -1 2 -1
Ac

Figure 9.12: 2n -INPUT BINARY ENCODER.

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BINARY ENCODER: HIGH-LEVEL SPECIFICATION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}, with at most one xi = 1

E ∈ {0, 1}
Outputs: y = (yn−1, . . . , y0), yj ∈ {0, 1}
A ∈ {0, 1}

i if (xi = 1) and (E = 1)


Function: y = 



0 otherwise
 1 if

 (some xi = 1) and (E = 1)
A = 
0 otherwise

n−1
y= yj 2 j
X

j=0

and
i = 0, . . . , 2n − 1

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EXAMPLE 9.7: FUNCTION OF AN 8-INPUT BINARY ENCODER

E x7 x6 x5 x4 x3 x2 x1 x0 y y2 y1 y0 A
1 0 0 0 0 0 0 0 1 0 0 0 0 1
1 0 0 0 0 0 0 1 0 1 0 0 1 1
1 0 0 0 0 0 1 0 0 2 0 1 0 1
1 0 0 0 0 1 0 0 0 3 0 1 1 1
1 0 0 0 1 0 0 0 0 4 1 0 0 1
1 0 0 1 0 0 0 0 0 5 1 0 1 1
1 0 1 0 0 0 0 0 0 6 1 1 0 1
1 1 0 0 0 0 0 0 0 7 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 - - - - - - - - 0 0 0 0 0

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BINARY SPECIFICATION OF ENCODER

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}, with at most one xi = 1

E ∈ {0, 1}

Outputs: y = (yn−1, . . . , y0), yj ∈ {0, 1}

A ∈ {0, 1}

Function: yj = E · P(xk ), j = 0, . . . , n − 1

A = E · P(xi), i = 0, . . . , 2n − 1

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EXAMPLE 9.8

y0 = E · (x1 x3 x5 x7)

y1 = E · (x2 x3 x6 x7)

y2 = E · (x4 x5 x6 x7)

A = E · (x0 x1 x2 x3 x4 x5 x6 x7)

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x7 x6 x5 x4 x3 x2 x1 x0
E

y0

y1

y2

Figure 9.13: IMPLEMENTATION OF AN 8-INPUT BINARY ENCODER.

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USES OF BINARY ENCODERS

Wind direction
in unary code
0
0
1 Wind direction
1

BINARY ENCODER
n in binary code
0
2
nw ne 0 1
0
3 1 0
w e 0 4
2 0
0
sw se 5
s 0 6
0
7

Figure 9.14: WIND DIRECTION ENCODER.

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PRIORITY ENCODERS: HIGH-LEVEL DESCRIPTION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}

Outputs: y = (yn−1, . . . , y0), yj ∈ {0, 1}

Function: 

 i if (xi = 1) and (xk = 0, k > i) and (E = 1)
y =


 0 otherwise





 1 if (some xi = 1) and (E = 1)
A =


 0 otherwise



n−1
y= yj 2 j
X

j=0

and
i, k ∈ {0, 1, . . . , 2n − 1}

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8-INPUT PRIORITY ENCODER

E x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0 A
1 0 0 0 0 0 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1 - 0 0 1 1
1 0 0 0 0 0 1 - - 0 1 0 1
1 0 0 0 0 1 - - - 0 1 1 1
1 0 0 0 1 - - - - 1 0 0 1
1 0 0 1 - - - - - 1 0 1 1
1 0 1 - - - - - - 1 1 0 1
1 1 - - - - - - - 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0
0 - - - - - - - - 0 0 0 0

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E
Lowest
En
priority z
0

-Input Binary Encoder

x 0 0 0
0 z

Priority Resolution
x 1 y
1 1 1 1 0
0
y

Outputs
1
Inputs

y n-1
n-1

n
z n

2
x n n n 2 -1 n
2 -1 2 -1 2 -1 2 -1
Highest Ac
priority
A

Figure 9.15: PRIORITY ENCODER.

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PRIORITY RESOLUTION: HIGH-LEVEL AND BINARY-LEVEL
DESCRIPTION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}

Outputs: z = (z2n−1, . . . , z0), zi ∈ {0, 1}


 1 if (xi = 1) and (xk = 0, k > i)
Function: zi = 


0 otherwise
with i, k = 0, 1, . . . , 2n − 1
• BINARY DESCRIPTION:
zi = x02n−1x02n−2 . . . x0i+1xi , i = 0, 1, . . . , 2n − 1
OR ITERATIVELY

ci−1 = ci xi
zi = c0ixi

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x0 z0
c0
x0
z0 Cell

x1 x1 z1
z1
c1
x2
z2

x2
z2
x3 z3 c2

x3 z3

(a) (b)

Figure 9.16: 4-BIT PRIORITY RESOLUTION NETWORKS: a) PARALLEL; b) ITERATIVE.

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USES OF PRIORITY ENCODERS

Request E=1
lines

1 En
Device A 0
lowest Highest
priority priority

PRIORITY ENCODER
0 0 request
Device B 1 0

PROCESSOR
1 1
Device C 2 1

0
Device D 3
Ac
highest Request
priority present
A=1

Figure 9.17: RESOLVING INTERRUPT REQUESTS USING A PRIORITY ENCODER.

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E=1
x 7 x 6 x 5 x 4 x 3 x2 x1 x 0
0 0 1 0 1 0 0 1 En
1

ENCODER
PRIORITY
0
0
1
1
2

Ac

SHIFTER

(x shifted left 2 positions with 0s

inserted into vacated positions)
1 0 1 0 0 1 0 0

Figure 9.18: DETECTING THE LEFTMOST 1 IN A BIT-VECTOR AND REMOVING LEADING ZEROES.

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MULTIPLEXERS (selectors)

• HIGH-LEVEL AND BINARY-LEVEL DESCRIPTION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}
s = (sn−1, . . . , s0), sj ∈ {0, 1}
E ∈ {0, 1}
Outputs: z ∈ {0, 1}


 xs if E = 1
Function: z = 


0 if E = 0

n−1
s= sj 2 j
X

j=0

2nX
−1
 

z = E ·  xi · mi(s)
i=0

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x 0 En
0

2 - Input Multiplexer
x 1
1

Data inputs
x 2
2 Data output

n
x n n
2 -1 2 -1
n-1 0

s n-1 s0

Select inputs
Figure 9.19: 2n -INPUT MULTIPLEXER.

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EXAMPLE 9.11: 4-INPUT MULTIPLEXER

E s1 s0 z
1 0 0 x0
1 0 1 x1
1 1 0 x2
1 1 1 x3
0 - - 0

z = E · (x0m0(s1, s0) x1m1(s1, s0) x2m2(s1, s0) x3m3(s1, s0))

= E · (x0s01s00 x1s01s0 x2s1s00 x3s1s0)

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x0

x1

x z
2

x3

E
s s
1 0

Figure 9.20: GATE IMPLEMENTATION OF 4-INPUT MULTIPLEXER

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TYPICAL USES

R0 R1 R0 R2 R3 R4

0 1 0 1 2 3
SelA SelB
MUX A MUX B

For n-bit operands, Mux A

and MuxB replicated n times
A B and connected to the corresponding
bit s of the input vectors.
FUNCTIONAL
f UNIT

Example: SelA = 1, SelB = 2

Z = f(R1,R3)

Z= f(A,B)

Figure 9.21: MULTIPLEXER: EXAMPLE OF USE.

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MULTIPLEXER AS UNIVERSAL COMBINATIONAL MODULE

• connect input variables x to select inputs of multiplexer s

• set data inputs to multiplexer equal to values of function for corresponding

assignment of select variables

• using a variable at data inputs reduces size of the multiplexer

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EXAMPLE

E(x2, x1, x0) = m(1, 2, 4, 6, 7)

X

= x02(x01x0) x02(x1x00) x2(x01x00) x2(x1x00) x2(x1x0)

= x02m1(x1, x0) x02m2(x1, x0)

x2m0(x1, x0) x2m2(x1, x0) x2m3(x1, x0)

= x2m0(x1, x0) x02m1(x1, x0) 1 · m2(x1, x0) x2m3(x1, x0)

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E=1

0 0
En E=1

8 - Input Multiplexer
1 En
x 0
1 2 2

4 - Input Multiplexer
x’ 1
0 f = one-set(1,2,4,6,7) 2 f = one-set(1,2,4,6,7)
3

1 1 2
4
x
0 2 3
5

1 6 1 0
1 7 2 1 0
x x
Select 1 0
inputs
x x x
2 1 0
(a) (c)

x0 x0

0 1 0 1
x2 x’2 x2 1
x2 1 0 1 1

x1 x1
(b)

Figure 9.22: IMPLEMENTATION OF f (x2 , x1 , x0 ) = one-set(1,2,4,6,7): a) 8-INPUT MULTIPLEXER; b) K-map; c) 4-INPUT

MULTIPLEXER.

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EXAMPLE 9.12: ONE-BIT ADDER

Inputs: a, b, cin ∈ {0, 1}

Outputs: z, cout ∈ {0, 1}

a b cin z cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

z = (a0b0) · cin (a0b) · c0in (ab0) · c0in (ab) · cin

= cinm0(a, b) c0inm1(a, b) c0inm2(a, b) cinm3(a, b)
cout = 0 · m0(a, b) cinm1(a, b) cinm2(a, b) 1 · m3(a, b)

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E=1 E=1

cin En 0 En
0 0

4-Input Multiplexer

4-Input Multiplexer
c’in
1 1
z cout
2 2

3 1 3

1 0 1 0

z: cin cout : cin

0 1 0 1 0 0 1 0
a 1 0 1 0 a 0 1 1 1
b b

cin c’in 0 cin

a c’in cin a cin 1

b b

Figure 9.23: IMPLEMENTATION OF ONE-BIT ADDER WITH 4-INPUT MULTIPLEXERS.

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MULTIPLEXER TREES

sleft = (s3, s2)

sright = (s1, s0)

wj = x(4j+sright) , 0 ≤ j ≤ 3

z = wsleft

s = 4sleft + sright

z = x4sleft+sright = xs

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16-INPUT TREE MULTIPLEXER

x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x7 x6 x5 x4 x3 x2 x1 x0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
1 En 1 En 1 En 1 En
1 MUX 1 MUX 1 MUX 1 MUX
0 0 0 0
s1
0
s0
1
x 13 x9 x5 x1

3 2 1 0
E En
s3 MUX
1
1
s2 0
0

z = x9

Figure 9.24: TREE IMPLEMENTATION OF A 16-INPUT MULTIPLEXER.

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DEMULTIPLEXERS (distributors)

• A HIGH-LEVEL DESCRIPTION:
Inputs: x, E ∈ {0, 1}
s = (sn−1, . . . , s0) , sj ∈ {0, 1}
Outputs: y = (y2n−1, . . . , y0) , yi ∈ {0, 1}


 x if (i = s) and (E = 1)
Function: yi = 


0 if (i 6= s) or (E = 0)

n−1
s= sj 2 j , 0 ≤ i ≤ 2 n − 1
X

j=0

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E
y0
En 0
y1
1
y2

Demultiplexer
2
Data input Data outputs

(DMUX)
x

n
y n
2 -1
2 -1

n-1 0

s n-1 s0

Select inputs
Figure 9.25: 2n -OUTPUT DEMULTIPLEXER.

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EXAMPLE 9.13: 4-OUTPUT DEMULTIPLEXER

E s1 s0 s y3 y2 y1 y0
1 0 0 0 0 0 0 x
1 0 1 1 0 0 x 0
1 1 0 2 0 x 0 0
1 1 1 3 x 0 0 0
0 - - - 0 0 0 0

yi = E · x · mi(s), 0 ≤ i ≤ 2n − 1

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x y
0

y
1

y
2

y
3

s s
1 0
Figure 9.26: GATE NETWORK IMPLEMENTATION OF A 4-OUTPUT DEMULTIPLEXER.

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DMUX Sel
0 1 2 3

S0 S1 S2 S3

0 1 2 3
MUX

X For n-bit operands, Mux

and Dmux replicated n times
and connected to the corresponding
FUNCTIONAL bit s of the input/output vectors.
f UNIT

Z= f(X)

Figure 9.27: DEMULTIPLEXER: example of use.

Introduction to Digital Systems 9 – Standard Combinational Modules

 x n x n-1 xi x 0 x -1

n n-1 i 0 -1
shift/
s no shift
E
n-bit Simple Shifter
d left/
right
n-1 i 0

Introduction to Digital Systems

y n-1 yi y0

(a)

xn x n-1 x i+1 x 1 x 0 x -1

s= YES shift/
no shift E=1

d= RIGHT left/
right

y n-1 yi y0
SIMPLE SHIFTER

(b)

x n x n-1 x n-2 x i-1 x 0 x -1

shift/
s= YES no shift
E=1

left/
d= LEFT right
Figure 9.28: n-BIT SIMPLE SHIFTER: a) BLOCK DIAGRAM; b) RIGHT SHIFT; c) LEFT SHIFT.

y n-1 yi y0
9 – Standard Combinational Modules

(c)
54
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SIMPLE SHIFTER: HIGH-LEVEL DESCRIPTION
Inputs: x = (xn, xn−1, . . . , x0, x−1) , xj ∈ {0, 1}
d ∈ {RIGHT, LEF T }
s ∈ {Y ES, N O}
E ∈ {0, 1}
Outputs: y = (yn−1, . . . , y0) , yj ∈ {0, 1}

Function: 






xi−1 if (d = LEF T ) and (s = Y ES) and (E = 1)
x if (d = RIGHT ) and (s = Y ES) and (E = 1)




yi =  i+1







xi if (s = N O) and (E = 1)
 0 if (E = 0)




for 0 ≤ i ≤ n − 1.







0 left shift with 0 insert
x−1 =  1 left shift with 1 insert


 x
n−1 left rotate










0 right shift with 0 insert
xn =  1 right shift with 1 insert


 x
0 right rotate




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EXAMPLE 9.14: 4-INPUT SHIFTER

Control Data
s d x 4 x3 x2 x1 x0 x−1
1 0 0 1 1 0
No shift no – 0 0 1 1
Right shift yes right 1 0 0 1
Left shift yes left 0 1 1 0
y3 y2 y1 y0

Coding:
s d
0 no 0 right
1 yes 1 left

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xn x n-1 x n-2 x1 x0 x -1
d LEFT

RIGHT

E
s
NO SHIFT

y n-1 y0

(a)

xn x n-1 x n-2 x1 x0 x -1

E
En 3 2 1 0 En 3 2 1 0

1 MUX 1 MUX
0 0
s
d

y n-1 y0

(b)

Figure 9.29: IMPLEMENTATION OF A SIMPLE SHIFTER: a) WITH GATES; b) WITH MULTIPLEXERS.

Introduction to Digital Systems 9 – Standard Combinational Modules

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p-SHIFTER: HIGH-LEVEL DESCRIPTION

Inputs: x = (xn+p−1, . . . , xn, xn−1, . . . , x0, x−1, . . . , x−p) , xj ∈ {0, 1}

s ∈ {0, 1, ..., p}
d ∈ {LEF T, RIGHT }
E ∈ {0, 1}
Outputs: y = (yn−1, . . . , y0) , yj ∈ {0, 1}

Function: 






xi−s if (d = LEF T ) and (E = 1)
yi =  xi+s if (d = RIGHT ) and (E = 1)


 0 if (E = 0)




0≤i≤n−1

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p-SHIFTER

x n+p-1 x n x n-1 x 0 x -1 x -p

s distance
log(p+1) n-bit p-Shifter En E
d left/right

y n-1 y0
Figure 9.30: n-BIT p-SHIFTER.

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BARREL SHIFTER

Stage 0

Stage 1

Stage 2

Stage 3
n+2p

0 or 4 SHIFT

0 or 8 SHIFT
0 or 1 SHIFT

0 or 2 SHIFT
x

y
d

s0

s2

3
s

s
Figure 9.31: BARREL SHIFTER FOR p = 15.

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UNIDIRECTIONAL SHIFTERS

x6 x5 x4 x3 x2 x1 x0

En 3 2 1 0 En 3 2 1 0 En 3 2 1 0 En 3 2 1 0

1 MUX 1 MUX 1 MUX 1 MUX

0 0 0 0
s1
s0

y3 y2 y1 y0

Figure 9.32: MULTIPLEXER IMPLEMENTATION OF A 4-BIT RIGHT 3-SHIFTER.

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TYPICAL USES OF SHIFTERS

• ALIGNMENT OF A BIT-VECTOR

• REMOVAL OF THE LEADING (or trailing) BITS OF A VECTOR

• PERFORMING MULTIPLICATION OR DIVISION BY A POWER OF TWO

• EXTRACTING A SUBVECTOR from a bit-vector, using a shifter instead of

a selector

Introduction to Digital Systems 9 – Standard Combinational Modules