EEE241 Digital Logic Design (DLD)

Lecture 19 – Combinational Circuits

Dr. Muhammad Rizwan Azam

COMSATS University Islamabad (CUI) Islamabad, Pakistan.
 Lecture Outline

• Combination Circuits
• Decoders
• Encoders
 Decoders

• Extract “Information” from the code

• Binary Decoder
• Converts binary information from n I/p lines to a max. ofOnly one
unique O/p lines lamp will
• Generates 2n (or fewer) minterms of n input variables turn on
• Example: 2-bit Binary Number

1
x1 0 0
Binary
0 0
x0 Decoder
0
 Decoders

• 2-to-4 Line Decoder D3

D3 D2

Decoder
I1 Binary
D2
D1
D1
I0
D0 D0

I1 I0 D3 D2 D1 D0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
D3 I1 I 0 D2 I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 D1 I1 I 0 𝐷 0=¯𝐼 1 ¯𝐼 0
 Decoders
D7
• 3-to-8 Line Decoder D6
D5

Decoder
I2

Binary
D4
I1
D3
I0
D2
D1
D0
 3-to-8 Line Decoder

Particular
application:
Binary
↓
Octal
Conversion
 Decoders
• “Enable” Control (2-to-4-line Decoder)
D3

Y3
D2

Decoder
I1
Binary Y2
I0
Y1 D1
E
Y0
D0
E I1 I 0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
1 0 1 0 0 1 0 E

1 1 0 0 1 0 0 A decoder with enable input can

function as a demultiplexer — a
1 1 1 1 0 0 0 circuit that receives information from
a single line and directs it to one of
 Decoders
• Expansion - Design 3-to-8-line Decoder using two 2-to-4-line
decoders I I I 2 1 0

I2 I 1 I 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0
Y6

Binary
0 1 0 0 0 0 0 0 1 0 0 Y2
I1
0 1 1 0 0 0 0 1 0 0 0 Y1 Y5
1 0 0 0 0 0 1 0 0 0 0 E
Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3

Decoder
1 1 1 1 0 0 0 0 0 0 0 I0

Binary
Y2 Y3
I1
Y1 Y2
E
Y0 Y1
 Decoders

• Expansion - Design 4-to-16-line Decoder using two 3-to-8-line

decoders
 Decoders

• Active-High Active-Low
I1 I0 Y3 Y2 Y1 Y0 I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y3 Y3 Y1
Decoder

I1 I1 Decoder
Binary

Binary
Y2 Y2 Y0

Y1 Y1
I0 I0 I1
Y0 Y0 I0
 Decoders

• 2-to-4-line Decoder (Enable + Active Low)

 Implementation Using
Decoders
• All minterms are available as the output of decoder
• Any Boolean functions can be expressed as "Sum of
minterms"
Y7
Example: Full Adder Y6
S(x, y, z) = ∑(1, 2, 4, 7) Y5
x I2
C(x, y, z) = ∑(3, 5, 6, 7) Y4
y I1
z Y3
I0
Y2
Y1
Y0
Binary
Decoder

S C
 Implementation Using
Decoders
Example: Full Adder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
 Implementation Using
Decoders
Binary Binary
Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 x I2
Y4 Y4
y I1 y I1
z Y3 z Y3
I0 I0
Y2 Y2
Y1 Y1
Y0 Y0
Active high Active Low

S C
S C
 Encoders

• Performs inverse of a Decoder Only one

switch
• Put “Information” into code
should be
• A Binary Encoder has (or fewer) I/p lines and activated at
O/p lines a time
• Example: 4-to-2 Binary Encoder

x1
x3 x2 x1 y1 y0
y1 0 0 0 0 0
x2 Binary
0 0 1 0 1
Encoder
y0 0 1 0 1 0
x3 1 0 0 1 1
 Encoders

• Octal-to-Binary Encoder (8-to-3) I7

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
0 0 0 0 0 0 0 1 0 0 0

Encoder
I5 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1
I4 Y1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1 I3 Y0
0 0 0 1 0 0 0 0 1 0 0 I2
0 0 1 0 0 0 0 0 1 0 1 I1
0 1 0 0 0 0 0 0 1 1 0 I0
1 0 0 0 0 0 0 0 1 1 1 I7
I6 Y2
I5
Y2 I 7  I 6  I 5  I 4 I4
I3 Y1
Y1 I 7  I 6  I 3  I 2 I2
I1
Y0 I 7  I 5  I 3  I1 I0 Y0
 Priority Encoders

• 4-Input Priority Encoder

I3 V

Encoder
I3 I 2 I 1 I 0 Y1 Y0 V

Priority
I2 Y1
0 0 0 0 0 0 0
I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 I 3  I 2 Y1
1 1 1 1
I2 Y0 I 3  I 2 I1
I3
1 1 1 1
I0 V
1 1 1 1 V  I 3  I 2  I1  I 0
I0
Priority Encoders
 Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2
I4 Y4
Y1 I1
I3 Y3
Y0 I0
I2 Y2
I1 Y1
I0 Y0