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Vlsi Links

The document provides a collection of links related to digital design, VHDL, Verilog, SystemVerilog, verification, protocols, scripting, tools, FPGAs, FPGA constraints, coding guidelines, and timing analysis. It includes links to courses, documentation, tutorials, and other resources on topics such as digital logic design, HDL languages, verification using UVM and SystemVerilog, protocols like AXI and SPI, scripting languages like Perl and Python, EDA tools from companies like Intel and Xilinx, FPGA architecture, constraints, coding styles, and static timing analysis.

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217 views6 pages

Vlsi Links

The document provides a collection of links related to digital design, VHDL, Verilog, SystemVerilog, verification, protocols, scripting, tools, FPGAs, FPGA constraints, coding guidelines, and timing analysis. It includes links to courses, documentation, tutorials, and other resources on topics such as digital logic design, HDL languages, verification using UVM and SystemVerilog, protocols like AXI and SPI, scripting languages like Perl and Python, EDA tools from companies like Intel and Xilinx, FPGA architecture, constraints, coding styles, and static timing analysis.

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AdityaGupta
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DIGITAL DESIGN

https://www.youtube.com/watch?v=M0mx8S05v60&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm – Digital
Electonics by Neso Academy.
http://www.fullchipdesign.com/
https://www.youtube.com/watch?v=Y8FvvzcocT4&list=PL1221EE053D86FDA1 – Digital Design by NPTEL.
https://www.youtube.com/watch?v=nzxT84jTbGk&list=PLPIqCiMhcdO7bBmieyG5u41x2Ogcn67Bs – Digital
Design Course.
https://www.electronicshub.org/binary-adder-and-subtractor/ -- Electronics Hub.
https://www.electronicshub.org/priority-encoder/#Simple4-Input_Priority_Encoder
 
VHDL
http://home.deib.polimi.it/sami/VHDL_merged.pdf -- VHDL Merged 
https://www.scribd.com/document/278006745/VHDL-merged-pdf -- VHDL Merged
http://www.dejazzer.com/ee478/lecture_notes/lec08_packages.pdf  -- VHDL Package and Other Construts. 
https://www.youtube.com/watch?v=0Ho4rDswOeE&list=PL0pU5hg9yniZ2ka-XBXROXNR0pAEAEFCB --Intel
FPGA Official Youtube Link(Verilog,VHDL,Timing,Quartus Prime Software,Qsys Editor,Platform Deisgner etc). 
 https://www.hdlworks.com/hdl_corner/index.html --HDL Works Official Webiste
http://www.asic-world.com/  -- ASIC World Webisite
https://ece.gmu.edu/coursewebpages/ECE/ECE545/F15/
https://www.youtube.com/watch?v=zm-RA6BsYmc –VHDL by Intel.
https://www.ics.uci.edu/~jmoorkan/vhdlref/vhdl.html -- VHDL Mini Reference.
https://www.youtube.com/watch?v=5d2okyFNjkA&list=PLEdaowO6UzNENeQ2WHyGC6mlmggnnhMD6 –
VHDL Tutorial.
https://www.youtube.com/watch?v=BDq8-QDXmek&list=PLZv8x7uxq5XY-IQfQFb6mC6OXzz0h8ceF – FPGA
Design using VHDL Lectures.
https://www.csee.umbc.edu/portal/help/VHDL/attribute.html  -VHDL Attributes
 
VERILOG AND SV

https://www.fpga4student.com/2017/02/verilog-code-for-full-adder.html -- Full Adder


http://www.asic.co.in/Index_files/verilogexamples.htm#link12 -- Verilog Examples
https://www.cs.upc.edu/~jordicf/Teaching/secretsofhardware/VerilogIntroduction_Nyasulu.pdf  -- Verilog Quick
Reference
https://www.youtube.com/watch?v=0Ho4rDswOeE&list=PL0pU5hg9yniZ2ka-XBXROXNR0pAEAEFCB --Intel
FPGA Official Youtube Link(Verilog,VHDL,Timing,Quartus Prime Software,Qsys Editor,Platform Deisgner etc).
https://www.youtube.com/watch?v=FWE0-FOoE4s&list=PLUtfVcb-iqn-EkuBs3arreilxa2UKIChl – Verilog By
NPTEL.
https://www.youtube.com/watch?v=PJGvZSlsLKs – Verilog By Intel.
https://www.hdlworks.com/hdl_corner/index.html --HDL Works Official Webiste  
https://www.udemy.com/rtl-design-using-hdl/ -- Verilog by Udemy.
http://vol.verilog.com/VOL/main.htm
http://www.testbench.in/
http://verilogcodes.blogspot.com/ -- Verilog Tips and Tricks/File Reading.
http://www.asic-world.com/
https://www.rfwireless-world.com/source-code/VERILOG/D-flipflop-with-synchronous-reset.html
https://electrofriends.com/source-codes/digital-electroninc/verilog-hdl/verilog-hdl-program-for-johnson-counter/
https://www.chipverify.com/ -- ChipVerify Official Webiste
http://www.asicguru.com/
https://www.youtube.com/watch?v=PybxgAroozA&list=PLKIyiG4E8v42Ljc2UVI1yhr6KCudcqEUw – Verilog
Training Course.
http://www.fullchipdesign.com/
https://ece.gmu.edu/coursewebpages/ECE/ECE545/F15/
https://www.fpga4fun.com/
http://www.verificationguide.com/p/systemverilog-tutorial.html  -- Verification Guide
http://only-vlsi.blogspot.com/
https://www.youtube.com/watch?v=jvbnKrIQpwo&list=PLEdaowO6UzNEHgNZ-ApqLiiV3XZjuNzpE
http://cva.stanford.edu/people/davidbbs/classes/ee108a/winter0607%20labs/ee108a_nham_intro_to_verilog.pd
f -- Intro to Verilog.
https://inst.eecs.berkeley.edu/~cs150/sp12/resources/FSM.pdf – FSM by Berkeley EDU.
 
VERIFICATION(SV/UVM)

The best links for UVM:


https://www.youtube.com/watch?v=igYsB_sKeNc&list=PLEgCreVKPx5AP61Pu36QQE0Pkni2Vv-HD -- UVM
By Synopsys.
https://www.youtube.com/watch?v=imH4CFmVGWE&list=PLBIILfL2t1lnvzw7vF0arlvu36Wj4--D7 --Easier UVM
By John Aysnley  
https://www.verificationguide.com/p/uvm-tutorial.html – Verification Guide UVM.
http://www.verificationguide.com/p/systemverilog-tutorial.html
https://www.youtube.com/watch?v=fBApIYoyx7E&list=PLrvBkPreD9mqzU3IfTyQYICHjaZfH-F0h --  SV by
Cadence.
https://verificationacademy.com/courses/basic-uvm – Mentor Graphics Verification Academy UVM.
https://verificationacademy.com/cookbook/uvm – Mentor UVM Cook Book.
https://www.doulos.com/knowhow/sysverilog/uvm/ -- UVM doulos.
https://www.doulos.com/knowhow/sysverilog/tutorial/interface_classes/ --  SV Interfaces.
http://testbench.in/UT_00_INDEX.html – Test bench.in UVM.
https://www.verilab.com/files/configdb_dvcon2014_1.pdf -- UVM Configuration DataBase DVCON  
http://verificationexcellence.in/learn-to-build-systemverilog-based-ovm-and-uvm-testbenches/ -- Verification
Excellence SV and UVM.  
http://www.testbench.in/
https://www.youtube.com/watch?v=y_hEbgWWuQs&list=PLF4DeZAfqGSar69xWgw5TpFuszBd1FSJJ –
System Verilog for Verification.
http://www.asic-world.com/
https://www.chipverify.com/ 
http://testbench.in/TS_00_INDEX.html
https://colorlesscube.com/uvm-guide-for-beginners/ --UVM for Beginners.
https://www.chipverify.com/systemverilog/systemverilog-static-variables-functions -- Static Variables and
functions.
http://systemverilog123.blogspot.com/2015/09/static-and-automatic-lifetime-of.html -- Static and Automatic
Lifetime of Variable and Methods.
https://www.verilab.com/files/verification_prowess_with_uvm_harness_presentation.pdf -- Verillab UVM.
https://www.verilab.com/files/verilab_dvcon_tutorial_a.pdf --  Verilab UVM. 
https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files2/tlm1-txt.html -- 
UVM TLM Interfaces.
 
PROTOCOLS(AXI/SPI/I2C/UART/PCIe/AXI4/AXI STREAM
etc..)
 
https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi/all -- SPI Protocol 
https://www.youtube.com/watch?v=AuhFr88mjt0 – SPI Protocol
http://infocenter.arm.com/help/index.jsp --Arm Official Webiste
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html --Arm Official
Webiste
http://verificationexcellence.in/soc-bus-protocols/ -- Bus Protocols.
https://courses.cs.washington.edu/courses/cse466/12au/calendar/07-Communication-posted.pdf – Basics Of
Communication.
https://www.doulos.com/knowhow/verilog_designers_guide/models/universal_asynchronous_receiver_uar/
http://www.cpri.info/downloads/CPRI_v_7_0_2015-10-09.pdf -- CPRI
http://www.cpri.info/downloads/eCPRI_v_1_1_2018_01_10.pdf -- eCPRI
 
SCRIPTING(Perl/Shell/Python/Makefile/Bash/Awk,Tcl)

https://www.youtube.com/playlist?list=PLbMVogVj5nJRa3VKt_eyZdJ_DitCz1cvQ --Linux,tcl,perl,Makefile by
nptel. 
https://www.tldp.org/LDP/Bash-Beginners-Guide/Bash-Beginners-Guide.pdf -Bash Guide for Beginners.
https://gutl.jovenclub.cu/wp-content/uploads/2013/10/Linux.Shell_.Scripting.Cookbook.pdf -- Shell Scripting
cookboook.
https://www.youtube.com/user/madhurbhatia89/playlists  -- Perl/Shell/Python
https://www.youtube.com/playlist?list=PL1h5a0eaDD3rsGDFnVki_fFEtDWQfXjca --TCL Tutorial.  
https://wiki.tcl-lang.org/page/Tcl+Tutorial+Lesson+0 -TCL. 
https://www.gnu.org/software/make/manual/html_node/#toc-Overview-of-make --GNU Makefile.   
https://www.gnu.org/software/make/manual/html_node/Introduction.html#Introduction 
https://www.gnu.org/software/make/manual/html_node/Rule-Introduction.html#Rule-Introduction
https://www.gnu.org/software/make/manual/html_node/Phony-Targets.html#Phony-Targets 
https://www.gnu.org/software/make/manual/html_node/Conditional-Example.html
https://www.gnu.org/software/make/manual/html_node/Conditional-Example.html 
https://www.youtube.com/playlist?list=PLS1QulWo1RIYmaxcEqw5JhK3b-6rgdWO_  --Shell Scripting.
https://www.youtube.com/playlist?list=PL2qzCKTbjutJRM7K_hhNyvf8sfGCLklXw   --Shell Scripting.
https://www.youtube.com/playlist?list=PL8cE5Nxf6M6b8qW7CSMsdKbEsPdG9pWfu --Shell Scripting.
http://www.asic-world.com/
http://www.asicguru.com/
https://www.w3schools.com/python/default.asp  -- Python for Beginners.
https://www.tutorialspoint.com/python/ 
https://www.javatpoint.com/python-tutorial

Tools
https://www.edaplayground.com/
https://www.youtube.com/watch?
v=LrwgdUURuek&list=PLlbA7yRAKFTdGN5WkUuOHXH1YsL_ZazI5&index=2 – VIVADO TCL.
https://www.youtube.com/channel/UCfC7s2QnPFXVrozNQHG7a8Q/videos -- Quartus Prime Tool
Tutorial,Clock Fabric Youtube Channel.
https://www.youtube.com/watch?v=VZW5a1GLZKQ -- Questasim
https://www.youtube.com/watch?v=B73G4BuTpLo&list=PLK9U1Ze9-otwKY-5R87rNJqOnqW4aMt2v -- Quartus
Prime Timing Analyzer

FPGA

https://www.intel.com/content/www/us/en/programmable/documentation/jbr1444752564689.html#esc14458819
61208 --Intel Hyperflex Architecture.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_hp_hb.pdf  --
Intel Stratix 10 user guide
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_implement_fpga_design.htm --
XILINX FPGA’s
https://www.youtube.com/watch?v=bwoyQ_RnaiA – FPGA Design by Intel.
https://www.embedded.com/model-based-fpga-design-tool-quietly-gains-adherents/

FPGA Constraints
https://www.edn.com/fpga-constraints-for-the-modern-world-product-how-to/ -- FPGA constraints.
 
CODING GUIDELINES AND STYLES

https://hackaday.io/project/20751-memory-on-cyclone5-fpga/details  -- Memory Coding Style.   


https://inst.eecs.berkeley.edu/~cs150/sp12/resources/FSM.pdf  --FSM Code style.  
https://www.xilinx.com/support/documentation/white_papers/wp231.pdf – HDL coding Practises by XILINX.

TIMING ANALYSIS & STA 

http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-3-STA.pdf --Timing Analysis.  


http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf -- Sunburst Reset Strategy.
http://www.vlsi-expert.com/ --  VLSI Expert, STA.  
https://www.eetimes.com/understanding-clock-domain-crossing-issues/#  --CDC Explained.  
https://www.edn.com/basics-of-multi-cycle-false-paths/ -- Multicycle and false paths EDN.
https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/ -- Synchronization
Techniques.
https://www.youtube.com/watch?v=0Ho4rDswOeE&list=PL0pU5hg9yniZ2ka-XBXROXNR0pAEAEFCB --Intel
FPGA Official Youtube Link(Verilog,VHDL,Timing,Quartus Prime Software,Qsys Editor,Platform Deisgner
etc).  
http://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3b.html  -STA & Timing
http://www.vlsi-expert.com/2012/09/maximum-clock-frequency-static-timing.html  -STA & Timing
http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-timing.html  -STA & Timing
http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html  -STA & Timing
http://www.ee.bgu.ac.il/~digivlsi/slides/STA_9_1.pdf  --STA
http://www.ee.bgu.ac.il/~digivlsi/slides/synopsys_class_3_6_1.pdf --STA
https://www.ijitee.org/wp-content/uploads/papers/v8i7s/G10240587S19.pdf --STA International Journal.
https://classes.engineering.wustl.edu/ese461/Lecture/week7b.pdf -- Timing Analysis 
https://classes.engineering.wustl.edu/ese461/  --Design Automation for Integrated Circuit systems. 
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an584.pdf -- Timing Closure
Methodology for Advanced FPGA Designs  
https://vlsiuniverse.blogspot.com/search/label/How%20to%20avoid%20setup%20and%20hold%20time
%20violations   -STA & Timing
https://www.allaboutcircuits.com/technical-articles/why-how-pipelining-in-fpga/  --What is pipelining.

Other
 
http://www.sunburst-design.com/  --Sunburst Design Official Website. 
https://www.verilogpro.com/systemverilog-always_comb-always_ff/-- Verilog pro Website  
https://hdvacademy.blogspot.com/p/index.html?view=classic -- Hardware Design and Verification Academy.
https://www.embedded.com/model-based-fpga-design-tool-quietly-gains-adherents/ 
http://verificationexcellence.in/ -- Verification Excellence Official Website.
https://www.chipverify.com/  -- Chip Verify Official Website.
 
 
 Inferring a Latch

https://stackoverflow.com/questions/22459413/what-is-inferred-latch-and-how-it-is-created-when-it-is-missing-
else-statement-i 
https://stackoverflow.com/questions/20036401/if-statements-causing-latch-inference-in-verilog 
https://www.nandland.com/articles/how-to-avoid-transparent-latches-in-vhdl-and-verlog.html  
http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/inferring_storge_elements.pdf 
http://www.doe.carleton.ca/~shams/ELEC3500/Ver2Syn.pdf
https://www.edaboard.com/showthread.php?313149-inferring-latch(es)-for-signal-VHDL-error
https://www.allaboutcircuits.com/technical-articles/vhdl-incomplete-if-statements-and-latch-inference/
https://www.doulos.com/knowhow/fpga/latches/
https://www.allaboutcircuits.com/technical-articles/use-of-clock-gating-to-reduce-power-consumption/ -- Clock
Gating. 
https://www.cypress.com/documentation/component-datasheets/edge-detector  -- Edge Detector Circuit.
https://groups.google.com/forum/#!topic/embeddednewbies/c6bMIbDUnt8 --Sunburst Papers.
https://vdocuments.mx/search?q=Synthesizable+SystemVerilog%3A+Busting+the+Myth+that+...+%3F
%3FSNUG+Silicon+Valley+2013+3+Synthesizing+SystemVerilog+1.0+Introduction+
%E2%80%94+debunking+the+Verilog+vs.
+SystemVerilog+myth+There+is+a+common+misconception+that+...&u=1 -- Sunburst Papers.
 
Aynchronous FIFO's Explained

https://zipcpu.com/blog/2018/07/06/afifo.html 
https://zipcpu.com/blog/2017/10/20/cdc.html 
https://esrd2014.blogspot.com/p/first-in-first-out-buffer.html
http://electrosofts.com/verilog/fifo.html
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf -- Sunburst Asynchronous FIFO.
https://github.com/JonathanJing/Asynchronous-FIFO 
 
 NPTEL Useful Courses
 
https://nptel.ac.in/courses/117/105/117105080/
https://nptel.ac.in/courses/106/105/106105185/
https://nptel.ac.in/courses/106/105/106105165/
https://nptel.ac.in/courses/106/103/106103016/
https://nptel.ac.in/courses/106/103/106103116/
https://nptel.ac.in/courses/117/108/117108040/
https://nptel.ac.in/courses/117/106/117106092/
https://nptel.ac.in/courses/117/106/117106086/
https://nptel.ac.in/courses/108/106/108106137/ 
 
  
 5G
 
https://www.keysight.com/upload/cmc_upload/All/Understanding_the_5G_NR_Physical_Layer.pdf --
Understanding 5G Layers.
https://www.youtube.com/watch?v=RagHojSWEz8&list=PLfUa5X9whlE9Ul3j1PcZ5FUKFsVixjiXP&index=1 
--5G
 
 
  
Interviews & Job Prep
https://www.wisdomjobs.com/e-university/universal-verification-methodology-uvm-interview-questions.html
--UVM Interview Questions.  
http://www.asic.co.in/vlsi_presentations.htm
https://www.bestsampleresume.com/job-descriptions/engineer/fpga-design-engineer.html
http://only-vlsi.blogspot.com/2009/01/digital-design-interview-questions.html
https://www.wisdomjobs.com/e-university/verilog-interview-questions.html
 
 

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