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Digital Design by Verilog HDL Summer Internship

The document outlines a training program on Digital Design using Verilog HDL offered by Indeeksha Digital Pvt Ltd. It covers various topics including VLSI introduction, Verilog HDL basics, data types, operators, constructs, tasks and functions, reset and delays, code coverage, and FPGA hardware. Each topic includes practical labs to reinforce learning and application of the concepts discussed.

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anshpandey622
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19 views4 pages

Digital Design by Verilog HDL Summer Internship

The document outlines a training program on Digital Design using Verilog HDL offered by Indeeksha Digital Pvt Ltd. It covers various topics including VLSI introduction, Verilog HDL basics, data types, operators, constructs, tasks and functions, reset and delays, code coverage, and FPGA hardware. Each topic includes practical labs to reinforce learning and application of the concepts discussed.

Uploaded by

anshpandey622
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DIGITAL DESIGN BY VERILOG HDL

Advance DV Industrial Training : Phase-1

INDEEKSHA DIGITAL PVT LTD


Ahmedabad, Gujarat
Please find below course content which we will cover during this
program.

TOPIC 1 TOPIC 2
(Introduction) (Introduction to Verilog HDL)
- What is VLSI?
- Introduction to Semiconductor Industries
- Application Area and Abstraction layer

- VLSI Flow - Simple Verilog code

- ASIC, FPGA, SOC - Synthesizable construct and code

- EDA tools hands on - Synthesizable RTL code

Practical: A Simple code to understand EDA


Practical: Simple digital circuit
tools
implementation & Verification using Verilog

TOPIC 3 TOPIC 4
(Data Types) (Operator)
- Net - Logical, bitwise and Reduction Operator
- Registers - Shift operator
- Parameter - Relational Operator
- Array and memory - Concatenation & Replication operator
- Port Assignment - Conditional Operator

- Configurable RTLs - Developing a Design and verification Plan

Practical: LAB1 and LAB2 Practical: LAB3 and LAB4

www.indeeksha.com
TOPIC 5 TOPIC 6
(Construct) (Assignment)
- Branching Construct - Continues and Procedural Assignment
- Casex and casez - Initial and always blocks
- Looping Construct - Sensitivity list and Event
- Wait statements - Blocking and non-blocking assignment
- Race Condition between RTL and TB
Practical: LAB5, LAB6 and LAB7 Practical: LAB8, LAB9 and LAB10

TOPIC 7 TOPIC 8
(Task & Function) (System Task)
- Need of task/function - Display system tasks
- Writing reusable codes - Simulation time system task
- A code with low maintenance and less rework - Simulation control system task
- developing generic code - File operation
- task and function
Practical: LAB13 and LAB14
Practical: LAB11 and LAB12

TOPIC 9 TOPIC 10
(Reset and Delays) (Compiler Directive)
- Synchronous and asynchronous reset - Need and implementation of self-checking TB
- Regular delay - `timescale and `define
- Intra assignment delay - Conditional compiler directive
- Inertial delay - `include
- Example Practical: LAB17
Practical: LAB15 and LAB16

www.indeeksha.com
TOPIC 11 TOPIC 12
(Code Coverage)
- Code Coverage and its classification
- Code coverage report and closure Practical: Mini Project
- Coverage exclusion

Practical: LAB21

TOPIC 13 TOPIC 14
(FPGA Hardware) - Introduction to SV and UVM

- FPGA Synthesis Flow and Reports


- FPGA Hardware and mini project
continue…
- Pin Configuration
- Generating and dumping a bit file
- API to communicate external device with
hardware

Practical: Tool and hardware interface

www.indeeksha.com

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