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EDT IMP Questions

This document contains 50 questions related to embedded deterministic test (EDT) topics such as: - Reasons for using EDT and benefits it provides over normal scan testing - Components of an EDT architecture like decompressors, compactors, and their functions - Factors that impact compression ratio and techniques for estimating it - Types of design rule checks faced during EDT insertion - Differences between ASIC and FPGA implementations and tools used for EDT insertion

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Mayur Mestry
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760 views1 page

EDT IMP Questions

This document contains 50 questions related to embedded deterministic test (EDT) topics such as: - Reasons for using EDT and benefits it provides over normal scan testing - Components of an EDT architecture like decompressors, compactors, and their functions - Factors that impact compression ratio and techniques for estimating it - Types of design rule checks faced during EDT insertion - Differences between ASIC and FPGA implementations and tools used for EDT insertion

Uploaded by

Mayur Mestry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EDT IMP Questions

Created by: Er. Manjeet Singh

1. Why we don’t go for high compression like 90- 34. Draw & explain EDT wave form.
100%. 35. Difference between ASIC & FPGA.
2. Draw & explain decompressor block. 36. Tools used for EDT insertion in Mentor &
3. Draw & explain compactor block. Synopsis.
4. How will you decide compression ratio. 37. Commonly used Compression Technique.
5. Explain SDC file. 38. Find C.R.
6. What is bypass mode in EDT.
7. What is EDT, why we use it.
8. Drc’s faced during EDT insertion.
9. What is EDT clock state during capture.
10. What is EDT update state during load_unload
11. Estimate the compression ratio for following
specification.
1. The design consist of 10k FF ,10 input ,10
Output
2. How many FF needed to keep in each chain 39. Find C.R.
to achieve a)20% b)100% c)50%
12. Take one example & explain how edt reduces
TAT.
13. What is meant by masking or X blocking, explain
types of masking.
14. Explain fault aliasing.
15. Explain fault collapsing.
16. How to share EDT clock & scan clock.
17. Explain pipeline stage used in compactor.
18. What are lockup cells. 40. EDT works on edt clock & scan works on scan
19. What are the advantages of EDT. clock,draw a diagram showing both clock.
20. What is the reason for increase in pattern count 41. Why only x-or gate used in compactor & phase
for compressed mode. shifter.
21. The actual compression achieved will be less 42. I have 330 internal core chains to each
than the specified compression why ? edt_channel & there are 7 edt channels.while
22. Explain k-17,k-18,k-19 violation. performing simulation the log file reporting that a
23. How are x’s handled in EDT , what is their flop is producing x instead of 1 in edt channel 2.
effect. How to fix this.
24. How do you control the ‘AND ‘ logic which is 43. Is it possible to reconvert the scan FF to normal
used to prevent ‘x’ from propagating to x-or FF .
logic. 44. Which reset is preferred active low or active
25. Is decompressor a combinational or sequential high.
block. 45. What is the off state for active low reset.
26. Write & explain test procedure file used in EDT. 46. What is the off state for active high reset.
27. What are the input & output files of EDT 47. What is scan sysnthesis.
insertion. 48. What is scan configuration.
28. Does coverage increase or decrease with increase 49. Whether RTL drc’s & DFT drc’s are same.
in compression. 50. What is spyglass.
29. How the compression technique factor affect the
number of scan chain? Is number of clock
domain also a factor.
30. What do you mean by TDV.
31. How many cycles required for loading of 3
patterns through 100 FF in normal mode &
pipeline mode.
32. ATE costs depend on.
33. Explain F9,F10 violation.

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