VLSI-Standard Titles

S.No Project Code Project Name

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
1 TVPGTO26 Pull Up Network
(Tools / Tanner EDA)

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
2 TVPGTO50 Pull Up Network
(Tools / Cadence EDA)

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
3 TVMATO642 Pull Up Network
(Tools / Cadence EDA)

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
4 TVMATO643 Pull Up Network
(Tools / Tanner EDA)

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
5 TVREBE19_25 Pull Up Network
(Back End Domains / Low Power VLSI)

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled
6 TVREBE19_26 Pull Up Network
(Back End Domains / Transistor Logic)

Seda - Single Exact Dual Approximate Adders for Approximate Processors

7 TVPGTO51
(Tools / Tanner EDA)

Seda - Single Exact Dual Approximate Adders for Approximate Processors

8 TVPGTO503
(Tools / Cadence EDA)

Seda - Single Exact Dual Approximate Adders for Approximate Processors

9 TVMATO602
(Tools / Cadence EDA)

Seda - Single Exact Dual Approximate Adders for Approximate Processors

10 TVMATO603
(Tools / Tanner EDA)

Seda - Single Exact Dual Approximate Adders for Approximate Processors

11 TVMABE26
(Back End Domains / Transistor Logic)

Seda - Single Exact Dual Approximate Adders for Approximate Processors

12 TVPGBE47
(Back End Domains / Transistor Logic)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

13 TVPGTO52
(Tools / Tanner EDA)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

14 TVPGTO498
(Tools / Cadence EDA)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

15 TVMATO582
(Tools / Cadence EDA)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

16 TVMATO583
(Tools / Tanner EDA)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

17 TVMABE40
(Back End Domains / Cadence EDA)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

18 TVMABE41
(Back End Domains / Transistor Logic)
VLSI-Standard Titles

S.No Project Code Project Name

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

19 TVPGBE39
(Back End Domains / Cadence EDA)

Design of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder

20 TVPGBE40
(Back End Domains / Transistor Logic)

Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
21 TVPGTO53
(Tools / Tanner EDA)

Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
22 TVMATO519
(Tools / Cadence EDA)

Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
23 TVMATO520
(Tools / Tanner EDA)

Low Leakage Clock Tree with Dual-Threshold- Voltage Split Input–Output Repeaters
24 TVREBE19_15
(Back End Domains / Transistor Logic)

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in

25 TVPGTO54 FPGA
(Tools / Tanner EDA)

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in

26 TVPGTO237 FPGA
(Tools / Cadence EDA)

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in

27 TVMATO219 FPGA
(Tools / Cadence EDA)

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in

28 TVMATO220 FPGA
(Tools / Tanner EDA)

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in

29 TVPGBE87 FPGA
(Back End Domains / Transistor Logic)

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in

30 TVMABE87 FPGA
(Back End Domains / Transistor Logic)

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
31 TVPGTO55
(Tools / Tanner EDA)

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
32 TVPGTO221
(Tools / Cadence EDA)

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
33 TVMATO203
(Tools / Cadence EDA)

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
34 TVMATO204
(Tools / Tanner EDA)

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
35 TVPGBE92
(Back End Domains / Transistor Logic)
VLSI-Standard Titles

S.No Project Code Project Name

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation
36 TVMABE91
(Back End Domains / Transistor Logic)

A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
37 TVPGTO56
(Tools / Tanner EDA)

A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
38 TVPGTO343
(Tools / Cadence EDA)

A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
39 TVMATO408
(Tools / Cadence EDA)

A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
40 TVMATO409
(Tools / Tanner EDA)

A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
41 TVPGBE82
(Back End Domains / Transistor Logic)

A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
42 TVMABE81
(Back End Domains / Transistor Logic)

A 2.4-Ghz Differential Low-Noise Amplifiers using 0.18um CMOS Technology

43 TVPGTO57
(Tools / Tanner EDA)

A 2.4-Ghz Differential Low-Noise Amplifiers using 0.18um CMOS Technology

44 TVPGBE86
(Back End Domains / Transistor Logic)

A 2.4-Ghz Differential Low-Noise Amplifiers using 0.18um CMOS Technology

45 TVMABE86
(Back End Domains / Transistor Logic)

A 2.4-Ghz Differential Low-Noise Amplifiers using 0.18um CMOS Technology

46 TVPGTO239
(Tools / Cadence EDA)

A 2.4-Ghz Differential Low-Noise Amplifiers using 0.18um CMOS Technology

47 TVMATO221
(Tools / Cadence EDA)

A 2.4-Ghz Differential Low-Noise Amplifiers using 0.18um CMOS Technology

48 TVMATO222
(Tools / Tanner EDA)

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
49 TVPGTO58
(Tools / Tanner EDA)

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
50 TVPGTO235
(Tools / Cadence EDA)

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
51 TVMATO217
(Tools / Cadence EDA)

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
52 TVMATO218
(Tools / Tanner EDA)

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
53 TVMABE88
(Back End Domains / Transistor Logic)

A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply
54 TVPGBE88
(Back End Domains / Transistor Logic)

55 TVPGTO27 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
VLSI-Standard Titles

S.No Project Code Project Name

in 130-nm CMOS
(Tools / Tanner EDA)

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
56 TVPGTO156 in 130-nm CMOS
(Tools / Cadence EDA)

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
57 TVMATO122 in 130-nm CMOS
(Tools / Cadence EDA)

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
58 TVMATO123 in 130-nm CMOS
(Tools / Tanner EDA)

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
59 TVPGBE95 in 130-nm CMOS
(Back End Domains / Low Power VLSI)

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits
60 TVMABE95 in 130-nm CMOS
(Back End Domains / Low Power VLSI)

Dual use of Power Lines for Design-for-Testability—A CMOS Receiver Design

61 TVPGTO59
(Tools / Tanner EDA)

Dual use of Power Lines for Design-for-Testability—A CMOS Receiver Design

62 TVPGTO328
(Tools / Cadence EDA)

Dual use of Power Lines for Design-for-Testability—A CMOS Receiver Design

63 TVMATO384
(Tools / Cadence EDA)

Dual use of Power Lines for Design-for-Testability—A CMOS Receiver Design

64 TVMATO385
(Tools / Tanner EDA)

Dual use of Power Lines for Design-for-Testability—A CMOS Receiver Design

65 TVMABE83
(Back End Domains / Transistor Logic)

Dual use of Power Lines for Design-for-Testability—A CMOS Receiver Design

66 TVPGBE83
(Back End Domains / Transistor Logic)

Evolutionary Approach to Approximate Digital Circuits Design

67 TVPGTO60
(Tools / Tanner EDA)

Evolutionary Approach to Approximate Digital Circuits Design

68 TVPGTO184
(Tools / Cadence EDA)

Evolutionary Approach to Approximate Digital Circuits Design

69 TVMATO158
(Tools / Cadence EDA)

Evolutionary Approach to Approximate Digital Circuits Design

70 TVMATO159
(Tools / Tanner EDA)

Evolutionary Approach to Approximate Digital Circuits Design

71 TVPGBE93
(Back End Domains / Transistor Logic)

72 TVMABE93 Evolutionary Approach to Approximate Digital Circuits Design

VLSI-Standard Titles

S.No Project Code Project Name

(Back End Domains / Transistor Logic)