INTEGRATED CIRCUITS

AN182
Clock regenerator with crystal-controlled
phase-locked loop VCO (NE564)

1991 Dec

 
   
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

INTRODUCTION “second-order” system. An RC series filter combination will cause a

In order to obtain a local clock signal in Multiplexed Data lead-lag condition that will permit dynamic selectivity, along with
Transmission systems, a phase and frequency coherent method of closed-loop stability.
signal extraction is required. A Master-Slave system using the
quartz crystal as the primary frequency determining element in a LOOP GAIN FUNCTIONS
phase-lock loop VCO is used to reproduce a phase coherent clock The phase detector conversion gain (Kd) and the VCO conversion
from an asynchronous Data Stream. gain (KO) determine, in large part, the lock range, capture range and
The NE564, a versatile phase-locked loop (PLL) operating at linearity characteristics of the NE564. These device parameters are
frequencies of 50MHz, has inputs and outputs designed to be TTL both dependent upon bias current and operating frequency. Some
compatible. The Philips Semiconductors NE564 is used to generate typical curves for each of the parameters are shown for the NE564
the phase-locked, crystal-stabilized clock reference signal. in Figures 2 and 3.

Its particular adaptation, for use with a crystal-controlled VCO CLOCK REGENERATOR CIRCUIT
instead of the usual RC control elements, requires a brief review of The basic building blocks of the clock regenerator circuit are shown
the principles of the Phase-Lock Loop design. in Figure 4. The PLL is shown as a frequency multiplier
incorporating a divide by “N” in the VCO phase detector feedback
The NE564 Phase-Locked Loop is a fully contained system,
loop. The functions of the ringing circuit and the NE527 high-speed
including limiter, phase detector, VCO, DC amplifiers, DC retriever
comparator will be discussed later.
and output comparator (reference Figure 1). For the clock
regeneration system to be discussed, the portions of the NE554 The waveforms of Figure 5 indicate the waveforms transmitted over
implemented are the input limiter, phase detector and VCO. a T1 line. The bipolar signal transmitted has “no” DC components
induced in the transmission line (reference should be made to the
The signal limiter amplifies low level inputs (until saturation is
effect of normal mode and common effects on signal information).
reached, which is typically 60mVP-P for the NE564). The signal
When transmitted over telephone wire pairs, the resultant signal (at
limiter output is fed to the phase detector, where the “unknown” input
the receive end) will have been degraded in both waveshape and
is compared to the “known” VCO frequency of the NE564. The
signal-to-noise ratios. Typical attenuation factors for a T1 line are
differential error signal that is generated is fed through a DC
-30dB per 6000 feet. In addition, pair-to-pair crosstalk can degrade
amplifier and a voltage-to-current converter. The change in the
signal-to-noise ratios. The energy transmitted in the bipolar system
current generated forces the VCO frequency to vary in its frequency
of signal transfer is centered at 772kHz (generated by the bit
and/or phase relationship, such that a θ of 90o lagging is obtained format).
(the actual phase relationship may be somewhat less than 90o
depending upon the KdKO (gain) product of the NE564 at the At the receiving end the bipolar signal information is converted to a
operating frequency and bias current). The external filtering unipolar pulse train after being amplified, filtered and fed through an
incorporated at Pins 4 and 5 control the dynamic frequency automatic level control circuit. Some types of PCM systems use the
response and loop stability criteria. rectified and filtered DC (average) to control the phase of the
regenerator clock; however, in newer systems, bipolar signals are
The NE564 is a first order system; therefore, the use of single processed (or preconditioned) by terminal common equipment
capacitors (at Pins 4 and 5) will automatically create a resulting in unipolar information.

LOW PASS
FILTER ANALOG
+VCC OUTPUT

1 4 5 14

2 LOOP GAIN
FM/RF LIMITER PULSE CONTROL
INPUT COMPARATOR
6

DC
7 FROM
BIAS VCO 3 RETRIEVER

ECL AMPLIFIER SCHMITT

OUT FSK
11 TRIGGER OUT
16

9
TTL
OUT POST DETECTION
VCO PROCESSOR

+VCC HYSTERESIS
10 SET
12 13 8

TIMING
CAPACITOR
SL01057
Figure 1.

1991 Dec 2
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

VD - PHASE COMPARATOR’S
OUTPUT VOLTAGE IN mV

800

fO = 1.0MHz
600

400

200

40 60 80 100 120 140 160

∴ PHASE
ERROR IN
DEGREES
–200

–400

–600

–800

SL01058
Figure 2. Variation of the Phase Comparator’s Output Voltage vs Phase Error and Bias Current

1991 Dec 3
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

VCO FREQUENCY
IN MHz

µ
IBIAS = 800 A
1.6

µ
IBIAS = 0 A

1.4

fO = 1.0MHz

1.2

–400 –200 200 400 600 800

VD IN mV

.8

.6

SL01059

Figure 3. VCO Output Frequency as a Function of Input Voltage and Bias Current
T1 Data Transmission At each receiving station the bipolar signal is amplified, filtered and
The bipolar signal, as transmitted on a T1 line, appears below with fed through an automatic level control circuit. A full wave rectified
the original binary, converted unipolar and clock waveform signal is then sent to the clock regeneration circuit. This is
(reference Figure 5). essentially the format followed by some of the original T1 repeater
equipment. The clock regeneration circuit described here could be
The bipolar signal, when transmitted over standard wire pairs, will be adapted to this system.
degraded both in wave shape and signal-to-noise by the time it
reaches the signal repeater. This is due to the attenuation factor of
the cable which is nearly -30dB for 6000 ft. In addition, pair-to-pair
THE T1 SPECTRUM
crosstalk degrades signal-to-noise. The energy in the transmitted
The bipolar signal is similar to NRZ data in that it does not contain
bipolar signal is centered at 772kHz due to the particular bit format.
carrier information. In order to give the PLL coherent frequency
Bipolar signals have no DC offset.

NE564 VCO
NE527

RINGING DET
NE527
CRT
DATA

XTAL
VREF
+4

REGENERATED
CLOCK SL01060
Figure 4.
information sufficient to obtain “capture” and lock, carrier class “C” transistor tank circuit (reference Figure 4) which is sharply
components must be obtained from the data stream. The time tuned to the basic clock frequency (1.544MHz). Each positive half
duration of the frequency information fed to the PLL is also important cycle of data then starts a wave train of coherent information which
in order to obtain accurate and stable information to update the PLL. is phase synchronous with each succeeding positive data bit. When
In order to begin the extraction of frequency information, the the LC tank is optimally tuned, relatively extended periods without
positive-going portions of the bipolar data signals are used to drive a data bits can be tolerated with minimal loss of frequency and phase

1991 Dec 4
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

information. The combination of good short-term frequency stability ineffective since it is an even subharmonic of fO. The PLL will not
of the high “Q” LC tank, coupled with the long-term stability of the normally lock to even harmonics, in fact, an error signal is produced
crystal-controlled VCO, is the foundation of the NE564 clock which tends to force the VCO out of lock. This fact further stresses
regeneration system accuracy. the need for preprocessing in the frequency domain. The class “C”
pulsed resonant tank significantly multiplies the magnitude of the fO
It must be emphasized that dda pulse synchronization of the
spectral component and filters out unwanted subharmonics.
preprocessing circuit must be frequency coherent with the
fundamental period of the time base to be extracted. That is, if the The loop error voltage available from the phase detector for phase
time period of the clock is 1/fC = T, where fC is the clock frequency, correction of the VCO is directly related to the product of the
then the spacing between any positive code bit sequence must be n incoming coherent spectral energy multiplied in the balanced mixer
x t (reference Figure 6). with the reference signal derived from the VCO. Since the phase
error information is integrated in the loop filters, the instantaneous
BINARY CODE 1 0 1 0 0 0 1 1
magnitude of the DC error voltage is proportional to the time integral
of coherent mixer products. Thus, as the magnitude and time
324ns
50% DUTY duration of the desired frequency component is in creased in the
CYCLE
BIPOLAR SIGNAL preprocessing circuitry, the VCO phase accuracy is greatly
improved. Capture time is obviously enhanced also.
648ns
The signal from the tuned tank is buffered by a FET follower
UNIPOLAR N-channel enhancement mode device (reference Figure 12). This
provides power gain with virtually no loading on the tank circuit and
avoids degrading the “Q”. The buffered signal is then fed to a
CLOCK 1.544MHz high-speed comparator (Philips Semiconductors’ NE527) which

ËËËËËË
SL01061
allows for waveform symmetry adjustment in addition to providing a

ËËËËËË
standard TTL output to drive the NE564 PLL.
Figure 5.

ËËËËËËËËËËËË
(FR)
NOTE:

ËËËËËËËËËËËËËË
A– Ab = 96.5kHz spacing

ËËËËËËËËËËËËËË
T

ËËËËËËËËËËËËËË
t

ËËËËËËËËËËËËËË
0 b T
323.8ns
SL01062
Figure 6.
1/T 3.068MHz 6.176MHz
Looking at the spectral analysis of the relative energy available to SL01063
the clock extraction circuitry (with a worst-case duty cycle of 1 of 16) Figure 7.
will demonstrate the need for enhancing the particular desired
frequency component before applying the signal to the Phase-Lock In the particular circuit shown in Figure 12, the 1.544MHz
Loop. For fO = 1.544MHz, the period is T = 647.67ns. The pulse or information is applied to the phase detector input of the NE564
bit width is 323.8ns. Phase-Lock Loop. The VCO, however, is operated at four (4) times
this frequency in order to take advantage of economical and readily
Here the bit duration 323.8ns = b. The Fourier expansion of the available crystals. The VCO signal is fed through a divide-by-four
discrete spectrum is related by the following equation: counter (74LS73) to provide the Phase Detector reference and final
(Ab)| sin(rt ) I Flnl T I n~iib In 0,1,2 (1) regenerated clock signal. To avoid loading, the clock signal
(1.544MHz) is buffered by the 75451 peripheral driver which
The basic frequency component resulting from various bit spacing provides a high-speed open collector TTL output.. The input signal
factors is defined by the equation is AC coupled in order to reduce DC bias errors in the Phase
f = 1/T Detector caused by “O” level variations.

If we consider the special case of a single pulse present out of 16 The Crystal
bipolar or 32NRZ periods, then The crystal used was chosen to match the NE564 VCO drive
T = 16 bipolar bit times characteristics. It is an “AT” cut oscillator crystal which operates
near the anti-resonate or “parallel” mode in this circuit. The crystal
= 16 x 647.67ns = 10.36ms may have to be fine-tuned, as indicated in Figure 8. The pulling
characteristic of the crystal is adequate to allow for 0 to 70oC
f = 96.5kHz
operational drift plus initial and aging accuracy tolerance factors and
Accordingly, the spectral lines will be spaced in multiples of 96.5kHz. still retain lock between master and slave station VCXOs. The
The spectrum for this particular worst case condition is shown in average lock range at room temperature with one of sixteen data
Figure 7 below. bits present is typically 1000Hz for a 6.176MHz crystal with a
capture range greater than 500Hz.
It is evident that as the bit spacing increases to the point where fO is
the 16th harmonic of the fundamental, very little fO energy is For VCO operation at 6.176MHz, CS is 22pF, CC is 18pF, and Ct, a 1
available to drive a phase-lock regeneration circuit. F(16) is also - 8pF trimmer capacitor (reference Figure 8).

1991 Dec 5
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

NE564 CRYSTAL-CONTROLLED VCO taken to roll-off the circuit gain. This is the purpose of CS in Figure
As shown in Figure 6, the crystal is operated with a series 8. Since the gain or the VCO is a factor in spurious oscillation, the
capacitor. When properly trimmed, this allows the crystal to operate current injected into Pin 2 will also have an effect in this respect.
near the series resonant mode. A crystal manufactured to operate (KO increases with I2). At higher operating frequencies this
in the series resonant mode will do so only if it sees a pure parameter may become more critical in attaining stable start ups in
resistance looking into the oscillator terminals. The circuit below the desired frequency mode. Obviously the size of CS must be
shows an oscillator which looks inductive with the equivalent crystal smaller than the value needed to cause free running near the
circuit and trimmer capacitor Ct (reference Figure 9). desired frequency without the crystal connected.

12
XTAL CRYSTAL SPECIFICATION
CC Crystals may be manufactured to operate in either the series mode
NE564 CS
with no external capacitance (purely resistive load) or in the parallel
mode with a specified value of load capacitance. The 564 tends to
13
operate at a frequency above the specified value when a series
CT SL01064 mode crystal is used, for a design frequency of 6.176000MHz and
Figure 8. zero load capacitance. Referring to Figure 8, for CS = 10pF and
CT = 10pF the average center frequency for an NE564 sample
measured in the lab was 6181.192kHz. For the same CS, but with
CT equal to 60pF, fO measured 6176.565kHz. A second crystal
LOSC showed a spread of 6176.600kHz to 6160.855kHz. The effect of the
C1
VCO was to pull the crystal to a frequency above its design value.
R1 CO CS This effect is then nearly tuned out by the external capacitances CS
XTAL
and CT. If CT is sufficiently increased, the crystal will see a purely
VCO
resistive load and operate at its rated frequency.
L1 A second approach is to specify a crystal which is to operate near
the anti-resonate or parallel mode. Normally this is done with a
certain value of external load capacitance specified by the customer
NOTES: which matches the existing circuit parameters. The maximum
CO = XTAL Shunt capacitors difference between series and parallel resonance for any crystal is
C1 = Equivalent series resonant arm capacitance
L1 = Equivalent Motional Inductance
0.5% of fO (series resonant mode); for fR = 6.126MHz, 0.5% of fR =
R1 = Equivalent crystal series resistance 30kHz. The usual value would be lower than this.
C5 = External shunt or stray capacitance
SL01065
Figure 9. rO = electromechanical coupling factor, fa = parallel resonant
frequency). The particular cut of the crystal material determines the
drift response over temperature. For oscillator applications, the AT
C1 cut offers the best over-all stability over a wide frequency and
temperature range. Final design uses second approach.
R1 CO
For a stability or total tolerance of +15ppm over the rated operating
range of -20oC to +70oC, a certain manufacturer’s crystal actually
performed as shown above (Refer to Figure 11).
L1
Calibration accuracy is the allowable frequency tolerance at the
NOTES: reference temperature, i.e., +10ppm @ 25oC.
C1 = Motional capacitance
C0 = Shunt capacitance Third, is a long-term drift spec which determines the customer’s
R1 = Equivalent Resistance maximum allowable drift due to aging effects. An acceptable value
L1 = Equivalent Inductance SL01066 in quality crystals is +2ppm/year.
Figure 10. Basic Crystal Equivalent Circuit Using our reference crystal of 6.176MHz and the above
specifications, the crystal limits over a 1 year period would be:
+20Hz Temperature stability: ±15ppm x 6.176 = ±93Hz
–20Hz Calibration tolerance: ±10ppm x 6.176 = ±62Hz
-20oC 0o +20oC +70oC
SL01067 @25oC Long term drift: ±2ppm x 1 x 6.176 = ±12Hz
Figure 11. Design Example Total: (+ 1 67Hz)
If LO is small and the internal gain of the device high over a wide The above figure of ±167Hz then determines the capture and lock
frequency range, LO may resonate with the CO of the crystal at a range over which two crystal stabilized VCOs must track under
very high frequency. Under certain conditions the circuit may even worst case conditions when the exact same crystal specifications
tend to operate in the 3rd overtone mode unless measures are are used for master and slave units within an operational system.

1991 Dec 6
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

Crystal Specifications a center data rate of 1.544000Mb/s. Monitor the buffered output of
the ringing circuit with a scope connected to the source of the
‘AT’ Cut Oscillator Type SD213 (Figure 15). The waveform should appear as in Figure 17.
Fundamental mode operation HC-33 Case (Standard) (6) Adjust tank trimmer cap CT for a maximum amplitude and note
that the cycle period should be 647ns. (7) Now monitor the
Calibration tolerance: ±15ppm @ 25oC
comparator output signal at Pin 7 and adjust Rt for a 50% duty
Temperature stability: ±15ppm; -15oC to +65oC cycle. The same signal will appear at Pin 5 of the NE527 except it
will be inverted. The signal on Pin 7 of the NE527 and Pin 6 of the
Circuit operating condition: Parallel resonance
NE564 should appear as shown in Figure 19. Now attach one lead
Frequency specified: 6.176000MHz of a dual-trace scope to Pin 7 of the NE527 and the other to Pin 3 of
the NE564 as shown (Figure 16).
Part designation: Croven #A330 DEF-32 or equivalent
The two signals should be in phase-locked with an approximate 90o
Setup Procedure differential as shown in Figure 20 (data signal applied to @
Referring to Figure 12 the following setup procedure will aid the 1.544Mb/s). If lock does not occur a slight trimming of the crystal
user in establishing proper circuit operation. trimmer CT should connect for slight differences in master-to-slave
crystal tolerance. It is recommended that master and slave crystals
Regulated supply voltage of +5V and -6V are required. Current
be of the exact same design and specification to insure optimal
drain on the +5V line is @100mA, and 6mA for the -6V.
tracking over time and temperature. A recommended manufacturer
With proper voltage applied, (1) First check the supply currents to be and part number appears at the end of this application note for your
sure they are in the range indicated above. (2) Check the operation convenience.
of the NE564 VCXO by looking at Pln 9 with an oscilloscope (see
Once lock is attained, move one lead of the dual-trace scope to the
Figure 13). A reasonably symmetric square wave should be
buffered output of the 75451 Pin 3 leaving the other scope probe on
present having a frequency near 6.1MHz. (3) Attach a DVM across
Pin 6 of the NE564. The phase-locked waveform should appear as
the 2k resistor which feeds Pin 2 of the NE564 and adjust for a
In Figure 25. If a data word generator Is being used, you may
reading of 2.00V, indicating a 1mADC current flowing into Pin 2 (The
check overall operation for various bit patterns by synchronizing the
(+) lead of the DVM should be connected to the end of t he 2k
scope trigger on the “end of word” pulse then observe the phase
resistor which ties to the wiper of the 10k pot and the (-) lead to Pin
error effect as different combinations are fed in.
2 of the 564; reference Figure 14). (4) The exact center frequency
is set by adjusting Ct, the crystal trimmer cap, for exactly
6.176000MHz with no signal input (this sets the center frequency of
the VCXO to free-run in the center of the capture range). (5) Enable PHASE JITTER
strobe ‘A’ and ‘B’ with a +2.7V min. to +5V max. level. Apply a When operating with real-time data transmission, the PLL loop filters
standard 1.544Mb/s NRZ data signal to the input terminal terminated must be optimized to minimize regenerated clock jitter. A good
in 50W. The amplitude should be +3 to +5V (0 to peak). Set the grade of mylar capacitor is recommended as connected to Pins 4
duty cycle for 1 bit in a 16-bit period. Note the data generator must and 5 of the NE564. A simple pair of shunt-connected loop filter
be driven from a crystal-controlled master oscillator also adjusted for caps of 0.33mF to 0.76mF was found to be adequate.

1991 Dec 7
1991 Dec
Philips Semiconductors

+5V

5 Ω I B ADJ
1k

SYMMETRY 13 10k .1
ADJ. 470 Ω µF
L1 430pF MICA
2k 470 Ω 470 Ω
10–60pF .1 µF
C1 C2 .1 µF
1k
f O = 1.544MHz 1 10 2

Figure 12.
5k 6

8
D 11
G NE527 7
phase-locked loop VCO (NE564)

4 COMPARATOR 200 Ω
SB
SO213 S
510k 3 7
3V 5 VCO
OUT
3 9 6.176MHz
6

8
Clock regenerator with crystal-controlled

CIN

2N2366 12
9 4 5 8 13
100pF 1k 1k .1
CS µF
.1 µF
CC
1k 100 Ω 6 8 10

.1 µF
BUFFER 5 Ω
AMP +5V
.1 µF +5V
1k
.1 µF 3
2

Data Transmission System Clock Regenerator

CLASS
‘C’ 1.544MHz
DRIVER BUFFERED
OUTPUT
74HCT73 1

75451

5 12 4
AN182

SL01068
Application note
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

100mV 500ns

11
VCO DATA ( 4 IN 16)
NE564
COUNTER
9 SCOPE

Q2 SIGNAL
NOTE:
Check VCO free–running frequency and output waveshape. SL01069

Figure 13. Check VCO Free-Running Frequency 2V

and Output Waveshape
SL01074

+VCC Figure 18. Ringing Circuit Response (4 Data Pulse in 16)

100mV 500ns
NE564 2k DVM
DATA INPUT
2 1.544Mb/s
IB

SL01070
Figure 14. COMPARATOR OUTPUT
IC1

D 2V
SL01075
G
SB
Figure 19. Ringing Circuit to Square Wave Conversion
S
SD213 SCOPE
100mV 200ns
NE564 INPUT
SL01071 PIN 6

Figure 15.

NE564
NE527 7 6 3 NE564 PIN 3

7473
2V
SL01076
CH1 CH2
Figure 20. Phase Comparator Signals (in Lock)

SL01072

Figure 16. 1V 200ns

1 DATA BIT
100mV 500ns
IN 16

DATA PULSE
1 IN 16
CLOCK OUT
1.544MHz

Q2 SIGNAL 2V

SL01077
Figure 21. Regenerated Clock Signals
2V
SL01073

Figure 17. Ringing Circuit Response (1 Data Pulse in 16)

1991 Dec 9
Philips Semiconductors Application note

Clock regenerator with crystal-controlled

AN182
phase-locked loop VCO (NE564)

1V 200ns 1V 200ns

MULTIPLE DATA 1’s CLOCK OUT

1.544MHz

CLOCK OUT VCO OUT

1.544MHz 6.176MHz

2V
2V
SL01078 SL01080

Figure 22. Regenerated Clock Signals Figure 24. Regenerated Clock Signal
Relative to NE564 VCO Signal

1V 200ns
1V 200ns

DATA IN DATA IN
(RANDOM) (RANDOM)

VCO OUT
(BUFFERED
6.176MHz) CLOCK OUT
(BUFFERED)
2V
SL01079 2V
SL01081
Figure 23. Regenerated Clock Signals
Relative to NE564 VCO Signal Figure 25. Regenerated Clock Signal
Relative to Random NRZ Data Signal
NOTES:
1. Recent versions of this circuit no longer require series capacitors CC and CT. See Figure 12.
2. Input levels to the NE564 have been reduced for this application to ≅ 800mVP-P. See Figure 12.
3. Improved operation regarding clock jitter is obtained by carefully decoupling the divider counter ICs and the PLLs VCC line. This is accom-
plished by adding a small series “R” into the VCC line with the bypass capacitor to ground.

References
1. “Fourier Analysis” by Hwei P. Hsu. Simon & Shuster Tech Outlines
2. “Pulse and Digital Circuits” by Millman and Taub. McGraw Hill
3. “Phaselock Techniques” by Floyd M. Gardner. Wiley, 1966

1991 Dec 10