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EE 671 Vlsi Design: A) Design A Logarithmic Adder Using Brent Kung Architecture For Adding 32 Bit Operands

A 32-bit logarithmic adder was designed using Brent Kung architecture and implemented in synthesizable VHDL. Simulation results demonstrated correct functionality for test vectors with inputs A = FFFFFFFF, B = 00000000F, and Cin = 1, producing Sum = 0000000E and Cout = 1. The critical path was identified as producing the sum output at the 30th place, requiring a maximum delay of 3150 picoseconds.

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Naveen Thotapalli
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90 views3 pages

EE 671 Vlsi Design: A) Design A Logarithmic Adder Using Brent Kung Architecture For Adding 32 Bit Operands

A 32-bit logarithmic adder was designed using Brent Kung architecture and implemented in synthesizable VHDL. Simulation results demonstrated correct functionality for test vectors with inputs A = FFFFFFFF, B = 00000000F, and Cin = 1, producing Sum = 0000000E and Cout = 1. The critical path was identified as producing the sum output at the 30th place, requiring a maximum delay of 3150 picoseconds.

Uploaded by

Naveen Thotapalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE 671

VLSI DESIGN
A) Design a logarithmic adder using Brent Kung architecture for adding 32 bit
operands.

Write its hardware description in synthesizable VHDL and show its correct working
using a test bench with appropriate test vectors.
Added in separate files.

Simulated results:
When A=(FFFFFFFF)H i.e (11111111111111111111111111111111)2
B=(00000000F)H; I.e (00000000000000000000000000001111)2
Cin=1;
Sum=(0000000E)H; i.e(0000000000000000000000000001110)2
Cout=1;
Plot is shown below
Simulated waves:

B.Critical path
The critical path is defined as the path between an input and an output with the maximum
delay. In our case sum prodused at 30th place will take maximum delay. so, it’s the critical
path. We can guarantee the sum output after 3150 psec in worst case.

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