MAIA-009445-000000

X-Band Phased Array Transmit / Receive Module (TRM)

2010 Datasheet v1

The most important thing we build is trust

Description Features
The Cobham Sensor Systems X-Band 7-Bit TRM is a full integrated, • Full Integration • 1uS to 80uS TX pulse width
environmentally sealed, but not hermetic, module featuring full • 10W HPA MMIC • 30% max Duty Cycle
capability for phase array applications.
• 1GHz Bandwidth • On-board hexfet for P.A. Gating
The on-board serial to parallel conversion of the control data minimizes
• Low noise figure (<4dB) • Demonstration Kit available
connections and provides a simple method of controlling the phase
• 7 Bit serial Phase and (MAEA-009445-000000)
shift range of 0—360 deg and a gain setting range of more than 20dB.
The TRM covers the frequency range from 9 to 10GHz and can be used Amplitude Control
in Radar and Communication applications. • European Manufacture

Dimension
60.8 (L) x 13 (W) x 5.7 (H) mm

TRM Functional Schematic

Gating CNTRL
Tx Path

Core Chip

Common MPA P.A Antenna

Switch Port Port

LNA
Limiter

Rx Path

www.cobham.com/sensorsystems
MAIA-009445-000000
X-Band Phased Array Transmit / Receive Module (TRM)
2010 Datasheet v1

RF Performance RF Performance

Parameter Performance Power Supplies

Frequency 9.0 – 10.0GHz Core Chip Programming (Pin’s 18-20) Serial 3-Wire (CMOS & TTL) See Pg. 8
Peak Output Power @ 30% duty cycle >8.5W Input/Output Switch (Pin’s 11 & 7) Complimentary Logic:
Transmit Input Power +6dBm Nom Tx Direction (Common Switch Port - Antenna) V1 = 0V , V2 = -6V
Pulse droop 0.5dB Max Rx Direction (Antenna - Common Switch Port) V1 = -6V, V2 = 0V
Pulse Width 1 – 80 μS P.A Control (Pin 13) +5V on, 0V off (CMOS & TTL)
Duty Cycle 30% Max MPA Control (Pin 2) +5V @ 10mA on, 0V off
Receiver Protection 10W peak Rx LNA Control (Pin 12) +5V on, 0V off (CMOS & TTL)
Receiver Gain 20 dB Nom Performance: 40°C Base Plate Temperature, Zo = 50 , Nominal Power Supply Voltages, Fo=9.5GHz
Receiver 1dB Compression Point +2dBm
Noise Figure < 4dB
Attenuation Range 24dB (7 Bits @ 0.5dB/Bit) Environmental & Mechanical
Attenuation Error 0.13 dB RMS Operating Base Plate Temperature -40°C to +50°C
Gain Variation with Phase Setting 3.3 dB Storage Temperature -40°C to +85°C
Phase Range 360° (7 Bits @ 5.625° /Bit) Size 60.8mm (L) x 13mm (W) x 5.7mm (H)
Phase Error 4.8° RMS Mass 14 gm
Phase Variation with Attenuator Setting 7.5° Performance: 40°C Base Plate Temperature, Zo = 50 , Nominal Power Supply Voltages, Fo=9.5GHz
Input Return Loss/Output Return Loss (Antenna Port) 14dB/11dB
Rx/Tx Switching Speedtenna Port) 200nS (From Falling Edge of LE Pulse)
Performance: 40°C Base Plate Temperature, Zo = 50 , Nominal Power Supply Voltages,

Power Supplies
Average TX Power Consumption @ 20% Duty Cycle 8.1 W Typ
PA & MPA Drain Voltage (Pin 1) +8V @ 4.4A pk Typ
PA Gate Voltage (Pin 3) -5V @ 30mA Typ
CMOS FET Gate Driver Vcc (Pin 14) +15V @ 20mA Typ
Core chip & LNA Drain Voltage (Pin 4) +5V @ 200mA Typ
Core chip Vcc (Pin 5) +2.5V @ 13mA Typ
Core chip Vcc (Pin 16) -3V @ 2.5mA Typ
Core chip Vcc (Pin 15) -5V @ 5mA Typ
Performance: 40°C Base Plate Temperature, Zo = 50 , Nominal Power Supply Voltages, Fo=9.5GHz
 MAIA-009445-000000
X-Band Phased Array Transmit / Receive Module (TRM)
2010 Datasheet v1

Typical Performance Typical Performance

Attenuation Set Error at 9.5GHz Phase Set Error at 9.5GHz
0.6 12
10
8
0.4
6
4
Attenuation Error (dB)

0.2 2
0

Phase Error (°)

-2
0.0 -4
-6
-0.2 -8
-10
-12
-0.4 -14
-16
-18
-0.6
0 5 10 15 20 25 -20
Attenuation Setting (dB) 0 50 100 150 200 250 300 350 400
Phase Setting (°)

RMS Attenuator Error at Reference Phase Set Phase Shifter Rx Mode RMS Phase Error, Reference Amplitude Set
0.45 8

0.4
7
0.35
6
RMS Attenuator Error (dB)

0.3

RMS Phase Error (°)

5
0.25

0.2 4

0.15 3

0.1
2
0.05
1
0
9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000
0
Frequency (MHz) 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000
Frequency (MHz)
Attenuation Variation at Reference Phase for 128 States (Results include test fixture losses)
25 Rx Phase w.r.t Ref Phase at Reference Gain, 128 States
400
20
350
15
300
Phase w.r.t Ref Phase (°)

10
Gain (dB)

250

5
200

0 150

-5 100

-10 50
9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000
Frequency 0
9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000
Frequency (MHz)
 MAIA-009445-000000
X-Band Phased Array Transmit / Receive Module (TRM)
2010 Datasheet v1

Typical Performance Typical Performance

Pout & Gain vs Pin (Results include test fixture losses) Typical 10µS Pulse Droop
0.6 2.5

2
0.4
1.5

Normalised Output Power (dB)

1
0.2
0.5
Pout (dBm)

0.0 0

-0.5
-0.2
-1

-0.4 -1.5
Pout 9.0GHx Pout 9.5GHz Pout 10.0GHz -2
Gain 9.0GHz Gain 9.5GHz Gain 10.0GHz
-0.6
-25 -20 -15 -10 0 10 15 20 -2.5
0 3 5 7 9 11 13
Pin (dBm)
Time (µS)
Typical 80µS Pulse Droop
Noise Figure and Gain (Results include test fixture losses)
8
25 6

7
20 5

Normalised Output Power (dB)

6

5
15 4
Gain (dB)

10 3
3

2
5 2
Gain Noise Figure 1

0 1
9000 9250 9500 9750 10000 0
0 10 20 30 40 50 60 70 80 90
Frequency (MHz)
Time (µS)

Receiver Gain for all 128 Phase States (Results include test fixture losses) Absolute Maximum Ratings
25
24
Base-plate Temperature +75°C
23 Input Power +5V on, 0V off (CMOS & TTL)
22
PA & MPA Drain Voltage +8V Supply (Pin 1) +9V
21
20 PA Gate Voltage -5V Supply (Pin 3) -5 ± 0.5 V
Receiver Gain (dB)

19 MPA Control Voltage (Pin 2) +6.5V @ 10mA On, 0V Off

18
17 Core chip & LNA Drain Voltage +5V Supply (Pin 4) +6V
16 CMOS FET Gate Driver +15V Supply (Pin 14) +20V
15
14
Core chip +2.5V Supply (Pin 5) +3V
13 Core chip -3V Supply (Pin 16) -5V Min, -2V Max
12
Core chip -5V Supply (Pin 15) -5 ± 0.5 V
11
10 Input/Output Switch High Level control Voltage 0V to -2V
8995 9070 9145 9220 9295 9370 9445 9520 9595 9670 9745 9820 9895 9970 V1 & V2 Control Voltage (Pin’s 11 & 7) Low Level control Voltage -4.75V to -6V
Frequency (MHz)
* Operation of this device above anyone of these limits can result in permanent damage.
MAIA-009445-000000
X-Band Phased Array Transmit / Receive Module (TRM)
2010 Datasheet v1

Core Chip Programming Timing Diagram

t5
t1 t2 t3
t4
VH(+5V) VH(+5V)
CLK(PIN 19)
P.A. CNTRL(PIN 13) VL(0V)
VL(0V)
t6
B0 B1 B15 B16 VH(+5V)
Core Chip

R.F. Pulse
DATA(PIN 18)
VL(0V) t7
VH(+5V)

D.C. Controls
MPA CNTRL(PIN 2) VL(0V)
VH(+5V)
VH(+5V)
LE(PIN 20) Rx LNA CNTRL(PIN 12)
VL(0V) VL(0V)

Timing Diagram
• Input Digital levels are CMOS and TTL compatible VH(0V)
• Data is sampled at the falling edge of CLK Switch V1(PIN 11) VL(-6V)
• LE must occur when all bits are loaded and CLK is inactive
• An extra CLK pulse is necessary at the end with no significant DATA (B16). Total of 17 CLK pulses
Switch V2(PIN 7) VH(0V)
• Upon re-programming all bits must be sent even if unchanged
VL(-6V)
Logic Truth Table Timing Characteristics
CLK(PIN 19)
Bit Number Description Reference State Nom. Value Parameter Limit Unit Comment
B0 Phase shifter B6 High 178° t1 4 nS min Clock Rate

Core Chip
D0 . . . . . . D16 D0 . . . . . . D16
B1 Phase shifter B5 High 81° t2 10 nS min CLK to LE DATA(PIN 18)
B2 Phase shifter B4 High 52° t3 8 nS min LE Pulse Duration
B3 Not Used N/A t8
(1) Programming Rise & Fall times should be at least a factor of 10 times CLK period used.
B4 Phase shifter B3 High 31° LE(PIN 20)
B5 Phase shifter B2 High 16°
B6 Phase shifter B1 High 12°
B7 Phase shifter B0 High 6°
B8 Transmit/Receive High = transmit, N/A
Low = receive Timing Characteristics
B9 Attenuator B0 Low 0.4 dB Parameter Limit Unit Comment
B10 Attenuator B1 Low 0.6 dB t4 80 μS max P.A Drain voltage duration
B11 Attenuator B2 Low 11.3 dB t5 266 μS max P.A Drain Inter pulse duration (30%Duty Tx)
B12 Attenuator B3 Low 6.1 dB t6 1 μS typ P.A Drain D.C stability duration
B13 Attenuator B4 Low 1.1 dB t7 TBD μS max Tx/Rx Switching Guard Time
B14 Attenuator B5 Low 3.3 dB t8 200 μS max Core Chip Response Time (From Falling Edge of LE Pulse)
B15 Attenuator B6 Low 1.9 dB
(1) Control voltage Rise & Fall times: <5nS, 10% to 90%.
B16 End BIT High N/A
(2) Overshoot on control voltage lines should not exceed limits as specified on page 6.
MAIA-009445-000000
X-Band Phased Array Transmit / Receive Module (TRM)
2010 Datasheet v1

Mechanical Outline Package Pin-Out

Pin No. Description / Function Level

1 P.A Drain Supply +8.0V @ 4.4Apk
2 MPA Control VH=+5V@ 10mA, VL=0V
3 P.A Gate Voltage -5.0V @ 30mA
4 Core Chip & Rx LNA Supply (+5V) +5.0V @ 200mA
5 Core Chip Supply (+2.5V) +2.5V @ 13mA
6 GND Ground
7 V2, Input Switch Control Line (V2) VH=0V, VL=-6V
8 GND Ground
9 RF IN +10dBm (max)
10 GND Ground
11 V1, Input Switch Control Line (V1) VH=0V, VL=-6V
12 Rx LNA Control, Logic I/P Drive For Gate Driver CMOS & TTL
13 P.A Control, Logic I/P Drive For P.A Gate Driver CMOS & TTL
14 CMOS FET Gate Driver Vcc +15V @ 20mA
15 Core Chip Supply (-5V) -5V @ 5mA
16 Core Chip Supply (-3V) -3V @ 5mA
17 BITE out (thru line) –
18 Data, Core Chip SPI Interface CMOS & TTL
19 CLK, Core Chip SPI Interface CMOS & TTL
20 LE, Core Chip SPI Interface CMOS & TTL
21 BITE in (thru line) –
22 +5V out (thru line) –
23 GND Ground
24 GND Ground
25 RF OUT (Antenna port) –
26 GND Ground
 For further information please contact:
Cobham Sensor Systems
Featherstone Road
Wolverton Mill
Milton Keynes, MK12 5EW
England
Tel: +44 (0) 1908 574200
Fax: +44 (0) 1908 574300
E-mail - cobham.mal@cobham.com

Cobham MAL Ltd trading as Cobham Sensor Systems

www.cobham.com/sensorsystems
© Cobham plc, 2010. Whilst every effort is made to ensure the accuracy of the information contained in this brochure, no responsibility
can be accepted for any errors and/or omissions. Descriptions and specifications of products are subject to change without notice.