Disclaimer

Exar reserves the right to make changes in the products contained in this book in order to improve design or perform-
ance and to supply the best possible products. Exar also assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representations that the circuits are
free from patent infringement. Applications for any integrated circuits contained in this publication are for illustration
purposes only and Exar makes no representation or warranty that such applications will be suitable for the use speci-
fied without further testing or modification. Reproduction of any portion hereof without the prior written consent of
Exar is prohibited.

Revised Edition First Printing-April 1986

750 Palomar Avenue

Sunnyvale, CA 94086
Telephone (408) 732-7970
TWX: 910-339-9233
 DATABOOK

EXAR Corporation 750 Palomar Avenue, Sunnyvale, California 94086

 Commitment to Excellence and Reliability
One of the founding principles of EXAR has been to provide our
customers with unsurpassed service and quality. Today, every indi-
vidual at EXAR has taken this principle as a personal commitment,
assuring that quality and reliability are built into all our products
from inception to realization.

For more than a decade, this commitment to excellence has allowed

EXAR to establish itself as a dependable supplier to industry leaders
in the telecommunications, data communications, computer
peripherals, and industrial control markets. As an ASIC (Applications
Specific Integrated Circuit) manufacturer, EXAR brings years of
accumulated engineering expertise in the design of USIC (User
Specific Integrated Circuit) for customers with unique requirements.
EXAR's ASSP (Application Specific Standard Product), USIC and
GPSP (General Purpose Standard Product), along with our linear
and digital applications support, allow us to offer a total solution
to your system requirements.

I am certain that our commitment and dedication to quality, technol-

ogy, and service will develop an outstanding long term relationship
with you, our valued customer.

Nob Hatta
President
 TABLE OF CONTENTS

Section 1 - Cross References and Ordering Information . . . . 1-1

Application Specific Standard Product Cross Reference 1-2
Telecommunication Product Cross Reference 1-2
Industry-wide Cross Reference 1-4
Numeric Index . . . . . . . . . . . . . . 1-3
Ordering Information ......... . 1-7
Section 2 - Telecommunication Circuits 2-1
PCM Line Interface . . . . . . . . . . . 2-2
XR-T5650 PCM Line Receiver & Clock Recovery Circuit 2-2
XR-T5670 B8ZS/AMI Line Transcoder 2-6
XR-T5675 Dual Line Driver ......... . 2-11
XR-T5680 PCM Line Interface Chip . . . . . . . . . . . 2-15
XR-T5681 PCM Transceiver Chip . . . . . . . . . . . . 2-17
XR-T5682 Voltage Controlled Crystal Oscillator . . . . . 2-19
XR-T5750 PCM Line Receiver & Clock Recovery Circuit 2-22
Repeaters . . . . . . . . . . . . . . . . . . . . 2-25
XR-C240 Monolithic PCM Repeater . . . . . 2-26
XR-C262 High Performance PCM Repeater . 2-28
XR-C262Z High Performance PCM Repeater 2-30
XR-C277 Low Voltage PCM Repeater . . . . 2-32
XR-C587/C588 T1 C PCM Repeater Chip Set 2-34
XR-T56001T5620 T1, T148C & 2 Mbitls PCM Line Repeater 2-40
XR-T57001T5720 T1, T148C & 2 Mbitls PCM Line Repeater 2-50
Speakerphone Circuits . . . . . . . . . . . 2-59
XR-T6420-1 Speakerphone Audio Circuit 2-60
XR-T6420-2 Speakerphone Audio Circuit 2-64
XR-T6421 Speakerphone Control IC .. . 2-68
XR-T6425 Speakerphone IC . . . . . . . 2-72
Telephone Set Circuits . . . . . . . . . . . 2-79
XR-T5990 Single Chip PulselTone Dialer 2-80
XR-T5992 Pulse Dialer .. 2-87
XR-T5995 Speech Network ..... . 2-93
XR-T8205 Tone Ringer . . . . . . . . . 2-97
Section 3 - Data Communication Circuits · 3-1
Modem Basics . . . . . . . . . . . . . · 3-2
XR-2121 Bell 212A Type Modulator .. · 3-8
XR-2122 Bell 212A Type Demodulator 3-16
XR-2123/2123A PSK Modulator/Demodulator 3-26
XR-2125 Bell 212A Type Data Buffer 3-37
XR-14412 FSK Modem System 3-42
Filters . . . . . . . . . . . . . . . . . . 3-49
XR-2103 Modem Filter . . . . . . . . 3-50
XR-2120 PSK Modem Filter . . . . . 3-55
XR-2126/2127/2128/2129 Bell 212A1CCITT V.22 Modem Filters 3-62
Line Interface Circuits . . . . . . . . . . . . 3-73
XR-1488/1489 Quad Line Driver/Receiver 3-74
Section 4 - Computer Peripheral Circuits . · 4-1
XR-117 Hard Disk Read/Write Amplifier . · 4-2
XR-2247/2247A Floppy Disk Write Amplifier · 4-6
XR-3448 Floppy Disk Read/Write Amplififer 4-13
XR-3470Al34 70B Floppy Disk Read Amplifier 4-21
XR-3471 Floppy Disk Write Amplifier 4-28
Section 5 - Industrial Circuits . . . . . . . 5-1
Operational Amplifiers . . . . . . . . . . . . 5-2
Fundamentals of Operational Amplifiers . 5-2
Definitions of Operational Amplifier Terms 5-3
Basic Applications of Operational Amplifiers 5-4
Choosing the Right Op Amp . . . . . . . . 5-10
XR-082/083 Dual Bipolar JFET Operational Amplifier 5-12
XR-084 Quad Bipolar JFET Operational Amplifier 5-15
XR-094/095 Quad Programmable Bipolar JFET Operational Amplifier 5-17
XR-096 Quad Programmable Bipolar JFET Operational Amplifier 5-19
XR-146/246/346 Programmable Quad Operational Amplifiers 5-21
XR-1458/4558 Dual Operational Amplifiers 5-25
XR-3403/3503 Quad Operational Amplifiers . . . . . 5-27
XR-4136 Quad Operational Amplifier . . . . . . . . 5-30
XR-4202 Programmable Quad Operational Amplifier 5-33
XR-4212 Quad Operational Amplifier 5-37
XR-4560 Dual Low Noise Operational Amplifier . . . 5-40
XR-4739 Dual Low Noise Operational Amplifier .. . 5-44
XR-4741 Quad Operational Amplifier . . . . . . . . 5-47
XR-5532/5532A Dual Low Noise Operational Amplifiers 5-50
XR-5533/5533A Dual Low Noise Operational Amplifiers 5-54
XR-5534/5534A Dual Low Noise Operational Amplifiers 5-58
Timers . . . . . . . . . . . . . . . 5-63
Fundamentals of IC Timers 5-63
Choosing the Right IC Timer . . . . 5-67
XR-320 Monolithic Timing Circuit 5-70
XR-555 Timing Circuit . . . . . . . 5-75
XR-L555 Micropower Timing Circuit 5-78
XR-556 Dual Timer . . . . . . . . 5-82
XR-L556 Micropower Dual Timer 5-85
XR-558/559 Quad Timing Circuits . 5-91
XR-2556 Dual Timing Circuit . . . . 5-95
XR-2240 Programmable Timer/Counter · 5-104
XR-2242 Long Range Timer . . . . . . · 5-112
XR-2243 Micropower Long Range Timer · 5-116
Voltage Regulators . . . . . . . . . . . . . · 5-121
XR-494 Pulse-Width Modulating Regulator · 5-122
XR-495 Pulse-Width Modulating Regulator · 5-126
XR-1468/1568 Dual Polarity Tracking Voltage Regulators · 5-130
XR-1524/2524/3524 Pulse-Width Modulating Regulators · 5-132
XR-1525A12525A13525A,
XR-1527Al2527 Al3527 A Pulse-Width Modulating Regulators · 5-140
XR-1543/2543/3543 Power Supply Output Supervisory Circuits · 5-147
XR-2230 Pulse-Width Modulator Control System · 5-155
XR-4194 Dual-Tracking Voltage Regulator . . . . · 5-162
XR-4195 ± 15 V Dual-Tracking Voltage Regualtor · 5-165
Section 6 - Instrumentation Circuits . . . . . . . . 6-1
Function Generators . . . . . . . . . . . . . . . . 6-2
Fundamentals of Monolithic Waveform Generation and Shaping 6-2
Choosing the Right IC Oscillator . . . . 6-3
XR-205 Monolithic Waveform Generator 6-5
XR-2206 Monolithic Function Generator . 6-10
XR-2207 Voltage-Controlled Oscillator . . 6-16
XR-2209 Precision Oscillator . . . . . . . 6-25
XR-8038 Precision Waveform Generator 6-30
XR-8038A Precision Waveform Generator 6-34
Multipliers/Multiplexers . . . . . . . . . 6-36
XR-2208 Operational Multiplier . . . . 6-38
XR-2228 Monolithic Multiplier/Detector . . 6-46
 Phase-Locked Loops . . . . . . . . . . . 6-55
Fundamentals of Phase-Locked Loops 6-56
Applications of PLL ICs ....... . 6-57
Choosing the Right PLL Circuit 6-59
XR-210 Modulator/Demodulator 6-60
XR-215 Monolithic Phase-Locked Loop 6-60
XR-2211 FSK DemodulatorlTone Decoder 6-65
XR-2212 Precision Phase-Locked Loop . 6-82
XR-2213 Precision Phase-Locked LooplTone Decoder 6-89
Tone Decoders . . . . . . . . . . . . 6-95
XR-567 Monolithic Tone Decoder 6-96
XR-567 A Precision Tone Decoder . . . · 6-106
XR-L567 Micropower Tone Decoder . . · 6-108
XR-2567 Dual Monolithic Tone Decoder · 6-115

Section 7 - Interface Circuits . . . . . . . 7-1

Display Drivers . . . . . . . . . . . . . . 7-2
XR-2271 Fluorescent Display Driver . . 7-2
XR-2272 High Voltage 7-Digit Display Driver 7-4
XR-2284/2288 High Voltage AC Plasma Display Drivers 7-7
XR-6118/6128 Fluorescent Display Drivers . . . . . . . 7-11
High Current Drivers . . . . . . . . . . . . . . . . . . . . 7-15
XR-2001/2002/2003/2004 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . 7-16
XR-2011/2012/2013/2014 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . 7-20
XR-2200 Hammer Driver . . . . . . . . . . . . . . . . . . . . . 7-24
XR-2201/2202/2203/2204 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . 7-26
Section 8 - Special Function Circuits . 8-1
XR-S200 Multi-Function PLL System . 8-2
XR-1310 Stereo Demodulator 8-11
XR-2216 Monolithic Compandor .. 8-13
XR-2264/2265 Pulse-Proportional Servo Circuit 8-17
XR-2266 Monolithic Servo Controller 8-20
XR-2917 Frequency-to-Voltage Converter . . . 8-28
XR-4151 VOltage-to-Frequency Converter . . . 8-38
XR-9201 8-Bit Microprocessor Compatible Digital-to-Analog Converter 8-43
XR-13600 Dual Operational Transconductance Amplifier . . . . . 8-51
Section 9 - User Specific Linear ICs - Semi-Custom/Full Custom 9-1
Semi-Custom Design Concept . . . . . 9-2
Answers to Frequently Asked Questions 9-4
Economics of Semi-Custom Design 9-5
Converting Semi-Custom to Full Custom 9-6
Full Custom Development 9-8
Testing of Semi-Custom ICs 9-9
Linear Semi-Custom Design 9-10
Linear Semi-Custom Design Cycle 9-11
Full Custom Designs 9-12
Linear Master-Chips . . . 9-14
XR-A 100 Master-Chip 9-16
XR-B100 Master-Chip 9-17
XR-C100A Master-Chip 9-18
XR-D100 Master-Chip 9-19
XR-E100 Master-Chip 9-20
XR-F100 Master-Chip 9-21
XR-G100 Master-Chip 9-22
XR-H100 Master-Chip 9-23
XR-J100 Master-Chip . 9-24
 XR-L 100 Master-Chip . 9-25
XR-M100 Master-Chip 9-26
XR-U100 Master-Chip 9-27
XR-V100 Master-Chip 9-28
XR-W100 Master-Chip 9-29
XR-X100 Master-Chip 9-30
XR-400 12L Master-Chip . 9-31
Linear Master-Chip Components Electrical Characteristics 9-32
Linear Master-Chip Kit Parts . . . . . . . . . . . . . . . . 9-34

Section 10 - User Specific Digital ICs - Semi-Custom/Full Custom 10-1

Semi-Custom Solutions (Gate Arrays) . 10-2
30,000 Series . . . . . . . . . . . . . . 10-3
CM Series . . . . . . . . . . . . . . . . . . . . 10-7
Full Custom Solutions (Standard Cells) 10-9
A3000 Standard Cell Family . . . . . . . . . . 10-10
Full Custom Conversions (Two Step Approach) . 10-12

Section 11- Application Notes . . . . . . . . . . . . . . . . . . . . . . . . · 11-1

Applications Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · 11-2
AN-01 Stable FSK Modem Featuring the XR-2207, XR-2206, and XR-2211 · 11-7
AN-02 XR-C240 Monolithic PCM Repeater . . . . . . . . . . . . . . . . . .11-13
AN-03 Active Filter Design with IC Op Amps . . . . . . . . . . . . . . . . · 11-20
AN-04 XR-C277 Low Voltage PCM Repeater IC . . . . . . . . . . . . . . · 11-28
AN-05 Three Stage FSK Modem Design Using the XR-2207 and XR-2211 · 11-35
AN-06 Precision PLL System Using the XR-2207 and XR-2208 '" · 11-41
AN-07 Single Chip Frequency Synthesizer Employing the XR-2240 · 11-45
AN-08 Dual Tone Decoding with XR-567 and XR-2567 . . . . . . . . . . . · 11-47
AN-09 Sinusoidal Output from XR-215 Monolithic PLL Circuit . . . . . . . · 11-50
AN-10 XR-C262 High Performance PCM Repeater IC . . . . . . . . . . . · 11-53
AN-11 A Universal Sine Wave Converter Using the XR-2208 and XR-2111 · 11-61
AN-12 Designing High Frequency Phase-Locked Loop Carrier Detector Circuits · 11-65
AN-12 Frequency Selective AM Detection Using Monolithic Phase-Locked Loops . · 11-68
AN-14 High Quality Function Generator System with the XR-2206 . . . · 11-72
AN-15 An Electric Music Synthesizer Using the XR-2207 and XR-2240 · 11-76
AN-16 Semi-Custom LSI Design with 12L Gate Arrays . . . . · 11-78
AN-17 XR-C409 Monolithic 12L Test Circuit . . . . . . . . . . . . . . . · 11-84
AN-18 Designing Wide-Tracking Phase-Locked Loop Systems . . . . . · 11-88
AN-19 Clock Recovery System . . . . . . . . . . . . . . . . . . . . . . · 11-92
AN-20 Building a Complete FSK Modem Using XR-2211 and XR-2206 · 11-95
AN-21 Precision Narrow-Band Tone Decoder . . . . . . . . . . . . . . · 11-98
AN-22 XR-210, XR-215, XR-S200 Phase-Locked Loops . . . . . . . . 11-101
AN-23 High Performance Frequency-to-Voltage Converter Using the XR-2211 11-110
AN-24 Digitally Programmable Phase-Locked Loop . . . . . . . . 11-112
AN-25 Full Duplex 1200 BPS/300 BPS Modem System 11-115
AN-26 High Speed FSK Modem Design . . . . . . . . . . . . . . 11-119
AN-27 High Frequency TTL Compatible Output from the XR-215
Monolithic PLL Circuit . . . . . . . . . . . . . . . . . . . . . 11-125
AN-28 XR-212AS Modem System . . . . . . . . . . . . . . . . 11-128
AN-29 XR-212ACS Performance Testing ........... . 11-132
AN-30 Speakerphone Design Using XR-T6420-1 and XR-T6421 11-134
AN-31 PCM Line Interface Using XR-T5680 . . . . . . . 11-138
AN-32 PCM Short Haul Line Interface Using XR-T5681 11-143
Implement Bell T1 C PCM Repeater Using Just Two ICs
by M. Kursat Kimyacioglu, EXAR Corp., Article Reprint 11-148
Section 12 - Quality Assurance and Reliability 12-1
Quality Assurance and Reliability 12-2
Section 13 - Packaging Information .. 13-1
Packaging Information/Plastic . . . . . . 13-2
Packaging Information/Cerdip 13-4
Packaging Information/Small Outline 13-6
Monolithic Chips for Hybrid Assemblies 13-9
The Benefits of Surface Attachment . . · 13-10
Reliability Data . . . . . . . . . . . . .. · 13-10
Products Available in Surface Mountable Packages · 13-11
Package Dimensions . . . . . . . . . . . . . . · 13-11
Surface Mounting Manufacturing Techniques · 13-12
Glossar,' of Surface Attachment Terms . . . . . . . · 13-12
Section 14 - Authorized Sales Repesentatives and Distributors 14-1
Authorized Sales Representatives and Distributors . . . . . . · 14-2
I---------
Telecommunication Circuits
......
•

I. . .
D_a_ta__
C_om
__m_u_n_ic_a_ti_o_n_C_i_rc_u_it_s________________•

Computer Peripheral Circuits

Industrial Circuits

Instrumentation Circuits

[ Interface Circuits

Special Function Circuits

User Specific Linear ICs

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

 Section 1 - Cross References and Ordering Information
Application Specific Standard Product Cross Reference
Telecommunication Product Cross Reference
1-2
1-2
II
Industry-wide Cross Reference 1-3
Numeric Index 1-4
Ordering Information 1-7

1-1
 APPLICATION SPECIFIC STANDARD PRODUCTS
(ASSP'S) CROSS REFERENCE
MODEMS - COMPETITION (NOT PIN COMPATIBLE UNLESS SPECIFIED)
EXAR Silicon TC:\:3S Micro
o.vlct'" AMI Fairchild Rockwell Sl~l('m\ In\lrument"l Power l\luforola AI\IO
-"R-~12"CS S35~ I ~A uA~l:!" R~I~UI' ~ I ~'\/IU3 TMS9953~A MI'7~"6 '\MU"C1~
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-"R-3470 MCH70 MCH7U CS3470
.\R-3"71 MC347 I I\1C347 I CSH7I
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.\R-~247 SSII17
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TELECOMMUNICATION PRODUCTS
CROSS REFERENCE
TELECOMMUNICATION (PIN COMPATIBLE)
LXAR Rohm l\1ilel l\Io\I.'k SharI' To~hib .. I'~II Chl'n~

XR-1'8205 IJA6565 ML8205 'f,\31 OU~I' CSR~lI~

XR-T6"25 DA6571
XR-1'5992 IJU899~ MK50992 LR40992
XR-1'S99U IJU656~

XR-C277 I{I'T82

1-2
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 NUMERIC INDEX
XR-082 Dual Bipolar JFET Operational Amplifier .............................................. 5-12
XR-083 Dual Bipolar JFET Operational Amplifier .............................................. 5-12
XR-084 Dual Bipolar JFET Operational Amplifier .............................................. 5-15
XR-094 Quad Programmable Bipolar JFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-17
XR-095 Quad Programmable Bipolar JFET Op Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-17
XR-096 Quad Programmable Bipolar JFET Op Amp ........................................... 5-19
XR-117 Hard Disk Read./Write Amplifier ....................................................... 4-2
XR-146 Programmable Quad Bipolar JFET Op Amp ........................................... 5-21
XR-S200 Multi-Function Phase Lock Loop (Video Bandwidth) ..................................... 8-2
XR-205 Waveform Generator ................................................................ 6-5
XR-210 FSK Modulator/Demodulator ........................................................ 6-60
XR-215 General Purpose Phase-Locked Loop ..................................... . . . . . . . . . .. 6-65
XR-C240 PCM Repeater T1 ............................................................... 2-26
XR-246 Programmable Quad Op Amp ...................................................... 5-21
XR-C262 High Performance PCM Repeater .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-28
XR-C262Z High Performance PCM Repeater 2MBit ........................................... 2-30
XR-C277 PCM Repeater DC Test .......................................................... 2-32
XR-320 Timing Cicuit ........................................... '.......................... 5-70
XR-346 Progammable Op Amp ............................................................ 5-21
XR-494 Pulse-Width Modulating Regulator .................................................. 5-122
XR-495 Pulse-Width Modulating Regulator with On-Chip 39V Zener ............................. 5-126
XR-555 Timing Circuit .................................................................... 5-75
XR-L555 Micropower Timing Circuit ......................................................... 5-78
XR-556 Dual Timing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-82
XR-L556 Micropower Dual Timing Circuit .................................................... 5-85
XR-558 Quad Timer Circuit Open Collector Output ............................................ 5-91
XR-559 Quad Timer Circuit Emitter Follower Output ........................................... 5-91
XR-567 Tone Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-96
XR-567A Precision Tone Decoder ......................................................... 6-106
XR-L567 Micropower Tone Decoder ....................................................... 6-108
XR-C587 TIC PCM Repeater-Preamp/ALBO Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-34
XR-C588 TIC PCM Repeater-Main Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-34
XR-1458 Dual Operational Amplifier ......................................................... 5-25
XR-1468 Dual Polarity Tracking Voltage Regulator ........................................... 5-130
XR-1488 Quad Line Driver ................................................................ 3-74
XR-1489 Quad Line Receiver ............................................................. , 3-74
XR-1524 Pulse-Width Modulating Regulator ................................................. 5-132
XR-1525 Pulse-Width Modulating Regulator with Soft Start ..................................... 5-140
XR-1527 Pulse-Width Modulating Regulator with Soft Start ..................................... 5-140
XR-1543 Power Supply Supervisory ........................................................ 5-147
XR-1568 Dual Polarity Tracking Regulator .................................................. 5-130
XR-2001 High Voltage, High Current Darlington Array, CMOS Interface .......................... 7-16
XR-2002 High Voltage, High Current Darlington Array, PMOS Interface ......... ; ................. 7-16
XR-2003 High Voltage, High Current Darlington Array, TTL Interface ............................. 7-16
XR-2004 High Voltage, High Current Darlington Array, PMOS-CMOS Interface ..................... 7-16
XR-2011 High Voltage, High Current Darlington Array, CMOS Interface .......................... , 7-20
XR-2012 High Voltage, High Current Darlington Array, PMOS Interface ........................... 7-20
XR-2013 High Voltage, High Current Darlington Array, TTL Interface ............................. 7-20
XR-2014 High Voltage, High Current Darlington Array, PMOS-CMOS Interface ..................... 7-20
XR-2103 FSK Modem Filter-103 ............................................................ 3-50
XR-2120 PSK Modem Filter-212A .......................................................... 3-55
XR-2121 Bell 212A Modulator ................................................................ 3-8
XR-2122 Bell 212A Modulator .............................................................. 3-16
XR-2123/2123A PSK Modulator/Demodulator ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-26
XR-2125 Bell 212A Data Buffer ............................................................ 3-37
1-4
XR-2126 Bell 212AN.22 Modem Filter ...................................................... , 3-62
XR-2127 Bell 212AN.22 Modem Filter with Analog Loopback (ALB) .............. " ...... " ...... 3-62
XR-2128 Bell 212AN.22 Modem Filter with ALB and Enhanced CPM ............................ 3-62
XR-2129 Bell 212AN.22 Modem Filter with ALB and Enhanced CPM ............................ 3-62
XR-2200 Hammer Driver .......... " .............................................. " ...... 7-24
XR-2201 High Voltage, High Current Darlington Array, CMOS Interface. . . . . . . . . . . . . . . . . . . . . . . . . .. 7-26
XR-2202 High Voltage, High Current Darlington Array, PMOS Interface ........................... 7-26
XR-2203 High Voltage, High Current Darlington Array, TIL Interface ..................... . . . . . .. 7-26
XR-2204 High Voltage, High Current Darlington Array, PMOS-CMOS Interface ..... '" ............ , 7-26
XR-2206 Monolithic Function Generator .............................................. " . . . . .. 6-10

•
XR-2207 Voltage Controlled Oscillator ............................................... " ...... 6-16
XR-2208 Operational Multiplier ..................................................... " ...... 6-38
XR-2209 Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-25
XR-2211 FSK Demodulatorrrone Decoder ................................................... 6-74
XR-2212 Precision Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-82
XR-2213 PLLfTone Decoder ....................................................... " ...... 6-89
XR-2216 Monolithic Compander .................................................... " ...... 8-13
XR-2228 Multiplier/Detector '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-46
XR-2230 PWM Switching Regulator ................................................. " ..... 5-155
XR-2240 Programmable Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-104
XR-2242 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-112
XR-2243 Micropower Long Range Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-116
XR-2247CN Floppy Disk Write Amplifier ....................................................... 4-6
XR-2264 Pulse-Proportional Servo Circuit .................................................... 8-17
XR-2265 Pulse-Proportional Servo Circuit Open Collector Outputs ............................... 8-17
XR-2266 Servo Controller ................................................................. 8-20
XR-2271 Fluorescent Display Driver ........................................................... 7-2
XR-2272 High Voltage 7-Digit Display Driver ................................................... 7-4
XR-22B4 High Voltage Plasma Display Driver ................................................... 7-7
XR-2288 High Voltage AC Plasma Display Driver ............................................... 7-7
XR-2524 Pulse-Width Modulating Regulator with Soft Start ..................................... 5-132
XR-2525 Pulse-Width Modulating Regulator with Soft Start ..................................... 5-140
XR-2543 Power Supply Supervisory ........................................................ 5-147
XR-2556 Dual Timing Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-95
XR-2567 Dual Monolithic Tone Decoder .................................................... 6-115
XR-2917 Frequency-to-Voltage Converter .................................................... 8-28
XR-3403 Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-27
XR-344B Single Chip Floppy Disk ReadlWrite Amplifier ........................................ 4-13
XR-3470A Floppy Disk Read Amplifier ....................................................... 4-21
XR-3470B Floppy Disk Read Amplifier ....................................................... 4-21
XR-3471 Floppy Disk Write Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-28
XR-3503 Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-27
XR-3524 Pulse-Width Modulating Regulator ................................................. 5-132
XR-3525A Pulse-Width Modulating Regulator with Soft Start ................................... 5-140
XR-3527A Pulse-Width Modulating Regulator with Soft Start ................................... 5-140
XR-3543 Power Supply Supervisory ........................................................ 5-147
XR-4136 Quad Operational Amplifier ....................................................... 5-30
XR-4151 Voltage-to-Frequency Converter .................................................... 8-38
XR-4194 Dual Tracking Voltage Regulator .................................................. 5-162
XR-4195 ± 15V Dual Tracking Voltage Regulator ............................................ 5-165
XR-4202 Programmmable Quad Operational Amplifier ......................................... 5-33
XR-4212 Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-37
XR-455B Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-25
XR-4560 Dual Low Noise Operational Amplifier ........................................ . . . . . .. 5-40
XR-4739 Dual Low Noise Operational Amplifier ............................................... 5-44
XR-4741 Quad Operational Amplifier ........................................................ 5-47
XR-5532 Dual Low Noise Operational Amplifier ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-50
XR-5533 Dual Low Noise Operational Amplifier ........................................ . . . . . .. 5-54
XR-5534 Single Low Noise Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-58
1-5
XR-T5600 T148 PCM Repeater DC Test .................................................... 2-40
XR-T5620 T148 PCM Repeater AC/DC Test ................................................. 2-40
XR-T5650 PCM Line Receiver ............................................................... 2-2
XR-T5670 B8ZS/AMI Transcoder ............................................................. 2-6
XR-T5675 Line Driver ..................................................................... 2-11
XR-T5680 PCM Transreceiver 8Mbit ........................................................ 2-15
XR-T5681 PCM Transreceiver 2Mbit-prices entered ............................................ 2-17
XR-T5682 Voltage Controlled Crystal Oscillator ............................................... 2-19
XR-T5700 Crystal Version of T5600 ......................................................... 2-50
XR-T5720 Crystal Version of T5620 ......................................................... 2-50
XR-T5750 Crystal Version of T5650 ......................................................... 2-22
XR-T5990 Tone/Pulse Dialer ............................................................... 2-80
XR-T5992 Pulse Dialer (MK50992 second source) ............................................ 2-87
XR-T6420-1 Speakerphone Audio Circuit of 2 Chip Set ........................................ 2-60
XR-T6420-2 Speakerphone Audio Circuit of 2 Chip Set ........................................ 2-64
XR-T6421 Speaker Control Circuit of 2 Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-68
XR-T6425 Single Chip Speakerphone ....................................................... 2-72
XR-T8205 Tone Ringer ................................................................... 2-97
XR-6118 Fluorescent Display Driver ......................................................... 7-11
XR-6128 Fluorescent Display Driver ........................................................ 7-11
XR-8038 Precision Waveform Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-30
XR-8038A Precision Waveform Generator with Low ~THD/d T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-34
XR-13600 Dual Transconductance Operational Amplifier ........................................ 8-51
XR-14412 FSK Modem System ............................................................ 3-42

1-6
 PRODUCT ORDERING INFORMATION

Part Identification

XR XXXXX Definition of Symbols: •

Manufacturer's Prefix Basic Type
M = Military Grade Part, Ceramic Package Only.
Grade Package Type are guaranteed to operate over military tempera- I

ture range. Consult factory for level of high rei

M = Military N Ceramic Dual-in-Line screening.
N Prime Electrical P Plastic Dual-in-Line N Prime Grade Part, Ceramic Package
P Prime Electrical MD Plastic SOIC P Prime Grade Part, Ceramic Package
C Commercial (Surface Mount)
Q Quad Package
F 4.75 V to 15 V Operating
V 4.75 V to 6 V Voltage Ranges N, P, CN, and CP parts are electrically identical and
K Kit operate over O°C to +70°C unless otherwise stated. In
addition, Nand P parts generally have operating para-
Example meters more tightly controlled than the CN or CP parts.

~R.22l~
Manufacturer's Basic
__
Grade
"""1
Package
For details, consult EXAR Sales Headquarters or your
Sales/Technical Representatives.

Prefix Type Type

ORDER ENTRY:

EXAR Corporation
750 Palomar Avenue
P.O. Box 3575
Sunnyvale, CA 94088-3575

Phone: 408 732-7970

TWX: 910-339-9233 (EXAR SUVL)

1-7
 Cross References & Ordering Information

Data Communication Circuits

Computer Peripheral Circuits

Industrial Circuits

Instrumentation Circuits

Interface Circuits

Special Function Circuits

User Specific Linear ICs

User Specific Digital ICs

I
Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

2
 Section 2 - Telecommunication Products
PCM Line Interface . . . . . . . . . . . . . . . . . . . . . . . · 2-2
XR-T5650 PCM Line Receiver & Clock Recovery Circuit
· 2-2 •
XR-T5670 88ZS/AMI Line Transcoder · 2-6
XR-T5675 Dual Line Driver . . . . . . . . . . . 2-11
XR-T5680 PCM Line Interface Chip . . . . . . 2-15
XR-T5681 PCM Transceiver Chip . . . . . . . . 2-17
XR-T5682 Voltage Controlled Crystal Oscillator 2-19
XR-T5750 PCM Line Receiver & Clock Recovery Circuit 2-22
Repeaters . . . . . . . . . . . . . . . . . . . . . . 2-25
XR-C240 Monolithic PCM Repeater 2-26
XR-C262 High Performance PCM Repeater . 2-28
XR-C262Z High Performance PCM Repeater 2-30
XR-C277 Low Voltage PCM Repeater . . . . 2-32
XR-C587/C588 T1C PCM Repeater Chip Set . 2-34
XR-T5600/T5620 T1, T148C & 2 Mbitls PCM Line Repeater 2-40
XR-T57001T5720 T1, T148C & 2 Mbitls PCM Line Repeater 2-50
Speakerphone Circuits . . . . . . . . . . . . . 2-59
XR-T6420-1 Speakerphone Audio Circuit 2-60
XR-T6420-2 Speakerphone Audio Circuit 2-64
XR-T6421 Speakerphone Control IC . , . 2-68
XR-T6425 Speakerphone IC . . . . . . . . 2-72
Telephone Set Circuits . . . . . . . . . . . . . 2-79
XR-T5990 Single Chip PulselTone Dialer 2-80
XR-T5992 Pulse Dialer 2-87
XR-T5995 Speech Network 2-93
XR-T8205 Tone Ringer 2-97

2-1
 XR-T5650

PCM Line Receiver & Clock Recovery Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-T5650 is a monolithic bipolar IC designed for PCM
type line receiver applications operating at T1. T148C, T1C
and 2 M bitls data rates. It provides all the active circuitry ALBO SUBSTRATE
required to perform automatic line build out (ALBO)' GND GND

threshold detection, positive and negative data and clock

recovery. ALBO
PORT 1
ALBO
CONTROL

Clock recover using a crystal filter instead of an LC tank CLOCK

ALBO AMPLIFIER
circuit is also available as XR-T5750. PORT 2
BIAS

AMPLIFIER LC TANK
-VE INPUT INPUT
FEATURES
AMPLIFIER VCC
On Chip Positive and Negative Data, Clock Recovery +VE INPUT

Less than 10 ns Sampling Pulse over the Operating Range

AMPLIFIER CLOCK
Double Matched ALBO Ports -VE OUTPUT OUTPUT

Single 5.1 V Power Supply

PHASE SHIFTED
2 M Bitls CaP9bility AMPLIFIER
• VE OUTPUT CLOCK INPUT

[)IGITAL
C"OUND CLOCK

APPLICATIONS
+1 DRIVER

T1 PCM Line Receiver

T 14SC Line Receiver
T1 C PCM Line Receiver (requires external amplifier)
General Purpose Bipolar Line R.eceiver
HDB3 Line Receiver
BSZS Line Receiver
SYSTEM DESCRIPTION

The XR-T5650 is designed for interfacing T1, T14SC and

2 Mbitls PCM carrier lines on plastic or pulp insulated
ABSOLUTE MAXIMUM RATINGS
cables. It can also be used at T1C rate (3.152 M bit/s) with
external gain. Since it outputs plus and minus ones on a
bipolar pulse stream together with the clock, it can be used
Storage Temperature -65°C to +150°C to interface systems having different line codes like AMI,
Operating Temperature _40° to +S5°C AMI-B8ZS or AMI-HDB3.
Supply Voltage -0.5 to +10 V
Supply Voltage Surge (10 ms) +25 V The XR-T5650 is a modified version of XR-T5620 PCM
Input Voltage (except Pins 2,3,4,17) -0.5 to 7 V repeater IC. It contains all the active circuitry needed to
Input Voltage (Pins 2,3,4,17) -0.5 to +0.5 V build a PCM line receiver up to 6300 ft. cable length. The
Data Output Voltage (Pins 10,11 ) 20V preamplifier, the clock amplifier, threshold detectors,
Voltage Surge (Pins 5,6,10,11) (10 msec only) 50 V data latches and output drivers are similar to the ones on
X R-T5620. Clock extraction is done by means of an LC
tank circuit.

In addition to plus and minus one outputs, a synchronous

ORDERING INFORMATION clock signal is made available at Pin 11 by deleting one of
the ALBO ports on XR-T5620 thus leaving two matched
Part Number Package Operating Temperature ALBO ports. All outputs have high current open collector
XR-T5650 Ceramic -40°C to +85°C transistors.

2-2
 XR-T5650

ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 5.1 V ± 5%, TA = 25°C, unless specified otherwise.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

Supply Current 26 34 mA ALBO Off

Clock & Data Output
Output Leakeage Current 0 100 J,lA Vpull- up = 15 V
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
2.4

-50
2.2
2.9

0
3.4

50
V

mV
V
At DC Unity Gain

Rs = 8.2 kn
Measured Differentially from
II
Pin 7 to Pin 6
Amplifier Input
Bias Current 5 J,lA
ALBO on Current 3 mA
Drive Current 1 mA

AC CHARACTERISTICS

Pre Amplifier
AC Gain @ 1 MHz 50 dB
Input Impedance 20 kn
Output Impedance 200 n
Clock Amplifier
AC Gain 32 dB
-3 dB Bandwidth 10 MHz
Delay 10 ns
Output impedance 200 n
ALBO
Off Impedance 20 kn
On Impedance 25 n

CLOCK DATA OUTPUT BUFFERS RL = 130n, Vpull-up = 5.1 V ± 5%

Rise Time 30 ns
Fall Time 30 ns
Output Pulse Width 244 ns
Sample Pulse Width 10 ns
VOL 0.7 V
I L sink 35 mA

THRESHOLDS

ALBO 1.4 1.5 1.6 V

Clock Drive Current Peak 1.0 rnA At Va = VALBO Threshold

CLOCK THRESHOLD

% of ALBO 63 m 75 %

DATA THRESHOLD

% of ALBO 40 46 52 %

2-3
 AlE 415-0692

5,6 AlE 31S-<l821 220 220

]1
1:2
I
6
I
I 6
----
I\) 300
~
2

5.6 I ~

CLOCKO/P

·1·s O/P

+5.1

1.544 M Bits/Sec Universal PCM Line Receiver Application Circuit

Random Pattern - Max. Cable loss 36 dB
><
::u
I
--I
U1
0)
c.n
o
 ><
:::c
I
-I
en
0)
en
o
AlE PART NO. 415-0804

15K
5.6 AlE 315-0821

220 220
T5650
3

I\)
300
0,

5.6

.221'F

T
1 +
6o
. l'F
+5.1V

900
~---------------+--~r:>ClOCKO/P

+1's O/P <=1t---+--------..J t-------------.. . . .-C>-l·s IO/P

900

+5.1V
1.544 M Bits/Sec Universal PCM Line Receiver Application Circuit
Maximum Cable Loss 25 dB
 XR-T5670

B8ZS/ AMI Transcoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5670 is an lSI CMOS integrated circuit which

performs the B8ZS or AMI transmission coding and re-
ceiving decoding functions with error detection. It is in-
tended for DS1 (1.544 Mbits/s) PCM transmission applica-
tions, but can operate at clock frequencies up to 161 MHzl.
The device is packaged in a 16 Pin CERDIP package and the
operating temperature is between -40°C to +85°C.

FEATURES

B8ZS Coding and Decoding for Data Rates

up to 6 Mbits/s to AT&T Technical Advisory 69
B8ZS/AMI Transmission Coding/Reception Decoding
with Code Error Detection SYSTEM DESCRIPTION
A" Transmitter and Receiver Inputs/Outputs are
TTL Compatible Coder
Internal loop Test Cilpability
Single 5 V ± 10% Supply Rail Binary data in "NRZIN" is clocked into the coder by a
synchronous transmission clock "TXClKIN" on the falling
edge. The "+B8ZS" and "-B8ZS" output signals appear 8.5
clock cycles later to allow for the insertion of extra pulses
due to sequences of eight consecutive zeros. These two sig-
APPLICATIONS nals are full width data and will be mixed with the "TX
ClKIN" at the input of an external line driver to produce
AMI Encoding/Decoding bipolar B8ZS signals for transmission.
B8ZS Encoding/Decoding
Decoder

Received half widt.h data on "+B8ZSIN" and "-B8ZSIN"

are locked into the decoder on the rising edge of the re-
ABSOLUTE MAXIMUM RATINGS ceived clock "RXClKIN". The "NRZOUT" binary data
output occurs on eight clock cycles later. Received signals
DC Supply Voltage (VDD) -0.3 to 7.0 V not consistant with B8ZS coding rules are detected as
Input Voltage Range (VIN) -0.3 to VDD + 0.3 V errors. The error output "E R RO R" is active high during
Input Protection Current (lD) ±10mA one "RXClKIN" clock period.
Storage Temperature Range -55°C to 150°C
Operating Temperature Range AIS (Alarm Indication Signal)
Ceramic _40° C to +85° C
Plastic O°C to 70°C If the decoder inputs received a continuous of ones (all
marks) over two consecutive periods of the external reset
signal "RAIS", the "AISOUT" output will be set high and
latched in that state until one or more zeros are received
ORDERING INFORMATION when the next reset signal "RAls" occurs.

Part Number Package Operating Temperature The number of received zeros required to reset "AISOUT"
XR-T5670CP Plastic OOC to 70°C over two consectuive periods of "RAls" can be mask pro-
XR-T5670CN Ceramic -40°C to +85°C grammed to two or three.

2-6
XR-T5670

ELECTRICAL CHARACTERISTICS
Test Conditions: T A -- _40°C to +85 C. VDD ~ 4.5 to 5.5 V. unless specified otherwise.
0

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

DYNAMIC CHARACTERISTICS

TXCLKIN Clock Input Frequency 6 MHz

Clock Input Frequency 6 MHz

•
RXCLKIN

tsl Data Set-Up Time 55 ns NRZIN to TXCLKIN

See Figure 6

thl Data Hold Time 25 ns NRZIN to TXCLKIN

See Figure 6

tpdl Data Propagation Delay TXCLKIN to BSZS OUT

Time 65 ns See Figures 3 and 6, Note 1

ts2 Data Set-Up Time 55 ns BSZSIN to RXCLKIN

See Figure 7. Loop Test = 0

th2 Data Hold Time 0 ns BSZSIN to RXCLKIN

See Figure 7, Loop Test = 0

tpd2 Data Propagation Delay RXCLKIN to NRZOUT

Time 90 ns See Figures 4 and 7. Note 2
Loop Test = 0

tpd3 Clock Delay Time 50 ns RXCLKIN to RXCLKOUT

See Figure 8, Loop Test = 0

ts3 RAIS = 0 Set-Up Time 30 ns RAIS to RXCLKIN

See Figure 7

th3 RAIS= 0 Hold Time 30 ns RAIS to RXCLKIN

STATIC CHARACTERISTICS, VDD = 5.0 V

IDD Quiescent Device Current 100 J.lA

Operating Current 4 mA Input Clock Frequency = 2.0MHz

VDD Supply Voltage 4.5 5 5.5 V

VIN Input Voltage 0 0 5.0 V

VIL Input Low Voltage O.S V

VIH Input High Voltage 2 V

VOL Output Low Voltage 0.1 V IOL = 0

VOH Output High Voltage 4.9 V IOH = 0

IOL Output Low Current 1.6 mA VOL=0.4V

IOH Output High Current -1 mA VOH = 4.6 V

IlL Input Low Current -10 J.lA VIL = 0 V

IIH Input High Current 10 J.lA VIH = 5 V

Note 1: The encoded B8ZS OUT are delayed by 8Y, clock periods from NRZIN.
Note 2: The decoded NRZOUT are delayed by 7Y, clock periods from B8ZS IN.

2-7
 XR-T5670

TXCLKIN

NRZIN
-.... TRANSMITTER
ENCODER
...
~

...
+88ZS OUT

-88ZS OUT
~

88ZS/AMI
- ~~

LOOP-TEST

--
+88ZSIN
t it
" " "
-- • ... NRZ OUT
...
-88ZS IN

RXCLK IN
- RECEIVER
DECODER
-'" RXCLK OP
~

--
"" ERROR
.-
I I
ERROR
'" DETECT

...
~

AIS ...
-.. DETECT ~ AIS OUT

- -
RAIS

Figure 1. XR-T5670 Block Diagram

Loop Test

When the Loop Test control input is set high, a test mode is code. If the pulse preceeding the inserted code is a negative
made in which the "+BalSOUT' and "-B8ZS0UT" are in- pulse (-l. the inserted code is 000-+0+-. Bipolar vio-
ternally connected to the decoder inputs. The external lations again occur in the fourth and seventh bit positions
8alS inputs and the "RXCLKIN" are disabled, and the as illustrated in Figure 2.
"TXCLKIN" is used to control the decoder timing. The
"NRlOUT" signals correspond to the "NRlIN" input,
but delayed by approx imately 16 clock periods.
Binary Signal 0 0 0 0 0 0 0 0

B8ZS/AMI BalS Signal +1 0 0 0 +1 -1 0 -1 +1

To operate the XR-T5670 in AMI mode,~the B8ZS/AMI or -1 0 0 0 -1 +1 0 +1 -1

control input is driven low. In this mode, two consecutive
pulses of the same polarity at the decoder inputs will be
Bipolar Code
detected and flagged as an error at the "ER ROR" output.

Definition of B8ZS Code Used in XR-T5670 Transcoder or

With 8aZS coding, each block of eight consecutive zeros is

removed and the B8ZS code is inserted. If the pulse pre- Figure 2. BaZS Code
ceding the inserted code is transmitted as a positive pulse
(+), the inserted code is 000+-0-+. Bipolar violations
occur in the fourth and seventh bit position of the inserted
2-8
XR-T5670

1. . . 1----8%
. CLOCK PERIODS--.....,~·I
TXCLKIN

NRZIN~~ ____________________ ~

+B8ZS0UT ________________________~r_1_______~r_1~_______~

-B8ZS0UT ______________________________________

Figure 3. Encoder Waveforms

~~

•
I~ 7% CLOCK PERIODS---1
TXCLK IN

Vt
+B8ZSIN~~--------LJ~---------LJ

-B8ZS IN

NRZ OUT _______________________ r-1~ ____________________ ~r__L_

Figure 4. Decoder Waveforms

RXCLKIN

E V
+B8ZSIN~--------------~---------------------

WITH ERROR V E
-B8ZSIN-----------LJ~---------LJ~--------~~~-----------

ERROR _____________ r-1~ __________________________ ~r_l~ ______

Figure 5. B8ZS Error Output Waweforms

2-9
 XR-T5670

TXCLKIN

NRZIN

B8ZS OUT

Figure 6. Encoder Timing Relationship

RXCLK IN

B8ZSIN

NRZ OUT

RAIS

Figure 7. Decoder Timing Relationship

RXCLK IN

RXCLK OUT \ __1

Figure 8. RXCLK IN to RXCLK OUT Relationship

2-10
 XR-T5675

Dual Line Driver

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5675 is a bipolar monolithic dual line driver

Vee A2 B2 D2

designed to drive PCM lines up to a 10 Mbits/s rate. The

•
device is powered from a single 5 V ± 5% source. Its current
consumption is 14 mA typical and the output can be
pulled up to 20 V dc. The XR-T5675 is packaged in a
standard 8 pin DIL plastic or ceramic package. and its
temperature of operation is between ci°c to +70°C.

FEATURES
50 mA Output Drive Current Capability
Low Current Consumption (18 mA Max.)
High Speed Switching
Dual Matched Driver Outputs
High Output Voltage
TTL or DTL Compatible Inputs

A1 B1 D1 GND
ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T5675CP Plastic 0°,: to +70°C
APPLICATIONS XR-T5675CN Ceramic O°C to +70°C

T1. T1 C. T2. 2048K and 8448K b/s PCM Line Driver SYSTEM DESCRIPTION
LAN Line Driver
Relay Driver Figure 1 contains the Functional Block Diagram of the XR-
LED/Lamp Driver T5675. The circuit consists of two AND logic gates with
their outputs internally connected to the bases of the out-
put transistors. The low level outputs are clamped at 1 VBE
to ground to insure non-saturating" operation for fast
switching.
A B OUTPUT (0)

L L H (OFF)

ABSOLUTE MAXIMUM RATINGS L H H (OFF)

Supply Voltage (VCC) +7.0V H L H (OFF)

Input Voltage (Pin 1.2.6.7) -0.2 V to +VCC
Output Pull-up Voltages (Pin 3.5) +35.0 V H H L (ON)
Power Dissipation
Ceramic 700mW
Plastic 600mW Truth Table - XR·T5675
Storage Temperature -65°C to 150°C H = H Level, L = Low Level

2-11
XR-T5675

ELECTRICAL CHARACTERISTICS
Test Conditions:Vcc = 5.0 V, TA = O°C to +70°C, unless specified otherwise.

SYMBOL PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

VCC Supply Voltage 8 4.75 5.0 5.25 V

VIH High Level Input Voltage 1,2,6,7 2.2 V IOL = 50 mA VOL = 0.95 V
VIL Low Level I nput Voltage 1,2,6,7 0.8 V

IIH High Level Input Current 1,2,6,7 40 J.lA VIH = 2.7 V, Pins 3 & 5 Open

IlL Low Level I nput Current 1,2,6,7 -1.2 mA VIL = 0.4 V, Pins 3 & 5 Open

VOL Low Level Output Voltage 3,5 0.6 0.95 V VIH = 2.2 V, IOL = 50 mA
IOL Low Level Output Current 3,5 50 mA VIH = 2.2 V, VOL = 0.95 V
IOH High Level Leakage Current 3,5 100 J.lA Pins 3 & 5, Pull-up to +20 V

IceH Supply Current Output High 8 3.0 mA Pins 3 & 5 Open

IceL Supply Current Output Low 8 14.0 18.0 mA Pins 3 & 5 Open

SWITCHING CHARACTERISTICS, VCC = 5.0 V ±5%, TA = +25°C

tpLH Propagation Delay,
Low to High 3,5 15 ns

tpHL Propagation Delay,

High to Low 3,5 15 ns
See Figure 2
trise Rise Time 3,5 15 24 ns
I

tfall Fall Time 3,5 10 24 ns

Output Pulse Imbalance 2.5 ns At 50% Output Level

2-12
 XR-T5675

130n
INPUT OUTPUT

PULSE
GENERATOR

T
(Note 1)
C L = 15pF

{NOTE 21
PIN 4
OV

NOTE 1. PULSE GENERATGOR FREQUENCY = 2.0 MHz, ZOUT = 50Q

NOTE 2. CL INCLUDED - PROBE AND JIG CAPACITANCE

~---------250ns--------~

~5.0ns
- - - - - - - 3.0V
INPUT

--------OV

__- - - - +5.0V

OUTPUT

FIGURE 2. AC TEST CIRCUITS AND SWITCHING WAVEFORMS

2-13
 XR-T5675

SAMPLING
CLOCK

n .----~-----l ~;~ELS
D+i/p

D-i/p n n
n
n ----.
n
BIPOLAR
SIGNAL
tr U ~ U

N.A.
I ALLOWABLE
SAMPLING
CLOCKS

*RX IS INTENDED FOR MATCHING LINE

IMPEDANCE, BUT ITS FINAL VALUE MAY
BE DETERMINED BY THE OUTPUT
SIGNAL AMPLITUDE REQUIRED.

D-i/P
RX*

SAMPLING
CLOCK i/P

BIPOLAR
SIGNAL TO LINE

SAMPLING
CLOCK i/P

D +i/P
RX*

IN THE CASE WHERE D+ AND D- ARE HALF WIDTH SIGNALS, PIN 1 AND PIN 7
SHOULD BE TIED TOGETHER AND RETURNED TO +5.0V VIA A 1K RESISTOR

FIGURE 3. XR-T5675 PCM LINE DRIVER APPLICATION CIRCUIT

2-14
 XR-T5680

PCM Line Interface Chip

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5680 is a PCM line interface chip. It consists of

both transmit and receive circuitry in a OIL 18 pin pack-

•
age. The maximum bit rate the chip can handle is 10 M
Bits/s and the signal level to the receiver can be attenuated r-----fl7lTX DATA + 'iP
by -10 dB cable loss at half the bit rate. Total current
consumption is between 27-46 mA at +5.0 V.

FEATURES

Single +5.0 V Supply

Receiver Input Can Be Either Balanced or Unbalanced
Up to 10 MBits/s Operation
TTL Compatible Interface

ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T5680 Ceramic O°C to 70°C

APPLICATIONS
SYSTEM DESCRIPTION
T1, T1C, T148C, T2, 2048 & 8448 KBits/s
PCM Line Interface The incoming bipolar PCM signal which is attenuated and
CPI distorted by the cable is applied to the threshold compara-
OMI tor and the peak detector. The peak detector generates a
DC reference for the threshold comparator for data and
clock extraction. A tank circuit tuned to the appropriate
frequency is added to the later operation. The clock signal,
data + data - all go through a similar level shifter to be
converted into TTL level to be compatible for digital
processing.

I n the transmit direction, the output drivers consist of two

identical TTL inputs with open collector output stages.
The maximum low level current these output stages can
sink is 40.0 mAo With full width data applied to the inputs
ABSOULTE MAXIMUM RATINGS together with a synchronized clock. The output will gene-
rate a bipolar signal when driving a centre-tapped trans-
Supply Voltage +20 V former. A typical circuit diagram to XR-T5680 is shown in
Storage Temperature -65°C to +150°C Figure 1, and the DC characteristics are indicated in the
Operating Temperature O°C to 70°C Electrical Characteristics chart.

2-15
XR-T5680

ELECTRICAL CHARACTERISTICS
Test Conditions: +VCC = 5.0 V. TA = 0° - 70°C. unless specified otherwise.
PARAMETERS MIN TYP MAX UNIT CONDITIONS

DC Supply +4.75 +5.0 +5.25 V

Supp Iy Current 35.0 46.0 mA Output Drivers Opens

Tank Drive Current 1.5 2.0 2.5 mA Measured at Pin 4

*C/ock Output/Low Level 0.4 0.8 V Measured at Pin 8.

'OL = 1.0 mA

*C/ock Output/High Level 3.0 3.6 V Measured at Pin 8

IOH = -400pA

*Data Output/Low Level 0.4 0.8 V Measured at Pins 10.11

IOL = 1.0 mA

*Data Output/High Level 3.0 3.6 V Measured at Pins 10.11

10 H = -400pA

Output Driver/Low Lev~.1 0.6 0.95 V Measured at Pins 13.15

IOL = 40 mA

Output Driver Current S!nk 40 mA Measured at Pins 13.15

VOL = 0.95 V

Output Driver Rise Time 20 25 ns Measured at Pins 13.15

with 150n Pull-up to +5.0 V
CL=15pF

Output Driver Fall Time 20 25 ns Measured at Pins 13.15

with 150n Pull-up to +5.0 V
CL = 15 pF

*These output terminals are LS-TTL compatible.

Figure 2. A recommended Circuit Diagram

2-16
~ l:Xt(IR XR-T5681
Preliminary Information

PCM Transceiver Chip

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5681 is a PCM transceiver chip. It consists of

both transmit and receive circuitry in a CERDIP 18 pin

•
package. The transceiver is designed for short line applica-
tion «-10 dB) such as in digital multiplexed interfacing
and digital PBX environments. The maximum frequency of
operation is 3 MBits/s so it covers T1, T148C, and Eurupe's
2.048 MBit/s PCM system. The device is designed to oper-
ate over the temperature range of O°C to +70°C.

F~ATURES

Single +5.0 V Supply

Receiver Can Accept Either Balanced or Unbalanced Inputs
TTL Compatible Interface
Transmitter and Receiver in One Package

ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T5681 Ceramic O°C to 70°C

SYSTEM DESCRIPTION
APPLICATIONS
The functions of the circuit terminals are defined in the
T1, T148C, and 2.048 MBits/s PCM Line Interface
Functional Block Diagram. At the receive direction, the
CPI
incoming bipolar signal which has been attentuated and dis-
DMI
torted by the cable is applied to the input of the peak de-
tector. The variable threshold voltage produced by the
peak detector controls the data comparator for P and
N rails signal extractions. Timing information is obtained
by means of a full wave rectifier and an L-C resonant
circuit tuned at the appropriate frequency. All data and
clock outputs are LSTTL compatible.

At the transmitter, the outputs have two identical non-

saturating open collector stages which can drive the out-
put line transformer directly with a maximum current of
40 mA. Full width, TTL compatible, P and N rail signals
ABSOLUTE MAXIMUM RATINGS at the inputs and a 50% duty cycle TTL clock are needed
to form the bipolar line signal at the secondary of the
Supply Voltage +20V transformer. The output signal conforms to CCITT G.703
Storage Temperature -65°C to +150°C recommendation. A circuit diagram connected for 2048 K
Operating Temperature O°C to 70°C bits/s line interface application is shown in Figure 1.

2-17
XR-T5681

ELECTRICAL CHARACTERISTICS
o
Test Conditions: +VCC = 5.0 V. TA = OoC - +70 C. unless specified otherwise.

PARAMETERS MIN TYP MAX UNIT CONDITIONS

DC Supply +4.75 +5.0 +5.25 V

Supply Current 35.0 46.0 mA TX Drivers Open

Tank Drive Current 1.5 2.0 2.5 mA Measured at Pin 9.

Clock O/P/Low Level 0.3 0.8 V Measured at Pin 13. IOL = 1.0 mA
Clock O/P/High Level 3.0 4.3 V Measured at Pin 13. IOH = 400,uA
Data O/P /Low Level 0.4 0.8 V Measured at Pins 10.12. IOL = 1.0 mA
Data O/P/High Level 3.0 4.5 V Measured at Pin 10.12. IOH = 400,uA
Transmitter O/P/Low Level 0.6 0.95 V Measured at Pin 13.15. IOL = 40 mA

Transmitter O/P/Current Sink 40 mA Measured at Pin 13.15. VOL = 0.95V

Transmitter O/P/Rise Time 20 30 ns Measured at Pin 13.15 with 150n
Pull-up to +5.0 V. CL = 15 pF

Transmitter O/P/Fall Time 20 30 ns Measured at Pin 13.15with 150n

Pull-up to +5.0 V. CL = 15 pF

+5.DV
a.0CIt

r---------==~::..-I_ RX
r-------!~~-O/P

R=2OI(

D·
TX.I/p_.::D~+_ _ _ _ _ _ _ _ _ _ --I
CLOCK

T1 .----o---+--~---------IrANK

~~311 ~.'~f
+5.011
390 CO\

*Q OF rANK CIRCUIT = 80-100

Tl· AlE input tr.nsformer part 0.315-0765

link Coil- AlE pM1no. 416-0804 (only termin.I' &: 4 being ..cI1.
MAX Input voltlge to T1 primary· 3 Vp or 6 Vp·p It 5.0 V supply.
ADJUST l until min. cloc:k jitter is obtJined.t pin 13.
T2·AIEportno.318~

Figure 2. Circuit Connection Diagram for 2048Kbits/s operating

2-18
 XR-T5682

Voltage Controlled Crystal Oscillator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5682 is a bipolar monolithic voltage controlled

crystal oscillator IC designed for general purpose crystal

•
phase locked loop (Pll) and particularly in data rate con-
version, jitter reduction, and down multiplexing applica- PHASE
tions in PCM systems operating at 1.536, 1.544 and 2.048 SHIFT COUPLE
M/bits/s data rates. It is packaged in 18 pin CERDIP and
CRYSTAL
can operate from 4.75 to 5.25 volts. TERMINAL 2

CRYSTAL
TANK
TERMINAL 1

PHASE SHIFT
liP 2

PHASE SHIFT
liP 1

VCO
TIMING RES.
CONTROL 2

VCO
CONTROL 1

GND DUTY CYCLE

(OV) SET RESISTOR

FEATURES ORDERING INFORMATION

Single +5V Circuit Part Number Package Operating Temperature

Built-in Programmable Analog Divider XR-T5682 Ceramic O°C to 70°C
TTL Compatible Clock Signal Output
Adjustable Duty Cycle of the Output Clock Squarewave
Uses Phase Lead/lag Capacitor and I nductor Instead
of a Varactor Diode to Control Frequency

SYSTEM DESCRIPTION

The XR-T5682 uses phase lead and lag components rather

than a varactor diode to contro I the freq uency of osci Ila-
tions. A filter crystal, at least twice the desired frequency,
is used in series oscillation mode. The generated signal
is fed back through a phase shift control circuit to sustain
and change the frequency of oscillations. An analog divide
by N circuit which consists of an astable mutlivibrator
is provided to obtain the desired clock rate. The frequency
ABSOLUTE MAXIMUM RATINGS of oscillations of the astable multivibrator can be changed
externally by means of a resistor and a capacitor to obtain
Supply Voltage +10V the required number of divisions. An ECl to TTL conver-
Storage Temperature -65°C to 150°C tor circuit is designed to provide a TTL compatible clock
Operating Temperature O°C to 70°C signal, the duty cycle of which is adjustable with an exter-
lead Soldering (10 Seconds) 300°C nal resistor tied either to VCO or Ground.

2-19
XR-T5682

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°e at a supply voltage of Vee = 4.75 V to 5.25 Voe, unless otherwise specified.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

Vee Supply Voltage 4.75 5.0 5.25 V

ICC Supply Current 20 35 45 mA

VREF Referene Voltage 2.5 2.7 2.9 V Pin 13

VREF Reference Voltage 2.5 2.7 2.9 V Pin 14

VREF Reference Voltage 2.5 2.7 2.9 V Pin 1 and 1a

VOH Output High Voltage 4 V Pin 8

VOL Output Low Voltage 0.8 V

ITANK Tank Circuit Current 1.4 1.73 2.3 mA Pin 15

ITIMING 1 3 mA Pin 7

GC VCO Convertion Gain 350 650 1000 Hz/V

Clock Duty Cycle 25 50 75 % Adjustable

DUTY CYCLE
+Roc SeT SETIING RESISTORS

XR-T5682

L------ol"l1.544MHz veo O/P

6.1767MHz

Figure 1. Typical 1.544 M/bits/s Application Circuit

2-20
 XR-T5682

5V

SN74LS74

4.7K

•
1K~---"'4

Q Q
TO FI LTEFl INPUT

Q 6 Q 8

13

-liP veo
O/P

Figure 2. Recommended Phase Detector

R,
Q O--~""~-o----e--O TO PIN 11

liP O/P

Q o--....I\,fV\I--...-~--O TO PI N 12

Figure 3. Phase Lag Filter

2-21
 XR-T5750

PCM Line Receiver & Clock Recovery Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5750 is a monolithic bipolar IC designed for PCM

line receiver applications operating at Tl, Tl48C, Tl C and
2 Mbitls data rates. It provides all the active circuitry re- ALBO
(;ND CLOCK
quired to perform automatic line build out (ALBa), thres- SUBSTRATE DRIVE
GND
hold detection, positive and negative data and clock recov-
ery using a crystal filter. ALBO ALBO
PORT 1 CONTROL

Clock recovery using an LC tank circuit instead of a crys- ALBO

CLOCK
AMPLIFIER
tal filter is also available as XR-T5650. PORT 2 INPUT

CLOCK
PREAMPLIFIER AMPLIFIER
·VE INPUT
fEATURES INPUT

PREAMPLIFIER VCC
On Chip Positive and Negative Data, Clock Recovery .VE INPUT

Less than 10 ns Sampling Pulse Over the Operating Range

Double Matched ALBO Ports PREAMPLIFIER
·VE OUTPUT
CLOCK
OUTPUT
Single 5.1 V Power Supply
2 M Bitls Capability PREAMPLIFIER
PHASE
SHIFTED
CLOCK
Clock Recovery using Crystal Filter ·VE OUTPUT
INPUT

DIGITAL CLOCK
GROUND

APPLICATIONS -1 DRIVER

T1 PCM Line Receiver

:rl48C LIne Receiver
T1C PCM Line Receiver (requires external amplifier)
General Purpose Bipolar Line Receiver
HDB3 Line Receiver SYSTEM DESCRIPTION
B8ZS Line Receiver
The X R-T5750 is designed for interfacing Tl, T148C and
2 Mbitls PCM carrier lines on plastic or pulp insulated
ABSOLUTE MAXIMUM RATINGS cables. It can also be used at T1C rate (3.152 M bit/s) with
external gain. Since it outputs plus and minus ones on a
bipolar pulse stream together with the clock, it can be used
Storage Temperature -65°C to +150°C to interface systems having different line codes like AMI,
Operating Temperature -40° C to +85° C AMI-BaZS or AMI-HDB3.
Supply Voltage -0.5 to +10 V
Supply Voltage Surge (10 ms) +25 V The XR-T5750 is a modified version of XR-T5720 PCM
Input Voltage (except Pins 2,3.4,17) -0.5 to 7 V repeater IC. It contains all the active circuitry needed to
Input Voltage (Pins 2,3.4,17) -0.5 to +0.5 V build a PCM line receiver up to 6300 ft. cable length. The
Data Output Voltage (Pins 10,11 ) 20 V preamplifier, the clock amplifier, threshold detectors,
Voltage Surge (Pins 5,6,10,11) (10 msec only) 50V data latches and output drivers are sim ilar to the ones on
X R-T5720. Clock extraction is done by means of a crystal
filter circuit.

In addition to plus and minus one outputs, a synchronous

ORDERING INFORMATION clock signal is made available at Pin 11 by deleting one of
the ALBO ports on XR-T5720 thus leaving two matched
Part Number Package Operating Temperature ALBO ports. All outputs have high current open collector
XR-T5750 Ceramic -40°C to +85°C transistors.

2-22
 XR-T5750

ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 5.1 V ± 5%, TA = 25°C, unless specified otherwise.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

Supp Iy Current 24 30 mA ALBO Off

Clock & Data Output
Vpull- up = 15 V

•
Output Leakeage Current 0 100 p.A
Amplifier Pin Voltages 2.4 2.9 3.4 V At DC Unity Gain
Amplifier Output
Offset Voltage -50 0 50 mV Rs = ~.2 kn
Voltage Swing 2.2 V Measured'Differentially from
Pin 7 to Pin 6
Ampl ifier Input
Bias Current 5 p.A
ALBO on Current 3 mA
Drive Current 1 mA

AC CHARACTERISTICS

Pre Amplifier
AC Gain @ 1 MHz 50 dB
Input Impedance 20 kn
Output Impedance 200 n
Clock Amplifier
AC Gain 32 dB
-3 dB Bandwidth 10 MHz
Delay 10 ns
Output impedance 200 n
ALBO
Off Impedance 20 kn
On Impedance 25 n

CLOCK, DATA OUTPUT BUFFERS RL = 130n, Vpull- up = 5.1 V ± 5%

Rise Time 30 ns
Fall Time 30 ns
Output Pulse Width 244 ns
Sample Pulse Width 10 ns
VOL 0.7 V
IL sink 35 mA

THRESHOLDS

ALBO 1.4 1.5 1.6 V

Clock Drive Current Peak 1.0 mA At Vo = VALBO Threshold
CLOCK THRESHOLD

% of ALBO 63 68 75 %

DATA THRESHOLD

%of ALBO 40 46 52 %

2-23
 ~:u
5.1V .111

lK .111

-::-
5.1V
1111

220n 220n
1:2

T5750

I\)

~
300n

-=- CLOCK DIP

-l's DIP

1's alP
><
:tI
5.1V I
-t
T5750 1.544 M BITS/S HIGH Q PCM LINE RECEIVER APPLICATION CIRCUIT en
~
en
o
 Section 2 - Telecommunication Products
Repeaters . . . . . . . . . . . . . . . . . . . . . . 2-25
XR-C240 Monolithic PCM Repeater 2-26 •
XR-C262 High Performance PCM Repeater . 2-28
XR-C262Z High Performance PCM Repeater 2-30
XR-C277 Low Voltage PCM Repeater . . . . 2-32
XR-C587/C588 T1C PCM Repeater Chip Set . 2-34
XR-T5600/T5620 T1, T148C & 2 Mbitls PCM Line Repeater 2-40
XR-T5700IT5720 T1, T148C & 2 Mbitls PCM Line Repeater 2-50

2-25
 XR-C240

Monolithic PCM Repeater

GENERAL DESCRIPTIDN FUNCTIONAL BLOCK DIAGRAM

The XR-C240 is a monolithic repeater circuit for Pulse-

Code Modulated (PCM) telephone systems. It is designed to ALBO
OUTPUT
operate as a regenerative repeater at 1.544 Megabits per
second (Mbps) data rate on Tl-type PCM I ines_
PREAMP!
The XR-C240 monolithic IC is packaged in a hermetic 16- INPUTS
Pin DIP package, and is designed to operate over a temper-
ature range of -40°C to +85°C. It contains all the basic
functional blocks of a regenerative repeater system including
Automatic Line Bu ild-Out (A LBO) and equal ization, and is PREAMP!
OUTPUTS
insensitive to reflections caused by cable discontinuities.

Compared to conventional repeater designs using discrete

GND
components, the XR-C240 monolithic repeater IC offers
greatly improved reliability and performance, along with
significant savings in power consumption and system cost. v· = 4.3V

1+) DRIVER
OUTPUT

FEATURES
SYSTEM DESCRIPTION
Contains all Active Components of PCM Repeater
On-Chip ALBO Port The XR-C240 contains all the active circuits required to
High-Current Output Drivers build one side of a T1 or 2 M bit/s PCM repeater. Tl is the
Low-Power Consumption most widely used PCM transm ission system, operating at
Increased Reliability over Discrete Designs 1.544 M bit/so It can operate on either pulp or plastic insu-
2 Megabit Operation Capability lated twisted pair cables. Although the cable gauge may
vary, the total cable loss should not exceed 36 dB at 772
kHz. For a 22 gauge pulp insulated cable and a bit error
rate (BER) of less than 10- 6, the max allowable repeater
to repeater spacing is about 6300 feet.
APPLICATIONS
Bipolar PCM signal is attenuated and dispersed in time
PCM Repeater for Tl Systems
as it travels along a transmission cable. This signal, when
PCM Repeater for 2 M Bit/s Systems
received, is amplified and reconstructed by the preamp-
lifier automatic line build out (ABLOI. clock and data
threshold detector circuits contained within the XR-C240.
Amplitude equalization and frequency spectrum shaping is
ABSOLUTE MAXIMUM RATINGS achieved through the variable impedance of the ALBO
ports and its associated ALBO network.
Storage Temperature -65°C to +150°C
Operating Temperature _40°C to +85°C Incoming pulse stream is full wave rectified and timing
Supply Voltage -0.5 to 10 V information is extracted by the clock threshold detector.
Input Voltage (Except Pin 1,16) -0.5 to +7 V Clock recovery is then achieved by driving an injection
Input Voltage (Pin 7,16) -0.5 to +0.5 V locked oscillator tuned to 1.544 MHz. The oscillator'S
Data Output Voltage (Pin 8,9) +20 V sinusoidal waveform is amplified and phase shifted by 90
Voltage Surge (Pin 2,3,8,9) (10 msec only) 50V degrees with the help of a capacitor between Pins 11
and 12.

Data is sampled and stored in the output data latches by

ORDERING INFORMATION an internally generated sampling pulse. Buffer drivers are
then enabled to produce precisely timed output pulses
Part Number Package Operating Temperature whose width and time of occurence are controlled by the
XR-C240 Ceramic -40°C to +85°C regenerated clock signal.

2-26
XR-C240

ELECTRICAL CHARACTERISTICS
(Measured at 25°C with V++ = 8.2V, V+ = 4.3V, unless specified otherwise.)

LIMITS
PARAMETERS UNIT CONDITIONS
MIN. MAX.

Supply Voltage:
V++ 7.79 8.61 V Measured at Pin 10
V+ 4.085 4.515 V Measured at Pins 7 and 15

Supply Current:
IA 1.1 2.5 mA
IS 6 11 mA Supply == 8.2V
Total Current 7.9 13.5 mA

Preamplifier
Input Offset Voltage, VOS 15 mV
Open Loop Differential Ga,in, AO 50 54 dB

Input Sias Current, IS 4 fJ.A

Input Offset Current, lOS 2 fJ.A
Input Impedance, Rin 50 kn

Comparator Thresholds
Peak Detector (A LSO) Threshold ±1.3 ±1.6 V Measured Differentially Across Pins 4 and 5
Full-Wave Rectifier Threshold ±0.9 ±1.15 V
Data Threshold ±0.28 ±0.48 V

Clock Extractor Section

Tank Drive Impedance 50 kn At Pin 14
Tank Drive Current
"Zero" Signal Current 12 24 fJ.A
"One" Signal Current 80 220 p.A
Recommended Tank Q 100
Phase Shifter Offset Voltage -18 +18 mV Voltage applied to Pins 7 and 14 to reduce
differential voltage across Pins 11 and 12 to zero.
Output Drive Section
Voltage levels referenced to Pin 7
Output Voltage Swing 3.0 V RL == 100n
Low Output Voltage 0.65 0.95 V Referenced to Pin 7, IL = 30 mA
Output Leakage Current 50 p.A
Output Pulse
Maximum Pulse Width Error ±30 ns
Rise and Fall Times 80 ns

2-27
 XR·C262

High·Performance PCM Repeater

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
XR-c282
The XR-c262Is a high-performance monolithic repeater
IC for pulse-code modulated (PCM) telephone lines. It is PR~ 1

designed to operate as a regenerative repeater at 1.544

Megabits per second (Mbps) data rates on T1-type PCM
lines.
-SIGNALIN 3
The XR-C262 operates with a Single 6.8 volt power sup-
ply, and with a typical supply current of 13 rnA. It pro-
vides bipolar output drive with hlgh-current handling ca-
pability. The clock-extractor section of XR-C262 uses
the resonant-tank circuit principle, rather than the
+SIGNAI. IN 5
Injection-locked oscillator technique used in earlier
monolithic repeater designs. The bipolar output drivers
are designed to go to their "off" state automatically.
when there is no Input signal present.

FEATURES
Contains all Necessary Active Components
of a PCM Repeater
Uses L-C Tank for Clock Recovery SYSTEM DESCRIPTION
Low-Voltage Operation (6.8 volts)
Low-Current Drain (13 rnA, typical) The XR-C262 contains all the active functions required
High-Current Bipolar Output Drivers to build one side of a T1 or 2 M bitls PCM repeater. T1 is
On-Chip ALBO Equalizer the most widely used PCM transmission system, oper-
Automatic Zero-Input Shutdown ating at 1.544 M blt/s. It can operate on either pulp or
Increased Reliability OVer Discrete Designs plastic Insulated twisted pair cables. Although the ca-
2 Megabit Operation Capability ble gauge may vary, the total cable loss should not ex-
ceed 36 dB at 772 kHz. For a 22 gauge pulp Insulated
cable and a bit error rate (BER) of less than 10- 6, the
APPLICATIONS max allowable repeater to repeater spacing Is about
6300 feet.
PCM Repeater for T1 Systems
Repeater for 2 Megabit PCM Systems Bipolar PCM signal Is attenuated and dispersed in time
as It travels along a transmission cable. This signal,
when received, Is amplified and reconstructed by the
ABSOLUTE MAXIMUM RATINGS peamplifier automatic line build out (ALBO), clock and
data threshold detector circuits contained within the
Storage Temperature -65°C to + 1S0°C XR-C262. Amplitude equalization and frequency spec-
Operating Temperature - 40°C to + 8SoC trum shaping is achieved through the variable Imped·
Supply Voltage -O.S to +10 V ance of the ALBO port and Its associated ALBO net-
Input Voltage (Except Pin 6,7) -O.S to +7 V work.
Input Voltage (Pin 6,7) -O.S to +O.S V
Data Output Voltage (Pin 9,11) +20V Incoming pulse stream Is full wave rectified and timing
Voltage Surge (Pin 3,S,9, 11) (10 msec only) SOV Information is extracted by the clock threshold detec·
tor. Clock recovery is then achieved by pulsing a tank
circuit tuned to 1.544 MHz.
ORDERING INFORMATION Data is sampled and stored In the output data latches.
Part Number Package Operating Temperature Buffer drivers are then enabled to produce precisely
timed output pulses whose width and time of occur·
XR-C262 Ceramic - 40°C to + 8S 0 C rence are controlled by the regenerated clock signal.

2·28
 XR·C262
ELECTRICAL CHARACTERISTICS
Tast Conditions: + Vee = 6.8 V, TA = - 40°C to + 85°C.

LIMITS
PARAMETERS MlN TYP MAX UNITS CONDITIONS
Supply Current
Digital Current 7 10 13 rnA Measured at Pin 12
Analog Current rnA Measured at Pin 8

•
2 3.5 5
Total Current 13 17 rnA
Preamplifier
Input Offset. Voltage -15 +15 mV Measured between
Pins 3 and 5
DC Gain 60 69 74 dB
Output High Level 4.3 V Measured at Pin 1
Output Low Level 0.5 V Measured at Pin 1
Clock Recovery Section
Clock Drive Swing (High) 5.1 V Measured at Pin 13
Clock Drive Swing (Low) 3.8 V Measured at Pin 13
Clock Bias 3.8 4 4.2 V Measured at Pin 15
Clock Source Input
Current 0.5 4 p.A Measured at Pin 16
Comparator Thresholds Measured at Pin 1
relative to Pin 14
ALBO Threshold 0.75 0.9 1.1 V
Clock Threshold 0.323 0.4 0.517 V
Data Threshold 0.323 0.4 0.517 V
Internal Reference Voltages
Reference Voltage 5.2 5.45 5.55 V Measured at Pin 2
Divider Center Tap 2.6 2.78 2.85 V Measured at Pin 14
ALBO Section
Off Voltage 10 75 mV Measured at Pin 7
On Voltage 1.2 1.7 V Measured at Pin 7
On Impedance 15 0 Measured at Pin 7
Filter Drive Current 0.7 1 1.5 rnA Drive current available
at Pin 6
Output Driver Section Measured at Pins 9 and 11
Output High Swing 5.9 6.8 V AL = 4000
Output Low Swing 0.6 0.7 0.9 V IL = 15mA
Leakage Current 100 p.A Measured with output
in off state
Output Pulse Width 294 324 354 nsec
Output Aise Time 100 nsec
Output Fall Time 100 nsec
Pulse Width Unbalance 15 nsec

2-29
 XR-C262Z

High-Performance PCM Repeater

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-C262Z is a high-performance monolithic repeater

IC for pulse-code modulated (PCM) telephone systems. It is PREAMP
OUT
designed to operate as a regenerative repeater at 1.544
Megabits per second (Mbps) data rate on T1-type PCM
lines.

The X R-C262Z operates with a single 6.8 volt power - SIGNAL

supply, and with a typical supply current of 13 mA. It IN
provides bipolar output drive with high-current handlinq
capability. The clock-extractor section of XR-C262Z uses ANALOG
GROUND
the resonant-tank circu it principle, rather than the injec-
tion-locked oscillator technique used in earlier monolithic DIGITAL
+ SIGNAL
repeater designs. The bipolar output drivers are designed to IN Vee
go to their "off" state automatically, when there is no
input signal present. ALBO - DATA
FILTER OUT

FEATURES ALBO DIGITAL

TAP GROUND

Contains all Necessary Active Components + DATA

ANALOG
of a PCM Repeater Vee OUT
Uses L-C Tank for Clock Recovery
Low-Voltage Operation (6.8 voltsl
Low-Current Drain (13 mA, typicall
High-Current Bipolar Output Drivers SYSTEM DESCRIPTION
On-Chip ALBO Port
Automatic Zero-I nput Shutdown The XR-C262Z contains all the active functions required to
Increased Reliability Over Discrete Designs build one side of a T1 or 2 M bit/s PCM repeater. T1 is the
2 Megabit Operation Capability most widely used rCM transmission system, operating at
Pin-to-Pin Compatible with XR-C262 with Improved 1.544 M bit/so It can operate on either pulp or plastic insu-
Switching Characteristics lated twisted pair cables. Although the cable gauge may
vary, the total cable loss should not exceed 36 dB at 772
kHz. For a 22 gauge pulp insulated cable and a bit error
APPLICATIONS rate (BER) of less than 10- 6 , the max allowable repeater to
repeater spacing is about 6300 feet.
PCM Repeater for Tl Systems
PCM Repeater for 2 M Bit/s Systems Bipolar PCM signal is attenuated and dispersed in time
as it travels along a transmission cable. This signal, when
received, is amplified and reconstructed by the preampli-
ABSOLUTE MAXIMUM RATINGS fier automatic line build out (ALBO). clock and data
threshold detector circuits contained within the X R-C262Z.
Storage Temperature -65°C to +150°C Amplitude equalization and frequency spectrum shaping is
Operating Temperature -40°C to +85°C achieved through the variable impedance of the ALBO
Supply Voltage -0.5 to +10 V ports and its associated ALBO network.
Input Voltage (Except Pin 6.7) -0.5 to +7 V
Input Voltage (Pin 6.7) -0.5 to +0.5 V Incoming pulse stream is full wave rectified and timing
Data Output Voltage (Pin 9,111 +20 V information is extracted by the clock threshold detector.
Voltage Surge (Pin 3,5,9,11) (10 msec only) 50 V Clock recovery is then achieved by pulsing a tank circuit
tuned to 1.544 MHz.

ORDERING INFORMATION Data is sampled and stored in the output data latches. Buf-
fer drivers are then enabled to produce precisely timed out-
Part Number Package Operating Temperature put pulses whose width and time of occurence are control-
XR-C262Z Ceramic -40°C to +85°C led by the regenerated clock signal.

2-30
XR-C262Z

ELECTRICAL CHARACTERISTICS
Test Conditions: +VCC "" 6.8 V, TA "" -40°C to +85°C, unless specified otherwise.

PARAMETERS MIN TYP MAX UNIT CONDITIONS

SUPPLY CURRENT

Digital Current 6 10 13 mA Measured at Pin 12

•
Analog Current 1.5 3.5 5 mA Measured at Pin 8
Total Current 13 15 mA

PREAMPLIFIER

Input Offset Voltage -15 +15 mV Measured betweeQ Pins 3 & 5

Open Loop Gain 58 69 76 dB
Output High Level 4.3 V Measured at Pin 1
Output Low Level 0.8 V Measured at Pin 1

CLOCK RECOVERY SECTION

Clock Drive Swing (High) 5.1 V Measuredat Pin 13

Clock Drive Swing (Low) 4.0 V Measured at Pin 13
Clock Bias 3.8 4 V Measured at Pin 15
Clock Source I nput Cur~'ent 0.5 4 IlA Measured at Pin 16

COMPARATOR THRESHOLDS

A LBO Threshold 0.75 0.9 1.1 V Measured at Pin 1 relative to Pin 14

Clock Threshold 0.323 0.4 0.517 V
Data Threshold 0.323 0.4 0.517 V

INTERNAL REFERENCE VOLTAGES

Reference Voltage 5.0 5.45 5.65 V Measured at Pin 2

Divider Center Tap 2.5 2.78 2.85 V Measured at Pin 14

ALBO SECTION

Off Voltage 10 75 mV Measured at Pin 7

On Voltage 1.2 1.7 V Measured at Pin 7
On Impedance 15 n Measured at Pin 7
Filter Drive Current 0.7 1 3 mA Drive Current available at Pin 6

OUTPUT DR IVER SECTION Measured at Pins 9 & 11

Output High Swing 5.9 6.8 V RL"" 400n

Output Low Swing 0.5 0.7 1.0 V IL"" 15 mA
Leakage Current 100 IlA Measured with output in off state
Output Pulse Width 298 324 350 nsec
Output Rise Time 80 nsec
Output Fall Time 80 nsec
Pulse Width Unbalance 15 nsec

2-31
 XR-C277

Low-Voltage PCM Repeater

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-C277 is a monolithic repeater circuit for Pulse-

ALBO
Code Modulated (PCM) telephone systems. It is designed to OUTPUT

operate as a regenerative repeater at 1.544 Megabits per

second (Mbps) data rate on T1-type PCM lines. It is pack-
aged in a hermetic 16-Pin CERDIP package and is designed
to operate over a temperature range of -40°C to +85°C. It
PREAMP
INPUTS lJ
contains all the basic functional blocks of a regenerative
repeater system, including Automatic Line Build-Out
(ALBO) and equalization, and is insensitive to reflections
caused by cable discontinuities. PREAMP
OUTPUTS \
I
The key feature of the XR-C277 is its ability to operate
with low supply voltage (6.3 volts and 4.3 volts) with a ANALOG
GROUND
supply current of less than 13 mA. Compared to conven-
tional repeater designs using discrete components, the
XR-C277 monolithic repeater IC offers greatly improved GND

reliability and performance, along with significant savings

(+1 DRIVER
in power consumption and system cost. OUTPUT

The XR-C277-5F is an improved version of XR-C277 with

an internal feedback that improved the phase gain margin most widely used PCM transm ission system, operating at
which enables the system to be more stable and less sensi- 1.544 M bit/s. It can operate on either pulp or plastic insu-
tive to PC board layouts. lated twisted pair cables. Although the cable gauge may
vary the total cable loss should not exceed 36 dB at 772
Other versions of the XR-C277-5F are XR-C277-F and XR- kHz. For a 22 gauge pulp insulated cable and a bit error
C277-Fl. XR-C277-F is an AC tested device of XR-C277- rate (BER) of less than 10-6 the max allowable repeater to
repeater spacing is about 6300 feet.
5F at 2Mbit while XR-C277-F L is the equivalen at 1.544
Mbit. Bipolar PCM signal is attenuated and dispersed in time as
it travels along a transmission cable. This signal, when re-
FEATURES ceived, is amplified and reconstructed by the preamplifier
automatic line build out (ALBO), clock and data threshold
Contains all the Active Components of a PCM Repeater detector circuits contained within the XR-C277. Amplitude
Low-Voltage Operation (6.3 volts) equalization and frequency spectrum shaping is achieved
Low-Power Dissipation (13 mAl through the variable impedance of the ALBO port and its
On-Chip ALBO Port associated ALBO network.
High-Current Outp ut Drivers
Incoming pulse stream is full wave rectified and timing
Increased Reliability over Discrete Designs
2 Megabit Operation Capability information is extracted by the clock threshold detector.
Pin-Compatible with XR-C240 Clock recovery is then achieved by pUlsing a tank circuit
tuned to 1.544 MHz. Either injection locking or pulsed
ABSOLUTE MAXIMUM RATINGS tank type clock extraction are possible with the XR-C277.
By grounding Pin 13, the circuit works in the injection
Storage Temperature -65°C to +150 C
o lock mode. Floating (open) Pin 13 switches the XR-C277
Operating Temperature -40°C to +85°C to an pulse tank mode. The oscillator's sinusoidal waveform
Supply Voltage is amplified and phase shifted by 90 degrees with the help
-0.5 to +10 V
Input Voltage (Except Pin 1,16) of a capacitor between Pins 11 and 12.
-0.5 to +7 V
Input Voltage (Pin 1,16) -0.5 to +0.5 V Data is sampled and stored in the output data latches by
Data Output Voltage (Pin 8,9) 20V an internally generated sampling pulse. Buffer drivers are
Voltage Surge (Pin 2,3,8,9) (10 msec only) 50V then enabled to produce precisely timed output pulses
whose width and time of occurence are controlled by the
SYSTEM DESCRIPTION regenerated clock signal.

The XR-C277 contains all the active circuits required to

build one side of a T1 or 2 M bitls PCM repeater. T1 is the

2-32
 XR-C277
ELECTRICAL CHARACTERISTICS
Test Conditions: +25°C, V++ = 6.3V ±5%, V+ = 4.4V ±5%, unless specified otherwise.

LIMITS
PARAMETERS CONDITIONS
MIN. TYP. MAX. UNITS

Supply Current
IA 3.5 mA Measured at Pin 10

•
IB 7.5 mA Measured at Pin 15
Total Current 8 11 13 mA (lc + IB)

Preamplifier
Input Offset Voltage 1.5 15 mV Measured at Pins 2 and 3
Input Bias Current 0.3 4 fJA Measured at Pins 2 and 3
Voltage Gain 44 48 51 dB Single-ended Gain
Prea!11P Output Swing Measured at Pins 4 and 5
High Swing 3.45 3.6 3.75 V Maximum Voltage Swing
Low Swing 1.25 1.4 1.55 V Minimum Voltage Swing
Output DC Level 2.47 2.55 2.72 V

A LBO Section
ALBO "Off" Voltage 10 75 mV Measured from Pin 1 and 16 to
Ground
ALBO "On" Voltage 0.6 0.87 1.1 V Measured at Pin 1
ALBO "On Voltage 1.2 1.5 2.1 V Measured at Pin 16
ALBO Threshold 1.35 1.50 1.65 V Measured Differentially
Across Pins 4 and 5
Differential Threshold -75 +75 mV Threshold Difference for
Polarity Reversal at Pins 4 and 5
ALBO "On" Impedance 5 10 fl Measured at Pin 1
ALBO "Off" Impedance 20 50 kfl Measured at Pin 1

Comparator Thresholds
Clock Threshold 68 73 78 % % of ALBO Threshold
Data Threshold 47 50 53 % % of ALBO Threshold

Clock Extractor
Oscillator Current 10 14 20 fJA
Tank Drive Impedance 50 kfl
Recommended OSC. 0 100
linjection/IOSC. 6.0 7 7.5 Ratio of Current 01 B to
Current in 01A
Output Driver
Low Output Voltage 0.65 0.75 0.95 V Measured at Pins 8 and 9
IL=15mA
Output "Off" Current 5 100 fJA Vout = 20V
Output Pulse
Max. Pulse Width Error ±30 n sec
Rise'Time 80 n sec
Full Time
I 80 n sec

APPLICATIONS ORDERING INFORMATION

PCM Repeater for Tl Systems Part Number Package Operating Temperature

PCM Repeater for 2 M Bit/s Systems XR-C277 Ceramic -40°C to +85°C
XR-C277-5F Ceramic -40°C to +85°C
XR-C277-F Ceramic -40°C to +85°C
XR-C277-FL Ceramic _40° C to +85° C
2-33
 ~R XR·C587 I C588

T 1C PCM Repeater Chip Set

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS

The IC pair, XR-C587 and XR-C588, provides all the active

circuitry needed to form one side of a Tl C PCM Repea-
..MP
ter (3.152 MBits/sec). Each chip is packaged in a 16-Pin OUTPUT Vcc

CERDIP package, with an operating temperature range of

AMP
a.6
- 40°C to +85°C. The supply voltage range is 6.0 to 6.8 INVERTING
COLLECTOR
INPUT
VDC' with a typical supply current for the pair of 16 mAo
AMP
NONINVERTING 0<6
BASE
INPUT
The XR-C587 contains an amplifier, three AlBO ports, and
an npn transistor. The amplifier is a modified version of the AMP 0<&
GND EMITTER
amplifier in Exar's XR-C262 Tl repeater chip. This ampli-
fier has its own ground pin for isolation, as well as for elim- ALBO
DRIVE ALBO
inating the amplifier current drain if only the XR-C587 INPUT PORT 3

AlBO diodes and/or the transistor are used. Each of the

..LBOGND ..LIlO
three ALBO ports has a separate ground and one common AND PORT 3
SUBSTRATE OND
drive input. Any number, up to three, can be used while
eliminating current in any not used. The npn transistor is ALBO
PORT'
ALBO
PORT 2
GND
provided for incidental uses.
ALBO ALBO
PORT' PORT 2
The XR-C588 contains a preamplifier, an AlBO drive GND

output, a voltage reference, comparators, a clock recovery

circuit, ECl latches and two output drivers. The XR-C588
is a modified version of XR-C262 for T1C performance.
The amplifiers in the XR-C587 and XR-C588 are the same.
The clock driver output is modified to drive a crystal and
has higher gain. Both inputs to the clock amplifier are
available. The clock amplifier may be biased, both from the
V.O
AMPLIFIER
OUTPUT
-,
CLOCK
AMPLIFIER
center tap voltage (Pin 14). and the clock bias voltage INPUTS

(Pin 7).
VZREF
ZENER VOLTAGE
--.J
PREAMP VCT
INPUT AMPLIFIER BIAS
Two options for the clock comparator threshold voltage (-) VOLTAGE

are provided. Option 1 is 65% of AlBO threshold, and ANALOG VCDO

CLOCK DRIVE
Option 2 is 50% (the same as C262). GROUND
OUTPUT

PREAMP VCD
FEATURES INPUT
(-)
DIGITAL
SUPPLY

IADO
Modified Preamplifier with Improved Phase Margin ALBO DRIVE
-DATA
OUTPUT
CURRENT
Separate Grounds for Preamplifier and AlBO Ports
VeB
Crystal Drive Capability for Hioh Q Operation CLOCK BIAS DIGITAL
VOLTAGE GROUND
Optional Clock Comparator Threshold Levels (50% & 65%)
VCA
ANALOG + DATA
SUPPLY OUTPUT
ABSOLUTE MAXIMUM RATINGS

Analog Supply Voltage -0.5V to 10V

Digital Supply Voltage -0.5V to 10V
Differential I nput Voltage -5V to 5V ORDERING INFORMATION
Output Voltage -0.5V to 20V
Storage Temperature - 65°C to +150°C Part Number Package Operating Temperature
0
Operating Temperature -40°C to +85°C XR-C587 Ceramic _45 C to +85° C
lead Soldering (10 seconds) 300°C XR-C588 Ceramic -45°C to +85°C

2-34
XR·C587 I C588

ELECTRICAL CHARACTERISTICS - XR·C587/C588

Test Conditions: TA = -40°C to +85°C, at a supply voltage of VCC = 6.0V to 6.8V dc, Unless otherwise specified.

PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

SUPPLY

Supply Voltage 6.0 6.4 6.8 V dc

Supply Current 2.3 2.7 3.3 mA All ALBO Pins open VCC = 6.3V
ALBO Bias Current 200 280 360 mA ALBO Grounds open
ALBO drive pin at 3.5V (~ 5 VBE's)

AMPLIFIER

DC open-loop gain 54 60 68 dB 1V p-p output level, RL = 4 kn

AC gain at 1 MHz 34 dB returned to VCM = 2.7V
Corner Frequency 110 kHz
Input Offset Voltage -15 0 +15 mV RS = 10 kn to both inputs
I nput Bias Current 1 4 J.LA
Output Sink Current 300 400 500 J.LA

ALBO

One Common Drive Input,

Three Ports, Each With Its
Own Ground

Max ALBO Current 2.5 4.5 6 mA Total current to Ground through

all ALBO Ground Pins, Drive input
returned to VCC = ~.OV through
51 kn.
ALBO Current Mismatch -5 0 +5 % Measured with 1 mA nominal level
in each ALBO Ground Pin.
ALBO Port Voltage 1.2V 1.45 1.7V V dc Two VBE above Ground,
1 mA in each Port.
ALBO OFF Impedance 10 kn Drive input and ALBO Ground Pins
Grounded Frequency = 1.5 MHz

SINGLE TRANSISTOR

Beta (~) 75 150 400 VCE = 6.8V, IC = 100 mA

Leakage 0.01 1 5 J.LA VCEO = 6.8V

2·35
 XR·C587 I C588

ELECTRICAL CHARACTERISTICS - XR·C588

Test Conditions: TA = -40°C to +85°C, at a supply voltage of VCC = VCA = VCD = 6.DV to 6.8V dc,
Unless otherwise specified.

PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

SUPPL Y CURRENTS

ICA' VCA Supply Current 1.8 3.5 5 mA VCA is Analog Supply Voltage
VCD is Digital Supply Voltage
lCD' VCD Supply Current 5 8 12 mA Outputs off, VAO = VCT
ICCT' ICA + ICD 7 12.5 14.5 mA Outputs off, VAO = VCT

AMPLIFIER

Same specification as VAO = Amplifier Output

amplifier in C587 Voltage

VOLTAGE REFERENCES

Vzref' Zener Voltage 5.0 5.4 5.65 Volts No external loading

VCT' Center Tap Voltage 2.35 2.70 2.90 Volts No external loading
VCB' Clock Bias 3.5 4.0 4.3 Volts No external loading

THRESHOLD VOLTAGES

A LBO Comparator
VAPD +' ALBO + peak .75 .9 1.05 Volts V AO measured w/respect to
detector voltage VCT, with IADO = 100 IJ.A
VAPD -' ALBO - peak ·.75 -.9 -1.05 Volts
detector voltage
VAPD + - VAPD - -50 0 50 mV

Data Comparators
VDT+, + data threshold 42 48 53 %of VAO varied, clock drive
VAPD+ input = 3.152 MHz sine wave
at .5V pp. Detect onslaught of
output pulses at 3.152 MHz,
measure VAO'
VDT-' - data threshold 42 48 53 %of Same as for VDT+
VAPD-
VDT+- VDT- 30 0 30 mV

Clock Comparator
VCLK+' + clock threshold *57/42 62/48 67/53 % of VAO varied, detect 100 mV
VAPD+ change in VCDO'
VCLK-' - clock threshold *57/42 62/48 67/53 % of
VAPD-
VCLK+ - VCLK- 35/30 0/0 35/30 mV

• Upper limits are for Option 1, lower limits are for OPtion 2.

2-36
XR·C587 I C588

ELECTRICAL CHARACTERISTICS - XR-C588 (Continued)

Test Conditions: TA = _40°C to +B5°C, at a supply voltage of VCC = VCA = VCD = 6.0V to 6.BV dc,
Unless otherwise specified.

PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

CLOCK DRIVE OUTPUT VCDO

•
ACD+, gain from -2.7 -3.0 -3.3 V!V VAO changed from VCLK+ to
VAO to VCDO (VCLK+ + .5V) measure change
in VCDO'
ACD- 2.7 3.0 3.3 V!V VAO changed from VCLK- to
(VCLK- - .5V) measure change
in VCDO'
ACD+/ACD- -1.1 -1.0 -.9
VCDO High -l.B -1.5 -1.1 V VCDO measured w/respect to
VCC. VAO=VCT
VCDO+ Low -3.2 V VCDO measured w/respect to
VCC' VAO = VCT +1.5 volts.
VCDO- Low -3.2 V ,VCDO measured w/respect to
VCC. VAO = VCT -l.&volts.

CLOCK AMPLIFIER

VCACM, Clock input 2.35 4.3 V VCT or VCB can be used as

Common Mode Bias VCACM
Voltage
I nput Offset Va Itage -15 15 mV
Input Bias Current 1 4 J.1.A

ALBO DR IVE IADO

IADO Max .7 1.5 3.0 mA VAO at VCT ± 1.5 volts

IADO measured to Gnd.
IADO Off 10 J.1.A VAO = VCT' IADO
measured to Gnd.

OUTPUT DRIVER

10± Leak 100 J.1.A Output off and returned

to 20 volts.
VOL± .5 .B 1.0 Volts ILOAD = 15 mA
VOL+- VOL- -80 0 +80 mV ILOAD = 15 mA
TOPW±, output 143 159 175 nsec 50% Pts. RL = 350n
pulse width
TOpW+ - TOPW- -10 0 10 nsec
TRT±' Rise time 40 nsec RL = 350n
20% to BO% Pts.
TFT±' Fall time 40 nsec RL = 350n
20% to BO% Pts.

With no clock signal, Output

NO SIGNAL PROTECTION
will be off.

2-37
 XR·C587 I C588

PRINCIPLES OF OPERATION

T1 C is a digital line system operating at 3.152 Mbits/sec, comparators which are internally biased from a voltage
very similar, in principle, to the T1 line system. It provides reference and precision voltage divider network. The pre-
48 digitally encoded and time division multiplexed voice amplifier output is sliced at various voltage levels to elimin-
channel repeaters containing 2 regenerators which have the ate the effects of baseline noise. This output is full wave
approximate spacing of 6300 ft. Power is provided by a rectified, and applied to a crystal time extraction circuit.
simplex arrangement with a line current of 120 mA. Two The sinusoidal wave shape from the time extraction circuit
is differentially coupled to a clock slicer block to produce
regenerators share a common power supply. Basic repeater
the internal square wave clock signal.
functions, namely re~haping, retiming and regenerating, are
performed for cable losses from 6 to 54 dB, as measured at
1.576 MHz.
The regeneration of data is ach ieved through a pair of
data comparators and ECL latches. The data slicing levels
The bipolar PCM signal, which is attenuated and distorted are set to ± 50% of the preamplifier output peak voltages
due to transmission medium, is applied to a preamplifier ECL latch outputs and clock signal are then gated
through a pulse-shaping network. This network, and the to produce two precisely timed output data signals. Tho
variolosser diodes, forms theALBO circuitry which pro- positive and negative data paths are separate but identical in
vides attenuation and shaping to automatically adjust for design.
varying cable characteristics.

A feedback network is used around the preamplifier for A zero input protection circuit is provided for the dual task
gain equalization, as well as to reject out-of-band of preventing the output switches from latching in an ON
noise. The output of the preamplifier is controlled to swing state, as WGII as reducing the likelihood of output pulses
between two established peak levels, and drives a set of data with no input signal.

70

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PHASE OF C262 " " , -
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20
I
_ _ _ PHASE OF CS87
-12So
CS88 AMPLIFIER
-1S00 10

10K 100K 1M 10M

FREQ. (HZ)

Figure 1: Bode Plot of C262 and C587/C588 Amplifiers.

2-38
XR·C587 I C588

BLOCK DIAGRAM OF CS87 AND CS88 INTERCONNECTED

VCT FOR AMPLIFIER BIAS VCD (OR VCT) FOR CLOCK BIAS

XR-CS87 VCDO

•
CLOCK DRIVE
OUTPUT

CLOCK X-TAL
INPUTS CIRCUIT

ALBa DRIVE

iE
ALBa CURRENT
HIH--I DIODESI-.....! -....~...........I-I

ALBa
FILTER V+

Figure 2: Block Diagram of C587/C588 Interconnected.

2-39
 XR-T5600/T5620

T1, T148C, & 2 M Bitls PCM Line Repeater

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5600/T5620 is a bipolar monolithic repeater IC

designed for PCM carrier systems operating at 1.544 M bit/s
(Tl),2 M bit/s, or 2.37 M bit/s (T148C). It provides all of ALBO GROUND SUBSTRATE GROUND
the active circuits required for one side of a PCM repeater.
A crystal filter clock extraction version of XR-T5600/ ALBO
PORT 1
ALBO
CONTROL
T5620 is available as XR-T5700/T5720.
CLOCK
ALBO AMPLIFIER
PORT 2 BIAS

ALBO
PORT 3 LC TANK

FEATURES
PREAMP
-VE INPUT VCC

Single 5.1 V Power Supply

Less than JO ns Sampling Pulse over the Operating Range PREAMP
+VE INPUT
CLOCK
OUTPUT
Triple Matched ALBO Ports
PREAMP PHASE SHIFTED
2 M Bit/s Capability -VE OUTPUT CLOCK INPUT

PREAMP -VE DATA

+VE OUTPUT OUTPUT

DIGITAL +VE DATA

APPLICATIONS GROUND OUTPUT

T1 PCM Repeater
T148C PCM Repeater
European 2 M Bit/s PCM Repeater
T1C PCM Repeater (requires external preamplifier)
SYSTEM DESCRIPTION

The XR·T5600/T5620 performs most of the functions

required for one side of a PCM repeater operating at 2 M
ORDERING INFORMATION bit/s or similar baud rate. The integrated circuit amplifies
the received positive and negative pulses and feeds them
Part Number Package Operation Temperature into Automatic Line Build-out (ALBO), clock and data
XR-T5600 Plastic _40° C to 85° C
threshold detectors, see Figure 1. The ALBO threshold
XR-T5620 Plastic or Ceramic -40°C to 85°C
detector ensures that the received pulses at Pins 7 and 8
have the correct ampl itude and shape. Th is is carried out by
controlling the gain and frequency shaping of the ALBO
network with three variable impedance ALBO ports.

ABSOLUTE MAXIMUM RATINGS The clock threshold detector extrar.ts timing information
from the pulses received at Pins 7 and 8 and passes it into
Storage Temperature -65°C to +150°C the external tank coil at Pin 15. The sinusoidal-type wave-
Operating Temperature -40°C to +85°C form is amplified into a square wave at Pin 13, and forward-
Supply Voltage -0.5 to +10 V ed through an external phase shift network into Pin 12.
Supply Voltage Surge (10 ms) +25 V This waveform provides the data sampling pulse which
lilput Voltage (except Pin 2,3,4.17) -0.5 to 7 V opens latches into which the dat) from the data thr8shold
Input Voltage (Pin 2,3,4,17) -0.5 to +0.5 V detectors is passed. The resulting pulses are stored for half
Data Output Voltage. (Pin 10. 11) 20V a bit period (normally 488 ns) in the latches. They appear
Voltage Surge (Pin 5,6,10,11) (10 msec only) 50V as half-width output pulses at Pins 10 and 11.

2-40
 XR-T5600

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 5.1 V ± 5%, unless specified otherwise (see Figure 1).

PARAMETERS PINS MIN. TYP. MAX. UNIT CONDITIONS

Supply Current 14 22 30 mA
Data Output Leakage Current 10,11 0 100 jJ.A Vpull-up = 15 V, Vcc = 5.35 V
ALBO Port Off Voltage 2,3.4 0 0.1 V

•
Amplifier Pin Voltage 5,6),8 2.4 2.9 3.4 V

DYNAMIC CHARACTERISTICS AMPLIFIER

Output Offset Voltage -50 0 50 mV Rs = 8.2 kn

ACGin@lMHz 47 50 53 dB
I nput Impedance 20 kn
Output Impedance 200 n

ALBO

A LBO Off Impedance 20 25 kn

ALBO On Imepdance 25 n

THRESHOLDS

ALBO Threshold 1.4 1.5 1.6 V

Clock Threshold as % of ALBO Threshold 68 80 %
DATA Threshold as % of ALBO Threshold 42 49 %
Clock Drive Current 0.7 1.4 mA At Vo = VALBO Threshold

OUTPUT STAGES R L = 130n, Vpull-up = 5.1 ± 5%

Output Pulse Rise Time 40 ns

Output Pulse Fall Time 40 ns
Output Pulse Width 224 244 264 ns
Output Pulse Width Differential -10 +10 ns
Buffer Gate Voltage (Low) 0.65 0.95 V
Buffer Gate Voltage Differential -0.15 0.15 V

2-41
 XR-T5620

ELECTRICAL CHARACTERISTJCS
Test Conditions: Unless otherwise stated, all characteristics shall apply over the operating temperature range of -40°C to +85°C
with Vcc = 5.1 V ± 5%, all voltages referred to ground = 0 V.

SYMBOL PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

GENERAL (Ref. Figure 2)

IS Supply Current 14 22 30 mA
ILD Data Output
Leakage Current 10,11 6 100 p.A From Vs (See Note 1)
Amplifier Pin Voltages 5,6,7,8 2.4 2.9 3.4 V
ALBO Ports Off Voltage 2,3.4 0 0.1 V

Note: 1. Vs = 15 V, VCC = 5.35 V

AMPLIFIER (Ref. Figure 2, Only Pins 1,9,10... 18 connected)

Input Offset Voltage 5&6 -10 +10 mV RS = 8.2 kn

(See Note 1)
Input Bias Current 5&6 0 5 p.A RS = 8.2 kn
(See Note 1)
I nput Offset Current 5&6 -1 1 p.A RS = 8.2 kn
(See Note 1)
Output Offset Voltage 7&8 -50 0 50 mV RS - 8.2 kn
(See Note 1)
Common Mode
Rejection Ratio 7&8 30 dB Vcc ±10%
Output Voltage Swing 7&8 2.2 V

Note: 1. RS = Source Resistance

CLOCK AMPLIFIER (Ref. Figure 2, Disconnect Pin 15 from Pin 16)

Input Offset Voltage 15 & 16 0.5 6 mV RS = 10 kn

(See Note 1)
Input Bias Current 15 & 16 10 p.A T = 25°C
Max. Output Voltage 13 0.7 V
Min. Output Voltage 13 0.7 V
Max./Min. Output
Voltage Difference - 0.7 50 mV

Notes: 1. RS = Source resistance, Pin 15 positive with respect to Pin 16

2. Pin 15 = Pin 16 = 3.6 V
3. Pin15=2.6V,Pin16=3.6V
4. Pin 15 = 4.6 V, Pin 16 = 3.6 V
5. Calculation only

2-42
 XR-T5620

SYMBOL I PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

ALBO (Ref. Figure 2)

On Current 1 3 mA VS-V7 = ± 1.75 V

Drive Current 17 0.4 1.4 mA VS-V7 = ± 1.75 V
Resistance Pin 17 to Ground 35 50 70 kn Not Powered

DYNAMIC CHARACTERISTICS

AMPLIFIER (Ref. Figure 3)

Ao
Zin
Zout
AC Gain @ 1 MHz
Input Impedance
Output Impedance
5 to S
5
7,S
47
20
50 53

200
dB
kn
n
(See Note 1)
(See Note 2)
•
Notes: 1. At 1 MHz, AC ground Pins 7 and S, disconnect 51 n resistor, allow for in-circuit R,C
2. At 1 MHz, use Figure 2

CLOCK AMPLI FIER (Ref. Figure 3)

Ao AC Gain 15,16to13 32 dB (See Note 1)

BW -3 dB Bandwidth 15,16 to 13 10 mHz (See Note 2)
td Delay 15 to 13 8 12 ns (See Note 3)
Zout Output Impedance 13 200 n (See Note 4)

Notes: 1. Remove dc offset, at 2.04S MHz, Pin 13 = 1 V pk-pk sine wave

2. Remove dc offset, Pin 13 = 1 V pk-pk sine wave
3. Remove dc offset, Pin 15 = 2 V pk-pk sine wave; delay from Pin 15 negative-going zero crossover to Pin 13 positive
edge
4. Remove dc offset, at 2.04S MHz

ALBO (Ref. Figure 2)

Off Impedance 2,3,4 20 kn (See Note 1)

l!1termediate Impedance
Difference 2,3,4 5 % (See Note 2)
On Impedance 2,3,4 25 n (See Note 3)
Transconductance 7/S to 1 0.03 dB (See Note 4)

Notes: 1. At 1 MHz, allow for in-circuit R,C

2. At 1 MHz, VS-V7 adjusted for current at Pin 1 = 100 pA
3. At 1 MHz, VS-V7 adjusted for ± 1.75 V
4. At 1 MHz, change in VS-V7 for current at Pin 1 = 10 pA to 100 pA

2-43
 XR-T5620

SYMBOLI PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

THRESHOLD VOLTAGES (Ref. Figure 3)

ALBO Threshold +ve 8-7 1.4 1.5 1.6 V (See Notes 1 & 2)
ALBO Threshold -ve 7-8 1.4 1.5 1.6 V (See Notes 1 & 2)
ALBO Threshold Difference - -5 0 5 % (See Note 3)
Clock Drive on Current
(peak) +ve 18 1.0 1.4 mA (See Note 4)
Clock Drive on Current
(peak) -ve 18 1.0 1.3 mA (See Note 5)
Clock Drive on Current
Difference - -5 0 5 % (See Note 3)
Clock Threshold +ve 87 68 80 % (See Notes 1, 6, 8)
Clock Threshold -ve 7-8 68 80 % (See Notes 1, 7, 8)
Clock Threshold Difference - -5 0 5 % (See Note 3)
Data Threshold +ve 8-7 44 46 48 % (See Notes 1,8,9,11)
Data Threshold -ve 7-8 44 46 48 % (See Notes 1,8,10,11 )
Data Threshold Difference - -3 0 3 % (See Note 3)

Notes: 1. Pk/pk voltage at Pins 7 and 8 of a 1 MHz sine wave derived through amplifier and measured differentially
2. Pk/pk voltage at Pins 7 and 8 adjusted for current at Pin 1 = 3 mA
3. Calculation only
higher value
percentage difference calculated from ( -1) x 100 %
lower value

4. V8-V7 adjusted to ALBO threshold +ve voltage, ref. Pin 16 = 3.6 V

5. V7-V8 adjusted to ALBO threshold -ve voltage, ref. Pin 16 = 3.6 V
6. V8-V7 adjusted to peak current at Pin 18 = % (clock drive on current peak +ve)
7. V7-V8 adjusted to peak current at Pin 18 = % (clock drive on current peak -vel
8. Figure taken as a percentage of lower A LBO tl,reshold
9. V8-V7 increased until 1 MHz PRF on counter at Pin 10
10. V7-V8 increased until 1 MHz PRF on counter at Pin 11
11 With 2048 MHz 2 V pk-pk sine wave to Pin 15 with 180pH in parallel with 36 [2to Pin 16 = 36 V
OUTPUT STAGES (Ref. Figure 3. Use 180 pH inductor between Pins 15 and 16. Apply 2.048 MHz 2V pk/pk to Pin 15.)

tr Output Pulse Rise

Time +ve 10 40 ns 10% - 90%
tr Output Pulse Rise
Time -ve 11 40 ns 10% - 90%
tf Output Pulse Fall
Time +ve 10 40 ns 10% - 90%
tf Output Pulse Fall
Time -ve 11 40 ns 10%- 90%
tw Output Pulse Width +ve 10 224 244 264 ns at 50%
Output Pulse Width -ve 11 224 244 264 ns at 50%
~tw Output Pulse Width
Difference - -10 10 ns
VOL Buffer Gate Voltage
(low) +ve 10 0.65 0.95 V
VOL Buffer Gate Voltage
(low) -ve 11 0.65 0.95 V
~VOL Buffer Gate Voltage
Difference - -0.15 0.15 V

2-44
XR-T5620

•
Figure 2. D.C. Parameter Test Circuit

Vee

I 27PF
Vee

3.3k

o 1,F
AMPLIFIER INPUT ~

151
Figure 3. A.C. Parameter Test Circuit

2-45
 XR-T5620

SYMBOL I PARAMETERS I PINS I MIN I Typi MAX I UNIT I CONDITIONS

SAMPLE PULSE WIDTH (Ref. Figure 4, Cy = 27 pF)

I Sample Pulse Width

l I I 10 I I
ns I(see Notes 1... 5)

Notes: 1. The sample pulse width is the period during which the output latches are opened to accept a signal above the data
hold at Pin 7 or 8 and cause a half-width output pulse at Pin 11 or 10 respectively.
2. Sample pulse width is specified with a 2.048 MHz TTL waveform at clock input (Pin 15) and a 2,400 MHz Schottky
TTL waveform at amplifier input in the circuit of Figure 4. Figure 7 shows the relevant IC waveforms.
3. Monitor the frequency of coincident output pulses at Pins 10 and 11 either directly or through ouput circuit to fre-
quency counter.
4. Sample pulse width = X ns + (0,1 x measured frequency in kHz) ns where X is the mean rise/fall times of the waveform
at Pin 8 between 25% and 75%.
5. X to be within the range of 10 nx < X < 12 ns. THis requires H F layout techniques with the amplifier operated closed
loop.

SAMPLE PULSE GENERATOR INPUT WAVEFORM (pin 12 - Ref. Figure 4, Cy = 40 pF)

lou,pu, Pulse Frequency 1,024 1.024 MHz (See Note 1)

1'0"'1',024-100 ppm f+l00ppm

Note: 1. With 2.048 MHz ±100 ppm TTLwaveform at clock input. With half of above waveform frequency at amplifier input.

CLOCK.
INPUT
Vee

36
1 0 '"F

130 130

33k

Figure 4. Sampling Pulse Test Circuit

2-46
XR-T5620

TYPICAL AT 5.1 V AND AT 2SoC

180

•
120
GAIN (dB)
PHASE (DEGREES)
20 -
60
10 -

-10 -
-60

2 3 4 6 8 10 2 3 4 6 8100 2 3 4 6 B 1000
FREQUENCY (MHz)

Figure 5. Typical and Limiting Values of Gain and Phase

INPUT WAVEFORMS
+2.4V
CLOCK lIP 2.048 MHz +O.4V

+2.4V
AMPLIFIER lIP 2.400 MHz +O.4V

IC WAVEFORMS

SAMPLE PULSE (INTERNAL)

PIN 8

PIN 10 r----- +5.1V

+0.7V TYP.

PIN 11 +5.1V
+0.7V TYP.

NOTE

COINCIDENT OUTPUT PULSES

Figure 6. Ie Waveforms for Measuring Sampling Pulse Width

2-47
 220 XR-T56001T5620

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2-49
 EX4R XR-T5700/T5720

T 1, T 148C, & 2 M Bitls PCM Line Repeater

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5700/T5720 is a bipolar monolithic repeater IC

that provides all the active circuits required for one side of ALBO GROUND
ANALOG GROUND CLOCK
a PCM repeater. The IC is designed for clock extraction by SUBSTRATE GROUND
-.....,nl~n
DRIVE

using a crystal filter.

ALBO ALBO
PORT 1 CONTROL

The primary applications of XR-T5700 are T1 (1.544 M

ALBO CLOCK
bit/sl. T148C (2.37 M bit/sl. and European 2 M bit/s PCM PORT 2 AMPLIFIER

repeater.
ALBO CLOCK
PORT 3 AMPLIFIER
INPUT
A tank circuit clock extraction version of XR-T5700-T5720
is available as XR-T5600/T5620. AMPLIFIER
-VE INPUT VCC

AMPLIFIER CLOCK
+VE INPUT ___I _ -. OUTPUT

FEATURES
AMPLIFIER PHASE SHIFTED
-VE OUTPUT CLOCK INPUT
Crystal Clock Extraction
Single 5.1 V Power Supply AMPLIFIER
+VE OUTPUT
-VE DATA
OUTPUT
Less than 10 ns Sampling Pulse over the Operating Range
Triple Matched ALBO Ports GROUND ·VE DATA
OUTPUT

APPLICATIONS

T1 PCM Repeater SYSTEM DESCRIPTION

T148C PCM Repeater
T1C PCM Repeater (requires external preamplifier) The X R-T5700/T5720 performs most of the functions
European 2 M Bit/s PCM Repeater required for one side of a PCM repeater operating at 2 M
bit/s or similar baud rate. The integrated circuit amplifies
the received positive and negative pulses and feeds them
into Automatic Line Build-out (ALBOl. clock and data
threshold detectors, see Figure 1. The ALBO threshold
ABSOLUTE MAXIMUM RATINGS detector ensures that the received pulses at Pins 7 and 8
have the correct amplitude and shape. This is carried out by
Storage Temperature -65°C to +150°C controlling the gain and frequency shaping of the ALBO
Operating Temperature _40° C to +85° C network with three variable impedance ALBO ports.
Supply Voltage -0.5 to +10 V
Supply Voltage Surge (10 ms) +25V The clock threshold detector extracts timing information
Input Voltage(except Pins 2,3,4,17) -0.5 to 7 V from the pulses received at Pins 7 and 8 and passes it into
Input Voltage (Pins 2,3,4,17) -0.5 to +0.5 V open collector Pin 18. A crystal filter is connected from
Data Output Voltage (Pins 10, 11) 20V Pin 18 to clock amplifier input Pins 16 and 15. The sin-
Voltage Surge (Pins 5,6,10,11) (10 msec only) 50V usoidal-type waveform is amplified into a square wave at
Pin 13, and forwarded through an external phase shift
network into Pin 12. This waveform provides the data
sampling pulse which opens latches into which the data
ORDERING INFORMATION from the data threshold detectors is passed. The resulting
pulses are stored for half a bit period (normally 488 ns
Part Number Package Operating Temperature for 2 M bit/s) in the latches. They appear as half-width
XR-T5700/T5720 Ceramic -40°C to +85°C output pu Ises at Pins 10 and 11.

2-50
 XR-T5700

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 5.1 V ± 5%, unless specified otherwise (see Figure 1).

PARAMETERS PINS MIN. TYP. MAX. UNIT CONDITIONS

Supply Current 14 22 30 mA
Data Output Leakage Current 10,11 0 100 pA Vpull-up = 15 V, Vcc = 5.35 V

•
ALBO Port Off Voltage 2,3,4 0 0.1 V
Amplifier Pin Voltage 5,6,7,8 2.4 2.9 3.4 V

DYNAMIC CHARACTERISTICS AMPLIFIER

Output Offset Voltage -50 0 50 mV Rs = 8.2 kn

ACGin@ 1 MHz 47 50 53 dB
I nput Impedance 20 kn
Output Impedance 200 n

ALBO

ALBO Off Impedance 20 25 kn

ALBO On Imepdance 25 n

THRESHOLDS

ALBO Threshold 1.4 1.5 1.6 V

Clock Threshold as % of ALBO Threshold 68 80 %
DATA Threshold as % of ALBO Threshold 42 49 %
Clock Drive Current 0.7 1.4 mA At Vo = VALBO Threshold
()UTPUT STAGES RL = 130n, Vpull-up = 5.1 ± 5%
Output Pulse Rise Time 40 ns
Output Pulse Fall Time 40 ns
Output Pulse Width 224 244 264 ns
Output Pulse Width Differential -10 +10 ns
Buffer Gate Voltage (Low) 0.65 0.95 V
Buffer Gate Voltage Differential -0.15 0.15 V

2-51
 XR-T5720

ELECTRICAL CHARACTERISTICS
Test Conditions; Unless otherwise stated, ail characteristics shall apply over the operating temperature range of -40°C to +85°C
with Vce = 5.1 V ± 5%, all voltages referred to ground = 0 V.

SYMBOL PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

GENERAL CHARACTERISTICS (Ref. Figure 2)

IS Supply Current 14 22 30 mA
ILD Data Output Leakage
Current 10.11 100 p.A from Vs (See Note 1)
Amplifier Pin Voltages 5,6,7,8 2.4 2.9 3.4 V
ALBO Ports Off Voltage 2,3,4 0 0.1 V

Note 1: Vs = 15V, VCC = 5.35 V

AMPLIFIER (Ref. Figure 2, Only Pins 1,9,10... 18 Connected)

I nput Offset Voltage 5&6 -10 +10 mV RS = 8, 2 kn

(See Note 1)
Input Bias Current 5&6 0 5 IlA RS = 8, 2 kn
(See Note 1)
I nput Offset Current 5&6 -1 1 RS = 8,2 kn
(See Note 1)
Output Offset Voltage 7&8 -50 0 -50 mV RS = 8, 2 kn
(See Note 1)
Common Mode
Rejection Ratio 7&8 30 dB Vcm ± 0,3 V

Power Supply
Rejection Ratio 7&8 30 dB Vcc ± 10

Output Voltage Swing 7&8 2.2 V

Note 1: RS = Source Resistance

CLOCK AMPLIFIER (Ref. Figure 2 Disconnect Pin 15 from Pin 16)

Input Offset Voltage 15 & 16 0.5 6 mV RS = kn (See Note 1)

Input Bias Current 15 & 16 10 IlA T =25°C
Max. Output Voltage 13 0.7 V
Min. Output Voltage 13 0.7 V
Max./Min. Output
Voltage Difference - 50 mV

Notes: 1. RS =Source resistance, Pin 15 positive with respect to Pin 16.

2. Pin 15 =Pin 16 = 3.6 V
3. Pin 15 = 2.6 V, Pin 16 = 3.6 V
4. Pin 15=4.6V,Pin 16=3.6V
5. Calculation only

2-52
XR-T5720

SYMBOL PARAMETERS I PINS MIN TVP MAX UNIT CONDITIONS

AlBa (Ref. Figure 2)

On Current 1 3 mA VS,V7 = ±1.75 V

Drive Current 17 0.4 1.4 mA VS,V7 = ±1.75 V
Resistance Pin 17 to GN 35 50 70 kn Not Powered

DYNAMIC CHARACTERISTICS

AMPLIFIER (Ref. Figure 3) II

All AC Gain @ 1 mHz 5toa 47 50 53
Zin Input Impedance 5 20 kn (See Note 1)
Zout Output Impedance 7,a 200 n (See Note 2)

Notes: 1. At 2 MHz, AC ground Pins 7 and a, disconnect 51 n resistor. Allow for in-circuit R, C.
2. At 1 MHz, use Figure 2.

CLOCK AMPLIFIER (Ref. Figure 3)

Ao AC Gain 15,16to 13 32 dB (See Note 1)

BW -3 dB Bandwidth 15, 16to 13 10 MHz (See Note 2)
Delay 15, 16 to 13 a 12 ns (See Note 3)
Output Impedance 13 200 n (See Note 4)

Notes: 1. Remove dc offset, at 2.048 MHz, Pin 13 = 1 V plc-pk sine wave

2. Remove dc offset, Pin 13 = 1 V pk-pk sine wave
3. Remove dc offset, Pin 15 = 2 V pk-pk sine wave. Delay from Pin 15 negative-going zero crossover to Pin 13 positive
edge.
4. Remove dc offset, at 2.048 MHz

ALBa (Ref. Figure 2)

Off Impedance 2,3,4 20 kn (See Note 1)

Intermediate Impedance
Difference 2,3,4, 5 (See Note 2)
On Impedance 2,3,4 25 M (See Note 3)
[Transconductance 7,'a to 1 0.03 dB (See Note 4)

Notes: 1. At 1 MHz, allow for in-curcuit R,C

2. At 1 MHz, VaN7 adjusted for current at Pin 1 = l00pA
3. At 1 MHz, Va-V7 adjusted for ± 1.75 V
4. At 1 MHz, change in Va-V7 for current at Pin 1 = 10pA to l00pA

2·53
 XR-T5720

SYMBOL I PARAMETERS PINS MIN TYP MAX UNIT I CONDITIONS

THRESHOLD VOLTAGES (Ref. Figure 3)

ALBO Threshold +ve 8-7 1.4 1.5 1.6 V (See Notes 1 & 2)
ALBO Threshold -ve 7-8 1.4 1.5 1.6 V (See Notes 1 & 2)
ALBO Threshold Difference - -5 0 5 (See Note 3)
Clock Drive on Current
(Peak) +ve 18 0.65 1.0 1.4 mA (See Note 4)
Clock Drive on Current
(Peak) -ve 18 0.65 1.0 1.3 mA (See Note 5)
Clock Drive on Current
Difference - -5 0 5 (See Note 3)
Clock Threshold +ve 8-7 68 80 (See Notes 1,6, 8)
Clock Threshold -ve 7-8 68 SO % (See Notes 1,7,8)
Clock Threshold Difference - -5 0 5 % (See Note 3)
Data Threshold +ve 8-7 44 46 48 % (See Notes 1, 8, 9, 11)
Data Threshold -ve 7-8 44 46 48 % (See Notes 1, 8, 10, 11)
Data Threshold Difference - -3 0 3 % (See Note 3)

Notes: 1. Pk/pk voltage at Pins 7 and 8 of a 1 MHz sine wave derived through amplifier and measured differentially
2. Pk/pk voltage at Pins 7 and 8 adjusted for current at Pin 1 = 3 mA
3. Calculation o n l y . rr{ higher value
percentage difference calculated fro I I
ower va ue
-i'~ x 100 %

4. V8-V7 adjusted to ALBO threshold +ve voltage (ref. Pin 16 = 3.6 V)

5. V7-V8 adjusted to ALBO threshold -ve voltage (ref. Pin 16 = 3.6 V)
6. V8-V7 adjusted to peak current at Pin 18 = % (clock drive on current peak +ve)
7. V7-V8 adjusted to peak current at Pin 18 = % (clock drive on current peak -vel
8. Figure taken as a percentage of lower ALBO threshold
9. V8-V7 increased until 1 MHz PRF on counter at Pin 10
10. V7-VS increased until 1 MHz PRF on counter at Pin 11
11. With 2.048 MHz 2 V pk-pk sine wave to Pin 15 with 180 pH in parallel with 36 n to Pin 16 = 3.6 V

OUTPUT STAGES (Ref. Figure 3. Use 180 pH inductor between Pins 15 and 16. Apply 2.048 MHz 2V pk/pk to Pin 15.)

tr Output Pulse Rise

Time +ve 10 40 ns 10% - 90%
tr Output Pulse Rise
Time -ve 11 40 nx 10% - 90%
tf Output Pulse Fall
Time +ve 10 40 ns 10% - 90%
tf Output Pulse Fall
Time -ve 11 40 ns 10%- 90%
tw Output Pulse Width +ve 10 244 244 264 ns at 50%
tw Output Pulse Width -ve 11 244 244 264 ns at 50%
Ytw Output Pulse Width Difference - -10 10 ns
VOL Buffer Gate Voltage
(low) +ve 10 0.65 0.95 V
VOL Buffer Gate Voltage
(low) -ve 11 0.65 0.95 V
bVOL Buffer Gate Voltage
Difference - -0.15 0.15 V

Note: 1. Calculation only 2-54

XR-T5720

•
Figure 2. DC Parameter Test Circuit

ClOCK
INPUT
Vs

0.1,.1'

AMPLIFIERT
INPUT
51

Figure 3. AC Parameter Test Circuit

2-55
 XR-T5720

SYMBOL I PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

SAMPLE PULSE WIDTH (Ref. Figure 4. Cy - 27 pF)

Sample Pulse Width - 10 20 ns (See Notes 1... 5)

Notes: 1. The sample pulse width is the period during which the output latches are opened to accept a signal above the data thres-
hold at Pin 7 or 8 and cause a hlaf-width output pulse at Pin 11 or 10 respectively.
2. Sample pulse width is specified with a 2.048 MHz TTL waveform at clock input (Pin 15) and a 2.400 MHz Schottky TL
waveform at amplifier input in the circuit of Figure 5. Figure 7 shows the relevant IC waveforms.
3. Monitor the frequency of coincident output pulses at Pins 10 and 11 either directly or through output circuit to fre-
quency counter.
4. Sample pulse width = Xns + (0,1 x measured frequency in kHz ns where x is the mean rise/fall times of the waveform
at Pin 8 between 25% and 75%.
< <
5. X to be within the range 10 ns X 12 ns. This requires HF layout techniques with the amplifier operated closed
loop.

SAMPLE PULSE GENERATOR INPUT WAVEFORM (Pin 12 Ref. Figure 4, Cy = 40 pF)

Output Pulse Frequency 10,11 1,024 1,024 1,024 MHz (See Note 1)
-100 ppm +100 ppm

Note: 1. Width 2,048 MHz ± 100 ppm TTL waveform at clock input with half of above waveform frequence at amplifier input.

Vs

TO
FREQUENCY
COUNTER

Figure 4. Sampling Pulse Test Circuit

2-56
XR-T5720

TYPICAL AT 5.1 V AND AT 25°C

60

53
50
47
180
40

30

II
120
GAIN (dB)
PHASE (DEGREES)
20

60
10

0 o

-10
-60
-20

-30 -120
2 3 4 6 8 10 2 3 4 6 8100 2 3 4 6 81000
FREQUENCY (MHz)

Figure 5. Typical and Limiting Values of Gain and Phase

INPUT WAVEFORMS
+2.4V
CLOCK liP 2.048 MHz +O.4V

+2.4V
AMPLIFIER liP 2.400 MHz
+O.4V

IC WAVEFORMS

SAMPLE PULSE (INTERNAL)

PIN 8

+5.1V
PIN 10
+0.7V TYP.

PIN 11 +5.1V
+0.7V TYP.

!::!.QJ!
COINCIDENT OUTPUT PULSES

Figure 6. Ie Waveforms for Measuring Sampling Pulse Width

2-57
 5.1V

lK

S.lV

.22p

220 220
T5720
-=
" OS.lV

I\) 'OP%%,~,P
0,
en 300

Jt
P 68P
22

1---._-+------<0 5.1V

150pF

><
II
I
T5720 1.544 MBITS/S HIGH Q PCM REPEATER APPLICATION CIRCUIT
-t
(II
~
I\)
o
 Section 2 - Telecommunication Products

•
Speakerphone Circuits . . . . . . . . . . . . . 2-59
XR-T6420-1 Speakerphone Audio Circuit 2-60
XR-T6420-2 Speakerphone Audio Circuit 2-64
XR-T6421 Speakerphone Control IC 2-68
XR-T6425 Speakerphone IC . . . . . . . . 2-72

2-59
 XR-T6420-1

Speakerphone Audio Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-T6420-1 is a monolithic integrated circuit for use
in high performance speakerphone systems. It is designed to XR-T6420-1
be used with the XR-T6421 Speakerphone Control Circuit.
SPI RVO

The XR-T6420-1 contains the audio paths comprising the SPC RXC
following: Two variable gain cells, a microphone amplifier,
a transmitting amplifier, a receive amplifier, and a speaker
SPO LiLJ~--- _ _--'-,YI RVI
amplifier.

VEE RVO

GND RX+

VCC RX-

FEATURES TXO ~VV~-------fl~MC+

Two Matched Variable GaiA Cells

Internal Microphone Amplifier TXI MC-
Independent Control of Transmitting and Receiving Levels
External Control of Gains and Freq·uency Response
TXC MCO

TVO

ORDERING INFORMATION
APPLICATIONS Part Number Package Operating Temperature
XR-T6420-1CN Ceramic O°C to 70°C
Speakerphones XR-T6420-1CP Plastic O°C to 70°C
Intercoms
Voltage Controlled Amplifiers SYSTEM DESCRIPTION
The speakerphone concept essentially requires that only
one direcction of sound transmission be permitted at any
time. This restraint is brought about by the large gains re-
quired to provide loudspeaker volume and high micro-
phone sensitivity. Owing to the inevitable acoustic
coupling between loudspeaker and microphone, plus
imperfections in the hybrid 2 to 4 wire conversion, it is
necessary to lower the gain in either the transmitting or
ABSOLUTE MAXIMUM RATINGSI receiving path at anyone time to avoid regeneration.

Power Supply (VCC - VEE) +20 V The XR-T6420-1 and XA-T6421 chip set enables the sys-
Power Dissipation lW tem designer to make a highly adaptive, high performance
Derate Above +25°C 7 mWtC speakerphone. The XA-T6421 provides for all sensing and
Operating Temperature aOc to 70°C control functions, while the XA-T6420-1 contains all audio
Any Input Voltage VCC - 0.5 V to VEE + 0.5 V paths needed to switch the gain in either path and provide
o
Storage Temperature -55°C to +150 C interfacing between the system and line.

2-60
XR-T6420-1

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C. VCC = +6 V. VEE = -6 V. unless specified otherwise.

PARAMETERS MIN TYP MAX UNIT CONDITIONS

VCC Minimum +4.5 V

VEE Minimum -6 V
ICC 15 :lL 30 mA
IGND -1 -.1 1 mA

MICROPHONE AMPLIFIER

VIN
VOFFSET
1.7 2
2
2.25
5
V
mV
Referenced to VEE
II
Ibias 1 5 Jl.A
AOL 40 50 dB
RIN 10 kn Typical Input Impedance to GND

SPEAKER AMPLIFIER

VOFFSET 4 10 mV
Ibias -3 -10 Jl.A
AOL 60 70 dB
Swing -4.9 4.8

TRANSMIT AMPLIFIER

Vpin 8 .8 1.3 1.5 V Referenced to VEE

Isource (Pin 7) "I rnA
Isink (Pin 7) -1 mA

RECEIVE AMPLIFIER

Differential Mode Gain -4 -1 0 dB

Common Mode Gain -30 -28 dB
VOUT (Pin 17) -2.7 V

TRANSMIT VCA

VOUT (Pin 10) -2.1 -1.9 -1.5 VOC

Gain Maximum 6 8 13 dB
VOUT Maximum 1 Vp-p

RECEIVE VCA

VOUT (Pin 20) 1.2 1.5 1.7 VDC

Gain Maximum 2 4 7 dB
VOUT Maximum 1 Vp-p

2-61
 XR-T6420-1

PRINCIPLES OF OPERATION Pin 3 - spa - Speaker amplifier output.

Power Supply - Normal operation is with two supplies. Pin 4 - VEE - Negative DC supply pin (usually -5 to -10 V).
VCC is the highest potential and VEE is the lowest. with
the ground pin in between. The circuit can be operated Pin 5 - GND - Ground pin reference for circuit. Can be
from a single supply if the ground pin is connected to a low used with ( VCC - VEE )/2 external reference.
impedance source of approximately half the supply voltage.
Pin. 6 - VCC - Positive DC supply voltage. usually +5 to
Microphone Amplifier - The microphone amplifier is an +10V.
operational amplifier with the noninverting input inter-
nally biased to approximately VEE + 2 Volts. The non- Pin 7 - TXO - Output of transmit amplifier.
inverting input impedance is nominally 10.3 Kohms. Gain
and frequency response can be set by external components Pin 8 - TXI - Input of transmit amplifier.
using the non inverting configuration for the op amp. The
amplifier has an emitter follower output. therefore. needs Pin 9 - TXC - Control voltage of transmit VCA. Transfer
an external pull down resistor to VEE. This resistor is function of VCA is:
selected low in value in order to prevent slewing of the
output waveform due to capacitance.
TVO = 2 (1 +exp (TXD - Vpin 5/VT))-1
Transmit VCA - This VCA provides a voltage dependent TVI
gain. given in Figure 2. The input. referred to VEE. has a
whereVT=
KT
-
°
2:!26mVat+25 C
nominal impedance of 14:8 Kohms. The output is also q,
referred to VEE and is buffered by an emitter follower.
Pin 10 - TVO - Output of transmit VCA. Output is an
Transmit Amplifier - This amplifier is a Darlington Com- emitter follower.
mon Emitter Amplifier with a Class A output stage. Pin 8
is approximately 1.1 Volt above VEE. Gain is set by the in- Pin 11 - TVI - Input of transmit VCA. Input impedance is
put and feedback resistor. To increase the output swing. nominally 14.9 Kohms.
the output DC level is determined using a resistor from Pin
8 to VEE. Pin 12 - MCO - Output of microphone amplifier.

Receive Amplifier - This amplifier has a high impedance Pin 13 - MC· - Inverting input of microphone amplifier.
differential input and a fixed gain of one. The inputs must
be referred to a voltage greater than VEE + 1.5 V. The Pin 14 - MC+ - Noninverting input of microphone ampli-
output is at a fixed DC level with a Class A output stage. fier. Input impedance is nominally 10.3 K ohms.

Receive VCA - This VCA provides a voltage dependent Pin 15 • RX- - Inverting input to receive amplifier. Input
gain. given in Figure 3. The input is referenced to VEE is high impedance.
and has a nominal impedance of 14Kohms. The output
is referred to ground and is buffered by an emitter follower. Pin 16 - RX+ - Noninverting input to receive amplifier.
Input is high impedance.
Speaker Amplifier - This is an operational amplifier with
the non inverting input referred to ground through a 1.8 Pin 17 • RXO - Output of receive amplifier. Output DC
Kohm resistor. The gain is externally set using the input level is nominally 0 volts.
and feedback resistor. The amplifier can be compensated
by a capacitor from the output to Pin 2 or from Pin 2 to Pin 18- RVI - Input to receive VCA. Input impedance is
ground. The output is capable of sourcing or sinking 4 mA. nominally 14 K ohms.

Pin 19 • RXC - Control voltage of receive VCA. Transfer

function of VCA is:

RVO = (1 + exp (( Vpin Q_ RXC)/VT))-1

RVI
CIRCUIT DESCRIPTION
where VT = ~ 2:! 26 mV at 25°C
Pin 1 • SPI - Inverting input to speaker amplifier. q.

Pin 2 • SPC - Speaker amplifier compensation Pin 20 • RVO - Output of receive VCA. Output is an
emitter follower.

2-62
XR-T6420-1

Vee eON~~OL
120K 13K

2.2

TO
SPKR
XR·T6420·1

~~~~ CONTROL
TO

FROM
1.8K

•
} HYBRID
'-----t~-.

~~4--'--~~.TO
CONTROL

Figure 1. Typical Application Schematic

----
ConlrolVoltlgeVerlulGlin

RXVCA

-.... ~
.......
~ -
.~ ~ V
/'"
./
~ -
I~ '\ 1/ /v
/
'\ ~ \
V
/ /
/ V
-50
-.20
"" ""
'\ '\
r\. V V
Vc (PIN 9- PIN 5) (V) Vc (PIN 19- PIN 5) (VI

Figure 2. Transmit Control Voltage vs. Gain Figure 3. Receive Control Voltage vs. Gain

2-63
 XR-T6420-2

Speakerphone Audio Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
r_-----.....,
The XR-T6420-2 is a monolithic integrated circuit for use VEE SPo

in high performance speakerphone systems. It is designed to

be used with the XR-T6421 Speakerphone Control Circuit. MCP vcc

The XR-T6420-2 contains the audio paths comprising the MCN SPc

following: Two variable gain cells, a microphone amplifier,

MCO SPN
a transmitting amplifier, a receive amplifier, and a speaker
amplifier. Mute and enable control logic of the variable
gains cells is provided internally. TVI RVO

TCH RVI

TCl RCH

GND RCl

FEATURES EN RXO

Two Matched Variable Gain Cells MUT RXG

Internal Microphone Amplifier
Independent Control of Transmitting and Receiving Levels TXN RXN
External Control of Gains and Frequency Response
Enable and Mute Logic Pins TXO RXP

ORDERING INFORMATION

Part Number Package Operating Temperature

XFI-T6420-2CN Ceramic O°C to 70°C
XR-T6420·2CP Plastic O°C to 70°C
APPLICATIONS

Speakerphones SYSTEM DESCRIPTION

Intercoms
Voltage Controlled Amplifiers The speakerphone concept essentially requires that only
one direction of sound transmission be permitted at any
time. This restraint is brought about by the large gains re-
quired to provide loudspeaker volume and high micro-
phone sensitivity. Owing to the inevitable acoustic coupling
between loudspeaker and microphone, plus imperfections
in the hybrid 2 to 4 wire conversion, it is necessary to lower
the gain in either the transmitting or receiving path at any
ABSOLUTE MAXIMUM RATINGS one time to avoid regeneration.

Power Supply (VCC - VEE) +30 V The XR-T6420·2 and XR-T6421 chip set enables the sys-
Power Dissipation lW tem designer to make a highly adaptive, high performance
Derate Above +25°C 7 mWtC speakerphone. The XR-T6421 provides for all sensing and
Operating Temperature O°Cto 70°C control functions, while the XR-T6420-2 contains all audio
Any Input Voltage VCC - 0.5 V to VEE + 0.5 V paths needed to switch the gain in either path and provide
Storage Temperature -55°C to +150°C interfacing between the system and line.

2-64
XR-T6420-2

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C. VCC = +5 V. VEE = -5 V. unless specified otherwise.

PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

VCC 3 V
VEE 3 V
ICC 4.9 8 mA Pin 23

•
~

MICROPHONE AMPLIFIER

Y,N 5 25 mV Pin 2
RIN 20 kQ Pin 2
VOFFSET 5 mV
IBIAS -.2 -0.5 IlA
Open Loop Gain 80 dB

SPEAKER AMPLIFIER

RIN 10 kQ Pin 20
VOFFSET 5 mV
IBIAS -.2 -0.5 /lA
Open Loop Gain 80 dB
'SOURCE.'S'NK 100 mA RLOAD = 10Q
VOUT High VCC V
-1.6 RLOAD = 5kQ
VOUT Low VEE V
+.8 RLOAD = 5kQ

TRANSMIT AMPLIFIER

IBIAS -.2 -0.5 /lA

Open Loop Gain 90 dB

RECEIVE AMPLIFIER

'BIAS 1.2 2 /lA Pin 13. Pin 14

Differential Mode Gain -3 -1 dB Pins 15 and 16 Shorted
Common Mode Gain -40 -60 dB Pins 15 and 16 Shorted
IBIAS -.2 -.5 /lA Pin 15
Open Loop Gain 90 dB

VCAs TRANSMIT AND RECEIVE

VOUT DC .3 V Pins 11 and 20

Maximum Gain -2 +2 dB f = 1kHz. Pins 5 and 19
IBIAS Control .5 IlA Pins 6. 7. 17 and 18

MUTE AND ENABLE LOGIC

'SOURCE -10 -20 IlA

Trip Voltage VCC VCC V
-2.8 -2.1

2~65
 XR-T6420-2

PRINCIPLES OF OPERATION

Power Supply Speaker Amplifier

Normal operation is with two supplies. Vec is the highest This is an operational amplifier with a class AS power out-
potential and VEE is the lowest. The circuit can be ope- put stage. Gain and frequency response are set using exter-
rated from a single supply if the ground pin is connected nal components. Depend ing on the load driven, compensa-
to a low impedance source of approximately one half the tion may be necessary using pin 22.
supply voltage.

Microphone Amplifier PIN DESCRIPTIONS

The microphone amplifier is an operational amplifier with Pin 1 . VEE - Negative DC supply.
the positive input internally connected to the ground pin
through a 20 K ohm nominal resistance. Gain and frequency Pin 2 . MCP - Microphone amplifier non inverting input.
responses are set using external components. Internally connected to ground with a 20 K ohm resistance.

Transmit Voltage Controlled Amplifier (TX VCAI Pin 3· MCN - Microphone amplifier inverting input.

The output of the microphone amplifier is normally capa- Pin 4· MCO - Microphone amplifier output.
citively coupled into the TX VCA. The input impedance is
nominally 10 K ohm. The gain of the TX VCA is dependent Pin 5 . TVI - Transmit voltage controlled amplifier input.
upon the voltage difference between the TCH and TCl in- Input impedance is 10 K ohm.
puts on pins 6 and 7. The output is internally connected to
the transmit amplifier. Pin 6 . TCH - Transmit VCA gain control pin; high refer-
ence. Used with pin 7 to control VCA gain according to
Transmit Amplifier Figure 1.

This is an operational amplifier with a class AS output Pin 7 . TCl - Transmit VCA gain control pin; low refer-
stage. Gain and frequency response are set with external ence. Used with pin 6 to control VeA gain.
components. This amplifier is used to drive the hybrid
interface network. Pin 8· GND -Ground reference pin for circuit.

Receive Amplifier Pin 9 . ENABLE - Active high; internally pulled high.

When pulled low, causes an internal 200 mV difference be-
The input on pins 13 and 14 is a high input impedance tween the gain control pins for both yeAs effectively
differencing amplifier. The output is internally referenced causing minimum gain in both.
to the ground pin and connected to the positive input of an
operational amplifier. The gain and frequency response of Pin 10· MUTE - Internally pulled high. When pulled low,
the amplifier can be adjusted using external components on causes only the transmit VeA to be minimum gain.
pins 15 and 16. This amplifier is normally connected to the
hybrid interface network to detect the receive signal while Pin 11 . TXN - Transm it ampl ifier inverting input.
rejecting the transm it signal.
Pin 12· TXO - Transmit amplifier output.
Receive Voltage Controlled Attenuator (RX VCAI
Pin 13 . RXP - Receive amplifier positive input. High
The output of the receive amplifier is capacitively coupled input impedance, must be De referenced externally.
to the RX VCA input on pin 19. The RX VCA's input im-
Pin 14· RXN - Receive amplifier negative input. Must be
pedance is a nominal 10 KI ohm. The gain of the RX VCA
De referenced to same source as pin 13.
is dependent upon the voltage difference between the RCH
and RCl inputs on pins 17 and 18. The output of the RX
Pin 15· RXG - Receive amplifier inverting input.
VCA is internally referenced to the ground pin through a
10 KI ohm resistance and connected to the positive input of
Pin 16· RXO - Receive amplifier op amp output.
the speaker amplifier on pin 20.

2-66
XR-T6420-2

Pin 11.. - RCL - Receive VCA gain control pin low refer- dB
enced used with pin 18 to control VCA gain according to
Figure 1.
VCONTROL:; pin 7-pin 6
or pin 17-pin 18

Pin 18 - RCH - Receive VCA gain control pin; high refer-

ence used with pin 17 to control gain of VCA.

Pin 19 - RVI - Receive VCA input. Input impedance is

10 K ohm.

Pin 20 - RVO Receive VCA output. Impedance is 10 -40

Kohm to ground.

Pin 21 - SPN - Speaker amplifier inverting input.

-60
Pin 22 - SPC - Speaker amplifier compensation. ·160 ·120 -«l 40 80 120 160 200
VCONTROl (mVI

Pin 23 - VCC - Positive DC supply. Figure 1. VCA Gain Characteristics

Pin 24 - SPO - Speaker amplifier output.

r--------.
1-_--oI_ _-TO CONTROL LOGIC

1-+-~iE--+--Vcc

150K
.33
t----~I'\r__tL-..
2K I...L

1-+---01,....JIV\J'\,---.O VCONTROL

1-......- - TO CONTROL LOGIC

RECEIVE
TRANSMIT SIGNAL
SIGNAL

Figure 2. Typical Application Schematic

2-67
 XR-T6421

Speakerphone Control IC
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T6421 is a monolithic integrated circuit for use in

high performance speakerphone systems. It is designed to
VCON TXA·IN
provide all control functions for the XR-T6420-1 or XR-T
6420-2 speakerphone audio circuit. VOL TXA·OUT

The XR-T6421 contains the level sensors and logic neces- MCR-IN CMPB-

sary to change the attenuation in 'the transmitting or

MCA·OUT THB
receiving path in order to avoid acoustic feedback.
NOISE CMPB+
Circuitry is included to detect bacground noise level and
provide a preset amount of attenuation in each path when
no voice is present.
VAEF

SIGNAL AXA·OUT

CMPA+ AXA·IN

THA HPF·OUT
FEATURES
HPF·IN

Low Current
A·OUT A·IN
Background Noise Detection and Suppression
External Control of Attach and Decay Time Constants
I ndependent Control of Gain and Frequency Response
Provides Three Level Control of Transmit & Receive Paths ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T6421CN Ceramic O°C to 70°C
XR-T6421CP Plastic O°C to 70°C

APPLICATIONS

Speakerphones
Intercoms
Voice Operated Switches SYSTEM DESCRIPTION

The speakerphone concept essentially requ i res that on Iy

one direction of sound transmission be permitted at any
time. This restraint is brought about by the large gains re-
quired to provide loudspeaker volume and high microphone
sensitivity. Owing to the inevitable acoustic coupling be-
tween loudspeaker and microphone. plus imperfections in
the hybrid 2 to 4 wire conversion. it is necessary to lower
the gain in either the transmitting or receiving path at any
ABSOLUTE MAXIMUM RATINGS one time to avoid regeneration.

Power Supply 20V The XR-T6420-1 and XR-T6421 chip set enables the sys-
Power Dissipation lW tem designer to make a highly adaptive. high performance
Derate Above +25°C 7 mWfC speakerphone. The XR-T6421 provides for all sensing and
Operating Temperature O°C to 70°C control functions. while the XR-T6420-1 contains all audio
Any Input Voltage VCC +0.5 V to VEE -0.5 V paths needed to switch the gain in either path and provide
Storage Temperature -55°C to 150°C interfacing between the system and line.

2-68
XR-T6421

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 1OV, unless specified otherwise.

PARAMETER MIN TYP MAX UNIT CONDITIONS

Supply Voltage Range 5 20 V

Supply Current 1.4 3 mA VCC = 10 V

•
VREF 1.85 2.1 2.25 V

RECTIFIERS

VOUT 1.9 2.1 2.27 V VAC= 0

VOUT (High Level) 5.0 V
VOFFSET 1 -5 5 mV Vpin 4 - Vpin 12
VOFFSET 2 -5 5 mV Vpin 17 - Vpin 23
AOL 45 dB
Ibias 0.2 /1A

HPF

VOUT DC 2.3 2.6 2.9 V

Maximum Isource (Pin 15) 1.0 mA
Maximum Isink (Pin 15) 1.0 mA
AoL 32 dB
Ibias 0.25 /1A
..
VOICE CIRCUITRY

Noise Amplifier Offset V6 - V5 -3 12 mV VIN =

Signal Offset V8 - V18 15 mV VIN =
Signal Gain .8 1 1.2 Vpin8-Vpin 18
Vpin 5 - Vpin 6

CONTROL OUTPUT

VCON High VCC-·9 VCC-·5 V

VCON Idle 4.~ 5 0.1 V 20 kn to 5 V
VCON Low Minimum 95 V
VCON,VOL Offset 50 250 mV

COMPARATORS

Ibias 1 /1A
Offset 5 17 mV VPOS-VNEG

2-69
 XR-6421

PRINCIPLES OF OPERATION CIRCUIT DESCRIPTION

Rectifiers - All four rectifiers are operational amplifiers Pin 1 • VCON - Provides three voltage states depending on
with the noninverting input connected to VREF. The cir- input conditions. The first is a low impedance voltage about
cuit contains the diodes internally to provide the func- equal to V+ ·.7 Volt. The second state is a low impedance
tion of a negative peak detector. Using the typical appli- voltage equal to voltage on Pin 2. The third state is a high
cation schematic of Figure 1, the "gain" of the rectifier is impedance state.
R2/R 1. The output is then filtered using another RC net-
work. The attack time is given by R3.C and the decay time Pin 2 • VOL - A high impedance input used to modify the
by (R2 + R3).C. control voltage (Pin 1) when in the low state.

High Pass Filter - This is a simple gain stage with a class Pin 3, 4 . MCR - Negative peak detector usually connected
AS output stage. Pin 14 is about 2.6 V above V'. This to microphone amplifier output. Gain, attack, and delay
amplifier is normally used as a high pass filter to reduce line times are externally set.
induced hum from the detection circuitry.
Pin 5 . NOISE - High impedance input used to buffer
Noise Control Circuitry - This function provides a signal speech plus noise input from microphone rectifier.
on Pin 8 related to the difference between Pins 5 and 6.
Pin 5 is usually connected to the filter network of the Pin 6 . TC - External RC network determines response
microphone rectifier. This signal represents the speech plus to background noise level. RC network determines rise
noise from the microphone. Pin 6 has an external RC net· time, internal circuitry will discharge network if Pin 6
work and functions as a detector for the noise level. The >Pin 5.
output on Pin 8 is the difference between Pins 5 and 6,
referenced to VREF. Pin 8 • SIGNAL - Provides voltage proportional to Pin 5,
Pin 6 output impedance is nominally 36 K ohms.
Comparators - 80th comparators have internally generated
offset of -lOmVolts nominally. With no difference between Pin 9, 11 . CMP A - Used to compare signal level to level
the inputs, the output will be in the low state. The amount of speaker signal.
of offset can be increased by connecting a -resistor between
the threshold adjust pin and V-. .pin 10 . TH A - Used 'to increase offset of comparator A.
With TH A open, offset is approximately -10 mV.
Control Logic - The purpose of the logic is to derive the
three speakerphone states, depending on Comparators Pin 12, 13 . R - Negative peak detector normally connect-
A and B. The three states are: ed to speaker amplifier. Gain, attack, and decay times are
externally set.
1) Transmit + Pin 1 = V+ -O.7V
2) Receive + Pin 1 ~ Pin 2 + O.lV Pin 14, 15· HPF - Inverting amplifier, normally connected
3) Idle + Pin 1 is High Impedance. as a high pass filter to reject low frequencies from received
signals into the control circuitry.
The truth table for the logic is:
Pin 16, 17 . RXR - Negative peak detector normally can·
Comj:arator State nected after line receive amplifier. Gain, attack, and decay
A 8 times are externally set.

0 0 Idle Pin 18· VREF - Internal 2 Volt reference.

0 1 Receive
1 0 Transmit Pin 20, 22 . CMP B - Used to compare transmitted and re-
1 1 Idle ceived signal levels.

Pin 21 . TH B - Used to increase offset of comparator B

with TH B open, offset is approximately -lO mV.

Pin 23, 24 . TXR - Negative peak detector normally con-

nected to transmit amplifier. Gain, attack, and decay
times are externally set.

2-70
XR-T6421

XR-T6421

CONTROL
LOGIC
•
v+

R2

Figure 1. Typical Application Schematic

2-71
 f..Xt(IR XR-T6425

Speakerphone Ie
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T6425 speakerphone IC is a low cost solution for

the implementation of a hands-free telephone. It is a con-
venient way of carrying on conversation without using the RXT J

handset. while the user is talking into a microphone and

listening from a loudspeaker located on the desk. It is ideal
for hands-free conference calls.
TXM OUT

The XR-T6425 contains most of the circuits to eliminate

singing and excessive background noise in a single chip
solution.
TxLOUT

Tx GNF

TXG OUT

TXS IN

FEATURES DTMFIN

Low Operating Voltage (4.5 V) VOL

Single Chip Speakerphone
No External Adjustments GND Tx eOMP
Smooth T/R Switching
Background Noise Detection and Suppression BIAS
On-chip Hybrid Circuit
Vee Vo NET

TXTJ TXT 4

APPLICATIONS
ORDERING INFORMATION
Speakerphones
Intercoms Part Number Package Operating Temperature
Voice Operated Switches XR-T6425CN Ceramic O°C to 70°C
XR-T6425CP Plastic O°C to 70°C

SYSTEM DESCRIPTION

The XR-T6425 single chip speakerphone IC is designed to

operate from the phone line and allows hands-free opera-
ABSOlUTE MAXIMUM RATINGS tion. The chip contains most of the necessary circuits to
reduce external component count and performs half-
Power Supply 16V duplex operation. The internal circuits consist of a trans-
Power Dissipation 700 mW mitter. receiver and control logic. DTMF input is provided
Operating Temperature O°C to 70°C for Touch Tone operation. An adjustable threshold circuit
Storage Temperature -55°C to 150°C is provided to separate voice from ambient noise.

2-72
XR-T6425

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 5 V, f = 1 kHz, unless otherwise specified.

SYMBOL PARAMETERS TYPICAL VALUE UNIT CONDITIONS

VCC Operating Voltage 4.5 - 6.5 V

•
IC Operating Current 8.0 mA No I nput of T fR Signal

RXS Receiving Sensibility -64 dBm

TXS Transm itting Sensibi lity -74 dBm

GVRX Receiving Gain -22.5 dB Receivin!=J Mode

GVTX Transmitting Gain 44 dB Transmitting Mode

VINLIM Mic Input Level -55 dBm THD = 1%

AttRX Receving Loss -50 dB Receiving

Transmitting Relative Value

AttTx Transm itting Loss -50 dB Transmitting

Receiving Relative Value

Figure 1. Circuit Board Layout

2-73
 XR-T6425

PIN DESCRIPTIONS

Pin Symbol Description

Transmitter stabilization 26 TXMOUT Transmit buffer output.

time constant.
27 Transmit buffer input.
2 Receiver stabilization time
constant. 28 Receiver stabilizer.

3 Receiver output.

4 RX COMP T /R comparator input for

receiver.

5 Receive buffer output.

FUNCTION DESCRIPTIONS
6) Receive buffer inputs.
Transmitting Sections
8 Transmitter holding time
constant. The transmit path is .divided into five sections: buffer,
limiter, bandpass filter and amplifier, current control
9 Receiver holding time attenuator and mixer.
constant.
Buffer
10 T T /R switching time constant
The buffer is used to do impedance matching and gives 9
11 GND Ground dB gain to signal.

12 BIAS Mid-point of the supply Limiter

voltage (VCCf2).
The output of the buffer is fed to limiting amplifier to
13 VCC Most positive voltage. increase the signal level. The gain can be set with
two external resistors R4, R5 to obtain proper signal level.
14 Voice rectifier time
constant. Bandpass Filter and Amplifier

15 Ambient noise and voice Filtering is performed in this section to eliminate un-
discriminator time constant. wanted signals. Gain of 20 dB is set for this section and
output of this amplfier is capacitor coupled to control
16 VONE Hybrid network output. Igoic to eliminate DC components for decision making.

17 VIN NET Hybrid network input. Current Control Attenuator

18 TX COMP T fR comparator input for The current control attenuator is used to do smooth
transmitter. switching between transmitter and receiver to perform
half-duplex operation.
19 VOL Transmit signal output.
Mixer
20 DTMFIN DTMF input terminal.
Additional input is provided for DIMF signaling and driving
21 TXSIN Voice detector output. transmitting signals to telephone line throuqh impedance
matched resistance R 14 (680Q), and simu Itaneously
22 TXG OUT Transmit amplifier output. inputs to the hybrid network for cancelling signals to
receiving circuit.
23 TXG NF Transmit amplifier input.
Receiving Section
24 TXLOUT Transmit limiter amplifier
output. Incoming signals are amplified by AMP H and AMP F
after passing through hybrid network. The result is
25 Transmit limiter amplifier fed to current control attenuator to control output
input. 2-74 level.
XR-T6425

Ambient Noise and Voice Discrimination Section Hybrid Network

This section d iscrim inates voice signals from ambient Hybrid network is used to attenuate transmit signal
noises of input signals from microphone at transmtting going to the receive path. Equivalent circuit is shown
mode and gives the instruction signals to keep transmitting below.
mode or changes the mode to T/R signal attenuator circuit
through timer circuit.

•
Controller Section

This section compares transmit signal level (pin 18) with

receive signal level (pin 4) according to the time settled
by C31. R30. C30. R29. the result is applied to the timer
circuit which is triggered with the resistor value of R3
connected from Pin 28 to Ground.

Timer Section
Figure 2. Equivalent Circuit
This section generates the signals to T /R signal attenuator TIMING CALCULATIONS
circuit and provides the time constant for T/R switching.
Transmit Rise Time = C22 x 10 4 4.7 IlF. T= 47 ms
Transmit time constant is set by pin 8. receive time con- Transmit Hold Time = C22 x R22 4.7 IlF. 470K. T = 2.2S
stant is set by pin 9. and T/R switching time constant is
determined by pin 10. Pin 10 outputs 2.5V at transmit Receive Rise Time = C21 x 10 3 .47 IlF. T = .47 ms
mode and +1.2V at receive mode. Receive Hold Time = C21 x R21 .47 IlF. 470K. T = .22S

DESCRIPTION OF AMPLIFIERS

Application Gain Remarks

A TX amplifier o dB For the impedance conversion (emitter-

follower microphone) (Zin = 20 kil)

B TX amplifier R5/R4 Negative input limiter amplifier. clamping

LYE
at..r-;- of Pin 24 output. (VO = 700

mVrms)

C TX amplifier 20 dB Fixed gain amplifier.

D TX amplfier TX: 20 dB Gain varies with transmitting (TX). re-

ST: -5 dB ceiving (RX) and standby (ST).
RX: -23 dB

E TX amplifier R11/R10 Output gain - the signal applied as a nega-

tive input when DTMF is used.

F RX amplifier R25/R26 Differential input amplifier. Its output is

connected to C.C.A. (amp G) through
pin 5 and ATT.

G RX amplifier TX:-23dB Gain varies with transmitting (TX).

ST: -5 dB receiving (RX) and standby (ST).
RX: 20 dB

H RX amplifier 7.5 dB For the network loss correction of re-

ceving (RX) side.
2-75
 XR-T6425

TYPICAL CHARACTERISTICS

XR·T642S RECEIVING ALC CHARACTERISTICS XR·T642S RECEIVING FREQUENCY CHARACTERISTICS

Vee = S.6V. APPLYING 12V BETWEEN L1 AND L2 Vee = S.6V. APPLYING 12V BETWEEN l1 AND L2

10000 10

~: -
III III I V..,.. ~
l/ V
" '" r,1\
~
1000
iii -10
:s!. ~V I\..
5
l .... ~
V
~ -20 //
100
V W r,
-30

"'"
10 -40
1 10 100 1000 .1 10
VIN (mV) Freq (kHz)
AC xB OA x BEFORE MOUNTING C32 0 AFTER MOUNTING C32

XR·T642S TRANSMITIING FREQUENCY CHARACTERISTICS XR·T642S MICROPHONE AMPLIFIER LIMITER CHARACTERISTICS

Vee = S.6V. APPLYING 12V BETWEEN L1 AND L2 Vee = S.6V. APPLYING 12V BETWEEN L1 AND L2

10
11111 3. 5
1
~~ rrn 9 dB

9 dB/oct
11111
10000

/ ad B/oct
" "I
9 db/oct.;" V ~"'"
" -1 L
I
~
I I
~ ~ I
I I'
V./ d~ I' 1000
iii -10 3.5
>
:s!.
a dB/oct II'
~ 1\ £
5 50 ~.....t"'L-o ~ I
~ -20 -1~ dB/oct > ,L fA' I I,
100

-30

, I I II III
-40
10 100

,*' INDICATION VALUES OF M3

Freq (Hz)
1000 10000
10
1 10

x 'INDICATION VALUES OF M2
I I I " II100I
VIN(mV)
0 INDICATION VALUES OF M3
"'
1000

2-76
 ><
:uI
V,S BAND-PASS FilTER
AND SENSIBILITY ADJUSTMENT -I

~CJ1
II

$URG£
I'RQncnoN
lNR IIII
R2 l2
....
2.2K

C2
HOSHIDEN 0.047
KUC-1523
~l--0O1
LOW PASS
FILTER

RX
STABDJZ(R

SP
32!l
C33
10 +
I\)
.!.J
-...J

RESISTANCE: U. CAPACITANCE;,.F

Figure 3. Typical Line Powered Application Circuit

I
 XR-T6425

I 101
I"'-. VOLUME
CONTROL

CH

ZNR

D D
L2 L1

Figure 4. Simplified Application Schematic

2-78
 Section 2 - Telecommunication Products
Telephone Set Circuits . . . . . . . . . . . . . . . 2-79
XR-T5990 Single Chip Pulse/Tone Dialer 2-80
XR-T5992 Pulse Dialer 2-87
XR-T5995 Speech Network 2-93
XR-T8205 Tone Ringer 2-97

2-79
 XR-T5990

Single Chip Pulse/Tone Dialer

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5990 Single Chip PulselTone Dialer is a silicon

gate CMOS technology circuit which performs both pulse
and tone functions.

It is designed to operate directly from the telephone line

or on a separate small power supply. A 17 digit buffer is
provided for red ial feature.

FEATURES

Pin Selectable PulselTone Dialing

Low Standby Current
17 Digit Redial Buffer
Uses TV Crystal Standard 3.58 MHz or Ceramic Resonato~
to Provide High Accuracy and Stability
3.5 Second Pause Timer
Regulated Tone Amplitude
Pin Selectable Dialing Rate (10 pps/20 pps)
Pin Selectable Break- Ratio (63%/66%)
I nterface Directly to a Standard Telephone Push Button
or Calcu lator Type X- Y Keyboard
Generates 12 Standard Tone Pairs
Single Tone and Dual Tone Capability

ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T5990CP Plastic O°C to 70°C
XR-T5990CN Ceramic O°C to 70°C
APPLICATIONS

Electronic Telephones
Smart Auto Dialers (modems)
Electronic Banking
Security Controller
Radio Communications
SYSTEM DESCRIPTION

The XR-T5990 Pulse/Tone Dialer is a CMOS integrated cir-

cuit that can provide recall of previously entered numbers
as well as perform the normal dialing function. Dialing is
interchangeable from pulse to tone or vice versa, capable
ABSOLUTE MAXIMUM RATINGS of inserting 3.5 second pause between digits for PABX
dialing.
DC Supply Voltage VDD 6V
Operating Temperature O°C to 70°C The XR-T5990 dialer is capable of dialing * and # func-
Input Voltage -.3 ~ VIN ~ VDD +.3 tions in tone mode and ignore in pulse mode. Selectable
Maximum Power Dissipation 500mW dialing rate is provided for rapid dialing.

2-80
XR-T5990

ELECTRICAL CHARACTERISTICS
Test Conditions:

SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS

DC CHARACTERISTICS 0 °c ~ T ~ 70°C, VOO = 3.5 V

VOO DC Operating Voltage 2.5 6 V

VREF

VM

lOp
Magnitude of (VOO-VREF)

Memory Retention Voltage

DC Operating Current
1.5

1.5
2.5 3.5

4.2
V

mA VOO = 3.5 V, Outputs Unloaded

II
IS DC Standby Current 1.5 IlA VOO = 3.5 V, Outputs Unloaded
500 nA VOO = 2.5 V, Outputs Unloaded
IML Mute Sink Current 10 mA VOO = 3.5 V, VOUT =.5 V

Ip Pulse Sink Current 20 mA VOO = 3.5 V, VOUT = .5 V

KL Keyboard "0" Logic Level VSS 20% of V
VOO

KH Keyboard" 1" Logic Level 80% of VOO V

VOO

KpU Keyboard Pu II-up Resistance 100 Kf2

KpO Keyboard Pull-down Resistance 4 Kf2

HSRU Hookswitch Pull-up Resistance 100 Kf2

Cfosc Oscillator Stability .05 % VOO 2.5 to 3.5 V

SF Keyboard Scanning Frequency 932 Hz

dBCR Ration of Column to Row Tone 2 3 dB

%OIS Distortion 6 7 %

VOR Single Tone

Row Frequency Alnplitude 212 mVRms RL = 330f2

VOC Single Tone

Column Frequency Amplitude 311 mVRms RL = 330f2

TOB Keyboard Oebound Time 11.8 ms

KT Keydown 40 ms

RT Tone Load Resistor 120 400 n

2-81
 XR-T5990

PIN AND FUNCTION DESCRIPTIONS

Pin Number

Supplies VDD, VSS 1,13 Dial Pulse Out 16

Power Supply Inputs - The device is designated to operate An output drive is provided to turn on a transistor at the
from 2.5 to 6 volts. dial pulse rate. The normal output will be "low" during
"space", and "high" otherwise.
2
Mode Select 17
The VREF output provides a negative reference voltage
relative to VDD, which defines minimum operating vol- State of this pin selects the proper dialing mode. Tone dial-
tage. In a typical application, this pin is simply tied to VSS. ing is selected by connecting this pin to VSS.

Keyboard Inputs Hookswitch 18

C1, C2, C3 4,5,6 HS

R1, R2, R3, R4, R5 24,23,22,21,20
This input detects the state of the hookswitch contact.
These inputs are open when the keyboard is inactive. When The XR-T5990 will accept key inputs when this pin is at
a key is pushed, an appropriate row to column input must low state (off hook).
go to VSS or connect with each other.
Single Tone Inhibit 8
Oscillator

OSCIN,OSCOUT 11,12
Single tone output can be inhibited when this pin is con-
These pins are provided to connect external crystal or cera- nected to VSS.
mic resonator. The device contains the necessary parasitic
capacitances and feedback resistor on chip so that is is only Tone Out 3
necessary to connect a standard 3.58 MHz TV crystal.
This N-channel open drain output is designed to drive ex-
Dialing Rate 9 ternal transistor.

DRS Pacifier Tone Output 7

Dialing Rate is programmable by connecting this pin to PT

VDD or VSS· The rate is 20 pps when connected to VDD
and 10 pps when connected to VSS. The XR-T5990 provides a pacifier tone output to provide
audio feedback to the user that a key has been depressed.
Mark/Space 19 The output is a 1800 Hz tone that can be capacitvely
coupled into the telephone receiver.
MIS
This option is provided in dial pulse mode only.
Mark/Space ratio may be selected by connecting the pin
to VDD or VSS.

MIS Pin (19) MARK SPACE

VSS 37% 63%
VDD 34% 66%

Mute 10

This N-channel open drain output is designed to driveexter-

nal bipolar transistor to mute the receiver during dialing.

2-82
XR-T5990

FUNCTIONAL DESCRIPTION CIRCUIT DESCRIPTION

Keyboard The XR-T5990 is capable of Qeneratin!=! 12 standard tones

in the tone mode. Low group frequencies consist of 697,
The XR-T5990 employs a scanning technique to determine 770, 852, 941 Hz and the high group consists of three fre-
a key closure. This permits interface to DPCT keyboard quencies 1209, 1336, and 1477 Hz
with common connected to VSS or SPST switch matrix
connecting row to column. A keyboard arranged in a row, column format is used for

•
number entry. When a push button corresponding to a digit
A logic interface is also possible as shown in Figure 1. is pushed, one appropriate row frequency, and one appro-
priate column frequency are selected. The appropriate row
COL _ _
1. 0----- ROW
and column frequencies in the keyboard arrangement are
vss-c1-COL shown below.
SPST SWITCH
O---ROW
2 OF 7 MATRIX KEYBOARD WITH NEGATIVE COMMON
Active Specified
Input Frequency
-{:>o-COL

DPCT KEYBOARD R1 697

-{:>o-ROW
R2 770
Figure 1. ,
LOGIC INTERFACE R3 852
Hookswitch R4 941
C1 1209
The XR-T5990 will enter in off hook mode when hook- C2 1336
sNitch is pulled low. This state enables the device to accept C3 1477
a valid key and enable the oscillator.

Mute Output Table 1.

The mute output turns on (pulls to !he VSS supply) at the

beginning of the mark, and turns off (goes to an open
circuit) following the last interdigit pause. A small delay is 1 2 3
provided to overlap mute output from the end of the last
interdigit pause. 4 5 6

Redial 7 8 9

The last number dialed is retained in the memory, and * 0 #

therefore can be redialed out by !=!oing off hook and press-
ing the redial key.
Table 2.
Dialing will start when the key is depressed and finish after
the entire number is dialed out unless an access pause is H,~~ _____________________________
detected. If this is the case, the dialing will stop, and re-
sume again after 3.5 seconds. During redial mode, tone will
be on for 70 ms and off for 70 ms.

Normal Dialing MODE

Normal dialing can start after gain!=! off hook, since the de-
____ ~rurn~ __________________
vice is designed in a FIFO arrangement, digitascan be
entered at a rate.considerably faster than the output rate. LJLJ: :
~:900nlSI~

Digits can be entered approximately once every 65 ms.

Pauses may be entered when required in the dial sequences TONE -----------------~
by pressing pause key which provides access pause for fu- -170 m. , -

ture redial.

During normal tone dialing, tone will go out at 70 ms

burst. Continuance sinale tone can be qenerated by de-
pressing two diqit keys in the appropriate row or appro- Figure 2. XR-T5990 Timing Diagram
priate column.

2-83
 XR-T5990

OPERATING DESCRIPTION

Normal Dialing Tone or Dial Pulse Output

Off Hook, @}] ,~ , ...... ~ ........... @Eil

Normal Oialinq using Pause Function

Off Hook, [QlJ ~ [Ql] . ...... ~ [QD [Q1] IQ1l . . . . . . . . . . . . .. ~

Redial

On Hook, Off Hook, I]QJ [[D[@~ .... .... IoN]

Dialing will halt for 3.5 seconds when a pause is detected. @] 13.5 sec\ (@ . .. .. @ill
Redial and Normal Oialina Combination

On Hook, Off Hook, ~ , 10181 ' 10191, 102ol.@B] @2] ... 10171 (0181 ............... ~
3.5V
,~

1
Voo
4 - 18 .....,.. ~
Cl Hs

5
-
C; 17 ~
MODE ~

6 -
C3 -
I 24
MIS
19 _ ..,!r-
""
1 2 3 Rl

4 6
23
R; 9 ~
5 DRS "V'"

22
7 8 9 R; XR·T5990 8 .sr-
* 0 #
21
R.;
STI "V'"

->1
PA RD
20
~ 750K~ ~750K
16 0( <C
'-- ~
PULSE :::> PULSE

~
10
OSCI MUTE MUTE

0
3.58MH z
PT
7
C> PT
~ OSCo
3
TONE :::> TONE
13
<'
~390n
<Ij

--
Figure 3. XR·T5990 Test Circuit
2-84
XR-T5990
+5

4
+5 C,
5 HS lB
+5 16 C;
6 - XR·T5990
15 A C3
+5
MIS 19
DRS 9

•
5K 14 B 24
~ Sii B
23
T 1
74C42 R; MODE 17
22 R; 13

2T 2
21 R;
13
XR·2240 11 OSC l
4T 3
~~~D 12
OSCo
BT 4 TONE
3
+5
16T 5
RESET +5
C
9
15 A R
C

-= 14 B

74C42
13
C 600n

12 11
D

30K

Figure 4. Typical Application Circuit for Auto Dialer Modem

R;

~,o------.

~z 0--+-----'

Al eeOKII AS' 3KII 01 2N540l 01 lN4004 Cl 6S"F

A2 l4KlI Al0' l00KII 02 2N5650 02 ·1N4004 S1 HOOK SWITCH
A3 470KII An • 20KII 03 2N5550 03 lN4004 S2 HOOK SWITCH
Ae 33011 05 2N540l 04·1N4004 Zl l20V 1 WATT ZENER
AS l20KII DR' ~EO

Figura 6. Typical Tone Dialing Application Circuit

2-85
 XR-T5990

R.

r~Tn+-__+-~~~~~
I
I
I I
MIS 19
1 ---
L __________ .J
DRS 9
TYPICAL "500" TYPE
SPEECH NEtwORK
V.. 13

Rl ~ 56OK1I R7 ~
lDDKlI 0, 2N5401 Ci = lN4004 Cl "6S.F
R2 ' 14KlI RS ~
3KlI 02 2NSS50 02 ~ lN4004 S1 ~ HOOK SWITCH
R3 - 470KlI Rg 3KlI
~ 03 2NSSSO 03 lN4004 S2 :. HOOK ."WITCH
R4 33011 R10 ~
lDDKlI 04 2NS401 04 - lN4004 Z, ~ 120V 1 WATT ZENER
Rl1 ~ 20KlI 05 2N540~ 06 LED
07 - lN4004

Figure 6. Typical Pulse Dialing Application Circuit

+5

RESET

+5
18
20
74LS240 HS VOO

18
Do c;- STI
+5
50K
16 17 o PULSE
0, C2 MODE
10K
~ONE
14 6 - 16
02 C3 PULSE

12 24
03 R1 TONE
I.F

04

Os
23

22

21
iii

R3
OSC, 11

oseo
DIALING LOOK UP TABLE
::
Os R4 DRS
-= DECIMALS
(1)
HEX
(09)
20 19 (2) (OA)
07 AS MIS
(3) (OC)
10 (4) (11)
VREF VSS (5) (12)
1.19 13 (6) (14)
-= (7)
(8)
(21)
(22)
CS,
(9) (24)
(0) (42)
(0) (41)
-= (II) (44)

Figure 7. Typical Microprocessor Interface Circuit

2-86
~ EXlIR XR-T5992
ADVAr~ CED Ir~ FOR MAT I0 rJ

Pulse Dialer
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5992 pulse dialer is a silicon gate CMOS inte-

grated.circuit which converts push·button inputs into pulses
to simulate a rotary telephone dial.

It is designed to operate directly from the telephone line

and to meet telephone specifications. A 17 digit buffer
is provided for redialing feature. The XR-T5992 is available
in a 18 pin package.
II

FEATURES

Direct Telephone Line Operation

Redial with Either a * or #.Input
Pin Selectable Mark/Space and Dialing Rate
Inexpensive RC Oscillator
Interface Directly to a.Standard Tel'ephone
Push-button or Calcu lator Type X- Y Keyboard
Mute Driver on Chip
Pin-to-pin Compatible with MK50992

ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T5992CP Plastic O°C to 70°C
XR-T5992CN Ceramic O°C to 70°C
APPLICATIONS

Electronic Telephones
Smart Modems (Auto Dialer)
Security Controller

SYSTEM DESCRIPTION

The XR-T5992 Pulse Dialer is a CMOS integrated circuit

ABSOLUTE MAXIMUM RATINGS that can provide recall of previously entered numbers as
well as perform the normal dialing function. It is capable
DC Supply Voltage V+ 6.2 Volts of receiving keys faster. than dialing rate. XR-T5992 is in-
Operating Temperature OOC to 70°C tended as a replacement for the mechanical telephone
Input Voltage -.3 < VIN < VDD +.3 dial and can operate directly from the telephone line.
Maximum Power Dissipation 500mW Selectable dialing rate is provided for rapid dialing.

2-87
XR-T5992

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

DC CHARACTER ISTICS: OoC ~ T ~ 70°C

VOO DC Operating Voltage 2.5 6.0 V

VREF Magnitude of (VOO-VREF) 1.5 2.5 3.5 V I Supply = 150 J.l.A

lOp DC Operating Current 100 150 J.l.A

IMR Memory Retention Current .7 2.5 J.l.A

IML Mute Sink Current .5 2.0 mA VOO = 2.5 V, Vo =.5 V

IMH Mute Source Current .5 2.0 mA VOO = 2.5 V, Vo = 2. aV

Ip Pulse Sink Current 1.0 4.0 mA VOO = 2.5 V, Vo =.5 V

KL Keyboard "a" Logic Level VSS 20% of V

VOO

KH Keyboard ''1'' Logic Level 80% of VOO V

VOO

KRU Keyboard Pull-up Resistance 100 Kn

KRO Keyboard PUll-down Resistance 4.0 Kn

HSRU Hookswitch Pull-up Resistance 100 Kn

fOSC Oscillator Frequency 4.0 KHz

t.fOSC Oscillator Stability ±4 % VOO = 2.5 to 3.5 V

TOS Keyboard Oebounce Time 10 ms

TMO Mute Overlap Pulse 5 ms

SF Keyboard Scanning Frequency 500 Hz

2-88
 XR-T5992

PIN AND FUNCTION DESCRIPTIONS

Pin Number

Supplies VDD, VSS 1,6 Dial Pulse Out 18

Power Supply Inputs - The device is designed to operate Output drive is provided to turn on a transistor at the dial
from 2.5 to 6 volts. pulse rate. The normal output will be "low" during
"space", and "high" otherwise.
2

The VR E F output provides a negative reference voltage

relative to VOD, which defines minimum operating voltage.
I n a typical application this pin is simply tied to VSS.
Hookswitch/Test 17

This input detects the state of the hookswitch contact.

The XR-T5992 will accept key inputs when this pin is at
II
low state (off hook).
Keyboard Inputs
C1, C2, C3 3,4,5
FUNCTIONAL DESCRIPTION
R1, R2, R3, R4 16,15,14,13

These inputs are open when the keyboard is inactive. When

a key is pushed, an appropriate row and column input
The VREF output provides a reference voltage that tracks
must go to VSS or connect with each other.
internal parameters of the XR-T5992. VREF provides a
negative voltage reference to the VOD supply. Its magni-
A logic interface is also possible as shown in Figure 2.
tude will be approximately 0.6 volt greater than the mini-
mum operating voltage of each particular XR-T5992. For
Oscillator and keyboard scanning starts when a key is
normal use this pin is connected to VSS.
pressed.

Oscillator
Rf, CO, RO 7,8,9 7.0

These pins are provided to connect external resistors

and capacitor to form an R-C oscillator. 6.0

Oialing Rate Select

ORS 10 5.0

Dialing rate is programmable by connecting this pin to IREF 4.0

VDD or VSS. The rate is .20 pps when connected to VOD, MA
and 10 pps when connected to VSS.
3.0
Mark/Space Select
M/S 11
2.0
Mark/Space ratio may be selected by connecting the pin
to VOO or VSS. 1.0
M/S Pin (11) Mark Space

VDD 34% 66% 1.0 2.0 3.0 4.0 5.0

(V+ )-VREF VOLTS

VSS 40% 60%

Figure 1. VREF Typical I-V Characteristics
Mute 12

This N-channel open drain output is designed to drive an

external bipolar transistor to mute the receiver during
dialing.

2-89
XR-T5992

Keylioard On Hook/Test

The XR-T5992 employs a scanning technique to determine The hookswitch input of XR-T5992 has a 100 Kn pull-up
'a key closure. This permits interface to a DPCT keyboard to the positive supply. A positive input or allowing the pin
with common connected to VSS or SPST switch matrix to float sets the circuit in its on hook, or test mode. Switch-
connecting rows to columns. ing the XR-T5992 to on hook while it.is outpulsing causes

COL~ L--ROW
V_liL-cm the remaining digits to be outpulsed at 100x the normal
rate. This feature provides a means of rapidly testing the
device.

~ L . . - ROW
Off Hook

,I
FORM A TYPE KEYBOARD
2·0F·7 MATRIX KEYBOARD
The XR-T5992 will enter in off hook mode when hook-

~~~co,
switch is pulled low. This state enables the device to accept
a valid key and to turn the oscillator on.
,-co,

~ROW v-
Mute Output
v+---, r--ROW
L...J The mute output turns on (pulls to the VSS supply) at the
beginning of the interdigit pause, and turns off (goes to an
2·0F·7 MATRIX KEYBOARD ELECTRONIC INPUT open circuit) following the last break. A small delay is pro-
vided to overlap mute output from the end of last break.
Figure 2. Keyboard Configurations
Pulse Output
Oscillator
The pulse output is an open drain N-channel transistor
The device contains an oscillator circuit that requires threE designed to drive an external bipolar transistor. These
external components: two resistors and one capacitor. All transistors would normally be used to pulse the telephone
internal timing is derived from this master timebase. For a line by disconnecting and connecting the network.
dialing rate of 10 pps, the oscillator should be adjusted to
4000 Hz. Typical values of external components are Rf = The XR-T5992 pulse out is an open circuit during mark and
2Mil, Ro = 220 Kil, Co = 390 pF. pulls to the VSS during break.

The oscillator frequency can be determined by the follow- Redial

ing equation:
The last number dialed is retained in the memory and there-
T=RC T1.386 +(3.5KCS)/C -2(2K/(K+1))LN (K/1.5K+.5))] fore can be redialed by going off hook and pressing the' *
or # key. Dial pulsing will start when the key is depressed
where Cs is the pad capacitance on pin 7 optimum stability and finish after the entire number is dialed.
occurs with the ration K = R F/RO equals 10.

DISABLE

RO

Figure 3. Oscillator Circuit

2-90
 XR-T5992

+
POWER
SUPPLY

XR-T5992
OFF
18 750KQ HOOK 750KV
VOO PULSE:
2 HS 17
VAEF
3 16
R1
FROM {
KEYBOARD

6
VSS
2M
RF
MUTE~~--------------+---r-~

Co 60% BREAK
11
220KQ 9 M/S~--------~y
RO tDP

10ppS 0----_

Figure 4. Test Configuration

DIGIT DIGIT REDIAL

1 3 • OR"
KEY INPUT~ L ..j'r----------
COLUMN SCAN ~_-~O.£.':!!~~L~~N-S~~N- ~- ____ ---~

ROWSCAN'-.h.n..n.nn..J___ ~...!i!.~~'§"C.6.N__ ~_______ ..ruu----

HOOKSWITCHINPUT--i !~ j~ i
MUTE OUTPUT 1 ::
o II

I I
PULSE OUTPUT I : : (~ , I

: :: J J J ; ; . ; :

o::~'::::rr::~]~~~~-+nr-~~~!;:K---r[ TEST
TYPICAL TIMING VALUES MODE
TpDP BOOms T'DP BOOms TMo 5mg

Figure 5. Timing Characteristics

2-91
 ><
:J:J
I
-I
(II
CO
CO
I\)

y Ag

DG
AJ

VOO

A" MUTEr,;
PULSE 18

I ~ft2 I
I\)
A.
cO
I\) C2

Co

An ~ Cl I A, 5- I'IBP
In As
AO

R.
MIS' 11
17 I
VREF
IDPr1
Vss n TYPICAL --500-- T E
SPEECH NETWOY:K

Al '56Ok<.1 R7 = l00l<Q 01 2N5401 01 lN4004 Cl 6/!j. (Low Leakagel

A2 14k<.1 AS = 3k<.1 02 2N5550 02 lN4004 C2 390pF
A3 470k<;[ R9 = 3kQ 03 2N5550 03 lN4004 SI HOOK SWITCH
R4 33Ok<.1 R10 = l00kQ 04 2N5401 04 lN4004 S2 HOOK SWITCH
AS 2M2 Rl1 = 20MQ OS 2N5401 D6 LED 11 120-yoI11-wat1zf'ner
1'6 2201<:'..1 07 lN4004

Figure 6. Typical ApPlication Schematic

 XR-T5995

Speech Network
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-T5995 Speech Network is a monolithic integrated

circuit specifically designed for implementing a low cost

•
telephone set circuit. It is designed to use a electrodynamic
microphone and electromagnetic receiver to replace a car-
bon microphone and telephone network hybrid.

FEATURES

Interfaces with Inexpensive'Condenser Electret

Microphone, Electromagnetic Receiver
Low Voltage CMOS Process to Operate from 20 mA
to 100 mA Loop Current
Minimum External Component Counts
Uses I nexpensive and Non-critical External Components
A DTMF Input for Tone Dialing
External Mute Capability

APPLICATIONS ORDERING INFORMATION

Low Cost Telephone Set Part Number Package Operating Temperature

Trimline Phone XR-T5995CP Plastic OOC to 70°C
Line Monitor XR-T5995CN Ceramic OOC to 70°C

ABSOLUTE MAXIMUM RATINGS SYSTEM DESCRIPTION

The XR-T5995 Speech Network contains all the necessary
DC Supply Voltage VDD 15 V circuits to perform hybrid operation. (On board micro-
Operating Temperature OOC to 70°C phone, receiver amplifier and driver, external muting for
Power Dissipation 1100mW tone dialing or pulse dialing.) A DTMF is provided to inter-
Storage Temperature -55°C to 125°C face to Touch Tone dialing.

2-93
XR-T5995

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

VL Operating Voltage 2.7 9 V 1=20-100 mA

IL Operating Current 15 100 mA

GT Transmitter Gain 39.5 43.5 47.5 dB VIN = 3 mY, I = 1 KHz

DT Transmit Distortion 2.5 6 % VL::: 1.2 Vp/p,1 = 1 KHz

NT Transmit Noise Level -76 dB VM=O

OT Transmit Output 2.3 Vp/p

GR Receiver Gain -14.8 -10.8 -6.8 dB VL = 100 mV,I= 1 KHz

DR Receive Distortion 2.7 6 % VR = .3 Vp/p, f = 1 KHz

NR Receive Noise Level -78 dB VL= OV

OR Receiver Output Level .6 Vp/p

ZNET Network Impedance 350 750 n VL = .5 Vp/p, f = 1 KHz

ST Side Tone 5 8 dB

GDT DTMF Gain 10 14 18 dB VDT = .03 V, f = 1 KHz

GAT Audible Tone Gain -7 -3 +1 dB

ZT Transmit Input Impedance 12 Kn

ZR Receive Input Impedance 100 n

2-94
 XR-T5995

PIN AND FUNCTION DESCRIPTIONS

Pin Number

GND TONE IN 9

Most negative supply terminal. External pacifier tone input, to provide audio feedback

•
to the user that a key has been depressed in dial pulse
2,3 mode.

Current sense input, allows loop loos compensation for re- RC .. RIN 10,11
ceiving or transmitting amplifiers.
Input, output of receiving amplifJOr.
LINE IN 4
MUTE 12
To hold DC current and AC input impedance matching seen
on the phone line. External mute input is provided to mute the line receive
amp and to insert the tone to the receiver.
AGC 5
DTMF IN 13
Automatic gain control unit to set transmit and receive
ar1plifier gain and attenuation on different line loop This input is used with a Touch Tone dialer to insert the
currents. DTMF signal to the line.

VDD 6 14,15

Most positive regulated supply terminal. Microphone input, output to transmitting amplifier.

OUT (-1). OUT (+) ST 16

Differential output driver, used to drive a speaker or an Sidetone compensation input.

electromagnetic receiver.

2-95
 R9

C3
~, __ I 10K
ODTMF
. . . - - - + - - - - - + - - - - - - + - - - - - 0 MUTE

C8
0.1

C1
2200p

(0
CJ)
c\r

SP
200
+

ECM
+
It)
0) IN4004

0)
It)
(RESISTOR n: CAPACITOR J-LF)
l-
I
a:
><
 EX'!IR XR-T8205

Tone Ringer
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-TB205 Tone Ringer is primarily intended as a re-

placement for the mechanical telephone bell. The device

•
can be powered directly from telephone AC ringing voltage
or from a separate DC supply. An adjustable trigger level
is provided with an external resistor.

The XR-TB205 is designed for nominal 15 volt operation

and is available in an 8 pin D I L package.

FEATURES

Low Supply Current

Operates Directly From Telephone Line
Provides Single or Dual Tone Frequencies to Simulate
Mechanical Bell
Operates from 15 to 30 Volts
Pin-to-Pin Compatible with MITEL ML8205

ORDERING INFORMATION

Part Number Package Operating Temperature

XR-T8205CP Plastic DoC to 70°C
XR-T8205P Plastic DoC to 70°C
APPLICATIONS

Electronic Telephones
Alarm or Other Alerting Devices
Power Line Indicator
Toys SYSTEM DESCRIPTION

The XR-T8205 Tone Ringer consists of two oscillator cir-

cuits, a dial reject filter and an amplifier to drive high impe-
dance audio transformer or plezo·eleetric transducers.

The power supply control circuit provides the hysteresis re-

quired to ensure positive triggering of the device and to pre-
vent transient triggering due to dial pulsing.

As the power supply voltage to the XR-T8205 is increased

ABSOLUTE MAXIMUM RATINGS up to the supply initiation voltage (VSll. oscillation begins.
The low frequency oscillator oscillates at a rate of FL con-
Storage Temperature -65°C to +150°C trolled by an external resistor and capacitor, connected
Operating Temperature DoC to 70°C between Pins 3 and 4. The output of F L is internally con-
Supply Voltage 30V nected to the switching threshold cicuitry of the high fre-
Input Voltage -.3 V <; V,N <; VDD +.3 V quencyoscillator.

2-97
XR-T8205

ELECTRICAL CHARACTERISTICS
Test Conditions: VOO = 17 V TA = 25°C, unless specified otherwise.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

VOO Operating Supply Voltage 15 17 30 V

10 Operating Current .7 1.2 rnA No Load

IS Supply Initiation Current 1.4 2.5 4.2 rnA No Load, RT = 6.8 kll
IT Trigger Current 10 20 1000 p.A

Vo Output Voltage 17 19 21 V No Load, VOO = 21 V

t.fo Oscillator Frequency

Tolerance 10 %

4.5

4.0

3.5

3.0

~
2.5
S
!!J 2.0

1.5

1.0

0 2 4 6 8 10 12 14 16 18 K~l

RT(KQI

Figure 1. SupplV Initiation Current (IS) VS RT

2-98
 XR-T8205

PIN AND FUNCTION DESCRIPTION

Pin Number

Supplies Ringing Oscillator 6, 7

VDD, GND 1,5 CH, RH High frequency oscillator external components.

When the output of the rate oscillator is high, the high

•
Power supply inputs - the device is designed to operate frequency oscillator oscillates at its normal rate, descri-
from 15 to 30 volts. bes by the relation FH == 1/(1.515 RHCHI where R is the
value of the resistor connected between Pins 6 and 7, and
Trigger In 2 C is the value of the capacitor connected between Pin 6 to
Ground. When the output of rate oscillator is low,
This pin is provided to adjust power supply initiation high frequency oscillator oscillation changes to FH =
current. 1.25 FL.

Rate Oscillator 3,4 Output 8

Rl, Cl low frequency oscillator external components. The output amplifier of the XR-T8205 is capable of driving
Oscillation rate is determined using the relation FL == a wide range of load impedances, when driven from a low
1/( 1.234 R l Cll where R is the value of the resistor con- source impedance power supply.
nected between Pin 3 and 4, and C is the value of the
capacitor connected between Pin 3 to Ground.

VDD

RATE OSC

RING OSC

Figure 2. Ring and Rate Oscillator Relationship

2-99
XR-T8205

8.2KS.'

.47JlF
9 1V 8 47S, 1,O •• F
I-=-~V----I
R Q-_ _ _-+-_...J
r---+-f----~2 ~XA- T8205 10KQ
3 6
4 5390KQ O,0027~F

160KQ 1..-_ _---1

220Q T,

II~
13K~?

1300Q 8Q SPEAKER

Figure 3. Typical Line Powered Tone Ringer Circuit

2 7

XA-l t!lU~ 170KQ

29" 3 6

150K
4 5

47.,F
25KQ

Figure 4. Typical Tone Ringer Circuit

Using Piezo·Electric

2-100
 Cross References & Ordering Information

Telecommunication Circuits

Computer Peripheral Circuits

~'n_d_u_s_tr_ia_l_c_i_rc_u_it_s_________________________ 1IIII
~ln_s_t_ru_m_e_n_t_at_i_on__C_ir_c_u_it_s____________________1IIII
~ln_t_e_rl_aC_e__C_ir_cu_i_ts__________________________ 1IIIII
~s_p_e_ci_a_I_F_un_c_t_io_n_C_i_rc_u_it_s____________________1IIII
User Specific Linear ICs
~-------------------------------------
II1II I

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

3
 Section 3 - Data Communication Circuits
Modems. . . . . . . . . . . . . . . . . .. . · 3-2
Modem Basics .. . . . . . . . . . . . . . . . · 3-2
XR-2121 Bell 212A Type Modulator . . . . . · 3-8
XR-2122 Bell 212A Type Demodulator 3-16
XR-2123/2123A PSK Modulator/Demodulator 3-26
XR-2125 Bell 212A Type Data Buffer 3-37
XR-14412 FSK Modem System 3-42
Filters . . . . . . . . . . . . . . . . . . . . 3-49
XR-2103 Modem Filter . . . . . . . . 3-50
XR-2120 PSK Modem Filter . . . . . . 3-55
XR-2126/2127/2128/2129 Bell 212A1CCITT V.22 Modem Filters 3-62
Line Interface Circuits . . . . . . . . . . . . . .. .. . 3-73
XR-1488/1489 Quad Line Driver/Receiver . . . . . . . . . . . . 3-74

3-1
Modem Basics
GENERAL INFORMATION MODULATION TECHNIQUES
The modem or modulator/demodulator serves as the inter- Many types of encoding formats are used in modems,
connecting link for digital equipment to communicate with the speed of the modem and type of media usually
over telephone or other wire media. As shown in Figure the determining factors. here the two most popular will
1 the modem encodes (modulates) incoming binary da- be discussed, FSK and PSK.
ta into signals suited for transmission over the available
media. FSK or frequency shift keying, illustrated in Figure 2, en-
codes binary data into two discrete frequencies.
Conversely on the opposite end, the other modem de-
codes (demodulates) the received signals from the line.
In this figure, Rxd2 (received data) would be identical to
that of Txd1 and Rxd1 equal to Txd2' That is a properly
operating modem receiving an encoded signal would ENCODING
reproduce at its output exactly what the transmitting STANDARD SPEED OPERATION TECHNIQUE
modem had at its Txd input. The modem initiating the
"conversation" is termed the originate and the receive 103 0-300 BPS Full-Duplex FSK
modem the answer. Figure 1 illustrates modems which 201 1200 BPS Half-Duplex PSK
202 1200 BPS Half-Duplex FSK
have the ability to communicate both directions, which
212A 0-300 Full-Duplex FSK
when able to do simultaneously is known as full-duplex 1200 PSK
operation. This same communication in both directions
but only one direction at a time is half-duplex operation. (A)
Communication in only one direction is simplex opera-
V.21 0-300 BPS Full-Duplex FSK
tion. These modes of operation can be likened to a tele- V.22 1200 BPS Full-Duplex PSK
vision for simplex, a CB which has to be keyed to talk for V.23 1200 BPS Half-Duplex FSK
half duplex and a telephone for full duplex where both 75 BPS
parties can talk at once. V.26 2400 BPS Half-Duplex PSK
(B)
Modem speeds of transmitting and receiving are speci-
fied in BPS (bits per second). This term describes the
Figure 2_ Popular Bell (A) and CCITT (B) Standards
number of binary data bits that can be transmitted per
second. For low speed modems, baud rate is inter-
changeably used in place of BPS. Low speed modems
are usually those with 0 to 1200 BPS, medium speed for
2400 to 9600 BPS, and those above 9600 BPS high
speed. Most modems are generally classified accord-
ing to which Bell (US) or CCITT (European) standard they
conform to. This standard indicates the modem speed,
operation and encoding technique used. Figure 2
shows the most popular low and medium speed stan- Figure 3_ FSK Encoding
dards used.

BINARY DATA TO BE PHONE LINE OR

TRANSMITTED OTHER MEDIA
L.J1.J1-
DIGITAL
EQUIPMENT
NO.1
L.fl..J"1.
TXD1
MODEM NO.1
/ \ '"
TXD2
MODEM NO.2
DIGITAL
EQUIPMENT
NO.2
IlP, TERMINAL
~
RXD1
fvwv'ENCODED
RXD2
--u-LJ1...
IlP, TERMINAL

RECEIVED BINARY DATA

LINE SIGNAL
Figure 1_ Modem System Block Diagram

3-2
The pair of frequencies used in the FSK scheme are I DIBll I

chosen to be within the bandwidth of the media used. .,""v ~FRAMEI

DAU
For example; the telephone line has a bandpass char-
acteristic with the low frequency cutoff of about 300 Hz I ,
I
and a high frequency cutoff of about 3 kHz. For the tele- '/01,01;.,
aNeeOIO I
phone line the FSK frequencies would have to both fall C."'''I(R

within its 300 Hz to 3 kHz frequency restriction. With c'

the FSK scheme the higher frequency is known as the Figure 4. PSK Encoding
Mark frequency and the lower the Space. The placing of
the frequencies, as mentioned, strongly depends on
the media bandwidth, however, the spacing between
the mark and space frequencies also depends on the
demodulation techniques used. For PLL (Phase-Locked STANDARD BELL 212A/V.22 BelL 201lV.26
Loop), demodulation, described in subsequent sec· Phase Shift 0 0 + 90 0 - 90 0 + 180 0 45 0 135 0 225 0 315 0
tions, the following relationships must be met: Dibit Value 01 00 11 10 00 01 11 10

A. For wide mark-space deviations (close to 2 to 1) Figure 5. Popular Phase Shifts and Dibit Values
fmark-fspace = ~f ~ baud rate (BPS) X .83

B. For narrow spacing

fmark - fspace = ~f ~ baud rate (BPS) X .67

In full-duplex systems two mark/space frequency pairs

must be used, one for answer mode and another for
originate. This is necessary because of the simulta-
neous two way communication for full-duplex opera-
tion. The phase of the frequencies, one relative to the
next, of mark to space or space to mark transitions can
be either coherent or noncoherent. Coherent indicating
that the phase is continuous on frequency transitions or
the phase of the "new" frequency takes over where the
"old" left off. Noncoherent indicating the phase of the TX OATA ~"NC
new frequency has no relationship to that of the old. SYNC
CONY.
SYNC
Here again the demodulation technique used being the "x DATA SYNC
MODEM

determining factor of the necessity of phase coherency. TO

.S .... NC

PLL demodulation is one popular scheme requiring CON".

phase coherent FSK signals.

I I
I CHA,AACTlfII ----f
The other popular encoding scheme used is PSK or I I

phase shift keying. Here a constant carrier frequency is LJ X;XiXiXlX!XiXlXl--"L-

ITAAT DATA 8ITS ITOI'
liT liT
used with the relative phase of it indicating the "value"
of the binary data bit. Because the relative and not ab-
solute phase of the carrier is important, most PSK
schemes are DPSK or dibit PSK. DPSK measures the
phase of the carrier in two successive bit frames in or- Figure 6. SYNC and ASYNC Formats
der to determine the phase change. Figure 4 illustrates
PSK encoding, with Figure 5 listing the phase shifts and
dibit values of two popular PSK modems.

PSK operates in either SYNC (synchronous) or ASYN

(asynchronous) formats. Sync systems use a transmit nT:"I~>---<>". DATA
clock from the digital equipment to clock data out and
maintain synchronization. In this format the data
stream itself has no synchronizing information. In
ASYNC systems, there is no timing signal from the digi- L_-.J~>---.> ~""II" onlCT

tal equipment to the modem. Here synchronization and

timing information is derived from start and stop bits
placed in the data stream bracketing each character.
Timing is maintained by the modem inserting or remov-
ing stop bits. Figure 6 illustrates a terminal connected
to a SYNC system in (A) and ASYNC system in (B). Dif-
ferent character lengths are used, with Bell 212A hav-
ing options for 9 or 10 bit lengths, or 7 or 8 data bits
each with one start and one stop bit. Figure 7

3-3
 DEMODULATION TECHNIQUES The output jitter is usually specified in percent, indicat-
ing what percentage of the bit frame the peak to peak
Once data has been encoded onto a carrier, Txcar, by jitter is.
the modulator in either FSK or PSK formats, the receiv-
ing modem (answer mode) must decode or demodulate . [Tmaximum - Tminimum]
this received carrier, Rxcar. For FSK encoding, analog Jitter == T 100
and digital techniques are used for demodulation. Popu- (%) b
lar analog schemes often employ PLL type demodula-
tion. Using this method, illustrated in Figure 7, a PLL
FILTER REQUIREMENTS
locks to the incoming FSK frequencies and produces Filters in modems serve two functions; to filter the mod-
two different DC error voltages at the phase detector ulator output for band limiting and filtering of the re-
output. These voltages are compared to a reference to ceived carrier (Rxcar) before the demodulator. Figure
indicate whether the incoming frequencies lie above or 10 illustrates these filter functions.
below a reference frequency, or whether they are mark RECEI\j'EOCAP""(A ... ,fJ04i1WO'SE CLi"''''
(high) or space (low) frequencies. ."0 LOCAL OS(; CCJlIoIfOONENlS ~!~~II~~O

A second phase detector (quadrature) is often added

whose output, when filtered and sliced, produces a car-
rier detector (CD) output. This output is active only when
the PLL is in lock, allowing an indication when valid da-
ta is present at Rx data.
Figure 10_ Transmit/Receive Filtering
PSK demodulators typically employ one of two popular The transmit filter is typically a lowpass or bandpass
schemes, differential digital or coherent demodulation structure. As this filter is used to bandlimit the modulat-
techniques. The differential scheme examines zero ed carrier, it is usually of low order (lOW number of poles
crossings to determine carrier phase. With coherent to zeros). The complexity is defined by the frequency
demodulators internal PLL's are used to lock and to de- spectrum generated by the modulator and how well this
termine the phase of the incoming carrier. Coherent has to be confined on the media. For example; tele-
schemes usually provide better overall performance, phone lines have restrictions as to the amplitude of fre-
but at the sacrifice of higher circuit complexity and quency even above its narrow 3 kHz band width (see
cost. FCC requirements).
The demodulator affects and determines several key The receive filter serves two functions: remove noise
parameters of the modem. The demodulation process from the received signal and more importantly remove
adds several degradations to the other originally trans- any local modulator signal which gets mixed with the
mitted data. One, Bias distortion, illustrated in Figure 8, is receiver carrier. Figure 11 illustrates the function of the
easiest seen in an alternating 0,1,0,1 ... data pattern. receive filter.
This pattern should have equal times for each bit, high
(1) and low (0) (T 1t == Tot). An additional block (duplexer) must be considered
TRANSMITTED
DATA

TXOATA

RECIEVEO
DATA
----,

_ _ _- - ,
'----"-_....J~ Tnx + TOTX j
r---- when specifying the receive filter. The duplexer acts to
channel the received carrier from the media to the de-
modulator, A, and channel the transmit carrier to the
media, B (four to two wire conversion). Imperfections in
AX DATA
the duplexer allow some of the Txcar to get into the Rx-
car, C. Therefore, to maintain a good SIN (signal to
noise) ratio at the demodulator input, Rxcar, the receive
Figure 8. Bias Distortion filter must remove this unwanted local Txcar. An exam-
ple illustrates the consideration in terminating the com-
Bias distortion describes how far from equal the re- plexity of the receive filter. In this case, an FSK, Bell
ceived data, RXdata, high and low times are: 103 Type, modem is examined, as shown in Figure 11,
with the following requirements:
Bias distortion == [(.5) T1 p;1
(%) +
R~ORX] 100 Demodulator: fmark == 2225 Hz; fspace == 2025 Hz,
2225 Hz - 2025 Hz
Output jitter is another parameter describing the quality fc == == 2125 Hz
of the demodulation process. Illustrated in Figure 9
2
again with an alternating 0,1,0,1 ... data pattern.
Rxcar dynamic range :::: - 10 dBm to
~:AME ~
-48 dBm
T X DATA } ,

II '----~ sIn at Rxcar == 15 dB

..... TL--
11------, Modulator: fmark == 1270 Hz, fspace == 1070 Hz,
AX DATA
fc == 1170 Hz

Figure 9 Txcar (B) == - 9 dBm

3-4
 II....
ft. OAT"
".eII..

'.OAt ..

Figure 11. Modem Signal Paths

Because of line impedance variations, 600n ± 1DOn or
more (telephone lines), the duplexer may only be able to
maintain 10 dB of Txcar ejection to the receive filter in- " ... _----------'
put. Rxcar wi" contain more than -19 dBm of Txcar and Figure 13. Mode Switching
at a minimum, Rxcar = 54 dB [Path (A) has a 6 dB loss
tent of the transmitted local carrier. An example of prob
due to termination]. If the receive filter has 0 dB pass-
band gain, to achieve a 15 dB sIn ratio at Rxcar the Tx- lems caused by the term are seen in the FSK 103 type
car "bleed through" (Path C) attenuation is calculated modem. If the local modulator is transmitting 1070 Hz,
as follows: the second harmonic content (2140 Hz) falls right in the
receive filter's passband. Therefore, the transmit filter
at Rxcar: Signal = 54 dBm must attenuate this harmonic content to an acceptable
level.

•
Txcar (C) = -54 dBm -15 dBm = -69 dBm
PHONE LINE INTERFACING
Attenuation = -10 dBm - (-69 dBm) =
50 dB The phone line interfacing has to couple the Txcar onto
the line while removing the Rxcar and channeling it to
The filter requirements are illustrated in Figure 12. the receiver. Figure 14 shows a simple acoustical con·
nection which uses the telephone's internal carbon mi·
Other requirements to consider are filter bandwidth, crophone and speaker.
which optimally is set close to the FSK baud rate, or
here 300 Hz (sma" bandwidths can alter the transmit-
ted carrier's spectrum). The phase response or specifi-
A.car
cally group delay within the passband can degrade the
quality of the Rx data in terms of jitter. The group delay
(GO) is a measure of the difference in time it takes for a
mark or space frequency to pass through the filter. It is
calculated by taking the first derivative of phase, with
respect to frequency: T.cat

dO
GD = -
df
Figure 14. Acoustical Coupling

In this connection the telephone headset itself acts as

the duplexer or 2 to 4 wire converter. Attenuation of Tx·
car to Rxcar should be infinite, but mechanical trans·
mission or bleed through may occur and should be con·
sidered.

Typica"y acoustical coupling is only used for FSK type

modems with low data rates, 1200 BPS and down. This
is because of the poor quality carbon microphones
found in most telephones.

The other coupling configuration is the direct connect,

typically design OAA (Direct Access Arrangements). The
DM, shown in Figure 15, serves to:
Figure 12. 103 FSK Receive Filter
Typical differential group delay values for the 103 exam- 1. Provide DC isolation between modem and telephone
ple are 50 - 300 us over the pass band. line-T 1·

For full or half·duplex modems the receive filter can be

used for transmit filtering of the opposite band, shown
in Figure 13 (mode switching).

An additional filtering requirement for many modems

must be considered. This is the second harmonic con- Figure 15

3-5
2. Provide a ring detect to control the on/off hook ations. The dotted line in Figure 18 illustrates a compro-
switch-may be manual. mise line equalization to flatten the effective group de-
lay variation.
3. Provide a DC current path during off-hook to
"hold" the Line-L 1. This current is monitored by Direct connect/on to the telephone line requires FCC approval
the telephone company to indicate when someone as specified in Part 68 of the FCC regulations. One of
is connected to the line. the main requirements of this FCC regulation is the
maximum in-band power levels over frequency bands
4. Provide transient protection-R1/Z1. not only within the 300 to 3000 Hz line bandwidth, but
also above it be restricted to given levels. Figure 19
A hybrid transformer is often used in place of the differ- shows the maximum power levels to be put on the line.
entially connected op amp to perform the duplexer
function, shown in Figure 16. Because modems communicate over vast distances of-
ten automatically operated, test facilities are often add-
The hybrid transformer, T1, provides better Txcar bleed- ed. These test facilities are used to test the local mo-
through attenuation (typically 20 dB) but at additional dem as well as the distant one. Figure 20 illustrates
expense over the op amp duplexer. these functions.
I ,.,110 COWRDMISI! IOUALlnll

/'-t-.. . . J
I I \ ACTUALGlIDl#OrLAY

I I \
I I
I
I
Figure 16 I
I
COMPLETE MODEM SPECIFICATIONS I.t

' .. lDurNCY '"HI'

Line signals received by the modem are often greatly
changed by the media from the originally transmitted Figure 18. Group Delay Characteristics
signal at the originating modem. With telephone com-
munications Bell specifies five different lines which ap- Frequency
pear in standard dial-up lines as shown in Figure 17. (KHz) 3.995 to 4.005 4 to 10 10 to 25 25 to 40 Above 50
Since which line will appear is totally unknown, the Maximum - 18 - 16 - 24 - 36 - 50
worst case line (Bell 3002) is generally used for modem Power Level
evaluation. (dBm)

From Figure 17 it can be seen that severe amplitude Figure 19. FCC Phone Line Restrictions
variations can occur on received line signals. Typically
modems should function with received line signals from
a to -45 dBm (2.2V to 12.3 mVp-p). "'CA"~ IIrcrlYI

H _I ! o II. DATA

.
FlLTlII Ol_
ANALOG DIGITAL
Group delay also can experience large changes. Figure LOONACII LOOPUCII

'.u.~'Y H rrt.,,.~
18 shows the general shape of the group delay charac- TIIA_,T
teristics as a function of frequency. Medium to high FlLTlII
speed modems (PSK encoding) generally use some
kind of equalization to compensate for group delay vari- Figure 20. Test Facilities
BEll SCHEDULE 3002 Cl C2 C4 DCS-S#
Attenuation Characteristic 300 to 3000 Hz 300 to 2700 Hz 300 to 3000 Hz 300 to 3200 Hz 300 to 3000 Hz
(referenced to 1000 Hz) -3 to +12 dB -2 to +6 dB -2 to +6 dB -2 to +6 dB -1 to +3 dB

Envelope Delay Distortion 800 to 2600 Hz 1000 to 2400 Hz 1000 to 2600 Hz 1000 to 2600 Hz 1000 to 2600 Hz
(max. ~sec) 1750 ~sec 1000 "sec 500 ~sec 300 ~sec 100 "sec

800 to 2600 Hz 600 to 2600 Hz 800 to 2800 Hz 600 to 2600 Hz

1750 "sec 1500 "sec 500 "sec 300 "sec

500 to 2800 Hz 600 to 3000 Hz 500 to 2800 Hz

3000 "sec 1500 "sec 600 ~sec

500 to 3000 Hz
3000 "sec

Figure 17. Bell Dial-up Line Characterlst/cs

3-6
EXAR CROSS REFERENCE TO MODEM TYPE

STANDARD
XR PART NUMBER FUNCTION BELL CCITT
XR-210 FSK Mod or Demod 103, 212A (FSK), 202, NS V.21, V.23, NS
XR-2211 FSK Demod 103, 212A (FSK), 202, NS V.21, V.23, NS
XR-2206 FSK Mod 103, 212A (FSK), NS V.21, V.23, NS
XR-2207 FSK Mod 103, 212A (FSK), NS V.21, V.23, NS
XR-14412 FSK ModlDemod 103 V.21
XR-2103 FSK Filter 103
XR-2120 PSK/FSK Filter 212A, 103 V.22 (needs 1800 Hz notch)
XR-2121 PSKIFSK Modulator 212A V.22 (no guard tone generator)
XR-2122 PSK/FSK Demodulator 212A V.22
XR-2123 PSK Mod/Demod 212A (PSK), 201 V.22, V.26, NS
XR-2125 Data Buffer 212A

NS = Non Standard

EXAR MODEM SUPPORT CIRCUITS

XR PART NUMBER FUNCTION

LINE INTERFACE
XR-1488 Quad Line Driver
XR-1489 Quad Line Receiver
OPERATIONAL AMPLIFIERS
XR-082/083 Dual Bipolar JFET Operational Amplifier
XR-084 Quad Bipolar JFET Operational Amplifier
XR-094 Quad Programmable Bipolar JFET Operational Amplifier
XR-095 Quad Programmable Bipolar JFET Operational Amplifier
XR-096 Quad Programmable Bipolar JFET Operational Amplifier
XR-146/246/346 Programmable Quad Operational Amplifier
XR-1458/4558 Dual Operational Amplifier
XR-3403/3503 Quad Operational Amplifier
XR-4136 Quad Operational Amplifier
XR-4202 Programmable Quad Operational Amplifier
XR-4212 Quad Operational Amplifier
XR-4739 Dual Low-Noise Operational Amplifier
XR-4741 Quad Operational Amplifier
TONE DECODERS
XR-567/567A Monolithic Tone Decoder
XR-L567 Micropower Tone Decoder
XR-2567 Dual Monolithic Tone Decoder

3-7
 XR-2121

Bell 2 12A Type Modulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The, XR-2121 is designed to provide the complete modu-

lator function for a Bell 212A type modem. The circuit
accepts a synchronous serial data stream and generates
DGNO
either a 300 BPS frequency shift keyed (FSK) or a 1200
BPS differential phase shift keyed (DPSK) carrier signal.
An on-board digital-to-analog converter provides a synthe- TXClKEXT

sized sine wave output. Also provided on the transmitted

carrier output is an inverting amplifier with external feed- NC
back resistor to provide a carrier amplitude adjust.

The XR-2121 contains an internal 17 bit scrambler. This ClK IN

scrambler which is used during DPSK operation has a dis-
able input for sending non-scrambled carriers. DIB ClK

A 1200 Hz transmit clock output is provided for 1200 BPS

NC
operation, although the XR-2121 will also accept an ex-
ternal transmit clock. For test or other purposes, a 600 Hz
baud clock output is also supplied. MODE

The XR-2121 is constructed using silicon gate CMOS tech- 'TXD

nology. The main clock frequency input is 1.8432 MHz,
The XR-2121, available in a 22 Pin (0.4 inch wide) package,
NC
is designed to operate from +5 volt and -5 volt power
supplies,
SCR EN

FEATURES
NC
Bell 212A Compatible
1200 BPS DPSK
300 BPS FSK
Digital Modulation Techniques for DPSK
External Transmit Clock Input ORDERING INFORMATION
600 Hz Dibit Clock Output
Complete Scrambler Function with Disable Input Part Number Package Operating Temperature
Transmit Carrier Level Adjust XR-2121CN Ceramic O°C to 70°C
1.8432 MHz Clock XR-2121CP Plastic O°C to 70°C
±5 Volt Operation
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2121 basically has two types of operation, 1200
Bell 212A Type Modulator BPS DPSK or 300 BPS FSK. For 1200 DPSK the XR-2121
Bell 103 Type Modulator generates carrier frequencies of 1200 Hz or 2400 Hz, de-
pending on mode selection (originate or answer). The
ABSOLUTE MAXIMUM RATINGS carrier frequencies are imposed with phase shifts to carry
the data to be transmitted (TXD) over the telephone net-
Power Supply work. The phase sh ifts correspond to the incoming data
VDD -0.3 to +7V grouped in pairs (dibits) and are one of four values -
VSS +0.3 to -7V 0°,90°, -90°, 180°,
Input Voltage VSS -0,3V to VDD +0.3V
DC Input Current ±1O mA During 300 BPS FSK operation, the XR-2121 generates
Power Dissipation 1.0 W one of two pairs of frequencies to represent the TXD,
Derate Above 25° C 5mWtC These pairs are either 1070 Hz/1270 Hz or 2025 Hz/2225
Storage Temperature Range -65°C to +125°C Hz depending on mode selection.

3-8
XR-2121

ELECTRICAL CHARACTERISTICS
Test Conditions: VDD:: 5 V ±5%. VSS:: -5 V ±5%. CLK IN = 1.8432 MHz ±0.01%. TA = 0°_70°C unless otherwise specified.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

IDO Positive Supply Current 2.5 4 mA

ISS Negative Supply Current -1.5 -2.5 mA

DIGITAL INPUTS/OUTPUTS

VOH Output High Voltage 2.4 V 10= 1 mA

VOL

VIH

VIL

10H
Output Low Voltage

Input High Voltage

Input Low Voltage

Output Drive Current

Output Drive Current

2.4

0.5

2.0
0.4

1.5

4.0
0.8

0.8
V

mA

mA
lo=-1.5mA

VOH:: 3.5 V

VOL = 0.5 V
•
IOL

liN Input Current 10 J1A

ANALOG SECTION

VTXC Transmit Carrier Amplitude -4 dBM REXT = 10k

VTXC2H Transmit Carrier Amplitude

2nd Harmonic Content -40 dB RL ~ 10k

3-9
 XR-2121

CLKIN 19~------~-----------------------'

TXC L K EX T 211--------1------1 CLOCK GENERATOR

TX CLK

DI B ClK 181---------+.----------.....J

DIFFERENTIAL
ENCODER
AND
ADDRESS PENETRATION

MODE 16~--_.--_+------------------------------~

300 BPS
SIGNAL
FSK
ELEMENT
MODULATOR
STORAGE

VDD@----

DIGITAL TO R
Vss[D-- ANALOG
CONVERTER

DGND~ ~AGND

EQUIVALENT SCHEMATIC DIAGRAM

3-10
XR-2121

PRINCIPLES OF OPERATION
TXD SCH

The X R-2121 is desiqned to perform all the necessary func-

tions for the modulator section of a Bell 212A type
modem. It has been specifically designed to operate with 17 BIT SHIFT REGISTER
the XR-2120 filter, XR-2122 demodulator, and XR-2125
data buffer to form the complete Bell 212A type modem
signal processor. This data sheet will cover just the XR-
2121 and its functions with Application Note AN-28
covering the complete system.

The X R-2121 has two basic types of operation; that of a

1200 BPS differential phase shift keyed (DPSK) or 300 Figure 2. 17 Bit Psuedo Random Scrambler
BPS frequency shift keyed (FSK) modulator.

The 1200 BPS section of the X R-2121 converts a serial

synchronous data stream (TXD) into a DPSK encoded car-
rier suited for transmission over a standard telephone
The output of the scrambler produces a psuedo-random
output which can be described by the following equation:
II
switched network. The incoming data, TXD, is clock-
ed into the X R-2121 by either an internally generated TXD SeR = TXDI9TXD -149TXD -17
transmit clock, Tx elK, or an externally applied clock, Tx (1) = exclusive - or operation
elK EXT The internal TX elK is derived from the main
1.8432 MHz clock, and is precisely 1200 Hz. If an external
The main purpose of the scrambler is to assure that the
transmit clock is applied to the TX elK EXT input. Tx
transmitted carrier will not have extended periods of 0°
elK will become phase locked to Tx elK EXT. Figure 1
phase shifts. This condition would cause the receiving
shows the relationship between TXD and Tx elK (lA) and
modem's demodulator to loose lock and be unable to
TX elK and TX elK EXT (1 B).
extract clock information from the received carrier. This
condition is discussed further within the XR-2122 data
I ! sheet.
i--_ _--,I-- 1 811 --j
TX [)
I I The scrambled data is fed into the actual modulator section
of the X R-2121. Th is section phase encodes a constant
frequency carrier to represent the incoming serial data,
A) T;;') AND ~K RELATIONSHIPS TXD. * This type of phase encoding phase shift the carrier
every two data bits. Figure 3 shows the relationship be-
tween the transmitted data, its clock, and the resultant
phase encoded carrier. As seen in this figure, although the
data rate is 1200 BPS, the baud rate is only 600. This is
because phase changes only occur every two data bits or
dibits. Table 1 gives the phase changes for the four possible
dibit values.

Figure 1. Transmit Data & Clock Relationships *The transmit carrier frequencies for 1200 BPS operation
are either 1200 Hz for originate mode or 2400 Hz for
answer mode.

As seen in Figure 1, data is clocked into the XR-2121 on

the falling edge of Tx elK.

1200 BPS data entering the XR-2121 is passed through a

scrambler circuit, as shown in Figure 2.

Figure 3. TX ClKITXC Timing

3-11
 XR-2121

DIBIT PHASE CHANGE The pairs of frequencies used for the two different modes
are shown in Table 2. The higher frequency in each pair
o0 is known as the mark frequency with lower the space.
o 1
1 0
1 1
MODE CARRIER FREQUENCIES (MARK/SPACE)
Table 1. Carrier Phase Change vs Dibit Value
Answer 2225 Hz/2025 Hz
It should be noted that the phase changes are relative
values. That is, each phase change as shown in Table 1 is Originate 1270 Hz/l070 Hz
relative to the previous carrier phase.
Table 2. FSK Carrier Frequencies
Figure 3 shows the TXC being phase shifted, however,
the XR-2121 does not introduce abrupt changes as shown Unlike 1200 BPS operation, for 300 BPS, the baud rate is
there. This figure was drawn in this fashion for clarity. the same as the data rate, 300. This is of cour~ because
The XR-2121 uses digital echo modulation techniques. This every input data change causes a carrier frequency sh ift.
technique allows incremental or·.slowly changing phase
changes. Using this method also allows precise shaping of The outputs of both 1200 BPS and 300 BPS sections are
the frequency spectrum. The spectrum analyzer photograph fed into a multiplexer which routes the proper one to the
in Figure 4 shows the carrier spectrum for each carrier output section depending on speed selection. The output
frequency. It can be seen from the photo that separation of circuitry consists of a seven bit digital-to-analog converter
about 40 dB between the two spectrums is possible even (DAC) and an output operational amplifier. The op amp is
before bandpass filtering. The frequency spectrums are configured as an inverting amplifier with the OAC feeding
designed for square root raised cosine shaping. an input resistor and the feedback resistor placed external-
ly. This allows TXC amplitude adjustment at this point.
Pin 5, TXC EN, can be used to disable transmission if
desired.

DESCRIPTION OF INPUTS AND OUTPUTS

Pin Name Description

AGNO This is analog or signal ground. It

should not carry logic or heavy
currents.

2 Vss Power input for the negative power

supply which is typically -5.0 volts.

3 TXCAOJ This is the inverting input of the

output op amp. A resistor (REXT)
Figure 4. Transmit Carrier Spectrum
from this pin to pin 4 (TXc) sets
For 300 BPS operation frequency shift keying, FSK, en- the output amplitude of the TXC
coding techniques are used. For this operation bit asyn- (see Figure 6).
chronous serial data is fed into the X R-2121 data input.
Being asynchronous, no transmit clock is used. The scramb- 4 TXC This is the transmit carrier output.
ler is bypassed for 300 BPS operation.
6 1200/300 Speed select input to set either
FSK encoding uses pairs of frequencies to represent input 1200 BPS OPSK or 300 BPS FSK
data changes. Figure 4 shows the incoming data, TXO, operation.
and carrier output relationships.
7 VOO Power input for the positive power
supply which is typically +5.0 volts.
r",~

r~ r\NVVv'JV\J\./'~,-- 9 TXCLK The transmit clock is output

on this pin. It is internally gene-
rated from the main clock input
(pin 19) and is used internally to
clock TXO into the XR-2121.
Figure 5. FSK Data Carrier Relationships
3-12
XR-2121

13 SCR EN The data scrambler can be en- The synchronous data stream is fed into TXD with the
abled or disabled by this pin during TXC output being either a DPSK or FSK encoded carrieL
1200 BPS operation. In a complete system the TXC would go to the transmit
filter input. Application Note AN-28 shows the XR-2121
15 TXD This is the serial data input. in a complete modem signal processor.

16 MODE Answer or originate modes are Several output waveforms have been included to help
selected by this pin. understand the XR-2121 operation. Figure 6 shows fre-
quency spectrums for FSK for both answer and originate
18 DIB CLK The 600 Hz dibit clock is output modes. It can be seen to consist of two 300 Hz wide
on this pin. It may be used during spectrums centered around 1170 Hz and 2125 Hz. Figure
system testing such as digital loop- 7 and 8 show the higher harmonic contents of the FSK

•
back to provide an alternating spectrums. These figures show the second harmonic con-
1OlD... data pattern. tent to be more than 50 dB down from the fundamental.
This is very desirable in the originate mode as second
19 CLKIN This is the main clock input and harmonics not attenuated by the transmit filter will pass
should be 1.8432 MHz ±0.01%. unattenuated through the receive and cause degraded pel-
formance.
21 TXCLK EXT An external transmit clock may be
applied to this input during 1200
BPS operation +0.01%.

22 This is the ground for the logic

circuitry of the XR-2121.

CONTROL INPUTS

Table 3 gives logic conditions for the various control inputs

of the XR-2121.

FUNCTION
PIN NAME LOGIC HIGH LOGIC LOW

5 TXC EN Carrier Enabled Carrier Disabled

6 1200/300 1200 BPS Operation 300 BPS Operation

13 SCR EN Scrambler Enabled Scrambler Disabled

16 MODE Answer Originate

Table 3. Control Input Conditions

APPLICATIONS
A typical connection of the XR-2121 is shown in Figure 6.

GND

TXClKEXT
TxC
1.B432MHZ±O.01%
600HZDIBCLK

MODE
Txc DATA INPUT
TXCLK O-------Ej
SCREN

TXC' 20 LOG (.63/1REXT , ... > SINGLE POINT GROUND

10K C 1 "). 2.2~F

TX: -4 dBM for REX'" 10K C2 ->O.D1,101F

Figure 6. XR-2121 Typical Connection

3-13
 XR-2121

Figure 9 and 10 show the carrier being enabled and dis- Bell 212A Handshake
abled using the TXC EN pin (pin 5) for PSK and FSK
respectively. It shows about 10 ms necessary for the car- The Bell 212A modem specifications require auto speed
rier to be either fully enabled and settled, or disabled. selection on auto answer modems. Auto speed selection
These photos were taken with a transmit filter similar requires detection and decoding of the Bell 212A hand-
to the XR-2120 at the output of the XR-2121 to produce a shake protocol. This detection and decoding is automatical-
clearer picture. ly performed by the X R-2122, Bell 212A type demodu-
lator. Some additional logic I circuitry is required to per-
form the handshake properly. This logic / circuitry may
be digital, analog, or microprocessor-based.

Figure 12A and 12B illustrates the timing requirements

for the Bell 212A handshake.

For further application information on the XR-2121,

Application Note AN-28 shows a complete modem signal
processor utilizing the XR-2121 with the XR-2120 filter,
X R-2122 demodulator, and X R-2125 data buffer.
Figure 11.

I
~
0155 ~

2S~1S~0714S--+i
~132S---.f
t---'l 890S--+i
""033S~
~
~

Figure 12A. Figure 12B. V.22 Handshake (with V.25 Auto Answer)
3-14
XR-2121

lOKOt%

lOKlll%
TXCOUT 12120)

62KlIl%

5JKlI

V.

~AA~J5
s-2~:1~ F, II
r---------+-----~ 0 F,
v . o - - _ + - - - -......>----'
F, 550 H,
F, 1800H, 20KIl
R, 180 Klll%
R, 56K(ll%
C 001.F
V. - t5V v.
V. - ·5V
Figure 13. Guard Tone Generation

V.22 Guard Tone Generation

Figure 13 illustrates implementation of the V.22 guard tone

generation. V.22 specifies use of the 1800 Hz guard tone
in conjunction with the Originate carrier. The 550 Hz guard
tone is a national option. Specifications for guard tone
generation require the amplitude of the Quard tone to be
6 ±1 dBM lower than' the transmitted carrier which is
typically 9 dBM. The circuit of Figure 13 allows choice of
implementation of either Quard tone via TTL logic levels:
5 V giving 1800 Hz and 0 V producing 550 Hz. The 20
kn resistor to pin 3 sets the voltage at pin 2 to 1.2 V
peak. This voltage is then summed and attenuated at the
line driver (X R-1458) to give the -16 dBM output required.

Transmit Output Amplifier

To ensure transmit amplitude accuracy for the XR-2121, an

external amplifier is recommended. The input to this
amplifier should be from pin 3, TXC ADJ. Figure 14 shows
a typical implementation of this transmit amplifier.

10K (1%)

PIN 3
(XR-2121)

Figure 14. Transmit Carrier Output Amplifier

3·15
 XR-2122

Bell 212A Type Demodulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-2122 is designed to perform the complete Bell

212A type modem demodulator function. Both 1200 BPS
differential phase shift keyed (DPSK) and 300 BPS fre- ANI VDD

quency sh ift keyed carrier demodu lation is performed by

FADJ
the XR-2122. The 1200 BPS portion utilizes coherent iI'NV

demodulation. while the 300 BPS uses phase-locked loop

AOUT CSIH
techniques. For 1200 BPS operation. an internal 17 bit
descrambler provides the descrambled output with the non-
DEMOO IN AT
descrambled output also available.

RCV OUi CT
Automatic speed selection is performed by a handshake
circuit. Carrier detect outputs are supplied for FSK data.
CO IN CT
PSK data. and conventional energy detection.
AGND EYE OUT
A non-committed operational amplifier is supplied to pro-
vide receive carrier sensitivity tailoring. An automatic NC OGND
gain control circuit (AGC) assures wide dynamic input
carr ier range. (;1 KIN AXD NS

The XR-2122 is constructed using silicon gate CMOS tech- 1/(JO :;00 AXD
nology. The X R-2122 is designed to operate off of a 1.8432
MHz clock input. Available in a 28 Pin package. the MODE Ax eLK
XR-2122 is designed for +5 volt and -5 volt power
suppl ies. HS coour

FEATURES CDELAY
HANDSHAKE
PSK CD

CONTROL
Bell 212A Compatible VSS FSK CO

1200 BPS DPSK Coherent Demodulation

300 BPS FSK Demodulation
Eye Diagram Output
Internal 17 Bit Descrambler
Non-descrambled Demodulation Output Available ORDERING INFORMATION
FSK. PSK and Energy-type Carrier Detect Outputs
Automatic Speed Selection Part Number Package Operating Temperature
Non-committed Op Amp for Input AGC Amplifier D
XR-2122CN Ceramic ODC to 70 C
AGC Input Circuit for Wide Dynamic Range XR-2122CP Plastic
D
ODC to 70 C

APPLICATIONS
Bell 212A Type Demodulator SYSTEM DESCRIPTION
Bell 103 Type Demodulator
The X R-2122 provides two basic types of operation; de-
ABSOLUTE MAXIMUM RATINGS modulation for either 1200 BPS DPSK or 300 BPS FSK
encoded incoming carriers. For either speed. the incoming
Power Supply carrier is passed through a gain stage (uncommitted op
VDD -0.3 to 7 V amp) and an AGC circuit to condition the signal. For 1200
VSS 0.3to-7V BPS. the signal is processed using coherent demodulation
Input Voltage VSS -0.3V to VDO +o.3V techniques (Costas Loop).
DC Input Voltage ±1OmA
Power Dissipation 750mW For 300 BPS. a digital phase-locked loop type of demodu-
D
Derate Above 25 C 5mWtC lator is used providing low bias and jitter distortion without
D D
Storage Temperature Range -65 C to +150 C adjustments.

3-16
XR-2122

ELECTRICAL CHARACTERISTICS o
Test Conditions:VDD = 5 V ± 5%, VSS = -5 V ± 5%, TA = 0-70 C, ClK IN = 1.8432 MHz ± .01%, unless specified otherwise.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

DC CHARACTERISTICS

100 Quiescent Positive

Supply Current 8 12 mA Normal Operation

ISS Quiescent Negative

Supply Current -8 -12 mA Normal Operation
I

DIGITAL CHARACTERISTICS

liN

VIH
I nput Current

Input High Voltage 2.4

10 pA

V
VIN = VDD or GND II I

VIL Input low Voltage 0.8 V

VOH Output High Voltage 2.4 V 10H = -400 pA

VOL Output Loss Voltage 0.4 0.8 10L = 2 mA

ANALOG CHARACTE R ISTICS (Circuit Configuration of Figure 11)

AVG Amplifier Open Loop Gain 60 dB

VDEMOD Typical Input Voltage

IN to DEMOD IN -6 dBM

ZDEMOD DEMOD IN Input

IN Impedance 15 Kn

ZCOIN CD IN Input Impedance 50 Kn

COON CD On Level -32 -30.5 dBM

CD OFF CD Off Level -35.5 -34 dBM

Td CD CD Off/On Delay Time 10 17 24 ms

Tdlh FSK FSK CD Off/On Delay Time 105 150 205 ms

Tdhl FSK FSK CD On/Off Delay Time 10 17 24 ms

Tdlh PSK PSK CD Off/On Delay Time 200 270 350 ms C Delay = 0.47 pF

Tdhl PSK PSK CD On/Off Delay Time 10 17 24 ms

fVCO VCO Frequency

Answer Mode 4.8 KHz
Originate Mode 9.6 Khz

3-17
 XR-2122

ANI~+
A INV 2 -

AOUT 3 QPSK DEMODULATOR

SAMPLING
DEMOD IN 4 1---..---.....--1 MEMORY
DECODER

Voo(ill-
--@EYEOUT
VSS@--
~RT
RCV OUT [II
---§] CT
1200/300 E£}--
--§lCT
~CS/H
--0 FAO J

ClKIN 91--+--fg~~~~ATOR

HS 12~--~---------------------------4---------------,
DE·
SCRAMBLER

FSK DEMODULATOR

PSKCD
CARRIER
DETECTOR HANDSHAKEAND~----~ FSKCD
CONTROL LOGIC
RXD

AGNO~ RXDNS

DGNO~ RXCLK

MODE

EQUIVALENT SCHEMATIC DIAGRAM

3-18
XR-2122

PRINCIPLES OF OPERATION The output of the AGC, which is really a constant ampli-
tude RXC, is fed to two different circuits. One is for carrier
The XR-2122 is designed to perform the complete demodu- recovery and one tor clock recovery. The carrier recovery
lafor function in a Bell 212A type modem system. It has circuit is a Costas loop. The error voltage outputs of
been specifically designed to complement the XR-2120 the Costas loop are fed to a sampling memory decoder
filter, XR-2121 modulator, and XR-2125 data buffer to which will produce dibits, or pairs of bits, which are ex-
form a four chip Bell 212A type modem signal processor. tracted from each RXC phase change. Figures A, B, and C
This four chip set is known as the XR-212AS and is covered show the eye diagram at the output of the Costas loop
in depth in Application Note AN-28. This data sheet will with the receive clock, RX ClK. The eye diagram is the
deal specifically with the XR-2122 and its functions. prime indicator of demodulation quality in a cohert type
demodulator. The RX ClK sets the point where the eye is
The X R-2122 performs two different types of demodula- sampled, which should be at the point of zero intersymbol
tion; 300 BPS frequency shift keyed (FSK) and 1200 BPS interference, or, in other words, at the eye's maximum

II
differential phase shift keyed (DPSK) encoded carriers. opening. The three photographs were taken at Pin 22,
eye out, with a complete modem signal processor utiliz-
First consider the 1200 BPS type of demodulation. For ing the XR-2121 modulator, XR-2120 filter, and XR-2125
this demodulator operation, the XR-2122 accepts a DPSK data buffer. The eye opening, or quality of demodulation, I

encoded carrier (RXc) typically from the telephone changes with different line (telephone) quality. The three
switched network, and demodulates it to produce a serial photos show the eye and RX C l K for:
received data output. Th is serial data stream is synchro-
A) Back-to-back operation, or two modems directly tied
nous, that is a clock, RX ClK, is used for synchronization
together, A 1 is originate and A2 is answer mode.
purposes.
B) A 3002, C2 conditioned phone line. B1 is originate and
B2 is answer mode.
The DSPK encoded receive carrier, RX(' is first applied to
C) A 3002 CO unconditioned phone line. Cl is originate
an automatic gain control circuit, AGe. This circuit, shown
and C2 is answer mode.
in Figure 1, provides a constant voltage output for a wide
dynamic range input signal.

Figure 1. AGC Circuit

Operation of the AGC is as follows. Vo is internally set to

about 1.5 volt peak-to-peak. The ~ain (non-inverting) of Al
is set by R2 and Rl, and is R2/Rl for R2» Rl. With the Figure. A1
gain of Al set and a constant Vo , the input voltage to Al 's
non-inverting input will be a constant voltage: VNI =
(Vo)';-(R2/Rl). FET Ql acts as a variable resistor to form a
voltage divider with R3 for the input signal. Ql's resistance
is controlled by the feedback path from Al 's output,
through C2, the full-wave rectifier and filter network
R4-R5-Cl. The feedback will control the resistance of Ql
in such a way that the voltage divider action it produces
with R3 will produce the precise voltage at VNI of Al,
which, when multiplied by Al 's gain, will produce the
correct Vo. Values are given in the applications section for a
typical circuit which will accept an input dynamic range of
-40 dBM to 0 dBM.

Figure. A2
3-19
 XR-2122

Figure. 81 Figure. C2

More information is given on this subject in Application

Note AN·28. DPSK encoding introduces a phase shift to a
constant frequency carrier every two data bits, or dibits
(see XR·2121 modulator data sheet). Table 1 shows the
four possible dibits for phase changes of RXe. The XR·
2122 conversely produces two data bits for each phase
change. The two carrier frequencies are 1200 Hz and
2400 Hz; Table 2 shows the Mode/Frequency convention.

RX CAR PHASE SHIFT OUTPUT D I B IT

o0
o1
1 0
1 1

Table 1. Dibit Values for RXC Phase Changes

Figure. B2
RECEIVE
MODE CARRIER FREQUENCY

Answer 1200 Hz

Originate 2400 Hz

Table 2. Carrier Frequency Assignments

;-he mode is controlled by a logic level on pin 10. The

d ibits are returned to serial form by a parallel to serial
converter. Next, the serial data stream is descrarnbled;
the circuitry for this function is shown in Figure 2.

RXOi

RXO~
OEseR ~~---<

Figure. C1 Figure 2. 17 Bit Psuedo Random Descrambler

3-20
XR-2122

The descrambler is n.ecessary· as all Bell 212A type modems The output of the two demodulators, FSK and DPSK, are
use a scrambled data format for the 1200 BPS speed. This fed into a handshake and control logic section. The primary
is used to insure that certain data patterns which would purpose of this section is to decide whether the incoming
cause few, or no phase changes, ever exist. The output of carrier, RXC, is FSK or DPSK encoded, or, in other words,
the descrambler can be described by: which speed the carrier modulation is: 300 BPS or 1200
BPS. This produces an auto speed control circuit. During
RXD DESCR = RXDI (1 Ell RXD -14 Ell RXD -17) the initial handshake routine, the XR-2122 will first look
for an FSK RXC- It does this by an FSK mark sensor which
For tim ing purposes during 1200 BPS operation, a clock looks for five consecutive errors. If this condition occurs,
operation will automatically be switched to 1200 BPS
must be extracted from the received carrier, RXC- This
DPSK. The handshake circuit produces three carrier detect,
clock represents a baud period and is 600 Hz. It is used in-
CD, outputs; an FSK CD (pin 15). PSK CD (pin 16),
ternally for sampling and multiplied by two, 1200 Hz, and

•
and an energy level type CD (pin 17) which will respond
output on pin 18, RX ClK. The timing relationship be-
to all in-band signals.
tween RX ClK and output data, RXD, is shown in Figure
3. DESCRIPTION OF INPUTS AND OUTPUTS
RXClK Pin Name Description

ANI Th is is the input op amp non-invert-

ing input. This op amp is typically
used in the AGC circuit.
Figure 3_ RXD/RX CLK Relationships
2 AINV The inverting input of the input
op amp.
As seen in Figure 3, RXD changes on the falling edge of
RX ClK· 3 The output of the input op amp.
AOUT

4 DEMOD The input to both 300 BPS and 1200

Rxe 0--.------4
BPS demodulators. Also the AGC
output.
------------------~
CARRIER DRIVE I

5 RCV OUT This pin is used to drive the gate of

an external FET used in the AGC
circu it.

6 COIN The input to the carrier detect

circuitry.

7 AGND Analog ground for the linear cir-

cuitry of the XR-2122. This ground
should not carry logic current to
Figure 4. Timing Recovery Circuit avoid ground noise.

Clock recovery is accomplished from both the received car- 9 ClKIN The master clock input, typically
rier, RXc. and data drive timing. Initially, the clock is re- 1.8432 MHz ±0.01%.
covered from RXC for quick response and then assisted by
the Costas loop for data drive. A digital phase-locked loop, 10 1200/300 Speed select input for selecting
Pll, locks the two types of RX ClK'S together for a more 1200 BPS DPSK or 300 BPS FSK
stable clock. This clock is used internally for sampling operation.
and timing, and outputted on pin 18, RX ClK, for sam-
pling use externally. 11 MODE Mode selection for answer or origi-
nate mode.
The demodulation for the 300 BPS operation accepts an
FSK encoded carrier and produces an asynchronous serial 12 HS Handshake enable/disable input. The
data output. Since it is asynchronous, no RX ClK is used. handshake is primarily an auto speed
The RXC from the AGC output is fed to a digital phase- selection circuit with a full descrip-
locked loop, PlL. The error voltage of the Pll is low pass tion with the text section.
filtered using switched capacitor filter techniques and com-
pared against a reference voltage to produce the demodu- 13 CDElAY Provides carrier detect turn-off and
lated output. turn-on timinq programming.
3-21
 XR-2122

C, FILTERED
r------~>------------__i 1-1--------0 RECEIVE
IC4 Voo CARRIER

1.8432 MHz IN O-----------""'""'"i

1200/300

TO CH/CI OF RS-232-C n-------------f MODE

TYPICAL COMPONENT VALUES
HS
R, = 33KO Cl =1/.lF
COELAY
R2 = 1 KO =
C2 0.01/.lF
R3 = 100KO =
C3 0.0033pF
Vss R4 = 220KO =
C4 0.47 pF
Rs = 33KO =
Cs 1/.lF
Vss Rs = 390KO =
Cs 1/.lF
TO CF OF RS-232-C (')...-----------------------1 R7 = 10KO POT
Rs = 220K
=
C7 O.0033/.lF

TO DATA BUFFER { Rg = 1K
(SYNC-TO-ASYNC) n----------------------.......I R,O = 43KO

FIGURE 11. TYPICAL CONNECTION DIAGRAM

21 DGND The ground for the digital logic

14 VSS Power supply input for the negative of the XR-2122. This pin should
power supply. This supply is -5.0 ± be connected to AGND at the power
0.25 volts and should be well by- supply - single point ground.
passed with decoupling capacitors.
22 EYE The Costas loop eye diagram out-
15 FSK CD This is the FSK CD output. put is available at this pin.

16 PSK CD Provides the DPSK CD output. 23/24 CT The Costas loop voltage controlled
oscillator, VCO, timing capacitor is
17 CD The energy-type CD output. connected between these pins.

18 RX ClK Receive clock output which is a The Costas loop VCO timing resistor.
25 RT
1200 Hz square wave derived from
the incoming DPSK encoded carrier, Sample and hold capacitor is con-
26 CS/H
RX ClK. Used for external timing of nected between this pin and analog
RXD· ground, AGND.

19 RXD Serial receive data output for either 27 Costas Loop VCO fine tuning input.
1200 BPS DPSK or 300 BPS FSK.
28 VDD Power supply input for the posi-
20 RXD NS This provides a receive data output tive supply. This supply is +5.0 ±
before the internal descrambler. 0.25 volts and should be well bypa-
sed with decoupling capacitors.
3-22
XR-2122

CONTROL INPUTS BeJl212A Handshake Protocol

Table 3 gives logic conditions for the various control inputs The X R-2122 performs the sensing for the Bell 212A hand-
of the XR-2122. shake protocol. With the handshake pin, pin 12, pulled
high (+5 V). the XR-2122 will perform energy and sensing
FUNCTION and indication, and auto speed adjust. These functions
PIN NAME LOGIC HIGH LOGIC LOW can be utilized to complete the Bell 212A handshake.
Timing parameters are illustrated in Figure 14A and 14B.
10 1200/300 1200 BPS DPSK 300 BPS FSK
Operation Operation Since the XR-2122 will change speeds internally, over-
riding the speed selection pin (pin 10). the designer must
11 MODE Answer Originate Originate provide a means for selecting the required handshake proto-
col carrier from the modulator, the XR-2121. This selection
12 HS Handshake Handshake can be achieved irl hardware or software.
F u nction/Enab Ie Function/Disabled

Table 3. Control Input Conditions

APPLICATIONS Addendum:

The XR-2122 is shown in a typical connection in Figure 11. Handshake:

In a complete modem system the received carrier, RXe.

The handshake pin (HS), pin 12, must be low when
would come from the receive filter such as the X R-2120.
For the XR-2122 it would be either a FSK or DPSK en- the device is first powered up. The reason for this is
coded carrier typically from the telephone network. The that at power up, the digital portions of the XR-2122
data output, RXD, would be either a 300 BPS serial bit will reset to an initial state. The HS pin being high
asynchronous or 1200 BPS serial synchronous data stream. will prevent this from occurring. It is best to have
In a full application (AN-28), the RXD output would go the HS pin low for 2 seconds to allow the reset to
through the XR-2125 data buffer. For the 1200 BPS completely finish.
operation, the data buffer will convert the X R-2122 syn-
chronous data into a character asynchronous format with
a character length of 9 or 10 bits.
AGe:
The input signal range of the RXC is -40 dBM to 0 dBM
for the AGC values given. The requirements for the AGe Field Effect Transistor
that is tied to pin 1 (ANI) is as follows:
Figure 13 shows R8 and Rg replaced by potentiometer
Pl· VGS (gate-source cut-off voltage) ==
-0.8 V minimum, -4.0 V maximum
Potentiometer Pl adjusts an internal DC offset in the
Costas Loop, or 1200 BPS section of the XR-2122. For VOS(on) (drain-source on voltage =
optimum system performance, it should be adjusted for 0.5 Vat '0 = 5 mA maximum
maximum eye opening at pin 22, EYE OUT (see Figure rds(on) (drain-source on resistance) =
12). Figure 13 shows the test set-up for observing the eye 60 ohms maximum
output of 1200 BPS and determining the demodulation BVGSS (gate-source breakdown voltage =
quality. -30 V minimum

The 2N4681 meets these requirements and Is used for

all demonstrations in EXAA's labs.

MAXIMUM EYE OPENING

Figure 12. Eve Diagram Characteristics

Further, more complete applications information on the
XR-2122 is given in Application Note AN-28 which covers
the device used in a complete system.
3·23
 XR-2122

OSCILLOSCOPE

CH 1

EYE OUT
i
CH 2

VERT HORIZ

CH 1

RXCLK
CH 2 EXT
TRW

HANDSHAKE
CONTROL

Figure 13. Set·up for Eye Diagram Output

3-24
XR-2122

ORIGINATING STATION
~ANSWERTONE~
______~~r----------------DA-T~A-----------------
RECEIVE CARRIER
1270Hz~
TRANSMIT CARRIER _____________________~r------------D-AT~A----------------
FSK CD

PSK CD
I-l
0.15 S

•
ANSWERING STATION

RECEIVE CARRIER ____________________~~~l--________~D~A~TA~______________

TRANSMIT CARRIER ______~~~______________D_A_T_A________________

FSK CD

PSK CD
1 - - .0.890 S - . j
1-0.33S.j
f-J
0.15S

Figure 14A. 212A Handshake 300 BPS

ORIGINATING STATION
. I- !-ANSWERTONE
2400HzMARK-I;.-_ _ _ _ _ ._ _ _ _ _ _ _ _ __
RECEIVE CARRIER ______~~~______D_A_T_A ________________

,. 1200HzMARK~-:-:_~-~,~-------------
TRANSMIT CARRIER _ _ _ _ _ _ _ _ _ _ _~~_ _ _ _ _ _ _ D_A_T_A_ _ _ _ ___

FSK CD

PSK CD

1-1 I---l
0.15 S 0.27 S

ANSWERING STATION

RECEIVE CARRIER

TRANSMIT CARRIER

FSK CD

PSK CD

2 s----,-*I••- - - - - 1 S - - - - - - -••+-1."---0. 774 s - f

I....1I----------1.32·S-----------t-~1
J-l
0.275

Figure 14B. 212A Handshake 1200 BPS

3-25
 XR-2123/2123A

PSK ModulatorIDemodulator
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS

This series of devices provide the modulator and demodu-

lator for phase-shifted keyed modulated signals. The de- VDD
vices have an on-chip digital-to-analog converter, allowing
digital external programming of Bell 212A, CCITT V.22 or C22
V.26 functions.
PSK
RXS
The XR-2123 provides the modulator and demodulator DEMODULATOR
functions. It is adequate for Bell 212A (1200 BPS only) RBA

"r
and Bell 201 standards. The XR-2123 requires a synchron-
ous-to-asynchronous converter and scrambler-descrambler RXD ~
for the digital portion of the modem for 212A applications.
Level shifters and filtering is required for the analog
portion.
QUA ,V~
MDC
The X R-2123A provides the ±7 Hz carrier capture range CONTROL
needed for V.22 and V.26. It is externally identical to the LOGIC
CCL
XR-2123.

The XR-2123 and XR-2123A utilize CMOS technology for

TRM
/)
)~
power operation while providing single 5 volt operation. TXS
Both devices come in a 28 pin DI L pin package in either
plastic or ceramic. TLV V

PSK
RLD
MODULATOR
FEATURES
4CR
Single +5 Volt Operation
Low Power Consumption (typ. 10 mw) vss
1200 BPS Full Duplex
2400 BPS Half Duplex
Programmable for US or European Standards (CCITT)
Dibit PSK (DPSK) Operation ORDERING INFORMATION
Cyrstal Controlled
Synthesized Sine Wave Modulator Output Part Number Package Operating Temperature
Adjustable Modulator Output Amplitude XR·2123CN Ceramic O°C to +70°C
I nput Protection XR-2123CP Plastic O°C to +70°C
XR-2123ACN Ceramic aOc to +70°C
XR-2123ACP Plastic aOc to +70°C

APPLICATIONS

Bell Standard 201 or 212A Modems

CCITT Standard V.22 or V.26 Modems
SYSTEM DESCRIPTION

The XR-2123 and XR-2123A provide the complete modu-

ABSOLUTE MAXIMUM RATINGS lation and demodulation of DPSK modem systems. The
modulator transmits a sampled sine wave in dibit phase-
Power Supply 5.5V shifted keyed format (DPSK). The phase shifts and carrier
Power Dissipation 1.0W frequencies are controlled with logic inputs. With these
Derate Above 25°C 5 mW/oC controls, a Bell 212A/CCITT V.22 or a Bell 2a1/CCITT
Operating Temperature O°C to 7aoC V.26 can be created.
Storage Temperature -65°C to 150°C
All Input Voltage -0.5 V to (VDD to 0.5 V) The XR-2123 and XR-2123A require a separate scrambler/
DC Current Into Any Input ±mA descrambler and synchronous-to-asynchronous converter.

3-26
XR-2123/2123A

ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = +5V, VSS = OV, Tj = O°C to 70°C

Digital Inputs: RXS, MOC, CCl, RTS, ANS, TDA, RTE, COD V22, TXC, BAC, SYN, NSY,LSD

Digital Outputs: C22, RBA, RXD, QUA, TBA, 4CR, TTG, RBY, RXC

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

VOL Output low Voltage 0.4 V IOl = 1.6 MA

VOH Output High Voltage 4.6 V IOH = 1.0 MA

Vil Input low Voltage -0.5 11 V

VIH Input High Voltage 3.5 5 V

III Input leakage Current pA

IDO Power Supply Current 2.5 4 MA

CI Input Capacitance

tR low to High Logic 20 nS C L = 10 pF

Transition Time

tF High to Low Logic 20 nS C L oolOpF

Transition Time

VTXS T ransm itted Carrier -9 dBm VPIN 11 =1 V

Signal Level

XR·2123A FUNCTIONAL BLOCK OIAGRAM

3-27
 XR-2123/2123A

THEORY OF OPERATION

A system using a XR-2123 or XR-2123A would require The baud carrier recovery is similar. After the AGe, the
both additional analog and digital circuitry. The digital signal is applied to a precision full wave rectifier. The baud
circuitry required for the XR-2123, XR-2123A is a scram- rate is always 600 Hz for Bell 212A (1200 BPS) or V.22.
bler/descrambler which is a pseudo-random pattern gene- Sy rectifying the signal, the 600 Hz carrier appears as an
rator. Figure 1 showns a hardware approach of doing amplitude modulation. After the rectifier, the signal is ap-
the scrambler/descrambler. If the modem is intended to be plied to a 600 Hz bandpass filter with an approximate Q of
operated asynchronously, a synchronous-to-asynchronous 20. The phase shift through this portion is very important.
converter is needed. With the XR-2123 or XR·2123A the It must be -180° of phase shift from input to output. This
XR-2125 can be used. If additional features are desired, a is to place the baud clock in the correct reference with the
microprocessor can be used to implement both the scram- recovered bit carrier. This signal is then level-shifted and
bler/descrambler and the synchronous·to·asynchronous applied to Pin 26, SYN. Figure 2 shows the signals after the
converter. XR-2120 after the full wave precision rectifier, after the
600 Hz bandpass filter, and after the level-shifter.
A counter circuit is needed to provide the baud clock
(SAC)' which needs to be synchronized with the 4.608
MHz master clock (MOC)' Bell 201/CCITT standard V.26 implementation with the
XR-2123A requires an additonal filter and a mixer stage in
The analog portion of the modem circuit consists of two the analog portion. V.26/201 is a synchronous data trans-
parts, the bit carrier recovery and the baud carrier recovery. mission and does not require a synchronous-to-asynchro-
The bit carrier occurs at either 1200 or 2400 Hz. A modem nous converter. A scrambler/descrambler is also not re-
filter, such as the XR-2120, can be used to remove out-of- quired, making the digital portion of the modem circuit
band signals. The signal is passed through an automatic gain very simple. A counter circuit to divide down the 4.608
control (AGCl. and then through a level shifter. The signal MHz clock (MOC) for the baud clock (SAC) is the only
from the level shifter is applied to Pin 3 of the XR-2123 digital circuit needed.
or XR-2123A (RXSI.

SCRAMBLED OUTPUT

DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO

c c c c c c c c c c c c c c c c c

~~-----IN-P-U-T-D-M-A----------------------------~~~--------------------~
~--------------_. TRANSMIT DATA CLOCK

Figure 1A. Scrambler

...----oC SCRAMBLED RECEIVED DATA

DO DO DO DO DO DO DO DO DO DO DO DO

c c c c c c c c c c c c c c

DESCRAMBLED OUTPUT

~---------------411. RECEIVED DATA CLOCK

Figure 18. Descrambler

3-28
XR-2123/2123A

The receive portion of the analog circuit will be discussed

first. The received signal is filtered through an 1800 Hz
bandpass filter with -3 dB points at 760 and 2860 Hz. This
can be constructed with discrete components or with a pro-
grammable filter. After the filter, the signal is passed
through an automatic gain control (AGel. A mixer is then
used to bring the 1800 Hz received signal up to 9 kHz. This
signal is filered through a 9 kHz bandpass filter. This filter
should have a Q of approximately 9. The signal is limited
and applied to Pin 3, RXS.

The baud carrier can be seen as a amplitude modulation on

•
the 9 kHz signal. This is filtered off using a 1200 Hz band-
pass filter. The Q of this filter should be approximately 2.
The phase shift through this filter is very important. At
1200 Hz, the phase of the output referenced to the input
Figure 2. Showing received signal after the XA-2120, after
should be _90°. After the 1200 Hz bandpass filter, the I

signal is applied to a level shifter and applied to Pin 26,

full wave precision recitifier, after the 600 Hz bandpass
SYN. filter and after the level shifter_

Figure 3 shows the signal after the mixer, after the 9000
Hz filter and after the 1200 Hz filter. Figure 4 shows one
method of utilizing the XR-2123A for aV.26/201 modem.
To create the optional 75 baud reverse direction, the
XR-2206 and XR-2211 can be used.

The transmit output, Pin 10. of the XR-2123A or XR-2124

requires a low pass filter with a -3 dB point of 3500 Hz.
Either the X R-lO08 low pass filter or a discrete component
filter can be used.

Figure 3. Showing the output of the mixer, the output of

the 9000 Hz filter, and the output of the 1200 Hz band-
pass filter (baud clock recovery).

3-29
 / A.G.C. AND AMPUFIER 1800Hz RECEIVE FILTER \
R55
~

C181 C17,2 1 3,5

C
T1

LINE
IN
4 6

R11
9000Hz CARRIER FILTER \

."
ce'
~
CD

~
n
n
~
<
N
en
N
~
CNO
'aJ
CN"lJ
Orn
~
8.
CD
3

~
l>
"C

g'
><
:J:J
=.o I
::::J
rn I\)
9-
CD
3
~ R34
R44
.....
c:r I\)
':" R45
W
':" ':"
' - - - - - - - - - - - - - 1 2 0 0 H z BAUD F I L T E R - - - - - - - - - - - . - J
~12

~hC30 '~2gC32
FULL WAVE RECTIFIER

-h ".....
I\)
C29
p C33
p C34
I\)

"*" w
»
XR-2123/2123A

INTEGRATED CIRCUITS RESISTORS

A XR-2123 EXAR R1 l.2K R21 2K R41 10K

B XR-1488 EXAR R2 2.2K R22 lOOK R42 10K
C XR-2208 EXAR R3 2.2K R23 10K R43 10K
D DM-74193 National R4 2.2K R24 10K R44 10K
E XR-1489 EXAR R5 2.2K R25 1M R45 10K
F LM-339-N Texas Instruments R6 2K R26 3.32K R46 5.76K
G XR-4741 EXAR R7 24K R27 2.2K R47 2.74K
H XR-4741 EXAR R8 24K R28 lK R48 2.61 K
J XR-1458 EXAR R9 50K R29 lK R49 75K
K F-7404 Fairchild Rl0 50K R30 10K R50 7.87K
L XR-4741 EXAR Rll 200K R31 10K R51 249K
M XR-1458 EXAR R12 43.2K R32 82.2K R52 120K
N XR-4741 EXAR R13 lK POT R33 29.1 K R53 10K
R14 1K POT R34 29.1 K R54 1K
R15 1K POT R35 29.1 K R55 68K
R16 43.2K R36 500n POT R56 1M
CAPACITORS R17 43.2K R37 500n POT R57 10K
R18 109K R38 500n POT R58 4.7K
Cl 82 pf C19 .01 fJ.f R19 109K R39 82.2K R59 lK
C2 .0022 fJ.f C20 .001 fJ.f R20 109K R40 82.2K R60 6.8K
C3 .033 fJ.f C21 .01 fJ.f
C4 033fJ. f C22 100 pf TRANSISTORS
C5 .033 fJ.f C23 2.2 fJ.f 01 2N4861 02 2N4403
C6 .033fJ.f C24 2 fJ.f
C7 .033fJ.f C25 10 fJ.f TRANSFORMERS DIODES
C8 .033 fJ.f C26 .033fJ. f
C9 .033fJ. f C27 1 fJ.f Tl T2220 D1 IN914
ClO .1 fJ.f C28 .1 fJ. T2 T2220 D2 IN914
Cl1 .0033 fJ.f C29 4.7 fJ.f
C12 .0033 fJ.f C30 .1 fJ.f CONNECTOR
C13 .0033 fJ.f C31 4.7 fJ.f
C14 .0033 fJ.f C32 .1 fJ.f J1 RS232
C15
C16
.0033 fJ.f
.0033 fJ.f
C33
C34
4.7 fJ.f
.1 fJ.f
-
C17 .1 fJ.f C35 .0068 fJ.f
C18 .1 fJ.f

Figure 4A. V.26 2400 BPS Modem System Components List

3-31
 XR-2123/2123A

Modulation

The data to be modulated is applied to Pin 17, TDA. This

must be synchronized to the transmitter bit timing clock,
Pin 22, TTG. This internally creates a dibit signal which
then selects the amount of phase shift needed to be encod-
ed properly. This is coherent phase modulation which
means the only phase reference is the phase of the signal be-
fore the transition.

To encode the data, a counter, which accesses the digital-

to-analog converter, is preset to a particular point depend-
ing on the phase change needed. Figure 5 shows four possi-
ble phase shifts with the four bit patters (00, 01, 10, 11)
and the ouput of the XR-2120 filter. It should be noted
that the baud rate stays at 600 Hz whether in originate
(2400 Hz carrier) or in answer mode (1200 Hz data carrier).
0
C. 1 0; 180
The ampl itude of the transm itted signal is controlled by
the TLV, transmitter level, Pin 11. This is a DC input,
typically set for 0.8 VDC. The input draws approximately
15 J.l.A, and can be controlled with a resistor divider or a
digital-to-analog converter for adapting to poor lines. Figure
6 shows the relationship between VTLV and VTXS.

Figure 5. TXS, Transmit Output

Output of 2120, Output of Limiter
Recovered Baud Clock

0
D.1 1; 270

10

~I

10
/
~ ~
~~
~ 20

:>
z
c;: /~
30

~~
40 ~

/if'
50
001 U 1 10 10

Figure 6. TXS vs. VTLV

3-32
XR-2123/2123A

Demodulation PIN DESCRIPTIONS

The demodulator uses a pulse width measuring techni- Pin Name Description
que which compares the pattern received on RXS within
the window set by the baud clock, applied to the syn- VDD +5 VDC ±0_25 V
chronizer pin, SYN This is a coherent demodulation tech-
nique, so no reference phase is needed_ The carrier clock, 2 C22 Carrier clock for Bell 212/V_22. This
CCL, is used to time the widths of the received pulses. output clock is used by the demodu-
As it was shown in Figure 5, the phase changes produce a lator for timing the pulse widths of the
distinctive pulse pattern. The clock frequency applied to received signal. When in the originate
the carrier clock pin, CCL, is changed for each carrier mode, the frequency of the pin is
frequency used. The greater the carrier freq uency, the 614.4 kHz. When the XR-2123 or

•
greater the carrier clock frequency. XR-2123A is set in the answer mode,
the frequency at this pin is 1.2288.
The V.26 demodulation is the same internally. With a 1800 This allows the counter circuit in the
Hz bit carrier and a 1200 Hz phase carrier, only 1'h demodulator to arrive at the same to-
cycles of the 1800 Hz carrier exist within the window cre- tal count for a given baud rate. This
ated by the baud clock. This does not provide enough pin is controlled by v'22, ANS, and
pulses to provide an accurate measurement. Also, the baud COD pins on the device as shown_
clock is not easily recovered with the received waveform.
When the received signal is mixed up to 9000 Hz, the phase
carrier appears as an amplitude modulation. This can be V.22 ANS COD C.22
easily detected with the full wave precision rectifier and a
1200 Hz bandpass filter. 1200 Hz 0 1.2288 MHz

The quality pin, Pin 6, on the XR-2123A is error jitter of 2400 Hz 0 o 0.6144 MHz
the phase-lock loop. It is latched so that it remains high a
minimum of approximately 1 ms. This can be used as an See x x 9600 Hz Mode
indication of the quality of the line in use. If the quality Select Mode
pin is high often, the possibility of errors is greater.
When V_22 is high, C.22 produces a
The received bit timing clock is used to synchronize the 9600 Hz clock. This clock is not nor-
data at Pin 5, RXD. This clock is found on Pin 24, RXe. mally used for V.26 and is NOT appli-
Figure 7 shows the relationship between RXC and RXD. ed to Pin 8, CCL
If the XR-2125 was used, RXC is tied to Pin 9, RXC IN,
and RXD is tied to RXD IN, Pin 10. 3 TXS Received signal input. This is the re-
ceived signal input after level shifting
(0-5 Vl- This signal carries the bit
data.

4 RBA Received baud tlmlng_ This output

I • provides a clock at the baud rate
chosen_ For V.22 and Bell 212, it is at
I 600 Hz. For V.26, it is at 1200 Hz. It
• is derived from BAC and also phase
locked to the signal applied to Pin 26,
SYN.
I

• •
5 RXD Received data. This output is the de-
modulated data from the signals ap-
plied to pins 3 and 26 (RXS and SYN
• • I respectively).

Figure 7. Top Trace RXD, Bottom Trace RXC

3-33
 XR-2123/2123A

6 QUA The quality of demodulation. This pin 11 TlV Transmitter level. This input con-
2123/A shows the amount of error in the tim- trols the amplitude of the transmitter
ing relationship between SYN and output, Pin 10. It typically draws
RBA. If the recovered baud carrier approximately 15 pA and can be ad-
has too much noise, this pin will be justed using a resistor divider circuit.
high for a minimum of approximtely Although not critical, this input
1 ms. Please read the demodulation should be relatively free of any AC
section of this data sheet for more component since it will cause an amp-
detail. litude modulation of the TXS output.

7 MOC Modulator clock input. This is the 12 RLD Received data. This tells the terminal
master clock. For V.22, Bell 212A and that the data to be transmitted has
V.26, this clock is 4.608 MHz. been received by the modem. It is at
the baud rate of the mode the device
is set in. It is counted down from
8 CCl Carrier clock. This input is for the BAC, Pin 25. When R LD goes high,
clock which measures the time that this marks the end of the dibit set.
RXS, Pin 3, is high within one win-
dow. This input is always 512 times
the received bit carrier. For example
if

fRXS= 1200Hz fCCl = 614.4 kHz

fRXS= 2400 Hz fCCl = 1.228 MHz V 221Bell 212A - 180"5rllll

V26/Bell201a 270"Sh,11

fRXS = 9000 Hz fCC l = 4.608 MHz Figure 8. RLD Timing

For V.22 and Bell 212 applications,

CCl is applied from the output C22, 13 4CR Four times the carrie.r frequency. This
Pin 2, of the device. When V.26 is output is used for the V.26 mixer in
needed, CCl is tied to the master the demodulator circuit. For V.22 and
clock, Pin 7. The received frequency Bell 212A it is not used.
of 9000 Hz for V.26 is explained in
the demodulation section. 14 Ground.
VSS

15 RTS Request to send. This input controls

9 TRM Transmit mode. This output indicates
the transmitter output and the TRM,
the state of the modulator. When high,
transmit mode output. The following
the device is transmitting. When low,
chart describes the possibilities:
carrier output is c~ed. It ~n­
trolled by Pin 15, RTS. When RTS is
RTS TRM TXS
low, TRM is high. When RTS is high,
TRM is low.
o carrier
10 TXS Transmitted signal. This is the output
o clamped to DC level
of the internal digital-to-analog conver-
ter. The modulated 8-level sine wave
16 ANS Answer tone. This input controls the
can be seen at this pin. This output is
frequency of the transmitter output.
usually applied to the XR-2120 mo-
It is used along with V.22 and COD.
dem filter.
The details about using this pin is
found under those two pins.

17 TDA Transmitted data. This input is where

data to be transmitted is applied. It
should be synchronized to the trans-
mit clock, Pin 22. TTG. By compar-
ing the data applied to this pin and Pin
12. R LD. the various phase shifts
can be predicted for troubleshooting
purposes.
3-34
XR-2123/2123A

18 RTE Rate. Control RXC, Pin 24, and Pin 23 RBY Received byte timing. This output is a
22, TTG. When set at a logic 1 level, square wave at a frequency 16 times
the frequency at the two outputs is the received baud tim ing. It is not nor-
twice what is normally seen there. mally used.
The block diagram shows the dividers
controlled by RTE. 24 RXC Received bit timing. This output is
synchronized to the recovered baud
19 COD Code. These three inputs determine carrier. It is usually used to perform
the mode of the modulator and de- the asynchronous-to-synchronous
20 V22 modulator of the device. Also, with conversion.
V.22 mode these pins the 2100 Hz tone for
handshaking can be created. The 25 BAC Baud clock. This input is used to cre-
ANS following truth table applies to these ate the modulation and demodulation
answer pins: baud clock. Internal countdown cir-
tone cuitry sets the baud rate at either
600 Hz or 1200 Hz. For V.22/Bell
ANS COD APPLICATION 212A operation, a 307.2 kHz clock is
applied to BAC. For V.26 operation,
o o o Transmit and receive a 614.4 kHz clock isapplied.
at 2400 Hz (high ch.)
This is for analog 26 SYN Synchronization. This input is where
loop back. the recovered baud carrier is applied.
This clock is internally applied to a
o o Transmit and receive phase lock loop which has BAC as
at 1200 Hz (low ch.) the local oscillator. The error vol-
Th is is for analog tage is shown as the difference be-
loop back. tween RXC and RBA. This error out-
put can be found on the quality pin,
o o Transmit at 2400 Hz QUA, Pin 6.
(high ch.) Receive at
1200 Hz (low ch.) 27 New synchronization. This input will
force the received data output to a
o Transmit at 1200 Hz high state. The synchronization takes
(low ch.) Receive at place when the NSY pin is changed
2400 Hz (high ch.) from high to low.

o o Answer Tone at 28 LSD Line signal detector. When high, the

o 1 2100 Hz. receiver is operating normally. When
this input is low, the receiver is clamp-
o V.26 mode ed. This can be tied through an inver-
Phase sh ifts have an ter to the· signal applied to the NSY
initial 90° skew. input.

V.26 mode
Phase sh ifts have an
initial 45° skew.

21 TXC Transmitter bit timing. This input

is usually tied to Pin 22, TTG, timing
for transmitter. For V.22/Bell 212A
(1200 BPS). the frequency at Pin 21
is 1200 Hz. For V.26, the frequency is
2400 Hz. Note: this assumes that Pin
18, RTE, is low in both cases.

22 TTG Timing for transmitter. This output

is appl ied to pin 21 for all standard
uses (V.22, Bell 212A, Bell 201, and
V.26). It is counted down from BAC
clock input. Please read the descrip-
tions for TXC and RTE for details.
3-35
 XR-2123/2123A

u
';;
CQ

E
«II
.c
u
en
c
o

:~c.
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E
«II
"C
o
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N
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ai
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3-36
 XR-2125

Data Buffer
GENERAL DESCRIPTIDN FUNCTIONAL BLOCK DIAGRAM

The X R-2125 is a logic circu it designed to perform the data

buffer function for Bell 212A Type Modem Systems. Both
asynchronous to synchronous and synchronous to asyn- VDC
chronous conversion are performed at nominal data rates of
1200 bits per second. The XR-2125 is selectable for charac-
TXD OUT
ter lengths of 9 or 10 bits. Separate enable/d isable inputs

•
are supplied for async to sync and sync to async converter
sections. These inputs allow the same data lines to be used TXC IN
for asynchronous or synchronous operation.
ClKIN
The receive data buffer section (sync to async) accepts in-
put sync data (typically from the modem demodulator) at
1200 BPS and converts it to a 1219 BPS async data format. RXDIN
The transm it data buffer (async to sync) accepts input
async format data with a data rate of 1200 BPS +1%, RXC IN
-2.5% and it is synchronized to 1200 BPS, which is typical-
ly sent to the modulator. This section also provides break
signal automatic extension. 10/9

The XR-2125 is constructed using silicon gate CMOS tech-

nology for low power operation. Operation is designed for
an input clock frequency of 1.8432 mHz. The X R-2125,
ORDERING INFORMATION
available in a 14 Pin package, is designed for single 5 volt
Part Number Package Operating Temperature
operation.
XR-2125CN Ceramic O°C to 70°C
XR-2125CP Plastic O°C to 70°C

FEATURES

Bell 212A Compatible SYSTEM DESCRIPTION

Asynchronous to Synchronous Conversion
Synchronous to Asynchronous Conversion The X R-2125 provides the complete interface between
Independent Disable Input for synchronous and character - asynchronous data systems.
Receiver and Transmitter Sections The synchronous side consists of two data lines, TXD and
1.8432 MHz Clock RXD, each with their respective clocks, TXC and RXC' The
Break Signal Automatic Extension for Transmitter synchronous portion is designed for data rates of 1200 ±
1200 BPS +1 %, -2.5% Operation .01% BPS. The asynchronous side handles data oriented in
Single 5 Volt Operation characters where the actual data bits are bracketed by a
start and stop bit. Character lengths are 9 or 10 bit (7 or
8 data bits), pin selectable.
APPLICATIONS
To perform this interface, the XR-2125 consists of two
main sections: synchronous to asynchronous (receive
Bell 212A Data Buffer
section) converter to reinsert stop bits deleted by the
sending modem. The other section is the a synchronous to
synchronous converter (transm it section) to add or delete
ABSOLUTE MAXIMUM RATINGS stop bits to correct the transmit data rate to 1200 BPS.
This section also extends the break signal to two char-
Power Suppiy -0.3 to +7.0 V acter lengths plus three bits when it comes in at a short-
Input Voltage -0.3 to VDD +0.3 er period.
DC Input Current (any input) ±1O mA
Power Dissipation 250mW A standby mode is included to put the X R-2125 in a low
Storage Temperature Range -65°C to +125°C supply current, non-operative, mode on command.

3-37
XR-2125

ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 5 V ± 5%, TA = 0-70°C, ClK IN = 1.8432 MHz ±O.Ol%, unless otherwise specified.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

DC CHARACTERISTICS

VOL Output low Voltage 0.05 0.8 V IOl = 2 mA

VOH Output High Voltage 2.4 V 10M = -400 ~A

Vil Input low Voltage 0.8 V

VIH Input High Voltage 2.4 V

IOl Output low Current 2 mA

IOH Output High Cu rrent -400 ~A

liN Input Current ±1O ~A VIN=O-VDD

100 Supply Current Quiesent 100 250 ~A

100 Supply Current Standby 10 ~A

AC CHARACTER ISTICS: fTXC IN = 1200 ±0.01% Hz, f RXC IN = 1200 ±0.01% Hz.

twstr Start Bit Width 820 ~s

twstp Stop Bit Width

9 Bit Character 938 ~s Reinserted Stop Bits and (n)
lOB it Character 951 ~s (820 ~s) long

ftxd TXD in Bit Rate 1170 1200 1212 BPS

tdtxd TXD Out Delay Time 200 ns Cl = 50 pf; 10/9 = Hi

tdrxd RXD Out Delay Time 200 ns 10/9 = Hi
f rxco RXC Out Frequency 1219 Hz

3-38
 XR-2125

RECEIVE TIMING

Rxc

RXD OUT

•
TORXD

TRANSMIT TIMING

TXC

Txo OUT

TOTXO

TRANSMIT AND RECEIVE TIMING CHARACTERISTICS

10/9

....--_ _ _ _ _----.19.2 KHZ RS

ClKIN +96 COUNTER PRESETTABLE +16 COUNTER

TX EN

RX EN RXDIN

RXCIN

RXD OUT 5 1-------+------4

RXC OUT 6 1---------1

EQUIVALENT SCHEMATIC DIAGRAM

3-39
XR-2125

DESCRIPTION OF INPUTS AND OUTPUTS

Pin Name Description

This pin places the XR-2125 in a 11 ClKIN Master clock input of 1.8432 Hz
non-operative, low quiesent current ±0.01%.
mode.
12 TXC IN The transmit clock input which is
2 TXEN An enable input for the transmitter typically supplied by the modulator
section (async to sync). When en- (XR-2121J. The frequency should be
abled, async to sync conversion is 1200 Hz ± 0.01 %.
performed on TXD IN. When dis-
abled, the data on TXD OUT will be 13 TXD OUT The synchronous serial data output
identical to that of TX DIN (flow which typically goes to the modula-
through mode) In Bell 212A type tor input (XR-2121). The data rate
modem applications the sync to of this signal is 1200 BPS ± 0.01%.
async will be disabled for 300 BPS
FS K operation and for 1200 BPS 14 VDD This pin provides the input for the
synchronous operation. positive power supply which should
be +5 ± 0.25 volts.
3 RX EN An enable input for the receiver
section (sync to async). When en-
abled, sync to async conversion is
CONTROL INPUTS
performed on RXD IN. When dis-
Table 1 gives the logic conditions for the various control
abled, the data on RX OUT will be
inputs of the X R-2125.
identical to that of RX DIN (flow
through mode). In Bell 212A type
FUNCTION
modem applications the sync to
PIN NAME lOGIC HIGH lOGIC LOW
async will be disabled for 300 BPS
FSK operation and for 1200 BPS
SB Normal Operation Standby Mode
synchronous operation.
2 TXEN Transm itter Transmitter
4 TXD IN The transmitter data input. This is
Enabled Disabled
a serial data stream with a data rate
of 1200 BPS +1%/-2.5% (TX EN
3 RXEN Receiver Receiver
active).
Enabled Disabled
5 RXD OUT The asynchronous serial data out-
8 10/9 10 Bit Character 9 Bit Character
from the sync to async converter
(RX EN active). The data rate of
Table 1. Control Input Conditions
this signal is 1219 BPS.

6 RX ClK OUT Received clock output.

PRINCIPLES OF OPERATION
7 VSS Ground pin.
The XR-2125 performs the complete asynchronous to syn-
chronous and synchronous to asynchronous conversion
8 10/9 Asynchronous character length se-
on the serial transmit and receive data paths in a Bell 212A
lection input. Ten bit (start bit, 8
type modem. This conversion allows the synch modulator/
data bits and a stop bit) or nine bit
demodulator such as the XR-2121/XR-2122 to communi-
( 7 data bits) can be selected.
cate with the async DTE. The async format is character
type as shown in Figure 1.
9 RXC IN The receive clock input, which
typically is supplied by the demodu-
lator (XR-2122). The frequency
should be 1200 Hz ± 0.01%.
T,

10 RXD IN The synchronous serial data input

I \
which is typicaIJ from the demodu- 1 - - - - - - 1 CHARACTER------+i: NEXT START BIT
lator data output (RX D of the X R-
2122). The data rate of this signal is
1200 BPS ± 0.01%. Figure 1. Async Character
3-40
 XR-2125

Figure 1 shows each character starting with a start bit X R-2125 into the high speed asynchronous mode. The
(T1) followed by either 7 or 8 data bits (8 shown + T2 - main function of the XR-2125 is to synchronize asyn--
T9) and ending by a stop bit T10} this makes a total chronous data (1200 BPS + 1% - 2.5%) from the DTE to
character length of either 9 or 10 bits, which the XR-2125 synchronous data (1200 BPS) for the modulator, and to
can be selected for by pin 8, 10/9. take synchronous demodu lated data (1200 BPS) and con-
ver it to the 1219 BPS asynchronous format for the DTE.
The XR-2125 can also provide "flow through" operation
by disabling the transmit and receive sections using pins
2 and 3, TXEN and RXEN. This mode would be used
for 1200 BPS sync mode or 300 BPS bit async operation. The break detector serves to distinguish between an actual
break character and two consecutive nulls with the stop
Figure 2 illustrates a typical connection of the X R-2125. bit deleted. It forces reinsertion of the stop bit between the

•
Pins 2 and 3 (TXEN and RXEN) are used to toggle the nulls and passes

V DD V DD

HIGH SPEED ASYNCHRONOUS SELECT o-----...-~ 1 - - - - - - - 0 ( ) TO MODULATOR T xc IN

1 - - - - - - - 0 ( ) FROM MODULATOR T XCLK

TRANSMIT DATA FROM DTE o------~ 1 - - - - - - - 0 ( ) 1.8432 MHz INPUT

RECEIVED DATA TO DTE o------~ 1 - - - - - - 0 FROM DEMODULATOR RXD OUT
1 - - - - - - - 0 ( ) FROM DEMODULATOR RXCLK
1 - - - - - - - 0 ( ) CHARACTER LENGTH SELECT

Figure 2. Typical Connection XR·2125

3-41
 XR·14412

FSK Modem System

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-14412 contains all the necessary circuitry to
construct a complete FSK modulator/demodulator
(MODEM) system. Included is circuitry for pin- Voo
programmable frequency bands, either U.S. or foreign
(CCITI) standards for low-speed MODEMS. The
XR-14412 provides T2L-compatible inputs and outputs. TTLD
Included in the XR-14412 are features for self-testing
and an echo suppression tone generator. The XR-14412
TYPE
utilizes complementary MOS technology for low-power
operation.
ECHO

Tx EN
FEATURES
Simplex, Half-Duplex, and Full-Duplex Operation Tx DATA
Crystal Controlled
Answer or Originate Modes MODE
Single Supply Operation
Self-test Mode
Selectable Data Rates-300, or 600 bps TXCAR

T2L- or CMOS-Compatible Inputs and Outputs

Echo Suppressor Disable Tone Generator
U.S. or Foreign (CCITT) Compatible
ORDERING INFORMATION
Operating
Part Number Package Voltage Range
APPLICATIONS
XR-14412FP Plastic 4.75V to 15V
Stand-Alone MODEMS XR-14412VP Plastic 4.75V to 6V
Remote Terminals XR-14412FN Ceramic 4.75V to 15V
Acoustical Couplers XR-14412VN Ceramic 4.75V to 6V
Built-in MODEMS
SYSTEM DESCRIPTION
The XR-14412 is basically comprised of two main com-
ABSOLUTE MAXIMUM RATINGS ponents; the FSK modulator and demodulator. The
modulator serves to convert or encode incoming binary
Power Supply data into two discrete frequencies. The pair of frequen-
XR-14412F 15V cies generated are determined by which standard (US
XR-14412V 6V or CCITI), and mode (answer or originate), are select-
Any Input Voltage VDD + .5V to VSS - .5V ed. These frequencies are within a range suitable for
Output Current from any Pin 10 mA transmission over the telephone lines. The demodulator
(Except Pins 7 or 8) performs the opposite function by decoding the re-
Output Current from Pin 7 or 8 35 mA ceived pairs of frequencies into binary data. It also re-
Operating Temperature Range -40°C to +85°C sponds to those frequencies selected by the standard
Storage Temperature Range - 65°C to + 150°C and mode selected. All functions within the XR-14412
Power Dissipation are digital and controlled by a master clock. This clock
Ceramic Package 1000 mW is generated by an external crystal connected between
Derate Above TA = + 25°C 8.0 mW/oC the OSCIN and OSCOUT pins. As well as being used in-
Plastic Package 625mW ternally by the 14412, the clock may be used to clock
Derate Above TA = + 25°C 5.0 mW/oC other circuitry by using the OSCOUT pin.

3-42
XR·14412
ELECTRICAL CHARACTERISTICS

-40°C +25°C +85°C

VOO··
SYMBOL PARAMETERS Vdc MIN MAX MIN TYP MAX MIN MAX UNIT
vOL Output Voltage "0" Level 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
VIN=VDD or 0 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
VOH "1" Level 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
VIN=O or VDD 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
VIL Input Voltage* "0" Level Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO = 9.0 or 1.0 Vdc) 10 - 3.0 - 4.50 3.0 - 3.0
(VO = 13.5 or 1.5 Vdc) 15 - 4.0 - 6.75 4.0 - 4.0
VIH

IOH
(VO = 0.5 or 4.5 Vdc)
(VO= 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

Output Drive Current

(VOH=2.5)
(VOH=9.5)
"1" Level

(Pin 7)
5.0
10
15
Pins 12, 15 5 to 15

5
10
3.5
7.0
11.0
0.75

-0.62 -
-0.62 -
-
-
-
-
3.5
7.0
11.0
0.8

-0.5
-0.5
2.75
5.50
8.25
2.0

-1.5
-1.0
-
-
-
-
-
-
3.5
7.0
11.0
0.85

-0.35
-0.35
-
-
-
-
-
-
Vdc

mAdc
•
(VOH= 13.5) 15 -1.8 - -1.5 -3.6 - -1.1 -
IOL (VOL =0.4) 4.75 2.3 - 2.0 4.0 - 1.6 - mAdc
(VOL =0.5) 10 5.3 - 4.5 10 - 3.6 -
(VOL = 1.5) 15 15 - 13 35 - 10 -
liN Input Current (Pin 15 = VDD) - - - - ±0.00001 ±0.1 - - ILAdc
Ip Input Pull-up Resistor Source Current 5 285 - 250 460 - 205 - ILAdc
(Pin 15=VSS, VIN=2.4 Vdc)
Pin 1,2,5,6,10,11,12,13,14

C'N Input Capacitance - - - - 5.0 - - - pF

IT Total Supply Current 5 - 4.5 - 1.1 4.0 - 3.5 mAdc
(Pin 15=VDD) 10 - 13 - 4.0 12 - 11
15 - 27 - 8.0 25 - 23
ACC Modulator/Demodulator Frequency 5 to 15 - - - 0.5 - - - %
Accuracy
(Excluding Crystal)
V2H Transmit Carrier Output 5 to 10 - - -20 -26 - - - dB
2nd Harmonic 10 to 15 - - -25 -32 - - -
VOUT Transmit Carrier Output 5 - - 0.2 0.30 - - - VRMS
Voltage (RL = 100 kO) 10 - - 0.5 0.85 - - -
(Pin 9) 15 - - 1.0 1.5 - - -
tTLH, Receive Carrier Rise and 5 - 15 - - 15 - 15 ns
tTHL Fall Times (Pin 1) 10 - 5.0 - - 5.0 - 5.0
15 - 4.0 - - 4.0 - 4.0

*DC Noise Immunity (VIL,VIH) is defined as the maximum voltage change from an ideal "0" or "1" input level,
that the circuit will withstand before accepting an erroneous input.
* * Note: Only 5-Volt specifications apply to XR-14412VP devices.

3-43
 XR·14412
EQUIVALENT
SCHEMATIC TRANSMIT
ENABLE 12

DIAGRAM TRANSMIT
DATA 11

"",PUlL·UP
DlSABl.E 15
1 RECEIVE
CARRIER

RECEIVE
DATA RATE '

RECEIVE
CATA 1

vDD

Yoo ,. Pin 16
VSS .. Pin I

FIgure 1. Typical
XR_1441:~nection
C of the
Modem sma Complete
ystem

Figure 2. 'Iiransmit Carrier S·me Wave Figure 3. 'Iiyplcal Transmit Carrler Frequency Spectrum

3-44
 XR·14412
PRINCIPLES OF OPERATION Receive Carrier (RX CAR. Pin 1): The FSK-encoded receive
carrier is fed into this input. The input signal must have
Figure 1 shows the typical connection for the XR-14412 either TIL or CMOS logic levels with a duty cycle of
as a modem system. The system has four main compo- SO% ± 4%.
nent blocks. They are FSK modulator and demodulator,
which are contained in the XR-14412, the bandpass fil- Receive Data Rate (RX RATE. Pin 6): This input is used to
ter, and the line hybrid. The function of each block is as adjust the demodulator for the incoming data rate.
follows:

line Hybrid: This block acts to direct received FSK infor-

Self-Test (ST. Pin 2): When a high level (ST =
"1") is
placed on this input, the demodulator is switched to the
mation to the bandpass filter and demodulator, while
modulator frequency and demodulates the transmitted
the FSK modulated carrier is directed to the telephone
FSK signal.
network.

Bandpass Filter and limiter: Received FSK information is Reset (RS, Pin 5): This input can be used to disable the
filtered by this block to remove extraneous signals re- demodulator. With reset at logic "1", the demodulator
ceived from the telephone network. The local transmit- output is forced high, logic "1 ". For normal operation,

•
ter carrier is also filtered out. The limiter stage is used reset is tied low, logic "0".
to provide the XR-14412 with a TTL- or CMOS-
compatible signal. Crystal (OSCIN. OSCOUT. Pin 4, Pin 3. respectively): A
1.0 MHz crystal is connected between these two pins
Modulator: This block, contained in the XR-14412, con- for utilizing the on-chip oscillator. An external oscillator
verts serial binary data into an FSK-encoded carrier sig- can also be used by feeding it into the OSCIN, Pin 4, in-
nal. The carrier frequency is controlled by the mode put. In the crystal mode, external paraSitic capaci-
and type inputs. Input data must be TIL- or CMOS- tance, including crystal shunt capacitance, must be
compatible. The output of the modulator is a digitally less than 9 picofarads at Pin 4.
synthesized sine wave (see Fig. 2), with its harmonic
content shown in Fig. 3. TTL Pull-Up Disable (TTLD, Pin 15): All of the inputs to the
XR-14412 have on-chip pull-up resistors. These pull-up
Demodulator: This is used to convert an FSK-encoded resistors may be disabled when interfacing to CMOS
carrier signal into serial data. The rate at which data logic by taking the TILD input to a logic" 1". For TIL
can be received and decoded is controlled by the RX logic interfacing, TILD is tied to a logic "0".
rate and type control inputs.

Description of Control Inputs-Refer to Figure 1 and Table 1.

Type (Pin 14): This input is used to select either U.S. or APPLICATIONS
CCITI operating frequencies.
Figure 4 shows the XR-14412 connected as a 300-baud
Transmit Data (TX DATA. Pin 11): This is the input for binary FSK modem. Amplifiers A1 - A3 are connected as
serial data. bandpass filters to remove extraneous signals picked
up from the phone line as well as local oscillator isola-
Transmit Carrier (TX CAR. Pin 9): This output provides a tion. A4 is connected as a comparator to provide limit-
digitally synthesized sine wave derived from a 1 MHz ing to the received carrier and provide the necessary
crystal oscillator. The carrier frequency is controlled by square wave for Pin 1, RX CAR, input. AS acts as a line
the type and mode inputs. hybrid. It provides amplification to the received carrier
while attenuating the local oscillator, trying to go toward
Transmit Enable (TX ENABLE. Pin 12): This pin is used to the bandpass filter. A6 is simply used to buffer the TX
enable and disable the modulator, or TX CAR, output. CAR, Pin 9, output of the XR-14412.

Mode (Pin 10): In conjunction with the type input, the The configuration as shown is for answer mode, as the
carrier frequencies are selected with this input. mode pin is at a logic "0". This circuit will work over a
received carrier range of - 10 dBm to - 40 dBm.
Echo (Pin 13): This input is used to program the modula-
tor to produce a 2100-Hz tone for disabling line echo Figure S shows a connection using the two spare ampli-
suppressors. fiers from the XR-346 to provide a carrier detect output.
Here A7 acts to amplify and peak detect the received
Receive Data (RX DATA. Pin 7): This is the binary data out- carrier from the output of the bandpass filter. This volt-
put resulting from demodulating the FSK-encoded re- age is then fed to A8, connected as a comparator, to
ceive carrier. provide a logic output for carrier detect indication.

3-45
Table 1. Input/Output Controls
XR·14412
INPUTS OUTPUTS
TX ENABLE RX RATE MODE TYPE ECHO
(12) (6) (10) (14) (13) STANDARD MODE TX DATA TX CARRIER BAUD RATE
1 0 1 1 0 US ORIGINATE MARK 1 1270 Hz 600 bps
1 0 1 1 0 US ORIGINATE SPACE a 1070 Hz 600 bps
1 0 0 1 0 US ANSWER MARK 1 2225 Hz 600 bps
1 0 0 1 0 US ANSWER SPACE 0 2025 Hz 600 bps

1 1 1 1 a US ORIGINATE MARK 1 1270 Hz 300 bps

1 1 1 1 0 US ORIGINATE SPACE 0 1070 Hz 300 bps
1 1 a 1 0 US ANSWER MARK 1 2225 Hz 300 bps
1 1 a 1 0 US ANSWER SPACE 0 2025 Hz 300 bps

1 1 1 0 a CCITI CHANNEL 1 MARK 1 980 Hz 300 bps

1 1 1 0 0 CCITI CHANNEL 1 SPACE a 1180 Hz 300 bps
1 1 0 0 0 CCITI CHANNEL 2 MARK 1 1650 Hz 300 bps
1 1 a 0 0 CCITI CHANNEL 2 SPACE a 1850 Hz 300 bps
1 X a 0 1 CCITI CHANNEL 2 - 1 2100 Hz -
0 x x x x - - - - NO OUTPUT -
1 - Input or output IS at a digital high, refer to Electrical Characteristics for exact value.
o- Input or output is at a digital low, refer to Electrical Characteristics for exact value.
X - Can be either a 1 or a O.

0.01 ~, 0,011"-' O.OI,.F

XR·U41Z

DATA TO
BE SENT

AI-A4 =. XR·346
AS-A6 = . 'I, XR·346 L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ ~:~:,VED

• CRYSTAL MODE - PARALLEL

FREQUENCY -IMHz ~ 0.1%
= =
RS 540 II TYP, Co 7 pF TYP
SUGGESTED SUPPLIERS
TYCO. CTS KNIGHT, MOTOROLA CRYSTAL PRODUCTS
•• FOR DIRECT CONNECT TO PHONE LINE, SYSTEM MUST BE APPROVED BY FCC
TI = .' MICROTRAN Tll04 OR EQUIVALENT
PI =/ ADJUSTED FOR 50% SQUARE WAVE AT Rx CAR INPUT AT MINIMUM RECEIVED CARRIER

Figure 4. Complete 300 Baud, Answer Mode, FSK Modem

+5V
2.2 M

10K 82011
22K
TO (+) INPUT A4 --w'V---+-;

TO (+)INPUT A3 _-----~ >-_-4-__ --o=R

A7-A8 = . 'h XR·346
Dl = . L.E.D. 3.3~F J
+
20K

Figure 5. Carrier Detect Circuit

3-46
 XR·14412

GRNO.
PHONE LINE
PHONE LINE

+SV

DATA TO X·MIT
DATA RECIEYED
GRNO.

COMPONENT
SIDE
SHOWN

(SCALE 32:1)

Figure 6. Complete FSK Modem Printed Circuit Board Layout

(Circuit Shown In Figure 4)

Table 2. Parts List for 300 Baud MODEM.

'*1 % tolerance; all other resistors are 1/4W, 10%; all capacitors are 10%.
Resistors are in ohms and capacitors are in ILF.

ANSWER ORIGINATE ANSWER ORIGINATE

'*R1 40.2K 47.SK R24 20K 20K
'*R2 499 191 R26 500 SOO
*R3 270K 357K '*R27 600 600
'*R4 383K 270K
*RS 680 160 C1-C6 .01 .01
'*R6 60AK 39AK C7 .1 .1
'*R7 160K 160K C8 22 22
*R8 24.9K 20K C9 .01 .01
*R9 1.21 K 360 C10 4.7 4.7
R10-R11 1K 1K C11 3.3 3.3
R12 SOOK SOOK
R13 SOOK Pot SOOK Pot 01 IN914 IN914
R14 10K 10K 02 LED LED
R15 220K 220K
R16 1SM 1SM T1 Microtran Microtran
R17-R18 10K 10K T1104 T1104
'*R19 600 600
R20 220K 220K CRYSTAL 1 MHz ± .1 % 1 MHz ± .1 %
R21 22K 22K
R22 2.2M 2.2M A1-A8 XR·346 XR·346
R23 3.0K 3.0K
R24 20K 20K MODEM 1C1 XR·14412VP XR·14412VP
R2S 30K 30K

3-47
 Section 3 - Data Communication Circuits
Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
XR-2103 Modem Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
XR-2120 PSK Modem Filter . . . . . . . . . . . . . . . . . . . . . . 3-55
XR-2126/2127/2128/2129 Bell 212A1CCITf V.22 Modem Filters . . . . . . . . . . . 3-62

II

3-49
 XR-2103

FSK Modem Filter

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-2103 is a Monolithic Switched-Capacitor Filter de-

signed to perform the complete filtering function necessary
for a Bell 103 Compatible Modem. The XR-2103 is specifi-
cally intended for use with the XR-14412 ModulatorlDe-
modulator to form a complete stand alone two-chip mo-
dem. I n addition to complete high and low bandpass filters,
the XR-2103 contains internal mode switching, auto-zero-
ing limiter and dedicated duplexer op amp. An on board
carrier detect circu it is also included to complete the overall
system. Designed for crystal-controlled operation, the X R-
2103 operates from a 1.0 M Hz crystal or external clock.
Buffered clock output is provided for the X R-14412. A
self-test circuit is included.

The XR-2103, available in a 20 pin package, utilizes CMOS

technology for low power operation with a supply voltage
range from 4.75V to 6V.

FEATURES

Single 5 Volt Operation

Complete On Board Output Active Filters
Low Supply Current
Internal Answer/Originate Mode Switching
Programmable I nput Receive Gain
Carrier Detect Output
Active Duplexer

ORDERING INFORMATION

Part Number Package Operating Temperature

APPLICATIONS XR-2103CP Plastic O°C to 70°C
XR-2103CN Ceramic O°C to 70°C
Bell 103 Transmit/Receive Filtering
Complement to XR-14412 or Other
Modulators/Demodulators
SYSTEM DESCRIPTION

The XR-2103 internally consists of four main signal blocks.

ABSOLUTE MAXIMUM RATINGS They are: input and output multiplexers to route the trans-
mit and receive signals to the proper filter and output, ac-
Power Supply 16V cording to the mode input; high and low band filters, 6
poles each, to perform precise bandpass filtering; output
Power Dissipation Plastic Package 650mW
RC active filters to perform output reconstruction and
Derate Above 25°C 5.0 mWtC
filtering; carrier detection circuit for system interfacing.
Power Dissipation Ceramic Package 1.0W
Derate Above 25°C 8.0 mWtC An input amplifier with programmable gain is provided for
Operating Temperature O°C to 70°C the receive signals. The XR-2103containsan internal clock
Storage Temperature -65°C to 150°C oscillator which accepts either a crystal or an external oscil-
Any Input Voltage (VDD + 0.5V) to (VSS -0.5V) lator of 1 MHz.

3-50
 XR-2103

ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 5V, VSS = OV, XIN = 1.0 MHz, T A = 25°C, unless specified otherwise.

SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS

VDD Power Supply Voltage Range 4.75 6 V VSS= 0

IDO Power Supply Current 7 10 mA VDD = 5V

ANALOG SECTION
RECEIVE AMPLIFIER
VOS Offset Voltage -150 150 mV
AOL Open Loop Gain 80 dB RL = 100k
IB Input Bias Current 1 pA
SR Slew Rate 2 V/J,lS
Output Swing 3 4.5 Vp-p RL = 100k to GND (Pin 2)

DUPLEXER
Isolation 44 dB R2 = Line Resistance = 600n
Output Swing 3 4.5 Vp-p
VOS Offset Voltage -150 150 mV

LIMITER
Output Symetery ±1.5 ±2.0 % Cc - 0.1 J,lf, from 50% Duty Cycle
Output Swing 4 Vp-p RL = 1 meg
Output Current 100 IJ.A RL = lk
CARRIER DETECT
Vth Threshold Voltage -48 dBm Receive Amplifier Gain -24 dB
Hysteresis 2 4 6 dB
ton Turn On Time >100 msec Ccd = 0.1 J,lf, Vin = 48 dBm, Gain = 24d6
toff Turn Off Time .;;;100 msec

LOW BAND FI L TER

fa Center Frequency 1160 1170 1180 Hz
BW Bandwidth 500 Hz
Vfs Full Scale Input 2.5 Vp-p
Ar Pass Band Gain 3 4 5 dB
DR Dynamic Range 50 dB
PSRR Power Supply Rej. 15 dB f = 2 KHz
Pass Band Ripple 2 dB p-p 1070 Hz-1270 Hz
High Band Rejection 40 dB 2025 Hz-2225 Hz
GD Differential (Group) Delay 200 500 J,lS 1070 Hz-1270 Hz
Clock Feedthrough -60 dBV 62.5 kHz
HIGH BAND FILTER
fa Center Frequency 2105 2125 2145 Hz
BW Bandwidth 500 Hz
Vfs Full Scale Input 2.5 Vp-p
Ar Pass Band Gain 3 4 5 dB
DR Dynamic Range 50 dB
PSRR Power Supply Rej. 18 dB f = 1 kHz
Pass Band Ripple 2 dB p-p 2025 Hz - 2225 Hz
Low Band Rejection 40 dB 1070 Hz - 1270 Hz
GD Differential (Group) Delay 200 500 J,lS 2025 Hz - 2225 Hz
Clock Feedthrough -60 dBV 62.5 kHz
TRANSMIT
VOS DC Offset Voltage -150 +150 mV
Output Swing 2.2 Vp-p R2 = Line Resistance = 600n
Output Current 1.2 mA

DIGITAL CMOS LOGIC LEVELS (VDD = 5V, VSS = 0 V)

Vih Input Voltage 2.75 3.5 V '1' Level
Vii Input Voltage 1.5 2.25 V '0' Level
loh Output Current 0.5 1.5 mA '1' Level CLK OUT
101 Output Current 1.0 5.0 mA '0' Level CLK OUT
loh Output Current 0.1 1.5 mA '1' Level X OUT
101 Output Current 0.2 0.9 mA '0' Level X OUT

3-51
 XR-2103

OPERATING PRINCIPLES

The XR-2103 contains all the filtering and multiplexing swings of 4.5 Vp-p, and a slew rate of 2V/j.ls. This pin-out
functions necessary for a Bell 103 type (300 baud) FSK allows flexible signal processing capabilities: for example,
modem. A complete modem requires only the XR-2103, an input low pass filter for eliminating aliasing is easily
the XR-14412, and telephone line interfacing hardware. A achieved.
description of the main functional blocks follows.
Auto·Zeroing Limiter: An automatic offset zeroing com-
Bandpass Filtering: Two six pole, 500 Hz bandwidth parator (limiter) compensates for errors caused by system
switched capacitor fi Iters, designed for Bell 103 standard offset voltages and currents, and converts the received car-
center frequencies of 1170 Hz (low band) and 2125 Hz rier into an accurate 50% duty cycle waveform. The resul-
(high band). constitute the main portion of the device. tant square wave on Pin 16 is at digital logic levels and can
Both filters feature +4 dB passband gain, 50 dB dynamic interface directly with the modulator/demodulator circuit.
range, and more than 40 dB opposite band rejection. Filter
response curves are depicted in Figure 3. On board multi- Carrier Detector: An on board carrier detection circuit
plexing allows using these filters for both transm itting and simplifies total system interfacing. Carrier detect output
receiving. Active low pass filters reconstruct the time (Pin 18) pulls low when a suitable signal is received. With
sampled output signals, characteristic of switched capacitor 14 dB of gain in the receiver preamplifier, the threshold
filters, and attenuate the unwanted energy above 15 kHz. level is -38 dBM and has 4 dB of hysteresis. Turn on/off
delay time is externally programmable by a capacitor from
Duplexer: An operational amplifier is employed as an active Pin 19 to ground. A 0.1 J.1F unit yields 100 ms; delay is
two to four wire converter (duplexer). The two phone wires
directly proportional to capacitance.
are "split" into transmit and receive components for proper
processing; the transmit output from Pin 8 is applied to the
lines through a resistor and the received signal is drawn Clocking: Filter frequency accuracy is directly related to
from the line and routed into a preamplifier. Transmit the clock frequency. The device operates within specifi·
energy appears as a common mode signal, hence does not cations with a 1 MHz clock. provided by either a 1 MHz
appear on the duplexer output. The received signal, mean- crystal or by sharing the 1 MHz clock signal from the
while, is amplified by two. Isolation is maximized when X R-14412. The device will operate at other clock fre-
the transmit injection resistor (between Pins 6 and 8) is quencies. but the filter center frequencies will differ. The
equal in magnitude to the phone line impedance (600 n crystal and a parallel 10 Mn resistor are attached between
nominal). Transmit signal levels are typically -9 dBm. Pins 11 and 12. The crystal should be series resonant with a
shunt capacitance less than 9 pF. Pin 10 is the buffered
clock output for interconnection with other devices.
Received Carrier Amplifier: An operational amplifier, with
its inverting input on Pin 20 and output on Pin 3, serves
as a received carrier amplifier. Duplexer output (Pin 7) is
Self Test: An on board self test diagnostic activates an ana-
routed to Pin 20 through a 100 kn or larger resistor. Gain,
log loop-back mode: the transmit carrier is routed through
typically 5 (14 dB). equals the ratio of the feedback resis- the proper filter and back through the receive limiter,
tor (Pin 3 to Pin 20) to the input resistor (Pin 7 to Pin 20). allowing performance verification of all systems. TX OUT
The non-inverting input is internally biased to one half sup- and RX IN are disabled when self test is high.
ply. The amplifier features open loop gain of 80 dB, output

' - - - - - - - - - - - - - - - - - - ; 8 T"ouT

EaUIVALENT SCHEMATIC DIAGRAM

ST 9~------------------~

3-52
XR-2103

100kQ

510kQ
Voo ~5v

MODE
SELECT

TX INPUT 1 - - - - - - - - 0 RX CARRIER OUTPUT

1"F

(~Q
FILTER OUTPUT

R2

SELF TEST

BUFFERED CLOCK
OUTPUT

Figure 1. Basic Applications Circuit

Carrier detect threshold is '38dBm in this configuration.

~
LOGIC INPUT
0 1
+4
,---
MODE ORIGINATE
II '\
ANSWER

ST NORMAL OPERATION SELF TEST MODE

I \
I \
I \
Figure 2. Control Inputs I \
I \
-20
I \
I \
I \
10K I \
I \
-40
I \
I \
2
/~ - \
\
I
I
I
---:,---/-1 \

\ /
-50
\j \ /
\ I
\I
-80L-_ _ _ _ ___ __________________
\I
~
~
~
~
~
~
~
920 "70 1420 1875 2125 2375

FREQUENCY lfizl

Figure 3. Reference Voltage Trimming for Performance Figure 4. Filter CharacteristiCi

Optimization

3-53
 XR-2103

APPLICATIONS

The Bell 103 compatible modem of Figure 5 consists of the pulls low after a 100 ms delay, controlled by the 0.1 IlF
XR-2103 FSK modem filter and the XR-14412 FSK modu- capacitor on the CCD pin (Pin 19). The limiter circuit
lator/demodulator. Designed for full duplex 300 baud op- compensates for circuit imperfections (offset voltages, etc.).
eration, the circuit requires only telephone line and compu- and outputs a 50% duty cycle waveform to the demodu-
ter interfacing. The entire system uses a single 5V supply, lator input (Pin 1) of the XR-14412. The demodulated data
appears on Pin 7 of the X R-14412.
and performs both answer and originate functions. Answer/
Originate selection is controlled by the mode input; low
Transmit data is applied to the modulator input (Pin 11) of
inputs select answer, high selects originate. the XR-14412. Depending on mode, answer or originate,
the data modulates either the high or low band. The modu-
The telephone line is connected via an isolation transformer lated signal exits Pin 9 and is applied to the transmit multi-
to the duplexer input (Pin 6) of the XR-2103. A resistor, plexer input (Pin 5) of the XR-2103; is filtered, recon-
equal to the line resistance, attaches from Pin 6 to the structed, and sent into the duplexer and the phone line.
transmit output (Pin 8) and couples the transmit signal to
the line. The received signal is removed from the line via the One shared time base is employed: here, the oscillator
duplexer (also called a "two to four wire converter" or of the X R-21 03 serves both devices. Buffered output is
"hybrid"). Duplexer output is coupled through the receive routed from Pin 10 of the XR-2103 into Pin 4 of the XR-
14412.
carrier preamplifier into the multiplexer, where the proper
band pass filter is selected. Transmit energy is seen as a
With suitable telephone line coupling and data system
common mode signal and does not appear on the duplexer
interfacing, this modem realizes its goals of high perfor-
output. mance and reliability at low cost.

If the system is in the originate mode (mode pin pulled

high). the received signal passes through the high band fil-
ter. Then, the sampled signal is reconstructed by an on
board RC active low pass filter and is fed into the limiter
and carrier detect circuit. Carrier detect output (Pin 18)

100K

510.

CARRIER
DETECT

Tx DATA

MODE

'--------------+-+-0 Rx DATA

L..:====================:i:==============--o ~~6pT~~bK)
Figure 5. 8ell103 Compatible Modem

3-54
 XR-2120

PSK Modem Filter

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The X R-2120 is a self-contained bandpass fi Iter set designed

for realization of Bell 212A compatible 1200 bits/sec PSK Voo ClK OUT
modems. The XR-2120 utilizes CMOS technology and
switched capacitor circuit techniques to minimize external ClK IN
XOUT
components to a single crystal or frequency source. Con-
tained in the device are two complete bandpass filters cen-
tered around the Bell standard 1200 Hz and 2400 Hz send DIG Vss

and receive frequencies. These filters also provide compro-

mise line equalization. Additional features included are INPUT GND MODE
digitally programmable transmit and receive gains as well
as input anti-aliasing and complete output smoothing fil- RECV IN TRANS IN
ters. Separate VSS pins for transmit, receive, and digital
sections are provided to minimize crosstalk.
r-Bo B2 --,
RECEIVE FILTER TRANS FilTER
The XR-2120 features guaranteed filter group delay specifi- GAIN SET GAIN SET
cations, within ±1001lS of nominal. The XR-2120C is a L-B, B3.--1
relaxed version of the X R-2120 with group delay specified
within ±15QIlS. The devices are available in a 22 pin (0.4 RECV OUT Vss TRAN OUT vss
inch wide) plastic or ceramic package, and operate over a
wide range of supply voltages.
RECV OUT TRAN OUT

FEATURES lBGND HBGND

On-board Crystal Oscillator With Buffered Output lB Vss HB vss

Internal Anti-al iasing Filters
Complete On-board Output Active Filters
Digitally Programmable Transmit and Receive Gains
MODE Input Internally Switches Filters ORDERING INFORMATION
for Answer/Originate
Single or Split Supply Operation Part Number Package Operating Temperature
Center Frequencies Movable with Input Clock XR-2120CN Ceramic O°C to +70°C
High-I~pedance Inputs (100 kn min) XR-2'120CP Plastic O°C to +70°C
1% Center Frequency Accuracy XR-2120N Ceramic O°C to +70°C
Separate ClK IN and ClK OUT Pins XR-2120P Plastic O°C to
0
+70 C

APPLICATIONS SYSTEM DESCRIPTION

The X R-2120 is comprised of four main signal blocks: The

Bell 212A Transmit/Receive Filtering
digitally programmable gain amplifier, an input anti-aliasing
Answer Back Signal Filtering
switched capacitor filter, switched capacitor bandpass
filters at 1200 Hz and 2400 Hz, and output RC active
filters. These sections serve to: (1) amplify and condition
ABSOLUTE MAXIMUM RATINGS incoming signals, (2) remove noise which can cause aliasing
problems in the bandpass filters, (3) provide very precise
Power Supply 16V bandpass filtering and phase compensation, and (4) perform
Power Dissipation, Plastic 1.0W output reconstruction and filtering, To perform these
Derate Above 25°C 5mWtC necessary filtering and phase compensation functions, a
Power Dissipation, Ceramic 1.3W total of 48 poles are used in the XR-2120.
Derate Above 25°C 7 mWtC
Operating Temperature OOC to 70°C The programmable gain stages provide 4 selectable gains for
Storage Temperature -65°C to 150°C transmit or receive. Separate clock output and input pins
Any I nput Voltage (VOD + 0.5V) to (VSS - 0.5V) are provided for flexibility.

3-55
XR-2120

ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 5 V, VSS = -5 V, XIN = 4.032 MHz (ClK IN = 1.00S MHz). TA = 25°C, unless otherwise specified.
Input gain = 0 dB (Bl/B3 = BO/B2 = 0).

SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS

DIGITAL SECTION

ClK OUT ClK OUT Drive Capability 50 pF

II Digital Input Current -1.0 1.0 p.A dc

Vil Digital Input Voltage VSS VSS+2 V For "0" level

VIH VDD-2 VDD V For" 1" level

ANALOG SECTION

fOl Filter Center 1190 1200 1210 Hz low Band

fOH Frequencies 23S0 2400 2420 Hz High Band

BW 3 dB Bandwidth 900 950 Hz Either Band

Ri I nput Impedance lOOk Ohms

Ci I nput Capacitance 10 pF

fSI Anti-Aliasing Filter

Sampling Frequency 504 kHz

fSB High/low Band

Sampling Frequency 126 kHz

TranIRecv Output 10k Ohms

Drive Capability 50 pF

Output Clock Feedthrough 2 mVrms at 126 kHz

eol00 Output Noise 160 J1,V rms In Passbands (100 Hz BW)

eol000 Output Noise 700 J1,Vrms In Passbands (1 kHz BW)

eirange Dynamic Range of Filters 70 dB Note 1

VO sw Output Voltage Swing 6.0 6.S V pp Note 2

2nd Harm 2nd Harmonic Content -60 dB fiN = 1200 Hz

Referenced to Fundamental

TSW Mode Switching 10 ms

IDD Supply Current 9 27 mA

VSUP Supply Voltage Range ±4.75 ±5 ±7.5 V Dual Supplies

9.5 10 15.0 V VDD Reference to VSS

AV Passband Gain Input Gain = 0 dB

low Band 3.2 4.2 5.2 dB 1200 Hz
-1.4 0 1.4 dB 900 - 1500 Hz (Note 3)
High Band 2.S 3.S 4.S dB 2400 Hz
-1.7 0 1.7 dB 2100 - 2500 Hz (Note 3)
0 1.2 2.2 dB 2500 - 2800 Hz (Note 3)

Note 1 Dynamic range is defined as eirange = 20 Log IVosw/eol.

Note 2 VO sw is the maximum output swing before output clipping occurs.
Note 3 Gain measurements are relative to passband center frequency gain normalized to 0 dB.

3-56
 XR-2120

ELECTRICAL CHARACTERISTICS Continued

FILTER RESPONSE

XR·2120 XR·2120C
SYMBOL PARAMETER UNIT CONDITIONS
MIN TYP MAX MIN TYP MAX

GO Group Delay
Low Band Filter 5060 5160 5260 5010 5160 5310 p.s 900 Hz (See Figure 7)
5100 5200 5300 5050 5200 5350 p.s 1kHz
5160 5260 5360 5110 5260 5410 p.s 1.1 kHz
5200 5300 5400 5150 5300 5450 p.s l.2kHz
5215 5315 5415 5165 5315 5465 p.s 1.3kHz
5255 5355 5455 5205 5355 5505 p.s 1.4kHz
5260 5360 5460 5210 5360 5510 p.s 1.5kHz

High Band Filter 5270 5370 5470 5220 5370 5520 p.s 21kHz (See Figure 8)
5040 5140 5240 4990 5140 5290 p.s 22kHz
5140 5240 5340 5090 5240 5390 p.s 23kHz
5015 5115 5215 4965 5115 5265 p.s 24kHz
5000 5100 5200 4950 5100 5250 p.s 2.5kHz
4920 5020 5120 4870 5020 5170 p.s 26kHz
4800 4900 5000 4750 4900 5050 p.s 2.7kHz

SUBSTRATE ~ VDD

EQUIVALENT
ClK IN i?'21;J----'t--.r--------,
SCHEMATIC
DIAGRAM

RECV 18 TRANS IN
IN

,.....--, ~
RECV B 6 "B TRANS
FILTER FILTER
GAIN GAIN
SET B·
L.....-.....I

lBGND~10~-_.-~ a--+----l'';2j, HB GND

LB Vss ,"-"1J---"'---z

RECV
OUT

RECV TRANS
OUT ~8cJ---41-.a.-"'" --t,o
L . . . - -...... OUT
Vss Vss

3-57
XR-2120

PRINCIPLES OF OPERATION
Figure 1 shows the typical connection for the X R-2120 in smoothing filter; a two-pole RC active filter used to recon-
a spl it supply configuration. In th is mode, Pins 4, 10, and struct the signal from its sampled data form.
13, are simply tied to ground. For single supply operation,
Pins 10 and 13 internally bias to half supply and should be The mode input pin is used to direct the transmit and
externally bypassed with 2.2 /.IF capacitors. Pin 4 does not receive signals to the appropriate filter section. Figure 4
internally dc bias, however, Pin 10 or 13 can provide it with shows mode selection logic convention.
a half supply bias point. In this connection, a 10 kn resis-
tor should be used between Pin 4, and Pin 10 or 13, with The XR-2120 is designed to be operated with a 4.032 MHz
Pin 4 bypassed with a 2.2 /.IF capacitor. crystal between the XIN and XOUT pins. The 4.032 MHz
is divided by four and output on the ClK OUT pin, Pin 22.
Signal flow is illustrated as shown in Figure 2. The transmit For normal operation, the ClK OUT is tied to the ClK IN
or receive signal will follow a path through four internal p in, Pin 21; however, the bandpass center frequencies can
blocks. First it passes through a digitally programmable qain be decreased by providing a divider between these two pins.
stage. The gain, as a function of a 2-Bit digital input, is An external ClK can be used by inputing a 1.008 MHz
shown in Figure 3. Next, the signal passes through a two- clock into the ClK IN pin, or a 4.032 MHz clock into the
pole anti-aliasing low-pass filter at 12 kHz. This is used to XIN pin.
remove noise around the main filter switching frequency of
126 kHz. The anti-aliasing filter is also a sampled-data filter, Figure 5 shows circuitry suitable for translating TTL signals
but is switched at a much higher rate of 504 kHz. It is to the CMOS levels required by all XR-2120 digital inputs.
necessary, therefore, to ensure that wideband noise above The amplitude and group delay characteristics of the
252 kHz is not present at the inputs. In noisy environments XR-2120 are shown in Figures 6 through 8.
a single noise pole RC filter at 30 kHz is usually sufficient
for filtering input noise. The third signal block is the main The XR-2120 may also be used in CCITT V.22 applications
bandpass filtering section at 1200 Hz or 2400 Hz, depend- by adding guard tone notch filters as shown in Figure 9 or
ing on the mode selected. The last section is the output 10. This type of filter, when used with the XR-2120, will
produce at least 60 dB of attenuation to either 550 Hz or
1800 Hz signals.

RECEIVE
OUTPUT

'SINGLE PQINT CONNECTION TO

MINIMIZE CROSSTALK • -6V

Figure 1: Typical Split Supply Connection.

3-58
 XR-2120

HIGH OR LOW OUTPUT

BAND FILTER FILTER
(SCF)

Vi

BO/2

Figure 2: Signal Path

INPUT
B1/ B3 BO / B2 GAIN (dB)

0 0 0

0 1 6

1 a 10 1 = Logic High

1 1 14 0= Logic Low

Figure 3: Gain Programming (Nominal Gain Shown in Fig. 6)

MOOE PIN TRANSMIT RECEIVE TERMINOLOGY

1 Low Band High Band Ori~Jinate

a High Band Low Band Answer

Figure 4: Mode Selection Logic

XR-2120

~
(A) SINGLE SUPPLY (B) SPLIT SUPPLY

Figure 5: TTL Interfacing of Digital Inputs.

3-59
XR-2120

10

,r-----....,,,
I
____ LO BAND
_ _ _ HI BAND
'0
'0
1200 Hz
2400 Hz

10 I
I
,,
,,
I
I
~ 20
z
~ I
l'J 30 I
I
I
I ""..,.--
,
40
I ,."
/
50 /
I
I
60
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
FREOUENCY 1Hz)

NOTE 1 80 - 83 ' LOGIC 0

Figure 6: High and Low Band Amplitude Response.

Figure 7: Low Band Group Delay Characteristics Figure 8: High Band Group Delay Characteristics

3-60
 XR-2120

1.79 KQ 1.79 KQ

Figure 9. V.22 1800 Hz Notch Filter

1.1 KQ 1.1 KQ
•
0.033 IlF 0.033 IlF

Figure 10. V.22 550 Hz Notch Filter

3-61
 XR-2126/7/8/9

Bell 212A/CCITT V.22 Modem Filters

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS
The XR-2126/2127/2128/2129 modem filters are mono-
lithic CMOS switched capacitor filters designed for use in
full duplex 1200 BPS modems. They meet all the filtering
functions of the Bell 212A and CCITT V.22 modem spe-
cifications. They include the low band (centered at 1200
Hz) and high band (centered at 2400 Hz) filters with full
channel compromise equalization and output smoothing
filters for both bands.

For CCITT V.22 applications, a notch filter is included

that can be selected for either 550 Hz or 1800 Hz and
provide greater than 55 d 8 of rejection at these frequencies.
Also included in these devices are two uncommitted op-
erational amplifiers which can be used for input anti-
aliasing filtering or for additional gain, and additional
equalization for Worst Case Line (3002, Co) conditions.

The XR-2126 is pin and function compatible to the AMI

S35212 while the XR-2127 is pin and function compatible
to the AM I S35212A. The X R-2128 is an enchanced
version of the XR-2126 and XR-2127. Like the S35212 and
S35212A, the high band filter in the XR-2126, XR-2127
and XR-2128 can be scaled down by a factor of 6 so it
can be used to monitor Call Progress tones in smart mo-
dems. And, like the S35212A, the XR-2127 and XR-
2128 have analog loop back mode for testing the functions
of the modem.

The XR-2128 contains two additional control pins, CPM

(Pin 12) and NFl (Pin 13). that allow more accurate Call
Progress Monitoring and easier V.22 implementation
without the need for external multiplexers and smoothing
filters. The CPM pin scales the low band filter by a factor
of 2.5 for better centering over the Call Progress frequency
range of 300 to 660 Hz, allowing the unsealed high band
filter to be used for monitoring the modem answer tone. FEATURES
The XR-2129 is an EXAR version of the 212AN.22 Bell 212A/CCITT V.22 Compatible Transmit and Receive
modem filter. All the features of the XR-2126/2127/2128 Filters with Full Channel Compromise Equalization
except the clock frequencies are provided. The XR-2129 Selectable V.22 Notch Filters Included (550 Hz/1800 Hz)
operates from a 1.8432 MHz crystal with an onboard clock Built-in Call Progress Mode/Enhanced Call Progress Mode
oscillator. It also features a 1.8432 MHz buffered clock out- Analog Loop Back Capability
put and 10 d 8 of gain in the receive path. When used with Phone Line Status Monitor Capability (Bypass Mode)
the XR-2121 modulator, XR-2122 demodulator, and XR- Additional Equilization for Worst Case Line
2125 buffer, and a small amount of external circuitry, all (3002, Co) Conditions
the functions needed to realize the 8ell 212A modem are in On-chip Transmit and Receive Output Smoothing Filters
place. Two Uncommitted Operational Amplifiers
APPLICATIONS Choice of Clock Frequencies:
153.6 KHz or 1.2288 MHz/2.4576 MHz on XR-2126,
Bell 212A Modem Filtering XR-2127. XR-2128
CCITT V.22 / V.22bis Modem Filtering 1.8432 MHz Crystal with On-Chip Clock Oscillator
Bell 103 Modem Filtering on XR-2129
Other Modem Filter Applications TTL/CMOS Compatible Digital Inputs

3-62
XR-2126/7/8/9

ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION

Power Supp Iy 12V (±6V) Part Number Package Operating Temperature
Power Dissipation, Plastic 1.0W XR-2126CN Ceramic aOc to 70°C
Derate Above 25°C 5mWtC XR-2126CP Plastic aOc to 70°C
Power Dissipation, Ceramic 1.3W XR-2127CN Ceramic aOc to 70°C
Derate Above 25°C 7 mW/oC XR-2127CP Plastic aOc to 70°C
Operating Temperature OoC to 70°C XR-2128CN Ceramic aOc to 70~C
Storage Temperature -65°C to 150°C XR-2128CP Plastic aOc to 70°C
Any I nput Voltage (VDD +O.5V) to (VSS -O.5V) XR-2129CN Ceramic aOc to 70°C
XR-2129CP Plastic aOc to 70°C
All devices are also available in Surface Mount Packages.
Consult factory for complete information.

BLOCK DIAGRAM (XR-2126/2127/2128)

"oo.'=t>J
T,.",.

T ... ,
•

TRANSMIT E F

TOPlLTIN

Note: eLK 1, ALB, CLK 2 have internal pull-up to VDD Note: SEL 2, SEL 1, MODE, CPM, NFl have internal pull-down to ground
BLOCK DIAGRAM (XR-2129)

.oo'=t>J
T •., -

T,o, •

TAAfIISMIT E ,

"o.'=t>J
R., ..

R.... , •

3-63
 XR-2126/7/8/9

DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 0° C to 70° C, VDD '" +5V ±5%, VSS'" -5V ±5%, un less otherwise specified.

SYMBOL PARAMETER MIN TYP MAX UNIT CONDITIONS

IDD Quiescent Current 15 mA

ISS Quiescent Current 15 mA

VIH High Level Input Voltage,

Digital Signal Pins 2.5 V Note 1

VIL Low Level Input Voltage,

Digital Signal Pins 0.8 V Note 2

VOH High Level Output Voltage 2.6 V

VOL Low Level Output Voltage 0.5 V

AC ELECTRICAL CHARACTERISTICS
Test Conditions: 25°C, VDD = +5V, VSS'" -5V, unless specified otherwise.

SYMBOL PARAMETER MIN TYP MAX UNIT CONDITIONS

Low Band Center Frequency 1190 1200 1210 Hz
High Band Center Frequency 2380 2400 2420 Hz

Adjacent Channel Rejection

Low Band 55 65 dB
High Band 55 75 dB

3 dB Bandwidth 950 Hz

Pass Band Gain at

Center Frequency -.5 +.5 dB 1200 Hz, 2400 Hz

Crosstalk 65 dB

Dynamic Range 70 dB

Total Harmonic Distortion 0.3 %

Output Noise 1 2 mVrms In Passband

Stop Band Rejection

Low Band Filter 30 dB At 500 Hz
25 dB At 1800Hz
75 dB At 2400 Hz
43 dB At 4000 Hz
High Band Filter 55 dB At 500 Hz
95 dB At 1200 Hz
25 dB At 1800 Hz
35 dB At 4000 Hz

NFl = High 65 dB At 550 Hz, NSE L = Low

65 dB At 1800 Hz, NSEL = High

Group Delay
Low Band Filter 5160 ,",sec At 900 Hz
5300 ,",sec At 1200 Hz
5360 ,",sec At 1500Hz
High Band Filter 5370 ,",sec At 2100 Hz
5110 ,",sec At 2400 Hz
4900 ,",sec At 2700 Hz

Output Voltage Swing 8.0 Vp-p

Note 1: Yin > VI H is a logic 1.

Note 2: Yin < VI L is a logic O.

3-64
XR-2126/7/8/9

The following table lists EXAR filters and their pin com- CPM Enhanced Call Progress Mode selection
patible counterparts. on XR-2128 and XR-2129; CPM logic
o for normal operation; CPM logic 1
EXAR Counterpart scales down the low band filter by 2.5
for enhanced Call Progress Monitoring.
XR-2126 AMI S35212 No connection on XR-2126/2127.
13 NC
Reticon RM5632A
XR-2127 AMI S35212A NFl Notch filter insert pin on XR-2128;
Sierra SC11005 logic 0 for notch filter bypass (Bell
XR-2128 Sierra SC11001 212A), logic 1 for inserting 550 Hz/
XR-2129 none 1800 Hz notch (V.22).

•
XTAl IN XR-2129 only. On chip oscillator for
input requiring 1.8432 MHz crystal
connected across XT A L OUT and
PIN DESCRIPTIONS XTAl IN.
Pin Name Desciption/F unction
No connection on XR-2126.
14 NC
SEl2 Call Progress mode selection; SEl 2
ALB Analog loop back on XR-2127 and XR-
logic 0 for normal operation, SE l 2
2128. Same as Pin 90n XR-2129.
logic 1 scales down the high band filter
by 6 for Call Progress Monitoring.
XTAlOUT XR-2129 only. Unbuffered oscillator
output.
2 VSS Negative supply voltage (typically
-5V).
15 TXC OUT Transmit output signal on XR-2126,
XR-2127, XR-2128.
3 RXCIN Receive signal input.

4 ClK 1 Clock input 1 on XR-2126/2127/ ClK OUT 1.8432 MHz buffered clock output on
2128; 2.4576 MHz with SEll logic XR-2129.
1 or 1.2288 MHz with SEll logic 0,
TTL or CMOS compatible. 16 NFO Buffered notch filter output on XR-
2126, XR-2127, XR-2128
NC No connection on XR-2129.
TXC OUT Transmit output signal on XR-2129.
5 R(OUT) Receive uncommitted operational Same as Pin 15 on XR-2126/2127/
amplifier output. 2128.

6 R(-IN) I nverting input of the receive uncom- 17 NSE l Notch filter selection; logic 0 for 550
mitted operation amplifier. Hz, logic 1 for 1800 Hz.

7 R(+IN) Non-inverting input of the receive un- 18 TXC IN Transmit input signal.
committed operational amplifier.
19 T(OUT) Transmit uncommitted operational
8 VOD Positive supply voltage (typically +5V). ampl i fier output.

9 SEll Selects clock frequency into Pin 4 on 20 T(+IN) Non-inverting input of the transmit un-
XR-2126/2127/2128; logic 0 for committed operation amplifier.
1.2288 MHz, logic 1 for 2.4576 MHz.
21 T(-IN) Inverting input of the transmit uncom-
Analog loop back on XR-2129; logic 1 mitted operational amplifier.
for normal operation, logic 0 to inter-
nally loop back TXC OUT to RXC 22 ClK 2 Clock input 2 on XR-2126/2127/2128.
OUT with no signal (MUTE) on TXC 153.6 KHz TT L or CMOS clock.
OUT.
NFl Notch filter insert pin on XR-2129,
10 AGNO Analog ground. same as Pin 13 on XR-2128.

11 MODE Originate/Answer mode selection; 23 DGND Digital ground.

logic 0 for Originate, logic 1 for
Answer. 24 RXC OUT Receive output signal.

12 NC No connection on XR-2126/2127.

3-65
 XR-2126/7/8/9

PRINCIPLES OF OPERATION In the XR-2129, a 10 dB gain is built into the receive filter
path.
Low Band Filter
Transmit and Receive Output Smoothing Filters
The low band filter is a 20th order switched capacitor
filter consisting of a 10th order bandpass filter centered at The transmit and receive output smoothing filters are 2nd
1200 Hz and a 10th order allpass filter centered at 1200 order, active RC, low pass filters that reconstruct the time
Hz. The all pass filter is a delay equalizer that provides sampled output signals characteristic of switched capacitor
compensation for the pass band group delay variation in the fi Iters.
low band filter and half of the compromise line character-
istics. See Figure 1 for the group delay response and Figure V.22 Notch Filter
2 for amplitude response.
The V.22 notch filter is a 4th order switched capacitor
In the Originate mode, the low band is used in the transmit notch filter cascaded with the low band filter. The notch
path and in the Answer mode, it is used in the receive path. frequency of the filter is at 550 Hz when NSEL (Pin 17) is
When analog loop back is used in the Originate mode, the logic 0 and is shifted to 1800 Hz when NSEL is logic 1. In
low band filter will be in the test loop. In Call Progress the XR-2128 and XR-2129, the notch filter is bypassed in
Monitoring mode with SE L 2 (Pin 1) at logic 1, and CPM the low band filter if NFl pin is logic O. On the XR-2126/
(Pin 12) at logic 0, the center frequency of the filter will be 2127/ 2128, the notch filter output will always be available
shifted down by a factor of 6 to 250 Hz. If CPM (Pin 12) is at Pin 16 (NFO). On the XR-2129, the NFO pin is not
logic 1, then the center frequency will be scaled down by available; the notch filter will appear on Pin 24 (RXC OUT)
2.5 to 480 Hz. This allows the precision dial tone of 350 if (NFl) is logic 1.
Hz/440 Hz to pass, as well as audible ringing at 440 Hz/480
Hz and the busy tone and the precision reorder tone of Worst Case Line Equalizer
480 Hz/620 Hz.
The worst case line equalizer is an optional fixed compro-
High Band Filter mise (amplitude and delay) equalizer designed for worst
case line conditions (3002, Co) in the high band receive
The high band filter is a 20th order switched capacitor mode. The equalizer is inserted in the high band receive
filter consisting of a 10th order bandpass filter and a 10th path in operating modes 14 and 16 (see Table I).
order allpass filter centered at 2400 Hz. The allpass filter is
a delay equal izer that provides compensation for the Uncommitted Operational Amplifiers
pass band group delay variation in the high band fi Iter
and half of the compromise line characteristics. See Figure Two uncommitted operational amplifiers are provided on
3 for the group delay response of the high band filter and all four versions of the modem filters. These are the trans-
Figure 2 for amplitude response. mit and receive amplifiers. They can be used as input
anti-aliasing filters or as gain stages.
In the Answer mode, the highband filter is used in the
transmit path. In the Originate mode, it is used in the re- Analog Loop Back Test
ceive path.
When ALB (Pin 14) on XR-2127, XR-2128 and (Pin 9) on
When analog loop back is used in the Answer mode, the XR-2129 is logic 0, the modem transmit signal, TXC OUT
high band filter will be in the test loop. In Call Progress (internally) is looped back to the modem through the RXC
Monitoring mode with SEL 2 (Pin 1) at logic 1 and CPM OUT pin with no signal present (MUTE) on TXC OUT (out-
(Pin 12) at logic 0, the center frequency will be scaled put pin). If the low band filter is to be tested, the MODE
down by a factor of 6 to 400 Hz. If Pin 1 is at logic 0 or Pin pin should be logic 0 and logic 1 if the highband filter is to
12 is at logic 1 this filter operates in the normal data mode. be tested. The receive output smoothing filter will always
be in the test loop regardless of the MODE level.

Figure 1. Low Band Group Delay Characteristics

Figure 2. Low and High Band Amplitude Response
3-66
XR-2126/7/8/9

Figure 3. High Band Group Delay Characteristics

Figure 4A. XR-2129 with 500 Hz Notch Figure 4B. XR-2129 with 1800 Hz Notch

Figure SA. XR-2126/2127/2128 with 500 Hz Notch Figure 5B. XR-2126/2127/2128 with 1800 Hz Notch
3-67
 XR-2126/7/8/9

Originate/Answer Mode Selection RXC OUT will be connected to RXC IN. This feature can
be used to monitor the status of the phone line. The out-
When MODE (Pin 11) is logic 0, the modem filter operates put smoothing filters will always be in the TXC OUT and
I

in the Originate mode, transmitting in the low band and RXC OUT paths.
receiving in the high band. If MODE is logic 1, the modem
fi Ite( operates in the answer mode; transm itting in the high Clock Selection (Note 1)
band and receiving in the low band.
On the XR-2126/2127/2128, SEll (Pin 9) is used to select
Transmit Squelch in Call Progess Mode the internal clock divider (+8/+16) depending on the exter-
nal clock frequency. SE l 1 is set at logic a for a 1.2288
If CPM (Pin 12) is logic 1, the input of the transmit MHz input clock and at logic 1 for a 2.4576 MHz clock on
smoothing filter will be disconnected and shorted to ClK 1 (Pin 4). A 153.6 KHz clock input is provided on
ground, muting the transmitter. I n the handshake sequence ClK 2 (Pin 22). If used, ClK 1 (Pin 4) and SEll (Pin 9)
of the 8ell 212A modem, this feature can be used to should be left open.
eliminate the transmit signal output.
On the XR-2129, neither of these clock options are avail-
Phone Line Status Monitor able. Instead, the device operates from an on chip clock
oscillator which requires an external 1.8432 MHz crystal.
If the logic levels on the control pins are shown in opera- Also available on the XR-2129, is a buffered 1.8432 MHz
tion 15 (Table 1), the low band and high band filters will clock output on Pin 15.
be bypassed; TXC OUT will be connected to TXC IN and

TABLE I OPERATING MODES

OPERATION CPM SEL 2 ALB MODE NFl NSEL TXCIN TXC OUT RXCIN RXC OUT

0 a a a a x l l H H
1 a a 1 a x H H l l
2 a a a a a x l MUTE L
3 a a a a x H MUTE H
4 a 1 a x x L/6 L/6 H/6 H/6
5 a x x H/6 H/6 L/6 L/6
6 a a a x x L/6 L/6 H/6 l/6
7 a a 1 x X H/6 H/6 L/6 H/6
8 a a x x MUTE H H
9 X 1 X X MUTE L/2.5 L/2.5
10 X a a x x MUTE L/2.5 L/2.5
11 1 a a x x H MUTE H
12 a a 1 a H H L L+ 550 Hz Notch
13 a 0 1 H H L L+ 1800 Hz Notch
14 a a a 0 L L H H+WCLEO
15 0 0 0 TXCIN RXC IN
16 0 a 0 1 X H MUTE H+WCLEO
17 0 0 0 0 0 L MUTE L+ 550 Hz Notch
18 0 a a a L MUTE L+ 1800 Hz Notch

Note: MUTE means no signal present on transmitter output.

l refers to low band filter with center frequency of 1200 Hz.
H refers to high band filter with center frequency of 2400 Hz.
- means no filter connection.
+ means connection to both filters.
X means "don't care" condition.
N refers to Notch
Mode 15 is filter bypass mode where low band and high band filters are bypassed to monitor status of phone line.
WCL EO is the Worst Case Line equalizer.
3-68
XR-2126/7/8/9

1JlF 10KO
SEL 2 RXOUT t - - - - t ~ TO ANI &
CD IN OF
XR-2122
-5V Vss DGND
R3
RXCIN T(-IN) FROM
Txc OUT OF
XR-2121
R(OUT) T(+IN)

R1

R2
R(-IN)

R(+IN)

VDD
T(OUT)

TXCIN

NSEL
•
AGND TXCOUT TIP

MODE
PHONE
LINE

RECEIVED CARRIER

RING

Figure 6. XR-2126/2127/2128/2129 Typical Connection

Normal Call Progress/Enhanced Call Progress functions by their mnemonic. The receive amplifier gain
is set by R1
When SEL 2 (Pin 1) and CPM (Pin 12) are logic 0, the R2
modem filter operates in the normal modem data mode. If
either pin is logic 1, the modem filter operates in the Call and transmit amplifier gain is
Progress Monitoring mode. If SEL 2 is logic 1, and CPM is
logic 0, the low band and high band filters will be scaled
down by a factor of 6. If CPM is logic 1, the low band filter SEL 2
will be scaled down by a factor of 2.5 and, depending on
the mode on MODE (Pin 11) and ALB (Pin 14), RXC OUT SEl2 (pin 1) allows the sampling clock of the high band
will either be the output of the scaled low band filter filter to be divided down by 6. This reduction of the samp-
(L/2.5) or the unscaled high band filter. ling frequency provides filtering for the Call Progress Moni-
toring tones. SE l 2 is taken to a logic 1 for Call Progress
Note 1: When using ClK1, ClK2 may be left open, tied to Monitoring, and is returned to a logic 0 for normal high
logic 1, or tied to logic O. When using ClK2, ClK1 may be band filtering. When used in conjunction with the XR-2122
floated, tied to logic 1, or tied to logic O. Bell 212A Type Demodulator, Call Progress Tones can be
detected by the Energy Carrier Dectect pin of the XR-2122
TYPICAL APPLICATIONS (pin 17, CD OUT) and the tone identified by its cadence or
interruption rate. This is the method used by most Call Pro-
XR-2126/2127/2128/2129 gress Decoder ICs. It is assumed that a processor will moni-
tOI' the Energy Carrier Detect pin of the XR-2122 and
The XR-2126 through XR-2129 have a number of common a look-up table will be available to match cadence with
functions. Figure 6 shows typical connection of these tone.
3-69
 XR-2126/7/8/9

DESCRIPTIONS OF INPUTS AND OUTPUTS TXCIN

VSS TXC IN (p in 18) is the fi Iter input for the transm itted
signal.
VSS (pin 2) is the negative supply line to the IC. In most
modem applications this will be -5 V. This signal may be taken directly from TXC OUT (pin 4)
of the XR-2121 Bell 212A Type Modulator.
RXCIN
T(OUT), T(+ IN), T(-IN)
RXC IN (pin 3) is the filter input for the received signal.
This signal may be taken directly from the secondary side T(OUT) (pin 19), T(+ IN) (pin 20). and T(- IN) (pin 21)
of the DAA isolation transformer, or may pass through a are respectively the output, non-inverting input, and
gain/ anti-aliasing stage. inverting input of an additional onboard op amp. Figure 6
shows this op amp with gain setting resistors R3 and R4.
ROUT, R(-IN), R (+IN) This op amp may also be used in an anti-aliasing filter.
This cut off frequency is chosen to be approximately 'Y.! of
ROUT (pin 5), R(-IN) (pin 6), and R(+ IN) (pin 7) are re- the sampling frequency.
spectively the output, inverting input, and non-inverting
input of an additional onboard op amp. Figure 6 shows OGND
this op amp with gain setting resistors R 1 and R2. This
amplifier may also be used in an anti-aliasing filter. The cut DGND (pin 23) is the digital ground line of the IC. ft
off frequency is chosen to be approximately 'Y.! of the should be connected, single point, to all other digital cir-
sampling frequency. cuitry in a system design.

VOO RXC OUT

VDD (pin 8) is the positive supply line to the IC. In most RXC OUT (pin 24) provides the smoothed received signal
modem applications, this will be 5 V DC. output. This is typically taken through a lpF capacitor to
the AGC circuit and ;CD IN of the XR-2122 Bell 212A
AGNO Demodu lator.

AGND (pin 10) is the analog ground line of the IC. It

should be connected to all other analog circuitry in a sys- XR-2126
tem design.
The XR-2126 has four features in addition to those com-
MODE mon to the other members of this filter family. They
are ClK 1, SE l 1, NFO, and ClK 2.
MODE (pin 11) sets the mode of operation for the filters.
The filters consist of a high band filter with a center fre- ClK 1
quency at 2400 Hz and a low band filter with a center
frequency at 1200 Hz. MODE is used to place the proper ClK 1 (pin 4) is one of two clock inputs for the XR-2126.
filter (2400 Hz or 1200 Hz center frequency) in the proper Either clock input may be used (ClK 1 or ClK 2). ClK 1
signal path (transmit or receive). Answer mode (MODE will accept either a 2.4576 MHz input or a 1.2288 MHz in·
10'Jic 1), places the low band filter in the receive path and put, depending on the state (logic 1 or logic 0 respectively)
the hirjh band filter is the transmit path. Originate mode of SEl 1.
(MODE logic 0) places the high band filter in the receive
path and the low band filter in the transmit path. SEl1

TXC OUT SEl 1 (pin 9) selects either the 2.4576 MHz clock or the
1.2288 MHz clock for input on pin 4, C lK 1.
TXC OUT (pin 15 for XR-2126/2127/2128 and pin 16for
XR-2129) provides the smoothed transmit signal output. NFO
This is typically taken through a 1 pF capacitor and into
the secondary of an isolation transformer which repre- NFO (pin 16)' is the notch filter output.
sents a 1200 n load.
ClK 2
NSEL
ClK 2 (pin 22) takes a 153.6 KHz TTL or CMOS clock
NSE l (pin 17) is used to select one of two notch filters input.
which are available for CCITT Y.22 mode filtering. A logic
o on NSEl selects the 550 Hz filter while a logic 1 on
NSE l selects the 1800 Hz filter. Both notch filters are in
the low band path and are used to attenuate the feed-
through of the transmitted guard tone through the trans-
former and into the Answer modem's received carrier input
to a level much lower than the received carrier. (See Fig-
ures 4 and 5.)
3-70
XR-2126/7/8/9

XR·2127
The XR·2127 has five functions in addition to those ALB (pin 14) selects the Analog loop Back mode when
common to the other members of this filter family. They logic O. A high on ALB allows normal operation.
are ClK 1, SEl 1, ALB, NFO, and ClK 2.
NFO
ClK 1
N Fa (p in 16) is the notch fi Iter output.
ClK 1 (pin 4) is one of two clock inputs for the XR-2127.
Either clock input may be used (ClK 1 or ClK 2). ClK 1 ClK 2
will accept either a 2.4576 MHz input or a 1.2288 MHz in·
put, depending on the state (logic 1 or logic 0 respectively) ClK 2 (pin 22) takes a 153.6 KHz TTL or CMOS clock.
of SEl 1.
XR·2129
SEl1
The X R-2129 is designed specifically for use with the X R·
SEl 1 (pin 9) selects either-the 2.4576 MHz clock or the 212AS chip set (XR-2125, XR-2121, and XR-2122 ex-
1.2288 MHz clock for input on pin 4, C lK 1. cluding the XR-2120). This part requires no division of the
1.8432 MHz clock oscillator frequency. A 1.8432 MHz
ALB crystal is connected between XTAl IN and XTAl OUT
(pins 13 and 14 respectively). ;Figure 7 shows the XR-
ALB (pin 14) selects the Analog loop Back mode when 212AS chip set using the XR-2129 in place of the XR·
logic O. A logic 1 on ALB allows normal operation. 2120 to complete the Bell 212A Modem Signal Processor.

NFO The XR-2129 has six functions in addition to those com-

mon to the other members of this filter family. They are
NFO (pin 16) is the notch filter output. ALB, CPM, XTAl IN, XTAl OUT, ClK OUT, NFl.

ClK 2 ALB
ClK 2 (pin 22) takes a 153.6 KHz TTL or CMOS clock ALB (pin 9) selects the Analog loop Back mode when logic
input. O. A logic 1 on ALB allows normal operation.

CPM
XR·2128
CPM (pin 12) is used to select either normal low band
The X R-2128 has seven functions in add ition to those operation (fo = 1200 Hz) or low band divided by 2.5
common to the other members of this filter family. They (fo = 480 Hz). logic is TTL with a logic 0 for normal low
are ClK 1, SEl 1, CPM, NFl, ALB, NFO, ClK 2. band operation and a logic 1 for low band divided by 2.5
for Call Progress Monitoring.
ClK 1
XTAl IN, XTAl OUT
ClK 1 (pin 4) is one of two clock inputs for the XR-2128.
Either clock input may be used (ClK 1 or ClK 2) ClK 1 XTAl IN (pin 13) and XTAl OUT (pin 14) are the oscil-
will accpet either a 2.4576 MHz input or a 1.2288 MHz lator nodes across which a 1.8432 MHz crystal must be con·
input, depending on the state (high or low respectively) nected for operation. This 1.8432 MHz crystal is the same
of SEl 1. frequency crystal required for operation of the XR-2121,
XR-2122, and XR-2125. The buffered output from this
SEl1 onboard oscillator is available from ClK OUT (pin 15).
XTAl OUT (pin 14) offers the unbuffered oscillator
SEl 1 (pin 9) selects either the 2.4576 MHz clock or the output.
1.2288 MHz clock for input on pin 4, ClK 1.
ClK OUT
CPM
ClK OUT (pin 15) provides the buffered output from the
CPM (pin 12) selects normal low band filter operation onboard oscillator. It can be used to drive other circuitry
and divides by 2.5 for Call Progress Monitoring use. logic is requiring a 1.8432 MHz clock.
TTL with a logic 0 for normal low band operation and a
logic 1 for low band divided by 2.5 for enhanced Call
Progress Monitoring. NFl
NFl NFl (pin 22) selects the low band filter path. With NFl
logic 1, the notch fi Iter (550 Hz or 1800 Hz) selected by
NFl (pin 13) selects the low band filter path. With NFl NSEl (pin 17), is inserted in the low band filter signal path.
logic 1, the notch filter (550 Hz or 1800 Hz) selected by With NFl logic 0, the notch filters are bypassed by the
NSEl (pin 17) is inserted in the low band filter signal path. signal.
With NFl logic 0, the signal bypasses the notch fi Iters.
3-71
 .J

.,
Voo C7 ·5

c,

c.>
.!.J
I\) .,

><
II
Al 150K Ag lK 'TXC Amplifier Adjust
A2
A3
50K
10K'
AlO
All
1M
5llK
"TXC Magnitude Adjust
I
A4 10K' A12 lK Cl lliF C4 1 IIF
N
A5
A6
A7
Aa
600
300
600
200K
Al3
A14
A15
A16
lOOK
10K
390K
20K"
C2
C3

Tl
O.OII1F
.000011F

Microtran T2220
C5
C6
C7
1 IIF
O.4711F
lliF
(cannot handle PC line currentl
.....
Ql 2N4961 N
ICI
IC2
XA·1489
XA·I488
Aesistors· 10%
Capacitors - 20%
en
IC3 CD-4069
""-
Figure 7. XR-212AS Bell 212A Modem Utilizing the XR-2129 Modem Filter ~
""-
0)
""-
CO
 Section 3 - Data Communication Circuits
Line Interface Circuits . . . . . . . . . . . . . .......... . 3-73
XR-1488/1489 Quad Line Driver/Receiver . . . . . . . . . . . . . . . . . 3-74

3-73
 XR-1488/1489A

Quad Line Driver/Receiver

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS
The XR-1488 is a monolithic quad line driver designed
to interface data terminal equipment with data commu-
nications equipment in conformance with the specifica-
tions of EIA Standard No. RS232C. This extremely ver-
satile integrated circuit can be used to perform a wide
range of applications. Features such as output current
limiting, independent positive and negative power sup-
ply driving elements, and compatibility with all DTL and
TIL logic families greatly enhance the versatility of the
circuit.

The XR-1489A is a monolithic quad line receiver de-

signed to interface data terminal equipment with data
communications equipment. the XR-1489A quad re-
ceiver along with its companion circuit, the XR-1488
quad driver, provide a complete interface system be-
tween DTL or TIL logic levels and the RS232C defined
voltage and impedance levels.

ABSOLUTE MAXIMUM RATINGS

Power Supply
XR-1488 ± 15 Vdc
XR-1489A + 10 Vdc
Power Dissipation
Ceramic Package 1000 mW
Derate above + 25°C 6.7 mW/oC
Plastic Package 650 mW/oC
Derate above + 25°C 5 mW/oC SYSTEM DESCRIPTION
The XR-1488 and XR-1489A are a matched set of quad
line drivers and line receivers designed for interfacing
between TIL/DTL and RS232C data communication
lines.

The XR-1488 contains four independent split supply line

drivers, each with a ± 10 mA current limited output. For
RS232C applications, the slew rate can be reduced to
ORDERING INFORMATION the 30 V/p.S limit by shunting the output to ground with a
410 pF capacitor. The XR-1489A contains four indepen-
Part Number Package Operating Temperature
dent line receivers, designed for interfacing RS232C to
XR-1488N Ceramic O°C to + 70°C TIL/OTL. Each receiver features independently pro-
XR-1488P Plastic O°C to + 70°C grammable switching thresholds with hysteresis, and
XR-1489AN Ceramic O°C to + 70°C input protection to ± 30 V. The output can typically
XR-1489AP Plastic O°C to + 70°C source 3 mA and sink 20 mA.

3-74
XR·1488/1489A
ELECTRICAL CHARACTERISTICS
Test Conditions: (V + = + 9.0 ± 1 % Vdc, V - = - 9.0 ± 1 % Vdc, TA = O°C to + 70°C, unless otherwise noted)

XR-1488 LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Forward Input Current 1.0 1.6 mA Yin = 0 Vdc
Reverse Input Current 10 p,A Yin = + 5.0 Vdc
Output Voltage High Vdc Yin = 0.8 Vdc,
RL = 3.0 kO
V+ = +9.0 Vdc, V- = -9.0 Vdc +6.0 +7.0
V+ = + 13.2 Vdc, V- = -13.2 Vdc +9.0 + 10.5
Output Voltage Low Vdc Yin = 1.9 Vdc,
RL = 3.0 kO
V+ = +9.0 Vdc, V- = -9.0 Vdc -6.0 -7.0
V+ = + 13.2 Vdc, V- = -13.2 Vdc -9.0 -10.5
Positive Output Short-Circuit Current +6.0 +10 +12 mA
Negative Output Short-Circuit Current -6.0 -10 -12 mA
Output Resistance V + = V- = 0 300 Ohms IVol = ±2.0 V
Positive Supply Current (RI = 00) mA
Yin = 1.9 Vdc, V+ = +9.0 Vdc +15 +20
Yin = 0.8 Vdc, V + = +9.0 Vdc +4.5 +6.0
Yin = 1.9 Vdc, V+ = + 12 Vdc +19 +25
Yin = 0.8 Vdc, V + = + 12 Vdc +5.5 +7.0
Yin = 1.9 Vdc, V+ = + 15 Vdc +34
Yin = 0.8 Vdc, V + = + 15 Vdc +12
Negative Supply Current (RL = 00) mA
Yin = 1.9 Vdc, V- = -9.0 Vdc -13 -17
Yin = 0.8 Vdc, V- = -9.0 Vdc 0 0
Yin = 1.9 Vdc, V- = -12 Vdc -18 -23
Yin = 0.8 Vdc, V- = -12 Vdc 0 0
Yin = 1.9 Vdc, V- = -15 Vdc -34
Yin = 0.8 Vdc, V- = -15 Vdc -2.5
Power Dissipation mW
V+ = 9.0 Vdc, V- = -9.0 Vdc 333
V+ = 12 Vdc, V- = 12 Vdc 576
Switching Characteristics (V + = + 9.0 ± 1 % Vdc, V- = - 9.0 ± 1 % Vdc, TA = +25°C)
Propagation Delay time (tpd +) 150 200 ns ZL = 3.0k and 15 pF
Fall Time 45 75 ns ZL = 3.0k and 15 pF
Propagation Delay Time (tpd -) 65 120 ns ZL = 3.0k and 15 pF
Rise Time 55 100 ns ZL = 3.0k and 15 pF

3-75
 ELECTRICAL CHARACTERISTICS
XR·1488/1489A
Test Conditions: Response control pin is open. (V + +5.0 Vdc ± 1 %, TA = O°C to + 75°C,
unless otherwise noted)
XR-1489 LIMITS

PARAMETERS MIN TYP MAX UNITS CONDITIONS

Positive Input Current mA
Yin = +25 Vdc 3.6 8.3
Yin = + 3.0 Vdc 0.43
Negative Input Current mA
Yin = -25 Vdc -3.6 -
8.3
Yin =- 3.0 Vdc -0.43
Input Turn-On Threshold Voltage Vdc
TA = +25°C, VOL :50.45 V 1.75 1.95 2.25
Input Turn-Off Threshold Voltage Vdc IL = -0.5 mA
TA = +25°C, VOH ~2.5 V 0.75 0.8 1.25
Output Voltage High Vdc IL = -0.5 mA
Yin = 0.75 V 2.6 4.0 5.0
Input Open Circuit 2.6 4.0 5.0
Output Voltage Low 0.2 0.45 Vdc Yin = 3.0 V,
IL = 10 rnA
Output Short-Circuit Current 3.0 mA
Power Supply Current 20 26 mA Yin = +5.0 Vdc
Power Dissipation 100 130 mW Yin = +5.0 Vdc
Switching Characteristics (V + = 5.0 Vdc ± 1 %, TA = + 25°C)
Propagation Delay Time (tPLH) 25 85 ns RL = 3.9 kO
Rise Time 120 175 ns RL = 3.9 kO
Propagation Delay Time (tpHL) 25 50 ns RL = 390 kO
Fall Time 10 20 ns RL = 390 kO

EQUIVALENT SCHEMATIC DIAGRAMS

XR·1488 XR-1489A

v' " O - - -_ _ ------.---t--K..-.-......-y,,f'o,---Q ,.....---.----t"'--o " v'

OUTPUT

3 OUTPUT

INPUTS

GND 'f

3-76
Cross References & Ordering Information

Telecommunication Circuits

Data Communication Circuits

Industrial Circuits

Instrumentation Circuits

Interface Circuits

Special Function Circuits

User Specific Linear ICs

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

4
 Section 4 - Computer Peripheral Circuits
XR-117 Hard Disk ReadlWrite Amplifier . . . . . . 4-2
XR-2247/2247A Floppy Disk Write Amplifier . 4-6
XR-3448 Floppy Disk ReadlWrite Amplififer 4-13
XR-3470Al3470B Floppy Disk Read Amplifier . . 4-21
XR-3471 Floppy Disk Write Amplifier . . . . .. . . . . 4-28

4-1
 XR-117
PRELIMINARY INFORMATION

Hard Disk Read/Write

GENERAL DESCRIPTION FUNCTIONAL 81.0CK DIAGRAM

The XR-117 is a high speeq head interface integrated circuit

for hard disk drives, performing both read and write func-
tions. The XR-117 is compatible with 3%" to 14" single
and multiple platter drives, and features high bandwidth,
large dynamic range, and low noise. Several packaging op-
tions extend usefulness to applications requiring two, four,
or six center-tapped read/write heads; multiple devices are
easily cascaded for drives with more heads.

The XR-117, manufactured with a high speed bipolar pro-

cess, operates on +5 V and +12 V.

FEATURES

Complete Head Interfacing Functions, Read and Write

High Bandwidth and Dynamic Range
Low Noise
Available in Two, Four, and Six Head Versions
Easily Cascaded for Larger Systems
Power Monitor with Automatic Disable
TTL Compatible Inputs

APPLICATIONS

Single or Multiple Platter Hard Disk Drives

ABSOLUTE MAXIMUM RATINGS

SYSTEM DESCRIPTION
VDD1 and VDD2 15V
VCC 6V
Digital Inputs Four major blocks comprise the XR-117: a multiplexer for
-0.3 V to Vee +0.3 V
head selection, write data 'control circuitry, read signal amp-
Write Current 60mA
lifiers and buffers, and a power supply monitor that dis-
Junction Temperature 150°C
o ables the device whenever improper supply voltages are pre-
Storage Temperature -65°C to +150 C
sent. Designed for six read/write heads, the XR-117 is also
available in smaller packages for systems requiring only two
or four heads. The 30 MHz minimum bandwidth facilitates
ORDERING INFORMATION data rates exceeding 25 Mbits per second.

Part Number Package Operating Temperature Less than 2 nV/.,fHZ (nominal) noise allows error free
XR-117 -2CP Plastic oOe to 70°C operation with small input signals. Up to 50 mA of write
XR-117-4CP Plastic O°C to 70°C current output means the disk signal can be large, further
XR-117-6CP Plastic oOe to 70°C enhancing the readback signal-to-noise ratio for very low
0
XR-117-xCN Ceramic OoC to 70 e error rates.
XR-117-xCQ'Surface Mount Quad oOe to 70°C
0
XR-117-xMD* Surface Mount OoC to 70 e Cascading multiple XR-117s is accomplished by alternately
XR-117-x PLCC OoC to 70°C enabling and disabling devices via the chip select (eS) pin.
x = 2, 4. or 6, depending on number of heads required Guaranteed write current tolerances allow close write
* = contact factory for availability matching between devices.

4-2
XR-117

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VDD = 12 V, VCC = 5 V, RW = 3.1 kn, Lh = 10 JlH, Rd = 750 n, CL (RD+, RD-l. <
20 pF, Data Rate = 5 MHz.

SYMBOL PARAMETER MIN TYP MAX UNIT CONDITIONS

DC CHARACTERISTICS

ICC Supply Current 25 mA VCC = 5.5 V, Read or Idle Mode

30 mA VCC = 5.5 V, Write Mode

100 Supply Current 25 mA VDD = 13.2 V, Idle Mode

50 mA VDD = 13.2 V, Read Mode
30 mA VDD = 13.2 V, Write Mode,
IW = 0 mA

Po Power Dissipation 400 mW VCC - 5.5 V, VDD = 13.2 V,

Idle Mode
600
700

1050
mW
mW

mW
Read Mode
Write Mode, IW = 50 mA,
RCT = 130 n
Write Mode, IW = 50 mA,
II
RCT = 0 n

VCT Center Tap Voltage 4.0 V

6.0 V

WUS Write Unsafe Output

VOL Saturation Voltage 0.1 0.5 V IOL = 8 mA
IOH Leakage Current 100 p.A VOH = 5 V

DIGITAL INPUTS

VIL Input "Low" Voltage 0.8 V

VIH Input "High" Voltage 2.0 V

IlL Input Current, Low 1-0.4 mA

IIH Input Current, High 100 JlA

WRITE CHARACTERISTICS

Write Current Accuracy -5 +5 % Note 1

IW Recommended Write
Current Range 10 45 50 mA

Differential Head
Voltage Swing 5.7 10 Vpeak

Unselected Differential
Head Current 2 mApeak

Differential Output CapacitancE 15 pF

Differential Output Resistance 10 kn

WD Rate
(Transisition Frequency) 125 500 625 kHz

KI Current Source Factor 20 KI = Iwl/Current through RW)

4-3
 XR-117

READ CHARACTERISTICS

AV Differential Voltage Gain 80 100 120 V!V Vin = 1 mVp-p @ 300 kHz
RL+= RL-= 1 kn

Rin Differential Input Resistance 2 kn

Cin Differential Input Capacitance 23 pF f = 5 MHz

eni I nput Noise Voltage 1.5 2.1 nV/$z Lh = 0, Rh = 0, BW = 15 MHz

BW Bandwidth 30 55 MHz -3dB point IZsl< 5n, Vin =

1 mVp-p

IB Input Bias Current 45 J.LA

CMRF Common Mode Rejection Ratic 50 dB VCM = VCT + 100 mVp-p at
5 MHz

PSRR Power Supply Rejection Ratio 45 dB 100 mVp-p at 5 MHz

Superimposed on VDD1,
VDD2, or VCC

Channel Separation 45 dB Unselected Channel: Vin =

100 mVp-p at 5 MHz
Selected Channel: Vin = 0 V

Output Offset Voltage -480 ± 50 480 mV

VCM Common Mode

Output Voltage 5 6 7 V

SWITCHING CHARACTERISTICS

R/W Read to Write 0.1 1 jJS Note 2

Write to Read 0.1 1 jJS Note 3, Note 4

CS Start-Up Delay 0.1 1 jJS Delay to 90% of IW or to 90%

CS of 100 mV 10 MHz read signal
envelope.

Inhibit Delay 0.1 1 jJS Note 4

Head Switching Delay 0.1 1 jJS Note 3

Switching between any heads.

WUS Write Unsafe

Safe to Unsafe 1.6 2.5 8.0 jJS IW= 50 mA, See Fig. 1, TDl
Unsafe to Safe 0.2 1 jJS IW= 20 mA, See Fig. 2, TD2

IW Head Current
Propagation Delay 4 25 nS Lh = 0 JJH, Rh = 0 n, Note 5,
Asymmetry 2 nS Note 6 See Fig. 1, TD3
Rise or Fall Time 9 20 nS 10% to 90% or 90% to 10%
points

140 V
Note 1: Error from IW = ""RW(-n;-)
Note 2: Delay to 90% of IW
Note 3: Delay to 90% of 100 mVp-p 10 MHz read single envelope
Note 4: Delay to 90% decay of IW
Note 5: From 50% points
Note 6: Input WD has 50% duty cycle and 1 nS rise and fall times.
4-4
XR-117

Write Mode Design Considerations

Write current, IW, typically between 20 mA and 50 mA.

is determined by a single resistor, RIW.
140,000
RI W = - - -
IW

where IW is in mA and R IW is in ohms.

Figure 1. Write Mode Timing Diagram The VCC supply monitor disables writing when VCC drops
below about 4 V.

Device power dissipation is reduced by a resistor, RCT,

connecting VDD2 to the +12 V supply. Some of the center
tap driver voltage drop then is across the resistor.

•
With the nominal 12 V supply, RCT, is calculated as
55
CAUTION: This device may be damaged by electrostatic RCT = 130 (iw)
discharge. ESD precautions should be taken.
where RCT is in ohms and IW is in milliamperes.
PRINCIPLES OF OPERATION
Internal dissipation reduction is primarily a consideration
Write Mode with high write current levels and small outline packages.
For low write currents, RCT may be deleted, with VDD2
Before writing may begin, both chip select (CS) and Read/ directly connected to the supply.
Write (R/W) must be pulled low. The desired head, selected
In addition to the individual head damping resistors, a
by HSO to HS2, is driven by a differential current sink of
ferrite bead around the VCT line to the heads will further
magnitude IW set by R IW. I nput data is applied to a faIl-
ing edge triggered toggle flip-flop, which in turn selects the reduce overshoot and ringing in extreme conditions.
active side of the center tapped write head.
Write unsafe (WUS) pulls high whenever one or more of six
Current is sourced through the center tap driver, VCT, write error conditions exist. Four conditions; open head,
which is "high" in the write mode. Write unsafe (WUS) open center tap, no write current and write data transition
signals the disk controller whenever one of six error condi- rate too low, are detected with a differential capacitor
tions exist and writing should be discontinued. The si~ charge/discharge circuit. Device unselected and read mode
faults are: open head, open center tap, no write current, digital conditons also force WUS high.
write data frequency too low, device unselected, and
writing aHempted while the device is in the read mode. After removal of the fault condition, two negative write
data transitions are requjred to clear WUS. This output is
Read Mode for indication only, intended for signaling a controller,
and does not directly impede device operation. A pull-up
Pulling R/W high enables the data read back mode. A low resistor of about 2 kn is necessary for operation of this
noise, high gain differential amplifier increases the weak open collector output.
signal amplitude and provides low output impedance.
Read Mode Design Considerations
APPLICATIONS INFORMATION
The read amp has a fully differential input and output and
As will all high frequency, high gain systems, layout is provides approximately 100 V!V gain. Its 30 MHz mini-
critical. Lead lengths should be minimized and supplies mum bandwidth and low noise characteristics (1.5nV /
should be well bypassed. The XR-117 is available in small v'Hz typical) provide substantial margins in most drives.
outline surface mount and flat-pak packages facilitating The ouput should be AC coupled to delete the approxi-
installation near the drive heads. Its high frequency charac- mately 6 V output common mode voltage. Best results are
teristics lead to a certain degree of electrostatic discharge obtained by limiting load capacitance to 20 pF and load
(ESD) susceptabi lity, so static reducing precautions shou Id current to 100 pA.
be taken.

4-5
 XR·2247/2247A

Floppy Disk Write Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2247/2247A is a write amplifier designed to pro-
vide the complete interface between write data signals Vee

and tunnel-erase magnetic heads. Although primarily

eTa
intended for floppy disk drive systems, the XR-22471
2247A can also be used in other magnetic media sys-
tems such as tape drives. To minimize external part r--_----4 20 ~
HEAD 1
count for dual head systems, complete head switching
is does internally with emitter-coupled PNP transistors ~
in the XR-2247 and diodes (which offer improved broad-
band noise characteristics) in the XR-2247A. Write and ~
~OUT
erase currents are each externally programmable with
a single resistor. Also included is circuitry for inner
track write current compensation. To prevent false TOOFF
~
write current outputs during power-on, an inhibit input HEADO

has been provided. Erase turn-on and turn-off times are GND
~
each externally programmable.
HS IRWS

The XR-2247/2247A, available in a 22-Pin DIP, operates

from a single power supply and provides TIL compati-
ble inputs.
fGND

FEATURES
ORDERING INFORMATION
Fully Programmable Write and Erase Currents
Fully Programmable Erase Turn-onlTum-off Times Part Number Package Operating Temperature
Internal Head Switching for Dual Head Drives XR-2247CN Ceramic O°C to + 70°C
Single Supply Operation XR-2247CP Plastic O°C to + 70°C
Inner Track Write Current Compensation XR-2247ACN Ceramic O°C to + 70°C
Inhibit Input XR-2247ACP Plastic O°C to + 70°C
TIL Compatible Inputs
Low External Parts Count
SYSTEM DESCRIPTION
The XR-2247/2247A accepts a serial binary data
APPLICATIONS stream input. With the write mode selected, negative
transitions of this input signal will alternately provide
Floppy Disk Drives
write current to each half of the head. The XR-22471
SinglelDual Head Systems
2247A provides two sets of current outputs for dual
Magnetic Tape Write Amplifier
head drives, with the head select (HS) control determin-
ing which is active. The write current is externally pro-
grammed with a resistor between the internal voltage
ABSOLUTE MAXIMUM RATINGS reference and the current setting input. Two high-
current open-collector outputs provide the erase coil
Power Supply Voltage (Pin 1) 16 V dc drive. Turn-on and turn-off delay circuitry is provided for
Input Voltage (all digital inputs) - 0.2V to + 16 V dc these outputs, with the delay externally programmed.
Reference Current (Pin 4) 10 rnA dc
Output Current (Pins 2, 10, 12,22) 100 mA dc
Storage Temperature - 55°C to + 150°C An inhibit input (INH) is provided to disable the outputs
Operating Junction Temperature 150°C to prevent false writing during power-on. With the read
Power Dissipation 750 mW mode selected, internal head switching channels the
Derate Above 25°C 6.5 mW/oC proper head to the read outputs.

4-6
 XR·2247/2247A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 12V, Rref = 10 kO, unless otherwise specified.

SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS

ICC Power Supply Current - 13 20 rnA VCC = 9V to 16V
VCC Power Supply Range 9 12 16 V
DIGITAL INPUT VOLTAGE
V,H High Level Voltage 2.0 - - V
V,L Low Level Voltage - - 0.8 V
DIGITAL INPUT CURRENTS
IIH High Level Current - 0.1 4.0 p.A V, = 2.4V
',L Low Level Current - 15 100 p.A
CTO or CT1 OUTPUTS
VCTH Output High Voltage 9.5 10.2 - V lout = 100 rnA
VCTL Output Low Voltage - 0.1 0.2 V lout = 1 rnA
EO or E1 OUTPUTS
IOL Output High Leakage - 0.01 20 p.A VCC = 16V
- = 100 rnA

•
VOEL Output Low Voltage 1.0 1.5 V 'out
TD ON Erase Turn-on Delay 0.45 0.5 0.55 mS RD1 = 4.55 KO, CD1 = 0.1 p.F
TD OFF Erase Turn-off Delay 0.9 1.0 1.1 mS RD2 = 9.54 KO, CD2 = 0.1 p.F
CURRENT SOURCE
Vref Reference - Pin 4 8.0 8.5 9.0 V Iref = 1 rnA
7.8 8.2 8.8 V Iref = 10 rnA
Vmir Iref Input Voltage - Pin 13 0.65 0.80 0.95 V Iref = 1 rnA
'WRL Write Current Off Leakage - - 0.03 15 p.A
Pins 15, 16, 19,20
Vcomp Current Sink Compliance - 7 - 12 V
Pins 15, 16, 19,20
'WR Write Current wlo IAWS- 3.7 4.1 4.5 rnA 'RWS = Low
Pins 15,16, 19,20
'WRS Write Current with 'RWS - 5.1 5.7 6.3 rnA 'RWS = High
Pins 15, 16, 19,20
AIWA Difference in Write Current - - 40 p.A 'RWS = Low (Note 1)
READ OUTPUT
eno Differential Noise Voltage at Read
Output -
2247 - 4 - p.V rms 8W = 10 Hz to 1.0 MHz
2247A - 1 - p.V rms 18 = 200 p.A

Note 1: Difference = 1(lplN 15,16 - 'piN 19,20)1

4-7
XR·2247/2247A
AC SWITCHING CHARACTERISTICS
Test Conditions: Test Circuit of Figure 4, VCC = 12V, TA = 25°C, IRWS = OAV

SYMBOL PARAMETER MIN TYP MAX UNIT CONDITIONS

td1 Delay from R/W going low through 0.8V - 0.11 - P.s R/W signal at Pin 5: f = 50
to CTO or CT1 going high through 9.0V. KHz, 50 % duty cycle,
amplitude = OAV to 2AV
td2 Delay from R/W going low through 0.8V - 0040 - P.s
to AO, A1, BO, or B1 settlir~g to final
See Figure 1
value.
td3 Delay from R/W going high through 2.0V to - 0.20 - P.s
AO, A1, 80, or 81 settling to final value.
td4 Delay from R/W going low through 0.8V - 0.13 - P.s
to Vref going high through 8.0V.
td5 Delay from R/W going high through 2.0V - 3.50 - P.s
to Vref going low through 1.0V.
td6 Delay from HS going high through 2.0V - 0.12 - p'S HS Signal at Pin 9: f = 50 KHz,
to CTO going high through 9.0V. 50% duty cycle, amplitude
Delay from HS going high through 2.0V - 0.11 - P.s
= OAV to 2AV
td7
to CT1 going low through 1.0V.
See Figure 1
td8 Delay from HS going low through 0.8V - 0.10 - P.s
to CTO going low through 1.0V.
td9 Delay from HS going low through 0.8V - 0.20 - P.s
to CT1 going high through 9.0V.
t10 WD low hold time. 150 - - ns See Figure 1
t11 WD high hold time. 500 - - ns
td12 Delay from WD going low through 1AV - 75 - ns See Figure 3
to AO or A1 turning on through 50%.
td13 Delay from WD going low through 1AV - 75 - ns
to BO or B1 turning off through 50%.
td14 Delay from WD going low through 1AV - 75 - ns
to AO orA1 turning off through 50%.
td15 Delay from WD going low through 1AV - 75 - ns
to BO or B1 turning on through 50%.
t16 Turn-on time, 10% to 90 %, of AO or A 1 - 50 - ns
t17 Turn-on time, 10% to 90%, of 80 or B1 - 50 - ns
t18 Turn-off time, 90% to 10%, of AO or A1 - 50 - ns
t19 Turn-off time, 90% to 10%, of BO or B1 - 50 - ns

4·8
 XR·2247/2247 A
PRINCIPLES OF OPERATION Erase 0 - EO (Pin 10), Erase 1 - El (Pin 12): These pins
provide high-current open-collector outputs for supply-
The functions of the input and output pins are as fol- ing erase current to the head. With R/W low, the erase
lows: output selected by HS will be low with the other open.
With R/W high, both EO and E1 will be open or high im-
Head Select - HS (Pin 9): The head select input makes a pedance outputs.
selection between head 0 and head 1. It channels the
proper drive signals to the CT and E pins. AD (Pin 16), BO (Pin 15): These pins provide the write cur-
rent to the head. AO is connected to one side of the
Read/Write - R/W (Pin 5): This input selects read data head, with BO connected to the other. They provide out-
when high, and write data when low. of-phase drive to each end of the head write coil. These
outputs are selected when HS is low.
Write Data - WD (Pin 21): Digital data to be written to the
head is fed into this pin. Data is alternately written to A1 (Pin 20), Bl (Pin 19): These outputs provide the same
AO, BO or A 1, B1 on negative transitions of WO. current-sink drive as AO/BO, except to the other head
when HS is high.
'RW Select - IRWS (Pin 14): This pin is used to provide a
digital control for the amount of current written to the RA (Pin 18), RB (Pin 17): These are read signal outputs to
head. It is used to provide inner track compensation. be connected to the read amplifier inputs. With R/W
When low, the head current is that dictated, by Rref. high, the head selected by HS will be connected to
When driven high, the head current is increased by these pins.

•
40%.
Inhibit - INH (Pin 3): When active (low), this input will turn
Vref (Pin 4), Iref (Pin 13): A resistor, Rref, connected be- off both erase and center taps to avoid erroneous out-
tween these pins control the write current. With IRWS puts during power-on.
low, the write current is approximately five times the
Rref current, and seven times with IRWS high. TD ON (Pin 6), TD OFF (Pin 7): The resistor, RO, and ca-
pacitor, CD, combination of these pins will set the turn-
Center Tap 0 - CTO (Pin 2), Center Tap 1 - CTl (Pin 22): on and turn-off times of the erase outputs. Figure 5
These pins are high-current outputs used to apply VCC shows the connection of these components, with sec-
to the center taps of the head. With R/W low, both CT tion 3 of the applications information describing the
outputs are in the high state. time as a function of RO and CD.

EaUIVALENT
SCHEMATIC
DIAGRAM

4-9
XR·2247/2247A
HS 2.0V

191 -------------------'1 0.8V

ANi
151

TOOFF

EO
1101

EI
(12)

CTO
(2)

CTI
(22)

WO
(21)

AO
1161

BO
115)

AI
(20) /--'<1J

BI

L"
(19)

re
141
V '3F '<14 \!.1.0V

Figure 1. Timing Diagram

INPUT OUTPUT
INH R/W HS CTO CT1 EO E1 Vref
1 0 0 H H Low Open H
1 0 1 H H Open Low H
1 1 0 L H Open Open L
1 1 1 H L Open Open L
0 - - L* L* Open Open H
* High impedance
Figure 2. Truth Table

4-10
 XR·2247/2247A
24V - - - - " ' "
'M>
(21) l.4V - - - ---r--------+_

o.4V - -

10%
NJ,A1 5mb
(16,20)

00, B1

•
(15,19)

Figure 3. Write Current Output Characteristics

q Vee

r
]
H1~F L
1 22
,..
9.4Kn <: 4.7Kn
• .<: [
[
2

3
XR-2247
21

20 n ...
~

y- ...
WD

f.I 1Kn
r 4 h
19 ~ ...
.......
...
L
1Kn
RJW ,.. r
L 5 18
~
~
r
6 17

T
L
1Kn
O.1IJ F O.lIJ F :: r 7 16 tt .........
.A'" •
L
r
L 8 15
,
f.I
J
l~n
.........
HS~
r
L 9 14
,
J ~IRWS
12Kn
....
......... r 10 13 }--
l
r
l 11 12 ~
J
......
12Kn
':" ...............
10Kn
Figure 4. Test Circuit for AC Switching Characteristics

4-11
XR·2247/2247A
APPLICATIONS INFORMATION Control of the erase outputs can also be done from
an external source by grounding Pin 6 and driving
A typical dual head connection of the XR-2247 in a flop- Pin 7 directly. The selected erase output will be on
py disk system is shown in Figure 5. Referring to Figure when Pin 7 is low and off when Pin 7 is high. This in-
5 and the electrical characteristics, the external com- put is not TTL compatible, however, with the thres-
ponents are calculated as follows: hold voltage being approximately % VCC.

1) Write Current, IWR 4) Resistors RWO are used to damp any ringing that
may occur when the write current transitions are ap-
plied to the head. Their value is determined by the
IWR = (5.3) (V ref - Vmir) IRWS = Low head characteristics and the desired damping.
Rref
Given IWR = 4.1 mA, Rref = 10 kO RRO is used to provide additional damping in the
Iref, the current into Pin 13, should not exceed 2.0 read mode if this is desired. Usually, RRO is only
mAo used with the XR-2247A where the head switching
diodes make the total read damping resistance ap-
2) Erase Current, IE proximately RROIIRWO. In the XR-2247, the transis-
tors used for head switching act to buffer RRO from
IE = VCTH - VOEL VCC - 2V the head.
RE RE Resistors RS are used to bias the head switching
network in the read mode and their value is selected
Given IE = 50 mA and VCC = 12V, RE = 2000 V2 W to provide currents in the 100 J.tA to 300 J.tA range.
3) Erase Oelay Time, TO ON and TO OFF 5) When in the read mode, digital signals appearing
along the WO line (Pin 21) can couple externally
TOON == 1.1 (R01 XC01)
through stray capacitances into the read si~
TO OFF == 1.05 (R02 x C02)
coming from the head. It is recommended that WO
Given TO ON = 0.5 ms and TO OFF = 1.0 ms, be held low while reading.

R01 = 4.55 kO, R02 = 9.54 kO

C01 = C02 = 0.1 J.tF

Vee

DiGITAL
READDATA
I (OUT)
I_ _ _ _ _ _ .J

READ AMP
See Dala Sheel

Figure 5_ Typical Dual Head Floppy Disk System

4-12
 XR-3448

Floppy Disk Read/Write

GENERAL DESCRIPTION FUNCTIONAL BLOCK DlAG,.R_AM
_ _ _.......,

The XR-3448 Floppy Disk Read/\Nrite is a single 28 Pin

monolithic solution for double-sided floppy disk drives.
The device is compatible with 8". 5)1., ... and 3Y2" drives.
providing all read and write functions and offering im-
proved performance over industry standard dual chip sets.
with lower external parts count. Schmitt trigger inputs and -LPF,I·Ao)
separate analog and power grounds aid noise and crosstalk
immunity. Both pre and post amplifiers. plus an AGC.
+LPFof+IN)
allow reliable operation with input signals ranging from
0.5 mV to 25mV.

The XR-3448 is available in standard or small outline 28

Pin packages. Control. write inputs. and read outputs are
TTL compatible. The device operates from +12 V and +5 V
supplies. The pinout is specially designed for similarity.to
the SSI-570 Read/\Nrite. and in many applications. the
XR-3448 acts as an improved version of that device.

FEATURES
A.GND

AGC
•
,CD
All Read/Write Functions on a Single Chip
Schmitt Trigger Inputs for Noise Immunity
TTL Compatible
Power Up and low Voltage Inhibit
low Peak Shift - No Trimming Necessary
On Board AGC
Wide Read Dvnamic Range
low External Parts Count
All Delays Rl Programmable
Separate Power and Signal Ground
Tunnel or Straddle Erase Compatibility

APPLICATIONS
SYSTEM DESCRIPTION
Single or Dual Head Floppy Disk Drive Systems
The XR-3448 Floppy Disk Read/\Nrite is a high perfor-
mance single chip solution for all standard floppy disk
ABSO LUTE MAXIMUM RATINGS drives. TTL compatible control and interface levels. and
+ 12 V and +5 V operation allows easy system implementa-
Power Supply Voltage tion with standard components. An on-board voltage moni-
Pin 28 (5 V) 7V tor. with hysteresis. supervises device voltage and disables
Pin 9 (12 V) 15V all operation during power up and down. Dual grounds.
Storage Temperature -65°C to +150°C one for the digital levels. the other for low level signals.
Operating Junction Temperature 150°C and the use of ECl processing logic eliminates digital
Power Dissipation (28 Pin 01 L) 800mW crosstalk and jittering coupled back into.the read heads.
Derate Above 25° C 6.5 mW/oC
Read error reduction performance is greatly enhanced by
ORDERING INFORMATION the window gating logic that qualifies data pules and
eliminates errors generated by noise or discontinuities
Part Number Package Operating Temperature during shouldering. A time domain filter further reduces
X R-3448CP Plastic aOc to +70°C errors caused by nonlinearities about data peaks. Together.
XR-3448CN Ceramic aOc to +70°C these systems allow improved performance margins over
XR-3448MD Small Outline OOC to +70°C simpler floppy disk read devices.
XR-3448CQ Quad Surface Mount aOc to +7aoC

4-13
XR-3448
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VOO = 12 V, VCC = 5 V, RW = 430n, RED = 10k, CE = 0.051lF, REH = 10kn, CD = 100 pF, RO
= 200n, CTO = 100 pF, RTO = 10kn, CPW = 330 pF, RPW = 10kn, Output Load = lkn to VCC, VIN (preamp) = DC coupled
10 mVp-p sine wave, VIN (postamp) = AC coupled 200 mVp-p sine wave, unless otherwise specified.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONOITIONS

Vee Recommended Power

Supply Voltage 4.5 5 5.5 V

VOO Recommended Power

Supply Voltage 10.8 12 13.2 V

lec Power Supply Current (5 V) 30 35 mA Read Mode

33 40 mA Write Mode

100 Power Supply Current (12 V) 17 22 mA Read Mode

22 25 mA Write Mode, IE =0
POWER SUPPLY MONITOR

Vec Power Up Threshold 3.0 3.5 4.0 V

Power Down Threshold 2.3 2.6 3.0 V

VOO Power Up Threshold 7.9 8.6 9.2 V

Power Down Threshold 6.5 7.5 8.0 V

LOGIC INPUTS

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

IlL Input Low Current -400 IlA VIL = 0.4 V

IIH Input High Current 20 IlA VIH = 2.4 V
DATA OUTPUT

VOL Output Low Voltage 0.5 V IOL=4mA

VOH Output High Voltage 2.7 V IOH = 400llA

TPW Pulse Width Accuracy -20 ±5 20 % RPW = 10kn CPW = 330 pF

RPW Recommended Resistor Range 5 25 kn

CPW Recommended Capacitor Range 100 620 pF

TIMERS

Erase Delay Accuracy -15 ±5 15 % Error from TED = RED CE

Erase Hold Accuiacy -15 ±5 i5 % Error from TEH = (REO+REH)CE

REoiREH Recommended Resistor Value 5 30 kn

CE Recommended Capacitor Value 0.01 0.068 IlF

Time Domain Filter Accuracy -15 ±5 15 % RTO = 10k, CTO =100 pF

RTO Recommended Resistor Value 1 15 kn

CTO Recommended Capacitor Value 51 330 pF

4-14
 XR-3448

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C. VDD = 12 V. VCC = 5 V. RW = 430n. RED = 10k, CE = 0.05.uF, REH = 10kn, CD = 100 pF, RD
= 200n. CTD = 100 pF. RTD = 1Okn. CPW = 330 pF, RPW = 1Okn, Output Load = 1kn to VCC. Y,N (preamp) = DC coupled
10 mVp-p sine wave. Y,N (postamp) = AC coupled 200 mVp·p sine wave. unless otherwise specified.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

READ MODE

PREAMP

AV Differential Voltage Gain 300 V/V f = 250 kHz, VCT = 1.5 V

Pin 22 Shorted to Ground

BW Bandwidth 5 15 MHz -3 dB Point

Gain Flatness -1.0 1.0 dB f = a to 1.5 MHz

•
ZIN Differential Input Impedance 10 30 kn f = 250 kHz

AGC

Dynamic Range 12 dB For 3 dB Output Variation

RAGC Recommended Resistor Range 3.3 10 25 kn

CAGC Recommended Capacitor Range 0.01 0.1 1 .uF

POST AMPLIFIER & DIFFERENTIATOR

AV Differential Voltage Gain 4 4.5 6 V!V f=250kHz

BW Bandwidth 5 15 MHz -3 dB Point

Gain Flatness -1.0 1.0 dB

WRITE MODE

VCT Center Tap Output ON Voltage VDD VOO VDO V RE'" 150n
-2.5 -2 -1.3

VE Erase Output ON Voltage 0.5 1.0 V RE = 150n

Unselected Head Erase Leakage 100 .uA YEO. VEl = 12 V, RE = 150n
IW Recommended Write
Current Range 3 10 mA RW = 680n to 180n

Write Current Accuracy -5 ±0.2 5 % CB =a

Write Current Unbalance -1 ±0.01 1 % Head a to Head 1

CB Current Boost Factor 1.25 1.30 1.35 CB = 1

4-15
XR-3448

DIFFERENTIATOR

+LPFo

FROM
LPF
-LPFo

TIME
DOMAIN
FILTER

AGC
CONTROL
OUTPUT
SHAPER
&
DRIVER

Figure 1. Read Error Reduction Circuitry

RD

PRINCIPLES OF OPERATION post-amplifier compensates for LPF insertion losses and

drives both the Peak Detector and Active Differentiator
Write Mode (see Figure 1) with waveform A. shown in Figure 2. The
Peak Detector is a comparator-like device that produces
In the write mode. RNY (Pin 19) is held low. Data is applied output whenever data input is above a threshold level (see
to the input Schmitt trigger (Pin 12). goes through a toggle Figure 2B). This output is employed as the Gating Logic
flip-flop, and into the write matrix. The proper magnetic enable. Rectified peak detector (.~utput is returned to the
head is selected by the matrix. depending on the level at AGC as the control signal.
HS (Pin 11). Both head center taps are connected to CT
(Pin 10) which sources the current sunk by the proper The Active Differentiator computes the first derivative of
transistor (Pin 1.2.3. or 4). the input signal. producing waveform C of Figure 2. Zero
Crossing Detector output toggles (Figure 20) at zero cross-
Write current is controlled by the resistor. R IW. on IWR ings. which correspond to data peaks - one crossing per
(Pin 6); when CB (Pin 5) is pulled high. write current is datum. Hysteresis in the detector aids noise immunity. The
boosted 30%. Tunnel erase delay and hold times are set by Window Gating Logic effectively provides an AND func-
a capacitor and two resistors on RECE (Pin 7) and RE (Pin tion: output (Figure 2E) appears only when (1) the Zero
8). Straddle erase heads are accommodated by eliminating Crossing Detector sees a crossing. and (2) the Peak Detector
CEo sees a data peak. Spurious signals. therefore. do not cause
output.
Read Mode
Noise and system nonlinearities however, occasionally pro-
Pulling RNY high selects data readback mode. The dual duce closely spaced false outputs. Further error reduction is
error reduction system employed by the XR·3448 greatly provicJ~cJ by a time domain fiiter foiiowing the gating logic.
diminishes read error rates. The read signal is routed Adjacent pulses. occurring before the minimum time delay
through a diode multiplexer into a low noise preamplifier. set by a resistor and capacitor on Td (Pin 16). are ignor-
This output is routed to an automatic gain control (AGC) ed (Figure 2E). Since nonlinearities occur in pairs, a valid
circuit which lowers peak shift: for most systems. external data pulse mixed with two invalid pulses still provides one
peak shift adjustment is unnecessary across an input dy- meaningful output - exactly as desired. Output pulse width
namic range from 500 J1.V to 25 mV. The AGC compresses is determined by an RC on Tpw (Pin 17). which feeds the
a 20 dB input variation down to a 5 dB output range. AGC output driver with TTL level constant width pulses. The
response time is affected by the RC at the AGC pin data appears at RD (Pin 18). as shown in Figure 2G.
(Pin 22). The compressed signal is applied to a low pass
filter (LPF) which attenuates high frequency noise. A

4-16
 XR-3448

A /\..
v
o DOD
\AI
Active Differentiator

The differentiation function requires a capacitor network

across Pins 20 and 21. The dominant component, capacitor
CD, is optimum when its current slew rate is maximized.
This occurs when

~ /\/\ ~f\-... 1 mA

J~ VV CD =
(AVO) (Ep) (wmax) (AF)

I I D I 10
xx
Where AVO is the gain of the amplifier
·Ep is the maximum expected input voltage
wmax is the maximum operating frequency in
n n n n xx
rad ians/sec of the sy stem
AF is the gain of the filter network

•
If Co is greater than the max imum value calculated above,
peak shifting will occur.

When Co is the only component employed, a pole is pro-

-fl:-fl:-fl:-f} duced by Co and the effective output resistance of 01
and 02 (See Figure 3). Ro. This pole lies at
X=ERROR CONDITIONS 1
wp = - - -
Figure 2. Read Waveforms 2Ro CO

APPLICATIONS INFORMATION where Ro is typically 40n.

The applications circuit of Figure 4 may be customized to

match the available magnetic head, interface pulse widths,
write currents, AGC times, data transfer rates, etc. Table 1
gives recommended component values anc~ ranges.

DESIGN INSTRUCTIONS

AGC:

The AGC time constant is set by the resistor and capacitor

on Pin 22. The time must be short enough that initial data
does not overdrive the amplifiers, yet long enough that
noise and offset levels between data bits do not register as
output. Delay time is determined by:
Figure 3. Simplified Active Differentiator Section

Perfect differentiation req~ires a phase shift of 90

0
This
For most applications at 500 kB data rate, a time of 1 ms, suggests wp should approach 00 since
using RAGC = 10 kn and CAGC = O.lfJF.
(J = arctan (wp/wo)

where Wo = operating frequency.

LPF
A large wp, however, produces a large noise bandwidth;
The LPF is strongly dependent on head type and other a reasonable compromise sets wp at 10 wmax. This pro-
system and circ;uit considerations. Constant gain and phase duces a phase shift of approximately 84° and limits the
to f = (baud rate/2) is tantamount to proper performance. noise bandwidth. The design criteria is now given by
Avoiding driver saturation requires that the filter current is
less than 2.8 mA. The postamplifier inputs are DC biased wmax = ----
internally. Blocking capacitors should isolate the DC level 20(R o Col
from the AGC output; optimum transient response charac-
teristics occur when the capacitors are before the filter,
directly after the AGC output.

4-17
XR-3448

XR·3448

Lc

C'2

C8

+5V

CE

+12V

~--------------oR/W

HS I - - - - - - - - - D R D OUTPUT

200

ERASE
DELAY

200

Figure 4. XR·3448 Typical Application

For maximum gain applications delete RAGC and CAGC and ground pin 22.

TABLE I
TYPICAL COMPONENT VALUES
Component Typical Value Recommended Range Component Typical Value

RIW 560n 180· 680n RH 1.5kn

REO. RE1 280n 100· 680n Cc .022pF
RED.REH 10kn 5k·30kn RF 470n
CE .047pF 0.01 ·O.068pF CF1 .001pF
RPW 10k 5k·25kn CF2 470pF
CPW 100 pF 51 pF· 1000 pF LC 680pH
CTD 100pF 51pF·330pF RO 200n
RAGC 6.81k 3.3k·25kn Co 1000pF
CAGC lpF .01p!;·lpF Lo 56pH

4-18
 XR-3448

Often, Ro is too low, creating a pole at a frequency greater Peak Shift Adjustment
than 10 wmax. I n this case, a resistor R 0, in series with Co
gives the equation: For the majority of applications, the inherent low peak
shift of the XR-3448 requires no improvement. However,
Wmax = ------ an additional trim can be implemented if necessary. The
20(RO + Ro) CD arrangement shown in Figure 7 will eliminate the current
imbalance in the differentiator and reduce comparator off-
This allows a degree of flexibility in selecting the noise set voltages. The potentiometer is adjusted for symmetrical
bandwidth, as shown in Figure 5. output with sinusoidal input.
PIn 18 OutPut

'cll)

PS • V, ('PSI - IPS2)
IPSI + IpS2

Co
Co AvO Epw
2OKTOSOK

10 K

Figure 7. Nulling Network to Minimize Peak Shift (PS)

Figure 5: Differentiator Response for CD and R
Time Doman Filter
A series inductor, LO, will further reduce noise bandwidth
by introducing another pole. When selected for 10 wmax, Filter time, t, is determined by the maximum period of ex-
as shown in Figure 6, LO is given by pected distortion, ~t, and the maximum operating fre-
1 quency, f max .
LO =
100(wmax) 2C O
Determination of Rand C involves the following considera-
tions:
The damping ratio, 0, should be between 0.3 and 1 where
(Ro + 0.5 RO) CD t = 0.215 RTO CTO + 200 nS
0=------
2y LOCO where RTO: 1 kn EO; R EO; 15kn, and CTO: 51pF EO; C EO;
330 pF

Output Shaper

The output shaper determines the pulse width of the data

Co AVO Epw
signal. Resistor and capacitor ranges follow the same guide-
lines as presented in the Time Domain Filter above. Pulse
width is:
t =0.215 RPW CPW + 120 nS

where RPW: 5kn EO; R EO; 30kn, and CTO: 100 pF ~ C ~

wVinlt1 620 pF.

Figure 6: Differentiator Response with RD. CO. and L.

Damping Resistors

Head damping resistors should be optimized for writing.

Their value depends entirely on the head employed and the
desired damping coefficient.

4-19
XR-3448

Write Current Write Erase Resistors

A current mirror uses the internal voltage reference and a Erase current is limited by series resistors from EO and E1
resistor from Pin 6 to ground for write current program- to the respective erase heads. Resistor values may be
ming. The resistor value is determined by approximated by:
2.35V VCT - VSAT
RIW (kil)
IWR (mA)
IERASE
Write current increases by 30% over this value when CB
(Pin 5) is held at a high TTL logic level.
For typical IERASE = 50 mA, VCT = 10.5 V, and VSAT =
Additional write current steps, if necessary, are implement- 500 mV, RE = 200 il.
ed as shown in Figure 8. In Figure 8(a), TTL logic lines and
reistors vary current output. Figure 8(b) shows the resis- Erase Delay Time
tive ladder method, with transistors selectively switching
resistors. The varying resistance on Pin 6 causes varying Tunnel erase delays are provided by the X R-3448. Both
write currents. Erase Delay Time, TED, which controls erase initiation
2.35V and Erase Hold Time, TEH, which delays erase release,
Iw(mA) are controlled by a simple RC circuit. In the configuration
R IW (total) (kil)
of Figure 1, TED is calculated as:

These method work for any number of control lines. CB

(Pin 5) is still active, and will multiply current by 1.3 when-
ever held high.
and TEH is determined by

Suggested resistor values range between 5kil and 30kil.

CE should range from O.OlJ1F to 0.068J1F.

~Vn CBl CB2 Rlw(eff)

Rn
I • 0 0 Rl + R2
I •• 0 1 R31/Rl + R2
I 1
1
0
1
Rl
R3 11R l
Vo=2.35V
I 6 1----4-----~
I-----+----'V\/'v---O VI

l+....I\N\r----<JCBl

Iw = ::!.2.... _ ( VI - Vo ) _ ( V 2 - Vo ) _ ... _ ( Vn - Vo )
R1w Rl R2 Rn
~-------~~v_-~CB2
WHERE Vo =2.35V AND VI THROUGH Vn ARE LOGIC LEVELS.

(A) (B)

Figure. 8. Obtaining Additional Write Current Steps: (A) TTL lines and Resistors Increase
and Decrease IW. (B) Transistors Switch Resistors to Increase IW.

4-20
 XR-3470A/3470B
Floppy Disk Read Amplifier
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-3470Al3470B is read amplifier system designed
primarily for use in a floppy disk drive system. It is de-
signed to perform the complete readback function, by
accepting the readback signal from a magnetic head
r
AMPLIFIER
INPUTS
and converting it into digital output pulses. To perform
this function, the circuit contains a high-frequency am- L l AMPLIFIER
OUTPUTS
plifier, an active differentiator, a zero-crossing detector,
and a time domain filter. OFF}:
DECOUPLING
J
L IACTIVE
The XR-3470Al3470B is suited for systems with data DIFFERENTIATOR
INPUTS
transfer rates up to 3 megabaud. High input sensitivity GROUND
allows operation with signal levels as low as 1.4 mV pp, -1
which gives it the flexibility to be used for single or dou- r l

•
ble density floppy disk systems. .1TONE-SHOT
COMPONENTS
DIFFERENTIATOR
COMPONENTS

The XR-3470Al3470B offers improvements (over the L J

standard 3470) of lower peak shift and power part-to- r
DIGITIZER
part input amplifier gain variations. ONE-SHOT
COMPONENTS DATA

The XR-3470Al3470B, available in an 18 Pin DIP, is L OUTPUT

powered by + 5 and + 12 volt power supplies.

ORDERING INFORMATION
FEATURES
Part Number Package Operating Temperature
Complete Floppy Disk Read Amplifier
Low Input Voltage detection 1.4 mV pp XR-3470ACN Ceramic O°C to + 70°C
Low Peak Shift 3470A 2% Max XR-3470ACP Plastic O°C to + 70°C
3470B 4% Max XR-3470BCN Ceramic O°C to + 70°C
Low Amplifier Gain Variation 100 VIV Min XR-3470BCP Plastic O°C to + 70°C
130 VIV Max
High Amplifier Frequency Response 10 MHz, Min.

SYSTEM DESCRIPTION
APPLICATIONS
The XR-3470Al3470B contains four internal signal
Single/Double Density Floppy Disk Read Amplifier blocks. Their functions are as follows: Input Amplifier -
Magnetic Read Amplifier This section receives an input directly from the mag-
netic head. It provides a nominal gain of 110 VIV, with
gain select pins to reduce gain or tailor it for ac re-
sponse. The amplifier has differential inputs and out-
puts. Active Differentiator - This circuit differentiates the
ABSOLUTE MAXIMUM RATINGS signal from the amplifier which causes a zero-crossing
for each peak of the readback signal. The time constant
Power Supply Voltage (Pin 11) 7 V dc and response of this section is externally set. Zero-
Power Supply Voltage (Pin 18) 16 V dc Crossing Detector - This function is performed by a volt-
Input Voltage (Pins 1 and 2) -2V to + 7 V dc age comparator. It produces complementary outputs
Output Voltage (Pin 10) -2V to + 7 V dc for the internal digital section. Digital Section - This sec-
Operating Ambient Temperature O°C to + 70°C tion consists of 2 one-shots and other control circuitry.
Storage Temperature - 65°C to + 150°C The one-shots are used to prevent false outputs, and
Operating Junction Temperature 150°C set the output pulse width.

4-21
XR·3470A/3470B
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = aoc to 7aoC; VCC1 = 4.75V to 5.25V; VCC2 = 1av to 14V; unless otherwise specified.

SYMBOL PARAMETERS MIN TYP MAX UNIT CONOITIONS

GAIN AMPLIFIER SECTION

AVD Differential Voltage Gain 100 110 130 VN f = 200 kHz, VID = 5 mV (RMS)
liB Input Bias Current - -10 -25 /LA
VICM Input Common Mode Range -0.1 - 1.5 V 5% max THD
Linear Operation
VID Differential Input Voltage Linear - - 25 mVpp 5% max THD
Operation
VOD Output Voltage Swing Differential 3.0 4.0 - V pp
10 Output Source Current, Toggled - 8.0 - rnA
lOS Output Sink Current 2.8 4 - rnA Pins 16 and 17
RI Small Signal Input Resistance 100 250 - kO TA = 25°C
RO Small Signal Output Resistance - 15 - 0 TA = 25°C, VCC1 = 5V
Single-Ended VCC2 = 12V
BW Bandwidth, - 3 dB 10.0 - - MHz TA = 25°C, VCC1 = 5V
VID = 2 mV (RMS), VCC2 = 12V
CMRR Common Mode Rejection Ratio 50 - - dB TA = 25°C, f = 100 kHz
AVD = 40 dB, VCC1 = 5V
VIN = 200 mV pp, VCC2 = 12V
PSSR1 VCC1 Supply Rejection Ratio 50 - - dB TA = 25°C, AVD = 40 dB
4.75 < VCC1 < 5.25, VCC2 = 12V
PSSR2 VCC2 Supply Rejection Ratio 60 - - dB TA = 25°C, AVD = 40 dB
10 < VCC2 < 14V, VCC1 = 5V
VDO Differential Output Offset - - 0.4 V TA = 25°C, VID = VIN = OV
VCO Common Mode Output Offset - 3.0 - V VID = VIN = OV
Differential and Common Mode
en Differential Noise Voltage - 15 - /LV BW = 10 Hz to 1.0 MHz
Referred to Input (RMS) TA = 25°C
ACTIVE DIFFERENTIATOR SECTION

10D Differentiator Output Sink Current 1.0 1.4 - rnA Pins 12 and 13, VOD = VCC1
PS Peak Shift 3470A - - 2.0 % f = 250 kHz, VID = 1V pp
3470B - - 4.0 % ICAP = 500/LA
VCC1 = 5V, VCC2 = 12V
See Figure 2
RID Differentiator Input Resistance - 30 - kO TA = 25°C
Differential
ROD Differentiator Output Resistance - 40 - 0 TA = 25°C
Differential
DIGITAL SECTION

VOH Output Voltage High Logic Level 2.7 - - V Pin 10, VCC1 = 4.75V
10H = - 0.4 rnA, VCC2 = 12V
VOL Output Voltage Low Logic Level - - 0.5 V Pin 10, VCC1 = 4.75V
10L = 8.0 rnA, VCC2 = 12V
tTLH Output Rise Time - - 20 ns Pin 10
tTHL Output Fall Time - - 25 ns Pin 10
t1A,B Timing Range Mono #1 500 4000 ns t1A,t1B
Et1 Timing Accuracy Mono #1 85 - 115 % R1 = 6.4 kO, C1 = 200 pF (Note 1)
t2 Timing Range Mono #2 150 - 1000 ns
Et2 Timing Accuracy Mono #2 85 - 115 % R2 = 1.6 kG, C2 = 200 pF (Note 2)
ICC1 VCC1, Power Supply Current - 25 40 rnA
ICC2 VCC2, Power Supply Current - 3 10 rnA

1. Accuracy guaranteed for R1 and C1 in range 2. Accuracy guaranteed for R2 and C2 in range
1.5 kO < R 1 < 10 kO 1.5 kO < R2 < 10 kO
150 pF < C1 < 680 pF 100 pF < C2 < 800 pF

4-22
 XR·3470A/3470B
42 K
3.6 K

13 K
13 K
PS1 PS2
PS = V2 (t - t ) at Pin 10
tPS1 + tPS2

1K 1 K

14
ICAP = current into Pin 12
15

Figure 2.

t VCCI

Figure 3. Active Differentiator and Zero Crossing Detector •

R/W
HEAD

COMP

DIGITAL
PULSE OUT

'RpS IS USED TO ADJUST FOR MINIMUM PEAK SHIFT.

V+ V+

Figure 4. Generalized Circuit Connection for Floppy DIsk Read System

4-23
XR·3470A/3470B
2.8 K 2.8 K

3.2 K 3.2 K

220 \I 220 !I

t VCCI
o II

Figure 5. Input Amplifier

10

F/F

Figure 6. Digital Section

4-24
 XR·3470A/3470B
R/W HEAD COUPLING so C1 should not be made too low. C1 = 0.1 ILF is nomi-
nal for most floppy disk applications.
When switching from the write channel to the read
channel, one must be careful not to present a differen-
tial voltage to the inputs of the amplifier, for this will FILTER NETWORK
result in an amplified swing at the output of the amplifi-
er, which will cause peak shifting at the digital output. A The filter network, between the XR-3470Al3470B ampli-
balanced diode network or FET switches, as shown in fier stage and differentiator stage, is subject to several
Figure 4, may be used to overcome this problem. system and circuit considerations.

The filter network, first and foremost, must be designed

READ·BACK II 16
to pass all frequencies up to 1/2 the maximum baud
SIGNAL
(AMPLIFIER
rate, with a constant gain and phase shift. This frequen-
INPUT) cy can be stated as f max , where
a)

DIFFERENTIATED
READ·BACK
f max = 1/2 (Baud rate}max
SIGNAL
b) In order to avoid saturation of the amplifier current
sources, the current into the filter must not exceed
2.8 mA. In order to meet this condition the impedance

•
COMPARATOR
OUTPUT of the filter must be governed by the following con-
c) straint
051 OUTPUT
d)

TIME DOMAIN
FILTER OUTPUT
z . > (AVO EP}max
e) min 2.8 mA
DIGITAL OUTPUT
(052)
where AVO is the gain of the amplifier
Ep is the maximum peak voltage of the
input signal
Figure 7a-1. Waveforms Through the XR-3470Al3470B
The differentiator inputs are dc biased internally. This I

implies that the dc level from the amplifier stage must

be blocked in order not to disturb these levels. There-
AMPLIFIER STAGE
fore blocking capacitors, Cb1 and Cb2, should be
The amplifier stage will typically amplify the read back placed before the differentiator inputs. In order to keep
signal by a factor of 110. In order to eliminate any offset the transient response to a minimum it is best to place
between the amplifier stages, a capacitor, C1, should the dc blocking capacitors before the filter network.
be inserted between Pins 3 and 4. If the input signal to
the amplifier is to be above 25 mV, clamping of the am-
plifier may occur. To reduce the gain, a resistor Ax may ACTIVE DIFFERENTIATOR
be inserted in series with C1 between Pins 3 and 4. The
graph in Figure 8 shows a plot of normalized gain vs Ax. The amplified filtered read back signal is fed into the ac-
tive differentiator. Here, the peaks of the read back sig-
It should be noted that capacitor C1 with Ax and the re- nal are transformed into zero crossings as shown by
sistance looking into Pins 3 and 4, will create a pole at Figures 7a and 7b.
approximately
In order to perform the differentiator function a capaci-
w - 1 tor Co is needed across Pins 12 and 13. The selection
P - (Ax + 250) C1 of Co for accurate zero crossing is optimized by maxi-
mizing current slew rate through CO, which occurs
when
NORMALIZED
GAIN

1.00 Co = 1 mA
0.80
(AVO Epw}max AF
0.60 Where AVO is the gain of the amplifier
0.40
Ep is the maximum expected input voltage
w is the maximum operating frequency in
0.20
radians/sec of the system
'--+--t--t--+---i-+--t--t--+-If---- R,(II) AF is the gain of the filter network
100 200 300 400 500 600 700 800 900 1000

If Co is greater than the maximum value calculated

Figure 8. Normalized Gain vs Rx for Amplifier Stage above, peak shifting will occur.

4-25
XR·3470A/3470B
As can be seen from Figure 9; the capacitor Co and the
effective output resistance, RO of transistors 01 and
02 produce a pole given by

1
"'p = 2ROCO

where RO is typically 400.

Figure 10. Differentiator Response for Co and R

+~---------4----------+----------,
Yin(l)

In order to reduce the noise bandwidth further a second

pole can be introduced at 10 "'max by placing an induc-
tor in series with Co and RO, where LO is given by

1
LO = ----=---=--
Figure 9. Simplified Active Differentiator Section 100(wmax)2 Co

The damping ratio, 0, should be between .3 and 1 where

In order to obtain a phase shift approaching 90° for per- o = .:....(R..;:O:....+--=0=.5=Ro~)=-C-=.o

fect differentiation "'p would have to approach 00 since 2"LOCO

() = tan -1 (wp/"'o)

"'0 = operating frequency

It must be considered, however, that making "'p as high

as possible also produces a noise bandwidth as high as
possible.

In order to come to a reasonable compromise "'p

should be selected to be ten times the maximum ex- Co AVO Epw

pected operating frequency.

"'p = 10 "'max

where "'max is the maximum operating frequency of

the system in radians/sec. wVin(1)

Doing this produces a phase shift of approximately 84°,

while limiting the noise bandwidth. The deSign criteria
Figure 11. Differentiator Response with RD. CO. and L
is now given by

1
"'max = 20ROCO

It may be that RO is too low, creating a pole at a higher PEAK SHIFT CONSIDERATIONS
frequency than 10 "'max. If this is so one can insert a
resistor RO in series with CO, giving the equation The arrangement shown in Figure 12 will eliminate the
current imbalance in the differentiator, and offset in the
1 comparator, thus minimizing the peak shift at the digital
"'max = 20RCO output. The potentiometer is adjusted with a minimum
sinusoidal Ep", at the input, for symmetrical digital
where R = RO + 0.5RO waveform at the digital output, Pin 10.

4-26
 XR·3470A/3470B
ZERO CROSSING DETECTOR MONOSTABLE #2 (OS2)
The differentiated output signals from the active differ- This one shot is used to adjust the pulse width of the
entiator are run into a comparator. Since the outputs of digital output pulses at Pin 10. The adjustment of this
the active differentiator are 180 0 out of phase, the com- one shot is done via external components R2 and C2
parator will produce an output pulse whenever the dif- where
ferentiated Signal crosses zero. This is shown in Fig-
ures 7b and 7c. 1.5 K < R2 < 10 K
150 pF < C2 < 680 pF
MONOSTABLE #1 (OS1) The pulse width of the output pulse is given by
This one shot is used to prevent false digital outputs to = R2C2 (0.625)
due to noise at zero crossings as shown at time tA, in
Figure 7a. The adjustment of the one shot is done via This one shot is triggered on the rising and falling edges
external components R1 and C1 where of the time domain filter output, as shown on Figures 7e
and 7f, giving the corresponding digital pulses for the
1.5K < R1 < 10K peaks of the read back signal, shifted by OS1 's time, t,
0.150 pF < C1 < 680 pF as can be seen from Figures 7a, 7d, and 7f.
and t = R1C1 (0.625) + 0.2 p'sec
Pin 10 OUTPUT

•
The value of t is determined by the maximum period of
expected distortion, .:IT, and the maximum operating
frequency PS = V. (IPSI - IPS2)
IPSI + IPS2

where .:IT < t < _1_ _ .:IT

4f max 2

The one shot is triggered on the rising and falling edge

of the comparator output as can be seen in Figures 7c 10 K
and 7d. The time domain filter will change state on the
rising edge of OS1 's output if and only if the pulse width
of the comparator output is greater than the time of
OS1 's pulse, t. This is shown in Figures 7c, 7d, and 7e. Figure 12. Nulling Network to Minimize Peak Shift (PS)

4-27
 XR-3471

Floppy Disk Write Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-3471 is a write amplifier designed to provide the

complete interface between write data signals and tunnel XR·3471
and stradd Ie erase magnetic heads. Although primarily 20 cn
intended for floppy disk drive systems, the XR-3471 can CURRENT
SELECT
also be used in other magnetic media systems such as tape
drives. Write and erase currents are each externally resistor
programmable. Also included is circuitry for inner track
write current compensation.
GND

The XR-3471, available in a 20 pin DIP or small outline

package, provides TTL compatible inputs. Tunnel erase
delays are determined by external reistors and capacitors.

WD

R/W2 TOGGLE
FEATURES
R/W1
Fully Programmable Write & Erase Currents
Fully Programmable Erase Turn-on/Turn-off Times
(Tunnel and Straddle Erase Compatibility)
CB
Inhibit Output
TTL Compatible Inputs
Direct Replacement for Motorola MC3471 NC

INH

APPLICATIONS ORDERING INFORMATION

Floppy Disk Drives Part Number Package Operating Temperature
Magnetic Tape Write Amplifier XR-3471CN Ceramic O°C to +70°C
o
XR-3471CP Plastic OoC to +70 C
XR-3471MD Small Outline O°C to +70°C

ABSOLUTE MAXIMUM RATINGS

Power Supply Voltage, VCC 2 30 V dc SYSTEM DESCRIPTION

VCC 1 7.0 V dc
Input Voltage -0.2 V to +5.75 V dc The X R-3471 accepts a serial binary data stream input.
(All Digital Inputs) With the write mode selected, negative transitions of this
Output Current 100 mA dc input signal will alternately provide write current to each
Storage Temperature -55°C to +150°C half of the head. The write current is externally program-
Power Dissipation med with a resistor between the internal voltage reference
Plastic Package 650mW and the current setting input. A high-current open collector
Derate Above 25°C 5.0 mWfC output provides the erase coil drive. Turn·on and turn-off
Ceramic Package lW delay circuitry is provided, with the delay externally
Derate Above 25°C 8.0mWfC programmed.

4-28
XR-3471

ELECTRICAL CHARACTERISTICS
Test Conditions: VCC1 ~ 4.5 to 5.5 V, VCC2 ~ 10.8 to 26.4 V, unless specified otherwise. Typicals given for VCCl .. 5.0 V, VCC2" 12 V
and TA" 25° C, unless noted otherwise.

SYMBOL PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

DIGITAL INPUT VOLTAGES

ICC2 Power Supply Current 17 60 rnA VCCl

ICC2 7.5 30 VCC2

V,H High Level Input Voltage 4,8,13 2.0 V VCCl .. 4.5 V

V,L Low Level Input Voltage 4,8,13 0.8 V VCCl =5.5 V

V,K Input Clamp Voltage 4,5,8,13 -0.87 -1.5 V ',K" -12mA

VT(+) Positive Threshold 5 1.5 1.75 2.0 V VCCl =5.0 V

VT(-) Negative Threshold 5 0.7 0.98 1.3 V VCC1 .. 5.0 V

II
VHTS Hysteresis 0.4 0.76 V VT(+l - VT(-l

DIGITAL INPUTeURRENTS

"H High Level Input Current 4,5,8,13 0.1 40 /J.A VeCl .. 5.5 V, VCC2 .. 26.4 V,
V, = 2.4 V

',L Low Level Input Current 4,5,8,13 -1.6 rnA VeCl .. 5.5 V, VCC2 .. 26.4 V
4 0.36 VCC2" 12 V
4 0.76 VCC2 =24 V
5 0.46 VeCl" 5.0 V
8,13 0.39 VCCl .. 5.0 V

DIGITAL OUTPUT LEVEL (lNHIBITl

IOH High Level Output

Current 10 100 /J.A VOH" 7.0 V, VCC1 .. 4.5 V

VOL Low Level Output

Voltage 10 0.5 V IOL = 4.0 rnA, VCCl .. 4.5 V

CENTER·TAP and ERASE OUTPUTS

VOH Output High Voltage 18,20 V

VCC2 VCC2 'OH" -100 rnA VCCl .. 4.5
-1.5 V -1.0 VCC2 .. 10.8 to 26.4 V

VOL Output Low Voltage 18,20 mV 'OL" 1.0mA

70 150 VCC2" 12 V
70 150 VCC2 =24 V

IOH Output High Leakage 15,17 0.01 100 /J.A VOH .. 24 V, VCC1 = 4.5 V,
VCC2= 24 V

VOL Output Low Voltage 'OL" 90 rnA, VCCl .. 4.5 V

0.27 0.60 V VCC2 = 12 V
0.27 0.60 V VCC2=24 V

4-29
 XR-3471

ELECTRICAL CHARACTERISTICS
Test Conditions: VCCl = 4.5 to 5.5 V, VCC2 = 10.8 to 26.4 V, unless specified otherwise. Tvpicals given for VCCl .. 5.0 V, VCC2 = 12 V
and TA = 25°C unless noted otherwise. .

SYMBOL PARAMETERS PINS MIN TYP MAX UNIT CONDITIONS

CURRENT SOURCE

VREF Reference Voltage 1 5.7 V

VDEG Degauss Voltage 1 1.0 V Voltage Pin 1-Voltage Pin 2

VF Bias Voltage 2 0.7 V

IOH Write Current

Off Leakage 6,7 0.03 15 IJA VOH" 30 V

VSAT Saturation Voltage 6,7 0.85 2.7 V VCC2 = 12 V

fllRW Current Sink Compliance 6,7 15 40 IJA V6,7 = 4.0 V to 24 V

IRA Average Value

Write Current 6,7 Note 2

2.91 3.0 3.09 mA RW = 10k, CB = Low

5.64 5.89 6.14 mA RW" 5.0k, CB" Low

CB Current Boost 31.3 33.3 35.5 % RW" 10k, CB = High

fllRW Difference in
Write Current 6,7
IRIW2 - IRlWl
0.003 0.015 mA R = 10k, IWRS = Low
0.005 0.030 mA R .. 5.0k, IWRS = Low

IRlWl + IRIW2
Note 2 IAVG=-----
2

4-30
XR-3471
AC SWITCHING CHARACTERISTICS
Test Conditions: VCC1 = 5.0 V. TA = 25°C. VCC2 = 24 V. IRWS = 0.4 and IRNJ = 3.0 mAo unless specified otherwise (refer to Figure 1).

PARAMETERS FIN MIN TVP MAX UNIT

Note 4
1. Delay from Head Select going through 0.8 V to
CTO going high through 20 V. HS. Pin 13 1.6 4.0 J.l.S

2. Delay from Head Select going low through 0.8 V

to CTl going low through 1.0 V. HS 2.1 4.0 J.l.S

3. Delay from Head Select going high through 2.4 V

to CTO going low through 1.0 V. HS 1.7 4.0 J.l.S

4. Delay from Head Select going high through 2.4 V

to CTl going high through 20 V. HS 1.4 4.0 J.l.S

5. Delay from RNJ going low through 0.8 V to

CTO going low through 1.0 V. RNJ. Pin 4 1.3 4.0 J.l.S

•
6. Delay from RNJ gOing low through 0.8 V to
CTl going high through 20 V. RNJ. Pin 4 0.8 4.0 J.l.S

7. Delay from RNJ going low through 0.8 V to

CTO going high through 20 V. RNJ. Pin 4 0.75 4.0 J.l.S

8. Delay from RNJ goin~' low through 0.8 V to

CTl going low through 1.0 V. RNJ. Pin 4 1,2 4.0 J.l.S

9. After RNJ goes high. delay from RNJl turning

off through 10% to CTO going high through 20 V. RNJ. Pin 4 20 750 ns

10. After RNJ goes high. delay from RNJl turning

off through 10% to CTl going low through 1.0 V. RNJ. Pin 4 20 1200 ns

11. After RNJ goes high. delay from RNJ2 turning

off through 10% to CTO going low through 2.0 V. RNJ. Pin 4 20 1200 ns

12, After RNJ goes high. delay from RNJ2 turning

off through 10% to CTl going high through 20 V. RNJ. Pin 4 20 600 ns

13. After RNJ goes low. delay from CTO going low
through 1.0 V to R(Wl turning on through 10%. R(W, Pin 4 20 750 ns

14. After RNJ goes low. delay from CTl gOing low
through 1.0 V to RNJ2 turning on through 10%. RNJ, Pin 4 20 750 ns

15. After RNJ goes low, fall time (10·90%) of RNJ1. RNJ, Pin 4 5.0 200 ns

16. After RNJ goes low, fall time (10-90%) of RNJ2 RNJ, Pin 4 5,0 200 ns

17 Set-up time, HS going low before RNJ going low. RNJ, Pin 4 4.0 J.l.S

18. Write Data low Hold Time. WD, Pin 5 200 ns

19. Write Data high Hold Time. WD, Pin 5 500 ns

20. Delay from RNJ going high through 2.0 V to RNJ1

turning off through 10% of on value. RNJ, Pin 4 3.9 J.l.S

21. Delay from RNJ going low through 0.8 V to

inhibit going low 0.5 V (Note 5). R/'N, Pin 4 0.08 4.0 J.l.S

22. After RNJ goes high, delay from R/'Nl turning off
through 10% to inhibit going high, through 1.5 V
(10k pull-up on inhibit) (Note 5) RNJ, Pin 4 20 750 ns

23. After RNJ goes high, delay from El going high

through 23 V to inhibit going through 1.5 V
(10k pull-up on inhibit) (Note 5). R/'N, Pin 4 20 750 ns

4-31
 XR-3471

RtW

EO-----4-+-----------r---------4~------~

E1---+-h1

R/W1 7----..;;;;.,.~

R/W2 6-----.,.--"""

r---- -r-----,
I

-... 26
27

Figure 1. AC Timing Diagram

WD (PIN 5)
2.4 V

0.9 V -- ---
, I
I \
0.2 V

RJW1 (PIN 7)
10% .!1, ~® --. !.-ev
50%
90% f\
"- ~,,~

---. CD ~ -. II ... @

===-~~®--1-
RJW2 (PIN 6)
~® -'1 ®
10~o
50%
90%

Figure 2. R/W1 and R/W2 Relationship

4-32
XR-3471

AC CHARACTERISTICS Continued Q
Test Conditions: Veet - 5.0 V, TA .. 25 e, Vee2 .. 24 V. AM = 0.4 V. unless specified otherwise (refer to Figure 2).

PARAMETERS (Note 6) MIN TVP MAX UNIT

1. Delay from Write Data going low through 0.9 V to

R/Wt turning on through 50%. 85 ns

2. Delay skew difference of R/W1 turning off and

R/W2 turning on through 50% after Write Data
going low through 0.9 V. -40 1.0 40 ns

3. Delay from Write Data going low through 0.9 V to

R/W1 turning off through 50%. 80 ns

4. Delay skew, difference of RM'1 turning on and

R/W2 turning off 50% after WD going low through
0.9 V. -40 1.0 40 ns

5. Rise time, 10 to 90% of RM'1. 1.7 200 ns

6.

7.

8.

Note 3
Note 4
Rise time, 10 to 90% of RM'2

Fall time, 90 to 10% of RM'1

Fall Time, 90 to 10% of R/W2.

Test numbers refer to encircled number in Figure 1.

AC test waveforms applied to the designated pins as follows:
Pin fin Amplitude Duty Cycle
1.7

12

12
200

200

200
ns

ns

ns
•
HS. Pin 1350kHz 0.4 to 2.4 V 50%
AM', Pin 450kHz 0.4 to 2.4 V 50%
WD, Pin 5 1.0 MHz 0.2 to 24 V 50%
Note 5 26 or 27. whichever produces the longer delay, will control inhibit.
Note 6 Test numbers refer to encircled numbers in Figure 2. fin - 1.0 MHz, 50% Duty Cycle and Amplitude of 0.2 V to 2.4 V.

t-----t--+---t--Q+12V

R/W 0--+--+------1

we Q - - t - + - - - - - \

t--_----......-o+5V
CBo---------1

INH 0--------1

HSo-------------------------~
Figure 3. XR·3471 Typical Application Schematic
4-33
 XR-3471

PIN DESCRIPTION TABLE

NAME SYMBOL PIN DESCRIPTION

Head Select HS 13 Head Select input selects between head I/O pins center-tap, erase, and
read write. A HIGH selects Head 0 and a LOW selects Head 1.

Read/Write Select R/W 4 Th is input selects the write mode when LOW, the read mode when HI G H.

Write Data WID 5 Write Data input controls the turn on/off of the write current. The internal
divide-by-two flip-flop toggles on the negative going edge of this input to
direct the current alternately to the two halves of the head coils.

Current Boost CB 8 Current Boost selects the amount of write current used.
When LOW, the current e~uals the value according to the external resistor. When
HIGH, the current equals the low current +33%.

Vref Vref 1 A resistor between these pins sets the write current. A 10k resistor produces
Iref Iref 2 3 mA of write current.

Center-tap 0 eTO 18 Center-tap 0 output is connected to the center tap Head O. It will be pulled
to GND or VCC2 (+12 or +24) depending on mode and head selection.

Erase 0 EO 17 Erase 0 will be LOW for writing on Head 0, and floating for other conditions.

Center-tap 1 CT1 20 Center-tap 1 output is connected to the center tap of Head 1. It will be pulled
to GND or VCC2 (+12 or +24) depending on mode and head selection.

Erase 1 E1 15 Erase 1 will be LOW for writing on Head 1, and floating for other conditions.

R/W1 R/Wl 7 These pins are the differential outputs, connected directly to the magnetic
R/W2 R/W2 6 heads.

VCC1 14 +5 V Power

VCC2 19 +12 V or +24 V Power

PGND 16 Coil grounds

GND 3 Reference and logic ground

TED ON TED 12 Erase turn on delay control (RC or logic).

TEH OFF TEH 11 Erase Hold (turn off delay) control (RC or logic).

INHIBIT INH 10 I nh ibit is an open collector output pulled low whenever the leads are in the
write, degauss, or erase mode. Inhibit is used for step or read inhibit.

4-34
XR-3471

A/W 0--+---1------1

Hso-------------------------------------~

Figure 4. Dual Head Floppy Drive Using the XR·3470 and XR·3471

TYPICAL APPLICATIONS
The XR·3471 is designed for use with the XR-3470 Read
Amplifier. A complete dual head floppy disk signal proces-
sing chain includes the XR-3470, XR-3471, and a head
selection switching matrix. Figure 3 shows the XR-3471
in a typical application. Figure 4 shows the XR-3470 and
the XR-3471 in a complete floppy drive.

Component Selection 10r---------------------------------~

Write current is set by RW. Figure 5 shows the relationship

between IW and RW.

Erase current is limited by external resistors, REO and RE1.

VCC2 -1.5 V
IE~----
RE
Tunnel erase delay times are determined by external resis-
tors and capacitors. Erase delay, the time between the write
mode is selected and erase current flows equals

4 5 6 7 8 9 10 11 12 13 14 15
RW (kn)
Erase Hold, the time between the end of writing and cessa-
tion of erasure is found as
Figure 5. Write Current Dependence on RW

In Figure 4, the head selection is performed by standard

switching diodes. CDEG controls degaussing times and may
be omitted in systems not requiring degaussing. The reader
is directed to the XR·3470 data sheet for a discussion of
read circuit component selection.

4-35
4-36
 Cross References & Ordering Information

Telecommunication Circuits

Data Communication Circuits

Computer Peripheral Circuits

n_s_t_ru_m_e_n_ta_t_io_n_c_ir_c_u_it_s___________•
.....

.....In_t_e_rf_a_c_e_C_i_rc_u_it_s______________•

.....s_p_e_c_ia_I_F_u_n_ct_io_n_C_ir_c_u_it_s__________•

1IIII
~u_s_e_r_s_pe_c_if_ic__Li_n_ea_r_I_C_s___________________
I

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

5
 Section 5 - Industrial Circuits
Operational Amplifiers. . . . . . . . . . 5-2
Fundamentals of Operational Amplifiers 5-2
Definitions of Operational Amplifier Terms . 5-3
Basic Applications of Operational Amplifiers 5-4
Choosing the Right Op Amp . . . . . . . . . 5-10
XR-082/083 Dual Bipolar JFET Operational Amplifier 5-12
XR-084 Quad Bipolar JFET Operational Amplifier .. 5-15
XR-094/095 Quad Programmable Bipolar JFET Operational Amplifier 5-17
XR-096 Quad Programmable Bipolar JFET Operational Amplifier 5-19
XR-146/246/346 Programmable Quad Operational Amplifiers 5-21
XR-1458/4558 Dual Operational Amplifiers . . . . . . 5-25

•
XR-3403/3503 Quad Operational Amplifiers . . . . . . 5-27
XR-4136 Quad Operational Amplifier . . . . . . . . . 5-30
XR-4202 Programmable Quad Operational Amplifier 5-33
XR-4212 Quad Operational Amplifier . . . . . . 5-37
XR-4560 Dual Low Noise Operational Amplifier '" 5-40
XR-4739 Dual Low Noise Operational Amplifier .. . 5-44
XR-4741 Quad Operational Amplifier . . . . . . . . . 5-47
XR-5532/5532A Dual Low Noise Operational Amplifiers 5-50
XR-5533/5533A Dual Low Noise Operational Amplifiers 5-54
XR-5534/5534A Dual Low Noise Operational Amplifiers 5-58
Timers . . . . . . . . . . . . . . . . . . 5-63
Fundamentals of IC Timers . . . . 5-63
Choosing the Right IC Timer . . . . 5-67
XR-320 Monolithic Timing Circuit . 5-70
XR-555 Timing Circuit . . . . . . . . 5-75
XR-L555 Micropower Timing Circuit 5-78
XR-556 Dual Timer . . . . . . . . 5-82
XR-L556 Micropower Dual Timer 5-85
XR-558/559 Quad Timing Circuits . 5-91
XR-2556 Dual Timing Circuit . . . . 5-95
XR-2240 Programmable Timer/Counter · 5-104
XR-2242 Long Range Timer . . . . . . · 5-112
XR-2243 Micropower Long Range Timer · 5-116
Voltage Regulators . . . . . . . . . . . . . . . · 5-121
XR-494 Pulse-Width Modulating Regulator · 5-122
XR-495 Pulse-Width Modulating Regulator · 5-126
XR-1468/1568 Dual Polarity Tracking Voltage Regulators · 5-130
XR-1524/2524/3524 Pulse-Width Modulating Regulators . · 5-132
XR-1525A12525A13525A,
XR-1527A12527A/3527A Pulse-Width Modulating Regulators · 5-140
XR-1543/2543/3543 Power Supply Output Supervisory Circuits · 5-147
XR-2230 Pulse-Width Modulator Control System · 5-155
XR-4194 Dual-Tracking Voltage Regulator . . . · 5-162
XR-4195 ± 15 V Dual-Tracking Voltage Regulator · 5-165

5-1
Fundamentals of Operational Amplifiers
The "ideal" operational amplifier can be defined as a
voltage-controlled voltage amplifier circuit which offers
infinite voltage gains with an infinite input impedance,
zero output impedance, and infinite bandwidth. The ad-
vantage of such an idealized block of gain is that one
can perform a large number of mathematical "opera-
tions", or generate a number of circuit functions by ap-
plying passive feedback around the amplifier.

The key features of operational amplifier application

can be illustrated using the simple feedback circuit of AS
+ o--"I..''V'v--.....---+
Figure 1, and assuming that the operational amplifier
has infinite gain and infinite input impedance. Then, the
following two conditions have to be satisfied:

a) Since the voltage gain is infinite, the net voltage

across the input terminals of the operational amplifi-
er must be zero, if the operational amplifier output Figure 2. Basic Feedback Configuration Using an Operational
voltage is to be finite. In the circuit of Figure 1, this Amplifier With Finite Input Impedance and Gain
causes the inverting input terminal of the operation-
al amplifier to behave as a "virtual ground". It should be noted that, for large values of RIN, as the
voltage gain increases (i.e. A -+ 00), this expression rap-
b) Since the input impedance of the ideal operational idly converges to that given in equation 2; and the cir-
amplifier is infinite, no input current is drawn by the cuit performance becomes solely determined by the ex-
operational amplifier, the total current going into the ternal components.
circuit node connected to the inverting input of the
operational amplifier (node Q in Figure 1) must be In addition to having finite gain and input impedance,
equal to the total current coming out, i.e.: an actual operational amplifier circuit also has finite in-
put bias currents as well as input offset voltage and cur-
IS = -IF and VIN = _ Vo (1 ) rents. A more complete model of a practical operational
RS RF amplifier is shown in Figure 3 where IS indicates the fi-
nite input bias currents; Vio and lio represent the volt-
Solving for the overall voltage gain, one obtains: age and current offsets associated with the circuit and
RO is the output resistance. Due to non-zero values of
Vio and lio in a practical operational amplifier circuit,
(2)
VOUT =1= 0 for VIN = O.

Secause of this property, the noninverting input of

an operational amplifier is often referred to as its
"summing input".

r' . . . ......
I .....
......
I ......
......

-o-------~----~ ~
As ,-
I .......
......
......
......
+ I + (' JIB AV1 ...... ~
v IN
, Vio~ ~ .... .... ,,-, RO ......
v'l
"' .I:~~t: '-",-".,./ ,,'"
-to ".,. +
Figure 1. The "Ideal" Operational Amplifier as a Feedback lAIN

1
Amplifier R2 I I ".,.
'io

In the case of actual operational amplifiers, both the

;+ /
,- /
".,.
Vo U1'

voltage gain and the input impedance are quite high,

I ,.. /

but still finite. Figure 2 shows the same basic feedback

I ".,.
/ -
circuit assuming that the amplifier now has a finite in-
~".,.
put resistance, RIN, and a finite voltage gain A. For sim-
pliCity, the output impedance of the operational amplifi- Figure 3. Equivalent Circuit of a Practical Operational
er is assumed to be negligible. The overall voltage gain Amplifier Showing the Effects of Finite Input
of the circuit can now be expressed as: Impedance, Current and Voltage Offsets

5-2
Definitions of Operational Amplifier Terms
Since the operational amplifier has become a universal Output Voltago Swing: The peak output voltage swing, re-
building block for circuit and system design, a number ferred to zero, that can be obtained without Clipping.
of widely accepted design terms have evolved which
describe the comparative merits of various operational Large·Signal Voltage Gain: The ratio of the output voltage
amplifiers. Some of these terms are defined below: swing to the change in input voltage required to drive
the output from zero to this voltage.
Input Offset Voltage: The input voltage which must be ap-
plied across the input terminals to obtain zero output Full·Powor Bandwidth: Maximum frequency over which
voltage. the full output voltage swing can be obtained.

Input Offset Current: The difference of the currents into Unity·Galn Bandwidth: Frequency at which the open loop
the two input terminals with the output at zero volts. voltage gain is equal to unity.

Input Bias Current: The average of the two input cur- Slew Rate: The maximum time rate of change of the out-
rents. put voltage, for a voltage step applied to the input. It is
normally measured at the zero crossing point of the
Input Common·Mode Range: Maximum range of input volt- output voltage swing with the amplifier frequency com-
age that can be simultaneously applied to both inputs pensated for unity gain.
without causing cutoff or saturation of amplifier gain
stages. Overload Recovery Time: Time required for the output
stage to return to active region, when driven into hard
Common·Mode Rejection Ratio: Ratio of the differential saturation.
open-loop gain to the common-mode open-loop gain.
Gain Margin: The amount by which the voltage gain is
Supply Voltage Rejection Ratio: Input offset voltage below the unity (0 dB) level, at the frequency where the
change per volt of supply voltage change. excess phase shift across the amplifier is exactly 180 0 • •

It is measured in decibels, and must be positive for un-

Input Resistance: The ratio of the change in input voltage conditional stability.
to the change in input current on either input with the
other grounded. Phase Margin: 180 0 minus the" excess phase shift at the
Frequency where the magnitude of the open loop volt-
Supply Current: The current required from the power age gain is equal to unity. It is measured in degrees and
supply to operate the amplifier with no load and the out- must be positive for unconditional stability.
put at zero.

5-3
Basic Applications of
Operational Amplifiers
The general usefulness of the operational amplifier the amplifier input without circuit adjustment, the
stems from the fact that when used in a feedback loop, source resistance for both inputs should be equal. In
its overall performance and transfer characteristics are this case, the maximum offset voltage would be the al-
determined almost totally by the choice of feedback gebraic sum of amplifier offset voltage and the voltage
components. To be universally useful in such an appli- drop across the source resistance due to offset cur-
cation, the "ideal" operational amplifier should exhibit rent. Amplifier offset voltage is the predominant error
infinite gain, infinite input impedance and infinite band- term for low source resistances, and offset current
width. Although these are all idealized characteristics, causes the main error for high source resistances.
the practical monolithic operational amplifiers closely
approximate these features, particularly for low fre-
quency applications.

The availability and the low-cost of the integrated oper-

ational amplifier makes it an extremely versatile build-
ing block for analog system or equipment design.
Therefore, it is mandatory that the circuit designer be
familiar with the fundamental applications of operation-
al amplifiers. This section of Exar's Operational Amplifi-
er Data Book is intended to familiarize the designer with VOUT
some of the simple but fundamental circuit configura-
tions using IC operational amplifiers. The discussion is
slanted toward the practical applications of operational
amplifiers, as controlled by the external feedback cir-
cuitry. The particular operational amplifier parameters
will be discussed as they effect the circuit performance
and accuracy.

The integrated operational amplifiers shown in the fig- Figure 1. Inverting Amplifier
ures are for the most part internally compensated, so
frequency stabilization components are not shown:
however, other amplifiers using external compensation In high source resistance applications, offset voltage at
may be utilized to achieve greater operating speed in the amplifier output may be adjusted by adjusting the
many circuits. value of R3 and using the variation in voltage drop
across it as an input offset voltage trim.
The Inverting Amplifier
Offset voltage at the amplifier output is not as important
The basic operational amplifier circuit is shown in Fig- in AC coupled applications. Here the only consideration
ure 1. This circuit gives closed-loop gain of R2/R1 when is that any offset voltage at the output reduces the
this ratio is small compared with the amplifier open- peak-to-peak linear output swing of the amplifier.
loop gain and, as the name implies, is an inverting cir-
cuit. The input impedance is equal to R1. The closed- The gain-frequency characteristic of the amplifier and
loop bandwidth is equal to the unity-gain frequency di- its feedback network must be such that oscillation does
vided by one plus the closed-loop gain. not occur. To meet this condition, the phase shift
through amplifier and feedback network must never ex-
The only cautions to be observed are that R3 should be ceed 180 0 for any frequency where the combined gain
chosen to be equal to the parallel combination of R1 of the amplifier and its feedback network is greater than
and R2 to minimize the offset voltage error due to bias unity. In practical applications, the phase shift should
current; and that there will be a DC offset voltage error not approach 180 0 since this is the situation of condi-
due to bias current; and that there will be a DC offset tional stability. Obviously, the most critical case occurs
voltage at the amplifier output equal to closed-loop gain when the attenuation of the feedback network is zero.
times the offset voltage at the amplifier input.
Amplifiers which are not internally compensated may
Offset voltage at the input of an operational amplifier is be used to achieve increased performance in circuits
comprised of two components, these components are where feedback network attenuation is high, Le., the
identified in specifying the amplifier as input offset volt- amount of feedback around the amplifier is low. The
age and input bias current. The input offset voltage is compensation trade-off for a particular connection is
fixed for a particular amplifier; however, the contribu- stability versus bandwidth. Larger values of compensa-
tion due to input bias current is dependent on the cir- tion capaCitor yield greater stability and lower band-
cuit configuration used. For minimum offset voltage at width and vice versa.

5-4
The Non-Inverting Amplifier The cautions to be observed in applying this circuit are
as follows: the amplifier must be compensated for
Figure 2 shows a high input impedance non-inverting unity-gain operation, and the output swing of the ampli-
circuit. This circuit gives a closed-loop gain equal to the fier may be limited by the amplifier common-mode
ratio of (R1 + R2) to R1. Its closed-loop 3-dB bandwidth range. The input signal swing should not exceed the in-
is equal to the amplifier unity-gain frequency divided by put common-mode range, since this may cause a latch-
the closed-loop gain. up condition.

VOUT

VOUT" VIN

Figure 3. Unity-Gain Buffer

Summing Amplifier
The summing amplifier, a special case of the inverting
amplifier, is shown in Figure 4. The circuit gives an in-

•
verted output which is equal to the weighted algebraic
sum of all three inputs. The gain of any input of this cir-
Figure 2. Non-Inverting Amplifier cuit is equal to the inverse ratio of the appropriate input
resistor to the feedback resistor, R4. Amplifier band-
width may be calculated as in the inverting amplifier
The primary differences between this connection and shown in Figure 1 by assuming the input resistor to be
the inverting circuit are that the output is not inverted
the parallel combination of R1, R2, and R3. Application
and that the input impedance is very high and is equal cautions are the same as those for the inverting amplifi-
to the differential input impedance multiplied by loop er. If an uncompensated amplifier is used, compensa-
gain (open-loop gain/closed-loop gain). In DC coupled tion is calculated on the basis of this bandwidth as is
applications, input impedance is not as important as in- discussed in the section describing the simple inverting
put current and its voltage drop across the source re- amplifier.
sistance. To minimize the output error due to the input
bias current of the operational amplifier, (R1 + R2)
should be chosen equal to the source impedance of the
input signal. Applications cautions are the same for this
amplifier as for the inverting amplifier with one excep-
tion: the amplifier output will go into saturation if the in-
put is allowed to float. This may be important if the am-
plifier must be switched from source to source. The
compensation trade off discussed for the inverting am-
plifier is also valid for this connection.
VOUT

The Unity-Gain Buffer

The unity-gain buffer is shown in Figure 3. The circuit
gives the highest input impedance of any operational
amplifier circuit. Input impedance is equal to the differ-
ential input impedance multiplied by the open-loop
gain, in parallel with common mode input impedance.
The gain error of this circuit is equal to the reciprocal of
the amplifier open-loop gain or to the common-mode re- Figure 4. Summing Amplifier
jection, whichever is less. Input impedance is a mis-
leading concept in a DC coupled unity-gain buffer. Bias
The advantage of this circuit is that there is no interac-
current for the amplifier will be supplied by the source tion between inputs, therefore, operations such as sum-
resistance and will cause an error at the amplifier input ming and weighted-averaging are implemented very
due to its voltage drop across the source resistance.
easily.

5-5
The Difference Amplifier tion of two additional components, R1 and C2. R2 and
C2 form a 6 dB per octave high frequency roll-off in the
The difference amplifier is the complement of the sum- feedback network, and R1C1 form a 6 dB per octave
ming amplifier and allows the subtraction of two volt- roll-off network in the input network for a total high fre-
ages or, as a special case, the cancellation of a single quency roll-off of 12 dB per octave, to reduce the effect
common to the two inputs. This circuit is shown in Fig- of high frequency input and amplifier noise. In addition
ure 5 and is useful as a computational amplifier, in mak- R1C1 and R2C2 form lead networks in the feedback
ing a differential to single-ended conversion, or in re- loop which, if placed below the amplifier unity-gain fre-
jecting an unwanted common-mode signal. quency, provide 90 0 phase lead to compensate the 90 0
phase lag of R2C1 and prevent loop instability.

VINo----i
C1

VOUT

Figure 5. Difference Amplifier Figure 6. Basic Differentiator Connection

Circuit bandwidth may be calculated in the same man-

ner as for the inverting amplifier, but input impedance is
somewhat more complicated. Input impedance for the
two inputs is not necessarily equal: inverting input im-
pedance is the same as for the inverting amplifier of
Figure 1 and the noninverting input impedance is the
sum of R3 and R4. Gain for either input is the ratio of R1
to R2 for the special case of a differential input single-
ended output where R1 = R3 and R2 = R4. The gen-
eral expression for gain is given in the figure. Compen-
sation should be chosen on the basis of amplifier band-
width.

Care must be exercised in applying this circuit since in- fC=_1-

put impedances are not equal for minimum bias current 21TR1C1
error.
f --,----,-
h - 21TR2c1 - 21TR2C2
Differentiator Circuit
The basic principle of a differentiator circuit is shown in Figure 7. Practical Differentiator Circuit
the simplified connection diagram of Figure 6. How-
ever, although mathematically accurate, this particular
connection is not directly useful in practice because it Integrator Circuit
is extremely susceptible to high frequency noise since
AC gain increases at the rate of 6 dB per octave. In ad- Figure 8 shows the basic circuit connection for per-
dition, the feedback network of the differentiator made forming the mathematical operation of integration. This.
up of the resistor R3 and the capacitor C3 is an RC low circuit is essentially a low-pass filter with a constant
pass filter which contributes 90 0 phase shift to the loop frequency roll-off of - 6 dB per octave.
and may cause stability pioblems even with an ampiifi-
The circuit must be provided with an external method of
er which is compensated for unity-gain.
establishing initial conditions. This is shown in the fig-
ure as the double-pole, single-throw switch S1. When
A practical differentiator which corrects the high fre- S1 is in position 1, the amplifier is connected in unity-
quency noise problem is shown in Figure 7. Here both gain configuration, and capacitor C1 is discharged, set-
the stability and noise problems are corrected by addi- ting an initial condition of zero volts. When S1 is in posi-

5·6
tion 2, the amplifier is connected as an integrator, and
its output will be the time·integral of the input voltage.

r - - - - - - - - I S'B
I I
I I 2
I
I
I
I VOUT
I
s'AI

fL - -'-
- 2rrA,C,

fC=-'-
2rrA3C,

Av=-~
A,

Figure 9. A Simple Low-Pass Filter Circuit

Figure 8. The Integrator Circuit

The cautions to be observed with this circuit are two:

the amplifier used should generally be stabilized for
60
unity·gain operation and R2 must equal R1 for minimum

•
error due to bias current.
R3
-='00
R,
Simple Low-Pass Filter fe
40
The simple low·pass filter is shown in Figure 9. This cir·
cuit has a 6 dB per octave roll·off after a closed·loop
3·dB point defined by fC. Gain below this corner fre· co
:s 20
quency is defined by the ratio of R3 to Rl. The circuit 2
may be considered as an AC integrator at frequencies
well above fC; however, the time domain response is
«
(!)

that of a single RC rather than an integral.

0
A gain vs. frequency plot of circuit response is shown in
Figure 10 to illustrate the difference between this cir·
cuit and the true integrator. Note that the frequency re-
sponse is flat for frequencies below fC
-2o~----~--------h------4--------
0-1 10 100 1000
where fC = __
1_
211" R3C1 Normalized Frequency. fIfe

Current-to-Voltage Converter Figure 10. Frequency Response of the Simple Low-Pass

Current may be measured in two ways with an opera- Filter
tional amplifier: the current may be converted into a
voltage with a resistor and then amplified or it may be
injected directly into a summing node. Converting into
voltage is undesirable for two reasons: first, an imped-
ance is inserted into the measuring line causing an er·
ror; second, amplifier offset voltage is also amplified scale factor of this circuit is R1 volts per ampere of cur·
with a subsequent loss of accuracy. The use of a rent. The only conversion error in this circuit is the bias
current-to-voltage converter avoids both of these prob- current of the operational amplifier input which is
lems. summed algebraically with the input current, liN. The
main design constraints are that scale factors must be
The current·to-voltage converter is shown in Figure 11. chosen to minimize errors due to bias current and since
The input current is fed directly into the summing note, voltage gain and source impedance are often indeter-
and the amplifier output voltage changes to extract the minate (as with photocells) the amplifier must be com·
same current from the summing node through R1. The pensated for unity·gain operation.

5-7
 RI V+

10 J Al

-liN

+
VOUT

Vour = -lIN Al
1- "::"
V,N

':'

Figure 11. Operational Amplifier as a Current-to-Voltage

Converter

Voltage Controlled Current-Source

Figures 12, 13, and 14 show three simple circuit config· Figure 13. Voltage-Controlled Current-Source Circuit
urations for voltage-controlled constant-current stages.
The circuit of Figure 12 is a basic current-sink circuit
which uses a pair of Darlington connected NPN transis- Figure 14 shows an alternate approach to obtaining a
tors external to the operational amplifier. Assuming that voltage-controlled current source which does not re-
the base current of T 1 is negligible compared to the quire additional active devices. The circuit provides an
controlled current la, the current of the output transis- output current proportional to the input voltage VIN. If
tors is equal to VIN/R1. the resistors R1 through R4 are chosen to be equal and
much larger than R5, then the output current is:

The above expression assumes that the current

through R3 is much smaller than 10.

R4

Figure 14. A Voltage-Controlled Current Source Circuit

Which Does Not Require External Active Devices

Figure 12. Voltage-Controlled Current-Sink Circuit

This circuit can supply an output current of either polar-
Figure 13 shows a current-source circuit which uses a ity, up to the maximum positive or negative output cur-
composite connection of external PNP and NPN tran- rent available from the operational amplifier. The maxi-
sistors and produces a constant output current which is mum voltage compliance of the output is limited by the
proportional to the net voltage drop across the sensing output swing of the operational amplifier minus the volt-
resistor, R1. age drop across the sensing resistor, R5.

5-8
Triangle Wave Oscillator state until the voltage at its input again reverses. The
complete circuit operation may be understood by exam-
A constant amplitude triangular wave generator is ining the operation with the output of the threshold de-
shown in Figure 15. This circuit provides a variable fre- tector in the positive state. The detector positive satura-
quency triangular wave whose amplitude is indepen- tion voltage is applied to the integrator summing junc-
dent of frequency. This entire circuit can be built inex- tion through the combination R3 and R4 causing the
pensively, using a dual operational amplifier IC, such as current IA to flow.
the XR-4558.

INTEGRATOR The integrator then generates a negative-going ramp

C1 with a rate of IA/C1 volts per second until its output
equals the negative trip point of the threshold detector.
The threshold detector then changes to the negative
output state, and supplies a negative current, 'B, at the
integrator summing point. The integrator now generates
a positive-going ramp with a rate of IB/C1 volts per sec-
ond until its output equals the positive trip point of the
threshold detector, where the detector again changes
output state and the cycle repeats.

Triangular wave frequency is determined by R3, R4 and

8.2K C1 and the positive and negative saturation voltages of
the amplifier A1. Amplitude is determined by the ratio of
Figure 15. A Simple Triangle Wave Oscillator R5 to the combination of R1 and R2 and the threshold
detector saturation voltages. Positive and negative
ramp rates are equal and positive and negative peaks
The generator embodies an integrator as a ramp gener-
are equal if the detector has equal positive and nega-
ator and a threshold detector with hysteresis as a reset
tive saturation voltages. The output waveform may be

•
circuit. The integrator has been described in a previous
offset with respect to ground if the inverting input of the
section and requires no further explanation. The thresh-
threshold detector, A1, is offset with respect to ground.
old detector is similar to a Schmitt trigger in that it is a
latch circuit with a large dead zone. This function is im-
The generator may be made independent of tempera-
plemented by using positive feedback around an opera-
ture and supply voltage if the detector is clamped with
tional amplifier. When the amplifier output is in either matched zener diodes.
the positive or negative saturated state, the positive
feedback network provides a voltage at the non- The integrator section should be compensated for
inverting input which is determined by the attenuation unity-gain. The detector section may require compen-
of the feedback loop and the saturation voltage of the sation if power supply impedance causes oscillation
amplifier. To cause the amplifier to change states, the during its transition time. The current into the integrator
voltage at the input of the amplifier must be caused to should be large with respect to the input bias current
change polarity by an amount in excess of the amplifier for maximum symmetry; and offset voltage should be
input offset voltage. When this is done, the amplifier small with respect to peak output voltage swing.
saturates in the oppOSite direction and remains in that

5-9
Choosing the Right Op Amp
Because of its versatility and ease of application, the they can be operated with a single positive supply, and
op-amp is often the easiest active component to design still be able to detect or sense small Signals near
into the circuit. However, once the initial "paper de- ground potential. The particular circuit recommended
sign" is accomplished, the user is faced with the key for this application is Exar's XR-3403 quad operational
question: which op-amp is the best choice for the par· amplifier.
ticular application? The availability of a very wide
choice of IC op-amps of varying part numbers, types Programmable Op-Amps
and features does not make the answer to this question
an easy one. If the op-amp characteristics are not care- Programmable op-amps allow the user to "program" or
fully considered, the total system performance may be set the operating current levels within the IC op-amp by
degraded: similarly if each op-amp is overspecified with means of an external setting resistor, and thus be able
an excessive amount of "overkill" for the particular ap- to trade-off power dissipation for slew-rate or Signal
plication, then the system cost will increase unneces- bandwidth. These circuits are normally available in
sarily. The key selection criteria is finding the lowest quad form, where the power levels of all or some of the
cost operational amplifier which will be sufficient to op-amps in the package can be programmed by one or
meet the system performance requirements. This sec- two external setting resistors. The key areas of applica-
tion provides a brief summary of vcy:ious classes of IC tions for programmable op-amps are active filters and
op-amps, their features and key ap~lications, to assist telecommunication channel filters where the user is
the user in choosing the most cost-effective operational normally concerned with power dissipation. These op-
amplifier for his application. amps can also be programmed to operate at micro-
power levels, by the choice of external setting resistors.
General Purpose Op-Amps
The programmable quad operational amplifiers are
A wide variety of op-amp applications such as low- available with either one or two separate setting con-
frequency amplifiers, active filters, voltage-to-current trols. Those with a Single setting control have all four of
converters and voltage regulators are most economi- the operational amplifiers programmed from same cur-
cally accomplished using the low-cost general purpose rent setting control. Those with two setting controls
IC op-amps. These op-amps are almost all variations of have the four op-amps on the chip programmed either
the basic 741-type op-amp, and offer significant cost in groups of two, or in groups of one and three op-amps.
savings over any special-purpose op-amps. They are The advantage of partitioned programming is that some
commercially available in single, dual or quad versions. of the op-amps in the IC package can be operated at a
The dual and quad op-amps are particularly cost- different power or bandwidth level than the rest of the
effective for applications such as active filters which re- op-amps in the same chip. For example, in an active fil-
quire a multiplicity of op-amps. The cost per op-amp is ter application, the three op-amps performing the filter-
usually lower if one can use multiple op-amp IC's rather ing can be operated at a low-power level, yet the fourth
than single op-amps. op-amp which may be serving as an output buffer can
be operated at a higher power level to provide load-
The single and dual general purpose op-amps are avail- drive capability.
able in both internally compensated and uncompensat-
ed versions. The quad op-amps are almost Invariably in- Exar offers the broadest product line of programmable
ternally compensated, to reduce the IC package pin op-amps in the industry: The XR-4202, XR-146 and the
count. Most general purpose IC op-amps have compa- XR-346-2 families of op-amps are all-bipolar program-
rable electrical characteristics, namely open loop gain mable quad op-amp circuits. The XR-4202 offers a sin-
of ~ 20 mVIV, small-signal unity gain bandwidth of 1 to gle current-setting control for all of the four op-amps on
2 MHz and a slew rate of =:: 1V/p.sec. the chip; the XR-146 and the XR-346-2 offer partitioned
programming of the four op amps. The XR-094 and
Exar manufactures a wide choice of dual or quad gen- XR-095 families are programmable FET-input quad op-
eral purpose op-amps. All of these op·amps are inter- amps which have the same pin configuration as the
nally compensated to make them cost-effective and re- XR-146 and the XR-346-2 families, respectively. These
duce the external parts count. Exar's general purpose programmable FET-input quad op-amps are fabricated
op-amps recommended for most applications are using Exar's ion-implanted bipolar/FET or BIFET pro-
XR-1458 and XR-4558 for duals, and XR-4136, XR-4212 cess technology which combines matched junction
and XR-4 7 41 for quad op-amps. FETs and high-performance bipolar transistors on the
same chip.
Ground Sensing Op-Amps
FET-Input Op-Amps
These types of op-amps have an input stage common-
mode range which extends all the way to the negative Finite input impedance or input bias currents associ-
supply rail. This is obtained by using Darlington- ated with conventional bipolar op-amps can be a prob-
connected PNP transistors at the input stage of the op- lem in specific applications such as sample-hold cir-
amp. The key advantage of this class of op-amps is that cuits or signal sensing applications from high-

5-10
impedance signal source such as transducer systems. low noise characteristics than the FET-input op-amps.
For such applications, op-amps with junction-FET input Exar manufactures a number of low noise op-amp cir-
stages offer significant performance advantages since cuits uniquely suited to audio applications. Among Ex-
they offer input resistances of the order of 10 12 ohms, ar's family of low noise op-amps, the XR-5534 opera-
and input bias currents in the low pico-ampere range. tional amplifier, and its dual versions, the XR-5532 and
Another unique feature of FET-input op-amps is their the XR-5533 offer the best noise performance.
high slew-rate and wide bandwidth. For example, most
FET-input op-amps offer slew-rates in excess of 10
V/p.sec and unity gain bandwidth of 3 MHz. Low Distortion Op-Amps
The FET-input op-amps offer somewhat higher offset In addition to low noise characteristics, another key
voltages and input noise than all-bipolar op-amps. performance requirement for audio applications is low
distortion. The distortion characteristics of op-amps are
Exar offers a wide selection of FET-input dual and quad normally determined by the design of the output stage
op-amps which are manufactured using Exar's ion- as well as the amplifier bandwidth characteristics. The
implanted BIPOLAR/FET process. The XR-082/XR-083 total harmonic distortion (THO) is made up of three
are dual op-amps; the XR-084 is a quad FET-input op- components: (a) intermodulation distortion; (b) cross-
amp. The XR-094 and the XR-095 are programmable over distortion which depends on output stage design,
quad FET-input op-amps. Because of their low power and (c) slew-induced distortion which occurs when the
capability, the programmable JFET op-amps are partic- output of the op-amp is forced to slew faster than its
ularly suitable for low-power active filter designs. slew-rate.
Low Noise Op-Amps
The cross-over distortion can be avoided by using op-
These op-amps are particularly suited for audio amplifi- amps which have class-AB, rather than class-B type
er and mixer applications, where low noise is of prime output stages. All of Exar's op-amps fall into this cate-
importance. The noise characteristics of an op-amp are gory.
determined by the noise generated at the input stage,
since the noise generated at this point is amplified by To avoid slew-induced distortion, one should ensure •
the full open-loop gain of the a.!!lPlifier. In most cases, that the slew rate of the amplifier is never exceeded
input noise voltages of 10 nV/vHz or less is required to during the excursions of the input signal. The high-
be suitable for high quality or professional audio signal speed operational amplifiers such as Exar's XR-5533 or
processing applications. Such low noise characteris- XR-5534 op-amps which have slew rates in excess of
tics are normally obtained by careful device design and 10 V/p.sec with a power bandwidth of 200 kHz can easi-
manufacturing processing of the Ie chips. In general, ly cover the entire audio frequency range without intro-
all-bipolar operational amplifiers tend to have better ducing slew-induced distortion.

5-11
 XR-082/083

Dual Bipolar J FET Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS
The XR-082/XR-083 family of dual bipolar JFET opera-
tional amplifiers are designed to offer higher perform-
ance than conventional bipolar op amps. Each amplifier XA·082
features high slew rate, low input bias and offset cur-
rents, and low offset voltage drift with temperature. +Vcc
These operational amplifier circuits are fabricated us-
ing ion-implantation technology which combines well-
matched junction JFETs and high-performance bipolar
OUTPUT B
transistors on the same monolithic chip.

The XR-082 of family of dual bipolar JFET op amps are

packaged in 8-pin dual-in-line packages. The XR-083 -INPUT B
family of op amps offer independent offset adjustment
for each of the individual op amps on the same chip,
and are available in 14-pin dual-in-line packages.
+INPUT B

FEATURES
Direct Replacement for TL082ITL083
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short Circuit Protection
OFFSET
High Input Impedance .. JFET Input Stage -INPUT A
NULL A
Internal Frequency Compensation
Latch-Up-Free Operation
+INPUT A +Vee
High Slew Rate .. 13 V/p.s, Typical

OFFSET
APPLICATIONS NULL A
OUTPUT A

Buffer Amplifiers
Summing/Differencing Amplifiers -VEE Ne
Instrumentation Amplifiers
Active Filters
OFFSET OUTPUT B
Signal Processing NULL B
Sample and Differencing
I to V Converters +INPUT B -Vee
Integrators
Simulated Components OFFSET
Analog Computers -INPUT B
NULL B

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ±18V
Differential Input Voltage ±30V
Input Voltage Range (Note 1) ±15V ORDERING INFORMATION
Output Short Circuit Duration (Note 2) Indefinite
Package Power DisSipation: Part Number Package Operating Temperature
Plastic Package 625 mW XR-082M/XR-083M Ceramic - 55°C to + 125°C
Derate Above TA = + 25°C 5.0 mWoC XR·082N/XR-083N Ceramic - 25°C to + 85°C
Ceramic Package 750 mW XR·082P/XR-083P Plastic - 25°C to + 85°C
Derate Above TA = + 25°C 6.0 mW/oC XR·082CN/XR·083CN Ceramic O°C to + 70°C
Storage Temperature Range -65°C to + 150°C XR·082CP/XR-083CP Plastic O°C to + 70°C

5-12
 XR·082/083
ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = ± 15V, unless otherwise specified.
XR·082MI XR·0821 XR·082CI
XR·083M XR·083 XR·083C
SYMBOL PARAMETERS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
VOS Input Offset Voltage 3 6 3 6 5 15 mV RS = 500
VOS 9 9 20 mV RS = 500,
TA = Full Range
I1VOS/I1T Offset Voltage 10 10 10 p.V/oC RS = 500,
Temp. Coet. TA = Full Range
IB Input Bias Current 30 200 30 200 30 400 pA
IB Input Bias Current 50 20 20 nA TA = Full Range
Over Temp.
lOS Input Offset Current 5 100 5 100 5 200 pA
Input Offset Current 20 10 5 nA TA = Full Range
Over Temp.
ICC Supply Current 1.4 2.8 1.4 2.8 1.4 2.8 mA No Load,
(per amplifier) No Input Signal
ViCM Input Common Mode ±12 ±12 ±10 V

•
Range
AVOL Voltage Gain 50 200 50 200 25 200 V/mV RL ~ 2 kO,
VO=±10V
25 25 15 TA = Full Range
VOpp Max. Output Swing 24 27 24 27 24 27 V RL ~ 10 kO
(peak-to-peak) 24 24 24 TA = Full Range

R'N Input Resistance 10 12 10 12 10 12 0

BW Unity-Gain Bandwidth 3 3 3 MHz
Ct.iiRR Common-Mode 80 86 80 86 70 76 dB RS :s 10 kO
Rejection
PSRR Supply-Voltage 80 86 80 86 70 76 dB
Rejection
Channel Separation 120 120 120 dB AV = 100,
Freq. = 1 kHz
dVOUT/DT Slew Rate 13 13 13 V/p.S AV = 1,
RL = 2 kO
CL = 100 pF,
V1 = 10V
TR Rise Time 0.1 0.1 0.1 p'sec AV = 1,
RL = 2 kO
TO Overshoot 10 10 10 % CL = 100 pF,
V1 = 20 mV
EN Equivalent Input 20 20 20 nV/..JRz RS = 1000
Noise Voltage f = 1 kHz

Note 1: For Supply Voltage less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be
limited to ensure that the dissipation rating is not exceeded.

5·13
XR·082/083
+Vcc o-------------~------------------~----------~--------~--------~----__,

NON'INVE~~~~ 0--------------+----------------...,
INVERTING
INPUT 0--_41+-' 12811
.....~w"v---+------i-o OUTPUT

r-
I
I
I
-VEE O-~----~--------~------~~~~----------~----------~--------~------*_~
6 6
OFFSET NULL OFFSET NULL
(N1)' (N2)'

• AVAILABLE IN XR·083 ONLY. (ONE CHANNEL ONLY)

EQUIVALENT SCHEMATIC DIAGRAM

5-14
 XR-084

Quad Bipolar J FET Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-084 quad bipolar JFET operational amplifier is
designed to offer higher performance than convention-
OUTPUT A OUTPUT 0
al bipolar quad op amps. Each of the four op amps on
the chip is closely matched in performance character-
istics, and each amplifier features high slew rate, low -INPUT A -INPUT 0

input bias and offset currents, and low offset voltage

drift with temperature. The XR-084 JFET input quad op +INPUT A +INPUT 0
amp is fabricated using ion-implanted bipolar JFET
technology which combines well-matched JFETs and
+Vee -VEE
high-performance bipolar transistors on the same mon-
olithic integrated circuit.
+INPUT B +INPUT e

FEATURES
-INPUT B -INPUT e
Direct Replacement for TL084

•
Same Pin Configuration as XR-3403, LM324 OUTPUT B OUTPUT e
High-Impedance JFET Input Stage
Internal Frequency Compensation
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short Circuit Protection
Latch-Up-Free Operation
High Slew Rate ... 13 V/p,S, Typical

APPLICATIONS
Buffer Amplifiers ORDERING INFORMATION
Summing/Differencing Amplifiers
Instrumentation Amplifiers Part Number Package Operating Temperature
Active Filters XR-084M Ceramic -55°C to + 125°C
Signal Processing XR-084N Ceramic - 25°C to + 85°C
Sample and Differencing XR-084P Plastic - 25°C to + 85°C
I to V Converters XR-084CN Ceramic O°C to + 70°C
Integrators XR-084CP Plastic O°C to + 70°C
Simulated Components
Analog Computers

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ± 18V
Differential Input Voltage ±30V
Input Voltage Range (Note 1) ±15V
Output Short Circuit Duration (Note 2) Indefinite SYSTEM DESCRIPTION
Package Power Dissipation:
The XR-084 is a quad JFET input operational amplifier
Plastic Package 625mW
featuring extremely high input resistance, low input bi-
Derate Above TA = + 25°C 5.0 mW/oC
as and offset currents, large common mode Yoltage
Ceramic Package 750 mW
6.0 mW/oC range, and large output swing range. Unity gain band-
Derate Above TA = +25°C
width is 3 MHz and slew rate is 13V/p,S. The devices are
Storage Temperature Range - 65°C to + 150°C
unity gain compensated.

5-15
XR·084
ELECTRICAL CHARACTERISTICS TA = 25°e, Vee ± 15, unless otherwise specified.

XR-084M XR-084 XR-084C

SYMBOL PARAMETERS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
VOS Input Offset Voltage 3 6 3 6 5 15 mV RS ., 500
Vas 9 9 20 mV RS ., 500,
TA '" Full Range
AVOS/AT Offset Voltage 10 10 10 p.V/oC RS '" 500,
Temp. Coel. TA '" Full Range

IB Input Bias Current 30 200 30 200 30 400 pA

IB Input Bias Current 50 20 20 nA TA '" Full Range

Over Temp.

lOS Input Offset Current 5 100 5 100 5 200 pA

Input Offset Current 20 10 5 nA TA '" Full Range
Over Temp.

ICC Supply Current 1.4 2.8 1.4 2.8 1.4 2.8 mA No Load.
(per amplilier) No Input Signal

VICM Input Common Mode ±12 ±12 ±10 V

Range

.tvOL Voltage Gain 50 200 50 200 25 200 V/mV RL ~ 2 kO,

Va., ±10V
25 25 15 TA ., Full Range

VOPP Max. Output Swing 24 27 24 27 24 27 V RL ~ 10 kO

(peak·to·peak) 24 24 24 TA = Full Range

RIN Input Resistance 1012 1012 10 12 0

I
BW Unity-Gain Bandwidth 3 3 3 MHz
CMRR Common-Mode 80 86 80 86 70 76 dB RS s 10 kO
Rejection
PSRR Supply-Voltage 80 86 80 86 70 76 dB
Rejection
Channel Separation 120 120 120 dB .tv = 100,
Freq. = 1 kHz

DVOUTIDT Slew Rate 13 13 13 V/p.S .tv = 1,

RL = 2 kO
CL = 100 pF,
V1 = 10V

TR Rise Time 0.1 0.1 0.1 p'sec .tv = 1,

RL = 2 kO
TO Overshoot 10 10 10 % CL = 100 pF,
V 1 = 20 mV

EN Equivalent Input 20 20 20 nV/..JHz RS = 1000

Noise Voltage 1= 1 kHz

Nota 1: For Supply Voltage less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Nota 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating
is not exceeded.

-YEE; _ _-~-_"""-_4._"""" __""""___ +-_-+_-+~

EQUIVALENT SCHEMATIC DIAGRAM

5-16
 e".I1JR::
ll::IV4I, ' XR-094/095

Quad Programmable Bipolar J FET

Operational Amplifiers
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS
The XR-094 and XR-095 bipolar JFET input quad pro-
grammable operational amplifiers consist of four inde- OUTPUT A 1
pendent, high gain, internally compensated amplifiers.
Two external resistors (RSET) allow the user to program -INPUT A 2 -INPUT 0
supply current, slew-rate, and input noise without the usual +INPUT A 3 +INPUT 0
sacrifice of gain bandwidth product. For example, the
user can trade-off slew-rate for supply current or opti- -VEE
mize the noise figure for a given source impedance. Ex-
+INPUT B 5 +INPUT C
cept for the two programming pins at the end of the
package, the XR-094 8,nd XR-095 pin-out is the same as
the popular 324, 3403, 124, 148 and 4741 operational
OUTPUT B 7 OUTPUT C
amplifiers.

In the case of the XR-094, three of the op amps on the

chip share a common programming pin; and the fourth
op amp is programmed separately. In the case of the
XR-095, each pair of op amps share a common pro-
gramming pin.

FEATURES
Same Pin Configuration as LM-346 +INPUT C
High-Impedance FET Input Stage
Internal Frequency Compensation -INPUT C
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short-Circuit Protection
High Slew-Rate ... 13 V/pos, Typical
Programmable Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS (Continued)
APPLICATIONS Derate Above TA = + 25°C 5.0 mV/oC
Ceramic Package 750 mW
Total Supply Current = 5.6 mA (lSET/320 poA) Derate Above TA = + 25°C 6.0 mW/oC
Slew Rate = 13 V/pos (lSET/320 poA) Storage Temperature Range - 65°C to + 150°C
ISET = Current into set terminal
Note 1: For Supply Voltage less than ± 15V, the absolute maxi-
VCC - (VEE - 0.6V) mum input voltage is equal to the supply voltage.
ISET = RSET
Note 2: The output may be shorted to ground or to either sup-
Note. ISET must be s 400poA ply. Temperature and/or supply voltages must be lim-
ited to ensure that the dissipation rating is not exceed-
ed.
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Supply Voltage ±18V
Differential Input Voltage ±30V Part Number Package Operating Temperature
Input Voltage Range (Note 1) ±15V XR-094/XR-095N Ceramic - 25°C to + 85°C
Output Short-Circuit Duration (Note 2) Indefinite XR-094/XR-095P Plastic - 25°C to + 85°C
Package Power Dissipation: XR-094/XR-095CN Ceramic O°C to + 70°C
Plastic Package 625 mW XR-094/XR-095CP Plastic O°C to + 70°C

5-17
XR·094/095
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = ± 15V, unless otherwise specified.
ISET = 320 p.A.

XR-094/095 XR-094/095C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOL CONDITIONS
Input Offset Voltage 3 6 5 15 mV VOS RS = 500, TA = 25°C
9 20 mV VOS RS = 500, TA = Full Range
Offset Voltage 10 10 p.V/oC AVOS/AT RS = 500, TA = Full Range
Temp. Coet.
Input Bias Current IB
80 600 80 800 pA TA = 25°C
20 20 nA TA = Full Range
Input Offset Current lOS
40 300 40 500 pA TA = 25°C
10 5 nA TA = Full Range
Supply Current 1.4 2.8 1.4 2.8 mA ICC No Load, No Input Signal
(per amplifier)
Input Common Mode ±12 ±10 V ViCM
Range
Voltage Gain V/mV RL ~ 2KO, Vo = ±10V
50 200 25 200 AVOL TA = 25°C
25 15 TA = Full Range
Max. Output Swing RL ~ 10 KO
(peak-to-peak) 24 27 24 27 V VOpp TA = 25°C
24 24 TA = Full Range
Input Resistance 1012 1012 0 Rin TA = 25°C
Unity-Gain Bandwidth 3 3 MHz BW TA = 25°C
Common-Mode Rejection 80 86 70 76 dB CMRR RS s 10 KO
Supply-Voltage Rejection 80 86 70 76 dB PSRR
Channel Separation 120 120 dB AV = 100, Freq. = 1 kHz
Slew Rate 13 13 V/p.S dVout/dt AV = 1, RL = 2 KO
CL = 100 pF, V1 = 10V
Rise Time 0.1 0.1 p'sec tr AV = 1, RL = 2 KO
Overshoot 10 10 % to CL = 100 pF, V1 = 20 mV
Equivalent Input 18 18 nV/...[Rz en RS = 1000
Noise Voltage f = 1 kHz

(One Channel Only)

EQUIVALENT SCHEMATIC DIAGRAM

5-18
 Z!' EX4R XR-096

Quad Programmable Bipolar J FET

Operational Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XA-096 monolithic circuit contains four indepen-
dently programmable JFET operational amplifiers in a
single IC package. Each of the four op amp sections on seT A SET 0
the chip has its own external bias terminal; thus its per-
formance characteristics and power dissipation can be OUTPUT A OUTPUTO
independently controlled, without effecting the other op
amp sections on the chip. The respective bias-setting
-INPUT A -INPUT 0
resisters, RSETt connected to the programming termi-
nals of the circuit allow one to trade-off power dissipa-
-INPUT A -INPUT 0
tion for slew-rate, without sacrificing the gain-
bandwidth product of the circuit. These individual bias
terminals can also be used to switch the op amp sec- -Vee -Vee
tions "on" and "off", and thus, multiplex between vari-

•
ous op amp channels on the same chip. -INPUT B -INPUT 0

FEATURES -INPUT B -INPUT e

Programmable Version of XR-084

Independent Programming of All Four Op Amps OUTPUT B OUTPUT C
Programmable for Micropower Operation
High-Impedance JFET Input Stage
SET B SET e
Internal Frequency Compensation
Low Input Bias and Offset Currents

APPLICATIONS
Total Supply Current = 5.6 mA (ISET/320 p.A)
ORDERING INFORMATION
Slew-Rate = 13 V//LS (ISET/320 p.A)
ISET = Current into set terminal Part Number Package Operating Temperature
VCC - (VEE - 0.6V) XR-096N Ceramic - 25°C to + 85°C
ISET = --=-=---=---
ASET XA-096P Plastic - 25°e to + 85°C
XR-096CN Ceramic O°C to + 70 0 e
Note. ISET must be s 400/LA
XR-096CP Plastic O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ±18V
Differential Input Voltage ±30V SYSTEM DESCRIPTION
Input Voltage Range (Note 1) ±15V
Output Short-Circuit Duration (Note 2) Indefinite The XA-096 is a quad independently programmable
Package Power Dissipation: JFET input operational amplifier featuring extremely
Plastic Package 625 mW high input resistance, low input bias and offset current,
Derate Above TA = +25°C 5.0 mV/oC large common mode voltage range, and large output
Ceramic Package 750 mW swing range. Unity gain bandwidth is 3 MHz, and slew
Derate Above TA = +25°C 6.0 mW/oC rate is 13V/p.S. The devices are unity gain compen-
Storage Temperature Range -65°C to + 150°C sated.
Note 1: For Supply Voltage less than ± 15V, the absolute maxi-
mum input voltage is equal to the supply voltage. Each of the form amplifiers may be independently
Note 2: The output may be shorted to ground or to either sup- "programmed"-rebiased-by connecting a resistor from
ply. Temperature and/or supply voltages must be lim- the bias adjust pin to the positive supply. Bias current
ited to ensure that the dissipation rating is not exceed- may range up to 400 /LA, thus affording the designer
ed. flexibility along the power consumption/speed curve.

5-19
XR·096
ElECTRICAL CHARACTERISTICS
TA ::::: 25°C, VCC ::::: ± 15V, unless otherwise specified.
ISET ::::: 320 pA

XR-096 XR-096C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOL CONDITIONS
Input Offset Voltage 3 6 5 15 mV VOS RS ::::: 500, TA ::::: 25°C
9 20 mV VOS RS ::::: 500, TA ::::: Full Range
Offset Voltage 10 10 p.V/oC AVOS/AT RS ::::: 500, TA ::::: Full Range
Temp. Coef.
Input Bias Current IB
80 600 80 800 pA TA ::::: 25°C
20 20 nA TA ::::: Full Range
Input Offset Current lOS
40 300 40 500 pA TA ::::: 25°C
10 5 nA TA ::::: Full Range
Supply Current 1.4 2.8 1.4 2.8 mA ICC No Load, No Input Signal
(per amplifier)
Input Common Mode ±12 ±10 V ViCM
Range
Voltage Gain V/mV RL ~ 2KO, Vo ::::: ±10V
50 200 25 200 AVOL TA ::::: 25°C
25 15 TA ::::: Full Range
Max. Output Swing RL ~ 10KO
(peak-to-peak) 24 27 24 27 V VOpp TA ::::: 25°C
24 24 TA ::::: Full Range
Input Resistance 1012 1012 0 Rin TA ::::: 25°C
Unity-Gain Bandwidth 3 3 MHz BW TA ::::: 25°C
Common-Mode Rejection 80 86 70 76 dB CMRR RS ::s; 10 KO
Supply-Voltage Rejection 80 86 70 76 dB PSRR
Channel Separation 120 120 dB AV 100, Freq. ::::: 1 kHz
Slew Rate 13 13 V/p.S dVout/dt AV ::::: 1, RL ::::: 2 KO
CL ::::: 100 pF, V1 ::::: 10V
Rise Time 0.1 0.1 p'sec tr AV ::::: 1, RL ::::: 2 KO
Overshoot 10 10 % to CL ::::: 100 pF, V1 ::::: 20 mV
Equivalent Input 18 18 nV/...(Rz en RS ::::: 1000
Noise Voltage f ::::: 1 kHz

.VII
(ani Chlnn,1 Only) IIU_n"",

EQUIVALENT SCHEMATIC DIAGRAM

5-20
 XR-146/246/346

Programmable Quad Operational Amplifiers

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS
The XR-146 family of quad operational amplifiers con-
OUTPUT A OUTPUT D
tain four independent high-gain, low-power, program-
mable op-amps on a monolithic chip. The use of exter-
nal bias setting resistors permit the user to program -INPUT D
gain-bandwidth product, supply current, input bias cur-
rent, input offset current, input noise and the slew rate. +/NPUT 0

The basic XR-146 family of circuits offer partitioned -VEE

programming of the internal op-amps where one set-
ting resistor is used to set the bias levels in the three +INPUT C
op-amps, and a second bias setting is used for the re-
maining op-amp. Its modified version, the XR-346-2 pro- -INPUT C
vides a separate bias setting resistor for each of the OUTPUT C
two op-amp pairs.

FEATURES 'SET

•
Programmable
Micropower operation OUTPUT A OUTPUT 0
Low noise
Wide power supply range -INPUT A -INPUT 0
Class AB output
Ideal pin out for biquad active filters +/NPUT A +/NPUT 0
Overload protection for input and output
Internal frequency compensation -VEE
APPLICATIONS +INPUT B +INPUT C
Total Supply Current = 1.4 mA (lSET/1 0 pA) -INPUT B -INPUT C
Gain Bandwidth Product = 1 MHz (lSET/10pA)
Slew Rate = O.4V/ps (ISET/10 pA) OUTPUT B OUTPUT C
Input Bias Current == 50 nA (lSET/10 pA)
ISET = Current into pin 8, pin 9 (see schematic) 'SET 'SET
V+ -V- -0.6V
ISET = RSET

ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS (continued)

Supply Voltage
XR-146 ±22V Storage Temperature Range
XR-246/346 ±18V XR-146/246/346
Differential Input Voltage (Note 1)
XR-146/246/346 ±30V
Common Mode Input Voltage (Note 1)
XR-146/246/346 ±15V ORDERING INFORMATION
Power Dissipation (Note 2)
XR-146 900 mW Part Number Package Operating Temperature
XR-246/346 500 mW XR-146M Ceramic - 55°C to + 125°C
Output Short Circuit Duration (Note 3) XR-246N Ceramic -25°C to +85°C
XR-146/246/346 Indefinite XR-246P Plastic -25°C to +85°C
Maximum Junction Temperature XR-3461
XR146 346-2CN Ceramic O°C to + 70°C
XR-246 XR-3461
XR-346 346-2CP Plastic O°C to + 70°C

5-21
XR·146/246/346
ELECTRICAL CHARACTERISTICS (TA = + 2SoC, Vs = ± 1SV, ISET = 10 IlA)
XR-146 XR·246/346
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
Input Offset Voltage 0.5 5 O.S 6 mV VCM = OV,
RS :s SOO
Input Offset Current 2 20 2 100 nA VCM = OV
Input Bias Current SO 100 50 250 nA VCM = OV
Supply Current (4 Op·Amps) 1.4 2.0 1.4 2.S rnA
Large Signal Voltage Gain 100 1000 50 1000 VlmV RL = 10 kO,
AVOUT = ±10V
Input CM Range ±13.5 ±14 ±13.5 ±14 V
CM Rejection Ratio 80 100 70 100 dB RS :s 10 kO
Power Supply Rejection Ratio 80 100 74 100 dB RS :s 10 kO
Output Voltage Swing ±12 ±14 ±12 ±14 V RL :s 10 kO
Short-Circuit Current S 20 30 S 20 30 mA
Gain Bandwidth Product 0.8 1.2 0.5 1.2 MHz
Phase Margin 60 60 Deg
Slew Rate 0.4 0.4 V/lls
Input Noise Voltage 28 28 nVI.JFiz f = 1 kHz
Channel Separation 120 120 dB RL = 10kO,
AVOUT = OV to + 12V
Input Resistance 1.0 1.0 MO
Input Capacitance 2.0 2.0 pF

The following specifications apply over the Maximum Operating Temperature Range
Input Offset Voltage 0.5 6 0.5 7.5 mV VCM = OV,
RS :s 500
Input Offset Current 2 25 2 100 nA VCM = OV
Input Bias Current SO 100 50 250 nA VCM = OV
Supply Current (4 Op·Amps) 1.5 2.0 1.5 2.S mA
Large Signal Voltage Gain SO 1000 25 1000 V/mV RL = 10 k~,
AVOUT = ± 10V
Input CM Range ±13.5 ±14 ±13.5 ±14 V
CM Rejection Ratio 70 100 70 100 dB RS :s 500
Power Supply Rejection Ratio 76 100 74 100 dB RS :s 500
Output Voltage Swing ± 12 ±14 ±12 ±14 V RL ~ 10kO

ELECTRICAL CHARACTERISTICS (TA = 25°C, Vs = ± 15V, ISET = 1 IlA)

Input Offset Voltage 0.5 5 0.5 6 mV VCM = OV,
RS :s 500
Input Bias Current 7.5 20 7.5 100 nA VCM = OV
Supply Current (4 Op·Amps) 140 250 140 300 IlA
Gain Bandwidth Product 80 100 50 100 kHz

ELECTRICAL CHARACTERISTICS (TA = + 25°C, Vs = ± 1.5V, ISET = 10 IlA)

Input Offset Voltage 0.5 5 0.5 7 mV VCM = OV,
RS :s 500
Input CM Range ±0.7 ±0.7 V
CM Rejection Ratio 80 80 dB RS :s 500
Output Voltage Swing ±0.6 ±0.6 V RL ~ 10 kO

5-22
 XR·146/246/346
EQUIVALENT SCHEMATIC DIAGRAM
(One Channel Only)

- - - t - - - - - . ' ' = .... ---r--

TYPICAL PERFORMANCE CHARACTERISTICS Open Loop Voltage Gain VI
Input Bias Current vs ISET Supply Current VI ISET ISET
,.......
Ik 10
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ISET"'AI ISET!..AI ISET !..AI

Glin Bandwidth Product VI

Slew Rate VI ISET ISET Phase Margin VI ISET
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Open Loop Voltage Gain Gain Bandwidth Product Slew Rate vs

VI Temperature VITemperature Temperature

140

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100

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TEM'ERATURE rCI TEMPERATURE I'CI TEMPERATURE lOCI

5-23
XR·146/246/346
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Input Noise Volta!!,! Vi Input Noile Current VI Power Supply Rejection
Frequency Frequency Ratio VI Frequency
1\0 no .---.--r---r--r---,--,
1111111
~
lDO
1m ~ 'I'~~ l~ u
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t- ' 'SU" lO.A ~ II
ZO ~ 0.4 20
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Common·Mode Rejection Power Supply Rejection

Input Offset Voltage VI ISET Ratio vs ISET Ratio VI ISET
I 120 ItO r-r-rnrn""-~'T"m"""""""'"",,""
-a
--
O.! ~
;:
! lDO a 100 1-~~1I-++~+l!-4cl:!tli~

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Input Bias Current vi

Output Voltage Swing vs Input Voltage Range VI Input Common·Mode
Supply Voltage Supply Voltage Voltage

~ 14
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Input Bias Current VI Input Offset Current Vi Supply Current VI

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T£MP£AATUA£ ('CI
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Note 1: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The maximum power dissipation for these devices must be derated at elevated temperatures and is
dictated by TjMAX, )OjA, and the ambient temperature, TA. The maximum available power dissipation at
any temperature is Pd = (TjMAX - TA)/8jA or the 25°C PdMAX, whichever is less.
Note 3: Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should be
simultaneously shorted as the maximum junction temperature will be exceeded.

5-24
 XR-1458/4558

Dual Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-1458/4558 is a pair of independent internally
compensated operational amplifiers on a single silicon
chip, each similar to the popular 741, but with a power
consumption less than one 741. Good thermal tracking
OUTPUT A Vee
and matched gain-bandwidth products make these Du-
al Op-amps useful for active filter applications.
-INPUT A OUTPUT B
FEATURES
Direct Pin-for-Pin Replacement for MC1458, RC4558, -INPUT A -INPUT !I

N5558
Low Power Consumption - 50 mW typo and _INPUT B
VEE
120mW max.
Short-Circuit Protection

•
Internal Frequency Compensation
No Latch-Up
Wide Common-Mode and Differential Voltage Ranges
Matched Gain-Bandwidth

APPLICATIONS
Buffer Amplifiers
SumminglDifferencing Amplifiers ORDERING INFORMATION
Instrumentation Amplifiers
Active Filters Part Number Package Operating Temperature
Signal Processing XR-1458CN Ceramic O°C to + 70°C
Sample and Differencing
XR-1458CP Plastic O°C to + 70°C
I to V Converters
XR-4558CN Ceramic O°C to + 70°C
Integrators XR-4558CP Plastic O°C to + 70°C
Simulated Components
Analog Computers

ABSOLUTE MAXIMUM RATINGS

Supply Voltage
XR-4558CP ±18V
Input Voltage (Note 1) ±15V
Common Mode
Voltage Range VEE to VCC
Output Short-Circuit Duration (Note 2) indefinite
Differential Input Voltage ±30V
Internal Power Dissipation (Note 3) SYSTEM DESCRIPTION
Plastic Package: 500 mW
Storage Temperature Range: - 65°C to + 150°C The XR-1458 and XR-4558 are dual general purpose op
Operating Temperature Range: O°C to + 70°C amps featuring better performance than industry stan-
Note 1: For supply voltages less than ± 15V, the absolute max- dard devices such as the 741; bandwidth, slew rate,
imum input voltage is equal to the supply voltage.
and input resistance are greatly improved. Internal pro-
Note 2: Short circuit may be to ground or either supply. Rating
applies to + 125°C case temperature of + 75°C ambi- tection circuitry includes latch-up elimination, short cir-
ent temperature for XR1458/4558. cuit current limiting, and internal compensation.
Note 3: Rating applies for case temperatures to 125°C; derate
linearly at 6.5mW/oC for ambient temperatures above The two amplifiers are completely independent, shar-
+ 75°C for XR1458/4558. ing bias circuitry only.

5-25
 XR·1458/4558
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, ± 15V, unless otherwise specified.
XR1458/4558CP
PARAMETERS MIN TYP MAX UNITS SYMBOLS CONDITIONS
Input Offset Voltage 0.5 6.0 mV IViol Rs :s 10 KO
Input Offset Current 5 200 nA Iliol
Input Bias Current 40 500 nA IIbl
Input Resistance 0.3 5 MO Rin
Large Signal Voltage Gain 20 300 V/mV AVOL RL ;?; 2 KO
Vout = ± 10V
Output Voltage Swing ±12 ±14 V Vout RL ;?; 10 KO
±10 ±13 V Vout RL ;?; 2 KO
Input Voltage Range ±12 ±14 V ViCM
Common Mode Rejection Ratio 70 90 dB CMRR Rs :s 10 KO
Supply Voltage Rejection Ratio 30 150 p.VN PSRR Rs :s 10 KO
Power Consumption 50 170 mW Pi
Transient Response (unity gain) Yin = 20 mV
Risetime 0.13 P.s tr RL == 2 KO
Overshoot 5 % to CL :s 100 pF
Unity Gain Bandwidth 3.0 MHz BW
Slew Rate (unity gain) 1.0 V/p.s dVout/dt RL ;?; 2 KO
Channel Separation (open loop) 120 dB f = 10 kHz
Rs = 1 KO
(Gain of 100) 105 dB f = 10 kHz
Rs = 1 KO
The following specifications apply for O°C :S TA :S + 70°C for XR4558CP
Input Offset Voltage 7.5 mV IViol Rs :S 10 kO
Input Offset Current 300 nA lIiol
Input Bias Current 800 nA Ib
Large-Signal Voltage Gain 15 V/mV AVOL Rs ;?; 2 KO
Vout = ± 10V
Output Voltage Swing ±10 mV Vout RL 2: 2 KO
Power Consumption Vs = ± 15V
90 150 mW Pi TA = High
120 200 mW Pi TA = Low

EQUIVALENT SCHEMATIC DIAGRAM

5-26
 XR-3403/3503

Quad Operational Amplifiers

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-3403 and XR-3S03 are quad operational amplifi-
ers specifically designed for single supply operation. All
four amplifiers are similar in characteristics to industry
standard op amps like the 741. The XR-3403 is avail- OUTPUT A OUTPUT 0
able in both ceramic and plastic packages; the XR-
3S03 is available in a 14 pin ceramic package with
-INPUT A -INPUT 0
guaranteed performances across the military tempera-
ture range.
_INPUT A -INPUT 0

FEATURES
vee VEE
Short Circuit Protected Outputs
Class AB Output Stage for Minimal Crossover -INPUT B -INPUT e
Distortion
True Differential Input Stage

•
Single Supply Operation: 3.0 to 36 Volts -INPUT B -INPUT e
Split Supply Operation: ± 1.S to ± 18 Volts
Low Input Bias Currents: SOO nA Max OUTPUT B OUTPUT e
Four Amplifiers per Package
Internally Compensated
Similar Performance to Popular 741
Direct Pin-for-Pin Replacement for MC3403/3S03,
LM324 and RC4137

APPLICATIONS
Buffer Amplifiers
SummingIDifferencing Amplifiers ORDERING INFORMATION
Instrumentation Amplifiers
Active Filters Part Number Package Operating Temperature
Signal Processing
Sample and Differencing XR-3503M Ceramic - 55°C to + 125°C
I to V Converters XR-3403CN Ceramic O°C to + 70°C
Integrators XR-3403CP Plastic O°C to + 70°C
Simulated Components
Analog Computers

ABSOLUTE MAXIMUM RATINGS SYSTEM DESCRIPTION

Power Supply Voltages The XR-3403 is an array of four independent operation-
Single Supply 36V al amplifiers, each with true differential inputs. The de-
Split Supplies ±18V vice has electrical characteristics similar to the popu-
Input Differential Voltage Range with lar 741. However, the XR-3403 has several distinct ad-
Split Power Supply ±30V vantages over standard operational amplifier types in
Input Common Mode Voltage Range* ±1SV single supply applications. The XR-3403 can operate at
Package Power Dissipation: supply voltages as low as 3.0 volts or as high as 36
Plastic Package 625 mW volts with quiescent currents about one-fifty of those
Derate above TA = + 2SoC 5.0 mV/oC associated with the 741 \on a per amplifier basis). The
Ceramic Package 750 mW common mode input range includes the negative sup-
Derate above TA = +25°C 6.0 mW/oC ply, thereby eliminating the necessity for external bias-
Storage Temperature Range - 65°C to + 150°C ing components in many applications. The output volt-
"For Supply Voltage less than ± 15V, the absolute maximum in- age range also includes the negative power supply volt-
put voltage is equal to the supply voltage. age.
5-27
XR·3403/3503
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee::::: + 15V, VEE::::: 15V, TA + 25°e unless otherwise noted.
XR-3503M XR-3403C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS

Input Offset Voltage 2.0 5.0 2.0 10 mV

6.0 12 TA = Thigh to Tlow 1
Input Offset Current 30 50 30 50 nA
200 200 TA = Thigh to Tlow
Large Signal Open·Loop V/mV Vo = ±10V
Voltage Gain
50 200 20 200 RL = 2.0 KO
25 300 15 TA = ThightoTlow
Input Bias Current -200 -500 -200 -500 nA
-300 -1500 -BOO TA = Thigh to Tlow
Output Impedance 75 75 0 I = 20 Hz
Input Impedance 0.3 1.0 0.3 1.0 MO I = 20Hz
Output Voltage Swing ±12 ±13.5 ±12 ±13.5 V RL = 10 KO
±10 ±13 ±10 ±13 RL = 2.0 KO
±10 ±10 RL = 2.0 KO
TA = Thigh to Tlow
Input Common Mode Voltage + 13V,VEE + 13.5V·VEE + 13V,VEE + 13.5V,VEE V
Range
Common Mode Rejection 70 90 70 90 dB RS < 10 KO
Ratio
Power Supply Current 2.B 4.0 2.B 7.0 mA RL = 00
(Va = 0)
Individual Output ±20 ±30 ±45 ±10 ±20 ±45 mA
Short·Circuit Current 2
Positive Power Supply 30 150 30 150 p.VN
Rejection Ratio
Negative Power Supply 30 150 30 150 p.VN
Rejection Ratio
Average Temperature 50 50 pN°C TA = Thigh to Tlow
Coefficient of Input
Offset Current
Average Temperature 10 10 p.V/oC TA = Thigh to Tlow
Coefficient of Input
Offset Voltage
AV = 1, RL = 2.0 KO
Power Bandwidth 9.0 9.0 kHz Va = 20V (p.p)
THD = 5%

Small Signal Bandwidth 1.0 1.0 MHz

AV = 1, RL = 10 KO
Vo = 50 mV
AV = 1, Vi = -10V
Slew Rate 0.6 0.6 V/p.s
to +10V

Rise Time 0.6 0.6 p's

AV = 1, RL = 10 KO
Va = 50 mV
AV = 1, RL = 10 KO
Fall Time 0.6 0.6 p's
Vo = 50 mV
Av = 1, RL = 10 KO
Overshoot 20 20 %
Va = 50 mV
Av = 1, RL = 2.0 KO
Phase Margin 60 60 Degrees
CL = 200 pF
(Vin = 30 mV p.p
Crossover Distortion 1.0 1.0 % Vout = 2.0V p.p
F = 10 kHz)

IThigh = + 125°C lor XR·3503M, + 70°C for XR·3403C 2Not to exceed maximum package power dissipation.
Tlow = -55°C lor XR·3503M, O°C for XR·3403C 30utput will swing to ground. .

5-28
ELECTRICAL CHARACTERISTICS
XR·3403/3503
Test Conditions: Vee = 5.0V, VEE = Gnd, TA = + 25°e, unless otherwise noted.

XR·3503M XR·3403C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
Input Offset Voltage 2.0 5.0 2.0 10 mV
Input Offset Current 30 50 30 50 nA
Input Bias Current -200 -500 -200 -500 nA
Large Signal Open Loop 20 200 20 200 V/mV RL = 2.0 KO
Voltage Gain
Power Supply Rejection 150 150 INN
Ratio
Output Voltage Range 3 3.5 3.5 Vp·p RL = 10 KO
VCC = 5.0V
VCC-1.5V VCC-1.5V RL = 10 KO
5.0V s VCC s 30V
Power Supply Current 2.5 4.0 2.5 7.0 mA
Channel Separation -120 -120 dB f = 1.0 kHz to 20 kHz
(Input Referenced)

OUTPUT
alAS CIRCUITRY
COMMON TO FOUR
AMPLIFIERS
II
Vee

EQUIVALENT SCHEMATIC DIAGRAM

5-29
 XR-4136

Quad Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-4136 is an array of four independent internally
compensated operational amplifiers on a single silicon
chip, each similar to the popular 741. Good thermal
tracking and matched gain-bandwidth products make
these Quad Op-amps useful for active filter applica- -INPUT A -INPUT 0
tions.

+INPUT A +INPUT 0

FEATURES OUTPUT A OUTPUT 0

Direct Pin-for-Pin Replacement for RC4136 and

RM4136 OUTPUT B Vee

Short-Circuit Protection
Internal Frequency Compensation +INPUT B OUTPUT e
No Latch-Up
Wide Common-Mode and Differential Voltage Ranges
Matched Gain-Bandwidth -INPUT B +INPUT e

VEE -INPUT e

APPLICATIONS
Buffer Amplifiers
Summing/Differencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
ORDERING INFORMATION
Simulated Components Part Number Package Operating Temperature
Analog Computers
XR-4136M Ceramic - 55°C to + 125°C
XR-4136CN Ceramic O°C to + 70°C
XR-4136CP Plastic O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
XR-4136M ±22V
XR-4136C ± 18V
Common Mode
Voltage Range VEE to VCC
Output Short-Circuit Duration Indefinite
Differential Input Voltage ±30V SYSTEM DESCRIPTION
Internal Power Dissipation
Ceramic Package: 750 mW The XR-4136 is a quad operational amplifier featuring
Derate above TA = + 25°C 6 mW/oC similar characteristics to standard 741-type devices.
Plastic Package: 625 mW As all four are monolithic, they have matched charac-
Derate above TA = + 25°C 5 mW/oC teristics, including thermal tracking and gain bandwidth
Storage Temperature Range: - 65°C to + 150°C products.

5-30
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, Vs = ± 15V, unless otherwise specified.
XR·4136
XR4136M XR4136C
PARIlMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOLS CONDITIONS
Input Offset Voltage .5 5.0 .5 6.0 mV IViol As :5. 10 KfJ
Input Offset Current 5.0 200 5.0 200 nA Iliol
Input Bias Current 40 500 40 500 nA lib I
Input Resistance 0.3 5.0 0.3 5.0 MfJ Rin
AL ?; 2 KfJ
Large Signal Voltage Gain 50 300 20 300 V/mV AVOL Vout = ± 10V
±12 ±14 ±12 ±14 V Vout RL ?; 10 KfJ
Output Voltage Swing
±10 ±13 ±10 ±13 V Vout AL ?; 2 KfJ
Input Voltage range ±12 ±14.0 ±12 ±14.0 V ViCM
Common Mode Rejection Ratio 70 105 70 105 dB CMRR As s 10 KfJ
Supply Voltage Rejection Ratio 10 150 10 150 /.MV PSRR As s 10 KfJ
Power Consumption 210 340 210 340 mW Pi
Vin = 20 mV
Transient Response (unity gain) RL = 2 KfJ
Risetime .13 .13 /Ls tr CL s 100 pF
Overshoot 5.0 5.0 % to
Unity Gain Bandwidth 2.0 3.0 3.0 MHz BW
Slew Aate (unity gain)

Channel Separation (open loop)

(Gain of 100)
1.5

105

105
1

105

105
V//Ls

dB

dB
dVout/dt RL ?;

f = 10 KHz
As = 1 KfJ
f = 10 KHz
2 KfJ

II
As = 1 KfJ
The following specifications apply for - 55°C s TA S + 125°C for XR-4136M: DoC S TA S + 70°C for XR-4136C
Input Offset Voltage 6.0 7.5 mV IViol As S 10 KfJ
Input Offset Current 500 300 nA Iliol
Input Bias Current 1500 800 nA Ib
AL ?; 2 KfJ
Large-Signal Voltage Gain 25 15 V/mV AVOL
Vout = ± lOV
Output Voltage Swing ±10 ±10 V Vout AL ?; 2 KfJ
Vs= ±15V
Power Consumption 180 300 100 300 mW Pi TA = High
240 400 240 400 mW Pi TA = Low
Output Short-Circuit Current 45 45 mA ISC

TYPICAL PARAMETER MATCHING:

Test Conditions: TA = + 25°C, Vs = ± 15V unless otherwise noted

XR4136M XR4136C
PARAMETERS TYP TYP UNITS SYMBOLS CONDITIONS
Input Offset Voltage ±1.0 ±2.0 mV IViol Rs ?; 10 KfJ
Input Offset Current ±7.5 ±7.5 nA Iliol
Input Bias Current ±15 ±15 nA Ib
Voltage Gain ±0.5 ±1.0 dB AVOL Rs ?; 2 KfJ

5-31
XR·4136

OUTPUT

VEE ISUBSTRATEI

] /4 of XR-4136

EQUIVALENT SCHEMATIC DIAGRAM

5-32
 XR-4202

Programmable Quad Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-4202 is an array of four independent operational
amplifiers on a single silicon chip. The operating cur-
rent of the array is externally controlled by a single re-
sistor or current source, allowing the user to trade-off
power dissipation for bandwidth.
'INPUT A +INPUT e

-INPUT A -INPUT e

FEATURES
OUTPUT A OUTPUTe

Programmable
Micropower Operation Vee VEE
Wide Input Voltage and Common Mode Range

II
Internal Frequency Compensation OUTPUT B OUTPUT 0
No Latch-Up
Matched Parameters -INPUT B -INPUTD
Short-Circuit Protection

.INPUT B 'INPUT 0

BIAS N.C.
APPLICATIONS
The following approximate relations are useful for
design:

Gain-Bandwidth Product 50 ISET (kHz)

Power Supply Current 30 ISET (p.A)
Slew Rate 20 ISET (V/ms)
ORDERING INFORMATION
Where: ISET is in p.A Part Number Package Operating Temperature

VEE - VBE XR-4202N Ceramic - 40°C to + 85°C

ISET = XR-4202P Plastic -40°C to +85°C
RSET

WHERE VBE DIODE VOLTAGE"", 0.65V

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ± 18V
Differential Input Voltage ±30V SYSTEM DESCRIPTION
Power Dissipation
Ceramic Package: 750mW The XR-4202 is a quad independently programmable
Derate above TA = + 25°C 6 mW/oC operational amplifier featuring improved performance
Plastic Package: 625 mW over industry standard devices such as the 741. Ampli-
Derate above TA == + 25°C 5 mW/oC fier bias currents can be "programmed" by a single re-
Common Mode Range VEE to VCC sistor to Pin 8. Bias currents can range from less than
Short Circuit Duration Indefinite 1p.A, thus affording the designer flexibility along the de-
Storage Temperature - 60°C to + 150°C vice speed/power consumption trade off curve.

5-33
XR·4202
ELECTRICAL CHARACTERISTICS
Test Conditions: High Power Mode (VS = ± 15V, ISET = 75 pA and TA = + 25°C, unless otherwise specified.

PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS

Short Circuit Current 5 17 30 mA ISC O°Cs TAs70°C
Supply Current 0.8 1.7 6.0 mA Is Note 3
Input Offset Voltage 0.8 5.0 mV Vio Rss 10 KG
Input Bias Current 80 500 nA Ib
Input Off-set Current 10 200 nA lio
Input Resistance 0.1 0.6 MG Rin
Input Common Mode Voltage
Range 12 ±14 ±V ViCM
Common Mode Rejection Ratio 70 110 dB CMRR
Voltage Supply Rejection Ratio 15 150 pVN PSRR
Large Signal Voltage Gain 74 88 dB AVOL RL =: 3 KG;
t:No =: ±10V
Output Voltage Swing ±10 ± 13.6 ±V Vout RL =: 3 KG
Gain-Bandwidth Product 3.5 MHz f1
Phase Margin 45 Deg.
Rise Time 70 ns tR tlVo = ±20 mV
Overshoot 20 % to tlVo = ±20 mV
Channel Separation 120 dB Any amp. pair: freq. =
1 Hz, RL = 3 K G
105 dB Any amp. pair: freq. =
10KHz, RL = 3 K G
Slew Rate 1.5 VIps dVout/dt
Input Voltage Noise 25 nV/VHz en Bandwidth 100 Hz to
10 KHz
Note: Short circuit may be taken to either supply line or ground on only one amplifier at a time.

ELECTRICAL CHARACTERISTICS
Test Conditions: High Power Mode (VS = ± 15V, ISET = 75 pA and TA = - 55°C to + 125°C)
PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS
Input Offset Voltage 0.8 10 mV Vio Rs s 10 KG
Input Bias Current 80 1500 nA Ib
Input Offset Current 10 200 nA lio
Large Signal Voltage Gain 68 88 dB Avo I RL 3 KG
tlVo = ±10 V

5-34
ELECTRICAL CHARACTERISTICS
Test Conditions: Micropower Mode (lSET = 1 !LA, Vs = ± 1.5V)
XR·4202
PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS
Supply Current 100 !LA Is Note 3
Input Bias Current 200 nA IB
Input Offset Current 20 nA lOS
Input Offset Voltage 0.5 5 mV Vas Rs~ 10 KO
Input Resistance 0.5 MO Rin
Input Common Mode Voltage
Range 0.3 ±O.S ±V ViCM
Common Mode Rejection Ratio 60 100 dB CMRR
Voltage Supply Rejection Ratio 20 200 p.VN PSRR
Large Signal Voltage Gain 66 SO dB Avol RL~100 KO
Gain-Bandwidth Product 50 kHz GBW
Phase Margin 75 Deg.
Slew-Rate 20 V/ms dVout/dt
Rise Time 7 !L s tR t:.Vo= ±20 mV
Overshoot 0 % to t:.Vo= ±20 mV

•
Channel Separation 120 dB Freq. = Hz:
RL = 20 KO,
t:.Vo = ±0.5 V
120 dB Freq. = 1 KHz:
RL = 10KO,
!:No = ±0.5V
Equivalent Input Voltage Noise 200 nV"V'Hz en Bandwidth = 100 Hz
to 10 KHz

PARAMETER MATCHING (ISET = 75 !LA (2))

PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS
Input Offset Voltage 1 ±mV Vas Rs~ 10 KO
Input Bias Current 10 ±nA IB
Input Offset Current 2 ±nA los
Gain-Bandwidth Product 100 ±KHz f1
Slew Rate 0.2 ±V/!Ls dVo/dt

NOTES: 1. All tests refer to a single op amp unless otherwise specified.

2. Tests apply for parameter matching between any op amp pair.
3. Tests apply to four op amps and biCiS network.

5-35
XR·4202
"cc

•
BIAS 100
I
I
I

~.SE1
•I 'SET
-L

1/4 of XR-4202

EaUIVALENT SCHEMATIC DIAGRAM

5-36
 XR-4212

Quad Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-4212 is an array of four independent internally
compensated operational amplifiers on a single silicon
chip, each similar to the popular 741, but with a power OUTPUT A

consumption less than one 741 . Good thermal tracking

and matched gain-bandwidth products make these -INPUT A
Quad Op-amps useful for active filter applications.

+INPUT A

FEATURES Vee
Same Pinout as MC3403 and LM324
Low Power Consumption-50 mW typo and +INPUT B

120mW max.

•
Short-Circuit Protection -INPUT B
Internal Frequency Compensation
No Latch-Up
Wide Common-Mode and Differential Voltage Ranges OUTPUT B
Matched Gain-Bandwidth

APPLICATIONS
Buffer Amplifiers
SumminglDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing ORDERING INFORMATION
Sample and Differencing
Part Number Package Operating Temperature
I to V Converters
Integrators XR-4212M Ceramic - 55°C to + 125°C
Simulated Components XR-4212CN Ceramic O°C to + 70°C
Analog Computers XR-4212CP Plastic O°C to + 70°C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage
XR-4212M ±22V
XR-4212C ±18V
Common Mode SYSTEM DESCRIPTION
Voltage VEE to VCC
Output Short-Circuit Duration Indefinite The XR-4212 is a quad operational amplifier featuring
Differential Input Voltage ±30V improved performance over industry standard devices
Internal Power Dissipation such as the 741.
Ceramic Package: 750 mW
Derate above TA = + 25°C 6 mW/oC
Plastic Package: 625 mW
Derate above TA = + 25°C 5 mW/oC
Storage Temperature Range: - 65°C to + 150°C

5-37
XR·4212
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, Vs = ± 15V, unless otherwise specified.

XR-4212M XR-4212C

PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOLS CONDITIONS

Input Offset Voltage 1 5.0 1 6.0 mV IViol Rs :s 10 KO

Input Offset Current 10 50 10 50 nA lIiol
Input Bias Current 80 500 80 500 nA Ilbl
Input Resistance 0.3 1.8 0.3 1.8 MO Rin
Large Signal Voltage Gain 20 60 5 40 V/mV AVOL RL ~ 2 KO
Vout = ± 10V
Output Voltage Swing ±12 ±14 ±12 ±14 V Vout RL ~ 10 KO
±10 ±12 ±10 ±12 V Vout RL ~ 2 KO
Input Voltage Range ±12 ± 13.5 ±12 ±13.5 V ViCM
Common Mode Rejection Ratio 70 105 70 105 dB CMRR Rs :s 10 KO
Supply Voltage Rejection Ratio 10 150 10 150 p.VN PSRR Rs :s 10 KO
Power Consumption 50 120 50 120 mW Pi
Transient Response (unity gain) Yin = 20 mV
Risetime 0.07 0.07 p's tr RL = 2 KO
Overshoot 20 20 % to CL :s 100 pF
Unity Gain Bandwidth 2.0 3.0 3.0 MHz BW
Slew Rate (unity gain) 1.6 1.6 V/p.s dVout/dt RL ~ 2 KO
Channel Separation (open loop) 120 120 dB f = 10 KHz
Rs = 1 KO
(Gain of 100) 105 105 dB f = 10 KHz
Rs = 1 KO
The following specifications apply for - 55°C :S TA :S + 125°C for XR-4212M: O°C :S TA :S + 70°C for XR-4212C
Input Offset Voltage 6.0 7.5 mV IViol Rs :S 10 KO
Input Offset Current 200 200 nA Iliol
Input Bias Current 1500 800 nA Ib
Large-Signal Voltage Gain 20 5 V/mV AVOL RL ~ 2 KO
Vout = ± 10V
Output Voltage Swing ±10 ±10 V Vout RL ~ 2 KO
Vs= ±15V
Power Consumption 150 150 mW Pi TA = High
200 200 mW Pi TA = Low
Output Short-Circuit Current 5 17 35 5 17 35 mA ISC

TYPICAL PARAMETER MATCHING:

Test Conditions: TA = + 25°C, Vs = ± 15V unless otherwise noted
XR-4212M XR-4212C
PARAMETERS TVP iYP UNITS SYMBOLS CONDITIONS
Input Offset Voltage ±1.0 ±2.0 mV IViol Rs ~ 10 KO
Input Offset Current ±7.5 ±7.5 nA Iliol
Input Bias Current ±1S ±15 nA Ib
Voltage Gain ±0.5 ± 1.0 dB AVOL Rs ~ 2 KO

5-38
 XR·4212

VEE (SUBSTRA TEl

•
I /4 0 f X R-42 12
EQUIVALENT SCHEMATIC DIAGRAM

5-39
 XR-4560

Dual Low Noise Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The X R-4560 is a dual low noise, wide bandwidth opera-

tional amplifier ideal for active filter applications. The de-
vice is similar to the XR-1458/4558, with greatly enhanced
slew rate, bandwidth, and guaranteed noise characteristics.

Pin for pin compatibility allows direct substitution for

industry standard dual op amps where the low noise and OUTPUT A Vee
wide bandwidth of the XR-4560 is imperative.
- INPUT A OUTPUT B

+ INPUT A - INPUT B

FEATURES + INPUT B

High Gain, Low Input Noise

I nternally Compensated
Wide Small Signal Bandwidth
I nterchangeable with General Purpose Dual Op Amps

APPLICATIONS ORDERING INFORMATION

High Gain, Low Noise Amplifier Part Number Package Operating Temperature
High Performance Active Filter XR-4560CP Plastic O°C to 70°C
Small Signal Amplifier XR-4560CN Ceramic O°C to }O°C
Servo Control System XR-4560MD SO-8 o°c to 70°C
Telephone Channel Amplifier

SYSTEM DESCRIPTION

ABSOLUTE MAXIMUM RATINGS The XR-4560 dual op amp offers guaranteed low noise and
a 10 MHz small signal bandwidth. Slew rate typically ex-
Supply Voltage ±18 V ceeds 4 V IllS. I nternal protection circu itry includes latch-
Power Dissipation 500mW up elimination, short circuit current limiting, and internal
Derate Above at 25°C 5mWtC compensation.
o
Operating Temperature O°C to +70 C
Storage Temperature -55°C to +125°C
Differential Input VOltage ±30 V The two amplifiers are completely independent, sharing
Common Mode Range VEE to VCC only power supply connections.

5-40
XR-4560

ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25° C, VCC = + 15 V, VE E = -15 V, unless specified otherwise.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

VOS Input Offset Voltage 0.5 6.0 mV RS';;;; 10Kn

lOS Input Offset Current 5 200 nA

IB Input Bias Current 50 500 nA

Rin I nput Resistance 5 Mn

AV Open Loop Gain 86 100 dB RL;;;' 2Kn

Output Voltage Swing ±12 ±14 V RL;;;'10Kn

±10 ±13 V RL;;;' 2Kn

VICM Common Mode Range ±12 ±14 V

CMRR Common Mode Rejection Ratio 70 90 dB RS';;;; lOKn

PSRR

SR

BW
Supply Voltage Rejection Ratio

Slew Rate

Unity Gain Bandwidth

30

4.0

10
150 pV/V

Vips

MHz
RS';;;; 10Kn

AV= 1, RL;;;'2Kn

AV = 1
II
Pi Power Consumption 50 mW RL = 00

Channel Separation 100 dB AV = 100

en I nput Noise Voltage 2.2 pV f = 10Hz to 30 kHz

Circu it of Figure 7

EQUIVALENT SCHEMATIC DIAGRAM

VCCo----------.--------~--------~----.-----~----~

INVERTING OUTPUT
INPUT

NON INVERTING
INPUT

. vEEo-______ ~-+--+_----_+_-------6_---+_----_+_--_+_---...J

ISUBSTRA TE I

(One Channel Only)

5-41
 XR-4560

TYPICAL CHARACTERISTICS
5 35

/
/
30

L~
/"" 25
a
V V

/
V 20

15

V 10

10 100 lk 10k lOOk 1M

LOAD RESISTANCE (Q)
4 6 8 10 12 14 16 18

SUPPLY VOLTAGE v+ = v-

Figure 1. Output Voltage Swing vs Supply Voltage Figure 2. Loaded Output Voltage Swing

r- r- .--

'r- t- !-
.......

1\ 'r-
\ l"-
I

1\ .........

I""
+- ~
v+ m v- • 15V
RL ~ 10KQ
I HH)
I Ok I!Jk lOOk 1M
i'H
10M
'"
10 100 lk
FREOUENCY (HZ)
10k lOOk
"" "p;EQuE~n ~:

Figure 3. Large Signal Frequency Response Figure 4. Open Loop Gain

140

120

~ i'r'--,
r"-,
100

"I' 1
Av· +21
R , ·50Q

1"1J 10 100
. . . . r--I"-

lk
r--

10k lOOk
80
1 10 100 lk 10k lOOk FREOUENCYIHZl

FREQUENCY (HZ)

Figure 5. Channel Separation vs Frequency Figure 6. Input Noise Voltage Spectral Density
Noise measurements made on a Quantek 2173-2181 noise analyze'
= 21.
w ith the XR-4560 in a standard honinverting circuit with AV

5-42
XR-4560

TYPICAL APPLICATIONS
~--------------~ PHONO
OUTPUT
PHONO
INPUTo---~~----~

Rg*
~OISE
0.47f.1

'Transducer Load Resistor

•
Figure 7. RIAA Equalized Phonograph Preamplifier
(One Channell & Broadcast Noise Test Circuit

0.22/-1

INPUT~
~~--~~~-------o OUTPUT

Rgl
'Transducer Load Resistor

Figure 8. NAB Equalized Tape Playback Preamplifier

(One Channell

'" BODE PLOT

."
,,-,~ v-~
l\.
co
'0 .0
"~~
eOCE PLOT "
~ ACTUAL RESPONSE

2
« 30 '~ \ .... ACTUAL
/AESPONSE
(!)
"r\ ~ f-

FREQUENCY (Hz)
'" "\

100>

FREQUENCY (Hz)
lOOk

Figure 9. RIAA·Type Phonograph Equalization Figure 10. NAB· Type Tape Player Equalization

5-43
 XR-4739

Dual Low-Noise Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-4739 is a monolithic dual op amp featuring low
noise and a large gain bandwidth product. The device
is ideal for preamplifiers, signal processing equipment,
and active filters.

A OUTPUT

NC

FEATURES NC

Internally Compensated Replacement for ,.,.A 739

and MC1303 NC
Signal-to-Noise Ratio 76dB (RIM 10 mV ref.)
Channel Separation 125dB <1\ INPUT
Unity Gain Bandwidth 3MHz
Output Short-circuit Protected
-A INPUT
0.1 % Distortion at 8.5V RMS Output into 2KO Load

v-

APPLICATIONS
Buffer Amplifiers
Summing/Differencing Amplifiers
Instrumentation Amplifiers
Active Filters ORDERING INFORMATION
Signal Processing
Sample and Differencing Part Number Package Operating Temperature
I to V Converters XR-4739CN Ceramic O°C to + 70°C
Integrators XR-4739CP Plastic O°C to + 70°C
Simulated Components
Analog Computers

SYSTEM DESCRIPTION
The XR-4739 dual low-noise operational amplifier is fab-
ricated on a single silicon chip using the planar epitaxi-
al process. It was designed primarily for preamplifiers
ABSOLUTE MAXIMUM RATINGS in consumer and industrial signal proceSSing equip-
ment. TIle device is pin compatible with the ,.,.A739 and
Supply Voltage ±18V MC1303, however, compensation is internal. This per-
Internal Power Dissipation (Note 1) 500 mW mits a lowered external parts count and simplified ap-
Differential Input Voltage ±30V plication.
Input Voltage (Note 2) ±15V
Storage Temperature Range - 65°C to + 150°C The XR-4739 is available in a ceramic or molded dual
Lead Temperature (Soldering, 60s) 300°C inline 14 Pin package, and operates over the commer-
Output Short-Circuit Duration (Note 3) Indefinite cial temperature range from O°C to + 70°C.

5-44
ELECTRICAL CHARACTERISTICS
XR·4739
Test Conditions: TA = 25°C, VCC = ± 15V, unless otherwise specified.

PARAMETERS MIN TYP MAX UNITS CONDITIONS

Input Offset Voltage 2.0 6.0 mV RS ~ 10 kO
Input Offset Current 5.0 200 nA
Input Bias Current 40 500 nA
Input Resistance 0.3 5.0 MO
Large-Signal Voltage Gain 20 60 K RL ~ 2 kO
Vout = ± 10V
Output Voltage Swing ±12 ±14 V RL ~ 10 kO
±10 ±13 V RL ~ 2 kO
Input Voltage Range ±12 ±14 V
Common Mode Rejection Ratio 70 100 dB RS ~ 10 kO
Supply Voltage Rejection Ratio 10 150 INN RS ~ 10 kO
Power Consumption 40 120 mW
Transient Response (unity gain) Yin = 20 mV
Risetime RL = 20 kO
0.15 JLs CL ~ 100 pF

•
Transient Response (unity gain) Yin = 20 mV
Overshoot RL = 2 kO
10 % CL ~ 100 pF
Slew Rate (unity gain) 1.0 V/JLs RL ~ 2 kO
Broadband Noise Voltage BW = 10 Hz-30 KHz
2.5 JLVRMS RS = 1 kO
Channel Separation f = 1.0 kHz
AV = 40 dB
125 dB RS = 1 kO

The following specifications apply for O°C s TA s 75°C unless otherwise specified.
Input Offset Voltage 3.0 7.5 mV RS ~ 10 kO
Input Offset Current 7.0 300 nA
Input Bias Current 50 800 nA
Large-Signal Voltage Gain RL ~ 2 kO
15,000 200,000 Vout = ± 10V
Output Voltage Swing ±10 ±13 V RL ~ 2 kO
Power Consumption Vs = ± 15V
100 150 mW TA = 70°C
110 200 mW TA = O°C
Notes:
1. Rating applies for ambient temperatures below + 75°C
2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage.
3. Short-circuit may be ground, typically 45 mA. Rating applies to + 125°C ambient temperature.

5-45
XR·4739

VEE (SUBSTRATEI

EQUIVALENT SCHEMATIC DIAGRAM

% of XR-4739

5-46
 XR-4741

Quad Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-47 41 is an array of four independent internally-
compensated operational amplifiers on a single silicon OUTPUT A OUTPUT 0

chip, each similar to the popular 741. Each amplifier of-

fers performance equal to or better than the 741 type in -INPUT A -INPUT 0
all respects. It has high slew rate, superior bandwidth,
and low noise, which makes it excellent for audio ampli-
-INPUT A .INPUT 0
fiers or active filter applications.

FEATURES
Short-Circuit Protection -INPUT B 'INPUT C

Internal Frequency Compensation

No Latch-Up ·INPUT B -INPUT C

•
Wide Common-Mode and Differential Voltage Ranges
Matched Gain-Bandwidth OUTPUT B OUTPure
High Slew Rate 1.6V/p,S(Typ)
Unity Gain-Bandwidth 3.5 MHz(Typ)
Low Noise Voltage 9 nVYHZ
Input Offset Current 60 nA(Typ)
Input Offset Voltage .5 mV(Typ)
Supply Range ±2V to ±20V

APPLICATIONS
Buffer Amplifiers
SummingIDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing ORDERING INFORMATION
Sample and Differencing
I to V Converters Part Number Package Operating Temperature
Integrators XR-4741 M Ceramic - 55°C to + 125°C
Simulated Components XR-4741CN Ceramic O°C to + 70°C
Analog Computers XR-4741CP Plastic O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
XR-4741 ±20
Common Mode SYSTEM DESCRIPTION
Voltage VEE to Vce
Output Short-Circuit Duration Indefinite The XR-4741 is a quad independently programmable
Differential Input Voltage ±30V operational amplifier featuring improved performance
Internal Power Dissipation over industry standard devices such as the 741. Ampli-
Ceramic Package: 880 mW fier bias currents can be "programmed" by a single re-
Derate above TA = + 25°C 5.8 mW/oe sistor to Pin 8. Bias currents can range from less than 1
Plastic Package: 625 mW p,A to over 75 p,A, thus affording the deSigner flexibility
Derate above TA = + 25°C 5 mW/oC along the device speed/power consumption trade off
Storage Temperature Range: - 65°C to + 150°C curve.

5-47
XR·4741
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, Vs = ± 15 V unless otherwise specified.

XR-4741M XR-4741C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOLS CONDITIONS
Input Offset Voltage 0.5 3.0 1.0 5.0 mV IViol Rs ~ 10 KO
Input Offset Current 10 30 10 50 nA Iliol
Input Bias Current 60 200 60 300 nA Ilbl
Differential Input Resistance 5 5 MO Rin
Input Noise Voltage 9 9 nV/.JHz
(f = 1 kHz)
50 100 25 50 V/mV AVOL RL ~ 2 KO
Large Signal Voltage Gain
Vout = ± 10V
±12 ± 13.7 ±12 ± 13.7 V Vout RL ~ 10 KO
Output Voltage Swing
±10 ± 12.5 ±10 ±12.5 V Vout RL ~ 2 KO
Full Power Bandwidth 25 25 kHz
Output Resistance 300 300 0
Input Voltage Range ±12 ±13.5 ±12 ± 13.5 V ViCM
Common Mode Rejection 80 100 80 100 dB CMRR Rs ~ 10 KO
Ratio
Supply Voltage Rejection Ratio 10 100 10 100 p.VIV PSRR Rs ~ 10 KO
Power Consumption 150 210 mW Pi
Yin = 20 mV
Transient Response RL = 2 KO
(unity gain)
Risetime .07 .07 P.s tr CL ~ 100 pF
Overshoot 20 20 % to
Unit Gain Bandwidth 3.5 3.5 MHz BW
Slew Rate (unity gain) 1.6 1.6 V/p.s dVout/dt RL ~ 2 KO
Channel Separation f = 10 KHz
(open loop) 120 120 dB Rs = 1 KO
f = 10 KHz
(Gain of 100) 105 105 dB Rs = 1 KO
The following specifications apply for - 55°C ~ TA ~ + 125°C for XR-4741M; DoC ~ TA ~ + 70°C for XR-4741C
Input Offset Voltage 4.0 5.0 5.0 6.5 mV IViol Rs ~ 10 KO
Input Offset Current 75 100 nA Iliol
Input Bias Current 325 400 nA Ib
Input Voltage Range ±12 ±12 V
Common Mode Rejection 74 74 db
Ratio
RL ~ 2 KO
Large-Signal Voltage Gain 25 15 V/mV AVOL Vout = ±10V
Output Voltage Swing ±10 ±12.5 ±10 ± 12.5 V Vout RL = 2 KO
±12.0 ± 13.7 ±12 ± 13.7 RL ~ 10 K!2
Vs = ± 15V
Power Consumption 150 150 mW Pi TA = High
200 200 mW Pi TA = Low
Supply Voltage Rejection Ratio 100 p.VIV 100 p.VIV
Output Short-Circuit Current ±5 ±15 ±5 ±15 mA ISC

5-48
 XR·4741

1/4 0 f X R-4 74 1
VEE ISUBSTRATEI

•
EQUIVALENT SCHEMATIC DIAGRAM

5-49
 XR-5532/5532A

Dual Low-Noise Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-5532 dual low-noise operational amplifier is es-
pecially designed for applications in high quality profes-
sional audio equipment. The low-noise, wide bandwidth XR·5532
and output drive capability make it ideally suited for in-
strumentation and control circuits as well as active filt-
er design.

The XR-5532A is the specially screened version of the

XR-5532, with guaranteed noise characteristics.

FEATURES
Pin for Pin Replacement for Signetics NE 5532
Wide Small-Signal Bandwidth: 10 MHz
High-Current Drive Capability
(10V rms into soon at VS = ± 1aV)
High Slew Rate: 9 V/p.s 140
Wind Power-Bandwidth: 140 kHz
Very Low Input Noise: 5 nV/.JFfZ
Wide Supply Range: ± 3V to ± 20V

APPLICATIONS
High Quality Audio Amplification
Telephone Channel Amplifier
Servo Control Systems ORDERING INFORMATION
Low-Level Signal Detection Operating Temperature
Part Number Package
Active Filter Design
XR-5532N Ceramic DOC to +70°C
ABSOLUTE MAXIMUM RATINGS XR-5532P Plastic DoC to + 70°C
XR-5532AN Ceramic O°C to + 70°C
Power Supply ±22V
XR-5532AP Plastic DoC to + 70°C
Input Common-Mode Range -VEE to +VCC
Differential Input Voltage (Note 1) ±0.5V
Power Dissipation (Package Limitation)
Ceramic Package a-Pin SOOmW
Derate Above TA = 25°C mW/oC a
Storage Temperature - 60°C to + 150°C SYSTEM DESCRIPTION
Note 1: Diodes protect the inputs against over-VOltage. There·
The XR-5532 and XR-5532A are dual monolithic opera-
fore, unless current·limiting resistors are used, large
currents will flow if the differential input voltage ex- tional amplifiers featuring low noise and very large gain
ceeds 0.6V. Maximum current should be limited to ± bandwidth products. The devices have low output re-
10 mA. sistance and can drive 10 Vrms into soon. Input noise
is 100% tested on the XR-5532A, and is typically only 5
f'Jctc 2: Output may bo shorted to ground at Vee = VEE = nV/VHz. The small signal bandwidth is 10 MHz and
15V, TA = 25°C. Temperature and/or voltages must be slew rate exceeds 9 V/p.S. Supply voltage may range
limited to ensure dissipation rating is not exceeded. from ± 3V to ± 1av.
Note 3: Operation near the absolute maximum ratings will ex-
ceed the power dissipation of the package.

5-50
XR·5532/5532A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°e, Vee = VEE = 15V unless otherwise specified.

XR-5532A XR-5532
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOL CONDITIONS
DC CHARACTERISTICS
Input Offset Voltage 0.5 4 0.5 4 mV VOS TA = 25°C
5 5 mV TA = Full Range
Input Offset Current lOS
10 150 10 150 nA TA = 25°C
200 200 nA TA = Full Range
Input Bias Current IB
200 800 200 800 nA TA = 25°C
1000 1000 nA TA = Full Range
Large Signal Voltage Gain AVOL RL ~ 600n,
Vo = ±10V
25 100 25 100 V/mV TA = 25°C
15 15 V/mV TA = Full Range
Supply Current 8 16 8 16 mA ICC RL = Open
Output Swing VOUT RL ~ 600n
±12 ±13 ±12 ±13 V Vce = VEE = 15V
±15 ±16 ±15 ±16 V Vce = VEE = 18V

•
Output Short Circuit Current 38 38 mA ISC (Note 2)
Input Resistance 30 300 30 300 kn RIN
Common-Mode Range ±12 ±13 ±12 ±13 V ViCM
Common-Mode Rejection 70 100 70 100 dB CMRR
Power Supply Rejection 10 100 10 100 p.V/v PSRR
Channel Separation 110 110 dB f = 1 kHz,
As = 5 Kn
AC CHARACTERISTICS
Transient Response Voltage Follower
Rise Time 20 20 nsec tr RL = 600n
Overshoot 10 10 % to VIN 100 MV~p,
CL = 100 P
AC Gain f = 10 kHz
2.2 2.2 V/mV
Unity-Gain Bandwidth 10 10 MHz BW CL = 100 pF
Slew Rate 9 9 V/p.sec
Power Bandwidth 140 140 kHz fp VOUT = ± lOV
RL = 600n
Output Resistance .3 .3 n ROUT Av = 30 dB
Closed loop
f = 10kHz
RL = 600n
NOISE CHARACTERISTICS
Input Noise Voltage en
8 10 8 nV/~z fO = 30 kHz
5 6 5 nV/~z fO = 1 kHz
Input Noise Current in
2.7 2.7 pN~z fO = 30 Hz
.7 .7 pN~z fO = 1 kHz

5-51
 XR-5532/5532A
TEST CIRCUITS

CLOSED LOOP FREQUENCY RESPONSE VOLTAGE FOLLOWER

Vee

>-__......__--r_-oVOUT

lK

'·"1 60011

TYPICAL PERFORMANCE CHARACTERISTICS

OPEN LOOP FREQUENCY CLOSED LOOP FREQUENCY LARGE~IGNALFREQUENCY

RESPONSE RESPONSE RESPONSE

TYPICAL VALUES

'\~

" \
"\
'\
\
\
10 3 10" 105 10 6 10' 10 8
I(HII

OUTPUT SHORT·CIRCUIT INPUT BIAS CURRENT INPUT COMMON MODE

CURRENT VOLTAGE RANGE

V S··lSV VS"'1SV
H.lICAL vlLuEs
-- -- -
12 - - - -- f-- --f---i--r-

-- ---- -

- lL --
...........
~ 0.. t--t--- --..- .-- --t----+------I-~ -
-yp

- lL
7
55 _25
0
-- /

SUPPLY VOLTAGE IV)

5-52
XR·5532/5532A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

SUPPLY CURRENT INPUT NOISE VOLTAGE DENSITY

12 102 r-------~------~------r-----__,

TYP :s< 10 '- TYP

L
~
~
---- UJ
c.:l
<t
~
o
r-----+-~
...............
>
LU
til
o
2
..J
<t
a:
~ 0.1
~
til

0.01 L--_ _ _ _ _ _' - -_ _ _ _ _ _' - -_ _ _ _ _ _' - -_ _ _ _----I

o tl0 120 10 102 103 104

SUPPL Y VOLTAGE (V) FREQUENCY (Hz)

PREAMPLI FI ER-RIAA/NAB
TYPICAL APPLICATION II
COMPENSATION 70
BODE PLOT
JI
' -...."\. V-~
'\. \.
f--
BOOEPlOT~<
021

'"
ACTUAL RESPONSF

'"~F~--' '~
..
Z '\ ACTUAL
/RESPONSE
~ 30 '-
.~,
~~
20

"\.'\
10 1 10 2 103 10 5 10 2 104 10 5

FREOUENc.;V!H/I FREQUENCY IH/I

·SELECT TO PROVIDE SPECIfiED TRANSDUCER LOADING BODE PLOT Of RIA/\' EQUALIZATION AND THE BOOE PLOT OF NAB EOUALIZATION AND THE
OUTPUT NOISE 08 mV ,m\ !~"wl TH INPUT SHORTEDI RESPONSE REALIZED IN AN ACTUAL CIRCUIT RESPONSE REALIZED IN THE ACTUAL CIACUIT USING
USING THE XA 5533 THE XR !IS))
All AESIS1QR VALUES ARE IN OH"'-1S

EQUIVALENT SCHEMATIC DIAGRAM

r-""t"""-r-----""t"""-~--""t"""-~-----_r_o tVcc

1/2 of XR·5532

5-53
 XR-5533/5533A

Dual Low-Noise Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-5533 dual low-noise operational amplifier is es-
pecially designed for applications in high quality profes-
sional audio equipment. The low-noise, wide bandwidth
and output drive capability make it ideally suited for in- BALANCEI
CaMP. A
strumentation and control circuits as well as active filt-
er design. COMPo A

The XR-5533A is the specially screened version of the

OUTPUT A
XR-5533 with guaranteed worst-case noise specifica-
tions.
+VCC
FEATURES
OUTPUT B
Direct Replacement for Signetics SEINE 5533
Wide Small-Signal Bandwidth: 10 MHz COMPo B
High-Current Drive Capability
(10V rms into 6000 at Vs = ± 18V) BALANCEI
CaMP. B
High Slew Rate: 13 V/p.s
Wide Power-Bandwidth: 200 kHz
Very Low Input Noise: 4 nV/.J"HZ

APPLICATIONS
High Quality Audio Amplification
Telephone Channel Amplifier
Servo control Systems
Low-Level Signal Detection
Active Filter Design
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Part Number Package Operating Temperature
Power Supply ±22V XR-5533AN Ceramic O°C to + 70°C
Input Common-Mode Range -VEE to +VCC XR-5533AP Plastic O°C to + 70°C
Differential Input Voltage (Note 1) ±0.5V
XR-5533N Ceramic O°C to + 70°C
Short Circuit Duration (Note 2) Indefinite XR-5533P Plastic O°C to + 70°C
Power Dissipation (Package Limitation)
Ceramic Package 14-Pin 750 mW
Plastic Package 14-Pin 600mW
Derate Above TA = 25°C 5 mW/oC
Storage Temperature - 60°C to + 150°C

Note 1: Diodes protect the inputs against over-voltage. There- SYSTEM DESCRIPTION
fore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage ex- The XR-5533 and XR-5533A are dual monolithic opera-
ceeds 0.6V. Maximum current should be limited to ± tional amplifiers featuring low noise and very large gain
10 mA. bandwidth products. The devices have low output re-
sistance and can drive 10 Vrms into 6000. Input noise
Note 2: Output may be shorted to ground at VCC = VEE =
15V, TA = 25°C. Temperature and/or supply voltages is 100% tested on the XR-5533A, and is typically only 4
must be limited to ensure dissipation rating is not ex- nV/~ The small signal bandwidth is 10 MHz and
ceeded. slew rate exceeds 13 V/p.S.

5-54
XR·5533/5533A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°e, Vee = VEE = 15V unless otherwise specified.
XR-5533A XR-5533
PARAMETERS MIN. TYP. MAX. MIN. TYP. MAX. UNITS SYMBOL CONDITIONS
DC CHARACTERISTICS
Input Offset Voltage VOS
0.5 4 0.5 4 mV TA = 25°C
5 5 mV TA = Full Range
Input Offset Current lOS
20 300 20 300 nA TA = 25°C
400 400 nA TA = Full Range
Input Bias Current IB
500 1500 500 1500 nA TA = 25°C
2000 2000 nA TA = Full Range
Large Signal Voltage AVOL RL ~ 6000,
Gain Vo = ±10V
25 100 25 100 V/mV TA = 25°C
15 15 V/mV TA = Full Range
Supply Current 4 8 4 8 mA ICC RL = Open
(Each Amplifier)
Output Swing VOUT RL ~ 6000
±12 ±13 ±12 ±13 V VCC = VEE = 15V
±15 ±16 ±15 ±16 V Vec = VEE = 18V

•
Output Short Circuit 38 38 mA ISC (Note 2)
Current
Input Resistance 30 100 30 100 kO RIN
Common-Mode ±12 ±13 ±12 ±13 V ViCM
Range
Common-Mode 70 100 70 100 dB CMRR
Rejection
Power Supply 10 100 10 100 pVN PSRR
Rejection
Channel Separation 110 110 dB f = 1 kHz,
RS = 5 kO
AC CHARACTERISTICS
Transient Response Voltage Follower
Rise Time 20 20 nsec tr RL = 6000,
Cc = 22 pF
Overshoot 20 20 % to CL = 100 pF
VIN = 50 mV
AC Gain f = 10 kHz
6 6 V/mV Cc =0
2.2 2.2 V/mV Cc = 22 pF
Unity-Gain 10 10 MHz BW Cc = 22 pF,
Bandwidth CL = 100 pF
Slew Rate 13 13 V/p/sec Cc = 0
6 6 VIp/sec Cc = 22 pF
Power Bandwidth 95 95 kHz fp VOUT = ±10V,
Cc = 22 pF
200 200 kHz Cc = 0 pF
NOISE CHARACTERISTICS
Input Noise Voltage en
5.5 7 7 nV/.JRz fO = 30 Hz
3.5 4.5 4 nV/.JFiz to = 1 kHz
Input Noise Current in
1.5 2.5 pN.JFiz to = 30 Hz
0.4 0.6 pN.JFiz to = 1 kHz
Broadband Noise 0.9 0.9 dB RN FS = 5 kO
Figure t= 10 Hz to
20 kHz

5-55
TEST CIRCUITS
FREQUENCY COMPENSATION AND OFFSET
XR·5533/5533A
VOLTAGE ADJUSTMENT CIRCUIT CLOSED LOOP FREQUENCY RESPONSE

<c-

TYPICAL PERFORMANCE CHARACTERISTICS

SLEW-RATE AS A FUNCTION OF CLOSED LOOP FREQUENCY
OPEN LOOP FREQUENCY RESPONSE COMPENSATION CAPACITANCE RESPONSE
TYPICAL VALUES VS"" 15V
Cc
,~
,~C-O
\ B-
CC- 22pF'\
t\ \
~l\. I\.
I~ '" -..!.YP

. . . t'---.\-....
10102'03,04 10 5 ,06 ,07
10 3 ,0" 10 5 10 6 10' 10 8
FREQUENCY (Hzl Cc tpF) FREQUENCY IHI)

LARGE-SIGNAL FREQUENCY OUTPUT SHORT-CIRCUIT

RESPONSE CURRENT INPUT BIAS CURRENT

VS·· 15V V S ··15V Vs·% 15V

TYPICAL VALUES_
I
Cc- I
. / -OpF
-22~F- - -
nr:: -47~F_
- -
.......
r---....
r-- r-T~ r-- 0.8
r\.
~
,\
\\ \
'" -r-.---- TYP

~~ o
102 103 104 105 106 107 75 100 125 -55 -25 100 125

FREQUENCY (Hz)

INPUT COMMON MODE SUPPLY CURRENT INPUT NOISE VOLTAGE

VOLTAGE RANGE PER OP-AMP DENSITY
1 102 r----.....---..,.---r---r-----,
T~PICAL V'AlUES 10 '0

,..
~ 10
~
---
TYP
TYP
I--"" ...>
~ ~
~
I~
VPOS

.~
§v a:
t;
~
~V
:10 !. 20 :!:'0 ~ 20 102 10 3

SUPPl Y VOLTAGE (V) SUPPLY VOLTAGE (V)

'"
FREOUENCY IHll

5-56
XR·5533/5533A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
BROADBAND INPUT
INPUT NOISE CURRENT DENSITY TOTAL INPUT NOISE DENSITY NOISE VOLTAGE

102 r - - - r - - - - - - r - - - r - - - - r - - - - - , 10 6
TYPICAL VALUES

l
105

104
10 Hz

10 3 /
/ V
1kHz
102
"~~T...
YP"""__ _
l/~ 17
.~ ~ THERMAL NOISE OF

~
a:
0.1 .. V
V SOURCE RESISTANCE
10 1 1--+--+-+-+--+---1
~
0.1

0.01 ' - - _ - - - ' ' - - _ - - ' -_ _- ' -_ _-'-_--J 0.01 102 L...._..I-_.l...._...L-_...L_-L._-I
10 102 10 3 104 102 103 104 105 10 6

FREOUENCY 1Hz! RSllll RS 1111

TYPICAL APPLICATION

•
PR EAMPLI FI ER-R I AA/NAB
COMPENSATION II SODE PLOT

,
60 60
"'-'\ V-~
\.
~~ ~
~ ACTUAL RESPONSE

IN~ " 40

'~ 'I\.
ACTUAL

f" Z

~ jRESPONSE

~
20
"r\.
--
16K 0.003
10

101 10 2 103

FREQUENCY (Hz)
'" "\

10 5 101 10 2

FREOUENCY 1Hz!
105

'SELECT TO PROVIDE SPECI FlED TRA"SDUCER LOADING BODE PLOT OF RIAA EOUALIZATION AND THE BODE PLOT OF NAB EOUALIZATION AND THE
OUTPUT "OISE;> 0.8 mV , ... IWITH INPUT SHORTED} RESPONSE REALIZED IN AN ACTUAL CIRCUIT RESPONSE REALIZED IN THE ACTUAL CIRCUIT USING
USING THE XR·5533 THE XR·S533
ALL RESISTOR VALUES ARE IN OHMS.

EQUIVALENT SCHEMATIC DIAGRAM

11201 XR·5533 ISUBSTRA TE}

5-57
 XR-5534/5534A

Low-Noise Operational Amplifier

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-5534 is a high performance low-noise opera-
tional amplifier especially designed for application in
high quality and professional audio equipment. It offers XA·5534
five-fold improvement in noise characteristics, output
drive capability and full-power bandwidth over conven-
tional 741-type op amps. The op amp is internally com-
pensated for gain equal to, or higher than, three. The
frequency response can be optimzed with an external
compensation capacitor for various applications such
as operating in unity gain mode or driving capacitive
loads.

The XR-5534A is a specially-screened version of the

XR-5534, with guaranteed noise specifications.

FEATURES
Direct Replacement for Signetics NE/SE 5534
Wide Small-Signal Bandwidth: 10 MHz
High-Current Drive Capability
(10V rms into 600n at Vs = ±18V)
High Slew Rate: 13 V//Jos
Wide Power-Bandwidth: 200 kHz typo
Very Low Input Noise: 4 nV/..JHZ typo ORDERING INFORMATION
APPLICATIONS Part Number Package Operating Temperature
5534AM Ceramic - 55°C to + 125°C
High Quality Audio Amplification
5534M Ceramic -55°C to +125°C
Telephone Channel Amplifiers
5534ACN Ceramic O°C to + 70°C
Servo Control Systems
5534CN Ceramic O°C to + 70°C
Low-Level Signal Detection
5534ACP Plastic O°C to + 70°C
Active Filter Design
5534CP Plastic O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Power Supply ±22 V SYSTEM DESCRIPTION
Input Common-Mode Voltage +VCC to -VEE
Differential Input Voltage (Note 1) The XR-5534 and XR-5534A are monolithic operational
±0.5 V
amplifiers featuring low noise and a very large gain
Power Dissipation (Package Limitation)
bandwidth product. The devices offer low output resist-
Ceramic Package 385 mW
Plastic Package ance and can drive 10 Vrms into 600n. Input noise is
300 mW
2.5 mW/oC 100% tested on the XR-5534A, and is typically only 4
Derate Above + 24°C
nV/YHz. The small signal bandwidth is 10 MHz and
Short Circuit Duration (Note 2) Indefinite
slew rate exceeds 13 V//JoS.
Storage Temperature - 60°C to + 150°C

Note 1: Diodes protect the inputs against over-voltage. There-

fore, unless current-limiting resistors are used, large Reverse parallel diodes provide input protection; maxi-
currents will flow if the differential input voltage ex-
mum differential input voltage is 0.7 V. Balance pins are
ceeds 0.6V. Maximum current should be limited to ±
10 mA. provided to zero offset voltage. The device is internally
Note 2: Output may be shorted to ground at Vs = ± 15V, TA = compensated for gains ~ 3 and provides external com-
25°C. Temperature and/or supply voltages must be lim- pensation pins for unity gain applications. Supply volt-
ited to ensure dissipation rating is not exceeded. age may range from ± 3V to ± 20V.

5-58
XR·5534/5534A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°e, Vee = VEE = 15V, unless otherwise specified.
XR-5534M/5534AM XR-5534AC/XR-5534C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOL CONDITIONS
DC CHARACTERISTICS
Input Offset Voltage VOS
0.5 2 0.5 4 mV TA = 25°C
3 5 mV TA = Full Range
Input Offset Current lOS
10 200 20 300 nA TA = 25°C
500 400 nA TA = Full Range
Input Bias Current IB
400 800 500 1500 nA T = 25°C
1500 2000 nA ~ = Full Range
Large Signal Voltage AVOL RL ~ 6000,
Gain VO= ±10V
50 100 25 100 V/mV T = 25°C
25 15 V/mV ~= Full Range
Supply Current 4 6.5 4 8 mA ICC RL = Open
Output Swing VOUT RL ~ 6000
±12 ±13 ±12 ±13 V VCC = VEE = 15V
±15 ±16 ±15 ±16 V VCC = VEE = 18V
Output Short Circuit 38 38 mA ISC (Note 2)

•
Current
Input Resistance 50 100 30 100 kO RIN
Common·Mode ±12 ±13 ±12 ±13 V ViCM
Range
Common-Mode 80 100 70 100 dB CMRR
Rejection
Power Supply 10 50 10 100 IlVN PSRR
Rejection

AC CHARACTERISTICS
Transient Response Voltage Follower
Rise Time 20 20 nSec tr RL~6000,
Cc = 22 pF
Overshoot 20 20 % to CL = 100pF
AC Gain f = 10kHz
6 6 6 V/mV Cc = a
2.2 2.2 2.2 V/mV Cc = 22 pF
Unity-Gain 10 10 MHz BW Cc = 22 pF,
Bandwidth CL = 100 pF
Slew Rate 13 13 V/llsec Cc = a
6 6 V/llsec Cc = 22 pF
Power Bandwidth 95 95 kHz fp VOUT = ±10V,
Cc = 22 pF
200 200 kHz Cc = 0

NOISE CHARACTERISTICS
XR-5534A XR-5534
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYMBOL CONDITIONS
Input Noise Voltage en
5.5 7 7 nV/.JHz. to = 30 Hz
3.5 4.5 4 nV/.J'Hi. to = 1 kHz
Input Noise Current In
1.5 2.5 pA/.JHZ to = 30 Hz
0.4 0.6 pA/.JHZ to = 1 kHz
Broadband Noise 0.9 dB FN RS = 5 kO
Figure t = 10 Hz to
20 kHz

5-59
TEST CIRCUITS
XR·5534/5534A
FREQUENCY COMPENSATION AND OFFSET CLOSED LOOP FREQUENCY RESPONSE
VOLTAGE ADJUSTMENT CIRCUIT

'-'1 .. "

TYPICAL PERFORMANCE CHARACTERISTICS

SLEW·RATE AS A FUNCTION OF CLOSt:D LOOP FREOUENCY
OPEN LOOP FREQUENCY HESPONSE COMPENSATION CAPACITANCE RESPONSE

Vs" '5V

tl.
(<;

~
1-.. ._,...- -_.-
1--.

I--
~1-- . -
~V'
~ -. .. - 1-.-

""
1--- 1--. I--
'" ~ 1--- -- I - -

fREOUENCY IH,I

LARGE·SIGNAL FREOUENCY OUTPUT SHORT·CIRCUIT

RESPONSE CURRENT INPUT BIAS CURflENT

VS·· 1!iV
I~::r,;;-
__ _ _._ ''''''CAl VALUU_ ._- -_. f--- I-.. -+.--~--+-~-l --1-- I--1 -

10 --- --I-- ._- 1 - - 1 - + - - 1.2 --r-

1- --- I - - '.-1-
r\.
t'.. Tn

-"1"'- +--
20~. -

10 71 '00 .n
FAEOUfNCY IHI) 'A rct
INPUT COMMON MODE
VOLTAGE RANGE SUPf)L Y CURRENT INPUT NOISE VOLTAGE DENSITY
2
1
'0 •0

,- ~
~
TV'

- '0
I'-- TV'

.02
~ 10 .:1'0 ~ 10 '02 .1)'1

SUPPLY VOll.AOE tVI SUPPL y VOLT AGE CV) "UOUlNCY CH,I

5-60
XR·5534/5534A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

BROADBAND INPUT
INPUT NOISE CURRENT DENSITY TOTAL INPUT NOISE DENSITY NOISE VOLTAGE
'01 ....-_--,._ _- , -_ _,......._....,
,of 1
10 "'--r--r-~r--r---'r---"
lYPICAl VA-lUll

10 ttl
/
"'H,
/ V
.... ~__rv..' ...._ - - '
~ ~-
l / ~ .....
tHERMAL NOISE 0'

0.1 t---t---+---~--_l
p-- ~- snURCE RUISTANCE
·0.1 I--+--+--~-+--I--l

0.01 L - _........_ _-I.-_ _'--_.....I

'01 'OJ ,.. 0.01 0.01 '--_'--_L.---JL.---JL.---JL.-.....I

102 '0l 104 105 toS

fREOVENCV IH/I
ASfUI

TYPICAL APPLICATION

PREAMPLIFIER-RIAA/NAB

•
COMPENSATION

021

'N~~
l"SL ~P\"

_-i~--4....-;~J
,. d·d.
,,;:;1-
"
~--"""""",'v-- .
UiK 0003
'---_vv--~~ '0' '02 'OJ

fR£QUfN«;V 1.4,1

·SHECT TO PROVIOf SPECIFIED TRANSOUCER LOAOING BODE PLor OF RIAA fOUAlIl.ATION "NO THE BODE PLOT OF NAB hlUALlZA,110N "NO THE
OUTPUT NOISE 08,"'1/ It"' IWITH ' .... PUT SI10AtEOI RESPCNSf REALIZED IN AN ACtUAL t:IPCUIT REsPONS'E REALIZED IN THE A.ttUAl CIRCUIT USINC
USING THE XR-5534 THE XR-5!.3 •.
All RESISTOR VAlUlS ARE IN 0"''-1$

BAlANCE BALANCE/COMP COMPo

(SUBSTRATE I

EQUIVALENT SCHEMATIC DIAGRAM

5-61
5-62
 Section 5 - Industrial Circuits
Timers . . . . . . . . . . . . . . . . . . 5-63
Fundamentals of IC Timers . . . . 5-63
Choosing the Right IC Timer .. . 5-67
XR-320 Monolithic Timing Circuit 5-70
XR-555 Timing Circuit . . . . . . . 5-75
XR-L555 Micropower Timing Circuit 5-78
XR-556 Dual Timer . . . . . . . . 5-82
XR-L556 Micropower Dual Timer 5-85
XR-558/559 Quad Timing Circuits 5-91
XR-2556 Dual Timing Circuit . . . 5-95
XR-2240 Programmable Timer/Counter · 5-104
XR-2242 Long Range Timer . . . . . . · 5-112

II
XR-2243 Micropower Long Range Timer · 5-116

5-63
Fundamentals of Ie Timers
Monolithic timing circuits or timers find a wide variety ONE-SHOT OR SINGLE-CYCLE TIMERS
of applications in both linear and digital signal process-
ing. In a large number of industrial control or test se- One-shot or single-cycle timers operate by charging a
quencing applications, these circuits provide direct and timing capacitor through an external resistor or a cur-
economical replacement for mechanical or electro- rent source. The simplest form of the one-shot type tim-
mechanical timing devices. er is the "exponential-ramp generator" circuit shown in
Figure 1. Normally all the components except the Rand
Monolithic timers generate precise timing pulses, or the C shown in the Figure are internal to the IC, and the
time delays whose length or repetition rate is deter- switch 81 is a grounded-emitter NPN transistor includ-
mined by an external timing resistor, R, and a timing ca- ed in the IC chip.
pacitor, C. The timing interval is proportional to the ex-
ternal (RC) product, and can be varied from micro- The operation of the circuit can be briefly explained
seconds to minutes, days or months, by the choice of as follows: In the rest, or reset condition, the switch 81
the external Rand C. Integrated circuit timers can be is closed; and the voltage across the capacitor is
classified into two categories, based on their principle clamped to ground. The timing cycle is initiated by
of operation: applying an external trigger pulse to "set" the flip-flop
and to open the switch 81 across the timing capacitor.
1. One-Shot or Single-Cycle Timers: These timer IC's oper- The voltage across the capacitor rises exponentially to-
ate by charging an external capacitor with a current ward the supply voltage, VCC, with a time-constant of
set by an external resistor. Upon triggering, the RC. When this voltage level reaches an internally set
charging cycle happens only once during the timing threshold voltage, VREF, the voltage comparator
interval. The total timing interval, T, is the time dura- changes state, resets the flip-flops, closes the switch
tion necessary for the voltage across the capacitor 81, and end the !!.ming cycle. The output is taken from
to reach a threshold value. either the Q or Q terminal of the flip-flop and corre-
sponds to a timing pulse of duration 1; where:
2. Multiple-Cycle or Timer/Counters: These timer circuits
charge and discharge the external timing capacitor,
not once, but a multip/e number of times during the T = RC 1n [ VCC ] (1)
timing interval. The number of times the capacitor is VCC - VREF
charged and discharged is set by means of a pre-set Normally, the internal threshold voltage, VREF, is gener-
count, N, stored in a binary counter included on the ated from the supply voltage by means of a resistor di-
chip. Thus, the resulting time interval is proportional vider as shown in Figure 1. Then, VREF is equal to a
to N times the external (RC) product. fraction of the supply voltage:
80th the one-shot and the timer/counter type IC's can
be operated in either their monostable or free-running VREF = VCC [ R2 ] (2)
(Le., self-triggering) mode. They can also be used for R1 + R2
sequential timing, clock generation, as well as for
pulse-position or pulse-width modulation, as outlined in and the basic timing equation becomes independent of
Table I. the supply voltage:

Precision Timing T ~ RC 1n [ 1 + :~] (3)

Time-Delay Generation

Sequential Timing
Vee VFHF

Pulse Generation/Shaping r- --------,

Pulse-Position Modulation I
Pulse-Width Modulation

Missing-Pulse Detection I 1_'_1

1
Sweep Generation

Pulse Counting

Clock Generation
JLI'~1(~----
1_'_1 YL"'GGER

Table 1. Typical Applications of Monolithic Timers Figure 1. Exponential-Ramp Type Timing Circuit

5-64
Since the resistors R1 and R2 are inside the IC, their (PWM), or pulse-position modulated (PPM) signals, or
ratio is set by the design of the IC, and is normally ac- allows the timer circuit to be used as a voltage-
curate to within ± 1 %. Thus, virtually all the accuracy controlled oscillator.
of the timing interval is determined by the external R
and C. PRACTICAL LIMITATIONS OF ONE-SHOT TIMERS
An alternate approach to the design of one-shot timers The accurate timing intervals which can be obtained
is the "linear-ramp generator" circuit, shown in Figure from commercially available one-shot type timer IC's
2. This circuit operates on a principle similar to that of are limited to the range of several micro-seconds to
the basic exponential timer, except the timing capacitor several minutes. For generating very short timing
C is now charged linearly with a constant current, I, and pulses (in the few micro-second range) the internal time
generates a linear-ramp waveform with a constant delays associated with the switching speeds of the
slope of (IIC). The constant-current is in turn controlled comparator, the flip-flop and the discharge transistor
by an external control voltage, VC, applied to the cur- (Le., the switch S1) may contribute additional timing er-
rent source. The total timing interval, T, is the time nec- rors. Similarly, for long time delays (in the several min-
essary for the voltage across C to rise from ground to ute range) which require large values of Rand C, the in-
VREF, at a constant slope of (ltc), or: put bias current of the comparator, and the leakage cur-
rents associated with the timing capacitor, or the
T = (VREF)(CII) (4) internal discharge transistor, may limit the timing accu-
racy of the circuit.
Normally, VREF and Vc (and consequently I) would be
derived from VCC by means of resistor-dividers; there- In general, for timing applications requiring time delays
fore, they would be both proportional to VCC. Thus, the in excess of several minutes, the multiple-cycle or
effects of supply voltage variations cancel, and the ba- timer/counter type timer circuits provide a more eco-
sic timing equation for the linear-ramp type timer circuit nomical and practical solution than the one-shot type
of Figure 2 becomes IC timers.

T = ex RC
VCC
where ex is a constant of proportionality set by the inter-
nal resistor-dividers within the IC, and Rand C are the
external timing components.

The exponential-ramp type timing circuit of Figure 1 is

inherently simpler and more accurate than the linear-
ramp type circuit. However, the latter has the advan-
tage of providing a linear voltage across the capacitor
•
which is proportional to the elapsed-time during the tim-
ing cycle and can be used as a "linear sweep" or time-
base signal for oscilloscope or X-Y recorder displays.

Normally, the internal threshold reference, VREF. of JL(SOET_ _ _ _ _~

II-Tu-I
L
one-shot IC's is available as a package terminal and To· NT
can be modulated by an external input signal. This per-
mits the user to modulate or vary the timing interval by Figure 3. Simplified Block Diagram of a Timer/Counter
means of an external control signal. This feature can al-
so be used for generating pulse-width modulated

TIMER/COUNTER CIRCUITS
The timer/counter, or multiple-cycle timing circuits use
the combination of a time-base oscillator and a binary
1 counter to generate the desired time delay. Figure 3
I shows a simplified block diagram of a timer/counter IC,
I which is made up of three basic blocks: (1) a time-base
Vc

I
JL oscillator; (2) a binary counter; and (3) a control flip-flop.
I-T-I

(~'~----
With reference to the simplified block diagram of Figure
3, the principle of operation of a timer/counter can be
ACr! explained as follows: when the circuit is at rest, or reset

~
condition, the time-base oscillator is disabled, and the
1-,-1 ~RIGGER counter is reset to zero. Once the circuit is triggered,
the time-base oscillator is activated and produces a
series of timing pulses whose repetition rate is propor-
Figure 2. Block Diagram of a linear-Ramp Type Timer Circuit tional to external timing resistor R, and the capacitor

5-65
C. These timing pulses are then counted by the bi- ed by the binary counter; and when a given count, N, is
nary counter; and when a pre-programmed count is reached, the control flip-flop is latched in its reset con-
reached, the binary-counter resets the control flip-flops, dition until the next trigger input to the circuit.
stops the time-base oscillator and ends the timing cy-
cle. The total timing interval, TO, is then proportional In most timer/counter designs, it is convenient to set
to N times the (RC) product, where N is the pre- the ratio of resistors R1 and R2 such that:
programmed count.
(R1 + R2)
- - - = - = e = 2.718 ... (7)
r--~------------'---O Vee R1
", where "e" is the base of the natural logarithm. This
makes the period of the time-base oscillator directly
..... r -I equal to 1.0 RC and simplifies the selection of external
JLJl T • RC
R or C values for a given timer setting.

UNIQUE FEATURES OF TIMER/COUNTERS

The combination of a stable time-base oscillator and a
programmable binary counter on the same IC chip offer
some unique application and performance features.
Some of these are outlined below:

Generating Long Delays with Small Capacitors: For a given

Figure 4. Simplified Schematic of a Time-Base Oscillator time delay setting, the timer/counter would require a
Circuit timing capacitor, C, that is N times smaller than that
needed for the "one-shot" type timer, where N is the
Time-Base Oscillator: The time-base oscillator used in count programmed into the binary counter. Since large-
most of the timer/counter IC's is derived from the sim- value, low-leakage capacitors are quite expensive, this
ple exponential-ramp type timer circuit. Figure 4 shows technique may provide substantial cost savings for gen-
the simplified circuit diagram of such an oscillator. The erating long time delays in excess of several minutes.
timing components, Rand C, are external to the chip.
The operation of such an oscillator can be described as Generating Ultra-Long Delays by Cascading: When a cascad-
follows: when the circuit is at rest the flip-flop is latched ing two timer/counters, one cascades the counter stag-
in its reset state, and the transistor 01 is "off", the ex- es of both timers. Since the second timer/counter fur-
ternal capacitor C is fully charged to a voltage approxi- ther divides down the counter output of the first timer,
mately equal to VCC. When the circuit is triggered, the the total available count is Increased geometrically,
flip-flop is unlatched and set, which causes the dis- rather than arithmetically. For example, if one timer/
charge transistor 01 to turn "on" and discharge Crap- counter gives a time delay of NRC, two such timer/
idly. When the voltage across C discharges to the volt- counters cascaded will produce a time delay of N2 RC
age level VB, the comparator #2 changes state, resets where N is the count setting of the binary counter. Thus,
the flip-flop and turns 01 "off". Then, C charges toward a cascade of two timer/counter IC's, each with an 8-bit
VCC with a time constant set by the external Rand C. binary counter, can produce a time delay in excess of
When the voltage across it reaches the upper thresh- 32,000 RC.
old, VA, comparator #1 changes state and sets the flip-
flop again, and discharges C back to the lower thresh- Generating Multiple Delays From Same RC Setting: By using a
old level. VB. In this manner, the circuit continues to os- programmable binary counter, whose total count can
cillate, with the voltage level across C exponentially be programmed between a minimum count of 1, to a
rising to VA, then rapidly decaying to VB, and then re- maximum count of N, one can obtain N different time
peating Its cycle. The output of the circuit is a se- intervals from the same external RC setting.
quence of narrow pulses, with a repetition rate T, given
Easy to Set or Calibrate: Although timer/counters are nor-
as:
mally used for generating long time delays or intervals,
their accuracy characteristics are only determined by
T = RC In [1 + :~] (6) the characteristics of the time-base oscillator. The
counter section does not affect the over·all timing accu-
racy. Thus, time setting or calibration for long interval
where R1 and R2 are the internal bias resistors setting timing can be done quickly, without waiting for the en·
up the threshold levels VA and VB. The train of output tire timing cycle, by setting the accuracy of the time-
pulses coming out of the time-base oscillator are count- base oscillator.

5-66
Choosing the Right IC Timer
Because of its versatility, the monolithic IC timer offers Sequential Timing: Many timing applications require se-
a very wide range of applications in circuit or system quencing of timing functions, i.e., one timer completes
design. However, during the design phase, once the its operation and initiates the next timer, and so on.
"paper design" is accomplished, the user is faced with Since these applications require a multiplicity of timer
the key question: which IC timer is the best choice for a circuits, they are best served by dual-timer IC's, such
given application? If the performance characteristics as the XR-556 or the XR-2556.
and the limitations of the timer IC is not carefully con-
sidered, the total system performance may be degrad- Delayed Timing: Certain timing applications require that
ed; similarly, if the timing function is overspecified with the start of the timing pulse be delayed by a specific
an excessive amount of "overkill", particularly with re- time from the occurrence of the trigger. This can be
gards to its stability and accuracy requirements, then easily accomplished by using a dual-timer, such as the
the system cost will increase unnecessarily. XR-556, where one section of the dual-timer can be
used to set the initial "delay" subsequent to the trigger;
The key selection criteria in choosing the right timer for and the second section can be used to generate the ac-
the job is finding the monolithic IC which will result in tual timing pulse.
the lowest system cost (including the external compo-
nents) for a given performance requirement. Event Counting: In such an application, one needs to
keep an accurate count of "events" which are normally
A very large majority of applications for IC timers can a series of incoming pulses. This function can be easily
be classified into one of the four categories listed be- performed with a programmable timer/counter IC, such
low: as the XR-2240, where the binary counter section can
• Interval or Event Timing be programmed to count a given number of input
• Pulse Generation and Shaping pulses and stop the count, and/or reset the circuit when
• Oscillation or Clock-Generation the programmed count is reached. In the case of the
• Ramp Generation XR-2240, the existing count in the counters is displayed

•
in a 8-bit parallel binary-format.
These categories of applications are discussed in more
detail in the following sections, with the particular em- Digitally·Programmed Timing: Some timing applications
phasis on "choosing the right IC timer" for the particu- may require that the timing interval be digitally pro-
lar application. grammable, without switching additional precision re-
sistors and capacitors into the circuit. Such a function
INTERVAL OR EVENT TIMING can be easily achieved by using a programmable timer/
counter, such as the XR-2240, where output duration
In such an application one uses the IC timer either to can be programmed from 1.0 RC to 255 RC, in 1 RC in-
control the time interval between events, or the dura- crements, where Rand C are the external timing com-
tion of an event. A typical example of such application ponents.
would be to control the opening or closing of an electro-
mechanical relay or sequencing of indicator lights. PULSE GENERATION AND SHAPING
General Purpose Timing: Most timing applications fall with- A popular class of applications for the one-shot type
in the time interval range of a few microseconds to sev- timers is pulse shaping or stretching. Some specific ex-
eral minutes. For such applications the basic one-shot amples of such applications and the recommended
timer, such as the XR-555, is often the best choice, types of IC timers for each are given below.
based on its low cost and versatility.
Pulse Stretching: In such an application the IC timer is
Low·Power Timing: Many timing applications involving operated in its monostable mode and is triggered by an
battery-operated or portable equipment, require a low- input series of pulses, whose repetition period is longer
power timer which can perform the general purpose than that timing period of the IC. The output from the
timing functions with a minimum amount of power dissi- timer will then have the same repetition rate as the in-
pation. The XR-L555 Micropower Timer IC, which oper- put pulse train, except that each output pulse will now
ates with less than 1 mW of power dissipation and with have a uniform duration or length, as set by the RC time
supply voltages as low as 2.7 volts, is especially de- constant of the timer. The two IC's best suited to this
signed for such applications. application are the XR-555 and the XR-320. The XR-555
has the advantage of low unit price, whereas the
Long Interval Timing: For timing applications requiring in- XR-320 has the advantage of being able to trigger on
terval timing in the minutes, hours, or days range, the either positive- or negative-going edge of the input
timer/counter IC's present the most economical ap- pulses.
proach, since they can produce long time delays using
a small value capacitor. For such an application of the Delayed·Pulse Generation: In this application it is neces-
low-cost XR-2242 Long Range Timer, which operates sary to convert the input pulse train to a different pulse
on the timer/counter principle, is the most cost- sequence which has the same repetition rate but a dif-
effective circuit. ferent duration and a different phase. This function can

5·67
be accomplished with a dual-timer circuit, such as the Micropower Oscillator: Battery operated or remote-con-
XR-556 or the XR-2556, where the first timer which is trolled instruments often require a low-power clock os-
triggered by the input signal, sets the phase difference cillator. The XR-L555 Micropower Timer, which operates
or "delay" between the input and the output pulse se- with less than 1 mW of power drain, is the recom-
quence; and the second timer which is triggered at the mended choice for such applications, since it dissi-
trailing-edge of the first one, sets the output pulse- pates 1/15th the power of the conventional 555-type
width. timer.

Pulse Blanking: In this application it is necessary to se- Voltage-Controlled Oscillator: Voltage-controlled oscillator
lectively "interrupt" or "blank-out" a pulse train. Such (VCO) circuits find a wide range of applications in
an application can be performed using a dual-timer IC, phase-locked loop systems. The XR-555 (or its low-
such as the XR-556, where one section of the timer can powerllow-voltage version of the XR-L555) which has a
be operated as a "pulse-stretcher" triggered by the in- separate modulation terminal (Pin 5) can be used as a
put pulse train; and the second timer section can be VCO by applying the proper control voltage to its modu-
triggered by a separate timing signal and serve as an lation terminal and operating the IC in its self-triggering
enable/disable control for the first timer, thus interrupt- mode.
ing or "blanking" its output during its timing interval.
Low-Voltage Oscillator: Low threshold CMOS logic circuits
Pulse-Width Modulation: In certain timing applications it is normally require stable clock oscillators which can op-
necessary to modulate the pulse-width of an output erate with a Single 3 volt supply. The XR-L555 Micro-
pulse sequence, without affecting its repetition rate. power Timer which can operate with supply voltages as
Such a requirement can be met by a one-shot timer, low as 2.7 volts is particularly suited for such applica-
such as the XR-555, operating in its monostable mode tions.
and being triggered by a fixed-frequency input pulse-
train. The width of the output pulses from the timer IC Ultra-Low Frequency Oscillator: Certain battery operated or
can be modified without affecting the repetition rate, by remote-controlled equipment require a stable ultra-low
simply applying a control-voltage to the modulation ter- frequency clock oscillator, whose frequency can be as
minal of XR-555. low as one cycle per day. The XR-2242 Long-Range
Timer circuit which produces a square-wave output
Pulse-Position Modulation: This application requires the with a period of 256 RC, when operating in its free-
generation of a pulse sequence whose pulse-width is running mode, is a very cost-effective replacement for
constant (and usually very narrow) and, whose repeti- such an oscillator.
tion rate is modulated. Such a function can be easily
implemented using a dual-timer IC, such as the XR-556, Digitally-Programmed Oscillator: In certain applications it
where the second timer generates the narrow output may be necessary to program the frequency of an os-
pulses when triggered by the output of the first timer. cillator by means of a binary control signal, without
The first timer section is then operated in its free- switching additional resistors or capacitors into the cir-
running (I.e., astable) mode and its frequency is then cuit. The XR-2240 Programmable Timer/Counter, when
externally modulated by applying a control-voltage to its operating in its delayed-trigger mode (see Exar Applica-
modulation terminal. tion Note AN-O?) can be used in such an application to
generate an output frequency whose period is equal to
OSCILLATION OR CLOCK·GENERATION (N + 1)RC, where N is the binary count which can be
digitally programmed by an external 8-bit binary Signal,
IC Timers can be operated in their free-running or "self- to be any integer between 1 and 255.
triggering" mode, to generate periodic timing pulses.
Since the output pulse-width or the frequency can be Binary Pattern Generator: In certain test instrumentation
controlled by the choice of external resistors and ca- design, it is necessary to generate a pseudorandom bi-
pacitors. These circuits make excellent low-cost clock nary data pattern, which would then repeat itself peri-
oscillators, for a number of digital systems. Some of odically. The XR-2240 Programmable Timer/Counter
these applications are outlined below. which provides eight separate "open-collector" out-
puts, can perform such a function by selective shorting
Clock Generator: In such applications, the IC is used to of one or more of its outputs to a common pull-up resis-
generate a fixed-frequency output waveform with nearly tor.
50% duty cycle. The XR-555 timer, whose output duty-
cycle can be controlled by the choice of two external Tone-Burst Generator: Some instrumentation applications
resistors, is ideally suited for such an application, for require the generation of a certain tone or frequency
clock frequencies up to 300 kHz. signal, at periodic intervals. This function can be ac-
complished using a dual-timer IC, such as the XR-556
High-Current Oscillator: Certain oscillator applications re- or the XR-2556, where one of the timer sections would
quire that the circuit output should be able to source or operate as a keyed oscillator which is turned "on" and
sink high load currents (~ 100 mA) in order to drive "off" by the other timer section. The output of the first
electromechanical relays or capacitive loads. The timer section will then be a "tone-burst", which will be
XR-555 Timer IC, which can provide up to 200 mA of present only during the timing cycle of the second timer.
current drive, is well suited for such applications.

5-68
RAMP GENERATION from the ground level and rises up to a voltage level ap-
proximately equal to 80% of the supply voltage, during
In a number of timing applications, it is necessary to the timing interval. Since the current-source output at
generate an analog voltage which is proportional to the Pin 3 is a high impedance terminal, the sweep or linear
time elapsed during the timing cycle. This function is ramp signal at this point should be buffered by a high
particularly useful for generating linear sweep voltage impedance op amp connected as a voltage follower.
for oscilloscope or X-V recorder display applications amp connected as a voltage follower.
and it can be accomplished either linear/y or digitally,
as described below. Digital Ramp Generator: In certain applications, a digitally
generated "staircase" voltage is preferred over a linear
ramp signal. Such a digital ramp signal can be gen~r­
Linear Ramp Generator: A linear ramp can be obtained by ated using the XR-2240 Programmable Timer/Counter,
charging a timing capacitor with a constant-current along with an external resistor ladder and a current-
source. Since the XR-320 Timer IC operates on such a summing op amp. The digital ramp signal is particularly
principle, it is ideally suited for this application. Upon useful for analog-to-digital conversion or digital sample-
triggering, the XR-320 produces a positive-going ramp and-hold applications.
at its current-source output (Pin 3). This ramp starts tions.

5-69
 XR-320

Monolithic Timing Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-320 monolithic timing circuit is designed for use XR-320
in instrumentation and digital communications equip-
CURRENT
ment, and for a wide variety of industrial control and SOURCE
special testing applications. In many cases, this circuit INPUT
provides a monolithic replacement for mechanical or
electromechanical timing devices.
The XR-320 timing circuit generates precise timing CURRENT HIGH
SOURCE CURRENT
pulses (or time delays) whose repetition rate (or length) OUTPUT OUTPUT
is determined by an external timing resistor, R, and tim-
ing capacitor, C. The timing period is exactly equal to
2RC and can be continuously varied from 1 Ilsec to 1 SET 1
(NEGATIVE·
hour. The circuits can be operated in a monostable or GOING LOGIC
OUTPUT
free-running (self-triggering) mode. They can be used TRIGGERI
for sequential timing and sweep generation, and also SET 2
(POSITIVE·
for pulse-position and pulse-width modulation. GOING
TRIGGERI
The XR-320 integrated circuit is comprised of a stable
RESET GROUND
internal bias reference, a precision current source, a
voltage comparator, a flip-flop, a timing switch, and a
pair of output logic drivers. The high current output at ORDERING INFORMATION
pin 12 can sink or source up to 100 milliamps of cur-
rent. Part Number Package Operating Temperature
FEATURES XR-320P Plastic O°C to + 70°C
Wide Timing Range: 1 Ilsec to 1 hour
High Accuracy: 1 % SYSTEM DESCRIPTION
Excellent Temperature Stability: 100 ppm/oC
Wide Supply Voltage Range: 4.5V to 18V The XR-320 is an extremely versatile monolithic timer
Triggering with Positive or Negative-Going Pulses capable of delays ranging from 1 Ilsec to 1 hour. It
Programmable works with both positive and negative triggering, and
Resistor Programming: 3 decades features both normally high and normally low outputs.
Capacitor Program: 9 decades' An on board current source, programmable by an ex-
Logic Compatible Outputs ternal resistor, changes the timing capacitor. This pro-
High Current Drive Capability: 100 mA duces a true ramp function and allows accurate timing
intervals equal to 2 RC.
APPLICATIONS
Precision Timing Positive going triggering is applied to Pin 6; negative
Time-Delay Generation triggering is applied to Pin 5. After a trigger pulse is ap-
Sequential Timing plied, the open collector output (Pin 10) will go high and
Pulse Generation/Shaping the high current output (Pin 12) switches into the cur-
Pulse-Position Modulation rent sink mode. At timeout, the open collector pulls low,
Pulse-Width Modulation and can sink 10 mA; the high current output goes high
Sweep Generation and can source 100 mA. Utilizing the high current out-
put requires a pull-up resistor from Pin 10 to +VCC·
ABSOLUTE MAXIMUM RATINGS The resistor must limit current to no more than 10 mA;
1 mA is sufficient. Timing is interrupted and the device
Power Supply 18 volts is reset when Pin 7 is grounded. Astable operation is at-
Internal Power Dissipation 750 mW tained by tying the negative going (falling) trigger (Pin 5)
Plastic Package: 625mW to the timing capacitor (Pin 3). In this configuration, the
Derate above TA = + 25°C 5 mW/oC device will automatically retrigger itself upon comple-
Storage Temperature Range - 65°C to + 150°C tion of the timing interval.

5-70
 XR·320
ELECTRICAL CHARACTERISTICS
Test Conditions: Supply Voltage = 12V ±S%, Test Circuit of Figure 2, TA 25°C, unless otherwise specified.

XR-320
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Supply Voltage 4.5 18 Vdc
Quiescent Supply Current
V+ = 5V 2.0 3.5 mA
V+ = 12V 6.0 7.0 mA
V+ = 18V 10.0 12.5 mA
Timing Cycle Supply Current
V+ = 5V 2.5 4.0 mA
V+ = 12V 6.5 8.0 mA
V+ = 18V 12.0 14.0 mA
Timing Accuracy
V+ = 5V 1.0 5.0 %
V+ = 12V 1.0 5.0 %
V+ = 18V 1.0 5.0 %
Temperature Drift 100 ppm/oC
Timing vs. Supply Voltage 0.1 0.5 %IV
Stand-by Voltage (Pin 3) 0.7 V
Comparator Threshold

•
Voltage (Pin 3)
V+ = 5V 2.4 V
V+ = 12V 4.5 5.2 6.0 V
V+ = 18V 8.4 V
Current Source Input
Voltage (Pin 1)
V+ = 5V 4.15 V
V+ = 12V 9.0 9.75 10.6 V
V+ = 18V 16.15 V
Trigger Voltage
Set (Pin 5) 1.0 1.5 V See Figure 11
Set 2 (Pin 6) 0.5 1.4 V See Figure 12
Reset (Pin 7) 0.7 1.5 V
Trigger Current
Set 1 (Pin 5) 10 p.A
Set 2 (Pin 6) 60 p.A
Reset (Pin 7) 30 p.A
Output 1 (Pin 10) (Normally low)
"Low" Voltage 0.1 V
"High" Voltage 4.0 5.0 V
Rise Time 140 nsec
Fall Time 50 nsec
Output 2 (Pin 12) (Normally high)
"High" Voltage 10.4 V Isource = 100 mA
"Low" Voltage 1.5 V Isink = 100 mA
Rise Time 100 nsec
Fall Time 40 nsec

DEFINITIONS
Timing Accuracy: the timing error solely introduced by the XR-320. defined in per cent Stand-by Voltage: the voltage between pin
as: 3 and ground in reset
condition.
measured timing 2 RC based on actual Comparator Threshold
100 X _,,-p_ul_se_le_ng,,-t_h_-_co_m-,p_o_n_en_t_v_al_u_es_ % Voltage (Pin 3): the voltage at which the
2 RC based on actual component values internal comparator trig-
gers the flip-flop and the
Timing vs Supply
timing capacitor dis-
Voltage: the maximum timing drift over the power supply range of 5 to 18 volts
charges.
referenced to 12 volt operation, defined in per cent per volt as:
Trigger Voltage: the DC voltage level ap-
max. timing pulse length min. timing pulse length plied to each set or re-
100 X over 5 to 18 volt supply -over 5 to 18 volt supply 'ioN set terminal which
15 timing pulse length with 12 volt supply causes the output to
change state.

5-71
XR·320

EQUIVALENT SCHEMATIC DIAGRAM

OPERATING INSTRUCTIONS
R'I00K

Figures 2 and 3 show typical connections for the XA-

320. Only three external components are required for
~-+--o OUT'UT l basic operation: the resistor A and capacitor C which
~-~-oOUTNT 1
determine the time delay (2AC); and an external load re-
sistor, AL. The circuit provides two independent logic
sn 2 outputs: a medium current output (up to 10 mA) at pin
RUET 10, and a high current output (up to 100 mA) at pin 12.
The output at pin 10 is of the "bare-collector" type
which requires an external PUII-U~ resistor, AL, connect-
Figure 1. Test Circuit ed between this terminal and V for proper circuit op-
eration.

R
With no trigger pulse applied, the output at pin 10 is in a
low state near ground potential; and the output at pin 12
is in a high state, near V +. The circuit is triggered by
1---+--o0UTPUT 2 the application of a negative-going pulse to pin 5 or a
SET I 1 - - - - - 0 OUTPUT I
positive-going pulse to pin 6. At that instant, the output
levels change state such that pin 10 becomes high and
pin 12 low. The outputs will remain in this (switched)
state until the delay time, T = 2AC, expires, at which
time the outputs will return to their original state. In this
, mode of operation, the trigger input can be activated re-
v'
peatedly without further influenCing the time cycle, i.e.,
Figure 2. Monostable Operation, Negative Trigger once the circuit is triggered it becomes immune to sub-
sequent triggering until the entire timing cycle is com-
pleted.
R

For reliable operation, the trigger pulse width must he

shorter than the output pulse width. Although many
1---+---0 OUTPuT 2 units will function when this rule is not observed, proper
10
1 - - - - - 0 OUTPUT T operation cannot be guaranteed.
6
v.
1
S~T2M
7 8
Figure 4 shows the waveforms at various circuit loca-
RESET ':' tions for a negative-going trigger applied to pin 5. A sim-
Iv' ilar set of waveforms is displayed in Figure 5 for a
positive-going pulse applied to pin 6. The timing cycle
Figure 3. Monostable Operation, Positive Trigger can be reset at any time by simply grounding pin 7.

5-72
 XR·320
Iy high will go low. See Figure 11 for additional details.
r-------~ SET 1 When not used, pin 5 should be connected to V + to
INPUT (PIN 5) avoid false triggering.
VOLTAGE ACROSS By grounding or applying a negative pulse to the reset
TIMING CAPACITOR
(PIN 3) (Pin 7), the timing cycle is automatically interrupted and
OUTPUT 1
the outputs return to their original state. When the reset
(PIN 10) function is not in use, it is recommended that it be con-
nected to V + to avoid any possibility of false resetting.

Figure 4. Waveforms for Negative-Going Trigger SET 2 - POSITIVE TRIGGER (PIN 6)

A positive-going pulse applied to pin 6 will cause the

SET 2
outputs to change state. The normally low output at pin
' - - - - - - - - - - l INPUT (PIN 6) 10 will go high, and the normally high output at pin 12
will go low. See Figure 12 for additional details. When
VOLTAGE ACROSS
TIMING CAPACITOR not used, pin 6 should be grounded to avoid false trig-
(PIN 3) gering.
OUTPUT 1
(PIN 10) ADDITIONAL APPLICATIONS
FREE-RUNNING MODE
Figure 5. Waveforms for Positive-Going Trigger
By shorting pins 3 and 5, the XR-320 will operate in a
"free-running" or self-triggering mode. In this mode of
DESCRIPTION OF CIRCUIT CONTROLS operation, the circuit functions as a stable clock pulse
generator with a repetition rate of approximately 11
TIMING RESISTOR (PIN 1)
(2RC). The circuit connection and free-running frequen- •
Timing resistor, R, is connected between pin 1 and V + , cy in this application are shown in Figure 7. Note that
pin 14. For maximum timing accuracy, R should be in one cycle is not precisely equal to 2RC because of ca-
the range 6 kO :s R :s 1 MO. See Figure 6 for the mini- pacitor discharge time. Typical waveforms for self-
mum and maximum values for R for various supply volt- triggered operation are shown in Figure 8.
ages.
~ 100 Ml! r---r--.--,....-"""'T--.----.
z lA' 25 C
<I

! [==Ji@i~~~~~[J
~
u
<I
10 Mil
lMI!

rr.'
rr.' 100 Kl!
~ O.OOII--+--+-~+-~+-~

~.., lOKi!
z 10 100 lK 10K
~ 1 Kl! L-..-...I.._~_l....---L_...L----I FREE RUNNING FREOUENCY IHII
a 12 16 20 24
SUPPL Y VOL lAGE IVOL lSI
r-----\fV'I.o---...-+---o v'
Figure 6. Operating Range as a Function of Timing Resistor
and Supply Voltage
I--+--<l OUTPUT 2
I--f>--o OUTPUT 1
TIMING CAPACITOR (PIN 3)

Timing capacitor, C, is connected between pin 3 and

ground. The time delay, T, is equal to 2RC in seconds.
NOTE: A timing error can result due to the leakage cur- Figure 7. Free-Running Operation
rent of the timing capacitor. When a capacitor with a
VOLTAGE ACROSS
relatively low insulation resistance (e.g. a high·valued TIMING CAPACITOR
electrolytic) is used as the timing capacitor, the result- (PIN 3)
ing delay time will be much longer than 2RC because of
the associated leakage current. r----,,-~ OUTPUT 1
(PIN 10)
SET 1 - NEGATIVE TRIGGER (PIN 5) OUTPUT 2
......._..IL.~ (PIN 12)
A negative-going pulse applied to pin 5 will cause the
outputs to change state. Output 1, pin 10, which is nor-
mally low will go high, Output 2, pin 12, which is normal- Figure 8. Waveforms for Self-Triggered Operation

5-73
 XR·320
SWEEP GENERATION 70~----~--~----~----~-----.
In self·triggered operation, the waveform across the
timing capacitor (at pin 3) is a linear ramp as shown in
Figure 8. The waveform at pin 3 can be used as a highly
linear sweep voltage with a total nonlinearity of less
than 1 %. :z: 50~----+-----~----r---~~----i
I-
o
~ 40~--~----~--
PULSE-WIDTH MODULATION w
c.')
-'
For this application, the XR·320 should be connected ~ 30 t----+---~Il--
as shown in Figure 9.
:l!
The modulation input is applied to pin 1 through coup· i 20~--~~~-+~--~~---~--~
ling capacitor, ee. The input signal modulates the cur· Z
rent through the timing resistor, R, and, in turn, changes
the width of the output timing pulses. The resistor RM, i 10 t-----+-----+-----+------+.----4
in series with the signal source, is used to control the
O~ __~~ __
~ ____ ____ ____. J
~ ~

amount of modulation for a given input signal level.

o 0.25 0.5 0.75 1.0 1.25
VOL TAGE LEVEL AT PIN 5 (VOLTS)
R

Figure 11. Minimum Pulse Width for Triggering at Pin 5

t--+-<> OUTPUT 2
1---+-<> OUTPUT 1

Figure 9. Circuit Connection for Pulse-width Modulation

6% I
70

\, TA· 25 C

i
60

\.~. ~ \
~\\~ :z:F.o
'..,..
w ~'l"K ~
~-
t-
O
i40 \~
~ '~'rl ~~,...--
c(
:z:
o ,
.......
~
-'30 \ '\
u ...... -"'"
~C'
i!
~ -2%
w
u
s
=»20
' ~
a: :E
Z ~\ \ \
~ -4% ~
i 10
(\1
-6% o
2.5 5 10 _ 15 20 o O.S 1.0 1.S 2.0 2.5
SUPPL V VOL TAGE·CVOL TS) VOL TAGE LEVEL AT PIN. (VOL TS)

Figure 10. Change In Timing VS, Supply Voltage Figure 12. Minimum Pulse Width for Triggering at Pin 6

5-74
 XR-555

Timing Circuit
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-555 monolithic timing circuit is a highly stable XR 5S5

controller capable of producing accurate timing pulses.

It is a direct, pin-for-pin replacement for the SEINE 555
timer. The circuit contains independent control termi-
nals for triggering or resetting if desired.

In the monostable mode of operation, the time delay is

controlled by one external resistor and one capacitor.
For astable operation as an oscillator, the free-running
frequency and the duty cycle are accurately controlled
with two external resistors and one capacitor (as
shown in Figure 2).
ORDERING INFORMATION
The XR-555 may be triggered or reset on falling wave-

•
forms. Its output can source or sink up to 200 mA or Part Number Package Operating Temperature
drive TIL circuits.
XR-555M Ceramic - 55°C to + 125°C
FEATURES XR-555CN- Ceramic O°C to + 70°C
XR-555CP Plastic O°C to + 70°C
Direct Replacement for SEINE 555
Timing from Microseconds Thru Hours SYSTEM DESCRIPTION
Operates in Both Monostable and Astable Modes
High Current Drive Capability (200 mA) The XR-555 is an industry standard timing circuit capa-
TIL and DTL Compatible Outputs ble of both monostable and astable operation with tim-
Adjustable Duty Cycle ing intervals ranging from low microseconds up
Temperature Stability of 0.005%/OC through several hours. Timing is independent of supply
voltage, which may range from 4.5 V to 18 V. The out-
APPLICATIONS put stage can source or sink 200 mA.
Precision Timing In the monostable (one shot) mode, timing is deter-
Pulse Generation mined by one resistor and capacitor. Astable opera-
Sequential Timing tions (oscillation) requires an additional resistor, which
Pulse Shaping controls duty cycle. An internal resistive divider pro-
Clock Generation vides a reference voltage of 2/3 VCC, which provides a
Missing Pulse Detection timing interval of 1.1 RC. As the reference is related to
Pulse-Width Modulation VCC, the interval is independent of supply voltage; how-
Frequency Division ever, for maximum accuracy, the user should ensure
Pulse-Position Modulation Vec does not vary during timing.
Appliance Timing
The output of the XR-555 is high during the timing inter-
ABSOLUTE MAXIMUM RATINGS val, and pulls low at timeout. It ;s triggered and reset on
falling waveforms. The control voltage input (Pin 5) may
Power Supply 18 volts serve as a pulse width modulation point.
Power Dissipation (package limitation)
Ceramic Package 385 mW For applications requiring dual matched 555-type tim-
Plastic Package 300 mW ers, see the XR-556 and XR-2556. For low voltage andl
Derate above + 25°C 2.5 mW/oC or low power drain applications, consider the XR-L555
Storage Temperature -65°C to + 125°C and XR-L556 devices.

5-75
XR·555
ELECTRICAL CHARACTERISTICS
Tast Conditions: (TA = 25 De, Vee = + 5V to + 15V, unless otherwise specified.)

XR-555M XR-555C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
Supply Voltage 4.5 18 4.5 16 V
Supply Current Low State Output (Note 1)
3 5 3 6 mA Vee = 5V, RL = 00
10 12 10 15 mA Vee = 15V, RL = 00
Timing Error (Monostable) RA, RS = 1 KO to 100 KO
Initial Accuracy 0.5 2.0 1.0 3.0 % Note 2, e = 0.1 I'F
Drift with Temperature 30 100 50 ppm/DC ODe s TA s 75 De
Drift with Supply Voltage 0.05 0.2 0.1 0.5 %N
Timing Error (Astable) RA, RS = 1 KO to 100 KO
Initial Accuracy (Note 2) 1.5 2.25 % e = 0.1 I'F
Drift with Temperature 90 150 ppm/oe Vee = 15V
Drift with Supply Voltage 0.15 0.3 %N
Threshold Voltage 9.4 10.0 10.6 8.8 10.0 11.2 V Vee = 15V
2.7 3.33 4.0 2.4 3.33 4.2 V Vee = 5V
Trigger Voltage 1.45 1.67 1.9 1.67 V Vee = 5V
4.8 5.0 5.2 5.0 V Vee = 15V
Trigger Current 0.5 0.9 0.5 2.0 I'A
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V Trigger Input High
Reset Current 0.4 1.0 0.4 1.5 mA
Threshold Current 0.1 0.25 0.1 0.25 I'A (Note 3)
Control Voltage level 2,7 3.33 4.0 2.4 3.33 4.2 V Vee = 5V
9.4 10.0 10.6 8.8 10.0 11.2 V Vee = 15V
Output Voltage Drop (Low) Vee = 5V
0.10 0.25 0.3 V Isink = 8.0 mA
0.05 0.2 0.25 0.35 V Isink = 5.0 mA
Vee = 15V
0.1 0.15 0.1 0.25 V Isink = 10 mA
0.4 0.5 0.4 0.75 V Isink = 50 mA
2.0 2.2 2.0 2.5 V Isink = 100 mA
2.5 2.5 V Isink = 200 mA
Output Voltage Drop (High) Isource = 100 mA
3.0 3.3 2.75 3.3 V Vee = 5V
13 13.3 12.75 13.3 V Vec = 15V
Isource = 200 mA
12.5 12.5 V Vee = 15V
Turn Off Time (Note 4) 0.5 0.2 0.5 I's VRESET High
Rise Time of Output 100 200 100 300 nsec
Fall Time of Output 100 200 100 300 nsec
Discharge Transistor Leakage 20 100 20 100 nA
Ncte1: Supply current 'vvhen output is high is typically 1.0 rnA less.
Nota 2: Tested at Vee = 5V and Vee = 15V.
Note 3: This will determine the maximum value of RA + RS for 15V operation. The maximum total R = 20
megohms and for 5V operation, the maximum RT = 3.4 megohms.
Note 4: Time measured from a positive-going input pulse from 0 to 0.8 x Vee into the threshold to the drop from
high to low of the output. Trigger is tied to threshold.

5-76
 S CONTROL
XR·555
.vccOs----~--------~------~~--~--------~~+-------------~--1---~------~
Rl R3 R4 R7 R12
4.7K 4.7K lK SK 6.SK

09

R13
3.9K

THRESHOLD RIO
7K 3
OUTPUT
0 23

RS
5K

TRIGGER o------lf--------+----.r

O/SCHARGE 0---..., RS R6 R9
10K lOOK SK
1
GND~

•
I

EQUIVALENT SCHEMATIC DIAGRAM

r-------~--_.--O +Vee
r---~--~----~-o +Vee
T - 1.1 RAe

JL OUTPUT o-~::>---t 1fi.f OUTPUT

r-T--j XR555

CONTROL

lJ TRIGGER 0--<:>---;
0.01 ~F
I NPUT

f=-·-~
o-~::>---t

IRA + 2R B IC
I-=- CONTROL
VOLTAGE
RB
DUTY CYCLE = RA + 2RB

Figure 1. Monostable (One-Shot) Circuit Figure 2. Astable (Free-Running) Circuit

5·77
 XR·L555

Micropower Timing Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-L555 is a stable micropower controller capable

of producing accurate timing pulses. It is a direct re-
placement for the popular 555-timer for applications re-
quiring very low power dissipation. The XR-L555 has
approximately 1/15th the power dissipation of the stan-
dard 555-timer and can operate down to 2.7 volts with-
out sacrificing such key features as timing accuracy
and frequency stability. At 5-volt operation, typical
power dissipation of the XR-L555 is 900 microwatts.

The circuit contains independent control terminals for

triggering or resetting if desired. In the monostable
mode of operation, the time delay is controlled by one ABSOLUTE MAXIMUM RATINGS
external resistor and one capacitor. For astable opera- Power Supply 18 volts
tion as an oscillator the free-running frequency and the Power Dissipation (package limitation)
duty cycle are accurately controlled with two external Ceramic Package 385 mW
resistors and one capacitor as shown in Figure 2. The Plastic Package 300 mW
XR-L555 is triggered or reset on falling waveforms. Its Derate above + 25°C 2.5 mW/oC
output can source up to 100 mA or drive TIL circuits. Storage Temperature - 65°C to + 125°C

Because of its temperature stability and low-voltage ORDERING INFORMATION

(2.7V) operation capability, the XR-L555 is ideally suited Part Number Package Operating Temperature
as a micropower clock oscillator or VCO for low-power
XR-L555M Ceramic -55°C to +125°C
CMOS systems. It can operate up to 1500 hours with
only two 300 mA-Hr batteries. XR-L555CN Ceramic DoC to + 70°C
XR-L555CP Plastic DoC to + 70°C
SYSTEM DESCRIPTION
FEATURES The XR-L555 is a micropower timing circuit similar to
the industry standard 555-type timer. It is capable of
Pin Compatible with Standard 555 Timer
both monostable and astable operation with timing in-
Less than 1 mW Power DisSipation (V + = 5V)
tervals ranging from low microseconds up through sev-
Timing from Microseconds to Minutes
eral hours. Timing is independent of supply voltage
Over 1000-Hour Operation with 2 Batteries
which may range from 2.7 V to 15 V. The output stage
Low Voltage Operation (V + = 2.7V)
can sou rce 50 mA.
Operates in Both Monostable and Astable Modes
CMOS TIL and DTL Compatible Outputs In the monostabie (one shot) mode, timing is deter-
mined by one resistor and capacitor. Astable operation
(oscillation) requires an additional resistor, which con-
trols duty cycle. An internal resistive divider provides a
APPLICATIONS reference voltage of 2/3 VCC, the interval is indepen-
dent of supply voltage; however, for maximum accu-
Battery Operated Timing
racy, the user should ensure VCC does not vary during
Micropower Clock Generator timing.
Pulse Shaping and Detection
Micropower PLL Design The output of the XR-L555 is high during the timing in-
Power-On Reset Controller terval. It is triggered and reset on falling waveforms.
Micropower Oscillator The control voltage input (Pin 5) may serve as a pulse
Sequential Timing width modulation pOint.
Pulse Width Modulation
Appliance Timing For applications requiring dual L555-type timers, see
Remote-Control Sequencer the XR-L556.

5-78
 ELECTRICAL CHARACTERISTICS
XR·L555
Test Conditions: (TA == 2SoC, VCC == + SV, unless otherwise specified.)

XR-L555M t XR-L555C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
Supply Voltage 2.7 1S 2.7 1S V
Supply Current Low State Output
1S0 300 190 SOO p,A VCC == SV, RL == 00

Timing Error RA, RS == 1 KO to

100 KO
Initial Accuracy O.S 2.0 1.0 % C == 0.1 p,F
Drift with Temperature 30 100 SO ppm/oC O°C ~ TA ~ 75°C
Drift with Supply Voltage 0.05 0.05 %IV
Threshold Voltage 2/3 2/3 x VCC
Trigger Voltage 1.45 1.67 1.9 1.67 V VCC == 5V
4.8 5.0 5.2 S.O V VCC == 15V
Trigger Current 0.5 0.5 p,A
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Current 0.1 0.1 mA
Threshold Current 0.1 0.25 0.1 0.25 p,A

•
Control Voltage Level 2.90 3.33 3.80 2.60 3.33 4.00 V VCC == 5V
9.6 10.0 10.4 9.0 10.0 11.0 VCC == 15V
Output Voltage Drop (Low) 0.1 0.3 0.25 0.35 V Isink == 1.5 mA
Output Voltage Drop (High) Isource == 10 mA
3.0 3.3 2.75 3.3 V VCC == 5V
13 13.3 12.75 13.3 V VCC == 15V
Isource == 100 mA
12.5 12.5 V VCC == 15V
Rise Time of Output 100 100 nsec
Fall Time of Output 100 100 nsec
Discharge Transistor 0.1 0.1 p,A
Leakage

t Tested only at 25°C

~-----'---'--O+VCC

OUTPOU~T~b3~~_____. ,
~OUT~P_U_T~_3~
LnI
f---l--j XR-L555 t--o----,
TRIGGER 2

If
CONTROL
INPUT ""'---"-""'-_..,.---1

f = 1.46
O.0 1 IJ F + 2R S )C
I-= CONTROL
VOLTAGE DUTY CYCLE = RA
(R A

RS
+ 2RS

Figure 1. Monostable (One-Shot) Circuit Figure 2. Astable (Free-Running) Circuit

5-79
XR·L555 CHARACTERISTIC CURVES
GENERAL CHARACTERISTICS
400 1200 1200
360 A 1100 TA - +2sbc III v
cF
-SV+. I
I TA-~>
10 l/1
-,
I I ) ~Io. ~ 1000 I ~1000
320 -' -- - TA - -25 ;;; ~TA - U5.~
JJ -r J
~~ 280 ~ ~ 900
I I I
. . . .v ~ 800
I
vce - 2.SV II > 800 f-~ A- +25 O W
~ 240
!5 200 r- If V ~ ~ . . . .
a: ......v
......
/'
~ 700 l
1/ V
~
c
C
--"""'
---:::: ~ --2S"C-

~v ~ GOO Z 600
u
" f- j
V- ,- / P" TA ··7SC-
0
~ 160
.. f - ::IE 500 i=
120 f-j i 400 / J CI
c(
400
~ 80 J? Z 300 Ivcc-sv- ~
i 200 / IL J- I 0
f 200
40
V·
2 4 6 8 10 12 14 18 18 20
100
f-- ~
/
V
0.1 0.2 0.3 0.4
0.1 0.2 0.3 0.4
Figure 3. Supply Curr8nt as a Function 01 Figure 4. Minimum Pulse-Width Required lor Figure 5. Propagation Delay as a Function 01
Supply VoHag8 Triggering Voltage Level 01 Trigger Pulse
MONOSTABLE OPERATION
+4

~ +3 I--
V
2.0
a:
~ +2
V ~
/
,:
:;; V V
-
c(
CI +1
Z
V I'-- r-. Oil I.S
c J
i 0 ...::IE
i=
/ ~~ i= 1.0
/
S -1 ~
N
~ 1/ ~
::;;
-2
~ O.S
V I

:5z -3 ::IE
a:
I
o I
Z
-4 o
o5 10 15 20 -~25 0 25°C 50 75 o 0.2 0.4 0.6 0.8 1.0
Flgur8 6. Typical Timing Accuracy as a Figure 7. Typical Timing Accuracy as a Figure 8. Normalized Time Delay as a Function
Function 01 Supply Voltage Function 01 Temperature (VCC = 51V, 01 Control Voltage
RA = 100KO, C = 0.01 I'F)
ASTABLE OPERATION
_ +2 r---r--,..---r-,..---r---.--r--, _ +1.5
~ ~
~ ~
!!: +1 ~
a:
c
>
C
>
+1

1\ >
u
2.0
,
~ 0 ~ +0.5

", -.. - ffi

:::l I.S "'~

"
:l :l
S -1 I--t--II-I--t--t--t--t--t---f 8 S
~ :l: .......... :l: ~
........... S 1.0
~ -2 I--II-I-+-I-+-I-+--f
C
1::- 0 .5 r-.... N I~
:::; :::; :::;
c( c(
c(
::;; O.S
I i'-..
~-31--t--1-+-1--t--~~--f ~ -1 a:
o I
~ TA _25°C o vcc - 5V z
_4~-L~~-L_~-L_~-L~
Z
-1.5 T I I

o 5 10 15 20 -25 0 25 50 7S o 0.2 0.4 0.6 o.e 1.0

Figure 9. Typical Frequency Stability as a Figure 10. Typical Frequency Stability as a Figure 11. Normalized Frequency 01 Oscillation
Function 01 Supply Voltage Function 01 Temperature (RA = RS = 10KO, as a Function 01 Control Voltage
C = 0.11'F)
100r-~~r-'--'--~~~ 100 ..-.......- ........--.....--.--.......-...,
500
TA a ds'c
c( 400 u: 10 ~-+--f--+ u: 10
E
u
~Nv"mONA<
SS5-TIMER .=. .=.w
~300
zw
f--- - --- IIJ
~ 1.0 I---+---t~ o 1.0
z
~2(!!) cI;
I- ;:
;:)
U
~ 100 \\ U
cI;
0.1 U
cI;
0.1 I--!---+-~-~~~-~

~
Q.
8: 5 0.01
;:)
I/) 0 r-.... ~ 0.01
XR·LSSS o O·
TIMER 0.001 L---L_..l-_I...---L~..l-~
0.001 "--.....iL-i(--.Il.-t---'---l--'
o 200 - 400 800 800 10 JlI 1.0 ml 100 ms 10 I 0.1 1.0 10 100 10K 1.0K 100KHz
Figure 12. Comparison 01 Supply Currellt Figure 13. Timing Period, T, as a Function 01 Figure 14. Free Running Frequency as a
Transient 01 Conventional 555-Timer with External R-C Network Function 01 External Timing Components
XR-L555 Micropower Timer (Note: R = RA + 2RS)

5-80
FEATURES OF XR-L555
XR·L555
The XR-L555 micropower timer is, in most instances, a enced to 2/3 Vee with the use of three equal internal re-
direct pin-for-pin replacement for the conventional 555- sistors. When the voltage across the capacitor reaches
type timer. However, compared to conventional 555- this level, the flip-flop is reset, the capacitor is dis-
timer, it offers the following important performance fea- charged rapidly, and the output level moves toward
tures: ground, and the timing cycle is completed.

Reduced Power Dissipation: The current drain is 1/15th of The duration of the timing period, T, during which the
the conventional 555-timer. output logic level is at a "high" state is given by the
equation:
No Supply Current Transients: The conventional 555-timer T = 1.1 RAe
can produce 300 to 400 mA of supply current spikes
during switching. The XR-L555 is virtually transient-free The time delay varies linearly with the choice of RA and
as shown in Figure 12. e as shown by the timing curves of Figure 13. For
proper operation of the circuit, the trigger pulse-width
Low-Voltage Operation: The XR-L555 operates down to 2.7 must be less than the timing period.
volts of supply voltage, vs. 4.5V minimum operating
voltage needed for conventional 555-timer. Thus, the Once the circuit is triggered it is immune to additional
XR-L555 can operate safely and reliably with two 1.5V trigger inputs until the present timing-period has been.
batteries. completed. The timing-cycle can be interrupted by us-
ing the reset control (pin 4). When the reset control is
Proven Bipolar Technology: The XR-L555 is fabricated us- "low", the internal discharge transistor is turned "on"
ing conventional bipolar process technology. Thus, it is and prevents the capacitor from charging. As long as
immune to electrostatic burn-out problems associated the reset voltage is applied, the digital output level will

•
with low-power timers using eMOS technology. remain unchanged, i.e. "low". The reset pin should be
connected to + Vee when not used to avoid the possi-
APPLICATIONS INFORMATION bility of false triggering.

MONOSTABLE (ONE-SHOT) OPERATION ASTABLE (SELF-TRIGGERING) OPERATION

The circuit connection for monostable, or one-shot op- For astable (or self-triggering) operation, the correct cir-
eration of the XR-L555 is shown in Figure 1. The inter- cuit connection is shown in Figure 2. The external ca-
nal flip-flop is triggered by lowering the trigger level at pacitor charges to 2/3 Vee through the parallel combi-
pin 2 to less than 1/3 of Vee. The circuit triggers on a nation of RA and RS, and discharges to 1/3 Vee
negative-going slope. Upon triggering, the flip-flop is through RS. In this manner, the capacitor voltage oscil-
set to one side, which releases the short circuit across lates between 1/3 Vee and 2/3 Vee, with an exponen-
the capacitor and also moves the output level at pin 3 tial waveform. The oscillations can be keyed "on" and
toward Vee. The voltage across the capacitor, there- "off" using the reset control. The frequency of oscilla-
fore, starts increasing exponentially with a time con- tion can be readily calculated from the equations in Fig-
stant T = RAe. A high impedance comparator is refer- ure 2 and Figure 14.

EQUIVALENT SCHEMATIC DIAGRAM

5-81
 XR-556

Dual Timer
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-556 dual timing circuit contains two indepen-
dent 555-type timers on a single monolithic chip. It is a
direct, pin-for-pin replacement for the SEINE 556 dual DISCHARGE
timer. Each timer section is a highly stable controller
capable of producing accurate time delays or oscilla- THRESHOLD DISCHARGE
tions. Independent output and control terminals are
provided for each section as shown in the functional CONTROL
block diagram. VOLTAGE
THRESHOLD

In the monostable mode of operation, the time delay for RESET

CONTROL
each section is precisely controlled by one external re- VOLTAGE

sistor and one capacitor. For astable operation as an

oscillator, the free-running frequency and the duty cy- OUTPUT RESET

cle of each section are accurately controlled with two

external resistors and one capacitor. TRIGGER OUTPUT

The XR-556 may be triggered or reset on falling wave-

GROUND TRIGGER
forms. Each output can source or sink up to 150 mA or
drive TIL circuits. The matching and temperature track-
ing characteristics between each timer section of the
XR-556 are superior to those available from two sepa-
rate timer packages.
ABSOLUTE MAXIMUM RATINGS
Power Supply 18V
FEATURES Power DisSipation
Ceramic Dual-In-Line 750 mW
Direct Replacement for SEINE 556
Derate above TA = 25°C 6 mW/oC
Replaces Two 555-Type Timers
Plastic Dual-In-Line 625 mW
TIL Compatible Pinouts
Derate above TA = 25°C 5 mW/oC
Timing from Microseconds Thru Hours
Excellent Matching Between Timer Sections
Storage Temperature Range - 65°C to + 150°C
Operates in Both Monostable and Astable Modes
High Current Drive Capability (150 mA each output) ORDERING INFORMATION
TIL and DTL Compatible Outputs
Adjustable Duty Cycle Part Number Package Operating Temperature
Temperature Stability of 0.005%IOC
XR-556M Ceramic - 55°C to + 125°C
XR-556CN Ceramic O°C to + 70°C
APPLICATIONS XR-556CP Plastic O°C to + 70°C
Precision Timing
Pulse Generation
Sequential Timing SYSTEM DESCRIPTION
Pulse Shaping
Time Delay Generation The XR-556 is an industry standard dual timing circuit
Clock Pattern Generation capable of both monostable and astable operation with
Missing Pulse Detection timing intervals ranging from low microseconds up
Pulse-Width Modulation through several hours. Timing is independent of supply
Frequency Division voltage, which may range from, 4.5 V to 18 V. The out-
Clock Synchronization put stage can source or sink 150 mAo Each timer sec-
Pulse-Position Modulation tion is fully independent and similar to 555-type de-
Appliance Timing vices.

5-82
 XR·556
CONTROL

023 OUTPUT

°24

•
OISCHARGE

GNO~

-= -=

EQUIVALENT SCHEMATIC DIAGRAM

SYSTEM DESCRIPTION (continued)
In the monostable (one shot) mode, timing is deter- The output of the XR-556 is high during the timing inter-
mined by one resistor and capacitor. Astable operation val, and pulls low at timeout. It is triggered and reset on
(oscillation) requires an additional resistor, which con- falling waveforms. The control voltage inputs (Pins 3
trols duty cycle. An internal resistive divider provides a and 11) may serve as pulse width modulation points.
reference voltage of 2/3 VCC, which produces a timing Matching between sections is typically better than
interval of 1.1 RC. As the reference is related to VCC, 0.05% initially, with temperature drift tracking to ± 10
the interval is independent of supply voltage; however, ppm/oC and supply voltage drift tracking to 0.1 % IV. For
for maximum accuracy, the user should ensure VCC low voltage and/or low power drain applications, con-
does not vary during timing. sider the XR-L556.

5-83
XR·556
ELECTRICAL CHARACTERISTICS
Test Conditions: (Each timer section, TA = 25°C, VCC = + 5V to + 15V, unless otherwise specified.)
XR-556M XR-556C

PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS

Supply Voltage 4.5 18 4.5 16 V
Supply Current Low State Output,
(Each Timer Section) Note 1
3 5 3 6 mA Vee = 5V,
RL = 0>
10 11 10 14 mA Vee = 15V,
RL = 0>
Total Supply Current Low State Output,
(Soth Timer Sections) Note 1
6 10 6 12 mA Vee = 5V,
RL = 0>
20 22 20 28 mA Vee = 15V,
RL = 0>
Timing Error (Monostable) Timing, R = 1 KO
to 100 KO
Initial Accuracy 0.5 1.5 .75 3 % Note 2, e = 1.0 JlF
Drift with Temperature 30 100 50 ppm/oe ooe sTA s75°e
Drift wilh Supply Voltage 0.05 0.2 0.1 0.5 %N
Timing Error (Astable) RA, RS = 1 KO
to 100 KO
Initial Accuracy (Note 2) 1.5 2.25 % e = 0.1/lF
Drift with Temperature 90 150 ppm/oe Vee = 15V
Drift with Supply Voltage 0.15 0.3 %N
Threshold Voltage 9.4 10.0 10.6 8.8 10.0 11.2 V Vee = 15V
2.7 3.33 4.0 2.4 3.33 4.2 V Vee = 5V
Trigger Voltage
1.45 1.67 1.9 1.67 V Vee = 5V
4.8 5.0 5.2 4.5 5.0 5.6 V Vee = 15V
Trigger Current 0.5 0.9 0.5 2 /lA VTRIG = OV
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V VTRIG High
Reset Current 0.4 1 0.4 1.5 mA VRESET = OV
Threshold Current 0.03 0.1 0.03 0.1 /lA Note 3
Control Voltage Level
2.90 3.33 3.80 2.60 3.33 4.00 Vee = 5V
9.6 10.0 10.4 9.0 10.0 11.0 Vee = 15V
Output Voltage Drop (Low) Vee = 5V
0.10 0.25 0.3 V Isink = 8.0 mA
0.05 0.20 0.25 0.35 V Isink = 5.0 mA
Vee = 15V
0.1 0.15 0.1 0.25 V Isink = 10 mA
0.4 0.5 0.4 0.75 V Isink = 50 mA
2.0 2.25 2.0 2.75 V Isink = 100 mA
2.5 2.5 V Isink = 200 mA
Output Voltage Drop (High) Isource = 100 mA
3.0 3.3 2.75 3.3 V Vee = 5V
13 13.3 12.75 13.3 V Vee = 15V
Isource = 200 mA
12.5 12.5 V Vee = 15V
Rise Time of Output 100 200 100 300 nsec
Fall Time of Output 100 200 100 300 nsec
Matching Characteristic Note 4
Initial Timing Accuracy 0.05 0.1 0.1 0.2 %
Timing Drift with ±10 ±10 ppm/oe
Temperature
Drift with Supply Voltage 0.1 0.2 0.2 0.5 %N

Note 1: Supply current when output is high is typically 1.0 mA less.

Note 2: Tested at Vee = 5V and Vee = 15V.
Note 3: This will determine the maximum value of RA + RS for 15V operation. The maximum total R = 10
megohms, and for 5V operation, the maximum R = 3.4 megohms.
Note 4: Matching characteristics refer to the difference between performance characteristics of each timer section.

5-84
 XR-L556

Micropower Dual Timer

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-L556 dual timer contains two independent mi-
cropower timer sections on a monolithic chip. It is a di-
DISCH"RCI Vee
rect replacement for the conventional 556-type dual
timers, for applications requiring very low power dissi-
THRESHOLD OISCII"RG£
pation. Each section of the XR-L556 dual timer is equiv-
alent to Exar's XR-L555 micropower timer. The circuit CONTROL fllRUIiOLD
dissipates only 1/15th of the stand-by power of conven- VOLTAGE

tional dual timers and can operate down to 2.5 volts RESn
COlnnOL
VOLTAG£
without sacrificing such key features as timing accu-
racy and stability. At 5 volt operation, typical power dis- OUTPUT nnn
sipation of the dual-timer circuit is less than 2 mW; and
it can operate in excess of 500 hours with only two 300 TRIGGER OUtPUT

mA-Hr NiCd batteries.

GROUND lRIGGtR
The two timer sections of the circuit have separate con-

•
trols and outputs, but share common supply and
ground terminals. Each output can source up to 100
mA of output current or drive TTL circuits.
FEATURES ORDERING INFORMATION
Replaces two XR-L555 Micropower Timers
Part Number Package Operating Temperature
Pin Compatible with Standard 556-Type Dual Timer
Less than 1 mW Power Dissipation per Section (VCC = XR-L556 M Ceramic - 55°C to + 125°C
5V) XR-L556 CN Ceramic O°C to + 70°C
Timing from Microseconds to Minutes XR-L556 CP Plastic O°C to + 70°C
Over 500-Hour Operation with 2 NiCd Batteries Low
Voltage Operation (VCC = 2.5V)
Operates in Both Monostable and Astable Modes
SYSTEM DESCRIPTION
CMOS TTL and DTL Compatible Outputs
The XR-L556 is a micropower version of the industry
Introduces No Switching Transients
standard XR-556 timing circuit, capable of both
APPLICATIONS monostable and astable operation with timing intervals
ranging from low microseconds up through several
Battery Operated Timing hours. Timing is independent of supply voltage, which
Micropower Clock Generator may range from 2.5 V to 15 V. The output stage can
Pulse Shaping and Detection source 100 mA. Each timer section is fully independent
Micropower PLL Design and similar to the XR-L555.
Power-On Reset Controller
Micropower Oscillator In the monostable (one shot) mode, timing is deter-
Sequential Timing mined by one resistor and capacitor. Astable operation
Pulse-Width Modulation (oscillation) requires an additional resistor, which con-
Appliance Timing trols duty cycle. An internal resistive divider provides a
Remote-Control Sequencer reference voltage of 2/3 VCC, which produces a timing
ABSOLUTE MAXIMUM RATINGS interval of 1.1 RC. As the reference is related to VCC,
the interval is independent of supply voltage; however,
Power Supply 18V for maximum accuracy, the user should ensure VCC
Power Dissipation does not vary during timing.
Ceramic Dual-In-Line 750 mW
Derate above TA = 25°C 6 mW/oC The output of the XR-L556 is high during the timing in-
Plastic Dual-In-Line 625 mW terval. It is triggered and reset on falling waveforms.
Derate above TA = 25°C 5 mW/oC The control voltage inputs (Pins 3 and 11) may serve as
Storage Temperature Range -65°C to + 150°C pulse width modulation points.

5-85
 XR·L556
ELELTRICAL CHARACTERISTICS
Test Conditions: (TA = 25 DDC, VCC = + 5V, unless otherwise specified)

XR-L556M XR-L556C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITION
Supply Voltage 2.5 15 2.7 15 V
Supply Current Low State Output
(Each Timer Section) 150 300 200 500 p,A VCC = 5V, RL = 00
Total Supply Current
(Soth Timer Sections) 300 600 400 1000 p,A
Timing Error RA, RS = 1 KO to 100 KO
Initial Accuracy 0.5 1.0 % C = 0.1 p,F
Drift with Temperature 50 200 50 ppm/DC ODC ~ TA ~ 70 DC
Drift with Supply Voltage 0.5 0.5 %IV Monostable Operation
Threshold Voltage 2/3 2/3 X VCC
Trigger Voltage 1.45 1.67 1.9 1.67 V VCC = 5V
4.8 5.0 5.2 5.0 V VCC = 15V
Trigger Current 20 20 nA
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Curerent 10 10 p,A
Threshold Current 10 50 20 100 nA
Control Voltage Level 2.90 3.33 3.80 2.60 3.33 4.00 V VCC = 5V
9.6 10.0 10.4 9.0 10.0 11.0 V VCC = 15V
Output Voltage Drop (Low) 0.1 0.3 0.15 0.35 V Isink = 1.5 mA
Output Voltage Drop (High) Isource = 10mA
3.0 3.3 2.75 3.3 V VCC = 5V
13 13.3 12.75 13.3 V VCC = 15V
Isource = 100 mA
12.5 12.5 V VCC = 15V
Rise Time of Output 200 200 nsec
Fall Time of Output 100 100 nsec
Discharge Transistor 0.1 0.1 p,A
Leakage

, . - - - - _ -__--Qv.
,.----...----...---oVCC

RESET RL RESET

.. 14 14

OUTPUT
OUTPUT DISCHARGE

R8
112 OF XR L~~6 t--cr---, 112 OF XR 5~6

I
In T~Rl-GG-ER-----TR<IG~GE-R~_ _~~
INPUT -
CONTROL C

f.~
CONTROL
INPUT
CONTROL

R _S _
DUTYCYClE _ _ _
TRIGGER

THRESHOLD

IRA + 2RalC RA + 2RS

Figure 1. Monostable (One-Shot) Circuit Figure 2. Astable (Free-Running) Circuit

5-86
 XR·L556
CHARACTERISTIC CURVES
GENERAL CHARACTERISTICS
800 1200 1200
A
I 0
/I I '0 /1
720 1100 T A = +25 C
I
Vec -5V_
-,- , f-TA • .:s~
I
,.JC-2~OC
~ T~ = ~250~ ,A
iii
640 - - c: 1000
I ~ 1000
i.... I -l J
~.... 560
900 I
/'
a , ° ...... ~
V .,.,1/ 3: 800 Vee· 2.5V/ 1/ > 800 - T A = .25 e
~a '-"";:::: ~ __ 25 O C_
~ 480
a:
~ 400
u
~ 320
II
/'
... V
V~
t.,.....-V
.Y
TA = +75 'c -
I--
w
...
til

~
:;;
:J
700
600
500
/
V
J
I
z
0
;::
600
L-- I---
----
~ 240 V""" :;; 400 oCt
400
~ l7 Z 300 f v cc = 5V- ";t
160 :E 200
7 I I 0
~ 200
I
80
oV
4 6 8 10 12 14
SUPPLY VOLTAGE, V CC (VOL TSI
16 18 20
100
"'---
- 0.1
./
V
0.2
LOWEST VOLTAGE LEVEL OF
0.3 0.4 0.1 0.2
LOWEST TRIGGER VOLTAGE
0.3 0.4

TRIGGER PULSE (X V cel LEVEL (X vccl

Figure 3. Total Supply Current as a Figure 4. Minimum Pulse-Width Figure 5. Propagation Delay as a
Function of Supply Voltage Required for Triggering Function of Voltage Level of
Trigger Pulse
MONOSTABLE OPERATION
2.0
+4
1 /
/ V ....
>'
~ +3
VV
a:
~ +2
~
t:l +1
V
V
~
c:
~
t:l
Z
2

I'...
a
w
~
:;;
;:: 1.0
1.5

/
J
V
II
Z
:E
;::
~
0

-1
/
:E
;::
8N
0
--- I--

....... '" 8
N
:::;
<t 0.5
:;;
V
.11
I

~ -2
II :::; -1
<t
:;;
a:
o
z
I
I
::; c: o
~ -3 ~ -2 o 0.2 0.4 0.6 0.8 1.0
z CONTROL VOLTAGE AS FRACTION OF ~cc
-4 -3
o 10 15 20 -25 o 25°C 50 75
SUPPLY VOL TAGE V CC (VOLTSI TEMPERATURE (oCI

Figure 6. Typical Timing Figure 7. Typical Timing Figure 8. Normalized Time

Accuracy as a Function of Accuracy as a Function of Delay as a Function of
Supply Voltage Temperature Con trol Voltage
(V CC =5V, RA = IOOKr2, C =O.OIJLF)
ASTABLE OPERATION
+2 _ +1.5 2.0

t;:
a: +1
R
A
'= R
B
LJ J-1:1
~I J
~
t;:
a: +1
>.
u
~
:J 1.5
"-
"
I~ a

'"
o
> R A =R B =lOOK > ~ 8
u
~
:J
o
w -1
IJ'/
~ +0.5
:J
~
", f-.
----
:f
8N
:::;
1.0 "-1""'-.
:f
o
~ -2
:::;
If :f
a
~ -0.5
:::;
.......... .......... oCt
::; 0.5
c:
0
z
I
I
"-
I
oCt oCt
~ -3 ~ -1 0.2 0.4 0.6 0.8 1.0
o TA = 25°C o Vcc = 5V
Z
i I
z -j , CONTROL VOLTAGE AS FRACTION OF Vcc
-4 -1.5
10 15 20 -25 o 25 50 75
SUPPL Y VOL TAGE, V CC (VOL TSI TEMPERATURE tel

Figure 9. Typical Frequency Figure 10. Typical Frequency Figure 11. Normalized Frequency
Stability as a Function of Stability as a Function of of Oscillation as a Function of
Supply V oItage Temperature Control Voltage
(R A =RB = IOKr2. C =O.IJ1F)

5-87
XR·L556 soo
FEATURES OF XR-L556
TA _25°c
The XR-L556 micropower dual timer is, in most in-
stances, a direct pin-for-pin replacement for the con- 400
ventional 556-type dual timer. However, compared to
conventional 556-timer, it offers the following important
od:
E
~ CONVENTIONAL
NE556 DUAL TIMER
performance features: .... 300

Reduced Power Dissipation: The current drain is 1/15th of

the conventional 556-type dual timer.
Z
UI
a:
a::
j
u 200
\
No Supply Current Transients: The conventional 556-timer
can produce 300 to 400 mA of supply current spikes
during switching of either one of its timer sections. The
>
oJ
A-
A-
j
en 100
\\
XR-L556 is virtually transient-free as shown in Figure
0
.- f'.....
12. XR-L556
DUAL TlrER
Low-Voltage Operation: The XR-L556 operates down to 2.7
volts of supply voltage, vs. 4.5V minimum operating o 200 400 600 800
voltage needed for conventional 556-timer. Thus, the TIME AFTER TRIGGER INPUT InSec)
XR-L556 can operate safely and reliably with two 1.5V
NiCd batteries. Figure 12. Comparison of Supply Current Transient of
Conventional NE556 Dual Timer with XR-L556
Proven Bipolar Technology: The XR-L556 is fabricated us- Micropower Dual Timer
ing conventional bipolar process technology. Thus, it is
immune to electrostatic burn-out problems associated i.e. "low". The reset pin should be connected to + VCC
with low-power timers using CMOS technology. when not used to avoid the possibility of false trigger-
ing.

PRINCIPLES OF OPERATION ASTABLE (SELF-TRIGGERING) OPERATION

MONOSTABLE (ONE-SHOT) OPERATION For astable (or self-triggering) operation, the correct cir-
cuit connection is shown in Figure 2. The external ca-
The circuit connection for monostable, or one-shot op- pacitor charges to 2/3 VCC through the series combina-
eration is one of the timer sections of the XR-L556 is tion of RA and RS, and discharges to 1/3 VCC through
shown in Figure 1. The internal flip-flop is triggered by RS. In this manner, the capacitor voltage oscillates be-
lowering the trigger level to less than 1/3 of VCC. The tween 1/3 VCC and 2/3 Vcc, with an exponential wave-
circuit triggers on a negative-going slope. Upon trigger- form. The output level at pin 5 (or 9) is high during the
ing, the flip-flop is set, which releases the short circuit charging cycle, and goes low during the discharge cy-
across the capacitor and also moves the output level cle. The charge and the discharge times are indepen-
toward VCC. The voltage across the capacitor, there- dent of supply voltage. The oscillations can be keyed
fore, starts increasing exponentially with a time con- "on" and "off" using the reset controls (pin 4 or 10).
stant T = RAC. A comparator is referenced to 2/3 VCC
with the use of three equal internal resistors. When the 100
voltage across the capacity reaches this level, the flip-
flop is reset, the capacitor is discharged rapidly, the
output level moves toward ground and the timing cycle ~ 10
is completed. The duration of the timing period, T, dur- ~
ing which the output logic level is at a "high" state is w
given by the equation: CJ 1.0
Z
T = 1.1 RAC <
I-
(j 0.1
This time delay varies linearly with the choice of RA and <
~
C as shown by the timing curves of Figure 13. For
proper operation of the circuit, the trigger pulse-width
<
CJ 0.01
must be less than the timing period. d
Once the circuit is triggered it is immune to additional 0.001
trigger inputs until the present period has been com- 100 ms 105
10 J.Ls 1.0 ms
pleted. The timing-cycle can be interrupted by using the
reset control. When the reset control is "low", the inter- TIMING PERIOD, T
nal discharge transistor is turned "on" and prevents the
capacitor from charging. As long as the reset voltage is Figure 13. Timing Period, T, as a Function of External R-C
applied, the digital output level will remain unchanged Network

5-88
 The charge time (output high) is given by: 100
t1 = 0.695 (RA + RS)C

The discharge time (output low) by:

u: 10
3-
t2 = 0.695 (RS)C w
u 1.0
z
Thus the total period is given by: ct
I-
T = t1 + t2 = 0.695 ((RA + 1RS)C u 0.1
ct
Q.
The frequency of oscillation is then: ct
U 0.01
f =1 = 1.44 and U
T (RA + 2RS)C
0.001
may be easily found as shown in Figure 14. 0.1 1.0 10 100 10K 1.0K 100K

The duty cycle D, is given by: f, FREE·RUNNING FREQUENCY (Hz)

FiQure 14. Free Running Frequency as a Functionol External

D = _ _R--,S~_ Timing Components (Note: R = RA + 2RS)
RA + 2RS
T2 = 1.1 R2C2. In this manner, the unit behaves as a
APPLICATIONS INFORMATION "delayed one-shot" where the output of Timer 2 is de-

•
layed from the initial trigger at pin 6 by a time delay of
INDEPENDENT TIME DELAYS T1
Each timer section of the XR-L556 can operate as an in- KEYED OSCILLATOR
dependent timer to generate a time delay, T, set by the
respective external timing components. Figure 15 is a One of the timer sections of the XR-L556 can be operat-
circuit connection where each section is used sepa· ed in its free-running mode, and the other timer section
rately in the monostable mode to produce respective can be used to key it "on" and "off". A recommended
time delays of T1 and T2, where: circuit connection is shown in Figure 17. Timer 2 is
used as the oscillator section, and its frequency is set
T1 = 1.1 R1C1 and T2 = 1.1 R2C2 by the resistors RA, RS and the capacitor C2. Timer 1 is
operated as a monostable circuit, and its output is con-
SEQUENTIAL TIMING (DELAYED ONE-SHOT) nected to the reset terminal (pin 10 of Timer 2).
In this application, the output of one timer section (Tim- When the circuit is at rest, the logic level at the output
er 1) is capacitively coupled to the trigger terminal of of Timer 1 is "low"; and the oscillations of Timer 2 are
the second, as shown in Figure 16. When Timer 1 is inhibited. Upon application of a trigger signal to Timer
triggered at pin 6, its output at pin 5 goes "high" for a 1, the logic level at pin 1 goes "high" and the oscillator
time duration T 1 = 1.1 R1 C1. At the end of this timing section (Timer 2) is keyed "on". Thus, the output of Tim-
cycle, pin 5 goes "low" and triggers Timer 2 through er 2 appears as a tone burst whose frequency is set by
the capacitive coupling, CC, between pins 5 thru 8. RA, RS and C2, and whose duration is set by R1 and C1
Then, the output at pin 9 goes "high" for a time duration of Figure 17.
Vcc r----~-Q--Q---___1p_O Vee

R2

RU
T2· ·'R2CZ
'

JL I-T2-1
V·

13 '-"..:...0.-4----0 OUTPUT 2
R2
1f
TRIGGER

30K T,·'. 'R ,C,

-D o--4----II.......o----.J'IN'v-oO y+
OUTPUT
1
0.001 ~F
Cc
TZ·'·'RzCZ

Figure 15. Generation 01 Two Independent Time Delays Figure 16. Sequential Timing

5-89
XR·L556

c~
v'
H--<)-<~~-{) OUTPUT

1f
TRIGGER

Figure 18. Frequency Divider and Pulse-Shaper

1."&

MICROPOWER OSCILLATOR WITH INDEPENDENT

Figure 17. Keyed Oscillator FREQUENCY AND DUTY CYCLE ADJUSTMENT

FREQUENCY DIVIDER AND PULSE SHAPER If Timer 1 is operated in its astable mode and Timer 2 is
operated in its monostable mode, as shown in Figure
If the frequency of the input is known, each timer sec- 19, then an oscillator with fixed frequency and variable
tion of the XR-L556 can be used as a frequency divider duty cycle results.
by adjusting the length of its timing cycle. If the timing
interval T 1 (= 1.1 R1 C1) is larger than the period of the Timer 1 generates a basic periodiC waveform that is
input pulse trigger, then only those input pulses which then used to trigger Timer 2. If the time delay, T2, of
are spaced more than 1.1 R1 C1 will actually trigger the Timer 2 is chosen to be less than the period of oscilla-
circuit. tions of Timer 1, then the output at pin 9 has the same
frequency as Timer 1, but has its duty cycle determined
The output frequency is equal to (1/N) times the input by the timing cycle of Timer 2. The output duty cycle
frequency. The division factor N is in the range: can be adjusted over a wide range (from 1 % to 99%)
by adjusting R2.
...------t----t---<l'vcc
l-1 <N<l
Tp Tp

where Tp is the period of the input pulse signal. ".

Since the two timer sections of the XR-L556 are electri-
cally independent, each can be used as a frequency di-
vider. Thus, if the trigger terminals of both timer sec-
tions are connected to a common input, the XR-L556
can produce two independent outputs at frequencies f1
and f2: n.""1
fREQUlNCY- - -
IRA +2RB1C,

Where N 1 and N2 are the division factors for respective

Figure 19. Mlcropower Oscillator with Fixed Frequency and
timer sections, set by external resistors and capacitors
Variable Duty-Cycle
at pins (1, 2) and (12, 13).

Frequency division can be performed by 1/2 of the XR-

L556. The remaining timer section can be used as a
"pulse-shaper" to adjust the duty cycle of the output
waveform. As seen in Figure 18, Timer 1 is used as the
frequency divider section and Timer 2 is used as the
pulse shapero

The output of Timer 1 (pin 5) triggers Timer 2, which

produces an output pulse whose frequency is the same
as the output frequency of Timer 1, and whose duty cy-
cle is controlled by the timing resistor and capacitor of
Timer 2. The duty cycle of the output of Timer 2 (pin 9) ONE SECTION OF XR·L556
can be adjusted from 1 % to 99% by varying the value
of R2. EQUIVALENT SCHEMATIC DIAGRAM

5-90
 XR-558/559

Quad Timing Circuits

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-558 and the XR-559 quad timing circuits con-
tain four independent timer sections on a single mono-
lithic chip. Each of the timer sections on the chip are OUTPUT 0
entirely independent, and each one can produce a time
delay from microseconds to minutes, as set by an ex- TIMING 0

ternal R-C network. Each timer has its separate trigger

terminal, but all four timers in the IC package share a TRIGGER 0

common reset control.

COMMON
RESET
Both the XR-558 and the XR-559 quad timer circuits are
"edge-triggered" devices, so that each timer section GROUND
can be cascaded, or connected in tandem, with other
timer sections, without requiring coupling capacitors. TRIGGER C

The XR-558 is designed with open-collector outputs; TIMING C

•
each output can sink up to 100 mA. The XR-559 is de-
signed with emitter-follower outputs. Each output can OUTPUT C
source up to 100 mA of load current. The outputs are
normally at "low" state, and go to "high" state during
the timing interval. ORDERING INFORMATION
Part Number Package Operating Temperature
XR-558M Ceramic - 55°C to + 125°C
FEATURES XR-558CN Ceramic ooe to + 70°C
Four Independent Timer Sections XR-558CP Plastic ooe to + 70°C
High Current Output Capability XR-559M Ceramic - 55°C to + 125°C
XR-558: 100 mA sinking capability/output XR-559CN Ceramic ooe to + 70°C
XR-559: 100 mA sourcing capability/output XR-559CP Plastic ooe to + 70°C
Edge Triggered Controls
Output Stage Independent of Trigger Condition SYSTEM DESCRIPTION
Wide Supply Range: 4.5 V to 16 V
The XR-558 and XR-559 are easy to use quad timers
capable of operation with supply voltages between 4.5
V and 18 V. Each section has independent timing and
APPLICATIONS
triggering, and can operate over intervals ranging from
Precision Timing the low microseconds up through several minutes. The
Pulse Shaping devices are triggered on falling waveforms and are im-
Clock Synchronization mune to long trigger pulses. When the reset pin (Pin 13)
Appliance Timing is held below 0.8 V, all four outputs are set low and all
triggers are disabled. Timing period. accuracy is typi-
cally better than 1 %, independent of Vce, and drift is
better than 150 ppm/oe and 0.5 %N. The timing period,
ABSOLUTE MAXIMUM RATINGS
in seconds, equals R times C.
Power Supply 18V
Power Dissipation The XR-558 features open collector outputs, capable of
Ceramic Dual-In-Line 750mW sinking 100 mA, that are driven low during the timing in-
Derate above TA = 25" 6 mW/oC terval. The XR-559 has emitter followers, active upon
Plastic Dual-In-Line 625 mW timeout, capable of sourcing 100 mA. The XR-558 sinks
Derate above TA = 25"C 5 mW/oC load current from + Vec, the XR·559 sources load cur·
Storage Temperature Range - 65°C to + 150°C rent to ground.

5-91
 XR·558/559
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA = 25°C, VCC = + 5V to + 15V, unless otherwise noted.)
XR-558M/XR-559M XR-558C/XR-559C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
Supply Voltage 4.5 18 4.5 16 V
Supply Current VCC = VRESET = 15V
XR-558 Family 21 32 27 36 mA Outputs Open
XR-559 Family 9 16 12 18 mA Outputs Open
Timing Accuracy R = 2 kO to 100 kO
Initial Accuracy 1 3 2 % C = 1 ItF
Drift with Temperature 150 150 ppm/DC
Drift with Supply Voltage 0.1 0.1 %/V
Trigger Characteristics See Note: 1
Trigger Voltage 0.8 1.5 2.4 0.8 1.5 2.4 V VCC = 15V
Trigger Current 5 30 10 100 itA VTRIGGER = OV
Reset Characteristics
Reset Voltage 0.8 1.5 2.4 0.8 1.5 2.4 V See Note: 2
Reset Current 50 300 50 itA
Threshold Characteristics Measured at Timing Pins
Threshold Voltage 0.63 0.63 XVCC (Pins 2, 7, 10 or 15)
Threshold Leakage 15 15 nA
XR-558 Output See Note: 3
Characteristics
Output Voltage 0.1 0.2 0.1 0.4 V IL = 10 mA
Output Voltage 0.7 1.5 1.0 2.0 V IL = 100 mA
Output Leakage 10 10 nA Output High Condition
XR-559 Output See Note: 4
Characteristics
Output Voltage 13 13.6 12.5 13.3 V IL = 10 mA, VCC = 15V
Output Voltage 12.5 13.3 12.0 13.0 V IL = 100 mA, VCC = 15V
Propagation Delay
XR-558 Family 1.0 1.0 Itsec
XR-559 Family 0.4 0.4 Itsec
Output Rise-time 100 100 nsec IL = 100 mA
Output Fall-time 100 100 nsec IL = 100 mA
NOTES:
1. The trigger functions only on the falling edge of the trigger pulse only after previously being high. After reset the
trigger must be brought high and then low to implement triggering.

2. For reset below 0.8 volts, outputs set low and trigger inhibited. For reset above 2.4 volts, trigger enabled.

3. The XR-558 output structure is open collector which requires a pull up resistor to VCC to sink current. The
output is normally low sinking current.

4. The XR-559 output structure is a darlington emitter follower which requires a pull down resistor to ground to
source current. The output is normally low and sources current only when switched high.

DESCRIPTION OF CIRCUIT OPERATION the IC. All four timing sections can be used simultane-
ously, or can be interconnected in tandem, for sequen-
The XR-558/559 quad timing circuits are designed to be tial timing applications. For astable operation, two sec-
used in timing applications ranging from few microsec- tions of the quad-timer IC can be interconnected to pro-
onds up several hours. They provide cost-effective al- vide an oscillator circuit whose duty-cycle can be
ternative to single-timer IC's in applications requiring a adjusted from close to zero, to nearly 100 %.
multiplicity of timing or sequencing functions.
The generalized test and evaluation circuit for both the
Each quad-timer circuit contains four independent tim- XR-558 and the XR-559 quad timer circuits is shown in
er sections, where each section can generate a time Figure 1. Note that, the only difference between the two
delay set by its own resistor and capacitor, external to circuit types is the structure of the output circuitry.

5-92
 Vee
RESET
XRII558/559
The frequency of oscillation can be externally con-
trolled by applying a control-voltage to the control ter-
minal (pin 4). Since the control terminal is common to
all the timer sections, the duty cycle of the output
waveform is not effected by the modulation voltage;
thus the circuit can function as a variable-frequency,
fixed duty-cycle oscillator.
LOAD
SWITCH
15581
The frequency of oscillation increases as the voltage at
the control terminal (pin 4) is lowered below its open-
15591 circuit value.

Frequency of Oscillation

Figure 1. Generalized Test and Evaluation Circuit for XR-5581

XR-559 Quad Timer Circuits r----.---~-.---~-~r__·"cc

MONOSTABLE OPERATION

In the monostable, or one-shot mode of operation, it is

necessary to supply two external components, a resis-
tor and a capacitor, for each section of the timer IC. The
timing terminals of those timer-sections not being used
can be left open-circuited. The time period is equal to
the external RC product. A plot of the timing period, T.
as a function of the external R-C combination is shown
in Figure 2.
Figure 3. Typical Circuit Connection for Astable Operation Us-
ing Two Timer-Sections. (Note: For XR-559, RL1
and RL2 are Connected from Outputs to Ground.)
II
100 ~--~--~----~--~---'----r-~

OUTPUT STRUCTURE
10 The XR-558 family of quad timers have "open-
collector" NPN-type output stages. Each output can in-
... dividually sink up to 100 mA of load current. However,
...u.3 10 with more than one output active, the total current ca-
z pability is limited by the power-dissipation rating of the
! IC package (see Absolute Maximum Ratings). In the
u normal operation of the circuit, each output will require
:« 01 a pull-up resistor to + VCC. The output is normally
u
U "low" state (i.e. sinking current) when the timer is at re-
set; and goes to "high" state during the timing cycle.

The XR-559 family of quad timers have Darlington NPN

"emitter-follower" type outputs. Each output can
source up to 100 mA, during its "high" state. The total
0001 a-__ __ __ __ __ ____ __
~ ~~ ~ ~ ~ ~ ~

amount of output current, available from all outputs, is

10 "I 100 "I 1 0 milO m, 100 milO, 10, 100,
limited by the package power dissipation rating. For
TIMING PERIOD. T normal operation of the circuit, a pull-down resistor is
Figure 2. Timing Period, T, as a Function of External R-C required from each output to ground. The output of XR-
Combination (Note: T = 1.0 RC) 559 is normally low (i.e. at "off-state"), and goes to
"high" state when the circuit is triggered.
ASTABLE OPERATION
TRIGGER INPUTS
For astable, or free-running, operation of the quad timer
circuits, it is desirable to cross-couple two of the timer Each timer section of the quad-timer IC's has its own
sections on the chip, as shown in Figure 3. In this cir- trigger input. The trigger level is set at nominally + 1.5
cuit configuration, the outputs of each section are V. and the trigger input is edge-triggered on the falling
direct-coupled to the opposite trigger input. Thus, the edge of an input trigger pulse. In other words, for
"high" and "low" half-periods of the output can be set proper triggering, the trigger signal must first go "high"
by the external R-C products, as R1 C1 and R2C2, re- and then go "low". If both the trigger and the reset con-
spectively. The frequency of oscillation, and the output trols are activated, the reset control overrides the trig-
duty-cycle are given as: ger input.

5-93
XR·558/559
RESET INPUT an over-all timing variation of approximately 50:1. Since
the time period of each timer section is proportional to
The reset control (pin 13) is common to all four timer the control voltage, all four timing periods can be simUl-
section and resets all of the timer sections simultane- taneously varied, and their relative ratios remain un-
ously. changed over the adjustment range.

The reset voltage must be brought below 0.8 V to insure APPLICATIONS EXAMPLE
reset condition. When reset is activated, all the outputs
go to "low" state. While the reset is active, the trigger Sequential Timer:
inputs are inhibited. After reset is finished, the trigger
voltage must be taken high and then low to implement
triggering. Figure 4 shows a typical application for the quad-timer
in sequential timing application. For illustration pur-
CONTROL VOLTAGE poses, the XR-558 is used in the example. Note that,
when triggered, the circuit produces four sequential
The control voltage terminal (pin 4) is common to all time delays, where the duration of each output is inde-
four timer sections of the XR-558 or the XR-559. This pendently controlled by its own R-e time constant. Yet,
terminal allows the internal threshold voltages of all all four outputs can be modulated over a 50:1 range,
four timer sections to be modulated, and thus provides and remain proportional over this entire range. Since
the control of the pulse-width or the duty-cycle of the each timer section is edge-triggered, the sections can
output waveforms. The range of this control voltage is be cascaded by direct coupling of respective outputs
from 0.5 V to + Vee minus 1 Volt. This range provides and trigger inputs.

OUTPtJT~L....-_ _ _ _ _ __

our ... IIT_2_ _- - ' n L_ _ _ _ __

t - - - - o UUTPUT'
0'''.'''_]_----1, ~
~ AUJ Ufo' TO 130 'HANC",( --~
CUN,NOL
VOLtAGE
OUTPUT_._ _ _ _ _ _ _ ~~
NOH
t,. t,. t3. t4 remail"! proportional over entIre adJ rangp.

la) Circuit Connection Ib) Timing Waveforms

Figure 4. Using the XR-558 as a Four-Stage Sequential Timer with Voltage Control Capability

XR-558 EQUIVALENT SCHEMATIC XR-559 EQUIVALENT SCHEMATIC

5-94
 X!' EXAR XR-2556

Dual Timing Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2556 dual timing circuit contains two indepen- OUTPUT
dent 555-type timers on a single monolithic chip. Each
timer section is a highly stable controller capable of f)UTPUT
producing accurate time delays or oscillations. Inde-
pendent output and control terminals are provided for
each section as shown in the functional block diagram.

In the monostable mode of operation, the time delay for llMlR

each section is precisely controlled by one external re- SIC!tON
=]
sistor and one capacitor. For astable operation as an CONTROL

oscillator, the free-running frequency and the duty cy-

cle of each section are accurately controlled with two
external resistors and one capacitor.

The XR-2556 may be triggered or reset on falling wave-

•
forms. Each output can source or sink up to 200 mA or
drive TTL circuits. The matching and temperature track- ORDERING INFORMATION
ing characteristics between each timer section of the
XR-2556 are superior to those available from two sepa- Part Number Package Operating Temperature
rate timer packages.
XR-2556M Ceramic - 55°C to + 125°C
XR-2556CN Ceramic O°C to + 70°C
FEATURES XR-2556CP Plastic O°C to + 70°C
Replaces Two 555-Type Timers SYSTEM DESCRIPTION
TTL Compatible Pinouts (Gnd-Pin 7, Vcc-Pin 14)
Timing from Microseconds Thru Hours The XR-2556 is a high output dual timing circuit similar
Excellent Matching Between Timer Sections to the popular 555-type timer, capable of both monost-
Operates in Both Monostable and Astable Modes able and astable operation with timing intervals ranging
High Current Drive Capability (200 mA each output) from low microseconds up through several hours. Tim-
TIL and DTL Compatible Outputs ing is independent of supply voltage, which may range
Adjustable Duty Cycle from 4.5 V to 18 V. The output stage can source or sink
Temperature Stability of 0.005%/oC 200 mA. Each timing section is fully independent.
Normally ON and Normally OFF Outputs In the monostable (one shot) mode, timing is deter-
mined by one resistor and capacitor. Astable operation
APPLICATIONS
(oscillation) requires an additional resistor, which con-
Precision Timing Missing Pulse Detection trols duty cycle. An internal resistive divider provides a
Pulse Generation Pulse-Width Modulation reference voltage of 2/3 VCC, which produces a timing
Sequential Timing Frequency Division interval of 1.1 RC. As the reference is related to VCC,
Pulse Shaping Clock Synchronization the interval is independent of supply voltage; however,
Time Delay Generation Pulse-Position Modulation for maximum accuracy, the user should ensure VCC
Clock Pattern Generation does not vary during timing.
The output of the XR-2556 is high during the timing in-
ABSOLUTE MAXIMUM RATINGS terval and pulls low at timeout. It is triggered and reset
on falling waveforms. The control voltage inputs (Pins 4
Power Supply 18 volts and 10) may serve as pulse width modulation points.
Power Dissipation Matching between sections is typically better than
Ceramic Dual-In-Line 750 mW 0.2 % initially with temperature drift tracking to ± 10
Derate above TA = 25°C 5 mW/oC ppm/oC.
Plastic Dual-In-Line 625 mW
Derate above TA = 25°C 5 mW/oC For low voltage and/or low power drain applications
Storage Temperate Range - 65°C to + 150°C consider the XR-L556.

5-95
 XR·2556
ELECTRICAL CHARACTERISTICS
Test Conditions: (Each timer section, TA = 25°C, VCC = + 5V to + 15V, unless otherwise specified.)

XR-2556M XR-2556C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS FIGURE CONDITIONS
Supply Voltage 4.5 18 4.5 16 V 7
Supply Current 7 Low State Output,
(Each Timer Section) Note 1
3 5 3 6 mA VCC = 5V,RL = 00
10 12 10 15 mA VCC = 15V, RL = 00
Total Supply Current 7 Low State Output
(Soth Timer Sections) 6 10 6 12 mA VCC = 5V, RL = 00
20 24 20 30 mA VCC = 15V, RL = 00
Timing Error RA, RS = 1 kO to 100kO
Initial Accuracy 0.5 2.0 1.0 % Note 2, C = 0.1 /LF
Drift with Temperature 30 100 50 ppm/DC 13
Drift with Supply 0.05 0.1 0.05 %/V 12
Voltage
Th reshold Voltage 2/3 2/3 x VCC
Trigger Voltage
1.45 1.67 1.9 1.67 V 6 VCC = 5V
4.8 5.0 5.2 5.0 V VCC = 15V
Trigger Current 0.5 0.5 /LA
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Current 0.1 0.1 mA
Threshold Current 0.1 0.25 0.1 0.25 /LA Note 3
Control Voltage Level 2.90 3.33 3.80 2.60 3.33 4.00 VCC = 5V
9.6 10.0 10.4 9.0 10.0 11.0 VCC = 15V
Output Voltage Drop
(Low)
9 VCC = 5V
0.10 0.25 V Isink = 8.0 mA
0.25 0.35 V Isink = 5.0 mA
11 VCC = 15V
0.1 0.15 0.1 0.25 V Isink = 10 mA
0.4 0.5 0.4 0.75 V Isink = 50 mA
2.0 2.2 2.0 2.5 V Isink = 100 mA
2.5 2.5 V Isink = 200 mA
Output Voltage Drop 8
(High) Isource = 100 mA
3.0 3.3 2.75 3.3 V VCC = 5V
13 13.3 12.75 13.3 V VCC = 15V
Isource = 200 mA
12.5 12.5 V VCC = 15V
Rise Time of Output 100 100 nsec
Fall Time of Output 100 100 nsec
Matching Characteristics Note 4
Initial Timing 0.2 0.6 0.2 %
Accuracy
Timing Drift with ±10 ±10 ppm/DC
Temperature

Note 1: Supply current when output is high is typically 1.0 mA less.

Note 2: Tested at VCC = 5V and VCC = 15V. .
Note 3: This will determine the maximum value of RA + RB for 15V operation. The maximum total R = 20 meg-ohms.
Note 4: Matching characteristics refer to the difference between performance characteristics of each timer section.

5-96
PRINCIPLES OF OPERATION Figure 4 shows the waveforms during the monostable
timing cycle. The top waveform is the trigger pulse; the
Figure 2 is the functional block diagram for each timer
section of the XR-2556. These sections share the same
V+ and ground leads, but have independent outputs T = 1.1 RAe
and control terminals. Therefore, each timer section
can operate independently of the other. The timing cy-
cle of each section is determined by an external
resistor-capacitor network.
J L OUTPUT O--<l---I

r-T-i
MONOSTABLE (ONE-SHOT) OPERATION
When operating either timer section of the XR-2556 in
¥ TRIGGERo--o-~
the monostable mode, a single resistor and a capacitor
are used to set the timing cycle. The discharge and
threshold terminals are also interconnected in this
mode, as shown in Figure 3.
Figure 3. Monostable (One-Shot) Circuit
Referring to Figure 2, monostable operation of the
XR-2556 is explained as follows: the external timing ca-
pacitor e is held discharged by the internal transistor,
To. The internal flip-flop is triggered by lowering the trig-
ger levels (pins 2 or 12) to less than 1/3 Vee. The circuit
triggers on a negative-going slope. Upon triggering, the
flip-flop is set to one side, which releases the short cir-
cuit across the capacitor and also moves the output
level at pins 1 or 13 toward Vee. The voltage across the
capacitor, therefore, starts increasing exponentially
with a time constant 'T = RA A high impedance com-
parator is referenced to 2/3 Vee with the use of three
equal interval resistors. When the voltage across the
capacitor reaches this level, the flip-flop is reset, the
capacitor is discharged rapidly, and the output level
moves toward ground, and the timing cycle is com-
pleted.
CONTROL
VOLTAGE Vce
(40R 10) 14
Figure 4. Monostable Waveforms
Top: Trigger Input
Middle: Exponential Ramp across Timing Capacitor
rHRESHOLD Bottom: Output Logic Level
130,,111

OISCHARGE
(SOR 9)

10

~
.3:
w
u 1.0
z
ct
~
OUTPUT
(1 OR 13)
U
ct
D..
ct 0.1
Figure 2. Functional Diagram of One Timer Section u
u'
Once the circuit is triggerd it is immune to additional
trigger inputs until the present timing-period has been 0.01 .----.R--++-~+---A_-__1f__--+--~
completed. The timing-cycle can be interrupted by us-
ing the reset control (pins 6 or 8). When the reset con-
trol is "low", the internal discharge transistor is turned
0.001 ~~~_~____~~~_--:-~--:~_-I
"on" and prevents the capacitor from charging. As long 10/ols 100/ols 1.0 ms 10 ms 100 ms 1.0 s 10 s 100 s
as the reset voltage is applied, the digital output level
TIMING PERIOD. T (sec.)
will remain unchanged, i.e. "low". The reset pin should
be connected to V + when not used to avoid the possi- Figure 5. Timing Period, T, as a Function of External R-C
bility of false triggering. Network

5-97
XR·2556
TYPICAL CHARACTERISTICS (Each Timer Section) ASTABLE (SELF-TRIGGERING) OPERATION
middle is the exponential ramp across the timing ca- For astable (or self-triggering) operation, the correct cir-
pacitor. The bottom waveform is the output logic state cuit connection is shown in Figure 15. The external ca-
(at pins 1 or 13) during the timing cycle. For proper op- pacitor charges to 2/3 Vee through the parallel combi-
eration of the circuit, the trigger pulse-width must be nation of RA and RS, and discharges to 1.3 Vee
less than the timing period. through RS. In this manner, the capacitor voltage oscil-
lates between 1/3 Vee and 2/3 Vee, with the exponen-
The duration of the timing period, T, during which the tial waveform as shown in Figure 16. The output level at
output logic level is at a "high" state is given by the pin 1 (or 13) is high during the charging cycle, and goes
equation: low during the discharge cycle. The charge and the dis-
T = 1.1 RAe charge times are independent of supply voltage. The
This time delay varies linearly with the choice or RA oscillations can be keyed "on" and "off" using the re-
e
and as shown by the timing curves of Figure 5. set controls (pin 6 or 8)

I8 ---+--+--+-+--If---4-- ~..M=---I
16 16 --
;;:
E 14 - . _ - --

~ I 2 -----_. -- 1-
-3' I Ii -- - -0 • Il'. C -- !.- I I

0:: __ I1 . ...11JJJ
.v
L-
o~~~~~~~~~--~
O~' __

O~--"--I.~~~
00. -

__-'-~~~
°Tr-I~\
Vee

01 U3 04 ~ 10 I~ I '0 20 ~IJ 1(XI

VII""',I' MINIMUM TRIGGf R VOL IA(;[ VS' SUPPL Y VUL I AUf ,Void
ISOUI~CF l!llAI
IX Vee V"rl

Figure 6. Trigger Pulse Width Figure 7. Supply Current (Both Timer Figure 8. High Output Voltage
Sections)

10

¥
?
.:.,
>0

01

-_. -- -.-+-~-+---I

OO\~~~~---'---~~~~
10 20 &0 100 I 10 ~o &0 lOa
':iINK- Irl1Al ISINK·lnlAI

Figure 9. Low Output Voltage Figure 10. Low Output Voltage Figure 11. Low Output Voltage
Vee = 5.0 Vdc Vee = 10 Vdc Vee = 15 Vdc
I Olb r---r---r-'T""""-.,.........,r---r--..,..---,

1010 --- . - - ---- - - - - - --- - . ---.-

~
~ 1 00& --~ -- - - -.-~--~~
~ ~ ... roo- r-- __ _---
z 1000 _ ---
~
;:
>
~ a 99'1---+--l--+--4----!-- - -
o
-" 0 Y90 ---

I.
VS' SUPPL v vOL TAGE IV<lcl
20
a!185 ' - - ' - - - " _.....~_"---'---I.--l
-70 &0 -~s 0 '2[, '&0
TA _AMBIENT TEMPF.RATURE I CI
·75 .I()(l ·125
VTlm,nl' MINIMUM TRIGGER VOL TAGE
IX Vee Void

Figure 12. Delay Time vs. Supply Figure 13. Delay Time vs. Temperature Figure 14. Propagation Delay vs.
Voltage Trigger Voltage

5·98
The charge time (output high) is given by:
XR·2556
To obtain the maximum duty cycle, RA must be as small
as possible; but it must also be large enough to limit the
t1 = 0.695 (RA + RS)C discharge current (pin 5 current) within the maximum
rating of the discharge transistor (200 mA).
The discharge time (output low) by:

t2 == 0.695 (RS)C DESCRIPTION OF CIRCUIT CONTROLS

Thus the total period is given by: OUTPUT (PINS 1 or 13)

The output logic level is normally in a "low" state, and

T = t1 + t2 = 0.695 (RA + 2RS)C
goes "high" during the timing cycle. Each output of the
The frequency of oscillation is then: XR-2556 is a "totem pole" type capable of sinking or
sourcing 200 mA of load current (see Figure 18).
f = .! = 1.44 and 100
T (RA + 2RS)C

may be easily found as shown in Figure 17.

10~--~~---+~--+-~~---1----;
The duty cycle, D, is given by:
u:
RS ..::
D = ----.:=--- w
u 1.0
RA + 2RS z
~
l-
t;
~

•
Cl-
~ 0.'
u
u'

1.nS OUTPUT

1/2
XR·2556

CONTROL
INPUT
4
o --,o~O~--:"~.O~K--:-::-:---:'~OOK
0.00' LO.-,__,..J..o-_...J,L..
f. FREE-RUNNING FREQUENCV (Hz)
f= 1.46
(R A + 2R B)C 7 Figure 17. Free Running Frequency as a Function of
External Timing Components
RB
DUTY CYCLE = RA + 2RB

Figure 15. Astable (Free·Runnlng) Circuit

Figure 18. Circuit Schematlc-l/2 of XR·2256

TRIGGER (PINS 2 OR 12)

The timing cycle is initiated by lowering the de level at

the trigger terminal below 1/3 VCC. Once triggered, the
circuit is immune to additional triggering until the timing
cycle is completed.

THRESHOLD (PINS 3 or 11)

The timing cycle is completed when the voltage level at

Figure 16. Astable Waveforms
Top: Output Waveform the trigger terminal reaches 2/3 VCC. At this pOint,
Comparator #2 of Figure 2 changes state, resets the in-
BoHom: Waveform Across Timing Capacitor
ternal flip-flop, and initiates the discharge cycle.

5-99
XR·2556
2.0,..-----,----,.----r---..,...---r----, rately in the monostable mode to produce respective
time delays of T1 and T2, where:

T1 = 1.1 R1C1 and T2 = 1.1 R2C2

~
>'
I
1.5 t---1I----i---+---t-V--~'+------i SEQUENTIAL TIMING (DELAYED ONE-SHOT)

~ ~c~~:
In this application, the output of one timer section
(Timer 1) is capacitively coupled to the trigger terminal
1.0 _ _ _ _ _ _ _ _ of the second, as shown in Figure 21. When Timer 1 is
triggered at pin 2, its output at pin 1 goes "high" for a
time duration T 1 = 1.1 R1 C1. At the end of this timing

; //! cycle, pin 1 goes "low" and triggers Timer 2 through

the capacitive coupling, CC, between pins 1 and 12.
Then, the output at pin 13 goes "high" for a time dura-
i
1----
tion T2 = 1.1 R2C2. In this manner, the unit behaves as
z 0.5 .,//;'
a "delayed one-shot" where the output of Timer 2 is
delayed from the initial trigger at pin 2 by a time delay
I of T1.
O~_~ ____ ~ ____ ~ ____
J~ __ ~ ____ ~
v'
o 2V 4V 6V 8V lOV 12V
MODULATION VOL TAGE AT CONTROL TERMINAL
(PINS 4 OR 10)

Figure 19. Normalized Time Delay vs. Modulation Voltage

CONTROL OR FM (PINS 4 OR 10)

The timing cycle or the frequency of oscillation can be

controlled or modulated by applying a dc control volt-
age to pin 4 or 10. This terminal is internally biased at
2/3 VCC. The control signal for frequency modulation or
pulse-width modulation is applied to this terminal. Fig-
ure 19 shows the variation of the timing period. T, as a
function of dc voltage at the control terminal. When not
in use, the control terminals should be ac grounded
through 0.01 JLF decoupling capacitors. Figure 20. Generation of Two Independent Time Delays
.----~--<)~;>_---r--O v'
DISCHARGE (PINS 5 OR 9) AZ

Cz
This terminal corresponds to the collector of the dis-
charge transistor, To, of Figure 2. During the charging
cycle, this terminal behaves as an open-circuit; during 11 ~
Al
discharge, it becomes a low impedance path to ground. v'

OUTPUT =2
RESET (PINS 6 OR 8)

The timing cycle can be interrupted by grounding the

1f
TRIGGER .1-
reset terminal. When the reset signal is applied, the
output goes "low" and remains in that state while the
--.-IL
~Tl+ ~T2
rest voltage is applied. When the reset signal is re- 30K T l ' 1,1 R 1C 1
moved, the output remains "low" until re-triggered. v' T2 • 1.1 RZC Z

When not used, the reset terminals should be connect-

ed to VCC in order to avoid any possibility of false trig-
r
Jj-OU1PUT
Tl -I >1

gering. When the timing circuits are operated in the Figure 21. Sequential Timing
astable mode, the reset terminals can be used for "on"
and "off" keying of the oscillations. (See Figure 22). KEYED OSCILLATOR

APPLICATIONS INFORMATION One of the timer sections of the XR-2556 can be operat-
ed in its free-running mode, and the other timer section
INDEPENDENT TIME DELAYS can be used to key it "on" and "off". A recommended
circuit connection is shown in Figure 22. Timer 2 is
Each timer section of the XR-2556 can operate as an in- used as the oscillator section, and its frequency is set
dependent timer to generate a time delay, T, set by the by the resistors RA, RS and the capacitor C2. Timer 1 is
respective external timing components. Figure 20 is a operated as a monostable circuit, and its output is con-
circuit connection where each section is used sepa- nected to the reset terminal (pin 8) of Timer 2.

5-100
 XR·2556
When the circuit is at rest, the logic level at the output
of Timer 1 is "low"; and the oscillations of Timer 2 are
inhibited. Upon application of a trigger signal to Timer
1, the logic level at pin 1 goes "high" and the oscillator
section (Timer 2) is keyed "on". Thus, the output of
Timer 2 appears as a tone burst whose frequency is set
by RA ' RS and C2, and whose duration is set by R1 and
C1 of Figure 22.

FREQUENCY DIVIDER

If the frequency of the input is known, each timer sec-

tion of the XR-2556 can be used as a frequency divider
by adjusting the length of its timing cycle. If the timing
interval T 1 (= 1.1 R1 C1) is larger than the period of the
input pulse trigger, then only those input pulses which
are spaced more than 1.1 R1C1 will actually trigger the
circuit.
Figure 23. Frequency Divider Waveforms
Top: Input Pulse Train (f = 5 kHz)
Middle: Waveforms Across Timing Capacitor
R, RB Bottom: Output Waveform (f = 1 kHz)
C, Cz
11

~ ~
TIMER TIMER

•
;/1 #2 'FREQUENCY DIVIDER AND PULSE SHAPER
12
v+ Frequency division can be performed by 1/2 of the
13 Rl
OUTPUT
XR-2556. The remaining timer section can be used as a
"pulse-shaper" to adjust the duty cycle of the output
1J
TRIGGER 7 10
waveform. As seen in Figure 24, Timer 1 is used as the
frequency divider section and Timer 2 is used as the
pulse-shaper.

0.01 ~F 0.01 ~F

20K

Figure 22. Keyed Oscillator

The output frequency is equal to (1/N) times the input

frequency. The division factor N is in the range: INPUT

( l_
Tp
1) < N< lTp '. ,- 'siN

where Tp is the period of the input pulse signal.

20K
v·o-...J\AI'v-L-------'
Figure 23 shows the circuit waveforms for divide-by-five
operation for one of the timer sections of the XR-2556. Figure 24. Frequency Divider and Pulse-Shaper
In this case, the timing period of the circuit is set to be
approximately 4.5 times the period of the input pulse. The output of Timer 1 (pin 1) triggers Timer 2, which
produces an output pulse whose frequency is the same
Since the two timer sections of the XR-2556 are electri- as the output frequency of Timer 1, and whose duty cy-
cally independent, each can be used as a frequency di- cle is controlled by the timing resistor and capacitor of
vider. Thus, if the trigger terminals of both timer sec- Timer 2. The duty cycle of the output of Timer 2 (pin 13)
tions are connected to a common input, the XR-2556 can be adjusted from 1 % to 99 % by varying the value
can produce two independent outputs at frequencies f1 of R2.
and f2:
Figure 25 shows the circuit waveforms in this applica-
f1 = fs/N1 and f2 = fs/N2 tion. The top waveform is the input signal of frequency
fs applied to the trigger input (pin 2) of Timer 1. The mid-
where N1 and N2 are the division factors for respective dle waveform is the output of Timer 1 for divide-by-three
timer sections, set by external resistors and capacitors operation; and the bottom waveform is the pulse-
at pins (3, 5) and (9, 11). shaped output obtained from Timer 2 (pin 13).

5-101
XR·2556
Frequency = 1.44
(RA + 2RS)C1
(1.6) R2C2
Duty Cycle = ---=--"'---
(RA + 2RSC1)

OSCILLATOR WITH SYNCHRONIZED OUTPUTS

The circuit of Figure 26 can also be used as an oscilla-

tor with synchronized multiple frequency outputs.
Timer 1 generates an output at frequency f1 at pin 1, as
set by resistor RA, RS, and C1. Timer 2 is used as a fre-
quency divider by setting its timing cycle, T2, to be larg-
er than the period of Timer 1 (see section on frequency
division). The resulting output of Timer 2 (pin 13) is at
frequency f2 given as:

Figure 25. Frequency Divider and Pulse-Shaper Waveforms where N is the divider ratio set by the external R-C net-
Top: Input Signal (fs = 9 kHz) works as described by Figures 23 and 24.
Middle: Output at Pin 1 for Divide-by-3
Bottom: Variable Duty Cycle Output at Pin 13 PULSE-WIDTH MODULATION

For pulse-width modulation, one-half of the XR-2556 is

connected as shown in Figure 27. The circuit operates
in its monostable mode and is triggered with a continu-
ous pulse train. Output pulses are generated at the
same rate as the input pulse train, except the output
pulse-width is determined by the timing components R1
and C1.

OUTPUT

PWM
OUTPUT -.l. 1/2
C,

FREOUENCY - IRA ~l;:~)Cl XR-2556

r:t.
CLOCK INPUT o--<~-I MODULATION
INPUT

Figure 26. Fixed Frequency Oscillator With Variable Duty

Cycle

FIXED-fREQUENCY, VARIABLE DUTY CYCLE OSCILLATOR Figure 27. Pulse-Width Modulation

If Timer 1 is operated in its astable mode and Timer 2 is

operated in its monostable mode, as shown in Figure In this mode of operation, the duration of the timing cy-
26, then an oscillator with fixed frequency and variable cle (i.e., the output pulse-width) can be modulated by
duty cycle results. applying a modulation input to the control voltage termi-
nals (pins 4 or 10). The control characteristics associ-
Timer 1 generates a basic periodic waveform that is ated with the modulation terminals are depicted in Fig-
then used to trigger Timer 2. If the time delay, T2, of ure 19. Figure 28 shows the actual circuit waveforms
Timer 2 is chosen to be less than the period of oscilla- generated in this manner.
tions of Timer 1, then the output at pin 13 has the same
frequency as Timer 1, but has its duty cycle determined When using the XR-2556 for pulse-width modulation, an
by the timing cycle of Timer 2. The output duty cycle external clock signal is not necessary, since one sec-
can be adjusted over a wide range (from 1 % to 99%) tion can be operated in its astable mode (see Figure 15)
by adjusting R2. and serve as the clock generator. Figure 29 is the rec-
ommended connection for such an application. In this
The frequency and the duty cycle of the output wave- case, Timer 2 is used as the clock generator, and Timer
form are given as: 1 is used as the pulse-width modulator section.

5-102
 XR·2556
a PULSE-POSITION MODULATION

When a timer section of the XR·2556 is operated in its

astable mode (see Figure 15), the period of the output
pulse train can be varied by applying a modulation volt-
age to the corresponding modulation control terminal.
In this manner, the repetition rate of the output pulse
train can be varied, resulting in a pulse-position modu-
lated output. Typical transfer characteristics between
the timing cycle and the modulation voltage are given in
c Figure 19.

LOGIC "AND" AND "OR" CONNECTION OF OUTPUTS

The individual outputs (pins 1 and 13) of the XR-2556

d can be interconnected as shown in Figure 30 to per-
form logic "or" and "and" functions. Since the output
Figure 28. Pulse-Width Modulation Waveforms of each timer section is a high-current "totem-pole"
a) Clock Input at Pin 2 type, external diodes are needed to avoid current flow
b) Modulation Input at Pin 4 from one output into the other.
c) Capacitor Voltage at Pin 3
d) Pulse-Width Modulated Output at Pin 1 Referring to Figure 30(a), the output logic level "P"
would read "high" when either one of the outputs at
pins 1 or 13 is "high." For Figure 30(b), the output will
read "high" only when both outputs at pins 1 and 13 are

•
R2
"high".

PWM
oUTPuT

l 0.001
XR·2556

MODULATION
INPUT ~F

20K (A) (8)

Figure 29. Pulse-Width Modulation With Internal Clock Figure 30. Logic "OR" and "AND"

One section of XR-2556

EQUIVALENT SCHEMATIC DIAGRAM

5-103
 XR-2240

Programmable Timer/Counter
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2240 Programmable Timer/Counter is a mono-
lithic controller capable of producing ultra-long time de-
lays without sacrificing accuracy. In most applications,
it provides a direct replacement for mechanical or elec-
tromechanical timing devices and generates program-
mable time delays from micro-seconds up to five days.
Two timing circuits can be cascaded to generate time
delays up to three years.

As shown in Figure 1, the circuit is comprised of an

internal time-base oscillator, a programmable 8-bit
counter and a control flip-flop. The time delay is set by
an external R-C network and can be programmed to any
value from 1 RC to 255 RC.

In astable operation, the circuit can generate 256 sepa-

rate frequencies or pUlse-patterns from a single RC set-
ting and can be syncronized with external clock sig-
nals. Both the control inputs and the outputs are com-
patible with TIL and DTL logic levels. ORDERING INFORMATION
Part Number Package Operating Temperature
FEATURES XR-2240M Ceramic - 55°C to + 125°C
XR-2240N Ceramic O°C to + 70°C
Timing from micro-seconds to days
XR-2240CN Ceramic O°C to + 70°C
Programmable delays: 1RC to 255 RC
Wide supply range; 4V to 15V
XR-2240P Plastic O°C to + 70°C
XR-2240CP Plastic O°C to + 70°C
TIL and DTL compatible outputs
High accuracy: 0.5%
External Sync and Modulation Capability
Excellent Supply Rejection: 0.2%/v SYSTEM DESCRIPTION
The XR-2240 is a combination timer/counter capable of
APPLICATIONS generating accurate timing intervals ranging from mi-
croseconds through several days. The time base works
Precision Timing Frequency Synthesis
as an astable multivibrator with a period equal to RC.
Long Delay Generation Pulse Counting/Summing
The eight bit counter can divide the time base output by
Sequential Timing AID Conversion any integer value from 1 to 255. The wide supply volt-
Binary Pattern Generation Digital Sample and Hold
age range of 4.5 to 15 V, TIL and DTL logic compatibili-
ty, and 0.5% accuracy-allow wide applicability. The
ABSOLUTE MAXIMUM RATINGS counter may operate independently of the time base.
Counter outputs are open collector and may be wire-
Supply Voltage 18V OR connected.
Power Dissipation
Ceramic Package 750 mW The circuit is triggered or reset with positive going
Derate above + 25°C 6 mw/oC pulses. By connecting the reset pin (Pin 10) to one of
Plastic Package 625 mW the counter outputs, the time base will halt at timeout.
Derate above + 25°C 5 mW/oC If none of the outputs are connected to the reset, the
Operating Temperature circuit will continue to operate in the astable mode. Ac-
XR-2240M - 55°C to + 125°C tivating the trigger terminal (Pin 11) while the timebase
XR-2240C O°C to + 70°C is stopped will set all counter outputs to the low state
Storage Temperature - 65°C to + 150°C and start the timebase.

5-104
 XR·2240
ELECTRICAL CHARACTERISTICS
Test Conditions: See Figure 2, V + 10 kO, C = 0.1 J-LF, unless otherwise noted.

XR-2240 XR-2240C
PARAMETERS MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage 4 15 4 15 V For V+ < 4.5V, Short Pin 15 to
Pin 16
Supply Current
Total Circuit 3.5 6 4 7 mA V + = 5V, VTR = 0, VRS = 5V
12 16 13 18 mA V+ = 15V, VTR = 0, VRS = 5V
Counter Only 1 1.5 mA See Figure 3
Regulator Output, VR 4.1 404 3.9 404 V Measured at Pin 15, V+ = 5V
6.0 6.3 6.6 5.8 6.3 6.8 V V+ = 15V, See Figure 4
TIME BASE SECTION See Figure 2
Timing Accuracy· 0.5 2.0 0.5 5 % VRS = 0, VTR = 5V
Temperature Drift 150 300 200 ppm/oC V+ = 5V O°C ::5 T ::5 75°C
80 80 ppm/oC V+ = 15V
Supply Drift 0.05 0.2 0.08 0.3 %N V+ ~ 8 Volts, See Figure 11
Max. Frequency 100 130 130 kHz R = 1 kO, C = 0.007 JLF
Modulation Voltage Measured at Pin 12
Level
3.00 3.50 4.0 2.80 3.50 4.20 V V+ 5V
10.5 10.5 V V+ = 15V

•
Recommended Range See Figure 8
of Timing Components
Timing Resistor, R 0.001 10 0.001 10 MO
Timing Capacitor, C 0.007 1000 0.01 1000 JLF
TRIGGER/RESET CONTROLS
Trigger Measures at Pin 11, VRS = 0
Trigger Threshold 104 2.0 104 2.0 V
Trigger Current 8 10 JLA VRS = 0, VTR = 2V
Impedance 25 25 kO
Response Time·· 1 1 JLsec.
Reset
Reset Threshold 104 2.0 104 2.0 V
Reset Current 8 10 JLA VTR = 0, VRS = 2V
Impedance 25 25 kO
Response Time·· 0.8 0.8 JLsec.
COUNTER SECTION See Figure 4, V+ = 5V
Max. Toggle Rate 0.8 1.5 1.5 MHz VRS = 0, VTR = 5V
Measured at Pin 14
Input:
Impedance 20 20 kO
Threshold 1.0 104 1.0 104 V
Output: Measured at Pins 1 thru 8
Rise Time 180 180 nsec. RL == 3k, CL = 10 pF
Fall Time 180 180 nsec.
Sink Current 3 5 2 4 mA VOL::5 OAV
Leakage Current 0.01 8 0.01 15 JLA VOH = 15V
*Timing error solely introduced by XR·2240, measured as % of ideal time·base period of T = 1.00 RC.
* * Propagation delay from application of trigger (or reset) input to corresponding state change in counter output at pin 1.

v'

Figure 2. Generalized Test Circuit Figure 3. Test Circuit for Low-Power Figure 4. Test Circuit for Counter
Operation (Time-Base Powered Down) Section

5-105
XR·2240
PRINCIPLES OF OPERATION PROGRAMMING CAPABILITY
The timing cycle for the XR-2240 is initiated by applying
The binary counter outputs (pins 1 through 8) are open-
a positive-going trigger pulse to pin 11. The trigger in-
collector type stages and can be shorted together to a
put actuates the time-base oscillator, enables the
common pull-up resistor to form a "wired-or" connec-
counter section, and sets all the counter outputs to
tion. The combined output will be "low" as long as any
"low" state. The time-base oscillator generates timing
one of the outputs is low. In this manner, the time de-
pulses with its period, T, equal to 1 RG. These clock
lays associated with each counter output can be
pulses are counted by the binary counter section. The
timing cycle is completed when a positive-going reset
summed by simply shorting them together to a com-
pulse is applied to pin 10. mon output bus as shown in Figure 6. For example, if
only pin 6 is connected to the output and the rest left
Figure 5 gives the timing sequence of output wave- open, the total duration of the timing cycle, To, would
forms at various circuit terminals, subsequent to a trig- be 32T. Similarly, if pins 1, 5, and 6 were shorted to the
ger input. When the circuit is at reset state, both the output bus, the total time delay would be To =
time-base and the counter sections are disabled and all (1 + 16 + 32) T = 49T. In this manner, by proper choice
the counter outputs are at "high" state. of counter terminals connected to the output bus, one
can program the timing cycle to be: 1T :S To :S 255T,
In most timing applications, one or more of the counter
where T = RG.
outputs are connected back to the reset terminal, as
shown in Figure 6, with S1 closed. In this manner, the TRIGGER AND RESET CONDITIONS
circuit will start timing when a trigger is applied and will
automatically reset itself to complete the timing cycle When power is applied to the XR-2240 with no trigger or
when a programmed count is completed. If none of the reset inputs, the circuit reverts to "reset" state. Once
counter outputs are connected back to the reset termi- triggered, the circuit is immune to additional trigger in-
nal (switch S1 open), the circuit would operate in its puts, until the timing cycle is completed or a reset input
astable or free-running mode, subsequent to a trigger is applied. If both the reset and the trigger controls are
input. activated simultaneously trigger overrides reset.

DESCRIPTION OF CIRCUIT CONTROLS

fI~f''''SE

[JIJ 11 IlnnmmIIIlIlL ounuY

I!'INI.)
COUNTER OUTPUTS (PINS 1 THROUGH 8)

The binary counter outputs are buffered "open-

D.n on 0 0 L-,"N. collector" type stages, as shown in Figure 15. Each
output is capable of sinking == 5 mA of load current. At
l'IN2
reset condition, all the counter outputs are at high or
non-conducting state. Subsequent to a trigger input,
t"lL.--__"""'--__ . J -_ _....J I_, ,,"' the outputs change state in accordance with the timing
diagram of Figure 5.
hL--..-----'--- - - - . ' 'INI

The counter outputs can be used individually, or can be

Figure 5. Timing Diagram of Output Waveforms connected together in a "wired-or" configuration, as
y' described in the Programming section.

RESET AND TRIGGER INPUTS (PINS 10 AND 11)

y'

The circuit is reset or triggered with positive-going con-

trol pulses applied to pins 10 and 11. The threshold lev-
el for these controls is approximately two diode drops
(== 1.4V) above ground.

Minimum pulse widths for reset and trigger inputs are

Jl
TRIOCE"
shown in Figure 10. Once triggered, the circuit is im-
mune to additional trigger inputs until the end of the
Jl
FlUET timing cycle.

~C~ ____ <__ ~~&I~K _ _ _~ MODULATION AND SYNC INPUT (PIN 12)

i¥
T
1T < To< 2SST WHERE T· AC The period T of the time-base oscillator can be modu-
lated by applying a de voltage to this terminal (see Fig-
ure 13). The time-base oscillator can be synchronized
Figure 6. Generalized Circuit Connection for Timing to an external clock by applying a sync pulse to pin 12,
Applications (Switch S1 Open for Astable as shown in Figure 16. Recommended sync pulse
Operations, Closed for Monostable Operations) widths and amplitudes are also given in the figure.

5-106
TYPICAL CHARACTERISTICS XR·2240
/~
_12
<C
! V
~ /
V
a: •
;,
u
>-
t
til
v
/v
I'

o TIM'NG CAPACITOR, C I_FI

o • • 10 12 ,. 16 11
SUPPL Y VOL TACE IVOL TSI

Figure 7. Supply Current vs. Supply Figure 8. Rocommended Range of Figure 9. Time-Base Period, T, as a
Voltage in Reset Condition (Supply Timing Component Values. Function of External RC
Current Under Trigger Condition is
== 0.7 mA less)
_'00r-........~....~~....~~~~
lO

u !•
~ ~ -- f - - ~

\\ c· 0,1.' ;:
I"- R,,0KII II:
u
""1<
i
0

•
~ 10

~ ~ .75> C --= r-- r--

"~
...... '1S C

ac i
'i
-1,~ :I
::>
:I
Z
0.1 ~~.-F.~-....---1I------1I--....- l
1.--
11-

-1~
i
10
10 1S 10
TRIGGER OR Run A"PLITUOEIVOL TSI
30 • 10
Vcc '\lOLTS
12 u 01
T'MING CAPACITOR, C "'''
10 100

Figure 10. Minimum Trigger and Reset Figure 11. Power Supply Drift Figure 12.
Pulse Widths at Pins 10 and 11 A) Minimum Trigger Delay Time Sub-
sequent to Application of Power
B) Minimum Re·trigger Time, Subsequent
to a Reset Input
s '1~ '2.00.
o· Vec' 'W VCC' nv
0
) C·O.l ... ' C·O.li'"
0
~ '1.0'\

S
v· -5'1

V
/ ~.
~
ot--- ~
;:
~ ~~
0 / -1.~
R'~
S
v
/'
V !z .10'!10
u
a:
0 -3.0'!10
0 1S so n 100 15 100
"'OOUlATlON VOL TAGE, V", IVOL TSI TEMHRATUREICI TE"'PERATURE I'CI

Figure 13. Normalized Change In Time- Figure 14. Temperature Drift of Time·Base Period, T
Base Period As a Function of Mod-
ulation Voltage at Pin 12

a I.F
o-!I-W..,....-o.:.:12~ XR.224a
SYNC S.IK
INPUT

Figure 16. Operation with External Sync Signal.

(a) Circuit for Sync Input
Figure 15. Simplified Circuit Diagram of XR-2240 (b) Recommended Sync Waveform

5-107
XR·2240
HARMONIC SYNCHRONIZATION REGULATOR OUTPUT (PIN 15)

Time-base can be synchronized with integer multiples This terminal can serve as a V + supply to additional
or harmonics of input sync frequency, by setting the XR-2240 circuits when several timer circuits are cas-
time-base period, T, to be an integer multiple of the caded (See Figure 20), to minimize power dissipation.
sync pulse period, Ts. This can be done by choosing For circuit operation with external clock, pin 15 can be
the timing components Rand C at pin 13 such that: used as the V + terminal to power-down the internal
time-base and reduce power dissipation. The output
T = RC = (Ts/m) where current shall not exceed 10 mA.

m is an integer, 1 ~ m ~ 10. When the internal time-base is used with V + ~ 4.5V,

pin 15 should be shorted to pin 16.
Figure 17 gives the typical pull-in range for harmonic
synchronization, for various values of harmonic modu- APPLICATIONS INFORMATION
lus, m. For m < 10, typical pull-in range is greater than
± 4 % of time-base frequency. PRECISION TIMING (Monostable Operation)
TIMING TERMINAL (PIN 13) In precision timing applications, the XR-2240 is used in
its monostable or "self-resetting" mode. The general-
The time-base period T is determined by the external ized circuit connection for this application is shown in
R-C network connected to this pin. When the time-base Figure 18.
is triggered, the waveform at pin 13 is an exponential
ramp with a period T = 1.0 RC. v'

TIME-BASE OUTPUT (PIN 14) v'

Time-Base output is an open-collector type stage, as

shown in Figure 15 and requires a 20 KG pull-up resis-
tor to Pin 15 for proper operation of the circuit. At reset
state, the time-base output is at "high" state. Subse-
quent to triggering, it produces a negative-going pulse
train with a period T = RC, as shown in the diagram of
Figure 5. 1l
TRIGGER

Time-base output is internally connected to the binary 1L

RESET
counter section and also serves as the input for the ex-
ternal clock signal when the circuit is operated with an
external time-base.
OUTrUT

The counter input triggers on the negative-going edge

of the timing or clock pulses applied to pin 14. The trig-
-!- -l"Lf'f-
To
11 < To < 255T WHERE T" RC

ger threshold for the counter section is "" + 1.5 volts. Figure 18. Circuit for Monostable Operation (To = NRC
The counter section can be disabled by clamping the where 1 ~ N ~ 255)
voltage level at pin 14 to ground.
Note: The output is normally "high" and goes to "low" subse-
Under certain operating conditions such as high supply quent to a trigger input. It stays low for the time dura-
voltages (V+ > 7V) and small values of timing capaci- tion To and then returns to the high state. The duration
tor (C < 0.1 p.F) the pulse-width of the time-base output of the timing cycle To is given as:
at pin 14 may be too narrow to trigger the counter sec-
tion. This can be corrected by connecting a 300 pF ca- To = NT = NRC
paCitor from pin 14 to ground.

· where T = RC is the time-base period as set by the

choice of timing components at pin 13 (See Figure 9). N
·\
2
is an integer in the range of:

1 ~ N ~ 255

·
·
·
'"
2 ..
..................

6
.........

•
r-
10
as determined by the combination of counter outputs
(pins 1 through 8) connected to the output bus, as de-
scribed below.

PROGRAMMING OF COUNTER OUTPUTS: The binary

RATIO OF TIME·BASE PERIOD TO
$VNC·PUlSE PERIOD. (TIT.'
counter outputs (pins 1 through 8) are open-collector
Figure 17. Typical Pull-In Range for Harmonic type stages and can be shorted together to a common
Synchronization pull-up resistor to form a "wired-or" connection where

5-108
the combined output will be "low" as long as anyone of ASTABLE OPERATION
XR·2240
the outputs is low. In this manner, the time delays asso-
ciated with each counter output can be summed by The XR-2240 can be operated in its astable or free-
simply shorting them together to a common output bus running mode by disconnecting the reset terminal (pin
as shown in Figure 18. For example if only pin 6 is con- 10) from the counter outputs. Two typical circuit con-
nected to the output and the rest left open, the total du- nections for this mode of operation are shown in Figure
ration of the timing cycle, To, would be 32T. Similarly, if 21. In the circuit connection of Figure 21 (a), the circuit
pins 1, 5, and 6 were shorted to the output bus, the total operates in its free-running mode, with external trigger
time delay would be To = (1 + 16 + 32) T = 49T. In this and reset signals. It will start counting and timing sub-
manner, by proper choice of counter terminals con- sequent to a trigger input until an external reset pulse is
nected to the output bus, one can program the timing applied. Upon application of a positive-going reset sig-
cycle to be: 1T ~ To ~ 255T. nal to pin 10, the circuit reverts back to its rest state.
The circuit of Figure 21 (a) is essentially the same as
ULTRA-LONG DELAY GENERATION that of Figure 6, with the feedback switch S1 open.

Two XR-2240 units can be cascaded as shown in Figure

19 to generate extremely long time delays. In this appli-
cation, the reset and the trigger terminals of both units
are tied together and the time base of Unit 2 disabled.
In this manner, the output would normally be high when
the system is at reset. Upon application of a trigger in-
put, the output would go to a low stage and stay that
way for a total of (265)2 or 65,536 cycles of the time-
base oscillator.

•
PROGRAMMING: Total timing cycle of two cascaded units
A
can be programmed from To = 256RC to To =
65,536RC in 256 discrete steps by selectively shorting
anyone or the combination of the counter outputs from
Unit 2 to the output bus. 10K

XA-:U.a I(A.:I'24O
UNIT NO 1 U~ITNO 2

lO.'5.S3&"C~~ B
f-'.-l ...
Figure 21. Circuit Connections for Astable Operation
Figure 19. Cascaded Operation for Long Delay Generation (a) Operation with External Trigger and Reset Controls
(b) Free-running or Continuous Operation
LOW-POWER OPERATION
The circuit of Figure 21(b) is designed for continuous
In cascaded operation, the time-base section of Unit 2 operation. The circuit self-triggers automatically when
can be powered down to reduce power consumption, the power supply is turned on, and continues to operate
by using the circuit connection of Figure 20. In this in its free-running mode indefinitely.
case, the V + terminal (pin 16) of Unit 2 is left open-
circuited, and the second unit is powered from the reg- In astable or free-running operation, each of the
ulator output of Unit 1, by connecting pin 15 of both counter outputs can be used individually as synchro-
units. nized oscillators; or they can be interconnected to gen-
erate complex pulse patterns.

BINARY PATTERN GENERATION

In astable operation, as shown in Figure 21, the output

of the XR-2240 appears as a complex pulse pattern.
The waveform of the output pulse train can be deter-
mined directly from the timing diagram of Figure 5
which shows the phase relations between the counter

\-'.-1
Figure 20. Low-Power Operation of Cascaded Timers
LJ
*
OUT,uT
outputs. Figure 22 shows some of these complex pulse
patterns. The pulse pattern repeats itself at a rate
equal to the period of the highest counter bit connected

5-109
XR·2240
to the common output bus. The minimum pulse width The modulus N is the total count corresponding to the
contained in the pulse train is determined by the lowest counter outputs connected to the output bus. Thus, for
counter bit connected to the output. example, if pins 1, 3 and 4 are connected together to
the output bus, the total count is: N == 1 + 4 + 8 == 13; and
the period of the output waveform is equal to (N + 1) T
or 14T. In this manner, 256 different frequencies can be
synthesized from a given time-base setting.

~"+-"---1 ~---",------.j
'"",,.StPw:wt-.j

~~
~l'+ !.f·· +JT+-'-2'T---~-+llt~-,±:+-I&T'--

3K
Figure 22. Binary Pulse Patterns Obtained by Shorting v' O-...A./II'v--.1.-IL.-.L---L.-L-..l.-.L......JI..-...~D.-..--<) OUTPUT
Various Counter Outputs
10K~
~
OPERATION WITH EXTERNAL CLOCK
T IN'lI
The XR-2240 can be operated with an external clock or
time-base, by disabling the internal time-base oscillator Figure 24. Frequency Synthesis from Internal Time-Base
and applying the external clock input to pin 14. The rec-
ommended circuit connection for this application is SYNTHESIS WITH HARMONIC LOCKING: The harmonic
shown in Figure 23. The internal time-base can be de- synchronization property of the XR-2240 time-base can
activated by connecting a 1 KO resistor from pin 13 to be used to generate a wide number of discrete frequen-
ground. The counters are triggered on the negative- cies from a given input reference frequency. The circuit
going edges of the external clock pulse. For proper op- connection for this application is shown in Figure 25.
eration, a minimum clock pulse amplitude of 3 volts is (See Figures 16 and 17 for external sync waveform and
required. Minimum external clock pulse width must be harmonic capture range.) If the time base is synchro-
~ 1,."S. nized to (m)th harmonic of input frequency where 1 ~
m ~ 10, as described in the section on "Harmonic Syn-
For operation with supply voltages of 6V or less, the in- chronization", the frequency fo of the output waveform
ternal time-base section can be powered down by in Figure 25 is related to the input reference frequency
open-circuiting pin 16 and connecting pin 15 to V+ . In fR as:
this configuration, the internal time-base does not draw
any current, and the over-all current drain is reduced by fo == fR __
m_
"",,3 rnA. (N + 1)

JU1Il ~~6~~~~;UT where m is the harmonic number, and N is the pro-

n TRIGGER
grammed counter modulus. For a range of 1 ~ N ~
11 RESET 255, the circuit of Figure 25 can produce 1500 sepa-
rate frequencies from a single fixed reference.

51K

Figure 23. Operaticn '::ith External Cicek

FREQUENCY SYNTHESIZER
5.1K
The programmable counter section of XR-2240 can be OIJTPu' 5.1K
Foo-~K~~~---L.-L-..l.-~~~~I'v--~~r4~~~
used to generate 255 discrete frequencies from a given
time base setting using the circuit connection of Figure 3OOP~ 5OOP~
24. The output of the circuit is a positive pulse train with
a pulse width equal to T, and a period equal to (N + 1) T Figure 25. Frequency Synthesis by harmonic Locking to an
where N is the programmed count in the counter. External Reference

5-110
One particular application of the circuit of Figure 25 is
generating frequencies which are not harmonically re-
lated to a reference input. For example, by choosing
the external R-C to set m = 10 and setting N = 5, one
can obtain a 100 Hz output frequency synchronized to
60 Hz power line frequency.

STAIRCASE GENERATOR

The XR-2240 Timer/Counter can be interconnected

with an external operational amplifier and a precision
resistor ladder to form a staircase generator, as shown
in Figure 26. Under reset condition, the output is low.
When a trigger is applied, the op. amp. output goes to a
high state and generates a negative going staircase of
256 equal steps. The time duration of each step is
equal to the time-base period T. The staircase can be
stopped at any desired level by applying a "disable" 11
STROBE INPUT
signal to pin 14, through a steering diode, as shown in
Figure 26. The count is stopped when pin 14 is clamped Figure 27. Digital Sample and Hold Circuit
at a voltage level less than 1.4Y.
ANALOG-TO-DIGITAL CONVERTER

Figure 28 shows a simple 8-bit AID converter system

---.r
ENABLE

DISABLE
o--f{ 1--.-..
using the XR-2240. The operation of the circuit is very
similar to that described in connection with the digital •
sample/hold system of Figure 15. In the case of AID
conversion, the digital output is obtained in parallel for-
mat from the binary counter outputs, with the output at
pin 8 corresponding to the most significant bit (MS8).
The re-cycle time of the AID converter is "'" 6 msec.

Figure 26. Staircase Generator

DIGITAL SAMPLE/HOLD

Figure 27 shows a digital sample and hold circuit using Figure 28. Analog-to-Digital Converter
the XR-2240. The principle of operation of the circuit is
similar to the staircase generator described in the pre-
vious section. When a "strobe" input is applied, the RC
low-pass network between the reset and the trigger in-
puts of XR-2240 causes the timer to be first reset and
then triggered by the same strobe input. This strobe in-
put also sets the output of the bistable latch to a high
state and activates the counter.

The circuit generates a staircase voltage at the output

of the op. amp. When the level of the staircase reaches
that of the analog input to be sampled, comparator
changes state, activates the bistable latch and stops
the count. At this point, the voltage level at the op. amp.
output corresponds to the sampled analog input. Once CONTROL

the input is sampled, it will be held until the next strobe 1- ---~~~:---- c~I~~;;YR--1~1
signal. Minimum re-cycle time of the system is "'" 6
msec. EQUIVALENT SCHEMATIC DIAGRAM

5-111
 XR-2242

Long Range Timer

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2242 is a monolithic timer/controller capable of
producing ultra-long time delays from milliseconds to
days. Two timing circuits can be cascaded to generate
time delays or timing intervals up to one year. The cir-
cuit is comprised of an internal time-base oscillator, an
8 bit binary counter and a control flip-flop. For a given
external R-C network connected to the timing terminal,
the ci rcuit produces an output timing pulse of 128 RC.
If two circuits are cascaded, a total time delay of (128)2
or 16,384 RC is obtained.

Three output pins are provided on the device: the time

base (RC) on Pin 8, 2 RC on Pin 2, and the counter out-
put (128 RC) on Pin 3.

FEATURES ORDERING INFORMATION

Timing from micro-seconds to days Part Number Package Operating Temperature

Wide supply range: 4.5V to 15V XR-2242M Ceramic -55°C to + 125°C
TTL and DTL compatible outputs XR-2242CN Ceramic O°C to + 70 0 e
High accuracy: 0.5% XR-2242CP Plastic O°C to + 70 0 e
Excellent Supply Rejection: 0.2%N
Monostable and Astable Operation
SYSTEM DESCRIPTION
The timing cycle for the XR-2242 is initiated by applying
a positive-going trigger pulse to Pin 6. The trigger input
APPLICATIONS actuates the time-base oscillator, enables the counter
Long Delay Generation section, and sets the output to "low" state. The time-
base oscillator generates timing pulses with its period,
Sequential Timing
Precision Timing T, equal to 1 RC. These clock pulses are counted by the
Ultra-Low Frequency Oscillator binary counter section. The timing cycle is completed
when a positive-going reset pulse is applied to Pin 5.

In monostable timer applications the output terminal

(Pin 3) is connected back to the reset terminal. In this
ABSOLUTE MAXIMUM RATINGS manner, after 128 clock pulses are applied to the cir-
cuit, this output goes to "high" state and resets the cir-
Power Supply 18 volts cuit thus completing the timing cycle. Thus, subse-
Power Dissipation (package limitation) quent to triggering, the output at Pin 3 will produce a to-
Ceramic Package 385 mW tal timing pulse of 128 RC before the circuit resets itself
Plastic Package 300 mW to complete the timing cycle. During the timing interval,
Derate above + 25°C 2.5 mW/oe the secondary output at Pin 2 produces a square-wave
Temperature Range output with the period of 2 RC.
Operating
XR-2242M - 55°C to + 125°C If the output at Pin 3 is not connected back to the reset
XR-2242C O°C to + 70 0 e terminal, the circuit continues to operate in an astable
Storage -65° to + 150 0 e mode, subsequent to a trigger input.

5-112
 ELECTRICAL CHARACTERISTICS
XR·2242
Test Conditions: See Figure 3, V + = 5V, TA = 25°C, R = 10 kO, C = 0.1 pF, unless otherwise noted.
XR-2242M XR-2242C
PARAMETERS MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage 4 15 4 15 V
Supply Current 3.5 6 4 7 mA V+ = 5V, VTR = 0, VRS = 5V
Total Circuit 12 16 13 18 mA V+ = 15V, VTR = 0, VRS = 5V
TIME BASE SECTION See Figure 3
Timing Accuracy* 0.5 2.0 0.5 5 % VRS = 0, VTR = 5V
Temperature Drift 150 300 200 ppm/oC V+ = 5V O°C :s T :s 70°C
80 80 ppm/oC V+ = 15V
Supply Drift 0.05 0.2 0.08 0.3 %N V+ ~ 8 Volts
Max Frequency 100 130 130 kHz R = 1 kO, C = C = 0.007 pF
Recommended Range See Figure 5
of Timing Components
Timing Resistor, R 0.001 10 0.001 5 MO
Timing Capacitor, C 0.007 1000 0.01 1000 pF Low-Leakage Capacitor Required.
TRIGGER/RESET CONTROLS
Trigger Measured at Pin 6, VRS =0
Trigger Threshold 1.4 2.0 1.4 2.0 V
Trigger Current 8 10 pA VRS = 0, VTR = 2V
Impedance 25 25 kO
Response Time** 1 1 psec.
Reset Measured at Pin 5, VTR =0
Reset Threshold 1.4 2.0 1.4 2.0 V
Reset Current 8 10 p.A VTR = 0, VRS = 2V
Impedance 25 25 kO
Response Time** 0.8 0.8 p.sec.
COUNTER See Figure 4, V + = 5V
Max. Toggle Rate 0.5 1.0 1.0 MHz VRS = 0, VTR = 5V
Input:
Impedance 20 20 kO
Threshold 1.0 1.4 1.0 1.4 V
Output: Measured at Pins 2 and 3
Rise Time 180 180 nsec. RL = 3KO, CL = 10 pF
Fall Time 180 180 nsec.
Sink Current 3 5 2 4 mA VOL:S O.4V
Leakage Current 0.01 8 0.01 15 }-LA VOH :S 15V
*Timing error solely introduced by XR-2242, measured as % of ideal time-base period of T = 1.00 RC.
* *Propagation delay from application of trigger (or reset) input to corresponding state change in first stage counter
output at pin 2.

JUUl.+ JV

Figure 3. Generalized Test Circuit Figure 4. Test Circuit for Counter Section

5-113
XR·2242
will reset itself and complete its timing cycle after a
time interval of To, when the output at pin 3 goes to a
"high" state. This :orresponds to the "monostable"
mode of operation.

RESET AND TRIGGER INPUTS (PINS 5 AND 6)

The circuit is reset or triggered with positive-going con-

trol pulses applied to pins 5 and 6. The threshold level
TEMPERATURE t CI for these controls is approximately two diode drops (==
1.4V) above ground.
Figure 5. Recommended Range Figure 6. Temperature Drift
of Timing Component Values of Time-Base Period, T
Minimum pulse widths for reset and trigger inputs, mini-
mum trigger delay time and minimum re-trigger delay
DESCRIPTION OF CIRCUIT CONTROLS time are shown in Figures 9 and 10. Once triggered,
the circuit is immune to additional trigger inputs until
COUNTER OUTPUTS (PINS 2 AND 3) the end of the timing cycle.

The binary counter outputs are buffered "open- Note: In noisy operating environment, 0.01 p.F capaci-
collector" type stages. Each output is capable of sink- tors to ground are recommended from reset and trigger
ing == 5 mA of load current. At reset condition, all the terminals.
counter outputs are at high or non-conducting state.
Subsequent to a trigger !nput, the outputs change state When power is applied with no trigger or reset inputs,
in accordance with the timing diagram of Figure 7. the circuit reverts to "reset" state. Once triggered, the
circuit is immune to additional trigger inputs, until the
TRIGGER
INPUT
timing cycle is completed or a reset input is applied. If
(PIN 61 both the reset and the trigger controls are activated si-
TIME BASE multaneously, trigger overrides reset.
I 111111111111111111111111 OUTPUT
IPIN 81

tuuuuJ.no DJJfJO.ilf_. FIRST STAGE

OUTPUT
IPIN 21 ----f-
1---- 128 RC - - - . . . . COUNTER

H
I--L-.....:t'\.L~_ _ _ _ _ _ _: - - -
t
OUTPUT
(PIN 31

Figure 7. Timing Diagram of Output Waveforms 1 ~,':-._ - :.'.:---~,,:----:':-,._-!.

TfUGCER OR Run AMPLITUDE (VOL TSI

Basic circuit connection for timing applications is

Figure 9. Minimum Trigger Figure 10. Trigger and
shown in Figure 8. Subsequent to a positive trigger
pulse applied to pin 6, the timing output at pin 3 goes to
and Reset Pulse Widths at Retrlgger Delay Time
Pins 5 and 6
a "low" state and will stay low for a total time duration (A) Minimum Trigger Delay
To = 128 RC, where Rand C are the timing compo- Time Subsequent to Applica-
nents connected to pin 7. If the switch S1 is open, then tion of Power
the output at pin 3 would alternately change state every
(B) Minimum Re-trlgger
To interval of time, and the circuit would operate in its Time, Subsequent to a Reset
"astable" mode. If the switch S1 is closed, the circuit Input
TIMING TERMINAL (PIN 7)

The time·base period T is determined by the external R-

C network connected to this pin. When the time-base is
triggered, the waveform at pin 7 is an exponential ramp
with a period T = 1.0 RC.

nTAIGGER TIME-BASE OUTPUT (PIN 8)

Time-base output is an open-collector type stage, as

shown in Figure 1 and requires a 20 KG pull-up resistor
to Pin 1 (V +) for proper operation of the circuit. At reset
TO - 128 RC
state, the time·base output is at "high" stage. Subse-
Figure 8. Circuit Connection for Timing Applications (Switch quent to triggering, it produces a negative·going pulse
Sl Open for Astable Operations, Closed for train with a period T = RC, as shown in the diagram of
Monostable Operations) Figure 7.

5-114
TIMING TERMINAL (PIN 7)
XR·2242
cation circuit of Figure 13, the output (pin 3) of Unit 1 is
The time-base period T is determined by the external R- directly connected to the time-base output (pin 8) of
C network connected to this pin. When the time-base is Unit 2, through a common pull·up resistor. In this man-
triggered, the waveform at pin 7 is an exponential ramp ner, the counter section of Unit 2 is triggered every
time the output of Unit 1 make.~ a positive-going transi-
with a period T = 1.0 RC.
tion. The time-base section of Unit 2 is disabled by con-
TIME-BASE OUTPUT (PIN 8) nection pin 7 of Unit 2 to ground through a 1 KG resis-
tor. The reset and trigger terminals of both units are
Time-base output is an open-collector type stage, as
connected together for common controls. If an addi-
shown in Figure 1 and requires a 20 KG pull-up resistor
tional XR-2242 were cascaded with Unit 2 of Figure 13,
to Pin 1 (V +) for proper operation of the circuit. At re-
the total available time delay can be extended to
set state the time-base output is at "high" stage. Sub-
(1.065) (10 9) RC. With an external RC = 0.1 sec, this
sequent 'to triggering, it produces a neg~tive-goi~g
would correspond to a time delay of 3.4 years.
pulse train with a period T = RC, as shown In the dIa-

.~
gram of Figure 7.
, B , e III

ASTABLE OPERATION
, ,."" . "
'" ',.,,.,' ~
The XR-2242 can be operated in its astable or free-
running mode by disconnecting the reset te.rmina.1 (pi~
.'..'~'
,
"1"1-
" , , R,"".,.,
1-[' , • , R., .. ,
5) from the counter output (pin 3). T~o tYPical clrc~lt
connections for this mode of operation are shown In 1" ". .
To = (2 8 - 1)(2') RC = 32.640 RC
Figures 11 and 12. In the circuit connection of Fig~re ,

11, the circuit operates in its free-running mode, v.:lth Figure 13. Cascaded Operation of Two XR-2242 Timer
external trigger and reset signals. It will start counting Circuits
and timing subsequent to a trigger input until an exter-

•
nal reset pulse is applied. Upon application of a b) Sequential Timing:
positive-going reset signal to pin 5, the circuit reverts
Two XR-2242 timers can be cascaded to produce se-
back to its rest state. The circuit of Figure 11 is essen-
quential or delayed-timing pulses as shown in Figure
tially the same as that of Figure 8, with the feedback
14. In this configuration, the second timer is triggered
switch S1 open.
by the first timer, subsequent to the completion of its
The circuit of Figure 12 is deSigned for continuous op- timing cycle. Thus, the triggering of Unit 2 is delayed by
eration. The circuit self-triggering automatically when a time interval, T1 (= 128 R1C1) corresponding to the
the power supply is turned on, and continues to operate timing cycle of Unit 1.
in its free-running mode indefinitely.
The output of Unit 2, which is normally at "high" state
will stay high for a duration of T1 = 128 R1 C1, subse-
quent to the application of a trigger pulse; then go to a
low state for a du ration of T2 = 128 R2C2 correspond-
ing to the timing interval of Unit 2; and finally revert
back to its rest state after the completion of the entire
timing sequence.

B
Figure 11. Astable Operation with
External Trigger and Reset
Figure 12. Free-running Operation
Self-Triggered When Power
, ~
'~'O" ~I'

;>OK
e 1'1,

c,

Controls Supply Is Turned On "" , ",,,,' ' ..,,.,' '"l

ou"u, u,"",.o/ ... c/ UlII'fHOI -

J ~ H'" 01 1 (; It TRIGGI"
OPERATION WITH EXTERNAL CLOCK -~. • • S It llltSll

The XR-2242 can be operated with an external clock or I" -I 1- ' " . • ...
T, T't ".,,,,, ".,,..,',
time-base, by disabling the internal time-base oscillator
and applying the external clock input to pin 8. The inter- Figuro 14, Sequential Timing USing Two XR-2242 Timer
nal time-base can be de-activated by connecting a 1 KG Circuits
resistor from pin 7 to ground. The counters are trigger-
ed on the negative-going edges of the external clock
pulse. For proper operation, a minimum clock pulse
amplitude of 3 volts is required. Minimum external
clock pulse width must be ~ 1 /-,S.
CASCADED OPERATION:
a) Ultra-Long Delay Generation:
Ultra-long time delays, up to one-year duration, can be
generated by cascading two XR-2242 timers as shown
in Figure 13. In this configuration, the counter section
of Unit 2 is cascaded with the counter output of Unit 1,
to provide a total count of 32,640 clock cycles before
the output (pin 3 of Unit 2) changes state. In the appli- EQUIVALENT SCHEMATIC DIAGRAM
5-115
 XR-2243

Micropower Long Range Timer

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2243 is a monolithic Timer/Controller capable
of producing ultra-long time delays from micro-seconds
to days. Two timing circuits can be cascaded to gener-
ate time delays or timing intervals up to one year. The
circuit is comprised of an internal time-base oscillator,
an 11-bit binary counter and a control flop-flop. For a
given external R-C network connected to the timing ter-
minal, the circuit produces an output timing pulse of
1024 RC. If the two circuits are cascaded, a total time
delay of (1024)2 or 1,048,576 RC is obtained.

The XR-2243 long range timer was designed for low

power operation. Its supply current requires less than
100 p.A in standby or reset mode. Normal operation re-
quires less than 1mA.

The timing cycle is initiated by applying a positive going

pulse to the trigger input, Pin 6. The time-base oscilla-
tor generates timing pulses with its period, T, equal to 1
RC. These clock pulses are counted by the binary High Accuracy: 0.5%
counter section. The timing cycle is completed when a Excellent Supply Rejection
positive-going reset pulse is applied to Pin 5. Monostable and Astable Operation
Micro Power Consumption-Standby Operation
In monostable timer applications, the output terminal
Low Power Consumption-Normal Operation
(Pin 3) is connected to the reset terminal, Pin 5. In this
manner, after 1024 clock pulses are counted, this out-
put goes to "high" state and resets the circuit, thus ABSOLUTE MAXIMUM RATINGS
completing the timing cycle. Therefore, after triggering,
Power Supply 18 Volts
the output at Pin 3 will produce a total timing pulse of
1024 RC before the circuit resets itself to complete the Power Dissipation (package limitation)
Ceramic Package 385 mW
timing cycle. During the timing interval, the secondary
Plastic package 300 mW
output at Pin 2 produces a square-wave output with the
Derate above + 25°C 2.5 mW/oC
period of 2 RC.
Temperature Range
If the output at Pin 3 is not connected back to the reset Operating
terminal, the circuit continues to operate in an astable XR-2243C O°C to + 70°C
mode, subsequent to a trigger input. Storage - 65°C to + 150°C

APPLICATIONS ORDERING INFORMATION

Long Delay Generation Part Number Package Operating Temperature

Sequential Timing XR-2243CN Ceramic O°C to + 70°C
Precision Timing XR-2243CP Plastic O°C to + 70°C
Ultra-Low Frequency Oscillator
Battery Powered Applications PRINCIPLES OF OPERATION
FEATURES The ultra-long time delay micropower timer, in simplest
block diagram terms, consists of a timing section fol-
High Output Current Sink Capability lowed by a counter section and a control flip-flop.
Timing from Micro-seconds to Days
Wide Supply Range: 2.2V to 15V The main functional portion of the circuit is the time
TTL and DTL Compatible Outputs base section. It is a relaxation oscillator whose period

5-116
 ELECTRICAL CHARACTERISTICS
XR·2243
Test Conditions: See Figure 3, V + = 5V, TA = 25°C, R = 22 kO, C = 0.047 JLF, unless otherwise noted.

XR-2243C
PARAMETERS MIN TYP MAX UNIT CONDITIONS
Supply Voltage 2.7 15 V
Supply Current 45 95 JLA VCC = 2.7V VTR = OV VRS = 5V
Standby 80 135 JLA VCC = 5V
250 415 JLA VCC = 15V
Operating 900 1000 JLA VCC = 5V VTR = 5V VRS = OV
750 900 JLA VCC = 2.7V
1250 1500 JLA VCC = 15V
Time Base Section
Timing Accuracy· 0.5 3 % VCC = 2.7V VTR = 5V VRS = OV
Temperature Drift 80 125 ppm/oC VCC = 5V
150 225 ppm/oC VCC = 15V O°C s TA s 70°C
300 650 ppm/oC VCC = 8V
Supply Drift 0.30 1.0 %/V
Maximum Frequency 25 35 kHz
Recommended Range of
Timing Components
Timing Resistor, R 0.005 10 mO
Timing Capacitor, C 0.005 1000 JLF

II
Trigger/Reset Controls
Trigger Measures at Pin 6, VRS = 0
Trigger Threshold 1.4 2.0 V
Trigger Current 22 30 JLA VRS = 0, VTR = 2V
Impedance 25 kO
Response Time
Reset
Reset Threshold 1.4 2.0 V
Reset Current 22 30 JLA VTR = 0, VRS = 2V
Impedance 25 kO
Response Time
Counter Section See Figure 4, V+ = 5V
Max. Toggle Rate 100 250 kHz VRS = 0, VTR = 5V
Measured at Pin 8
Input:
Impedance 15 kO
Threshold 1.4 V
Output:
Sink Current 10 mA VOL s O.4V
Leakage Current 0.01 JLA VOH s 15V

Figure 1. Simplified Circuit Schematic

5-117
XR·2243
of oscillation is determined by the external Rand C val- a divide by 2 block. With eleven stages, one could cre-
ues. The timing section is followed by an 12L counter, ate delays of 1024 RC in a monostable mode of opera-
which consists of eleven binary stages, with high cur- tion. The counters change state on the falling edge of
rent drive capability output stages from the first and the the clock pulses.
last. A third subsection of the circuit is the control logic
circuit consisting of a flip-flop that is set and reset by When the trigger pulse is applied, the internal power
Pins 6 and 5, respectively. This section controls the re- line which is supplying voltage for 12L circuitry (12LVCc)
setting of all counter stages, and starting the timing cir- is set up first, a Schmitt trigger circuit with a built in de-
cuit upon application of a positive-going trigger pulse. lay ensures the application of an internal set pulse,
The control logic also activates the power shut down right after the power for the 12 section is made avail-
circuit when a reset pulse is received, or when the tim- able. The counters are all set to "1" and are ready to
ing cycle is completed. The power shut down circuit count with the incoming falling edges of clock im-
turns off the bias line to the time base and 12L counters pulses.
to reduce the standby power.
OUTPUT SECTIONS (Pins 2 and 3)
CONTROL FLIP-FLOP
The output sections are deSigned such that they can
The logic flip-flop circuit controls the time/counter, as handle 1OmA load currents @ VOL = 300mV. Both of
well as the internal power, to reduce standby current the transistors in this section are operating in a non-
consumption to approximately 100pA Upon command, saturated mode because of the clamping action. This
by a positive-going trigger pulse applied to Pin 6, the ensures faster operation and also decreases the need
control logic circuit will first establish the upper and of high base drive at full load operation.
lower threshold voltages and then setup all internal cur-
rent sources, biasing the time base and counter sec- The timing cycle for the circuit is initiated by applying a
tions. positive-going trigger to the set, or trigger pin, (Pin 6) of
the device. The trigger pulse actuates the time base os-
The circuit will automatically reset itself when power is cillator, enables the counter section, and sets the out-
first applied. Once triggered, the circuit is immune to puts to "low" state. The time base oscillator generates
additional trigger pulses until it is reset. A reset pin ter- timing pulses with its period, T = 1RC. These timing or
minates the timing cycle by resetting the internal logic clock pulses are counted by the binary counter section.
and shuts off the internal bias circuitry. The timing cycle is completed when a positive-going re-
set pulse is applied to the reset pin (Pin 5).
TIME BASE OSCILLATOR
,.----------..---0 -vcc
The time base oscillator is a simple exponential ramp
type timer circuit. The timing components, Rand C, are
external to the chip. The operation of such an oscillator
can be described as follows: when the circuit is at rest
the flip-flop is latched in its reset state, the discharge
transistor is "off", and the external capacitor, C, is fully
charged to a voltage approximately equal to VCC. fo.To..j
When the circuit is triggered, the flip-flop is unlatched L-..J
OUTPUT
and set, which causes the discharge transistor to turn
"on" and discharge C rapidly. When the voltage across
C discharges to the voltage level Vth _, the upper com- 51 51K
L------O"
parator changes state, resets the flip-flop and turns the
TO'I02.RC
discharge transistor "off". Then, C charges toward
VCC with a time constant set by the external Rand C.
When the voltage across it reaches the upper thresh- Figure 2. Typical Operation Diagram
old, Vth+, the comparator changes state, sets the flip-
flop again, and discharges C back to the lower thresh- ASTABLE AND MONOSTABLE MODE
old level, Vth _. In this manner, the circuit continues to
oscillate with the voltage level across C exponentially Figure 2 shows the basic connection diagram for
rising to Vth + ' then rapidly decaying to Vth _ and then astable and monostable modes. When switch S1 is
repeating this cycle until the timing period ends. open, the circuit is in its astable mode of operation.
Upon the 8pplication of a trigger pulse, the time base
COUNTER SECTION (Pin 8) oscillator resumes the timing cycles. Until the applica-
tion of a reset pulse, the circuit will keep on working
The counter consists of eleven stages connected in a while generating a square wave at the last stage out-
"ripple counter" configuration. The operating injector put, whose frequency is 1/2048 of the time base oscilla-
currents are set from a bus of 1.2 volts. This current is tor frequency. When switch S1 is closed, the circuit is
supply independent. Pin 8, which is time based o/p, is' in its monostable mode of operation, with the last stage
also the counter section input. being connected to the reset input via an external resis-
tor. This way, when a trigger pulse is applied, and the
12L counters are Ootype flip-flops with their Q output in- time base resumes its timing cycle, the last stage out-
ternally connected to their 0 input; basically, they form put will go low with the first pulse generated by the time
5-118
base generator, and will stay low for 1024 pulses. With
XR·2243
(1024)3 RC time delay, and so on. Thus, one can easily
the arrival of the 1024th pulse, the last output will go to achieve time delays in the range of days, months, or
a high state since it is coupled to the reset input (see years, simply by cascading two or three such counter!
Figure 3). When this stage goes high, the timing cycle timer circuits.
is completed.
Figure 4 shows the basic connection for cascaded op-
TRII~g~~J
eration. Unit 2's time base is disabled by grounding Pin
(PIN 6) '----------------- 7 to ground via 1 kO resistor. The last stage output of
Unit 1 is connected to the input of the counter section
TI~~!~~8~ I I I I I I I I I I I I I I I I I I I I I I I I I I I I of Unit 2. When the circuit is triggered, Unit 1 will
FIRST
resume generating a frequency whose period T =
STAGE
OUTPUT
RextCext. The output of Unit 1 will change state every
(PIN 2) If------- I 1024 pulses. Since these pulses are supplied to Unit 2,
cg~~~5~_,
(PIN 3) L..-------S5;--------I
.- the circuit will stop the timing cycle after 1024 pulses
are generated by Unit 1. Therefore, a time delay of
Figure 3. Timing Diagram of Output Waveforms (1024)2 RC is generated.

SEQUENTIAL TIMING APPLICATIONS

CASCADED MODE
Figure 5 shows the basic connections for sequential
The cascaded mode of operation allows the generation timing applications. In this mode of operation, Unit 2's
of ultra-long time delays. When several XR-2243 cir- trigger input is connected to Unit 1's last output, while
cuits are cascaded, such that their counter sections each unit's reset input is connected to their last output
are connected in series, the total count available in- via external resistors. This way, Unit 1 will generate a
creases geometrically rather than arithmetically. Since time delay 1024 R1C1 upon the application of a trigger

•
one XR-2243 is capable of generating a total of 1024 pulse. Once 1024 R1C1 seconds have elapsed, Unit 2
RC time delay, where Rand C are the external timing will be triggered, generating in its turn a delay equal to
components, then when two such timers are cascaded, 1024 R2C2 seconds; therefore, resulting in an overall
they will produce (1024)2 RC and three will produce time delay of 1024 R1C1 + 1024 R2C2 .

•v c c o - - - - . , - -_ _ _ _ _ _ _ _ _ _ _ _- - - - - - - - . . ,

Figure 4. Cascaded Operation of Two XR-2243 Timer Circuits

.vcc--<~-------- __- - _ - - - - - - - - _ _ ,

A, A,

C,
UN'~NO.
1----i--o<)TAIGGEA SL
1--"""--o<)AESET JL

Figure 5. Sequential Timing Using XR-2243 Timer Circuits

5-119
Both linear ramp waveforms have pk-pk amplitudes of acteristics. A simpler, and more practical, sine shaper
2VBE· Their frequency of oscillation, fo, can be deter- for monolithic circuits employs the "gradual cutoff"
mined from the formula characteristics of a basic differential gain stage, as in
Figure 3.
11
fo = ---.
4VBECo Reduction of the emitter = degeneration resistance, RE,
allows either transistor 03 or 04 to be brought near
And fo can be controlled by variation of charging- their cutoff point when the input triangle waveform
current 11 via control voltage VC. A subtraction of one reaches its peaks. For the proper choice of the input
output ramp voltage from the other, by use of a simple amplitude and bias-current levels, the transfer charac-
differential amplifier, obtains the linear triangular wave- teristics at the peaks of the input triangle waveform be-
form. come logarithmic rather than linear. Thus, the peaks of
the triangle become rounded, and the output appears
Symmetry of triangle and square-wave outputs may be as a low distortion sine wave.
adjusted by replacement of one of the two current
sources in Figure 2 by 12, where 12 =I: 11. Then the duty Use of this technique permits output harmonics to be
cycle of the output waveforms becomes the following: reduced to less than 0.5% with only a single adjust-
ment. The low distortion is possible because the tech-
nique relies on component matching rather than their
Duty Cycle = 50 ~ %. absolute values. Since monolithic ICs can be designed
12 readily for close matching, this wave-shaping is ideally
suited to monolithic design.
The duty cycle of the output may be varied over a wide
range by varying the ratio of the currents 11 and 12.
~---------'------~V+

Wave-Shaping Techniques
~-----o SINE WAVE
OUTPUT
The most useful waveform in Signal processing applica-
tions is the sine wave. In the design of function genera- r-v
tors, sinusoidal output is normally obtained by passing N
TRWlGLE
a triangular wave through a wave shaping circuit. In INPUT
most discrete-component generators, wave-shaping in-
volves a diode-resistor or a transistor-resistor ladder
network. Introduction of a finite number of "break
points" on the triangle wave changes it to a lower dis-
tortion sine wave.

Although this method can also be adapted to monolithic Figure 3. Conversion of triangle to sine wave employs a
circuits, it is not as practical because it requires· ex- differential gain stage, which avoids dependence
tremely tight control of resistor values and diode char- on absolute values of components.

5-120
 Section 5 - Industrial Circuits
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . · 5-121
XR-494 Pulse-Width Modulating Regulator . . . . . . . . · 5-122
XR-495 Pulse-Width Modulating Regulator . . . . . . . . · 5-126
XR-1468/1568 Dual Polarity Tracking Voltage Regulators · 5-130
XR-1524/2524/3524 Pulse-Width Modulating Regulators . · 5-132
XR-1525A12525A/3525A,
XR-1527A12527A/3527A Pulse-Width Modulating Regulators · 5-140
XR-1543/2543/3543 Power Supply Output Supervisory Circuits · 5-147
XR-2230 Pulse-Width Modulator Control System · 5-155
XR-4194 Dual-Tracking Voltage Regulator . . . · 5-162
XR-4195 ± 15 V Dual-Tracking Voltage Regulator · 5-165

5-121
 XR-494

Pulse-Width Modulating Regulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-494 is a monolithic pulse width modulating reg-
ulator designed to contain all the blocks necessary for
a switching regulator. Included in a 16 pin dual in-line
package is a voltage reference, oscillator, control logic, 'NV
INPUT
error amplifiers, and dual uncommitted outputs. This
device can be used for switching regulators of either FEED REF
BACK OUT
polarity, polarity converters, transformer coupled DC to
DC converters, transformerless voltage doublers, and DEAO
OUTPUT
I---! f-----f'
many other power control applications. The XR-494M is TIME
CONTROL
4
CONTROL

fully specified for operation over the full military tem-

perature range from - 55°C to + 125°C, while the XR-
494CN and XR-494CP are designed for commercial ap-
plications over O°C to + 70°C.

FEATURES
Complete PWM Power Control Circuitry
Uncommitted Outputs for 200-mA Sink or Source ORDERING INFORMATION
Output Control Selects Single-Ended
or Push-Pull Operation Part Number Package Operating Temperature
Internal Circuitry Prohibits Double Pulse XR-494M Ceramic - 55°C to + 125°C
at Either Output XR-494CN Ceramic O°C to + 70°C
Variable Dead Time Provides Control Over Total XR-494CP Plastic O°C to + 70°C
Range
Internal Regulator Provides a Stable SYSTEM DESCRIPTION
5-V Reference Supply
Circuit Architecture Provides Easy Synchronization All functions required to construct a pulse-width modu-
lating regulator are incorporated on a single monolithic
chip in the XR-494. The device is primarily deSigned for
power supply control and contains a on-chip five volt
APPLICATIONS regulator, two error amplifiers, an adjustable oscillator,
dead-time control comparator, a pulse-steering flip-flop,
Pulse-Width Modulated Power Control Systems and output control circuits. Either common emitter or
Switching Regulators emitter follower output capability is provided by the un-
committed output transistors. Single ended or push-pull
output operation may be selected through the output
control function. The XR-494 architecture prohibits the
ABSOLUTE MAXIMUM RATINGS, TA = 25°C possibility of either output being pulsed twice during
push-pull operation. The internal amplifiers's circuitry
Amplifier Input Voltages VCC + 0.3 Volts allows for a common-mode input voltage range of - 0.3
Output Current 250 rnA volt to VCC - 2 volts. The dead time control compara-
Supply Voltage 41 Volts tor provides approximately 5% dead time unless the
Collector Output Voltage 41 Volts dead time control is externally driven. The on-Chip
Power Dissipation oscillator may be used to drive the common XR-494
Total, at or below 25°C 1000 mW circuitry and provide a sawtooth input for associated
Ceramic Package control circuitry in synchronous multiple-rail power
Derate above + 28°C supplies, or may be bypassed by terminating RT (Pin 6)
Plastic Package to the reference output and providing a sawtooth input
Derate above + 41°C to CT (Pin 5).

5-122
ELECTRICAL CHARACTERISTICS
XR·494
Test Conditions: TA == 25°C, unless otherwise specified.
XR-494
PARAMETERS MIN TYP MAX UNIT CONDITIONS
Reference Section
Output Voltage (V ref) 4.75 5.0 5.25 V 10 == 1mA
Input Regulation 2.0 25.0 mV VCC == 7V to 40V
Output Regulation 1 15 mV 10 = 1 to lOmA
Output Voltage Change 0.2 1 % ~TA = Min to Max
with Temperature
Short Circuit Output 1 10 35 50 mA Vref =0
Current
Oscillator Section
Frequency 10 kHz CT = 0.01 JLF, RT = 12kO
Standard Deviation 2 10 % VCC, CT, RT, TA;
of Frequency all values constant
Frequency Change with 0.1 % VCC = 7V to 40V
Voltage
Frequency Change with 2 % CT = 0.01 JLF, RT == 12kO,
Temperature ~TA = Min to Max
Dead Time Control Section
(See Figure 2)
Input Bias Current (Pin 4) -2 -10 JLA VI = 0 to 5.25V
Maximum Duty Cycle 45 % VI = 0 (Pin 4)

•
(each output)
Input Threshold Voltage 3 3.3 V Zero Duty Cycle, Maximum
(Pin 4) Duty Cycle = OV Min
Error-Amplifier Sections
Input Offset Voltage 2 10 mV Vo (Pin 3) == 2.5V
Input Offset Current 25 250 nA Vo (Pin 3) = 2.5V
Input Bias Current 0.2 1 JLA Vo (Pin 3) = 2.5V
Common-Mode Input -0.3 to V VCC == 7V to 40V
Voltage Range VCC -2
Open Loop Voltage 70 95 dB ~VO = 3V, Vo =
Amplification 0.5V to 3.5V
Unity Gain Bandwidth 800 kHz
Common·Mode Rejection 65 80 dB VCC = 40V
Ratio
Output Sink Current 0.3 0.7 mA V,O == - 15mV to - 5V, V
(Pin 3) (Pin 3) = 0.7V
Output Source Current ·2 mA VID == 15mV to 5V, V
(Pin 3) (Pin 3) = 3.5V
Output Section
Collector Off·State Current 2 100 p.A VCE = 40V, VCC = 40V
Emitter Off·State Current -100 p.A VCC = Vc = 40V, VE = 0,
XR·494M Max = - 150p.A
Coliector·Emitter Saturation
Voltage Common·Emitter 1.1 1.3 V VE == a, Ic = 200mA,
XR·494M Max = 1.5V
Emitter·Foliower 1.5 2.5 V Vc == 15V, IE == -200mA
Output Control Input 3.5 mA VI = Vref
Current
PWM Comparator Section
Input Threshold Voltage 4 4.5 V Zero Duty Cycle
(Pin 3)
Input Sink Current (Pin 3) 0.3 0.7 mA V (Pin 3) == 0.7V
Total Device
Standby Supply Current 6 10 mA VCC == 15V, Pin 6 at Vref
9 15 mA VCC == 40V, All Other Inputs
and Outputs Open
Average Supply Current 7.5 mA V = 2V (Pin 4)

5-123
XR·494
RECOMMENDED OPERATING CONDITIONS

XR-494CN
XR-494M XR-494CP
PARAMETERS MIN MAX MIN MAX UNIT
Supply voltage, VCC 7 40 7 40 V
Amplifier input voltages, VI -0.3 VCC -2 -0.3 VCC -2 V
Collector output voltage, Vo 40 40 V
Collector output current 200 200 mA
(each transistor)
Current into feedback terminal 0.3 0.3 mA
Timing capacitor, CT 0.47 10,000 0.47 10,000 nF
Timing resistor, RT 1.8 500 1.8 500 kO
Oscillator frequency 1 300 1 300 kHz
Operating free-air temperature, TA -55 125 0 75 °c

SWITCHING CHARACTERISTICS TA = 25°C

PARAMETER MIN. Typ.1 MAX. UNIT TEST CONDITIONS
Output Voltage Rise Time 100 200 ns Common-Emitter Configuration.
Output Voltage Fall Time 25 100 ns See Figure 1
Output Voltage Rise Time 100 200 ns Emitter-Follower Configuration,
Output Voltage Fall Time 40 100 ns See Figure 2
1. All typical values except for temperature coefficients are at TA = 25°C.

r '"
- - - - -
IlACHOU1PuT

___
-

''''''''-(1' c.
1
I

I
I
l,'~

T11"'CLUOESPIIOeEAJiO
JIGCaPACIU,IrICE)
-

"""'' G' .-
IEACI'tOUTPUT

--
1
1_._

I
I
I
J
--+--t :(f0"""'
'. ~

J ~
_______ J ~.~'
Cl I~'I'
IINCLUOES'II0lEAND
JIQC",PACIUHCEI

Figure 1. Common-Emitter Configuration

Figure 2. Emitter-Follower Configuration

V, FUNCTION TABLE

INPUTS
OUTPUT CONTROL OUTPUT FUNCTION
VREF 0-----1
Grounded Single-ended or parallel output
At Vref Normal push-pull operation
At Vref PWM Output at 01
At Vref PWM Output at 02
Figure 3. Error-Amplifier Characteristics

5-124
 OUTPUT
CONTROL
XR·494
(SEE FUNCTION
TABLE)

--------CI

~--------- EI

RT--------~r_----,
1-----4~-_I .J}--+--1I""In.-_....1- - - - - - - - - - - C2
CT----r---~~~~ ~------E2

DEAD • O.IV
TIME - - 1 1 - + - - - 1 ........
CONTROL

NONINVERriNG INPUT -------f<f'o,

INVERTING INPUT - - - -__-1:"/

NONINVERTING INPUT ------f.~

INVERTING INPUT - - - - - - t.....
FEEDBACK - _ _ _ _ _ _ _ _---l

EQUIVALENT SCHEMATIC DIAGRAM

lJUllJ1fInr--
VCC
Yee" UY YOlT"C£
AT C1
u u____ • ,.--,,_ _ _ - Vee
VOLTACE
AT C2
OUTPUT 1

•
rUOeACI(
°T
OT
C2 OUTPUT 2 VOlUGE
E2 ~ AT C,

1'1 }
(-, ERROR
C·,
C-I
OU'!PUT
COUTROL

'DUTY
CYCLE
e. VOlTACE WAVEFORMS

Figure 4. Dead-Time and Feedback Control

OSCILL.ATOR FREQUENCY .od

FAEQUENCY VAR'AT10N' VI
TIMING RESISTANCE

;~c :~:VJ
r--r-.,. VCC l,sv
H"" J.1Tttl J.t-H~ ODO",lllJ
""-
.l.Voz3V
TA "25C
-

I
0'.

~O1,'
O.Ol"F

1IrJ>..-nl
FREQ
VAAl
3:+'"-'
'"'" l'\.
Cr" .. F I 11* ILl
'" [\

III I
RT-TIMING RESISTANCE-"
N
III~ 11111
N

0
1K
'" '"'\.
1 Frequency variation Is the change In oscillator frequency that I-FREQUENCY-Hz
occurs over the lull temperature range.

Figure 5. Oscillator Frequency and Frequency Variation 1 vs Figure 6. Amplifier Voltage Amplification vs Frequency
Timing Resistance

5-125
 XR-495
Pulse-Width Modulating Regulator
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-495 is a monolithic pulse width modulating reg- NON
INV
ulator designed to contain all blocks necessary for a INPUT

switching regulator. Included in the 16 pin dual in-line

packages is a voltage reference, oscillator, control INV
INPUT
INV
INPUT
logic, error amplifiers, and dual uncommitted outputs.
This device can be used for switching regulators of ei- FEED REF
ther polarity, polarity converters, transformer coupled BACK OUT

DC to DC converters, transformerless voltage dou-

blers, and many other power control applications. A DEAD
TIME 4
39V zener diode allows operation with supply voltages CONTROL

exceeding 40V. The XR-495M is fully specified for oper-

OUTPUT
ation over the full military temperature range from - CONTROL
55°C to + 125°C, while the XR-495CN and XR-495CP
are designed for commercial applications over O°C to STEERING
+ 70 o e. INPUT

FEATURES
Complete PWM Power Control Circuitry
Uncommitted Outputs for 200-mA Sink or Source Cl
Output Control Selects Single-Ended
or Push-Pull Operation
El
Internal Circuitry Prohibits Double Pulse
at Either Output
Variable Dead Time Provides Control Over Total Range SYSTEM DESCRIPTION
Internal Regulator Provides a Stable
5-V Reference Supply All functions required to construct a pulse-width modu-
Circuit Architecture Provides Easy Synchronization lating regulator are incorporated on a single monolithic
On-Chip 39-V Zener chip in the XR-495. The device is primarily designed for
External Control of Output Steering power supply control and contains a on-chip five volt
regulator, two error amplifiers, an adjustable oscillator,
APPLICATIONS dead-time control comparator, a pulse-steering flip-flop,
and output control circuits. Either common emitter or
Pulse-Width Modulated Power Control Systems
emitter follower output capability is provided by the un-
Switching Regulators
committed output transistors. Single ended or push-pull
ORDERING INFORMATION output operation may be selected through the output
control function. The XR-495 architecture prohibits the
Part Number Package Operating Temperature possibility of either output being pulsed twice during
XR-495M Ceramic - 55°C to + 125°C push-pull operation. The internal amplifier's circuitry al-
XR-495CN Ceramic O°C to + 70°C lows for a common-mode input voltage range of - 0.3
XR-495CP Plastic O°C to + 70°C volt to VCC - 2 volts. The dead time control compara-
tor provides approximately 5 % dead time unless the
ABSOLUTE MAXIMUM RATINGS, TA = 25°C dead time control is externally driven. The on-chip os-
cillator may be used to drive the common XR-495 cir-
Amplifier Input Voltages VCC + 0.3 Volts cuitry and provide a sawtooth input for associated con-
Output Current 250 mA trol circuitry in synchronous multiple-rail power sup-
Supply Voltage 41 Volts plies, or may be bypassed by terminating RT (Pin 6) to
Collector Output Voltage 41 Volts the reference output and providing a sawtooth input to
Power Dissipation CT (Pin 5).
Total, at or below 25°C 1000 mW
Ceramic Package The XR-495 also contains an on-chip 39 volt zener di-
Derate above + 28°C ode for high voltage applications where VCC is greater
Plastic Package than 40 volts, and an output steering control that over-
Derate above + 41°C rides the internal control of the pulse steering flip-flop.
5-126
ELECTRICAL CHARACTERISTICS
XR·495
Test Conditions: TA = 25°C, unless specified otherwise.
XR-495

PARAMETERS MIN TYP MAX UNIT CONDITIONS

Reference Section
Output Voltage (V ref) 4.75 5.0 5.25 V 10 = 1mA
Input Regulation 2.0 25.0 mV VCC = 7V to 40V
Output Regulation 1 15 mV 10 = 1 to 10mA
Output Voltage Change 0.2 1 % ~TA = Min to Max
with Temperature
Short Circuit Output 1 Current 10 35 50 mA Vref = 0
Oscillator Section
Frequency 10 kHz CT = 0.01 !J., RT = 12kn
Standard Deviation 2 of 10 % VCC, CT, RT, TA; all values constant
Frequency
Frequency Change with Voltage 0.1 % VCC = 7V to 40V
Frequency Change with 2 % CT = 0.01!J. F, RT = 12kn,
Temperature ~TA = Min to Max

Dead Time Control Section

(See Figure 2)
Input Bias Current (Pin 4) -2 -10 !J.A VI = 0 to 5.25V
Maximum Duty Cycle 45 % VI = 0 (Pin 4)
(each output)
Input Threshold Voltage (Pin 4) 3 3.3 V Zero Duty Cycle, Maximum Duty
Cycle = OV Min
Error-Amplifier Sections
Input Offset Voltage
Input Offset Current
Input Bias Current
Common-Mode Input Voltage
Range
-0.3 to
VCC -2
2
25
0.2
10
250
1
mV
nA
!J.A
V
Vo (Pin
Vo (Pin
Vo (Pin
VCC =
3) =
3) =
3) =
7V to
2.5V
2.5V
2.5V
40V
II
Open Loop Voltage 70 95 dB ~VO = 3V, Vo '" 0.5V to 3.5V
Amplification
Unity Gain Bandwidth 800 kHz
Common-Mode Rejection Ratio 65 80 dB VCC = 40V
Output Sink Current (Pin 3) 0.3 0.7 mA VID = -15mV to -5V, V (Pin 3) = 0.7V
Output Source Current (Pin 3) -2 mA VID = 15mV to 5V, V (Pin 3) = 3.5V
Output Section
Collector Off-State Current 2 100 !J.A VCE = 40V, Vce = 40V
Emitter Off-State Current -100 !J.A VCC = Ve = 40V, VE = 0,
XR-494M Max = - 15O!J.A
Collector-Emitter Saturation
Voltage Common-Emitter 1.1 1.3 V VE = 0, IC = 200mA,
XR-494M Max = 1.5V
Emitter-Follower 1.5 2.5 V Ve = 15V, IE '" -200mA
Output Control Input Current 3.5 mA VI = Vref
PWM Comparator Section
Input Threshold Voltage (Pin 3) 4 4.5 V Zero Duty Cycle
Input Sink Current (Pin 3) 0.3 0.7 mA V (Pin 3) = 0.7V
Total Device
Standby Supply Current 6 10 mA VCC = 15V, Pin 6 at Vref
9 15 mA VCC = 40V, All Other Inputs
and Outputs Open
Average Supply Current 7.5 mA V = 2V (Pin 4)

1. Duration of the short circuit should not exceed one second.

2. Standard deviation is a measure of the statistical distribution about the mean as derived from the formula a =.

SWITCHING CHARACTERISTICS TA = 25°C

PARAMETER MIN Typ1 MAX. UNIT TEST CONDITIONS

Output Voltage Rise Time 100 200 ns Common-Emitter Configuration,
Output Voltage Fall Time 25 100 ns See Figure 1
Output Voltage Rise Time 100 200 ns Emitter-Follower Configuration,
Output Voltage Fall Time 40 100 ns See Figure 2
1. All typical values except for temperature coefficients are at TA = 25°C.
5-127
XR·495
RECOMMENDED OPERATING CONDITIONS

XR-495CN
XR-495M XR-495CP
PARAMETERS MIN MAX MIN MAX UNIT
Supply voltage, VCC 7 40 7 40 V
Amplifier input voltages, VI -0.3 VCC-2 -0.3 VCC-2 V
Collector output voltage, Vo 40 40 V
Collector output current (each transistor) 200 200 mA
Current into feedback terminal 0.3 0.3 mA
Timing capacitor, CT 0.47 10,000 0.47 10,000 nF
Timing resistor, RT 1.8 500 1.8 500 kO
Oscillator frequency 1 300 1 300 kHz
Operating free-air temperature, TA -55 125 0 75 °C

,---------1
(EA~I~g~~uT
r-----------,
(EACH OUTPUT I
.,w" :

I ,-~I__--~
I

CIRCUIT) I I
I
I
I
CL. 15 pI'
(INCLUDES PROBE AND
I
JIG C.P....CIT.NCE) I
I

I
IL _________ .JI
.,w"
CL" 150 pF
IL __________ .JI (INCLUDES PROBE AND
JIG CAPACITANCE)

A) TEST CIRCUIT

I
,,--+--1
HI OUTPUT YOL lAGE WAvEFORM BI OUTPUT VOLTAGE WAVEFORM

Figure 1. Common-Emitter Configuration Figure 2. Emitter-Follower Configuration

r---.~----.----Vce
VCC·15V VOLTAGE
ATCI

I SOli ---- 0
2W
,...._•..-___ - Vce
VOLTAGE
OUTPUT I AT C2
TEST ( --- 0
INPUTS
OUTPUT :2 VOLTAGE
AT CT
(OPEN)
(O;;O:;';i O£it.i)..iiili~
CONTROL
INPUT
OV I
I
I
fEEDBACK I
I
I
O.7V
DUTY MAX
CYCLE
A) TES T CIRCUIT 8) VOLTAGE WAVEfORMS

Figure 3. Dead-Time and Feedback Control

5-128
 r----- ---, OUTPUT
CONTROL
I STEERING I (SEE FUNCTION
I CONTROL J TABLE)
L__ ~-"""i'v-...!I---, _-----C1

"------E1

RT -------l---, ------C2

CT---~---L----~ '------E2
DEAD D.1V
TIME ~ I--+--~";
CDNTROL
r-
r - - - - - - - - - - - - ' - + I - - - . - - - - - - - VCC

I
I
NON INVERTING INPUT ------f+'o I I-----~~~
INVERTING INPUT ------b" I
I
NONINVERTING INPUT - - - - - - 1 ......
INVERTING INPUT - - - - - - - b r
....-~'Vv-~:c--~..------- GND
Vz I
FEEDBACK _ _ _ _ _ _ _ _-...J L _ _ _ _ _ _ .J

EQUIVALENT SCHEMATIC DIAGRAM

ERROR AMPLIFIER
UNOER TES1 FUNCTION TABLE
VI

OUTPUT
CONTROL
INPUTS
STEERING
INPUT
OUTPUT FUNCTION II
Grounded Open Single-ended or parallel
VREF o----~
output
At Vref Open Normal push-pull operation
At Vref VI<O.4V PWM Output at 01
At Vref VI>O.4V PWM Output at 02
Figure 4. Error Amplifier Characteristics

OSCILLATOR FREQUENCY and

FREQUENCY VARIATION'
TIMING FlESI$TA,NCE
v.

"')c
Vee·,5V
T• • 25"C ..
AMPLIFIER VOLTAGE AMPLIFICATION

FREQUENCY

f-------" ..
f ... r-.. ~ 0,001 ~F r---- I'-.... Vee l,5V
'Yo -3Y -

'"'"
TA - 25-C
0.01 ~F

"'"
I 0.1 ~F 11l1~--
FREQ.
VARI
'\
~
• +,%

CT". I
'\
~
nil
I. ,. ffll
AT-TIMING RE5'STAHCE·11

1 Frequency variation Is the change In oscillator frequency that

occurs over the full temperature range.
100 1K
t-fFiEQUENCY-Hz
" I\.
'\
Figure 5. Oscillator Frequency and Frequency Variation 1 vs
Timing Resistance Figure 6. Amplifier Voltage Amplification vs Frequency

5-129
 XR-1468/1S68

Dual·Polarity Tracking Voltage Regulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-1468/1568 is a dual polarity tracking voltage
regulator, internally trimmed for symmetrical positive
and negative 15V outputs. Current output capability is
GND
100 mA, and may be increased by adding external pass
transistors. The device is intended for local "on-card"
BALANCE
regulation, which eliminates the distribution problems ADJUST
associated with single point regulation.
COMP.
The XR-1468CN and XR-1568N are guaranteed over
the O°C to 70°C commercial temperature range. The
XR-1568M is rated over the full military temperature SENSE.
range of - 55°C to + 125°C.
vO·

FEATURES N.C. N.C.

Internally Set for ± 15V Outputs vce VEE

± 100 mA Peak Output Current
Output Voltages Balanced Within 1 % (XR-1568)
0.06% Line and Load Regulation
Low Stand-By Current
Output Externally Adjustable from ± 8 to ± 20 Volts
Externally Adjustable Current Limiting
Remote Sensing

ORDERING INFORMATION
APPLICATIONS Part Number Temperature Output Offset Package
Main Regulation in Small Instruments XR-1568M -55°C to + 125°C ± 150 mV max Ceramic
On-Card Regulation in Analog and Digital Systems XR-1568N O°C to + 70°C ± 150 mV max Ceramic
Point-of-Load Precision Regulation XR-1468CN O°C to + 70°C ±300 mV maxCeramlc

ABSOLUTE MAXIMUM RATINGS SYSTEM DESCRIPTION

Power Supply ±30 Volts The XR-1468/1568 is a dual polarity tracking voltage
Minimum Short-Circuit Resistance 4.0 Ohms regulator combining two separate regulators with a
Load Current, Peak ± 100 mA common reference element in a single monolithic cir-
Power Dissipation cuit, thus providing a very close balance between the
Ceramic (N) Package 1.0 Watt positive and negative output voltages. Outputs are In-
Derate Above + 25°C 6.7 mW/oC ternally set to ± 15 Volts but can be externally adjusted
Operating Temperature between ± 8.0 to ± 20 Volts with a single control. The
XR-1568M - 55°C to + 125°C circuit features ± 100 mA output current, with exter-
XR-1568/XR-1468C O°C to + 70°C nally adjustable current limiting, and provision for re-
Storage Temperature - 65°C to + 150°C mote voltage sensing.

5·130
 ELECTRICAL CHARACTERISTICS
XR·1468/1568
Test conditions: (VCC = + 20V, VEE : - 20V, C1 = C2 = 1500 pF, C3 = C4 = 1,0 /LF, RSC + = RSC - = 4.00. IL +
= IL - = 0, TC = + 25°C unless otherwise noted.)

XR-1468C XR-1568
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS
Output Voltage 14.5 15 15.5 14.8 15 15.2 Vdc

Input Voltage - - 30 - - 30 Vdc

Input-Output Voltage Differential 2.0 - - 2.0 - - Vdc

Output Voltage Balance - ±50 ±300 - ±50 ±150 mV

Line Regulation Voltage mV

(Vin = 18V to 30V) - - 10 - - 10
(TL t to TH)tt - - 20 - - 20

Load Regulation Voltage mV

(IL = 0 to 50 mA, TJ = constant) - - 10 - - 10

(TA = TL to TH) - - 30 - - 30

Output Voltage Range 8.0 - 20 8.0 - 20 Vdc

Ripple Rejection (f = 120 Hz)

Output Voltage Temperature Stability

(TL to TH)

Short-Circuit Limit
(RSC = 10 ohms)

Output Noise Voltage

-

-
-
75

0.3

60
-

1.0

-
-

-
75

0.3

60
-

1.0

-
dB

mA

/LV(rms)
•
(BW = 10 Hz - 10 kHz) - 100 - - 100 -
Positive Standby Current mA
(Vin = +30V) - 2.4 4.0 - 2.4 4.0

Negative Standby Current mA

(Vin = -30V) - 1.0 3.0 - 1.0 3.0

Long-Term Stability - 0.2 - - 0.2 - %/kHr

tTL = O°C for XA-1468C/1568 ttTH = + 70°C for XR·1468C/1568 TJ = Junction Temp.
= - 55°C for XR·1568M + 125°C for XR-1568M TC = Case Temp.

INPUT 1010----0;-4 Vce VUI-';o----oINPIJT I-I

INI'U fI+1
ASC
. ~&
7
Vcc

Vo+
"n
Vo- '0
•
ASC-
INPU TI-I

4 SENSE SENSE "

1+1 1-1
,ooK 2 ,ooK
14 Vldl

<O""'l~ ]'.... ,-'

lI'ldj
OND

'5OOpF '500 pF

.
I.O.F
oVa C3
011 V..
+1'
C' rnc/ C2 t/Iould be ~1Id II cf4. 101M dwlct .. polllbit. A D.' /IF _Imlc ClplCitOf
mIY be requittd on tM Input Ii_II tile dna" located III Ippreci.bli dilt_1 from C3 I.O~F C41'~O~F
"" rectlf. filt .. ClPlCitOfL oVa -Va
C3 rnc/ C4 mIY belnclUllll to Improwe !old trllllltnt rISPOMI end to rlduc. th. output "":::
+IIIVd. -'IIVd.
noIII volt.... At low ternl*ltur. 01*1110". It mey be nee....,., to bypesl C4 with.
0.' IIF _ernie disc ClpKltor.
Figure 1. Basic 50 mA Regulator Figure 2. Voltage Adjust and Balance Adjust Circuit

5-131
 XR-1S24/2S24/3S24

Pulse-Width Modulating Regulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-1524 family of monolithic integrated circuits
contain all the control circuitry for a regulating power
supply inverter or switching regulator. Included in a 16-
pin dual-in-line package is the voltage reference, error-
amplifier, oscillator, pulse width modulator, pulse steer-
ing flip-flop, dual alternating output switches and cur-
rent limiting and shut-down circuitry. This device can be
used for switching regulators of either polarity, trans-
former coupled DC to DC converters, transformerless
voltage doublers and polarity converters, as well as
other power control applications. The XR-1524 is speci-
fied for operation over the full military temperature
range of - 55°C to + 125°C, while the XR-2524 and XR-
3524 are designed for commercial applications of O°C
to + 70°C.

FEATURES
Direct Replacement for SG-1524/2524/3524
Complete PWM power control circuitry
Single ended or push-pull outputs
Line and load regulation of 0.2%
1 % maximum temperature variation ORDERING INFORMATION
Total supply current less than 10 mA
Operation beyond 100 kHz Part Number Package Operating Temperature
XR-1524M Ceramic -55°C to + 125°C
XR-2524N Ceramic O°C to + 70°C
XR-2524P Plastic O°C to + 70°C
APPLICATIONS XR-3524N Ceramic O°C to + 70°C
XR-3524P Plastic O°C to + 70°C
Switching Regulators
Pulse-width Modulated Power Control Systems

ABSOLUTE MAXIMUM RATINGS SYSTEM DESCRIPTION

Input Voltage 40V The XR-1524/2524/3524 pulse width modulating regula-

Output Current (each output) 100 mA tor is a complete monolithic switching regulator. An in-
Reference Output Current 50 mA ternal 5V reference, capable of supplying up to 50 mA
Oscillator Charging Current 5 mA to external loads, provides an on board operating stan-
Power Dissipation dard. The oscillator frequency and duty cycle are ad-
Ceramic Packaqe 1000 mW justed by an external RC network. Regulation is con-
Derate above + 25°C 8 mW/oC trolled by an error amplifier which, combined with the
Plastic Package 625 mW/oC sense amplifier, also allows current limiting and remote
Derate above + 25°C 5 mW/oC shutdown functions. The outputs of the XR-1524/25241
Operating Temperature Range 3524 are two identical NPN transistors with both emit-
XR-1524 - 55°C to + 125°C ters and collectors uncommitted. Each output transis-
XR-2524/XR-3524 O°C to + 70°C tor has antisaturation circuitry for fast response and lo-
Storage Temperature Range -65°C to + 150°C cal current limiting set at 100 mAo

5-132
ELECTRICAL SPECIFICATIONS
XR·15/25/3524
Test Conditions: TA= - 55°C to + 125°C for the XR-1524 and O°C to + 70°C for the XR-2524 and XR-3524, VIN =
20V, and f = 20 kHz, unless specified otherwise.

XR-15241
XR-2524 XR-3524
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
REFERENCE SECTION
Output Voltage 4.8 5.0 5.2 4.6 5.0 5.4 V
Line Regulation 10 20 10 30 mV VIN = 8 to 40 Volts
Load Regulation 20 50 20 50 mV IL = 0 to 20 mA
Ripple Rejection 66 66 dB f = 120 Hz, TA = 25°C
Short Circuit Current Limit 100 100 mA VREF = 0, TA = 25°C
Temperature Stability 0.3 1 0.3 1 % Over Operating Temperature Range
Long Term Stability 20 20 mV/khr TA = 25°C
OSCILLATOR SECTION
Maximum Frequency 300 300 kHz CT = .001 ,.,.F, RT = 2 KO
Initial Accuracy 5 5 % RT and CT constant
Voltage Stability 1 1 % VIN = 8 to 40 Volts, TA = 25°C
Temperature Stability 2 2 % Over Operating Temperature Range
Output Amplitude 3.5 3.5 V Pin3, TA = 25°C
Output Pulse Width 0.5 0.5 ,.,.S CT = .01 mfd, TA = 25°C
ERROR AMPLIFIED SECTION

•
Input Offset Current 2 2 /-LA
Input Offset Voltage 0.5 5 2 10 mV VCM - 2.5 Volts
Input Bias Current 2 10 2 10 /-LA V CM = 2.5 Volts
Open Loop Voltage Gain 72 80 60 80 dB
Common Mode Voltage 1.8 3.4 1.8 3.4 V TA = 25°C
Common Mode Rejection Ratio 70 70 dB TA = 25°C
Small Signal Bandwidth 3 3 MHz AV - OdB, TA = 25°C
Output Voltage 0.5 3.8 0.5 3.8 V TA = 25°C
COMPARATOR SECTION
Duty Cycle 0 45 0 45 % % Each Output On
Input Threshold 1 1 V Zero Duty Cycle
Input Threshold 3.5 3.5 V Max. Duty Cycle
Input Bias Current 1 1 ,.,.A
CURRENT LIMITING SECTION Pin 9 = 2V with Error Amplifier
Sense Voltage 190 200 210 180 200 220 mV Set for Max. Out, TA = 25°C
Sense Voltage Temp. Coet. 0.2 0.2 mY/DC
Common Mode Voltage -1 +1 -1 +1 V
OUTPUT SECTION (Each Output)
Max. Collector-Emitter Voltage 40 40 V
Collector Leakage Current 0.1 50 0.1 50 JlA VCE = 40V
Saturation Voltage 1 2 1 2 V IC = 50 mA
Emitter Output Voltage 17 18 17 18 V VIN = 20V
Rise Time 0.2 0.2 ,.,.S RC = 2 KO, TA = 25°C
Fall Time 0.1 0.1 ,.,.S RC = 2 KO, TA = 25°C
TOTAL STANDBY CURRENT 8 10 8 10 mA VIN = 40V
(Excluding oscillator charging
current, error and current limit
dividers, and with outputs
open)

5-133
XR·15/25/3524 OPEN LOOP TEST CIRCUIT

2k

r-----------------------------------------------------~IW
L.--<';~-i 15 : ~ t----+-~:J OUTPUTS
3 XR-1524
11
16 14

V1N
8-40V

0.1

2k

DESCRIPTION OF CIRCUIT OPERATION

VOLTAGE REFERENCE SECTION
The internal voltage reference and regulator section
provides a 5-volt reference output at pin 16. This volt-
age also serves as a regulated voltage source for the
internal timing and control circuitry. This regulator may
be bypassed for operation from a fixed 5-volt supply by
connecting pins 15 and 16 together to the input voltage.
ILTOIOA
In this configuration, the maximum input voltage is 6.0 DEPENDING
volts. ON CHOICE
] FOR 01

This reference regulator may be used as a 5-volt source

for other circuitry. It will provide up to 50 mA of current
itself and can easily be expanded to higher currents Figure 2. Using the Internal Regulator as 5V Power Supply
with an external PNP as shown in Figure 2. for External Circuitry

+5V TO ALL
INTERNAL CIRCUITRY

C~

INV. INPUT 1

SENSE

9 COMPENSATION -:-
Ik
GROUND ~
(SUBSTRATE I B 10>--"'M.....-C
SHUT DOWN

Figure 1. Detailed System Block Diagram of XR-1524

5-134
 XRa~ 5/25/3524
OSCILLATOR SECTION 10

The oscillator section in the XR-1524 uses an external

resistor (RT) to establish a constant charging current in-
to an external capacitor (CT). While this uses more cur- ..,.V
rent than a series connected RC, it provides a linear
ramp voltage on the capacitor which is also used as a 2
V
reference for the comparator. The charging current is
equal to 3.6V -;- RT and should be kept within the range
of approximately 30 p,A to 2 mA, i.e., 1.8K < RT <
0
f-"""
V
~
100K.

The oscillator period is approximately T = RrCT where

5
- ~
T is in microseconds when RT = ohms and CT = 3

microfarads.
001 002 005 01 02 05
The use of Figure 3 allows the selection of RT and CT TIMING CAPACITOR VALUE (C T ' - MICROFARADS

for a wide range of operating frequencies. Note that for Figure 4. Output Stage Dead Time as a Function of the
series regulator applications, the two outputs can be Timing Capacitor Value
connected in parallel for an effective 0 - 90 % duty cy-
cle and the frequency of the oscillator is the frequency If it is desired to synchronize the XR-1524 to an external
of the output. For push-pull applications, the outputs clock, a pulse of ::::: + 3 volts may be applied to the os-
are separated and the flip-flop divides the frequency cillator output terminal with RrCT set slightly greater
such that each output's duty cycle is 0 - 45 % and the than the clock period. The same considerations of
overall frequency is 1/2 that of the oscillator.

•
pulse width apply. The impedance to ground at this
point is approximately 2K ohms.

If two or more XR-1524 circuits must be synchronized

together, one must be designated as master with its
~ 50 ~4---+-~~--~~~~~~~~~~
RrCT set for the correct period. The slaves should each
c::
;,; have an RrCT set for approximately 10% longer period
-.20 than the master with the added requirement that CT
c::
c::
(slave) = 1/2 CT (master). Then connecting pin 3 on all
~ 10 ~~--~~~-,~~~~~~~~--~~ units together will insure that the master output pulse -
which occurs first and has a wider pulse width - wil/ re-
~
~ 5 set the slave units.
~
;:

ERROR AMPLIFIER SECTION

The error amplifier is a simple differential-input, trans-
conductance amplifier. The output is the compensation
10 20 50 100 200 500 1 ms 2ms
terminal, pin 9, which is a high-impedance node (RL :::::
OSCILLATOR PERIOD - MICROSECONDS
5 MO). The gain is
Figure 3. Oscillator Period as a Function of RT and CT
8 IC RL
The range of values for CT also has limits as the dis- AV = gm RL = ---::::: .002 RL
charge time of CT determines the pulse width of the os- 2kT
cillator output pulse. This pulse is used (among other
things) as a blanking pulse to both outputs to insure that and can easily be reduced from a nominal of 10,000 by
there is no possibility of having both outputs on simUlta- an external shunt resistance from pin 9 to ground, as
neously during transitions. This output dead time rela- shown in Figure 5.
tionship is shown in Figure 4. A pulse width below ap-
proximately 0.5 microseconds may allow false trigger- In addition to DC gain control, the compensation termi-
ing of one output by removing the blanking pulse prior nal is also the place for AC phase compensation. The
to the flip-flop's reaching a stable state. If small values frequency response curves of Figure 5 show the un-
of CT must be used, the pulse width may still be ex- compensated amplifier with a single pole at approxi-
panded by adding a shunt capacitance (::::: 100 pF) to mately 200 Hz and a unity gain cross-over at 5 MHz.
ground at the oscillator output. (Note: Although the os-
cil/ator output is a convenient oscilloscope sync input, Typically, most output filter designs will introduce one or
the cable and input capacitance may increase the more additional poles at a significantly lower frequency.
blanking pulse width slightly.) Obviously, the upper limit Therefore, the best stabilizing network is a series R-C
to the pulse width is determined by the maximum duty combination between pin 9 and ground which intro-
cycle acceptable. Practical values of CT fall between duces a zero to cancel one of the output filter poles. A
.001 and 0.1 p,F. good starting point is 50 KO plus .001 p,F.

5-135
XR·15/25/3524 POSITIVE
r--NY'-- OUTPUT
80 VOLTAGES

RL " '
~
60
HL 1 M~!
....... 5'
NEGATIVE
k~!
"- " -...........,.,..._ OUTPUT
AL 300
""""lIlIIII
'" VOlTAC,fS

'"
"C
GNO-+--4- GND
~
Z III lOOk!:
;t 40
<.? .....
~ RL 30 k!!
~
;
~
2.5V IR, • R.I A, A.
Vo · _ - - - - ·2.5kn
0 R, R•• R.
> 20
Figure 6. Error Amplifier Biasing Circuits. (Note: Change

10 100
Al'=' Rtsistlnce hom Pin 9 to ground

1K 10K lOOK
"
~
1M
~
10M
in Input Connections for Opposite Polarity
Outputs)
age to get 25 % duty cycle with the error amplifier sig-
naling maximum duty cycle.
FREOUENCY- HERTZ

Figure 5. Error Amplifier Frequency Response as a Function In addition to constant current limiting, pins 4 and 5
may also be used in transformer-coupled circuits to
of External Resistor, RL, at Pin 9
sense primary current and shorten an output pulse,
should transformer saturation occur. (Refer to Figure
One final point on the compensation terminal is that 15.) Another application is to ground pin 5 and use pin 4
this is also a convenient place to insert any program- as an additional shutdown terminal, i.e., the output will
ming signal which is to override the error amplifier. In- be off with pin 4 open and on when it is grounded. Fi-
ternal shutdown and current limit circuits are connect- nally, foldback current limiting can be provided with the
ed here, but any other circuit which can sink 200 p.A network of Figure 8. This circuit can reduce the short-
can pull this point to ground, thus shutting off both out-
puts.

While feedback is normally applied around the entire

regulator, the error amplifier can be used with conven-
tional operational amplifier feedback and is stable in ei-
ther the inverting or non-inverting mode. Regardless of
the connections, however, input common-mode limits
must be observed or output signal inversions may
result. For conventional regulator applications, the 5-
volt reference voltage must be divided down as shown
in Figure 6. The error amplifier may also be used in
fixed duty cycle applications by using the unit gain con-
figuration shown in the open loop test circuit. Figure 7. Current Limiting Circuitry of the XR·1524

CURRENT LIMITING CONTROLS circuit current (lSc) to approximately one-third the max-
imum available output current (lMAX).
The current limiting circuitry of the XR-1524 is shown in
Figure 7. OUTPUT CIRCUITS
By matching the base-emitter voltages of 01 and 02, The outputs of the XR-1524 are two identical NPN tran-
and assuming negligible voltage drop across R1, sistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry for
Threshold = VSE (01) + 11 R2 - VSE (02) = 11 R2 fast response, and current limiting set for a maximum
=200 mV output current of approximately 100 mA. The availability
of both collectors and emitters allows maximum versa-
Although this circuit provides a relatively small thresh- tility to enable driving either NPN or PNP external tran-
old with a negligible temperature coefficient, there are sistors.
some limitations to its use, the most important of which
is the ± 1 volt common mode range which requires
sensing in the ground line. Another factor to consider is
1...... ·-v
R,
' (TW ·Vo-RD
R,tR,

that the frequency compensation provided by R1C1

and 01 provides a roll-off pole at approximately 300
Hertz.
VIM -200",V
Since the gain of this circuit is relatively low, there is a
transition region as the current limit amplifier takes
over pulse width control from the error amplifier. For Figure 8. Foldback Current Limiting Can Be Used to Reduce
testing purposes, threshold is defined as the input volt- Power Dissipation Under Shorted Output Conditions

5-136
In considering the application of the XR-1524 to voltage
XR·15/25/3524
regulator circuitry, there are a multitude of output con-
figurations possible. In general, however, they fall into
three basic classifications:

1. Capacitor-diode coupled voltage multipliers

2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits

Examples of each category are shown in Figures 9, 10

and 11. In each case, the switches indicated can be ei- (a) Push-Pull
ther the output transistors in the XR-1524 or added ex-
ternal transistors according to the load current require-
ments.

.VIN - - - - - -.....

•
(b) Flyback

Figure 11. Push-Pull and Flyback Connections for

Transformer-Coupled Outputs

DEADBAND CONTROL
The XR-1524 pulse width modulating regulator provides
Figure 9. Capacitor-Diode Coupled Voltage Multiplier Output two outputs which alternate in turning on for push-pull
Stages. (Note: Diode 01 is Necessary to inverter applications. The internal oscillator sends a
Prevent Reverse Emitter-Base Breakdown of momentary blanking pulse to both outputs at the end of
Transistor Switch S,A) each period to provide a deadband so that there cannot
SAlsa be a condition when both outputs are on at the same
'V'N--cr"'" •
'TYT" 'V o time. The amount of deadband is determined by the

± !
width of the blanking pulse appearing on pin 3 and can
V'N -- Va
be controlled by anyone of the four techniques de-
scribed below:

Method 1: For 0.2 to 2.0 microseconds, the deadband

is controlled by the timing capacitor, CT, on
pin 7. The relationship between CT and
'V'N~ C ~I 'V o deadband is shown in Figure 4. Of course,

SASS
I V'N' Va
since CT also helps determine the operating
frequency, the range of control is somewhat
I I limited.

Method 2: For 0.5 to 5.0 microseconds, the blanking

pulse may be extended by adding a small
capacitor from pin 3 to ground. The value of
'VIN~' I~

~
Vo
SA 58 the capacitor must be less than 1000 pF or
triggering will become unreliable.

f IV1NI<iVol

Figure 10. Single-ended Inductor Circuits Where the Two

Method 3: For longer and more well-controlled blanking
pulses, a simple one-shot latch similar to the
Outputs of the XR-1524 are Connected in Parallel circuit shown in Figure 12 should be used.

5-137
XR·15/25/3524
APPLICATIONS INFORMATION

10k POLARITY CONVERTING REGULATOR

The XR-1524 pulse width modulating regulator can be
interconnected as shown in Figure 14. The component
values shown in the figure are chosen to generate a -5
10k volt regulated supply voltage from a + 15 volt input.
This circuit is useful for an output current of up to 20
mA with no additional boost transistors required. Since
the output transistors are current limited, no additional
protection is necessary. Also, the lack of an inductor al-
lows the circuit to be stabilized with only the output ca-
pacitor.

Figure 12. Recommended External Circuitry for Long FLYBACK CONVERTER

Duration Blanking Pulse Generation (Method 3 of
Deadband Control. Note: For 5 p.sec blanking, Figure 15 shows the application of XR-1524 in a low-
choose Ca = 200 pF, Ra = 10 KO) current DC-DC converter, using the flyback converter
principle (see Figure 11 b). The particular values given
When this circuit is triggered by the oscilla-
in the figure are chosen to generate ± 15 volts at 20
tor output pulse, it will latch for a period de-
mA from a + 5 volt regulated line. The reference gener-
termined by CeRe providing a well-defined
ator in the XR-1524 is unused. The reference is provid-
deadband.
ed by the input voltage. Current limiting in a flyback
Another use for this circuit is as a buffer converter is difficult and is accomplished here by sens-
when several other circuits are to be syn- ing current in the primary line and resetting a soft-start
chronized to one master oscillator. This one- circuit.
shot latch will provide an adequate signal to
insure that all the slave circuits are com-
pletely reset before allowing the next timing
period to begin. SINGLE ENDED REGULATOR

Note that with this circuit, the blanking pulse The XR-1524 operates as an efficient single-ended
holds off the oscillator so its width must be pulse width modulating regulator, using the circuit con-
subtracted from the overall period when se- nection shown in Figure 16. In this configuration, the
lecting RT and CT two output transistors of the circuit are connected in
parallel by shorting pins (12, 13) and (11, 14) together,
Method 4: Another way of providing greater deadband respectively, to provide for effective 0 - 90% duty-cycle
is just to limit the maximum pulse width. modulation. The use of an output inductance requires
This can be done by using a clamp to limit an R-C phase compensation on pin 9, as shown in the
the output voltage from the error amplifier. A figure.
simple way of achieving this clamp is with
the circuit shown in Figure 13.

This circuit will limit the error amplifier's volt-

age range since its current source output
'15V
will only supply 200 p.A. Additionally, this cir-
cuit will not affect the operating frequency.

VREf~~-----------
2K -&V
20mA
IN916
01

Compo ®~---I~H-I-"'. 5k

Gnd 8 GND GND

Figure 13. Using a Clamp Diode to Control Deadband Figure 14. Circuit Connection for Polarity Converting
(Method 4 of Deadband Control) Regulator (Vln = + 15V, Vout = - 5V)
5-138
PUSH-PULL CONVERTER
XR·15/25/3524
.28V
The circuit of Figure 17 shows the use of XR-1524 in a
5<
transformer-coupled DC-DC converter with push-pull
outputs (see Figure 11 a). Note that the oscillator must 5<

be set at twice the desired output frequency as the XR-

1524's internal flip-flop divides the frequency by 2 as it t-i .....+--t V REF
...--.,;;..3<_oo4 RT
switches the PW.M. signal from one output to the other.
07
Current limiting is done in the primary. This causes the Cl·J-------+--..
pulse/width to be reduced automatically if the trans-
former saturation occurs.
CV ' t--------.
COMP
GND 001

50~

RETURN
GND

Figure 16. Conventional Single-Ended Regulator Connection

(Vin = + 28V, Vo = + 5V, lout :s 1 Amp)

V RH CB
5V

•
AT
'4
E.

CT Cl

C rER()X CUBE
v n13P-A2~

38'

Figure 15. A Low-Current DC-DC Converter Using Flyback

Principle (Vout = ± 15V, Vin = + 5V, IL :s 20 Figure 17. A High-Current DC-DC Converter with Push-Pull
rnA) Outputs (Vin = + 28V, Vo = + 5V, 10 :s 5A)

5-139
 XR·1525A/2525A/3525A
XR·1527 A/2527 A/3527 A

Pulse-Width Modulating Regulators

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-1525A11527 A is a series of monolithic inte-
grated circuits that contain all of the control circuitry INV
necessary for a pulse-width modulating regulator. In- INPUT
cluded in the 16-Pin dual-in-line package is a voltage
NON·Ir-;V
reference, an error amplifier, a pulse-width modulator, INPUT
an oscillator, under-voltage lockout, soft-start circuitry,
and output drivers. SYNC

The XR-1525A12525A13525A series features NOR logic, OSCILLATOR

OUTPUT
giving a LOW output for an OFF state. The XR-1527 AI
2525A13527A series features OR logic, giving a HIGH CT
output for an OFF state.
RT
FEATURES
DISCHARGE
8V to 35V Operation
5.1 V Reference Trimmed to ± 1 % SOFT·START
100 Hz to 500 kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft-Start ORDERING INFORMATION
Input Under-voltage Lockout
Latching PWM to Prevent Double Pulsing Part Number Package Operating Temperature
Dual Source/Sink Output Drivers XR-1525A127M Ceramic -55°C to +125°C
Capable of Over 200 mA XR-2525A127 AN Ceramic - 25°C to + 85°C
Power·FET Drive Capability XR-2525A127 AP Plastic - 25°C to + 85°C
XR-3525A127CN Ceramic O°C to + 70°C
APPLICATIONS XR-3525A127CP Plastic O°C to + 70°C

Power Control Systems

Switching Regulators SYSTEM DESCRIPTION
Industrial Controls
The on-chip 5.1-volt reference is trimmed to ± 1 % ini-
tial accuracy, and the common-mode input range of the
ABSOLUTE MAXIMUM RATINGS error amplifier is extended to include the reference
voltage. Deadtime is adjustable with a single external
Supply Voltage (+ VIN) +40V resistor. A sync input to the oscillator allows multiple
Collector Supply Voltage (Vc) +40V units to be slaved together, or a single unit to be syn-
Logic Inputs - 0.3V to 5.5V chronized to an external clock. A positive-going signal
Analog Inputs - 0.3V to + VIN applied to the shutdoown pin provides instantaneous
Output Current, Source or Sink 500 mA turnoff of the outputs. The under-voltage lockout cir-
Reference Output Current 50 mA cuitry keeps the output drivers off, and the soft-start ca-
Oscillator Charging Current 5 mA pacitor discharged, for an input voltage below the re-
Power Dissipation quired value. The latch on the PWM comparator in-
Ceramic Package 1000 mW sures the outputs are active only once per oscillator
Derate above TA = + 25°C 8.0 mW/oC period, thereby eliminating any double pulsing. The
Plastic Package 625 mW latch is reset with each clock pulse.
Derate above TA = + 25°C 5.0 mW/oC
Operating Junction Temperature (TJ) + 150°C The output drivers are totem-pole designs capable of
Storage Temperature Range - 65°C to + 150°C sinking and sourcing over 200 mA.

5-140
 XR·1527 A/2527 A/3527 A
XR·1525A/2525A/3525A
ELECTRICAL CHARACTERISTICS
Test Conditions: VIN = + 20V, TJ = Full operating temperature range, unless otherwise specified.
XR-1525A12525A XR-3525A
XR-1527 Al2527A XR-3527A
PARAMETERS MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
VOLTAGE REFERENCE SECTION
Output Voltage 5.05 5.10 5.15 5.00 5.10 5.20 V TJ = 25°C
Line Regulation 10 20 10 20 mV VIN = BV to 35V
Load Regulation 20 50 20 50 mV IL = 0 to 20 mA
Temperature Stability (2) 20 50 20 50 mV TJ = Full Operating Range
Total Output Variation (2) 5.00 5.20 4.95 5.25 V Line, Load and Temperature
Output Short Circuit BO 100 BO 100 mA TJ = 25°C, Vref = OV
Current
Output Noise Voltage (2) 40 200 40 200 J.LV rms TJ = 25°C, 10 Hz s f s 10 kHz
Long Term Stability (2) 20 50 20 50 mV/kHR TJ = 125°C
OSCILLATOR SECTION (Note 3)
Initial Accuracy (2,3) ±2 ±6 ±2 ±6 % TJ = 25°C, f = 40 kHz
Temperature Stability (2) ±3 ±6 ±3 ±6 % TJ = Full Operating Range
Input Voltage Stability (2,3) ±0.3 ±1 ±1 ±2 % VIN = BV to 35V
Minimum Frequency 100 100 Hz RT = 150 kO, Cr = 0.1 J.LF
Maximum Frequency 400 400 kHz RT = 2 kO, CT = 1 nF
Current Mirror 1.7 2.0 2.2 1.7 2.0 2.2 mA IRT = 2 mA
Clock Amplitude (2,3) 3.0 3.5 3.0 3.5 V
Clock Pulse Width (2,3) 0.3 0.5 1.0 0.3 0.5 1.0 J.Lsec TJ = 25°C, RD = 00
Sync Threshold 1.2 2.0 2.B 1.2 2.0 2.B V
Sync Input Current 1.0 2.5 1.0 2.5 mA Sync Voltage = 3.5V
ERROR AMPLIFIER SECTION (VCM = 5.1V)
Input Offset Voltage 0.5 5.0 2 10 mV
Input Bias Current 1 10 1 10 J.LA
Input Offset Current 1 1 J.LA
DC Open·Loop Gain 60 75 60 75 dB RL ~ 10 MO
Gain Bandwidth Product (2) 1 2 1 2 MHz TJ = 25°C
Output Low Voltage 0.2 0.5 0.2 0.5 V
Output High Voltage 3.B 5.6 3.B 5.6 V
Common·Mode Rejection 60 75 60 75 dB VCM = 1.5V to 5.2V
Ratio
Supply Voltage Rejection 50 60 50 60 dB VIN = BV to 35V
Ratio
PULSE-WIDTH MODULATING COMPARATOR
Minimum Duty Cycle 0 0 %
Maximum Duty Cycle 45 49 45 49 %
Input Threshold (3) 0.6 0.9 0.6 0.9 V Zero Duty Cycle
Input Threshold (3) 3.3 3.6 3.3 3.6 V Maximum Duty Cycle
Input Bias Current (2) 0.05 1.0 0.05 1.0 J.LA
SOFT-START SECTION
Soft-Start Current 25 50 BO 25 50 BO J.LA Vshutdown = OV
Soft-Start Voltage 0.4 0.6 0.4 0.6 V Vshutdown = 2V
Shutdown Input Current 0.4 1.0 0.4 1.0 mA Vshutdown = 2.5V
OUTPUT DRIVERS (Each Output) Vc = 20V
Output Low Voltage 0.2 0.4 0.2 0.4 V Isink = 20 mA
Output Low Voltage 1.0 2.0 1.0 2.0 V Isink = 100 mA
Output High Voltage 1B 19 1B 19 V Isource = 20 mA
Output High Voltage 17 1B 17 1B V Isource = 100 mA
Under-voltage Lockout 6 7 B 6 7 B V Vcomp and VSS = High
Collector Leakage (4) 200 200 J.LA Vc = 35V
Rise Time (2) 100 600 100 600 nsec TJ = 25°C, CL = 1 nF
Fall Time (2) 50 300 50 300 nsec TJ = 25°C, CL = 1 nF
Shutdown Delay (2) 0.2 0.5 0.2 0.5 J.Lsec VSD = 3V, Cs = 0, TJ = 25°C
TOTAL STANDBY CURRENT
Supply Current 14 20 14 20 mA VIN = 35V
Note 2: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 3: Tested at f = 40 kHz (RT = 3.6 kO, CT = 0.01 J.LF, RD = 00).
Note 4: Applies to XR-1525A12525A13525A only, due to polarity of output pulses.
5-141
XR·1525A/2525A/3525A
XR·1527 A/2527 A/3527 A
PRINCIPLES OF OPERATION Error Amplifier

The different control blocks within the XR-1525AJ1527 A The error amplifier of the XR-1525AJ1527 A is a differen-
function as follows: tial input transconductance amplifier. Its common-
mode range covers the reference voltage. Its open-loop
Voltage Reference Section gain, typically 75 dB, can be reduced by a load resistor
on Pin 9. To ensure proper operation, the output load
The internal voltage reference circuit of the XR-1525AJ should be limited to 50 kO or greater. An equivalent cir-
1527 A is based on the well-known "band-gap" refer- cuit schematic of the error amplifier is shown in Figure 9.
ence, with a nominal output voltage of 5.1 volts, inter-
nally trimmed to ± 1 % accuracy. It is short circuit pro- Soft-Start Circuitry
tected and is capable of providing up to 20 mA of
reference current. A simplified circuit schematic is The soft-start fun'ction is provided to achieve controlled
shown in Figure 7. turn-on of the pulse-width modulator. When power is
applied to the device, the external capacitor, Csoft-
Oscillator Section start, on Pin 8 is charged by a 50 IlA constant current
source. The ramp voltage appearing on this capacitor
The sawtooth oscillator derives its frequency from an is fed into the pulse-width modulator, which gradually
external timing resistor/capacitor pair. The timing resis- increases its output duty cycle from zero to the pre-
tor, RT, determines the charging current into the timing scribed value. When the shutdown terminal is raised to
capacitor, Cr. The magnitude of this current is approxi- a positive value, an internal transistor turns ON, and
mately given by: discharges the capacitor, CS, causing the PWM to turn
OFF. When the shutdown terminal is open or pulled low,
Vref - 2VBE 3.7V the transistor turns OFF, and Cs begins charging as be-
RT Rr fore. The turn-on time (time required to charge Cs to
+ 2.7 volts) can be approximated as:
where RT may range from 2 kO to 150 kO. In general,
temperature stability is maximized with lower values of
Rr. The current source charging CT creates a linear TC (msec) = 54 Cs
ramp voltage which is compared to fixed thresholds
within. When the capacitor voltage reaches + 3.3 volts,
the oscillator output (Pin 4) goes high, turning ON the where Cs is in IlF.
discharge transistor. The capacitor is discharged
through the deadtime resistor, RO. When the voltage on Output Section
CT falls to + 1.0 volt, the oscillator output goes low, the
discharge transistor is turned OFF, and the capacitor is The output drivers of the XR-1525AJ1527 A are totem-
charged through the constant current source as an- pole designs capable of sinking and sourcing 200 mA.
other cycle starts. With large values of RO (5000, maxi- The low source impedance in the high or low states pro-
mum), deadtime is increased. The actual operating fre- vides ideal interfaCing with bipolar as well as FET
quency is thus a function of the charge and discharge power transistors. Either push-pull or single-ended out-
times. Figure 2 shows how charge time is related to RT put configurations are possible with separate collector
and Cr, with RO = 00. Oeadtime is a function of RO supply terminals. The equivalent schematic of the out-
and Cr, and can vary between 0.5 to 7 Ilsec, with RO = put drivers is shown in Figure 10.
00, as shown in Figure 3. The equivalent circuit sche-
matic of the oscillator section is shown in Figure 8. RECOMMENDED OPERATING CONDITIONS
A unit can be synchronized to an external source by se- Note 1: Range over which the device is functional
lecting its free-running oscillator period to be 10% and parameter limits are guaranteed.
longer than the period of the external source. A Collector Supply Voltage (Vc) + 4.5V to + 35V
positive-going pulse of at least 300 nsec wide should be Sink/Source Load Current
applied to the sync terminal for reliable triggering; how- (Steady State) o to 100 mA
ever, it should not exceed the free-running pulse width Sink/Source Load Current (Peak) o to 400 mA
by more than 200 nsec. The amplifier of the pulse Reference Load Current o to 20 mA
should be kept between 2 and 5 volts. Multiple units Oscillator Frequency Range 100 Hz to 400 kHz
can be synchronized to each other by connecting all CT Oscillator Timing Resistor 2 kO to 150 kO
pins, and oscillator output pins together; RT pins and Oscillator Timing Capacitor 0.001 IlF to 0.1 IlF
discharge pins on slave oscillators must be left open. Oeadtime Resistor Range o to 5000

5-142
 XR·1525A/2525A/3525A
EQUIVALENT SCHEMATIC DIAGRAM XR·1527 A/2527 A/3527 A
r XR·1S25A OUTPUT STAGE

GROllND GI------·----...
SYNC [2]1----------,
RT~I--------~--~~
1-----1>----4
CT[J-----~--4---~~
OUTPUT B

DISCHARGE

Vc 13

INV. INPUT QI-------t

NON INV. INPUT

SOFT START

SHUTDOWN
@--.
0-------------.....---'
5K
r------4------------------~
10 1 - - - - ' \ I \ I \ r - - - -.....- - - I

52 K
'icC~.
-
-t:
:::r
.
-t'l

)--8
OUTPUT A

--~---
OUTPUT B
•
I ~
I -=
XR-1527A OUTPUT STAGE
L ..J

CT (51

200

100

50

~
w.
OUTPUT A (II) 20
7

OUTPUT B (14) J u u L
10
RT
Cr RO

-= I
XR·1S2SA oL-~~~~L--L~~_~_L~_~~ _ _~
1 2 5 10 20 50 100200 5001 ms 2m,5m,10ms
OUTPUT A (II)
CHARGE TIME (",ecl

OUTPUT B (14)l
L-.
n
_.....J L-_.....J "--_---'
n r
Figure 1: Typical Waveforms-XR-1525A/1527A Figure 2. Oscillator Charge Time vs RT and CT

5-143
XR·1525A/2525A/3525A
XR·1527 A/2527 A/3527 A
500

80 I----~-__

-
a:
0
400
60
I
a:
0
~ ~

~I9CP
en 300 ;; 40
~
a: :c
u
UJ UJ
:E
;::
0 200 ~ 20
~ o
> RZ
0

100

10 100 I K 10 K 100 KIM 10 M

FREOUENCY (Hz)
10 20 so 100 200
DISCHARGE TIME ("sec)

Figure 3. Oscillator Discharge Time vs RD and CT Figure 4. Error Amplifier Open-Loop Frequency Response.

§
so
5 3
~
UJ l
U ~ 40

~ o
>
o
§? 2
~ 30
z :l
o o
;::
c 20
~ 1~----------­
C
en
10

.02 .03 .04.05 .07 .10 .2.3.4 .5 .7 I A

OUTPUT CURRENT. SOURCE OR SINK (AMPS) ERROR VOLTAGE (VOLTS)

Figure 5. Output Saturation Characteristics Figure 6. Output Duty Cycle vs Error Voltage
V~~. ________________~____~________~_ __ _

TO
OuTPUTS

... A. A,

F"OM FAOM
SHUTDOWN OSC

Figure 7. Equivalent Schematic of Voltage Reference Section

5-144
 XR·1525A/2525A/3525A
XR·1527 A/2527 A/3527 A

RT 6~----~~----~r

CT 5~--------------~~--------~~

Rg
.-------------------~VVV~OSC

SYNC J
r-----.--------G DISC

R3

Figure 8. Equivalent Schematic of the Oscillator Section

RS

•
Vc

V,N 0--_--------,
COMP
RS

{ill
l
t4
OUTPUT

-IN

10 K

F/F OSC PWM 04 OMITTED

IN XR-I527A

Figure 9. Equivalent Schematic of Error Amplifier Section Figure 10. Equivalent Schematic of Output Drivers

5-145
 XR·1525A/2525A/3525A
XR·1527 A/2527 A/3527 A
+VSUPPl Y 0 - -.......- - - - , .
+VSUPPLY 0------_-----,.

OPEN
13

XR·1527A
XR·'525A

12

12

Figure 11. Single-Ended Output for XR-1525A Figure 12. Single-Ended Output for XR-1527A

+VSUPPLyQ----.------------,

+VSUPPLY 0--_--------..,

T\,\(O OUTPUT
RECTIFIERS
Tl( TO OUTPUT
RECTIFIERS

1 - - - _.......
AND FILTERS
II AND FILTERS

Figure 13. Push-Pull Outputs with XR-1525A Figure 14. Power FET Push-Pull Outputs with XR-1525A
YC (DC)

I.SK

O~TSp~T
SYNC

0- - - - f - - - - - - - - - - - - - t
r"
OUTPUT
A

Figure 15. Generalized Test Circuit

5-146
 XR-15/25/3543

Power Supply Output Supervisory Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-1543/2543/3543 are monolithic integrated cir-
cuits that contain all the functions necessary to monitor
and control the output of a power supply system. In- seR TRIGGER
cluded in the 16-Pin dual-in-line package is a voltage
reference, an operational amplifier, voltage compara- REMOTE
ACTIVAlE
tors, and a high-current SCR trigger circuit. The func-
tions performed by this device include over-voltage RESET GROUND
senSing, under-voltage sensing and current limiting,
with provisions for triggering an external SCR "crow- OVER·VOLTAGE
INDICATE
CL
OUTPUT
bar."
OIlER·VOLTAGE OFFSET\
DELAY COMPENSATION
The internal voltage reference on the XR-1543 is guar-
anteed for an accuracy of ± 1 % to eliminate the need OVER·VOLTAGE CL NI
It-;PUT INPUT
for external potentiometers. The entire circuit may be
powered from either the output that is being monitored UNDER·VOLTAGE CL INV
INPUT INPUT
or from a separate bias voltage.

•
UNDER·VOLTAGE UNDER-VOLTAGE
DELAY INDICATE
FEATURES
Over-Voltage Sensing Capability
Under-Voltage Sensing Capability
Current Limiting Capability ORDERING INFORMATION
Reference Voltage Trimmed ± 1%
SCR "Crowbar" Drive 300 mA Part Number Package Operating Temperature
Programmable Time Delays XR-1543M Ceramic - 55°C to + 125°C
Open Collector Outputs XR-2543N Ceramic -25°C to +85°C
and Remote Activation Capability XR-3543N Ceramic O°C to + 70°C
Total Standby current Less than 10 mA XR-3543P Plastic O°C to + 70°C

APPLICATIONS SYSTEM DESCRIPTION

DC/DC Converters An output supervisory cir~uit, such as the XR-1543, is
Switch Mode Power Supplies used to control and monitor the performance of a
Power Line Monitors power supply. In many systems, it is crucial that the
Linear Power Supplies supply voltage is always within some minimum and
maximum level, to guarantee proper performance, and
ABSOLUTE MAXIMUM RATINGS to prevent damage to the system. If the supply voltage
is out of tolerance, it is often desirable to shut down the
Input Supply Voltage, VIN 40V system or to have some form of indication to the opera-
Sense Inputs VIN tor or system controller. As well as protecting the sys-
SCR Trigger Current (Note 1) 300 mA tem, the power supply sometimes needs to be protect-
Indicator Output Voltage 40V ed under short circuit and current overload situations.
Indicator Output Sink Current 50 mA By providing an SCR "crowbar" on the output of a
Power Dissipation (Ceramic) 1000 mW power supply, it can be shut off under certain fault con-
Derate Above TA = + 25°C 8 mW/oC ditions as well.
Power Dissipation (Plastic) 625 mW
Derate Above TA = + 25°C 5 mW/oC The over-voltage sensing circuit (O.V.) can be used to
Operating Junction Temperature (TJ) + 150°C monitor the output of a power supply and provide trig-
Storage Temperature Range -65°C to + 150°C gering of an SCR, when lhe output goes above the pre-
scribed voltage level. The under-voltage sensing circuit
Note 1: At higher input voltages, a dissipation limiting (U.v.) can be used to monitor either the output of a
resistor, RG, is required. power supply or the input line voltage.

5-147
XR·15/25/3543
ELECTRICAL CHARACTERISTICS
Test Conditions: V,N = 10V, TA = full operating temperature range, unless otherwise specified. Refer to Figure 9 for component
designation.

XR-154312543 XR-3543

PARAMETERS MIN TYP MAX MIN TYP MAX UNIT CONDITIONS

Input Voltage Range 4.5 40 4.5 40 V TA = 25°C to max
Input Voltage Range 4.7 40 4.7 40 V TA = min to max
Supply Current 7 10 7 10 mA TA = 25°C, Y,N = 40V
REFERENCE VOLTAGE SECTION (Pins 15 and 16)
Output Voltage 2.48 2.50 2.52 2.45 2.50 2.55 V TA = 25°C
Output Voltage 2.45 2.55 2.40 2.60 V TA = min to max
Line Regulation 1 5 1 5 mV VIN = 5 to 30V
Load Regulation 1 10 1 10 mV Iref = 0 to 10 mA
Short Circuit Current 15 15 mA Vref = OV
Temperature Stability 50 50 ppm/DC

SCR TRIGGER SECTION (Pins 1, 2, and 3)

Peak Output Current 100 200 400 100 200 400 mA VIN = 5V, RG = on,
Vo = 0
Peak Output Voltage 12 13 12 13 V VIN = 15V, 10 = 100 mA
Output OFF Voltage 0 0.1 0 0.1 V Y,N = 40V
Remote Activate Current 0.4 0.8 0.4 0.8 mA Pin 2 = GND
Remote Activate Voltage 2 6 2 6 V Pin 2 = Open
Reset Current 0.4 0.8 0.4 0.8 mA Pin 2 = GND,
Pin 3 = GND
Reset Voltage 2 6 2 6 V Pin 2 = GND,
Pin 3 = Open
Output Current Slew Rate 400 400 mAlp,s TJ = 25°C, RL = 50n,
CD = 0
Propagation Delay Time 300 300 nsec TJ = 25°C, RL = 50n
(From Pin 2) CD = 0, Pin 2 = O.4V
Propagation Delay Time 500 500 nsec TJ = 25°C, RL = 50n,
(From Pin 6) CD = 0, Pin 6 = 2.7V
COMPARATOR SECTIONS (Pins 4, 5, 6, 7, 8, and 9)
Input Threshold
(Input Voltage Rising 2.45 2.50 2.55 2.40 2.50 2.60 V TJ = min to max
on Pin 6 and
Falling on Pin 7) 2.40 2.60 2.35 2.65 V TJ == 25°C
Input Hysteresis 25 25 mV
Input Bias Current 0.3 1.0 0.3 1.0 p,A Sense input = OV
Delay Saturation 0.2 0.5 0.2 0.5 V
Delay High Level 6 7 6 7 V
Delay Charging Current 200 250 300 200 250 300 p,A VD = OV
Indicate Saturation Voltage 0.2 0.5 0.2 0.5 V 'L == 10 mA
Indicate Leakage Current 0.01 1.0 0.01 1.0 p,A Vout = 40V
Propagation Delay Time 400 400 nsec CD = 0 Pin 6 = 2.7V
Pin 7 == 2.3V
Propagation Delay Time 10 10 msec CD = 1 p,F TJ = 25°C
CURRENT LIMIT AMPLIFIER SECTION (Pins 10, 11, 12, and 13)
Input Voltage Range 0 VIN-3V 0 VIN-3V V
Input Bias Current 0.3 1.0 0.3 1.0 p,A Pin 12 = Open, VCM = OV
Input Offset Voltage 0 10 0 15 mV Pin 12 = Open, VCM == OV
Input Offset Voltage 80 100 120 70 100 130 mV Pin 12 = 10 kO to GND
Common Mode 60 70 60 70 dB VIN = 15V, Os
VCM s 12V
Rejection Ratio
Open Loop Gain 72 80 72 80 dB VCM == OV, Pin 12 = Open
Output Saturation Voltage 0.2 0.5 0.2 0.5 V 'L == 10 mA
Output Leakage Current 0.01 1.0 0.01 1.0 p,A Vout = 40V
Small Signal Bandwidth 5 5 MHz TJ == 25°C, Av == 0 dB
Propagation Delay Time 200 200 nsec TJ == 25°C,
Voverdrive = 100 mV

5-148
 XR·15/25/3543
V,N -10V
200 80 k::::~---+-----i--- RL - 2 Kil
>-
!.
.... leo 'r-... I'... VIJ .JOV
RL" 2KO -r-
TJ -2S'C

"~
C 70
50 "-
0
>
30
f'
90

r~
X 20 "-
In
....
tr
10
V ...........
"-~
i!: II +
~
7
~d'2 "-
> 5
1T.~. "
2
I K
l"=l
3K 7K 20 K 50 K 0.1101 0.3101
" 1M lK 10K lOOK 1M 5101
2K 5K 10K 30K 70K 0.2101 0.5101 FREOUENCY (HERTZ)
Itr. THRESHOLD SETTING RESISTOR (OIlA.SI

Figure 1. Typical Current Threshold (VTH) vs. Threshold Setting Figure 2. Current Limiting Amplifier-Frequency Response
Resistor (RT)

RT" 00
80
V,N .. 10V
g

•
iii' Itr .100 KO RL '"' 2 KO LJ.voLAL ulJvoLAL
~
i!
a
c 70
TJ" 25'C
;8
0 INPUT
J.
IHPUT

....
a
RT .. 3OKO
"~c
~ 0
-' RT-'0KO >
~80 ~ 3
II.
8-' ~
0
z.... >-
II.
0
50
a
dO ~
..
40
100 lK 10K lOOK 1M 2.48 2.41 2.50 2.50 2.52 2.54
FREQUENCY (HERTZ) SENSE INPUT VOLTAGE (VOLTS)

Figure 3. Current Limiting Amplifier Gain vs. Threshold Figure 4. Over-Voltage and Under-Voltage Comparator
Setting Resistor (RT Hysteresis

iii 1.0
a DELAY .. 2.!iC RECOMMENDED SERIES GATE RESISTANCE. RG
c '0 FOR USE WITH HIGHER SUPPLY VOLTAGES
cz:
...0
c I I
/
cz: 0.1 - RG;o VI~.;5 0
U
!. V
1&1
U
z
C 0.01 lL
t:
u
C V
ilL
C
U
>-
0.001
/
~
1&1 V
a
0.0001 ./
0.001 0.01 0.1 1.0 10 10 15 20 25 30 35 40
DELAY TIME (MILLISECONDS) YIN SUPPLY VOLTAGE (YOLTS)

Figure 5. Comparator Activation Delay vs. Capacitor Value Figure 6. SCR Trigger-Series Gate Resistance (RG) vs.
Input Voltage

5-149
XR·15/25/3543
PRINCIPLES OF OPERATION input common mode range extending from ground to
approximately 3 volts below the positive supply. With a
The internal control blocks of the XR-1543 operate as 2 kO pull-up resistor, the open-loop voltage gain is 72
follows: dB minimum with a unity gain bandwidth beyond 5
MHz. The operational amplifier may be used as a com-
Voltage Reference Section parator or, if linear amplification is required, external
compensation may be added for stable performance
The internal voltage reference circuit of the XR-1543 is over a wide frequency range.
based on the well-known "band-gap reference" with a
nominal output voltage of 2.50 volts, internally trimmed The input offset voltage of this amplifier is specified for
to give an accuracy of ± 1 % at 25°C. It is capable of 10 mV maximum; however, it may be programmed ex-
providing a stable output voltage over a wide input volt- ternally for thresholds up to 200 mV. By connecting a
age range. Furthermore, its performance is guaranteed resistor, Rr. from Pin 12 to ground, the input threshold
for changes in line and load conditions. The accuracy voltage can be varied. For most current sensing appli-
of the output voltage is guaranteed to ± 2 % maximum cations, the required threshold polarity calls for a posi-
for the XR-1543/2543, and ± 4% maximum for the XR- tive voltage on the inverting input. Reducing the imped-
3543, over the entire operating temperature range. ance on Pin 12 also lowers the overall voltage gain of
the amplifier, which makes this pin a convenient point
The output of the reference circuit is capable of provid- to apply frequency compensation. This can be accom-
ing up to 10 mA of current for use as a reference for ex- plished by either connecting C1 to the output, or C2 to
ternal circuitry. The primary function of this circuit is to ground as shown in Figure 8. The diode, D1, and the re-
provide a very accurate and stable reference input for sistor, RC, are used only if it is necessary to increase
the under-voltage and over-voltage comparators, there- the frequency response by operating the output at a
by enabling very precise monitoring of line and output higher current and/or isolating the load from RC and
voltages without potentiometers. C1, when the amplifier is off.
Comparator Section
The under-voltage and over-voltage sensing compara- SCR Trigger Section
tors of the XR-1543 are identical except for the input po-
larities. Each section is made up of two comparators in The SCR trigger sectionof the XR-1543 is connected to
the output of the over-VOltage comparator and is capa-
series whose inputs are referenced to 2.50 volts. The
ble of handling 300 mA. The circuit also provides for re-
delay terminal between the comparators requires an
mote activation of the output as well as a reset termi-
external capacitor to ground for programmable time de-
lays on the output. nal. When an over-voltage situation occurs, the output
of the sensing comparator goes low, turning "on" the
When an out-of-tolerance situation occurs, the first over-voltage indicate transistor. At the same time, the
comparator activates a current source which then comparator drives an npn Darlington pair which pro-
charges the external capacitor at a constant rate. This vides 300 mA to activate an external SCR crowbar.
ramp voltage is then compared to the reference voltage
by the second comparator which activates the output A remote activation circuit is included to allow the user
indicating circuit. With no external capacitor, the overall to activate the SCR crowbar in other than an over-
time delay from sense input to output is approximately voltage situation. When this terminal, Pin 2, is ground-
0.5 Itsec. The charging current for the capacitor, CD, is ed, it forces the output of the comparator low which ac-
approximately 250 itA which results in the following re- tivates the output circuitry in the same manner as the
lationship: over-voltage comparator does.

Time delay = 10 CD (msec) Another function of this circuit is to provide the capabili-
ty to latch the O.v. indicate and SCR trigger outputs
where CD is in 1tF. "on", after a fault is sensed. This is done by connecting
the remote activate terminal (Pin 2) to the O.V. indicat-
The output npn transistors are capable of sinking 10 ing terminal (Pin 4). When an O.V. condition occurs, Pin
mA with saturation voltage of less than 0.4 volts. The 2 is pulled low, which in turn holds the outputs in the
outputs can be "wired OR'd" to provide a single output "on" condition until the reset terminal is externally
indicator. grounded, removing the latch and turning "off" the out-
puts. If the external connection is not made, the high
Current Sensing Amplifier current output will be activated only as long as a fault
condition exists. When the fault condition disappears,
The operational amplifier used in the XR-1543 is a high- the outputs will be disabled. The thresholds for both re-
gain, externally compensated amplifier with open col- mote activation and reset terminals are approximately
lector outputs. The pnp input stage provides for a wide 1.2 volts.

5-150
 XR·15/25/3543
EQUIVALENT SCHEMATIC DIAGRAM

•
seR
TRIGGER

U.V. 9 U.V.
SENSE INDICATE

SCR
TRIGGER

VIN
O.V.
INDICATE

INV.

N.I.

REMOTE
ACTIVATE 2
OFFSET/COMP (GROUND TO ACTIVATE)

GROUND EJr-------
1
Figure 7. XR·1543 Block Diagram

5-151
XR·15/25/3543
APPLICATIONS INFORMATION 2. C1 is determined by the loop dynamics.

A typical application of the XR-1543 is to monitor a sin- 3. Peak current to load,

gle power supply output voltage as shown in Figure 9.
In this circuit, both over- and under-voltage sensing and
current-limiting functions are performed. The circuit
shown is powered from an external bias capable of sup-
plying 10 mA in addition to the activation current for the 4. Short circuit current,
SCR trigger. With Pin 2 tied to Pin 4, a latch has been
provided such that when an over-voltage situation oc-
curs, the o.v. indicator and SCR trigger are activated ISC = VTH
and held until the reset terminal is externally grounded. RSC

In powering an SCR from supply voltages greater than 5 5. Low output voltage limit,
volts, an external resistor, RG, is required on Pin 1 to
limit the power dissipation for the XR-1543. Although
the XR-1543 is capable of handling 300 mA of current,
its power dissipation must be kept below the absolute
maximum ratings. 6. High output voltage limit,
In this circuit, current-limiting is performed by sensing
the voltage drop across the resistor, RSC, in the posi- Va (high) = 2.5(R4. + R5 + R6)
tive supply line. The threshold for the amplifier is exter- R6
nally set by the resistor, RT
7. Voltage sensing delay, TD = 10,000 CD
The values of the external components used in Figure 9 8. SCR trigger power limiting resistor,
are calculated as follows:
. . . t hresho Id , VTH == -
1. Current limiting 1000
- VIN -5
RG > ---
RT 0.2

TO CONTROL
LOOP

Figure 8. Current Limiting Amplifier Connections for

Threshold Control and Frequency Compensation

5-152
 XR·15/25/3543
YIN o-~t---~------------------------ .......--,
FROM RSC
POWER---1---~---......._VVV~--~--------------t_-~~----~­
SUPPLY

TO
SYST~M
CONTROL

TOYOLTAGE
CONTROL LOOP
RS

RT

Figure 9. Typical Connection for Linear Foldback Current Limiting as well as Over-Voltage and Under-Voltage Protection .

r-----------------.
I
I
I
I
I
I
XR·1543

I
I
I
I
I
I
•
I
I
I
I I
I I
~ II >------t--i IL _____ _
_-1
I

PIH7
INPUT

PIN8
DELAY _ _ _"

OU:~~~------------------------~Up-----------OFF

ON

Figure 10. XR-1543-lnput Line Monitor Circuit

5-153
XR·15/25/3543
MAIN SUPPl.Y
~--~------------------------------------------------------------~-.
BUS

VOl.T~~~ 0--------

r - - - - - - - - - - - . - - - - - XA'I543- - - - - - i
J
I I
I
I I SCR
I I
"CROWBAR"
I
I
I
I
I
L

RESET

SUPPLY BUS
RETURN

Figure 11. XR-1543-0ver Current Shutdown Circuitry

0.0111

VOUT

ISOl.ATED +10 V
BIAS SUPPl.Y

20 K

GND

Figure 12. XR-1543 - DC Converter with Isolated Current Limiting

5-154
 XR-2230

Pulse-Width Modulator Control System

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2230 is a high-performance monolithic pulse
width modulator control system. It contains all the nec-
COMP1 COMP2
essary control blocks for designing switch mode power
supplies, and other power control systems. Included in
the 18-Pin dual-in-line package are two error amplifiers,
a sawtooth generator, and the necessary control logic
to drive two open-collector power transistors. Also in-
cluded are protective features, such as adjustable
dead-time control, thermal shutdown, soft-start control, SET
and double-pulse protection circuitry.
OSCILLATOR
VCC
The device provides two open-collector output transis- OUTPUT
tors which are driven 180° out-of-phase, and are capa- EXTERNAL
DT ADJ
ble of sinking 30 mA. These outputs can be used to im- SHUTDOWN
plement single-ended or push-pull switching regulation

•
of either polarity in transformerless or transformer- PWM OUT
coupled converters.
GND PWM IN

OUT1 OUT2
FEATURES
Thermal Shutdown
Adjustable Dead-time ORDERING INFORMATION
Dual Open-Collector
30 mA Output Transistors Part Number Package Operating Temperature
Double-Pulse Protection Circuit XR-2230CP Plastic O°C to + 70°C
Soft-Start Control
High-Speed Remote Shut-Down Input
Two High-Performance Error Amplifiers
with ± 5V Input Common-Mode Range SYSTEM DESCRIPTION
The XR-2230 PWM circuit contains two high-
performance error amplifiers with wide input common-
mode range, and large voltage gains. Typically, one am-
APPLICATIONS plifier (Pins 16, 17, 18) is used for current sensing and
the other (Pins 1, 2, 3) is used as an error amplifier to
Switching Regulators sense the output voltage. The XR-2230 requires a split
Motor-Speed Controllers supply between ± 8 volts and ± 15 volts, however, it
Pulse-Width Modulated Control Systems can be operated from a single supply with proper exter-
nal biasing on the ground pin and input pins of the error
amplifiers. The output drivers capable of sinking 30 mA
at a saturation voltage of about 0.3V can be used in a
ABSOLUTE MAXIMUM RATINGS push-pull configuration, or can be paralleled for a
single-ended configuration with a duty cycle between
Positive Supply Voltage -0.5 to + 18V 0% to over 90%.
Negative Supply Voltage +0.5 to -18V
Input Voltage -18 to + 18V The XR-2230 features a self-protecting thermal-
Output Voltage -0.5 to + 18V shutdown circuitry which turns off the output drivers
Power Dissipation (TA S 25°C) 400 mW when the junction temperature exceeds 130°C. The on-
Operating Temperature -10°C to +85°C board regulator stabilizes the oscillator frequency to
Storage Temperature - 55°C to + 125°C 0.1 %N for reliable performance.

5-155
XR·2230
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = + 12V, VEE:::: -12V, fOSC = 20 kHz, unless otherwise specified.
SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS
SUPPLY SECTION
VCC Positive Supply Voltage +10 V
VEE Negative Supply Voltage -10 V
ICC Positive Supply Current 7.0 11.0 15.0 rnA
lEE Negative Supply Current -2.0 -6.0 -2.0 rnA
OSCILLATOR SECTION
fOSC Frequency Range 10 100 kHz
Initial Accuracy 15 % RT :::: 30 kO,
CT :::: 4700 pF
Supply Voltage Stability 0.1 %N VCC :::: + 10V :::z + 15V
Low Supply Voltage -20 +20 % VCC :::: + 18V, VEE:::: -8V
Temperature Stability 0.01 %IOC
VOSC Sawtooth Peak Voltage 3.0 3.5 4.0 V
0 Duty Cycle Range 10 90 % fOSC:::: 20 kHz
VOLTAGE ERROR AMPLIFIER
VOS Input Offset Voltage 2 10 mV
IBIAS Input Bias Current -.5 -30 ,.,.A
AVO Open-Loop Gain 60 90 dB
f-3dB Closed-Loop Bandwidth 25 kHz AVCL:::: 40 dB
CMMR Common-Mode Rejection 60 dB VICM:::: ±4.5V
Ratio
YOM Output Voltage Swing ±5 V RL :::: 10 kO
VCC :::: +8V, VEE :::: -8V
SR Slew Rate 2 4 V/,.,.s AVCL = 14 dB,
RF :::: 10 kO
Input Voltage Range ±5 V
CURRENT ERROR AMPLIFIER
VOS Input Offset Voltage 4 20 mV
IBIAS Input Bias Current -1.0 -60 ,.,.A
AVO Open-Loop Gain 60 90 dB
f-3 dB Closed-Loop Bandwidth 25 kHz AVCL :::: 40 dB
CMRR Common-Mode Rejection 60 90 dB VICM = ±4.5V
Ratio
YOM Output Voltage Swing ±5 V RL :::: 10 kO
±4 V VCC :::: +8V, VEE :::: -8V
SR Slew Rate 4 8 V/,.,.s AACL :::: 14 dB,
RF :::: 10 kO
Input Voltage Range ±5 V
MODULATOR SECTION
Set Input Open Voltage 3.1 3.6 4.1 V
(Pin 15) 2.8 3.3 4.3 V VCC:::: +8V, VEE :::: -8V
Modin Input Open Voltage 3.1 3.6 4.1 V
(Pin 11) 2.8 3.3 4.3 V VCC :::: +8V, VEE :::: -8V
Inhibit Input Current (Pin 13) -50 -10 ,.,.A
td Inhibit Propagation Delay 60 ns
Out1, Out2, Output Voltage 0.3 V 10 :::: 30 rnA, TA :::: 25°C
(Pins 9 and 10) 0.4 V TA:::: -10 :::z +85°C
Low Supply Voltage 0.3 V 10 :::: 27 rnA, TA :::: 25°C
tf Out1, Out2 Fall Time 30 ns
Modout Output Voltage 0.3 V 10 :::: 16 rnA, TA :::: 25°C
(Pin 12) 0.4 V TA:::: -10:::z +85°C
Under Low Supply Voltage 0.3 V 10 :::: 24 rnA, TA :::: 25°C
Oscillator Output Voltage 0.4 V 10 = 3 rnA, TA :::: 25°C
(Pin 14) 0.6 V TA:::: -10"" +85°C
Thermal Shutdown Temp. 130 °C

5-156
 XR·2230
OSCILLATOR
OUTPUT

DEAD TIME
CDMPAR ... TOR

EXTER~"'L
SHUTDOWN

Figure 1. Equivalent Schematic Diagram

PRINCIPLES OF OPERATION PWM output so that the output transistor's off time is
•
a function of the error amplifier'S input voltage.
The heart of the XR-2230 is the sawtooth generator. As
seen in Figure 1, this sawtooth drives one input of each 2. Pulse-steering information from flip-flop two, which
of the three system comparators. Comparators one and will determine which output transistor receives the
two have their other inputs tied to the outputs of the er- PWM input signal. Flip-flop two will toggle once eve-
ror amplifiers. These comparators will now produce, at ry cycle of the sawtooth generator's output, which
their outputs, square waves which will have a duty cy- will make the output transistor's toggle frequency
cle proportional to the voltage at the inputs to the error one-half that of the sawtooth generator's.
amplifiers, or pulse width information. The pulse width
information is fed into the NOR gate and used to pro- 3. Information from dead-time and thermal shutdown
vide the reset information to the pulse-width modulation circuitry. The dead-time is an externally adjustable
flip-flop (PWM). The PWM flip-flop information is fed in time between one output transistor turning off and
to the NAND gate with the external shutdown and PWM the other turning on. This is used to protect external
flip-flop set input. The information from the NAND gate circuitry. This dead-time is controlled by an external
drives an open-collector transistor to provide the pulse- voltage applied to Pin 6, which is internally com-
width modulation output, Pin 12. The PWM output will pared with the sawtooth waveform. The thermal
be a square wave with a frequency set by the sawtooth shutdown circuitry will drive the input to the NAND
generator, and a duty cycle equal to either comparator, gate low, if the junction temperature exceeds 130°C.
one or two, whichever is shorter. If the external shut- This will make both outputs low.
down, Pin 13 is driven low, the PWM output will remain
The circuit control blocks and functions operate as fol-
low or go to zero duty cycle. The set input of the PWM
lows:
flip-flop, Pin 15, is normally connected to the buffered
sawtooth generator output, Pin 14, so that a reset pulse Error Amplifiers-These are high-gain op amps which are
is provided every cycle. Each output transistor is driven used to sense output conditions, voltage and current,
by a three input NAND gate. These inputs consist of: and provide a de voltage to comparators one and two.
This will in turn adjust the PWM output duty cycle and
1. Pulse width information from the PWM input, Pin 11, ultimately that of the output transistors to correct for er-
which is used to control the off time of the output rors in the output voltage or overcurrent conditions. The
transistors. The PWM input is normally tied to the amplifier'S outputs are provided for tailoring the closed-

5-157
 XR·2230
loop gain or frequency response of the system. Figure FADJ, Pin 7-A resistor, Rext to + VCC, and a capacitor,
2 shows the relationship between output duty cycle, Cext, to ground from this pin, set the frequency of the
Pins 11 and 12 connected, and the voltage at Pins 1 or sawtooth and oscillator output, by the relationship:
18. Amplifier two is approximately twice as fast as Am-
plifier one, and should, therefore, be used to sense out-
FOSC = 2.68
put current.
Rext x Cext
External Shutdown, Pin 13-A low level signal applied to
this pin will turn both outputs on. If not used, this input The sawtooth waveform a signal varying from zero volts
should be left open-circuited. The impedance at this to + 5V, will be present at Pin 7. Normal values of Rext
node is approximately 1 MO. will range from 1 kO to 100 kO. Figure 3 shows the oscil-
lator period as a function of various Rext and Cext val-
Oscillator Output, Pin 14-This is an open-collector output ues.
which will be a square wave with a frequency set by the
sawtooth generator. The duty cycle of this output will The dead-time (minimum time from one output turning
vary from 10 to 90 %, and is a function of the dead-time on to the other turning off) is controlled by the voltage
setting. This pin is normally connected to Pin 15, set to applied to Pin 6.
provide reset pulses for the PWM flip-flop.
Dead-time Control, Pin 6-Figure 4 shows output deadtime
Set, Pin 15-This is the set input for the PWM flip-flop. A as a function of VplN 6. The maximum duty cycle of
low-going signal at this pin will cause the flip-flop to be each output is also controlled by the dead-time, and
reset. The impedance at this pin is approximately 7.5 may be determined by the following expression:
kO. This pin is normally connected to the oscillator out-
put, Pin 14.
Duty Cycle Max (%) = (1 - ~) x 50%
PWM Out, Pin 12-This is an open-collector output which VplN 6
provides a square wave with a duty cycle determined
by the error amplifiers. This output is normally connect- VPIN 6 <3.5V
ed to PWM IN, Pin 11.

PWM In, Pin 11-This is the input which controls the duty The impedance into this pin is approximately 10 kO.
cycle of the output transistors. A low level on this pin
will drive both output transistors on. The impedance in- APPLICATIONS INFORMATION
to this pin is approximately 7.4 kO.
The soft-start function may be implemented as shown
Output Transistors, Pins 9 and 10-These pins provide the in Figure 7. This configuration will reduce the output du-
open-collector output transistors which are capable of ty cycle to zero, and gradually increase to its normal
sinking 30 mA, typically. They are alternately turned off, operating pOint, whenever power is applied to the cir-
180 0 out-of-phase, at a rate equal to one-half the fre- cuit, or after an external shutdown command has been
quency of the oscillator. given. This is used to keep the magnetics in the circuit
from saturating.
100

- / lOOK

~~~v
V
-;~ ~ V~
V

/
SDK ,p'

30K
7 :/
,--- 20K
/ L / ~/
/ ~ V 0.Y- -
/~
/ rz:E 10K

SK
VV V
L

..
/ V
~ ,

/ / / /
0 K
/ / /
V V V V
/ 100 200
Vl.II(MV)
300 400
lK

5" 10~ 20,..

/

lO'A~" 100~ 200,..

Sawtooth Waveform JlertQdtI.)

Figure 2. Modulation Duty Cycle vs Error Voltage Figure 3. Oscillation Period vs REXT and CEXT

5-158
 XR·2230
9.0
The time for the duty cycle to start will be approximately
equal to R1 x C1.

A typical step-down switching regulator configuration is

shown in Figure 8. Only one output transistor is used,
so that the maximum duty cycle will be limited to 45 %.
8.0

V
/
ICC

-
If a larger duty cycle range is needed, the two outputs
may be externally NOR'd as shown in Figure 9. This
configuration will allow up to 90% duty cycles. C
§.
7.0
/ ----
Figure 10 shows a detailed timing diagram of circuit op-
eration. o
u
- 60

I 'ed
50
j
\
50

/
40

30
\ i\
40
BV

Figure 5. Supply Current vs Supply Voltage

10~ 12V ICV 16V

\\
•
soc mV

2C. --'
400
:;-
§.

10
\ Z
z
~
TA = 25 C

\ :>
0
11
300
VrWMOUT
!
9\~/
'l '"
2
.,; kUT1.2
~-C

,:;::;#'
z 200
~

..
-'
::>
fi\~q,·

Figure 4. Dead Time vs Dead Time Adjustment Voltage 0

>
100

?
/
-. 10
.<--.
20 30 40 50
'O\JT(mAl

Figure 6. Output Saturation Voltage vs load Current

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITION UNIT
VCC Positive Supply Voltage +10:::: +15 V
VEE Negative Supply Voltage -10:::: -15 V
RR Minimum Feedback Resistance 10 kO
AV Minimum Voltage Gain 14 dB
5 VN

5-159
XR·2230
EXTERNAL
SHUTDOWN
OR POWER DOWN
Vee

13

XR·2230
D.T.ADJ

D.T.ADJ.

Figure 7. SoH Start Connection

XR·2230

-15Vo------.~--------~--------------~

+ 11 -16V o------+--~..._--+_-+-....-----<....- -.....--_I

GNDo------+--~~--~--~----~--~--_I

.01,..F

0, '> MR 850
0, '> MJE 171
+15V @ 200 mA L1 ,.. 40 TURNS #20 WIRE ON
FERROXCUBE #K300S02
TOROID CORE

Figure 8. + 10V Step-Down Regulator

5-160
 XR·2230

.vcco-------~~----------~~~

Figure 9. Outputs Nor'd for up to 90% Duty Cycle's

•

NOR ..... L OP£R ... nON PROTECTION Of IIAXI ..O .. COTY

STE ... DY STATE WITH DOUBLE-PULSING CYCLE lIlIIT
VOLTAGE ERROR fEEDB ... CK DETECTION OPER ... nON

Figure 10. Timing Waveform Diagram

5-161
 XR-4194

Dual-Tracking Voltage Regulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-4194 is a dual-polarity tracking regulator de-
signed to provide balanced or unbalanced positive and
negative output voltages at currents of up to 200 mA. A VO+ +VIN
single resistor can be used to adjust both outputs be-
posmVE
REGULATOR
tween the limits of ± 50mV and ± 42 V. The device is
NC NC
ideal for local on-card regulation, which eliminates the
distribution problems associated with single-point regu-
lation. The XR-4194 is available in a 14-pin ceramic COMP+ GND
dual-in-line package, which has a 900 mW rating.

BAL RSET

COMP- RO

FEATURES NC NC

Direct Replacement for RM/RC 4194

80th Outputs Adjust with Single Resistor VO-
Load Current to ± 200 mA with 0.2 % Load Regulation
Low External Parts Count
Internal Thermal Shutdown at TJ = 175°C
External Adjustment for ± Vo Unbalancing

APPLICATIONS
On-Card Regulation ORDERING INFORMATION
Adjustable Regulator
Part Number Package Operating Temperature
XR-4194CN Ceramic DIP O°C to + 70°C
XR-4194M Ceramic DIP - 55°C to + 125°C

ABSOLUTE MAXIMUM RATINGS

Input Voltage ± V to Ground
XR-4194M ±45 V SYSTEM DESCRIPTION
XR-4194CN ±35 V
Input/Output Voltage Differential ±45 V The XR-4194 is a dual polarity tracking voltage regula-
Power Dissipation at TA = 25°C 900mW tor. An on board reference, set by a single resistor, de-
Load Current 30 mA termines both output voltages. Tracking accuracy is
Operating Junction Temperature Range better than 1 %. Non-symmetrical output voltages are
XR-4194M -55°C to + 150°C obtained by connecting a resistor to the balance adjust
XR-4194CN O°C to + 125°C (Pin 4). Internal protection circuits include thermal
Storage Temperature Range - 65°C to + 150°C shutdown and active current limiting.

5·162
ELECTRICAL CHARACTERISTICS
XR·4194
Test Conditions: ±5 s VOUT s VMAX; XR-4194M -55°C s +125°C; XR-4194CN O°C :5 TJ :5 +70°C

- 55°C s TJ :5 + 125°C XR-4194M XR-4194CN

PARAMETERS MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
Line Regulation 0.02 0.1 0.02 0.1 %VOUT AVIN = 0.1 VIN
Load Regulation 0.001 0.0025 0.001 0.004 %VO/mA XR-4194CN, M:
I L == 5 to 100 mA
TC of Output Voltage 0.002 0.020 0.003 0.015 %/OC
*Stand-by Current Drain from +0.3 +1.0 +0.3 +1.5 mA VIN = VMAX, Vo == OV

to -1.2 -2.0 -1.2 -2.0 VIN = VMAX, Vo = OV

Input Voltage Range ±9.5 ±45 ±9.5 ±35 V
Output Voltage Scale Factor 2.45 2.5 2.55 2.38 2.5 2.62 KOIV RSET = 71.5 K
TJ == 25°C
Output Voltage Range 0.05 +42 0.05 ±32 V RSET == 71.5 K
Output Voltage Tracking 1.0 2.0 %
Ripple Rejection 70 70 dB f = 120 Hz, TJ = 25°C
Input-Output Voltage Differential 3.0 3.0 V IL = 50mA
Output Short Circuit Current 300 300 mA VIN = ±30 V Max
Output Noise Voltage 250 250 /LV RMS CL = 4.7 /LF, Vo == ±15V
f = 10Hz to 100 KHz
Internal Thermal Shutdown 175

* ± IQuiescent will increase by 50 /LAIVOUT on positive side and 100 /LAIVOUT on negative side.

THERMAL CHARACTERISTICS
175 °C

II
XR-4194M XR-4194CN
PARAMETERS MIN TYP MAX MIN TYP MAX CONDITIONS
Power Dissipation 900mW 900 mW TA == 25°C
2.2 W 2.2 W TC == 25°C
Thermal Resistance
Junction to Ambient 128°C/W 128°C/W
Junction to Case 55°C/W 55°C/W
+YOUT -YOUT

+VOUT -VOUT

1 SAL
'Yo
AS

-Yo
•. 7~f TANTALUM

XA.. tf4 AO

G N O I - - -....

c+ c-

71.5K' 71.5K·

° For a.,t TrKklng TemPifaiur. Coetflclent

01 Ro Should Be S.""A1F~RS
Adt\4lRoIot -"S • ev (l51<UI 1'-"
Adiull R810f ·"5 • 12 'II (20 Kill

Figure 2. Typical Applications

5-163
XR·4194

COMP.

IAL
RO RUT L~ __
fR£""£NClU;;n- - - - - - - - - - - - -,
QHO

VO-

L __________________ ~I L ________________ ~
-VIN

EQUIVALENT SCHEMATIC DIAGRAM

5·164
 XR·4195

+ 15V Dual-Tracking Voltage Regulator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-4195 is a dual-polarity tracking regulator de-

signed to provide balanced positive and negative 15V
output voltages at currents of up to 100mA.
COMp·

The device is ideal for local "on-card" regulation, which POSITIVE

REGULATOR
eliminates the distribution problems associated with liND 2 'loVOIJT
single-point regulation. Intended for ease of application,
the XR-4195 requires only two external components for
operation. HAL

FEATURES
Direct Replacement for RM/RC 4195
± 15V Operational Amplifier Power
Thermal Shutdown at Tj = + 175°C
Output Currents to 100mA
As a Single Output Regulator, it may be used with up to
•
+50V Output
Available in a-Pin Plastic Mini-DIP
Low External Parts Count
ORDERING INFORMATION
Part Number Package Operating Temperature
XR-4195CP Dip O°C to + 70°C

APPLICATIONS
Operational Amplifier Supply
On-Card Regulation
Regulating High Voltage

SYSTEM DESCRIPTION

ABSOLUTE MAXIMUM RATINGS The XR-4195 is a dual polarity tracking voltage regula-
tor, internally trimmed to ± 15V. Only output capacitors
Input Voltage ± V to Ground ±30 V are required for operation. Internal protection circuits
Power Dissipation at TA = 25°C 600mW include thermal shutdown and active current limiting.
Load Current 100 mA The device may be configured as a single output high
Operating Junction Temperature voltage regulator by adding a voltage divider between
Range O°C to + 125°C an output pin, the device ground (Pin 2) and system
Storage Temperature Range -65°C to +150°C ground.

5-165
XR·4195
ElECTRICAL CHARACTERISTICS
Test Conditions: (lL = 1mA, VCC = ± 20V, CL = 10/-IF unless otherwise specified)

XR-4195CP
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Line Regulation 2 20 mV VIN = ± 18 to ±30V
Load Regulation 5 30 mV IL = 1 to 100 mA
Output Voltage Temperature
Stability 0.005 0.015 %/OC
Standby Current Drain ± 1.5 ±3.0 mA VIN = ±30V, IL = OmA
Input Voltage Range 18 30 V
Output Voltage 14.5 15 15.5 V Ti = +25°C
Output Voltage Tracking ±50 ±300 mV
Ripple Rejection 75 dB f = 120 Hz, Ti =
+25°C
Input-Output Voltage Differential 3 V IL = 50mA
Short-Circuit Current 220 mA Ti = +25°C
Output Noise Voltage 60 /-IV RMS Ti = +25°C,
f = 100Hzt0100kHz
Internal Thermal Shutdown 175 °C

THERMAL CHARACTERISTICS

XR-4195CP
PARAMETERS MIN TYP MAX CONDITIONS
Power Dissipation 0.6W TA = 25°C
TC = 25°C
Thermal Resistance 210°C/W OJ-C
OJ-A

+15V at 100mA -15V at 100mA

Vo =+50V at 100mA
lO,.,F Rl R2
lO,.,F

£,.-.il+ 1.........1--. t .1+. .

+Vo
---'-t

XR-4195
GND

R2
Va = +15V (1 +R,"l

1'1" -l llvo '3V' < vr" <60V

+53V to +60V -=-

Balanced Output Positive Single Supply

TYPICAL APPLICATIONS

5-166
 XR·4195

~--~----~----~------------------~--------------------~--------r---o+V'N

r----------f--------;---o CaMP

GROUND

CaMP
L-...4.--------------1---Q +15V

BALANCE 1IIIIIIII
t---......----~--<> -15V

L----J-----1--------~~-----------L------------~--------~------------~~__o -V'N
EQUIVALENT SCHEMATIC DIAGRAM

5-167
5-168
 Cross References & Ordering Information

Telecommunication Circuits

Data Communication Circuits

Computer Peripheral Circuits

Industrial Circuits

~ln_t_e_rl_a_Ce__C_ir_cu_i_ts__________________________ 1IIII
1IIII
~s_p_e_c_ia_I_F_u_n_~_io_n__C_ir_c_u_it_s____________________
User Specific linear ICs
~--------------------------------------
II I

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

6
 Section 6 - Instrumentation Circuits
Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Fundamentals of Monolithic Waveform Generation and Shaping 6-2
Choosing the Right IC Oscillator . . . . . 6-3
XR-205 Monolithic Waveform Generator 6-5
XR-2206 Monolithic Function Generator 6-10
XR-2207 Voltage-Controlled Oscillator . . 6-16
XR-2209 Precision Oscillator . . . . . . . 6-25
XR-8038 Precision Waveform Generator 6-30
XR-8038A Precision Waveform Generator 6-34
Multipliers/Multiplexers . . . . . . . . . . . 6-36
XR-2208 Operational Multiplier 6-38
XR-2228 Monolithic Multiplier/Detector 6-46
Phase-Locked Loops . . . . . . . . . . . . . 6-55
Fundamentals of Phase-Locked Loops 6-56
Applications of PLL ICs . . . . . . . . 6-57

•
Choosing the Right PLL Circuit 6-59
XR-210 Modulator/Demodulator . . . 6-60
XR-215 Monolithic Phase-Locked Loop 6-65
XR-22ll FSK DemodulatorlTone Decoder 6-74
XR-2212 Precision Phase-Locked Loop 6-82
I
XR-2213 Precision Phase-Locked Loop/Tone Decoder 6-89
Tone Decoders . . . . . . . . . . . . 6-95
XR-567 Monolithic Tone Decoder 6-96
XR-567 A Precision Tone Decoder · 6-106
XR-L567 Micropower Tone Decoder .. · 6-108
XR-2567 Dual Monolithic Tone Decoder · 6-115

6-1
Fundamentals of Monolithic Waveform
Generation and Shaping
Waveform or function generators find a wide range of Co goes off. Except for a half cycle delay, output VS(t) is
applications in communications and telemetry equip- the same as VA(t).
ment, as well as for testing and calibration in the labora-
tory. In most of these applications, commercially-
available monolithic IC oscillators and function genera- v+ SYNC OUTPUT
tors provide the system designer with a low-cost
alternative to conventional, non-integrated units costing
several hundred dollars or more.

The fundamental techniques of waveform generation

and shaping are well suited to monolithic IC technology.
In fact, monolithic integrated circuits offer some inher-
ent advantages to the circuit designer, such as the
availability of a large number of active devices and
close matching and thermal tracking of component val-
ues. Sy making efficient use of the capabilities of inte-
grated components and the batch-processing advan-
~ AM INPUT OUTPUT v-
IV\ (OPTIONAL) oc LEVEL
SELECT CONTROL
tages of monolithic circuits, it is now possible to design
integrated waveform generator circuits that can provide Figure 1. Basically, a waveform generator consists of four
a performance comparable to that of complex discrete sections. Each section can be built readily In
generators, at a very small fraction of the cost. This ar- monolithic form with established Ie technology.
ticle provides a brief review of the fundamental princi-
ples of monolithic waveform generation and wave-
shaping methods.
01 02
Basics of Ie Waveform Generation
Essentially a waveform generator is a stable oscillator
circuit that outputs well-defined waveforms; and, these
can be externally modulated or swept over a frequency
range. A waveform generator usually consists of four
sections: (1) an oscillator to generate the basic periodic
waveform; (2) a wave-shaper; (3) an optional modulator v A(I) O-+-------il-------+--O ve(t)
section to provide AM capability, and (4) an output
buffer amplifier to provide the necessary load drive.

Figure 1 shows a simplified generator using the four

functional blocks. Each block can be built readily in
monolithic form with established linear IC technology.
Hence fabrication of all four blocks on a single mono-
lithic chip has evolved as a natural extension of earlier
circuits.
vu,lPU n U I . ,
o

The oscillator, usually a relaxation type, can generate

linear, triangle or ramp waveforms. The usual technique
involves constant-current charging and discharging of
an external timing capacitor. Figure 2 shows a typical,
though simplified, example: an emitter-coupled multivi-
brator circuit, which can generate a square wave as
well as a triangle or a linear ramp output.

The circuit's operation is as follows: At any given time,

either 01 and 01 or 02 and 02 ara conducting such
that capacitor Co is alternately charged and discharged
by constant-current 11. The output across 01 and 02
corresponds to a symmetrical square wave, having a
pk-pk amplitude of 2VSE, or twice the transistor base-
emitter voltage drop. Output VA, constant when 01 is Figure 2. A simple oscillator circuit can be used to generate
on, becomes a linear ramp with a slope equal to -111 square, ramp and triangle waveforms.

6-2
Choosing The Right IC Oscillator
At the onset of his design, the user of monolithic oscil- FM Generation
lator products is faced with the key question of choos-
ing the oscillator or the function generator best suited Essentially all of Exar's Ie oscillator circuits can be
to his application. The broad line of function generator used for generating frequency-modulated waveforms.
products offered by Exar covers a wide range of appli- For small frequency deviations (i.e., ± 5% or less)
cations. It is often difficult to determine at a glance the about the center frequency, all of these oscillators have
best circuit for a given application. The purpose of this FM nonlinearity of 0.1 % or less. However, if wider FM
section is to review some of the key performance re- deviations are required the XR-2209, XR-2207 and the
quirements, from an applications pOint of view, and XR-2206 offer the best FM linearity.
help answer the question. "What is the best Ie oscilla-
tor for the job?"
FSK Generation
Sine Wave Generation
Frequency-shift keying (FSK) is widely used in digital
In evaluating the output characteristics of sinusoidal Ie communications, particularly in data-interface or
oscillators, total harmonic distortion (THD) of the out- acoustical-coupler type MODEM systems. In monolith-
put waveform is usually the key performance criteria. ic Ie oscillators, FSK capability is obtained by using a
In a number of vOice-grade telecommunication or labo- current-controlled oscillator and keying its control cur-
ratory applications, sine wave distortion of 2 % to 3 % rent between two or more programmed levels which
may be tolerable. However, for audio-quality signals, are set by external resistors. This results in output
distortion level of 1 % or less is required. Furthermore, waveforms which are phase-continuous during the fre-
it is desirable that the output distortion should be rela- quency transitions between the "mark" and "space"
tively independent of the output amplitude, frequency frequencies.
or temperature changes; and that the distortion level
be minimized with a minimum amount of external ad- The XR-2207 can produce four discrete frequencies,
justments. set by one external capacitor and four setting resistors.
Frequency keying between these four frequencies is
Exar manufactures three separate families of Ie oscil- achieved by a two-bit binary logic input. The circuit pro-
lators which provide sinusoidal output waveforms. duces both triangle and square wave outputs. The
These are the XR-205, XR-2206 and the XR-8038. All of XR-2206 produces two discrete frequencies, f1 and f2,
these circuits require external trimming to minimize the and has a one-bit keying logic input. The key advantage
output distortion. In the case of XR-205, the untrimmed of XR-2206 over the XR-2207 in FSK MODEM deSign is
distortion is about 5 %; in the case of the XR-2206 and the availability of a sinusoidal output waveform.
the XR-8038, untrimmed distortion is typically less than
2 %, and can be reduced to 0.5 % with additional trim- Exar has compiled a comprehensive application note
ming. describing the use of both of these Ie products in the
design of FSK MODEM systems. This application note
For low frequency sine wave generation (below 100 entitled "Stable FSK MODEMs Featuring the XR-2207,
kHz), the XR-2206 and the XR-8038 are the recom- XR-2206 and the XR-2211" is also included in this Data
mended circuits. The XR-8038 has a fixed output level, Book.
whereas the XR-2206 offers separate output dc level
and amplitude adjustment capability. Laboratory Function Generator
AM Generation One of the main applications for oscillators is for labo-
ratory or test instrumentation or calibration where a va-
Linear modulation of output amplitude by means of an riety of different output waveforms are required. Most
analog control Signal is a desirable feature for teleme- such applications require both AM/FM modulation ca-
try and data transmission applications. In monolithic Ie pability, linear frequency sweep and sinusoidal output.
oscillators, this capability is normally obtained by in- The circuit which fits this application best is the XR-
cluding a four-quadrant transconductance multiplier on 2206 since it has all the fundamental features of a com-
the Ie chip. Both the XR-205 and the XR-2206 circuits plete function generator system costing upwards of
have such a feature included on the chip and can be several hundred dollars.
used for generating sinusoidal AM signals. They can
operate both in suppressed-carrier or conventional A comprehensive description of building a self-con-
double-sideband AM generator mode. For operation tained laboratory-quality function generator system us-
with frequencies below 100 kHz, the XR-2206 has supe- ing the XR-2206, Application Note AN-14, is included in
rior performance characteristics over the XR-205. this Data Book.

6-3
Phase-Locked Loop Design Low-Cost General Purpose Oscillator
The current-controlled or voltage-controlled oscillator In many digital design applications, one needs a stable,
(VCO) is one of the essential components of a phase- low-cost oscillator IC to serve as the system clock. For
locked loop (PLL) system. The key requirement for this such applications, the XR-2209 precision oscillator is a
application is that the oscillator should have a high de- logical deSign choice since it is a simple, low-cost oscil-
gree of frequency stability and linear voltage or lator circuit and offers 20 ppm/oC frequency stability.
current-to-frequency conversion characteristics. Sinus-
oidal output, although often useful, is generally not re- The monolithic timer circuits, such as the XR-555, or its
quired in this application. micropower version, the XR-L555, can also be used as
low-cost, general purpose oscillators by operating
Although all of Exar's IC oscillators can be used as a them in their free-running, i.e., self-triggering, mode.
VCO in designing PLL systems, the XR-2207 or its low-
cost and simplified version, the XR-2209, are often the Ultra-Low Frequency Oscillator
best suited devices for this application. For additional
information refer to Application Note AN-06, entitled In certain applications such as interval-timing or se-
"Precision PLL System Using the XR-2207 and the XR- quencing, stable, ultra-low frequency oscillators which
2208," which is included in this Data Book. can operate at frequencies of 0.01 Hz or lower are re-
quired. Among Exar's oscillator circuits, the IC most
suited to such an application is the XR-8038 since it
Sweep Oscillator can operate with. a polarized electrolytic capacitor as
its timing component. All other oscillator circuits de-
A sweep oscillator is required to have a large linear scribed in this book require non-polar timing capaci-
sweep range. Among Exar's function generators, the tors, and therefore are not as practical as the XR-8038
XR-2207 and the XR-2206 have the widest linear sweep for ultra-low frequency operation.
range (over 1000: 1), and are best suited for such an ap-
plication. An alternate approach to obtaining stable ultra-low fre-
quency oscillators is to use the XR-2242 counter/timer
By using a linear ramp output from the XR-2207 to as an oscillator in its free-running mode. Such a circuit
sweep the frequency of the XR-2206, one can build a generates a square wave output with a frequency of
two-chip sweep oscillator system which has a 2000:1 (1/256 RC) where Rand C are the external timing com-
sweep range and sinusoidal output. ponents.

6-4
 XR-205

Monolithic Waveform Generator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-205 is a highly versatile, monolithic waveform
generator designed for diverse applications in commu-
nication and telemetry equipment, as well as in sys- MODULATOR
OUTPUTS
tems design and testing. It is a self-contained, totally
monolithic signal generator that provides sine, square, TIMING
CAPACITOR
triangle, ramp and sawtooth output waveforms, which
can be both amplitude and frequency modulated. MODULATOR
X-INPUTS FM. SYNC .•
AND SWEEP
The circuit has three separate sections: a voltage- INPUT

controlled oscillator (VCO) which generates the basic SOUAREWAVE

OUTPUT
periodic waveforms; a balanced modulator which pro- MODULATOR
vides amplitude or phase modulation; a buffer amplifier Y-INPUTS BUFFER
OUTPUT
section which provides a low impedance output with
high current drive capability. BUFFER
INPUT
WAVEFORM
ADJ

FEATURES
High Frequency Operation

•
AM and FM Capabilities
Sine, Triangle, Square, Sawtooth, Ramp
and Pulse Waveforms
Wide Supply Range 8 V to 26 V
Split Supply Capability
I

APPLICATIONS
Waveform Generation ORDERING INFORMATION
Sinewave Sawtooth
Triangle Ramp
Square Pulse Part Number Package Operating Temperature
AM Generation Double Sideband Suppressed Carrier XR-205 Ceramic O°C to + 70°C
FM Generation
Sweep Generation
Tone Burst Generation
Simultaneous AM/FM
Frequency-Shift Keyed (FSK) Signal Generation
Phase-Shift Keyed (PSK) Signal Generation SYSTEM DESCRIPTION
On-Off Keyed Oscillation
Clock Generation The XR-205 is a high frequency monolithic function
generator capable of sine, square, triangle, ramp, saw-
tooth, and pulse waveforms with frequencies ranging to
4 MHz. Operating frequency is determined by a single
capacitor and may be externally swept over a 10: 1
ABSOLUTE MAXIMUM RATINGS range. Duty cycle is variable from 10% to 90 %. Ampli-
Power Supply 26 Volts tude modulation, up to 100 %, is accomplished using
Power Dissipation 750 mW the modulator X inputs (Pins 3 and 4). The on board
Derate above + 25°C 6 mW/oC buffer amplifier features 50n output resistance and 20
Temperature mA output capability. The XR-205 operates with either
Storage single or split supplies.

6-5
 XR·205
ElECTRICAL CHARACTERISTICS
Test CondHlons: Supply Voltage = 12V (single supply) TA = 25°C, f - 10 kHz, RL = 3 kO, unless otherwise specified.
LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
I - General Characteristics
Supply Voltage:
Single Supply 8 26 Vdc See Figure 1
Split Supply ±5 ±13 Vdc See Figures 2 and 3
Supply Current 8 10 12 mA w/o buffer amp
Frequency Stability:
Power Supply 0.2 0.5 %N IVcc - VEEI > 10V
Temperature 300 600 ppm/oC Sweep Input open circuit
Frequency Sweep Range 7:1 10:1 See Figure 7
Output Swing:
Single Ended 2 3 Vpp Measured at pin 1 or 2
Differential 4 6 Vpp Measured across 1 and 2
Output Diff. Offset Voltage 0.1 0.4 Vdc Measured across 1 and 2
Amplitude Control Range 60 dB Controlled by Rq (see Figure 1)
Buffer Amplifier Output
Resistance 50 ohms RL = 7500
Output Current Swing ±6 ±10 mA
II - Output WavefOTms
Sinusoidal:
Upper Frequency Limit 2 4 MHz Measured at Pin 11
Peak Output Swing 2 3 Vpp S1, S3 closed, S2 open
Distortion (THO) 2.5 4 % closed S2 open
Triangle:
Peak Swing 2 4 Vpp Measured at Pin 11
Non·Linearity ±1 % S1, S2 open, S3 closed
Asymmetry ±1 % f = 10 kHz
Saw1ooth:
Peak Swing 2 3 Vpp See Figure 1, S2 closed;
Non·Linearity 1.5 % S2 and S3 closed
Ramp:
Peak-Swing 1 1.4 Vpp See Figure 1, S2 and S3 open
Non·Linearity 1 % pin 10 shorted to pin 15
Squarewave (Low Level):
Output Swing 0.5 0.7 Vpp See Figure 1, S2 and S3 open,
Duty Cycle Asymmetry q±1 ±4 % pin 10 shorted to pin 12
Rise Time 20 ns 10 pF connected from pin 11
Fall Time 200 ns to ground
Squarewave (High Level):
Peak Swing 2 3 Vpp See Figure 3, S2 open
Duty Cycle Asymmetry ±1 ±4 %
Rise Time 80 ns 10 pF connected from pin 11
Fall Time 60 ns to ground
Pulse Output: 2 3 Vpp See Figure 3, S2 closed
Peak Swing 2 3 Vpp See Figure 3, S2 closed
Rise Time 80 ns
Fall Time 60 ns
Duty Cycle Range 20·80 % Adjustable (see Figure 6)
III - Modulation Characteristics (sine, triangle and squarewave):
.A.mp!itude Modu!ation:
Double Sideband
Modulation Range 0-100 % See Figure 2
Linearity 0.5 % for 30% modulation
Sideband Symmetry 1.0 %
Suppressed Carrier
Carrier Suppression 52 dB f < 1 MHz
Frequency Modulation: I
Distortion 0.3 % See Figure 2 (± 10 frequency
deviation)

6-6
XR·205
TEST CIRCUITS DESCRIPTION OF CIRCUIT CONTROLS
(Refer to functional block diagram)
VCC I' 12VI

TIMING CAPACITOR (PINS 14 AND 15)

The oscillator frequency is inversely proportional to the
value of the timing capacitor, Co' connected between
pins 14 and 15. With the sweep input open circuited, fre-
quecy fo can be approximated as: fo = 400/C o where fo
is in Hz and Co is in microforads. (See Figure 4.)

MODULATOR Y-INPUTS (PINS 5 AND 6)

These inputs are normally connected to the oscillator
outputs. For sinewave or trianglewave outputs, they are
dc coupled to pins 14 and 15 (see Figure 1); for high-
level squarewave or pulse output, ac coupling is used
BUFfER OUTPUT
as shown in Figure 3.
Figure 1. Test Circuit for Single-Supply Operation
MODULATOR X-INPUTS (PINS 3 AND 4)
Modulator output (at pins 1 or 2) is proportional to a dc
'6V
voltage applied across these inputs - (see Figure 5).
~'V'v--il---o OM INPUT
These inputs can be used for amplitude modulation or,
.---t-----o,tDdl, as an output amplitude control. The phase of the output
voltage is reversed if the polarity of the dc bias across
pins 3 and 4 is reversed; therefore these inputs can be
used for phase-shift keyed (PSK) modulation .

15K
rvv
'V'v
OR
MODULATOR OUTPUTS (PINS 1 AND 2)
All of the high level output waveforms are obtained at
these terminals. The output waveforms appear differen-
tially between pins 1 and 2. The terminals can, therefore,
be used for either in-phase or out-of-phase outputs.
Norma"y, a 15 KO load resistor should be connected
between these terminals to prevent the output from
saturating or clipping at large output voltage swings.
•
This output has a high output impedance and should
be buffered.
Figure 2. Test Circuit for Split-Supply Operation and AM/FM
Modulation
LOW LEVEL SQUAREWAVE OUTPUT (PIN 12)

SWEEP OR lK The output at this pin is a symmetrical squarewave with

SYNC O----\/IIIr-+---. 0.7V amplitude and 20 ns rise time. It can be used di-
INPUT
rectly as an output waveform, or amplified to a 3 Vpp
signal level using the modulator section of the XR-205
as an amplifier (see Figure 3).

SWEEP OR FM INPUT (PIN 13)

The oscillator frequency increases linearly with an in-
creasing negative voltage, Vs , applied to this terminal.
20K Normally a series resistor, Rs (Rs := approx. 1 KO) is
connected in series with this terminal to provide current
limiting and linear voltage-to-frequency transfer charac-
JV1.. teristics. The frequency derivation (for any given modu-
lation level) is inversely proportional to Rs. Typical
L-----O ...A.JL sweep characteristics of the circuit are shown in Figure
OUTPUT
50.

AMPLITUDE
Aq ~~T:~T -u-u- 7. For proper operation of the circuit with Rs = 1 KO,
AOJ '------+---'
OUTPUT SOUARE WAVE S2 OPEN
PULSE S2 Cl OSEO
the sweep voltage, Vs , must be within range: (Vso - 6)
VEE 16VI
> Vs > (Vso + 1) where Vso is the open circuit voltage
Figure 3. Test Circuit for High-Level Pulse and Squarewave at pin 13. The frequency of oscillation can also be syn-
Output chronized to an external source by applying a sync

6-7
pulse to this terminal. For Rs = 1 KO, a sync
XR·205
OUTPUT WAVEFORMS
pulse of 0.1 V to 1V amplitude is recommended.
TRIANGLE OUTPUT
WAVEFORM ADJUSTMENT (PINS 7 AND 8)
The circuit is connected as shown in Figures 1 or 2,
The shape of the output waveform at pins 1 and 2 is with switches S1 and S2 open.
controlled by a potentiometer, Rj' connected between
these terminals as shown in Figure 1. For sinewave out- SINEWAVE OUTPUT
puts at pins 1 and 2, the value of Rj is adjusted to mini-
mize the harmonic content of the output waveform. This The circuit is connected as shown in Figures 1 or 2,
adjustment is independent of frequency and needs to with switch S2 open and S1 closed. The output wave-
be done only once. The output can be converted to a form is adjusted for minimum harmonic distortion using
symmetrical triangle waveform by increasing the effec- trimmer resistor Rj connected across pins 7 and 8. Si-
tive resistance across these terminals. This can be nusoidal output is obtained from pins 1 or 2 (or pin 11 if
done without changing the potentiometer setting, by the buffer amplifier is used). The amplitude of the out-
opening the switch S2 as shown in Figures 1-3. put waveform is controlled by the differential dc voltage
appearing between pins 3 and 4. This bias can be con-
BUFFER INPUT AND OUTPUT (PINS 10 AND 11) trolled by potentiometer Rq . for a differential bias be-
tween these terminals of ± 2 volts or greater, the output
The buffer amplifier can be connected to any of the cir- amplitude is maximum and equal to approximately 3
cuit outputs (pins 1, 2, 12, 14 or 15) to provide low out- volts pop.
put impedance and high current drive capability. For
proper operation of the buffer amplifier, pin 11 must be SAWTOOTH OUTPUT
connected to the most negative potential in the circuit,
with an external load resistor RL (0.75 KO < RL < 10 The circuit is connected as shown in Figures 1 or 2,
KO). The maximum output current at this pin must not with switch S1 open and S2 closed. Closing S2 places
exceed 20 mA. resistor RS across pins 13 and 14. This changes the du-
ty cycle of the triangle output and converts it to a saw-
DUTY CYCLE ADJUSTMENT tooth waveform. The polarity of the sawtooth can be
changed by reversing the polarity of the dc bias across
The duty-cycle of the output waveforms can be adjust- pins 3 and 4. If S1 is closed, the linear sawtooth wave-
ed by connecting a resistor RS across pins 13 and 14, form is converted to the sinusoidal sawtooth waveform
as shown in Figures 1-3. With switch S2 open, the out- of Figure gA.
put waveform will be symmetrical. Duty cycle is re-
duced as RS is decreased. (See Figure 6.) RAMP OUTPUT (FIGURE 9B)
ADDITIONAL GAIN CONTROL For ramp outputs, switch S3 of Figure 1 or 2 is opened,
and pin 10 is shorted to pin 14. This results in a 1.4 volt
For amplitude modulated output signals, the dc level pop ramp output at pin 11. The duty cycle of this ramp
across pins 3 and 4 is fixed by the modulation index re- can be controlled by connecting RS across pins (13-14)
quired. In this case, the output amplitude can be con- or (13-15).
trolled without effecting the modulation by connecting a
potentiometer between pins 1 and 2. SQUAREWAVE AND PULSE OUTPUTS
ON-OFF KEYING For squarewave outputs, the circuit is connected as
shown in Figure 3, with S2 open. The output can be
The oscillator can be keyed off by applying a positive converted to a pulse by closing S2. The duty cycle of
voltage pulse to the sweep input terminal. With Rs = 1 the pulse output is controlled by potentiometer RD. The
KO, oscillations will stop if the applied potential at pin amplitude and polarity of either the pulse or square-
13 is raised 3 volts above its open-circuit value. wave output can be controlled by potentiometer Rq .

6-8
XR·205
~--~--~----------

~ ~
~ 10"1 ~--+-+---+-~-+----i--+---l ~ 1.0
o ~
~ 10- 2
0.•
~
S 0.1 .-
j 10. 3 --+--+--+--+ o
S u--
~ 0.2 _.M __ '
::!
10·11..--"-_~--I.:---"-:-.....J:'-~~
1 10 102 i ~1~.0--.~0.1---~----~o,-~-~.'.0
'REOUENCY IH.I

Figure 4. Frequency II • Function of Co Figure 5. Modular Section Phase and Figure 6. Duty-Cycle and Frequency
Acrou Pins 14 and 15 Amplituda Transfar Characteristics Variation as a Function of Rulstor RS
Connected Acrm Plnl13 and 14

·611
,;WEEP IIOLTACE. ",IVOLTSI

Figure 7. Normalized Frequency VI.

Sweep Voltage
·lbll
o~o-~--·~--~-~-~-~

NORMA LinD FREaU~NCY 11/1.1

Figure 8. Sinusoidal Output Distortion

as a Function 01 Frequency Sweep
Figure 9. Sinusoidal Sawtooth and
Unear Ramp Outputs
•
11
BUFFER
AMPLlfll'I

OSCILLATOR

EQUIVALENT SCHEMATIC DIAGRAM

6-9
 XR·2206

Monolithic Function Generator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2206 is a monolithic function generator inte-
grated circuit capable of producing high quality sine,
square, triangle, ramp, and pulse waveforms of high-
stability and accuracy. The output waveforms can be
both amplitude and frequency modulated by an exter-
AM
INPUT l
SYMMETRY
ADJ.
nal voltage. Frequency of operation can be selected ,..,..ORN
externally over a range of 0.01 Hz to more than 1 MHz. OUTPUT J
The circuit is ideally suited for communications, instru-
mentation, and function generator applications requir-
MULT. OUT l
WAVEFORM
ADJ.
ing sinusoidal tone, AM, FM, or FSK generation. It has a
typical drift specification of 20 ppm/DC. The oscillator
frequency can be linearly swept over a 2000:1 frequen-
+vcc
J
cy range, with an external control voltage, having a GROUND
very small affect on distortion. TIMe:
CAPACITOR

L SYNC
OUTPUT

FEATURES TIMING
RESISTORS
r BYPASS

Low-Sine Wave Distortion

Excellent Temperature Stability
0.5 %,
20 ppm/DC,
Typical
Typical L FSK
INPUT

Wide Sweep Range 2000: 1, Typical

Low-Supply Sensitivity 0.01 % V, Typical
Linear Amplitude Modulation ORDERING INFORMATION
TIL Compatible FSK Controls
Wide Supply Range 10V to 26V Part Number Package Operating Temperature
Adjustable Duty Cycle 1 % to 99% XR-2206M Ceramic -55°C to +125°C
XR-2206N Ceramic O°C to + 70°C
XR-2206P Plastic O°C to + 70°C
XR-2206CN Ceramic O°C to + 70°C
APPLICATIONS XR-2206CP Plastic O°C to + 70°C

Waveform Generation
Sweep Generation
AM/FM Generation SYSTEM DESCRIPTION
V/F Conversion
FSK Generation The XR-2206 is comprised of four functional blocks; a
Phase-Locked Loops (VCO) voltage-controlled oscillator (VCO), an analog multiplier
and slne-shaper; a unity gain buffer amplifier; and a set
of current switches.

The VCO actually produces an output frequency pro-

ABSOLUTE MAXIMUM RP.lINGS portional to an input current, which is produced by a re-
sistor from the timing terminals to ground. The current
Power Supply 26V switches route one of the timing pins current to the
Power Dissipation 750 mW VCO controlled by an FSK input pin. to produce an out-
Derate Above 25°C 5 mW/oC put frequency. With two timing pins, two discrete output
Total Timing Current 6mA frequencies can be independently produced for FSK
Storage Temperature - 65°C to + 150°C Generation Applications.

6-10
XR·2206
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, V + = 12V, TA = 25°, C = 0.01 ILF, R1 = 100 kO, R2 = 10 kO, R3 = 25 kO
unless otherwise specified. S1 open for triangle, closed for sine wave.

XR-2206M XR-2206C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL CHARACTERISTICS
Single Supply Voltage 10 26 10 26 V
Split-Supply Voltage ±5 ±13 ±5 ±13 V
Supply Current 12 17 14 20 mA R1 ~ 10 k 0
OSCILLATOR SECTION
Max. Operating Frequency 0.5 1 0.5 1 MHz C = 1000 pF, R1 = 1 k 0
Lowest Practical Frequency 0.01 0.01 Hz C = 50 p,F, R1 = 2 M 0
Frequency Accuracy ±1 ±4 ±2 % of fo fo = 1/R1 C
Temperature Stability ±10 ±50 ±20 ppm/oC O°C s TA s 70°C,
R1 = R2 = 20 k 0
Supply Sensitivity 0.01 0.1 0.01 %/V VLOW = 10V, VHIGH ==
20V,
R1 = R2 = 20 k 0
Sweep Range 1000:1 2000:1 2000:1 fH=fL fH @ R1 == 1 k 0
fL @ R1 = 2 M 0
Sweep Linearity
10:1 Sweep 2 2 % fL = 1 kHz, fH = 10kHz
1000: 1 Sweep 8 8 % fL = 100 kHz, fH = 100
kHz
0.1 % ± 10% Deviation

•
FM Distortion 0.1
Recommended Timing
Components
Timing Capacitor: C 0.001 100 0.001 100 ILF See Figure 4.
Timing Resistors: 1 2000 1 2000 kO
R1 & R2
Triangle Sine Wave Output See Note 1, Figure 2.
Triangle Amplitude 160 160 mV/k 0 Figure 1, S1 Open
Sine Wave Amplitude 40 60 80 60 mV/kO Figure 1, S1 Closed
Max. Output Swing 6 6 V pop
Output Impedance 600 600 0
Triangle Linearity 1 1 %
Amplitude Stability 0.5 0.5 dB For 1000: 1 Sweep
Sine Wave Amplitude 4800 4800 ppm/oC See Note 2.
Stability
Sine Wave Distortion
Without Adjustment 2.5 2.5 % R1 = 30 k 0
With Adjustment 0.4 1.0 0.5 1.5 % See Figures 6 and 7.
Amplitude Modulation
Input Impedance 50 100 50 100 kO
Modulation Range 100 100 %
Carrier Suppression 55 55 dB
Linearity 2 2 % For 95% modulation
Square-Wave Output
Amplitude 12 12 V pop Measured at Pin 11.
Rise Time 250 250 nsec CL = 10 pF
Fall Time 50 50 nsec CL = 10 pF
Saturation Voltage 0.2 0.4 0.2 0.6 V IL = 2 mA
Leakage Current 0.1 20 0.1 100 ILA V11 == 26V
FSK Keying Level (Pin 9) 0.8 1.4 2.4 0.8 1.4 2.4 V See section on circuit
controls
Reference Bypass Voltage 2.9 3.1 3.3 2.5 3 3.5 V Measured at Pin 10.

Note 1: Output amplitude is directly proportional to the resistance, R3, on Pin 3. See Figure 2.
Note 2: For maximum amplitude stability, R3 should be a positive temperature coefficient resistor.

6-11
 SI = OPEN FOR TRIANGLE
XR·2206
- ~J
CLOSED FOR SINE WAVE.
w
o

~
J- I-

~ 1.0
~
~
g
\ V
5.1K

V+o-~--------~ ~ 0.5
1\ V
l------.--Jy'\,I\r--o V+
i
~ 1\ /
1\V
V+/2
DC VOLTAGE AT PIN 1

Figure 1. Basic Test Circuit. Figure 5. Normalized Output Amplitude versus DC Bias at
AM Input (Pin 1).

T~IANGLE V /
/ /
fR~~~JO~o~
/ /
VSINEWAVE
lz
o
3
MINIMUM
DISTORTION AT 30 KlI

J /V ~
o
:;; 2

/V 5

~
Ij/ ............ ~
20 40 60 80 100
R31N KlI
1.0 10 100
TIMING R KlI
Figure 2. Output Amplitude as a Function of the Resistor,
R3. at Pin 3. Figure 6. Trimmed Distortion versus Timing Resistor.

26 r---~--~--~~--~----

=
R 3KIl
=
VOUT 0.5 VRMS PIN 2
J
=
RL 10 KlI

I
14 I--...".,."-t-,,.,,c.-+----+---+------I

J'V
7
10 ' - - - - - - - ' - - - - - ' - - - - - ' - - - ' - - - - - - '
12 16 20 24 28
10 100 lK 10K lOOK 1M
VCc(V)
FREQUENCY (Hz)

Figure 3. Supplv Current versus Supply Voltage, Timing, R. Figure 7. Sine Wave Distortion versus Operating Frequency
with Timing Capacitors Varied.
10MlI

"~"'M'IM !'NU \ ..
1 Mil

It ~.!7. 7/7

i Ii:
<:l
l00KO

~~
~
~
~~
;:: -;-;%
lOKI!

~~%
lKII
10- 2 10 102 104 106 -25 0 25 50 75 100 125
FREQUENCY Hz
AMBIENT TEMPERATURE (OC)

Figure 4. R versus Oscillation Frequency. Figure 8. Frequency Drift versus Temperature.

6-12
XR·2206
PIN7
Re -Ie _IT ORB

SWEEP

{
+ Ve ~ Ie
INPUT

_~t 12

Figure 9. Circuit Connection lor Frequency Sweeo.

'1 =R:e
5.1K S.1K
'2 =R~e

5.1K

10K V+O-~~--------~

SOUAREWAVE
OUTPUT Ip.F

51 CLOSED FOR SINEWAVE

!M -,._ _ _ _ _9~
+~
.2V,-=-
KEYING
INPUT
9
..L 1V
J ,1
2

•
Figure 10. Circuit lor Sine Wave Generation without External
Adjustment. (See Figure 2 lor Choice 01 R3).
Figure 12. Sinusoidal FSK Generator.

rvoAN
, SAWTOOTH f 2 ,

ru
OUTPUT
OUTPUT C ,A, • R2.

!J\
AC

'O.F
5 'K -=- DUTY CYCLE R1 ~ 1R2

~'
~~~ 1
__ , .. F

1 -~~__ t'OK I'·F

I saUAREWAVF
o OUTPUT

M
s, CLOSED FOR SINEWAVE i
Figure 11. Circuit lor Sine Wave Generation with Minimum Figure 13. Circuit for Pulse and Ramp Generation.
Harmonic Distortion. (R3 Determines Output
Swing-See Figure 2.)

6-13
Frequency-Shift Keying: FSK Generation
XR·2206
The XR-2206 can be operated with two separate timing Figure 12 shows the circuit connection for sinusoidal
resistors, R1 and R2, connected to the timing Pin 7 and FSK signal operation. Mark and space frequencies can
8, respectively, as shown in Figure 12. Depending on be independently adjusted by the choice of timing re-
the polarity of the logic signal at Pin 9, either one or the sistors, R1 and R2; the output is phase-continuous dur-
other of these timing resistors is activated. If Pin 9 is ing transitions. The keying signal is applied to Pin 9. The
open-circuited or connected to a bias voltage ~ 2V, only circuit can be converted to split-supply operation by
R1 is activated. Similarly, if the voltage level at Pin 9 is simply replacing ground with V-.
:s 1V, only R2 is activated. Thus, the output frequency
can be keyed between two levels, f1 and f2, as: Pulse and Ramp Generation
f1 = 1/R1C and f2 = 1/R2C Figure 13 shows the circuit for pulse and ramp wave-
form generation. In this mode of operation, the FSK key-
For split-supply operation, the keying voltage at Pin 9 is ing terminal (Pin 9) is shorted to the square-wave output
referenced to V - . (Pin 11), and the circuit automatically frequency-shift
keys itself between two separate frequencies during
Output DC Level Control: the positive-going and negative-going output wave-
forms. The pulse width and duty cycle can be adjusted
The dc level at the output (Pin 2) is approximately the from 1 % to 99% by the choice of R1 and R2. The val-
same as the dc bias at Pin 3. In Figures 10, 11 and 12, ues of R1 and R2 should be in the range of 1 kO to 2
Pin 3 is biased midway between V + and ground, to MO.
give an output dc level of :::::: V + 12.

APPLICATIONS INFORMATION PRINCIPLES OF OPERATION

Sine Wave Generation Description of Controls
Without External Adjustment: Frequency of Operation:

Figure 10 shows the circuit connection for generating a The frequency of oscillation, fo, is determined by the ex-
sinusoidal output from the XR-2206. The potentiometer, ternal timing capacitor, C, across Pin 5 and 6, and by
R1 at Pin 7, provides the desired frequency tuning. The the timing resistor, R, connected to either Pin 7 or 8.
maximum output swing is greater than V + 12, and the The frequency is given as:
typical distortion (THO) is <2.5%. If lower sine wave
distortion is desired, additional adjustments can be pro- fo = ....!... Hz
vided as described in the following section. RC

The circuit of Figure 10 can be converted to split-supply and can be adjusted by varying either R or C. The rec-
operation, simply by replacing all ground connections ommended values of R, for a given frequency range, as
with V -. For split-supply operation, R3 can be directly shown in Figure 4. Temperature stability is optimum for
connected to ground. 4 kO < R < 200 kO. Recommended values of Care
from 1000 pF to 100 1lF.
With External Adjustment: Frequency Sweep and Modulation:
The harmonic content of sinusoidal output can be re- Frequency of oscillation is proportional to the total tim-
duced to :::::: 0.5 % by additional adjustments as shown ing current, Ir. drawn from Pin 7 or 8:
in Figure 11. The potentiometer, RA, adjusts the sine-
shaping resistor, and RB provides the fine adjustment
for the waveform symmetry. The adjustment procedure
is as follows:
f = 320 IT (mA) Hz
C (IlF)
1. Set RB at midpoint and adjust RA for minimum
Timing terminals (Pin 7 or 8) are low-impedance points,
distortion.
and are internally biased at + 3V, with respect to Pin 12
2. With RA set as above, adjust RB to further reduce Frequency varies linearly with IT, over a wide range of
distOition. current values, from 1 p.,f., to 3 mAo The frequency can
be controlled by applying a control voltage, VC, to the
Triangle Wave Generation activated timing pin as shown in Figure 9. The frequen-
cy of oscillation is related to Vc as:
The circuits of Figures 10 and 11 can be converted to
triangle wave generation, by simply open-circuiting Pin
13 and 14 (i.e., S1 open). Amplitude of the triangle is ap-
~
f = -11 + -R( 1 - - ) Hz
RC RC 3
vcj
proximately twice the sine wave output.

6-14
XR·2206
where Ve is in volts. The voltage-to-frequency conver- Amplitude Modulation:
sion gain, K, is given as:
Output amplitude can be modulated by applying a dc bi-
K = lJf/lJVe = - 0.32 Hz/V as and a modulating signal to Pin 1. The internal imped-
Ree ance at Pin 1 is approximately 100 kO. Output ampli-
tude varies linearly with the applied voltage at Pin 1, for
CAUTION: For safety operation of the circuit, IT values of dc bias at this pin, within ± 4 volts of V + /2 as
should be limited to ::s 3 mA. shown in Figure 5. As this bias level approaches V + /2,
the phase of the output signal is reversed and the am-
Output Amplitude: plitude goes through zero. This property i's suitable for
~hase-shift keyin.g and suppressed-carrier AM genera-
Maximum output amplitude is inversely proportional to
tion. Total dynamic range of amplitude modulation is ap-
the exte~nal resistor, R3, connected to Pin 3 (see Figure
proximately 55 dB.
2). For sme wave output, amplitude is approximately 60
mV peak per kO of R3; for triangle, the peak amplitude
C~UTlON: AM control must be used in conjunction
is approximately 160 mV peak per kO of R3. Thus, for
example, R3 = 50 kO would produce approximately with a well-regulated supply, since the output amplitude
± 3V sinusoidal output amplitude. now becomes a function of V + .

v+
..
INT'NL
REG.

12

•
EQUIVALENT SCHEMATIC DIAGRAM

6-15
 XR·2207

Voltage-Controlled Oscillator
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2207 is a monolithic voltage-controlled oscilla-
tor (VCO) integrated circuit featuring excellent frequen- tVee TRIANGLE
cy stability and a wide tuning range. The circuit pro- WAVE OUT

vides simultaneous triangle and squarewave outputs

over a frequency range of 0.01 Hz to 1 MHz. It is ideally
suited for FM, FSK, and sweep or tone generation, as
r
TIMING
CAPACITOR
SQUARE
WAVE OUT

well as for phase-locked loop applications.

L
~
The XR-2207 has a typical drift speCification of 20 ppml BIAS
DC. The oscillator frequency can be linearly swept over
a 1000:1 range with an external control voltage; and the
duty cycle of both the triangle and the squarewave out- I
TIMING
R2 GROUND

puts can be varied from 0.1 % to 99.9% to generate RESISTORS

stable pulse and sawtooth waveforms. I R3
I
BINARY
KEYING

L::
INPUTS

FEATURES ...J
Excellent Temperature Stability (20 ppm/DC)
Linear Frequency Sweep ORDERING INFORMATION
Adjustable Duty Cycle (0.1 % to 99.9%)
Two or Four Level FSK Capability Part Number Package Operating Temperature
Wide Sweep Range (1000:1 Min) XR2207M Ceramic -55°C to + 125°C
Logic Compatible Input and Output Levels XR2207N Ceramic O°C to + 70°C
Wide Supply Voltage Range (± 4V to ± 13V) XR2207P Plastic O°C to + 70°C
Low Supply Sensitivity (0.1 %IV) XR2207CN Ceramic O°C to + 70°C
Wide Frequency Range (0.01 Hz to 1 MHz) XR2207CP Plastic O°C to + 70 0 e
Simultaneous Triangle and Squarewave Outputs
SYSTEM DESCRIPTION
APPLICATIONS The XR-2207 utilizes four main functional blocks for fre-
FSK Generation quency generation. These are a voltage controlled os-
Voltage and Current-to-Frequency Conversion cillator (VCO), four current switches which are activated
Stable Phase-Locked Loop by binary keying inputs, and two buffer amplifiers for tri-
Waveform Generation angle and squarewave outputs. The veo is actually a
Triangle, Sawtooth, Pulse, Squarewave current controlled oscillator which gets its input from
FM and Sweep Generation the current switches. As the output frequency is propor-
tional to the input current, the veo produces four dis-
crete output frequencies. Two binary input pins deter-
ABSOLUTE MAXIMUM RATINGS mine which timing currents are channelled to the veo.
These currents are set by resistors to ground from each
Power Supply 26V of the four timing terminals.
Power Dissipation (package limitation)
Ceramic package 750 mW The triangle output buffer provides a low impedance
Derate above + 25 C Q
6.0 mW/oC output (10n TYP) while the squarewave is an open-
Plastic package 625 mW collector type. A programmable reference point allows
Derate above + 25°C 5 mW/oC the XR-2207 to be used in either single or slip supply
Storage Temperature Range -65°C to + 150°C configurations.

6-16
XR·2207
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, V+ = V- = 6V, TA = +25°C, C = 5000 pF, R1 = R2 = R3 = R4 =
20 KO, RL = 4.7 KO, Binary Inputs grounded, 81 and 82 closed unless otherwise specified.

XR·2207/XR·2207M XR·2207C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply 8 26 8 26 V See Figure 3
Split Supplies ±4 ±13 ±4 ±13 V
Supply Current
Single Supply 5 7 5 8 mA Measured at pin 1, S1 and S2 open
See Figure 2
Split Supplies
Positive 5 7 5 8 mA Measured at pin 1, S1, S2 open
Negative 4 6 4 7 mA Measured at pin 12, 51, S2 open
OSCILLATOR SECTION - FREQUENCY CHARACTERISTICS
Upper Frequency Limit 0.5 1.0 0.5 1.0 MHz C = 500 pF, R3 = 2 KO
Lowest Practical Frequency 0.01 0.01 Hz C = 50 JAoF, R3 = 2 MO
Frequency Accuracy ±1 ±3 ±1 ±5 % offo
Frequency Matching 0.5 0.5 % of fo
Frequency Stability
Temperature 20 50 30 ppm/DC DoC < TA < 70°C
Power Supply 0.15 0.15 %/V
Sweep Range 1000:1 3000:1 1000:1 fH/fL R3 = 1.5 KO for fH1
R3 = 2 MO for fL
Sweep Linearity % C = 5000 pF
10:1 Sweep 1 1.5

•
2 fH = 10 kHz, fL = 1 kHz
1000: 1 Sweep 5 5 fH = 100 kHz, fL = 100 Hz
FM Distortion 0.1 0.1 % ± 10% FM Deviation
Recommended Range of 1.5 2000 1.5 2000 KO See Characteristic Curves
Timing Resistors
Impedance at Timing Pins 75 75 a Measured at pins 4, 5, 6, or 7
DC Level at Timing Terminals 10 10 mV
I
BINARY KEYING INPUTS
Switching Threshold 1.4 2.2 2.8 1.4 2.2 2.8 V Measured at pins 8 and 9,
Referenced to pin 10
Input Impedance 5 5 KO
OUTPUT CHARACTERISTICS
Triangle Output Measured at pin 13
Amplitude 4 6 4 6 Vpp
Impedance 10 10 {}
DC Level +100 +100 mV Referenced to pin 10
Linearity 0.1 0.1 % From 10% to 90% to swing
Squarewave Output Measured at pin 13, S2 closed
Amplitude 11 12 11 12 Vpp
Saturation Voltage 0.2 0.4 0.2 0.4 V Referenced to pin 12
Rise Time 200 200 nsec CL s 10 pF
Fall Time 20 20 nsec CL s 10 pF

PRECAUTIONS
nent damage to the device may occur if the total
The following precautions should be observed when op- timing current exceeds 10 mA.
erating the XR-2207 family of integrated circuits: 2. Terminals 2, 3, 4, 5, 6, and 7 have very low internal
1. Pulling excessive current from the timing terminals impedance and should, therefore, be protected from
will adversely effect the temperature stability of the accidental shorting to ground or the supply volt-
circuit. To minimize this disturbance, it is recom- ages.
mended that the total current drawn from pins 4, 5, 3. The keying logic pulse amplitude should not exceed
6, and 7 be limited to s6 mA. In addition, perma- the supply voltage.

6-17
 XR·2207
r---~---------?------4r~------~--~------~--~~~---------'----~V·

TRIANGLE WAVE
14 OUTPUT

2R'

4R

~------~---------+------~~~6-~V-
12

EQUIVALENT SCHEMATIC DIAGRAM

O'J:1

t-l--;3::>--4~ ~~~~R5uT
14 TRIANGLE 14 TRIANGLE
WAVE OUT WAVE OUT

51 '----4--........---4------'

Figure 1. Test Circuit For Split Supply Operation Figure 2. Test Circuit For Single Supply Operation

PRINCIPLES OF OPERATION range from 100 pF to 100 I'F. The capacitor should be
non-polar.
TIMING CAPACITOR (PINS 2 AND 3)
TIMING RESISTORS (PINS 4, 5, 6, AND 7)
The oscillator frequency is inversely proportional to the
timing capacitor, C, as indicated in Figure 8. The mini- The timing resistors determine the total timing current,
mum capacitance value is limited by stray capaci- ITt available to charge the timing capacitor. Values for
tances and the maximum value by physical size and timing resistors can range from 2 KO to 2 MO; however,
leakage current considerations. Recommended values for optimum temperature and power supply stability,

6-18
XR·2207
recommended values are 4 KO to 200 KO (see Figures are activated by the logic signals at the binary keying
4, 5, and 7). To avoid parasitic pick up, timing resistor inputs (pins 8 and 9), as shown in the logic table (Table
leads should be kept as short as possible. For noisy en- 1). If a single timing resistor is activated, the frequency
vironments, unused or deactivated timing terminals is 1/RC. Otherwise, the frequency is either 1/(R11IR2)C
should be bypassed to ground through 0.1 ILF capaci- or 1/(R31IR4)C.
tors.

The squarewave output is obtained at pin 13 and has a

SUPPLY VOLTAGE (PINS 1 AND 12)
peak-to-peak voltage swing equal to the supply volt-
The XR-2207 is designed to operate over a power sup- ages. This output is an "open-collector" type and re-
ply range of ± 4V to ± 13V for split supplies, or 8V to quires an external pull-up load resistor (nominally 5 KO)
26V for single supplies. At high supply voltages, the fre- to the positive supply. The triangle waveform obtained
quency sweep range is reduced (see Figures 3 and 4). at pin 14 is centered about ground and has a peak am-
Performance is optimum for ± 6V, or 12V single supply plitude of V + 12.
operation.

BINARY KEYING INPUTS (PINS 8 AND 9) The circuit operates with supply voltages ranging from
±4V to ± 13V. Minimum drift occurs with ±6 volt sup-
The internal impedance at these pins is approximately plies. For operation with unequal supply voltages, see
5 KO. Keying levels are < 1.4V for "zero" and >3V for Figure 3.
"one" logic levels referenced to the dc voltage at pin
10 (see Figure 8). Note: For Single-Supply Operation, Logic Levels are
Referenced to Voltage at Pin 10
BIAS FOR SINGLE SUPPLY (PIN 11)

For single supply operation, pin 11 should be externally

biased to a potential between V + 13 and V + 12 volts

•
(see Figure 2). The bias current at pin 11 is nominally SINGLE SUPPLY OPERATION
5% of the total oscillation timing current, IT-
The circuit should be interconnected as shown in Fig-
GROUND (PIN 10) ure 11 for single supply operation. Pin 12 should be
grounded, and pin 11 biased from V + through a resis-
For split supply operation, this pin serves as circuit tive divider to a value of bias voltage between V + 13
ground. For single supply operation, pin 10 should be and V+ 12. Pin 10 is bypassed to ground through a 1 ILF
ac grounded through a 1 ILF bypass capacitor. During capacitor.
split supply operation, a ground current of 21T flows out
of this terminal, where IT is the total timing current. For single supply operation, the dc voltage at pin 10
and the timing terminals (pins 4 through 7) are equal
SQUAREWAVE OUTPUT (PIN 13) and approximately 0.6V above VB, the bias voltage at
pin 11. The logic levels at the binary keying terminals
The squarewave output at pin 13 is a "open-collector" are referenced to the voltage at pin 10.
stage capable of sinking up to 20 mA of load current.
RL serves as a pull-up load resistor for this output. Rec- For a fixed frequency of f3 = 1/R3C, the external cir-
ommended values for RL range from 1 KO to 100 KO. cuit connections can be simplified as shown in Figure
11b.
TRIANGLE OUTPUT (PIN 14)

rhe output at pin 14 is a triangle wave with a peak

swing of approximately one-half of the total supply volt-
age. Pin 14 has a very low output impedance of 100
and is internally protected against short circuits.
Table 1
BYPASS CAPACITORS Logic Table for Binary Keying Controls

The recommended value for bypass capacitors is 1 ILF, LOGIC

although larger values are required for very low fre- LEVEL SELECTED
quency operation. -- TIMING
8 9 PINS FREQUENCY DEFINITIONS
SPLIT SUPPLY OPERATION 0 0 6 11 11 = 1/R3C, AI1 = 1/R4C
Figure 1 is the recommended circuit connection for 0 1 6 and 7 11 + AI1 12 = 1/R2C, AI2 = 1/R1C
split supply operation. The frequency of operation is de- 1 0 5 12 Logic Levels: 0 = Ground
termined by the timing capacitor, C, and the activated 1 = >3 V
1 1 4 and 5 12 + AI2
timing resistors (R1 through R4). The timing resistors
 25r------,-------r------~----~
XR·2207

1 KII L-_ _- ' -_ _-..J._ _ _ _.1.-__ ~

o '8V '12V '16V

SPLIT SUPPL Y

°OL--------~5--------1~0-------~1~5----~-~ SINGLE SUPPL Y

NEGATIVE SUPPLY (VOLT) SUPPL Y VOL TAGE IVOL TSI -

Figure 3. Typical Operating Range For Spilt Supply Voltage Figure 4. Recommended Timing Resistor Value vs. Power
Supply Voltage*
1.04 r-----r--~---r--....,...---.,....._-......,

/ t;: 1.021---fl~--+---I---+-­
- - - - f - Cvs== 5000
'6V / a:
o
pF >
~ 1.00
/ ::>
~
o
/ ~
~
~
/ ~
u-
.9BI---h~-+---I-~~~--+--~
w
>
u
./ S
fS -1 /' N
~ .96~--+--+---4--~-4r+---4
::> V ct
::.
~ -2 ~

ff -3
/ o
Z .94
-4 ~
/ C
-5 .92 L-__....I-____' - -__....I-____.1..-__.-J..__- - I
-6 !2 !4 :6 !B !10 !12 ! 14
SPLIT SUPPL Y VOLTAGE (VOLTS)
-7 1.-__-'-1____.L.'_ _.L.I_ _ _.J...I____.l..1_----'I
lK 10K lOOK 1M 10M
8 12 16 20 24 28
TIMING RESISTANCE (OHMS)
SINGLE SUPPL Y VOLTAGE (VOL TS)

Figure 5. Frequency Accuracy VS. Timing Resistance Figure 6. Frequency Drift VS. Supply Voltage

§
t: +1%
a:0
>
u
Z
w
::>
~
ff -1%
S
N
~
ct
::;:
~
-2%
0
Z

-50 -25 +25 +50 +75 +100 +125

TEMPERATURE ("C)-

Figure 7. Normalized Frequency Drift With Temperature

6-20
XR·2207
LOGIC SELECTED FREQUENCY
LEVEL TIMING
f-- PINS
A U DEFINITIONS
0 0 6 fl fl= I/R3C,Ofl= I/R4C SQUARE WAVE
OUT

0 I 6 and 7 1'1 + Ofl f2 = I/R2C,Of2 = I/R Ie TRIANGLE WAVE

OUT
I 0 5 f2 Logic Lcv~ls: 0 = Ground
I I 4 and 5 1'2 + Of2 1=>3V

Figure 8. Logic Table For Binary Keying Controls.

Note: For Single-Supply Operation, Logic Levels are
Referenced to Voltage at Pin 10
A

v·

v,

SQUARE WAVE
QUT

10 TRIANGLE WAVE
OUT

12 V-

Figure 9. Simplified Schematic of Frequency Control

Mechanism
Figure 10. Split-Supply Operation:
(a) General
(b) Fixed Frequency

The frequency f will increase as the control voltage is

• I

made more negative. If RS = 2 MO, RC = 2 KO, C =

FREQUENCY CONTROL (SWEEP AND FM) 5000 pF, then at 1000: 1 frequency sweep would result
for a negativ sweep voltage Ve = V - .
The frequency of operation is controlled by varying the
total timing current, II. drawn from the activated timing The voltage to frequency conversion gain, K, is con-
pins 4,5, 6, or 7. The timing current can be modulated trolled by the series resistance RC and can be ex-
by applying a control voltage, VC, to the activated tim- pressed as:
ing pin through a series resistor Re as shown in Figures
12 & 13. K = ~ = - __
1_ Hz/volt
AVC ReCV -
For split supply operation, a negative control voltage,
VC, applied to the circuits of Figures 15 & 16 causes
the total timing current, IT, and the frequency, to in- The circuit of Figure 12 can operate both with positive
crease. and negative values of control voltage. However, for
positive values of Vc with small (RetR3) ratio, the direc-
As an example, in the circuit of Figure 12, the binary
tion of the timing current IT is reversed and the oscilla-
keying inputs are grounded. Therefore, only timing pin
tions will stop.
6 is activated.
Figure 13 shows an alternate circuit for frequency con-
The frequency of operation, normally f = ~c' is now
trol where two timing pins, 6 and 7, are activated. The
R3
frequency and the conversion gain expressions are the
proportional to the control voltage, Ve, and determined same as before, except that the circuit would operate
as: only with negative values of Ve. For Vc > 0, pin 7 be-
comes deactivated
f = _1_ [1 _
R3 C
R
VC 3 HZ]
RCV - and the frequency is fixed at f = R~C'

6-21
 XR·2207
with Figure 11. For a "high" logic level at pin 8, the tim-
CAUTION ing resistors R1 and R2 are activated. Similarly, for a
"low" logic level, timing resistors R3 and R4 are en-
For operation of the circuit, total timing current IT must abled.
be less than 6 mA over the frequency control range.
The "high" and "low" logic levels at pin 9 determine
the respective high and low frequencies within the se-
DUTY CYCLE CONTROL lected FSK channel.
The duty cycle of the output waveforms can be con- Recommended component values for various com-
trolled by frequency shift keying at the end of every half monly used FSK frequencies are given in Table 1. When
cycle of oscillator output. This is accomplished by con- only a single FSK channel is used, the remaining chan-
necting one or both of the binary keying inputs (pins 8 nel can be deactivated by connecting pin 8 to either
or 9) to the squarewave output at pin 13. The output V + or ground. In this case, the unused timing resistors
waveforms can then be converted to positive or nega- can also be omitted from the circuit.
tive pulses and sawtooth waveforms.
The low and high frequencies, f1 and f2' for a given
Figure 14 is the recommended circuit connection for FSK channel can be fine tuned using potentiometers
duty cycle control. Pin 8 is shorted to pin 13 so that the connected in series with respective timing resistors. In
circuit switches between the "0,0" and the "1,0" logic fine tuning the frequencies, f1 should be set first with
states given in Figure 11. Timing pin 5 is activated the logic level at pin 9 in a "low" level.
when the output is "high," and the timing pin is acti-
vated when the squarewave output goes to a low state. Typical frequency drift of the circuit for O°C to 75°C op-
eration is ± 0.2 %. Since the frequency stability is di-
The duty cycle of the output waveforms is given as: rectly related to the external timing components, care
must be taken to use timing components with low tem-
Duty Cycle = R2 perature coefficients.
R2 + R3
FSK TRANSCEIVER (FULL-DUPLEX MODEM)
and can be varied from 0.1 % to 99.9% by proper
choice of timing resistors. The frequency of oscillation, The XR-2207 can be used in conjunction with the XR-
f, is given as: 210, FSK demodulator, to form a full-duplex FSK trans-
ceiver, or modem. A recommended circuit connection

1- ~ [R2 : R3]
for this application is shown in Figure 20. Table 1 shows
the recommended component values for 300-Saud
(103-type) and 1200-Saud (202-type) Modem applica-
The frequency can be modulated or swept without tions.
v'
changing the duty cycle by connecting R2 and R3 to a
common control voltage VC, instead of to V - (see Fig- v'
ure 15). The sawtooth and the pulse output waveforms
are shown in Figure 15. ~~ARr.WAV£
BINARY KEYING
INPUTS

ON-OFF KEYING

The XR-2207 can be keyed on and off by simply activat-

ing an open circuited timing pin. Under certain condi-
tions, the circuit may exhibit very low frequency « 1
Hz) residual oscillations in the "off" state due to inter-
nal bias currents. If this effect is undesirable, it can be A
eliminated by connecting a 10 MO resistor from pin 3 to
V+.

TWO-CHANNEL FSK GENERATOR

(MODEM TRANSMITTER)

The multi-level frequency shift-keying capability of XR-

2207 makes it ideally suited for two-channel FSK gen-
eration. A recommended circuit connection for this ap-
plication is shown in Figure 16.

For two-channel FSK generation, the "mark" and B

"space" frequencies of the respective channels are Figure 11. Single Supply Operation:
determined by the timing resistor pairs (R1, R2) and (a) General
(R3, R4)· Pin 8 is the "channel-select" control in accord (b) Fixed Frequency

6-22
XR·2207
V·

saUARE WAVE
OUT

TRIANGLE WAVE
OUT

CB • BYPASS CAPACITOR

, . I- [I -
VCRl]
-
CAl RCV-
~;~EP' V-
- OR
FM
INPUT

Figure 12. Frequency Sweep Operation

B

v'

SQUARE WAVE
OUT

TRIANGLE WAVE
OUT

V·
c

CB • BYPASS CAPACITOR
Figure 15. Output Waveforms:
(a) Squarewave and Triangle Outputs
I [ VCRl]
, • CiiJ I - RC -
V (b) Pulse and Sawtooth Outputs
'ORVC:;:OONLY. V-
• VC?-l (c) Frequency-Shift Keyed Output
SWEEP
OR
-= Top: FSK Output With f2 = 2f1
FM INPUT Bottom: Keying Logic Input

Figure 13. Alternate Frequency Sweep Operation

SAWTOOTH
OUTPUT 4.7K

CB • BYPASS CAPACITOR

R2
DUTY CYCLE • ~ 14

XR-2207

frequency • + 12

4.7K

v- PULse L-~'----6_-6._~_.() v- 1-6VI

')UTPUT

Figure 14. Sawtooth and Pulse Outputs Figure 16. Multi-Channel FSK Generation

6-23
 V' - 12V
XR·2207
, ~. F

.p
12 11

2K
XR·210

FSK
41( DEMODULATOR

15

0.1 ~F
31( 500!!

DATA v·
OUTPUT

n~
101( 21(

FINE TUNE

-::' -::'
"2V 0.01 ~F

XA·2207

FSI(
GENERATOR

J:
MARI< DATA
INPUT
SPACE

FSI< OUTPUT

IVWN\ SPACE
501<
MARl<
ADJ. ADJ.

Figure 17. Full Duplex FSK Modem Using XR-210 and

XR-2207 (See Table 1 For Component Values)
15
TA"25'C

_30
~
! ...!z
~ 25 ~
~ 10
It:
~ 20~+-~~--~+-~~ :l V~
V
u U
> >
t 15~~-+~~~-b~--+-~ t
a
...a
> ~ 5
./
;:::
10~~__~~+--b~~·~~~~
;:::
« V
~ ~
z

o
'6 '8 .,0 ,,2 '14 o '6 ·S 10 12 '14
·SPlIT SUPPLY VOLTAGE (VOL TSI SPLIT SUPPLY VOLTAGE (VOLTS)

~ ~ ~ ~ ~ ~ h ~ ~ ~
SINGLE SUPPLY VOL TAGE (VOL TS)

Figure 18. Positive Supply Current, I + (Measured at Pin 1) Figure 19. Negative Supply Current, 1- (Measured at Pin
vs. Supply Voltage* 12) vs. Supply Voltage

*Note: RT Parallel Combination of Activated Timing Resistors

6-24
 XR-2209

Precision Oscillator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR·2209 is a monolithic variable frequency oscilla·
tor circuit featuring excellent temperature stability and
TRIANGLE
a wide linear sweep range. The circuit provides simul· OUTPUT
taneous triangle and squarewave outputs over a fre·
quency range of 0.01 Hz to 1 MHz. The frequency is set
by an external RC product. It is ideally suited for fre· SQUARE
7 WAVE
quency modulation, voltage to frequency or current to OUTPUT
frequency conversion, sweep or tone generation as
well as for phase· locked loop applications when used in
conjunction with a phase comparator such as the XR·
2208.

FEATURES

•
Excellent Temperature Stability (20 ppm/°C)
linear Frequency Sweep
Wide Sweep Range (1000:1 Min)
Wide Supply Voltage Range (± 4V to ± 13V)
Low Supply Sensitivity (0.15 % IV)
Wide Frequency Range (0.01 Hz to 1 MHz)
Simultaneous Triangle and Squarewave Outputs
ORDERING INFORMATION I
Part Number Package Operating Temperature
XR·2209M Ceramic - 55°C to + 125°C
XR·2209CN Ceramic O°C to + 70°C
XR·2209CP Plastic O°C to + 70°C
APPLICATIONS
Voltage and Current·to·Frequency Conversion
Stable Phase· Locked Loop
Waveform Generation SYSTEM DESCRIPTION
FM and Sweep Generation
The XR·2209 precision oscillator is comprised of three
functional blocks: a variable frequency oscillator which
generates the basic periodic waveforms and two buffer
amplifiers for the triangle and the squarewave outputs.
The oscillator frequency, set by an external capacitor,
ABSOLUTE MAXIMUM RATINGS C, and the timing resistor, R, operates over 8 frequency
Power Supply 26 volts decades, from 0.01 Hz to 1 MHz. With no sweep signal
Power Dissipation (package limitation) applied, the frequency of oscillation is equal to 1/RC.
Ceramic Package 385 mW
Plastic Package 300mW The XR·2209 has a typical drift specification of 20 ppml
Derate above + 25°C 2.5 mW/oC °C. Its frequency can be linearly swept over a 1000:1
Operating Temperatue Range range with an external control signal. Output duty cycle
XR·2209M - 55°C to + 125°C is adjustable from less than 1 % to over 99 %. The de·
XR·2209C O°C to + 70°C vice may operate from either single or split supplies
Storage Temperature Range - 65°C to + 150°C from 8 V to 26 V (± 4 V to ± 13 V).

6-25
 ELECTRICAL CHARACTERISTICS
XR·2209
= V - = 6V, TA
Test Conditions: Test Circuit of Figure 1, V + = + 25°C, C = 5000 pF, R - 20 KO, RL = 4.7 kO. S1 and S2
closed unless otherwise specified.

XR-2209M XR-2209C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply 8 26 8 26 V See Figure 2
Split Supplies ±4 ± 13 ±4 ±13 V See Figure 1
Supply Current
Single Supply 5 7 5 8 mA Measured at pin 1, S1, S2 open
See Figure 2
Split Supplies
Positive 5 7 5 8 mA Measured at pin 1, S1, S2 open
Negative 4 6 4 7 mA Measured at pin 4, S1, S2 open
OSCILLATOR SECTION - FREQUENCY CHARACTERISTICS
Upper Frequency Limit 0.5 1.0 0.5 1.0 MHz C = 500 pF, R = 2 KO
Lowest Practical Frequency 0.01 0.01 Hz C = 50 JLF, R = 2 MO
Frequency Accuracy ±1 ±3 ±1 ±5 % of
fo
Frequency Stability
Temperature 20 50 30 ppm/oC O°C < TA < 70°C
Power Supply 0.15 0.15 %N
Sweep Range 1000:1 3000:1 1000:1 fH/fL R = 1.5 KO for fH 1
R = 2 MO for fL
Sweep Linearity % C = 5000 pF
10:1 Sweep 1 2 1.5 fH = 10kHz, fL = 1 kHz
1000: 1 Sweep 5 5 fH = 100 kHz, fL = 100Hz
FM Distortion 0.1 0.1 % ± 10% FM Deviation
Recommended Range of 1.5 2000 1.5 2000 KO See Characteristic Curves
Timing Resistors
Impedance at Timing Pin 75 75 0 Measured at pin 4
OUTPUT CHARACTERISTICS
Triangle Output Measured at pin 8
Amplitude 4 6 4 6 Vpp
Impedance 10 10 0
Linearity 0.1 0.1 % 10% to 90% of swing
Squarewave Output Measured at pin 7, S2 closed
Amplitude 11 12 11 12 Vpp
Saturation Voltage 0.2 0.4 0.2 0.4 V Referenced to pin 6
Rise Time 200 200 nsec CL :::; 10 pF, RL = 4.7 KO
Fall Time 20 20 nsec CL :::; 10 pF

3. Triangle waveform linearity is sensitive to parasitic

PRECAUTIONS
coupling between the square and the triangle-wave
The following precautions should be observed when op- outputs (pins 7 and 8). In board layout or circuit wir-
erating the XR-2209 family of integrated circuits: ing care should be taken to minimize stray wiring ca-
1. Pulling excessive current from the timing terminal pacitances between these pins.
will adversely effect the temperature stability of the DESCRIPTION OF CIRCUIT CONiROLS
circuit. To minimize this disturbance, it is recom-
mended that the total current drawn from pin 4 be TIMING CAPACITOR (PINS 2 and 3)
limited to :::;6 mA.
2. Terminals 2, 3, and 4 have very low internal imped- The oscillator frequency is inversely proportional to the
ance and should, therefore, be protected from acci- timing capacitor, C. The minimum capacitance value is
dental shorting to ground or the supply voltages. limited by stray capacitances and the maximum value

6-26
XR·2209

Figure 1. Test Circuit for Split Supply Operation (01 1N Figure 2. Test Circuit for Single Supply Operation
4148 or Equivalent)

CHARACTERISTIC CURVES

'Kn~ __ ~ ____ ~ __ ~~ __ ~

o
SPLITSUP'PLY
1'6 24 32
NEGATIVE SUPPLY ,VOLTSI SINGLE SUPPLY
Figure 5. Output Waveforms

•
SUPPLY VOLTAGE (VOlTSI

Figure 4. Recommended Timing Re- Top: Triangle Output (Pin 8)

Figure 3. Typical Operating Range sistor Value vs. Power supply Voltage* Bottom: Squarewave Output (Pin 7)
For Split Supply VoHage

:: t.02I--1'''''--+---+--+-
~
>-
11----+---+--.I'- roor--t~~~*==~~~~
~ 2
~ 98 -
::; 1
o
~ 0

~:;I---.~.----~--~-~ i~
~ -3

-.
-s
92'-:---'-__- ' -__--'-__"'----'__-""
t2 U tS t8 t10 i12
-','-.----.l-----I----+--~ SPLIT SUPPl Y VOLTAGE (VOLTSI

TIMING RESISTANCE 'OHMS) • 12 16 20 24

SINGLE SUPPLY VOLTAGE (VOL lSI
Figure 8. Normalized Frequency
Figure 7. Frequency Drift vs. Supply Drift With Temperature
FIgure 6. Frequency Accuracy vs. Voltage
Timing Resistance *Note: RT = Timing Resistor at Pin 4

RECOMMENDED CIRCUIT CONNECTIONS

Figure 11. Simplified Circuit Connection

for Split Supply Operation With VCC =
VEE > ± 7V (Note: Triangle wave
Figure 9. Circuit Connection for Single Figure 10. Generalized Circuit Connec- output has + O.6V offset with re-
Supply Operation tion for'Split Supply Operation spect to ground.)

6-27
 OPERATING INSTRUCTIONS
XR·2209
by physical size and leakage current considerations.
Recommended values range from 100 pF to 100 ILF. SPLIT SUPPLY OPERATION
The capacitor should be non-polar.
The recommended circuit for split supply operation is
TIMING RESISTOR (PIN 4) shown in Figure 10. Diode D1 in the figure assures that
the triangle output swing at pin 8 is symmetrical about
The timing resistor determines the total timing current, ground. This circuit operates with supply voltages rang-
1,-; available to charge the timing capacitor. Values for ing from ±4V to ± 13V. Minimum drift occurs at ±6V
the timing resistor can range from 1.5 KO to 2 MO; how- supplies. See Figure 3 for operation with unequal sup-
ever, for optimum temperature and power supply stabili- Jlies.
ty, recommended values are 4 KO to 200 KO (see Fig-
ures 4,7, and 8). To avoid parasitic pick up, timing resis- Simplified Connection
tor leads should be kept as short as possible.
For operation with split supplies in excess of ± 7 volts,
SUPPLY VOLTAGE (PINS 1 AND 6) the simplified circuit connection of Figure 11 can be
used. This circuit eliminates the diode D1 used in Fig-
The XR-2209 is designed to operate over a power sup- ure 10; however the triangle wave output at pin 8 now
ply range of ± 4V to ± 13V for split supplies, or 8V to has a + 0.6 volt DC offset with respect to ground.
26V for single supplies. At high supply voltages, the fre-
quency sweep range is reduced (see Figures 3 and 4). SINGLE SUPPLY OPERATION
?erformance is optimum for ± 6V, or 12V single supply
operation. The recommended circuit connection for single-supply
operation is shown in Figure 9. Pin 6 is grounded; and
BIAS FOR SINGLE SUPPLY (PIN 5) pin 5 is biased from V + through a resistive divider as
shown in the figure, and is bypassed to ground with a 1
For single supply operation, pin 5 should be externally ILF capacitor.
biased to a potential between V + 13 and V + 12 volts
(see Figure 9). The bias current at pin 5 is nominally 5 % For single supply operation, the DC voltage at the tim-
of the total oscillation timing current, 1,-; at pin 4. This ing terminal, pin 4, is approximately 0.6 volts above VB,
pin should be bypassed to ground with 0.1 ILF capacitor. the bias voltage at pin 5.

SQUAREWAVE OUTPUT (PIN 7) The frequency of operation is determined by the timing

capacitor C and the timing resistor R, and is equal to 11
The squarewave output at pin 7 is a "open-collector" RC. The squarewave output is obtained at pin 7 and has
stage capable of Sinking up to 20 mA of load current. a peak-to-peak voltage swing equal to the supply volt-
RLserves as a pull-up load resistor for this output. Rec- age. This output is an "open-collector" type and re-
ommended values for RL range from 1 KO to 100 KO. quires an external pull-up load resistor (nominally 5 KO)
to V + . The triangle waveform obtained at pin 8 is cen-
TRIANGLE OUTPUT (PIN 8) tered about a voltage level Va where:
The output at pin 8 is a triangle wave with a peak swing Va = VB + 0.6V
of approximately one-half of the total supply voltage.
Pin 8 has a very low output impedance of 100 and is in- where VB is the bias voltage at pin 5. The peak-to-peak
ternally protected against short circuits. output swing of triangle wave is approximately equal to
V+/2.
FREQUENCY CONTROL (SWEEP AND FM)
The frequency of operation is proportional to the total
timing current IT drawn from the timing pin, pin 4. This
timing current, and the frequency of operation can be
modulated by applying a control voltage, VC, to the tim-
ing pin, through a series resistor, RS, as shown in Fig-
XR-2209 ure 12. If Vc is negative with respect to VA, the voltage
level at pin 4, then an additional current 10 is drawn
from the timing pin causing IT to increase, thus in-
creasing the frequency. Conversely, making Vc higher
than VA causes the frequency to decrease by decreas-
ing IT-

~-f The frequency of operation, is determined by:

f = fo [1 R Vc R]
+ RS - VA RS
Figure 12. Frequency Sweep Operation where fo = 1/RC.

6-28
XR·2209
r---1-.---------4~----_._1------~--~------~-----~~----------._--_c~ ,

T"'ANGU WAVE
• OUTPUT

Al
A4

4M

TlMlIIIO
IU.,ITCM

.'AI
L-______ ~ __________ 4_----~ __ ~ __ ~O~

•
• I

EQUIVALENT SCHEMATIC DIAGRAM

6-29
 XR-8038
Precision Waveform Generator
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-8038 is a precision waveform generator IC ca-
pable of producing sine, square, triangular, sawtooth
and pulse waveforms with a minimum number of exter-
nal components and adjustments. Its operating fre-
quency can be selected over nine decades of frequen-
cy, from 0.001 Hz to 1 MHz by the choice of external R-
C components. The frequency of oscillation is highly
stable over a wide range of temperature and supply
voltage changes. The frequency control, sweep and
modulation can be accomplished with an external con-
trol voltage, without affecting the quality of the output
waveforms. Each of the three basic waveforms, i.e.,
sinewave, triangle and square wave outputs are avail-
able simultaneously, from independent output termi-
nals. ORDERING INFORMATION
The XR-8038 monolithic waveform generator uses ad- Part Number Package Operating Temperature
vanced processing technology and Schottky-barrier di-
odes to enhance its frequency performance. It can be XR-8038M Ceramic -55°C to + 125°C
readily interfaced with a monolithic phase-detector cir- XR-8038N Ceramic O°C to + 70°C
cuit, such as the XR-2208, to form stable phase-locked XR-8038P Plastic O°C to + 70°C
loop circuits. XR-8038CN Ceramic O°C to + 70°C
XR-8038CP Plastic O°C to + 70°C

FEATURES SYSTEM DESCRIPTION

Direct Replacement for Intersil 8038 The XR-8038 preciSion waveform generator produces
Low Frequency Drift-50 ppm/DC Max. highly stable and sweepable square, triangle and sine
Simultaneous Sine, Triangle and Square-Wave Outputs waves across nine frequency decades. The device
Low Distortion-THD ::::: 1 % time base employs resistors and a capacitor for fre-
High FM and Triangle Linearity quency and duty cycle determination. The generator
Wide Frequency Range-O.001 Hz to 1 MHz contains dual comparators, a flip-flop driving a switch,
Variable Duty-Cycle-2 % to 98 % current sources, a buff~r amplifier and a sine wave
converter. Three identical frequency waveforms are si-
multaneously available. Supply voltage can range from
APPLICATIONS 10V to 30V, or ± 5V with dual supplies.

Precision Waveform Generation Sine, Triangle, Square, Unadjusted sine wave distortion is typically less than
Pulse 0.7%, with Pin 1 open and 8 kO from Pin 12 to Pin 11
Sweep and FM Generation (- VEE or ground). Sine wave distortion may be im-
Tone Generation proved by including two 100 kO potentiometers be-
Instrumentation and Test Equipment Design tween VCC and VEE (or ground), with one wiper con-
Precision PLL Design nected to Pin 1 and the other connected to Pin 12.

ABSOLUTE MAXIMUM RATINGS Frequency sweeping or FM is accomplished by apply-

ing modulation to Pins 7 and 8 for small deviations, or
Power Supply 36V only to Pin 8 for large shifts. Sweep range typically ex-
Power DisSipation (package limitation) ceeds 1000: 1.
Ceramic package 750 mW
Derate above + 25°C 6.0 mW/oC The square wave output is an open collector transistor;
Plastic package 625 mW output amplitude swing closely approaches the supply
Derate above + 25°C 5 mW/oC voltage. Triangle output amplitude is typically 1/3 of the
Storage Temperature Range -65°C to +150°C supply, and sine wave output reaches 0.22 VS.

6-30
 XR·8038
ELECTRICAL CHARACTERISTICS
Test Conditions: Vs = ± sv to ± 1SV, TA = 2SoC, RL = 1 MO, RA = RS = 10 kO, C1 = 3300 pF, S1 closed,
unless otherwise specified. See Test Circuit of Figure 1.

XR-S03SM/XR-S03S XR-S03SC
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage, Vs
Single Supply 10 30 10 30 V
Dual Supplies ±S ±1S ±S ±1S V
Supply Current 12 1S 12 20 mA Vs = ± 10V. See Note 1.
FREQUENCY CHARACTERISTICS (Measured at Pin 9)
Range of Adjustment
Max. Operating Frequency 1 1 MHz RA = RS = SOOO, C1 = 0,
RL = 15 kO
Lowest Practical Frequency 0.001 0.001 Hz RA = RS = 1 MO, C1 =
SOO /LF
Max. FM Sweep Frequency 100 100 kHz
FM Sweep Range 1000:1 1000:1 S1 Open. See Notes 2 and 3.
FM Linearity 0.1 0.2 % S1 Open. See Note 3.
Range of Timing Resistors O.S 1000 O.S 1000 kO Values of RA and RS
Temperature Stability
XR-8038M 20 SO - - - ppm/DC
XR-8038 SO 100 - - - ppm/DC
XR-8038C - - - SO ppm/DC
Power Supply Stability O.OS O.OS %N See Note 4.

•
OUTPUT CHARACTERISTICS
Square-Wave Measured at Pin 9.
Amplitude 0.9 0.98 0.9 0.98 x Vs RL = 100 kO
Saturation Voltage 0.2 0.4 0.2 0.5 V Is ink = 2 mA
Rise Time 100 100 nsec RL = 4.7 kO
Fall Time 40 40 nsec RL = 4.7 kO I
Duty Cycle Adj. 2 98 2 98 %
Triangle/Sawtooth/Ramp Measured at Pin 3.
Amplitude 0.3 0.33 0.3 0.33 x Vs RL = 100 kO
Linearity 0.05 0.1 %
Output Impedance 200 200 0 lout = 5 rnA
Sine-Wave Amplitude 0.2 0.22 0.2 0.22 x Vs RL = 100 kO
Distortion
Unadjusted 0.7 1.5 0.8 3 % RL = 1 MO. See Note 5.
Adjusted 0.5 0.5 % RL = 1 MO
Note 1: Currents through RA ad RS not included. Note 4: 10V :S Vs :S 30Vor ±5V :S Vs :S ± 15V.
Note 2: Vs = 20V, f = 10 kHz, RA = RS = 10kO. Note 5: 81 kO resistor connected between Pins 11
Note 3: Apply sweep voltage at Pin 8. and 12.
(2/3 Vs + 2V) :S Vsweep :S VS

CHARACTERISTIC CURVES
10 J 12
!
! 11
z ~ 10
2 10
o
;:
~ I~~-+-~
~ 01 .--~

~
8... §
1

100
i---I--
--=~
J
z
~ 10 ~ O~ II
'/
~ . I
a
~-
UNADJUSTED
o
Z 09 8 I I 'I~ ADJ~\TLD f--
1\1 I "
~~
10 15 20 2~ JO 10 15 20 25 30 10Hl looHl IkHl 10kHl lookHl IMHl

Supply Voltage Supply Voltage Sinewave THO vs. Frequency

Power Dissipation vs. Supply Voltage Frequency Drift vs. Power Supply

6-31
 XR·8038
...------<1>------<1--_--<1 ·1 ~V
If the duty-cycle is to be varied over a small range
about 50 % only, the connection shown in Figure 2b is
slightly more convenient. If no adjustment of the duty
cycle is desired, terminals 4 and 5 can be shorted to-
gether, as shown in Figure 2c. This connection, how-
ever, carries an inherently larger variation of the duty-
5, XR~038 cycle.

10 11
With two separate timing resistors, the frequency is
given by
C, 81'

L-_~~---4-----<1 -ISV

Figure 1. Generalized Test Circuit

WAVEFORM ADJUSTMENT
or, if RA = RS = R

The symmetry of all waveforms can be adjusted with

f = 0.3/Re (for Figure 2a)
the external timing resistors. Two possible ways to ac-
complish this are shown in Figure 2. Sest results are If a single timing resistor is used (Figures 2b and c), the
obtained by keeping the timing resistors RA and RB frequency is
separate (a). RA controls the rising portion of the trian-
gle and sine-wave and the "Low" state of the square f = 0.15/Re
wave.
The frequency of oscillation is independent of supply
The magnitude of the triangle waveform is set at 1/3 voltage, even though none of the voltages are regulated
Vee: therefore, the duration of the rising portion of the inside the integrated circuit. This is due to the fact that
triangle is: both currents and thresholds are direct, linear function
of the supply voltage and thus their effects cancel.
t1 = e x V =e x 1/3 x Vee x RA = ~ RA x e
I 1/5 x Vee 3
The duration of the falling portion of the triangle and DISTORTION ADJUSTMENT
the sinewave, and the "Low" state of the square wave is:
To minimize sine-wave distortion the 81 kO resistor be-
e x V e x 1/3 Vee 5 RARBe tween pins 11 and 12 is best made a variable one. With
t2 =-- = = - x ---- this arrangement distortion of less than 1 % is achieva-
2 Vee 1 Vee 3 2RA - RS ble. To reduce this even further, two potentiometers can
-x----x--
5 RS 5 RA be connected as shown in Figure 3. This configuration
allows a reduction of sine-wave distortion close to
Thus a 50% duty cycle is achieved when RA = RB. 0.5%

,vee ·vee
,vee

"L "L
"L

fin .nJ1. fin

XR~038 'V'v XR-B038 'V\ XR-B038 'V'v

"" '" ""

Figure 2. Possible Connections for the External Timing Resistors.

6-32
XR·8038 (load resistor connected to + 5 Volts) while the wave-
'Vee form generator itself is powered from a higher supply
voltage.
AA RS Rl
~ FREQUENCY MODULATION AND SWEEP

4
"
5 6
The frequency of the waveform generator is a direct
9f--~nn function of the De voltage at terminal 8 (measured from

[~ XR-8038 J f----<> Vv
+ Vee). Sy altering this voltage, frequency modulation
is performed.

For small deviations (e.g., ± 10%) the modulating sig-

10 II 12 I 2l-o "'"
r->- nal can be applied directly to pin 8 by merely providing
loo.n
ac coupling with a capacitor, as shown in Figure 4a. An
external resistor between pins 7 and 8 is not necessary,
: e but it can be used to increase input impedance. With-
100'S
out it (i.e. terminals 7 and 8 connected together), the in-
-v Of eND
put impedance is 8kO); with it, this impedance in-
creases to (R + 8kO).
Figure 3. Connection to Achieve Minimum Sine-Wave Distortion.
For larger FM deviations or for frequency sweeping, the
SELECTING TIMING COMPONENTS modulating signal is applied between the positive sup-
ply voltage and pin 8 (Figure 4b). In this way the entire
For any given output frequency, there is a wide range of bias for the current sources is created by the modulat-
Re combinations that will work. However certain con- ing signal and a very large (e.g., 1000: 1) sweep range is
straints are placed upon the magnitude of the charging obtained (f = 0 at Vsweep = 0). eare must be taken,
current for optimum performance. At the low end, cur- however, to regulate the supply voltage; in this configu-
rents of less than 0.1 /1-A are undesirable because cir- ration the charge current is no longer a function of the
cuit leakages will contribute significant errors at high supply voltage (yet the trigger thresholds still are) and
temperatures. At higher currents (1 > 5 mA), transistor thus the frequency becomes dependent on the supply
betas and saturation voltages will contribute increas- voltage. The potential on Pin 8 may be swept from Vee
ingly larger errors. Optimum performance will be ob- to 2/3 Vee -2V.
tained for charging currents of 1 /1- to 1 mA. If pins 7 and
8 are shorted together the magnitude of the charging (al
current due to RA can be calculated from:

I = R1 x Vee x J... = Vee

(R1 + R2) RA 5RA

A similar calculation holds for RS'

f M o--J f-*--<".>--I XR-B03B
When the duty cycle is greater than 60%, the device
may not oscillate every time, unless:
10 II 12
1) the rise times of the V + is 1Ox slower than RA·eT'
2) a 0.1 fl.F capacitor is tied from Pin 7 and 8 to ground. alk

NOTE: This is only needed if the duty cycle is powered v or GND

up with RA»RS'

SINGLE-SUPPLY AND SPLIT-SUPPLY OPERATION (bl

The waveform generator can be operated either from a 1

sw fEP
RA
. Ra
: RL

single power-supply (10 to 30 Volts) or a dual power- VOL TACE

4 5 6
supply (± 5 to ± 15 Volts). With a single power-supply 9 ~

L"
the average levels of the triangle and sine-wave are at
exactly one-half of the supply voltage, while the square- J
XR-8038
wave alternates between + Vee and ground. A split
power supply has the advantage that all waveforms 2 f---<:>
move symmetrically about ground. 10 11 12

The square-wave output is not committed. A load resis-

tor can be connected to a different power-supply, as e alk

long as the applied voltage remains within the break- - V 0' eND
down capability of the waveform generator (30V). In this
way, the square-wave output will be TTL compatible Figure 4. Connections for Frequency Modulation (a) and Sweep (b).

6-33
 XR·8038A

Precision Waveform Generator

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-8038A is a precision waveform generator IC ca-
pable of producing sine, square, triangular, sawtooth, SINE ADJ
and pulse waveforms, with a minimum number of exter-
nal components and adjustments. The 8038A allows
the elimination of the external distortion adjusting resis-
tor which greatly improves the temperature drift of dis- M

tortion, as well as lowering external parts count. Its op-

erating frequency can be selected ove:r nine decades r
DUTY CYCLE
of frequency, from 0.001 Hz to 1 MHz, by the choice of ADJ

external R-C components. The frequency of oscillation L

is highly stable over a wide range of temperature and
supply voltage changes. The frequency control, the
sweep, and the modulation can be accomplished with FMBIAS
an external control voltage, without affecting the quali-
ty of the output waveforms. Each of the three basic
waveform outputs, (i.e., sine, triangle and square) are ORDERING INFORMATION
simultaneously available from independent output ter-
minals. Part Number Package Operating Temperature
The XR-8038A monolithic waveform generator uses ad- XR-8038AM Ceramic -55°C to +125°C
vanced processing technology and Schottky-barrier di- XR-8038AN Ceramic O°C to + 70°C
odes to enhance its frequency performance. It can be XR-8038AP Plastic O°C to + 70°C
readily interfaced with a monolithic phase-detector cir- XR-8038ACN Ceramic O°C to + 70°C
cuit, such as the XR-2228 to form stable phase-locked XR-8038ACP Plastic O°C to + 70°C
circuits. SYSTEM DESCRIPTION
FEATURES The XR-8038A precision waveform generator produces
highly stable and sweepable square, triangle, and sine
Low Frequency Drift 50 ppm/DC, Typical waves across nine frequency decades. The XR-8038A
Simultaneous Sine, Triangle, and Square Wave Outputs is an advanced version of the XR-8038, with improved
Low Distortion THD 1 % sine distortion temperature drift. The device time base
High FM and Triangle Linearity employs resistors and a capacitor for frequency and
Wide Frequency Range 0.001 Hz to 1 MHz, Typical duty cycle determination. The generator contains dual
Variable Duty Cycle 2% to 98% comparators, a flip-flop driving a switch, current
Low Distortion Variation with Temperature sources, a buffer amplifier, and a sine wave convertor.
Three identical frequency outputs are simultaneously
APPLICATIONS available. Supply voltage can range from 10V to 30V, or
± 5V to ± 15V with dual supplies.
Precision Waveform Generation
Sweep and FM Generation Unadjusted sine wave distortion is typically less than
Tone Generation 0.7% with the sine wave distortion adjust pin (Pin 1)
Instrumentation and Test Equipment Design open. Distortion levels may be improved by including a
Precision PLL Design 100kO potentiometer between the supplies, with the
wiper connected to Pin 1.
ABSOLUTE MAXIMUM RATINGS Frequency sweeping or FM is accomplished by apply-
ing modulation to Pins 7 and 8 for small deviations, or
Power Supply 36V
only Pin 8 for large shifts. Sweep range typically ex-
Power Dissipation (package limitation)
ceed 1000:1.
Ceramic Package 750 mW
Derate Above + 25°C 6.0 mW/oC The square wave output is an open collector transistor;
Plastic Package 625 mW output amplitude swing closely approaches the supply
Derate Above + 25°C 5 mW/oC voltage. Triangle output amplitude is typically 1/3 of the
Storage Temperature Range -65°C to + 150°C supply, and sine wave output reaches 0.22VS.

6-34
XR·8038A
ELECTRICAL CHARACTERISTICS
Test Conditions: Vs = ± 5V to ± 15V, TA = 25°C, RL = 1 MO, RA = RB = 10 kO, C1 = 3300 pF, S1 closed,
unless otherwise specified.

XR-8038AM XR-8038AC
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage, Vs
Single Supply 10 30 10 30 V
Dual Supplies ±5 ± 15 ±5 ±15 V
Supply Current 12 15 12 20 mA Vs = ± 10V (Note 1)
FREQUENCY CHARACTERISTICS (Measured at Pin 9)
Range of Adjustment
Max. Operating Frequency 1 1 MHz RA = RB = 5000,
C1 = 0, RL = 15 kO
Lowest Practical Frequency 0.001 0.001 Hz RA = RB = 1 MO,
C1 = 500 ILF
Max. FM Sweep Frequency 100 100 kHz
FM Sweep Range 1000:1 1000:1 S1 Open (Note 2 & 3)
FM Linearity 0.1 0.2 % S1 Open (Note 3)
Range of Timing Resistors 0.5 1000 0.5 1000 kO Values of RA and RB
Temperature Stability
XR-8038AM 50 100 - - - ppm/oC TA = -55°C to + 125°C
XR-8038AC 20 ppm/oC TA = O°C to + 70°C
Power Supply Stability 0.05 0.05 %N (Note 4)
OUTPUT CHARACTERISTICS

•
Square-Wave Measured at Pin 9
Amplitude 0.9 0.98 0.9 0.98 x Vs RL = 100 kO
Saturation Voltage 0.2 0.4 0.2 0.5 V Isink = 2 mA
Rise Time 100 100 nsec RL = 4.7 kO
Fall Time 40 40 nsec RL = 4.7 kO
Duty Cycle Adjustment 2 98 2 98 %
Triangle/Sawtooth/Ramp Measured at Pin 3
Amplitude 0.3 0.33 0.3 0.33 x Vs RL = 100 kO
Linearity 0.05 0.1 %
Output Impedance 200 200 lout = 5 mA
Sine-Wave Amplitude 0.2 0.22 0.2 0.22 x Vs RL = 100kO
Distortion
Unadjusted 0.7 1.5 0.8 3 % RL = 1 MO (Note 5 & 6)
Adjusted 0.5 0.5 % RL = 1 MO (Note 5 & 6)
ATHD/AT 0.5 0.3 %

Note 1: Currents through RA ad RB not included.

Note 2: Vs = 20V, f = 10 kHz, RA = RB = 10kO.
Note 3: Apply sweep voltage at Pin 8.
2/3 Vs :::;; Vsweep :::;; VSN.
Note 4: 10V :::;; Vs :::;; 30Vor ±5V :::;; Vs :::;; ± 15V.
Note 5: Pin 12 open circuited (No 81 kO resistor as
standard 8038).
Note 6: Triangle duty cycle set to 50 %, use RA and
RB·

6-35
6-36
 Section 6 - Instrumentation Circuits
Multipliers/Multiplexers . . . . . . . . . . . 6-36
XR-2208 Operational Multiplier 6-38
XR-2228 Monolithic Multiplier/Detector 6-46

6-37
 XR·2208

Operational Multiplier
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-220B operational multiplier combines a four-
quadrant analog multiplier (or modulator), a high fre- V·
quency buffer amplifier, and an operational amplifier in MULTIPLIER
OUTPUTS
a monolithic circuit that is ideally suited for both analog HIGH FREQ.
computation and communications signal processing L OUTPUT

application. As shown in the functional block diagram,

for maximum versatility the multiplier and operational
X
INPUT 1OPAMP
amplifier sections are not internally connected. They INPUTS
COMMON
can be interconnected, with a minimum number of ex- J
ternal components, to perform arithmetic computation, y
INPUT COMPo
such as multiplication, division, square-root extraction.
The operational amplifier can also function as a pre-
amplifier for low-level input signals, or as a post detec-
Y·GAIN
r OPAMP
OUTPUT
tion amplifier for synchronous demodulator applica-
tions. For signal processing, the high frequency buffer
amplifier output is available at pin 15. This multiplier/
l V-

buffer amplifier combination extends the small signal X·GAIN

3-db bandwidth to B-M Hz and the transconductance
bandwidth to 100 MHz.
ABSOLUTE MAXIMUM RATINGS
The XR-220B operates over a wide range of supply volt-
ages, ± 4.5V to ± 16V. Current and voltage levels are Power Supply V + + 1B Volts
internally regulated to provide excellent power supply V- -1B Volts
rejection and temperature stability. The XR-220B oper- Power DiSSipation
ates over a O°C to 70°C temperature range. The XR- Ceramic Package 750mW
220BM is specified for operation over the military tem- Derate above + 25°C 6mW/oC
perature range of - 55°C to + 125°C. Plastic Package 625mW
Derate above + 25°C 5 mW/oC
FEATURES Storage Temperature Range - 65°C to + 150°C

Maximum Versatility ORDERING INFORMATION

Independent Multiplier, Op Amp, and Buffer
Excellent Linearity (0.3 % typ.) Part Number Package Operating Temperature
Wide Bandwidth XR-220BM Ceramic - 55°C to + 125°C
3 dB B.W.-B MHz typo XR-220BN Ceramic . O°C to + 70°C
3° Phase Shift B.W.-1.2 MHz typo XR-220BP Plastic O°C to + 70°C
Transconductance B.W.-100 MHz typo XR-220BCN Ceramic O°C to + 70°C
Simplified Offset Adjustments XR-220BCP Plastic O°C to + 70°C
Wide Supply Voltage Range (± 4.5V to ± 16V)

APPLICATIONS SYSTEM DESCRIPTION

Analog Computation Triangle-to-Sinewave The XR-222B multiplier/detector contains a four quad-
Multiplication Converter rant multiplier and a fully independent operational am-
Division AGC Amplifier pliJier. The four quadrant multiplier has fully differential
Squaring Phase Detector X and Y inputs and outputs. Both inputs have 3 MHz dy-
Square-Root Phase-Locked Loop (PLL) namic response and 100 MHz transconductance band-
Signal Processing Applications width. The operational amplifier features high gain and
AM Generation Motor Speed Control a large common mode range. The device is powered by
Frequency Doubling Precision PLL 4.5V to 16V split supplies.
Frequency Translation Carrier Detection
Synchronous AM Detection Phase-Locked AM For higher frequency applications, consider the XR-
Demodulation 220B.

6-38
XR·2208
ELECTRICAL CHARACTERISTICS
Test Conditions: Supply Voltage = ± 15V, TA = 25°C, unless otherwise specified.

XR-2208/
XR-2208M XR-2208C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS FIGURES CONDITIONS
I. GENERAL
Supply Voltage ±4.5 ±16 ±4.5 ±16 Vdc See Figure 11
Supply Current 4 7 5 8 mA 2 Measured at Pin 16
II. MULTIPLIER SECTION
Non-linearity No external offset trim
(Output Error
in % of Full Scale) 0.3 0.5 0.5 1.0 % 3 Vy = ±10V, -10V < Vx < +10V
0.3 0.5 0.5 1.0 % Vx = ±10V, -10V < V~ < +10V
0.7 1.0 0.8 % TLOW :S TA :S THIGH ( ote 1)
f = 50 Hz
Feedthrough
a) With Offset Adj.
X-input 45 80 70 120 mVp-p Vx = 20 Vp-p "J,
= 0
y..input 60 100 90 150 mVp-p Vy = 20 Vp-p, x = 0
b) No Offset Adj.
X-input 120 200 mVp-p Vx = 20 Vp-p, Vx = 0
y..input 120 200 mVp-p Vy = 20 Vp-p, Vx = 0
Temperature Coefficient of Scale ±0.07 ±0.07 %/oC TLOW :S TA :S THIGH (Note 1)
Factor
Input Bias Current
X, Y input 2 6 3 8 /LA 2 13,15 of Figure 2
Common input 4 12 6 16 /LA 2 14 of Figure 2

•
Input Resistance 0.5 1.0 1.0 MO 2 Measured looking into Pin 3 or
Pin 5
Output Offset Voltage 50 80 80 140 mV 2 Measured across Pins 1 and 2
Avg. Temp. Drift 0.5 0.5 mV/oC TLOW :S TA :S THIGH
Dynamic Response 5 See Definition Section
3-dB Bandwidth
X-input 6 8 6 8 MHz
Y-input 3 4 3 4 MHz
3° Phase-Shift Bandwdith 1.2 1.2 MHz
1 % Absolute Error Bandwidth 30 30 kHz
Transconductance Bandwidth 100 100 MHz
Output Impedance 6 6 kO Measured looking into Pins 1 or 2

III. BUFFER AMPLIFIER

Output Impedance 200 200 0 5 Measured looking into Pin 15
Gain 1.0 1.0
IV. OPERATIONAL AMPLIFIER
Input Offset Voltage 1 3 2 6 mV 6 RS < 500
Temperature Coefficient of Input 6 20 9 30 /LV/oC TLOW :S TA :S THIGH
Offset Voltage
Input Offset Current 4 75 10 100 nA 6 IB1- IB2
IB1 + IB2
Input Bias Current 30 200 50 300 nA 6
2
Voltage Gain 70 75 70 75 dB 6 RL ~ 2K, Va = ± 10V, f = 20 Hz
Differential Input Resistance 0.5 3 3 MO 6
Output Voltage Swing ±10 ±12 ±10 ±12 V RL ~ 2K, TLOW :S TA :S THIGH
Input Common + 12 +14 +12 +14
Mode Range -10 -12 -10 -12 V 6
Common Mode Rejection 70 90 70 90 dB 6 f = 20 Hz
Output Resistance 2 2 kO 6
Slew Rate 0.5 0.5 V//LS 7 Gain = 1, RL ~ 2K CL :S 100 pF
Cc = 20 pF
Power Supply Sensitivity 30 30 /LVN 6 RS :S 10K

Note 1: TLOW = -55°C,THIGH = +125°CforXR-2208M TLOW = O°C, THIGH = + 70°C for XR-2208/XR-2208C
CAUTION: When using only the op amp or only the multiplier section of the XR-220B, the input terminals to the unused
section must be grounded. Thus, when using the multiplier section alone, ground pins 13 and 14; when using
the op amp section a/one, ground pins 3, 4 and 5.

6-39
 XR·2208

5fK 5 fK ·\5V

Figure 1. Test Circuit for Quiescent Supply Current,

Multiplier Input Bias and Output Offset Voltage. Figure 4. Test Circuit for Multiplier Smail-Signal Bandwidth
for X-Input (For Y-Input, reverse connections
between Pin 3 and 5).

,R lXl8
'II
- 1\

v,~ ---,,-o-:'~lI-~
'I'

'0

ISV

Figure 2. Linearity Test Circuit Flgu~e 5. Test Circuit for Op Amp DC Parameters

Figure 3. Test Circuit for Feedthrough Measurement.

X-Input Feedthrough = Vz with S1, open, S2 closed. Figure 6. Op Amp AC Test Circuit
Y-Input Feedthrough = Vz with S1, closed, S2 open.
plier with scale factor K can be written as:
DEFINITION OF MULTIPLIER TERMS
Vz = K[(Vx + tPx) (Vy + tPy)] + tPo
NONLINEARITY: Nonlinearity is the maximum deviation
of the output voltage from a straight-line transfer func- where cJ>x and cJ>y are the offset voltages associated with
tion. It is measured separately for the X and Y inputs the respective inputs, cJ>0 is the offset voltage of the out-
and is specified as (%) of full scale output. put, Vz is the multiplier output, Vx and Vv are the multi-
plier inputs. As shown in Figures 13 and 14, each of
FEEDTHROUGH: The amount of peak-to-peak output volt- these offset voltages can be nulled to zero by external
age present with one input grounded and a specified adjustments.
peak-to-peak input applied 10 the other input. Feed-
through is a function of multiplier offsets and can be SCALE FACTOR, K: The constant of proportionality that
minimized by offset adjustment (see Figure 13). relates the multiplier output to the X and Y inputs. If the
offset terms are neglected, the multiplier output, Vz, is
OFFSET VOLTAGES: A four-quadrant analog multiplier has related to the X and Y inputs as Vz = K(Vx·Vy). The
three separate offsets: the X and Y input offsets and the scale factor K has the dimensions of (volts) - 1 and can
output offset. The transfer function of a practical multi- be adjusted externally.

6-40
 XR·2208
TYPICAL CHARACTERISTIC CURVES
5mA~----~----~----~ 10,.----,----r------r----, 1,00

<I 4mA 0,7!

e

la 3mA 0.50

r-- -
)0

! ,., ---::.::~~- - - -20 0.25 --

I mA'L..4v-----.~8V~----'1~2V~--~!1eV o
-5b -25 0 -25 +50 -75 +100 .,25
SUPPl V VOL TArlE, VOLTS FREOUENCV IMH.I TA' I\MBIENT TEMPE~ATURE I'CI
Figura 7. Supply Current vs Supply Figure 8. Smail-Signal Frequency Figure 9. Temperature Dependence of
Voltage Response for the Multiplier Section. Output Nonlinearity for X or Y Inputs
(Output Measured at Pin 15-See (See Figure 2).
Fig. 4).
+1S ,..------r-----.....,.-----, l00,..----,----r---~--~

......
8 -.
10 t==:r::~~~-.-_I_--~
5> • --~
! So~--~--~~~
d z
~ ~ 40~--~~--r_--~~·--;
~
!
-4 ---
~
~ 20 ~...,.._f_--r_--+-...~
~ ·-8

•
~
-12

-ISO~-------'b~V-----\~,0V-:----~.
1SV 100 H. 10 kHz 100 kHz
·8 .8 . 10 '12 '14 'IS
SUPPLY VOL TAG~,VOL TS SUPPl v VOL lAGE. VOL TS FREOUENCY

Figure 10. Multiplier Input Dynamic Figure 11. Op Amp Output Swing vs Figure 12. Op Amp Frequency
Range vs Power Supply Powor Supply Response

In most arithmetic applications the multiplier and op

amp sections of the XR-2208 are interconnected as
shown in Figure 14. In such applications, over-all scale
factor K can be written as:
x
K = (Km)(Ka) = (~)
VxY
(Vz)
Vo
"x
y
where Km is the gain constant of the multiplier section,
and Ka Is the gain of the op amp stage In Figure 14, Vo
Figure 13. Offset Adjustment
Is the multiplier output across pins 1 and 2, and Vz is
the op amp output at pin 11. With reference to Figure MULTIPLIER BANDWIDTH: Depending on the particular
14, these gain constants can be expressed as: application, a different definition of "multiplier band·
width" may be used. The most commonly accepted
Km::: ~(volts)-1; Ka::: _R_f_ definitions are:
RxRy 6 + RI
a) 3·dB BandwIdth: Frequency where the multiplier
where all resistors are in kO. output is 3-dS below Its low frequency (f = 20 Hz)
level.
Thus, overall scale factor K can be adjusted by varying
Rx, Ry, Rf. For fine adjustment of the scale factor, K, an b) 3° Phase Shift Bandwidth: Frequency where the net
additional potentiometer can be included Into the cir- phase shift across the multiplier is equal to 3°.
cuit, as shown in Figure 14.
c) 1% Absolute Error Bandwidth: Frequency where
INPUT DYNAMIC RANGE: The maximum peak signal the phase vector error between the actual and ideal
which can be applied to the X or Y inputs for a given output vectors is equal to 1 %. This frequency is
supply voltage without impairing linearity. (See Figure reached when the net phase shift across the mUlti-
10). plier is equal to 0.01 radian or 0.57°.

6-41
 XR·2208
d) Transconductance Bandwidth: Frequency where OP AMP INPUTS (PINS 13 AND 14)
the transconductance of the multiplier drops 3-d8
below its low frequency value. This bandwidth de- Pin 13 is the non-inverting and pin 14 the inverting in-
fines the frequency range of operation for phase- puts for the op amp section. In most multiplier applica-
detector and synchronous AM detector applications. tions, these terminals are connected to the multiplier
outputs (pins 1 and 2). Note: When the op amp section is not
DESCRIPTION OF CIRCUIT CONTROLS used, these terminals should be grounded.

MULTIPLIER INPUTS (PINS 3, 4, AND 5) OP AMP COMPENSATION (PIN 12)

The X and Y inputs to the multiplier are applied to pins 3 The op amp section can be compensated for uncondi-
and 5 respectively. The third input (pin 4) is common to tional stability with a 20 pF capacitor connected be-
both X and Y portions of the multiplier, and in most ap- tween pin 12 and pin 11. For op amp voltage gains
plications serves as a "reference" or ground terminal. greater than unity, this compensation capacitance can
The typical bias current at the multiplier inputs is 3 p.A be reduced to improve slew rate and small signal band-
for the X- and Y- inputs and 6 p.A for the "common" ter- width as shown in Figure 12.
minal. In circuit applications such as "synchronous AM
detection" or "frequency doubling" where the same in- OP AMP OUTPUT (PIN 11)
put signal is applied to both X and Y inputs, pin 4 can be
used as the input terminal since it is common to both X This terminal serves as the output for the op amp sec-
and Y sections of the multiplier. tion. It is internally protected against aCCidental short
circuit conditions, and can sink or source 10 mA of cur-
MULTIPLIER OUTPUTS (PINS 1 AND 2) rent into a resistive load. In most multiplier applications,
pin 11 is the actual XR-2208 output, with the op amp in-
The differential output voltage, Yo, across these termi- puts being connected to the multiplier outputs.
nals is proportional to the linear product of voltages Vx
and Vy applied to the inputs. Vo can be expressed as: BUFFER AMPLIFIER OUTPUT (PIN 15)

(R~~y) (VXvy)
The buffer amp is internally connected to the multiplier
Vo = section. The buffer amp has unity voltage gain, and pro-
vides a low-impedance output at pin 15 for the multipli-
er section. The buffer amp is particularly useful for high
where all voltages are in volts and the resistors are in
frequency operation since it minimizes the capacitive
kO. Rx and Ry are the gain control resistors for X and Y
loading effects at the multiplier outputs.
sections of tne multiplier.
The buffer amplifier is activated by connecting a load
The common-mode dc potential at the multiplier out-
resistor, R1, from pin 15 to ground. When it is not used,
puts is approximately 3 volts below the positive supply.
pin 15 can be left open circuited. However, since the
One of the multiplier outputs (pin 1) is internally con-
buffer amplifier output is a low impedance point, rea-
nected to the unity-gain buffer amplifier input for high-
sonable care should be taken to avoid burnout due to
frequency applications.
accidental short circuits. The maximum dc current
In most analog computation operations, such as mUlti- drawn from pin 15 should be limited to 10 mAo The dc
plication, division, etc., pins 1 and 2 are dc coupled to voltage at pin 15 is typically 4.5 volts below V + .
the op amp inputs (pins 13 and 14). The final output, Vz,
is then obtained from the op amp output at pin 11, as APPLICATIONS INFORMATION
shown in Figure 14.
PART I: ARITHMETIC OPERATIONS
X AND Y GAIN ADJUST (PINS 6, 7, 8, 9)
MultlpllcatJon
The gains of the X and Y sections of the multiplier are
inversely proportional to resistors Rx and Ry connected For most multiplication applications, the multiplier and
across the respective gain terminals. Tlie multiplier op amp sections are interconnected as shown in Figure
conversion gain, Km , can be expressed as: 15 to provide a Single-ended analog output with a wide
dynamic range. The circuit of Figure 14 provides a lin-
K,..., == ~ (volts) - 1 ear output swing of 10V for maximum input signals of
'" RxRy 10V, with a scale factor K = 0.1. The trimming proce-
dure for the circuit is as follows:
where Rx and Ry are in kO.

X AND Y OFFSET ADJUST (PINS 7 AND 8) 1. Apply OV to both inputs and adjust the output offset
to OV using the output offset control.
Two of the gain-control terminals, pins 7 and 8, are also
used for adjusting X and Y offsets. Figure 13 shows the 2. Apply 20V pop at 50 Hz to the X-input and OV to the
typical adjustment circuitry which can be connected to V-input. Trim the Y-offset adjust for minimum peak-to-
these pins to null-out input offsets. peak output.

6-42
XR·2208
3. Apply 20V pop to the Y-input and OV to the X-input. Dividing Circuit
Trim X-offset adjust for minimum peak-to-peak out-
put. Recommended circuit connection for performing ana-
log division is shown in Figure 16. This circuit uses the
4. Repeat step 1. multiplier in the feedback path of the op amp. For the
circuit shown, Va = + 10 VzN x where Vx < 0 and Vz
5. Apply + 10V to both inputs and adjust scale factor can have either sign. Positive values of Vx are not al-
for Va = + 10V. This step may be repeated with dif- lowed, since this will reverse the polarity of the feed-
ferent amplitudes and polarities of input voltages to back loop, causing positive feedback and latchup.
optimize accuracy over the entire range of input
voltages, or over any specific portion of input volt- This latchup mode is nondestructive to the XR-2208,
age range. and is common to all analog division circuits. The divide
circuit is trimmed as follows:
Squaring Circuit
1. Apply Vz = 0 and trim the output offset adjustment
The recommended circuit connection for squaring ap- for constant output voltage as Vx is varied from -1V
plications is shown in Figure 15. This circuit is the same to -10V.
as the basic multiplier circuit with both inputs tied to-
gether, except only one input offset adjustment is nec- 2. Keeping Vz = 0, and applying Vx = -10V, trim the
essary. Trimming procedure for the squaring circuit is Y-offset adjust until Va = O.
as follows:
3. Let Vz = Vx and/or Vz = -Vx and trim the X-offset
1. Apply 0 volts to the input and adjust the output offset adjustment for constant output voltage as Vx is var-
to zero. ied from -1V to -10V.

2. Apply 1.0V to the input and adjust the Y-offset until 4. Repeat steps 1 and 2 if step 3 required a large initial
Va = O.10V. adjustment.

3. Apply 10V to the input and adjust the scale factor 5. Keeping Vz = Vx , adjust the scalo factor trim for Va

•
until Va = + 10V. -10V as Vx is varied from -lV to -10V.

4. Apply - 10V to the input and check that Va= + 10V.

If not, repeat steps 1 through 3. Some compromise
may be necessary in scale factor adjustments given
in steps 3 and 4.

"1
...OC'Olli
,.
Figure 16. Dividing Circuit

Square Root Circuit

This is essentially the dividing circuit with the X input

Figure 14. Multiplication Circuit tied to the output. Thus, the voltage on the Z input is di-
vided by the output voltage, i.e. the output is proportion-
al to the square root of the input. A diode is included in
series with the output to prevent a latchup condition
which would result if Vz were allowed to go negative.
The square root circuit may be trimmed as a divider by
disconnecting the X-input from the output, keeping Vz
> 0 and Vx < O. The square root circuit may also be
trimmed in the closed-loop mode by the following pro-
cedure:

1. Apply Vz = + 0.1 OV and trim the output offset adjust

for Va = -0.316V.

2. Apply Vz = + 0.9V and trim the X-offset adjust for

Figure 15. Squaring Circuit Va = -3.0V.

6-43
 XR·2208
3. Apply Vz = + 10V and trim the scale factor adjust SYNCHRONOUS AM DETECTION
for Vo = -10V.
Figure 18 is a typical circuit connection for synchro-
4. Repeat steps 1 through 3 until desired accuracy is nous AM detection for carrier frequencies up to 100
achieved. MHz. The AM input signal is applied to the multiplier
"common" terminal (pin 4). The '{-gain terminals are
EQUIVALENT SCHEMATIC DIAGRAM shorted, and this section of the multiplier serves as a
"limiter" for input signals ~ 50 mVrms; the X-section of
the multiplier operates in its linear mode. The low-pass
filter capacitors, C1, at pins 1 and 2 are used to filter
the carrier feedthrough. If desired, the op amp section
can be used as an audio preamplifier to increase the
demodulated output amplitude.

TRIANGLE-TO-SINEWAVE CONVERSION

PART II: SIGNAL PROCESSING A triangular input can be converted into a low distortion
(TH D < 1 %) sinusoidal output with the XR-2208. A rec-
AM GENERATION ommended connection for this application is shown in
Figure 19. The triangle input signal is applied to the
Figure 17 is the recommended circuit connection for X-input (pin 3). The multiplier section rounds off the
generating double side-band (DSB) or suppressed carri- peaks of this input and converts it to a low distortion
er AM signals. Modulation and carrier inputs are ap- sine wave. For the component values shown in Figure
plied to the X and Y inputs respectively. The carrier lev- 19, the recommended input signal level at pin 3 is =
el at the output can be adjusted by the dc voltage ap- 300 mV pp in order to obtain a 2V pp sine wave output
plied to pin 3. For suppressed carrier operation, the at pin 15. This waveform can be further amplified using
carrier feedthrough can be further reduced by using the the op amp section to provide high level (10V pp), low
X and Y offset adjustments. In this application, the distortion output at pin 11.
unity-gain buffer amplifier section will provide a low im-
pedance output if desired. If the buffer amp is not used,
pin 15 should be open circuited to reduce power dissi-
pation.

Typical carrier suppression without offset adjustment is

40 dB for frequencies up to 1 MHz, and 30 dB for fre-
quencies up to 10 MHz. For low frequency applications
(f < 10 kHz), carrier suppression can be reduced to
60 dB by using the offset adjustment controls.

o-f,--~~--,

MO~~:'O'" Cc

o-f,-~""",_--,
Figure 19. Triangle-to-Sine Converter
~::~1: " '--;;t+.8:'--~
PHASE DETECTION

The multiplier section can be used as a phase detector.

A recommended circuit connection is shown in Figure
Figure 17. AM Generation 20. The reference input is applied to pin 5, and the input
signal whose phase is to be detected is applied to pin 3.
The differential dc voltage, VrjJ, at the multiplier outputs
(pins 1 and 2) is related to the phase difference, rjJ, be-
tV'w'cen the t'lJO input signals, VI and V2, as:

VrjJ = Kd cos rjJ

where Kd is the phase detector conversion gain. For in-

put signals ~ 50 mV rms, Kd is "" 2V/radian and is inde-
pendent of signal amplitude. For lower input ampli-
tudes, Kd decreases linearly with the decreasing input
level. The capaCitors C1 at pins 1 and 2 provide a low-
pass filter with a time constant T 1 = R1 C1, where R1
Figure 18. Synchronous AM Detector. = 6 kO is the internal impedance level at these pins.

6-44
XR·2208
If needed, the phase conversion gain can be increased
by using the op amp section of the XR-2208 to further
amplify the output voltage, V¢. The XR-2208 is suitable
for phase detection for input frequencies up to 100
MHz.

IV\

v. OUTPUT

' - - - - - - - - - - - - - - -.......IVV--o "2

INPUT I
VI - E, sin (Will
(REFERENCE INPUT)
~SOmV.rms.
Figure 22_ Precision PLL
Figure 20. Phase-Detector Circuit
PHASE-LOCKED AM AND CARRIER DETECTION
PART III: PHASE-LOCKED LOOP APPLICATIONS
The XR-2208 can be used as a "quadrature detector" in
MOTOR SPEED CONTROL conjunction with monolithic PLL circuits to perform
phase-locked AM demodulation and for carrier-level de-
A motor speed control where the frequency of the mo- tection. Figure 23 shows a recommended circuit con-
tor is "phase-locked" to the input reference frequency, nection for such applications. The XR-210 or XR-215
fr, is shown in Figure 21. The multiplier section of the monolithic PLL circuits can be adjusted to lock on the
XR-2208 is used as a phase-comparator, comparing the desired input AM signal and re-generate the unmodulat-
phase of the tachometer output signal with the phase of ed carrier. This carrier frequency appears across the
the reference input. The resulting error voltage across timing capacitor, Co, of the PLL and is used as the "ref- 6
pins 1 and 2 is low-pass filtered by capacitors C1 and erence input" to the XR-2208 multiplier. The AM Signal
amplified by the op amp section. This error signal is is applied simultaneously to the PLL input and to the
then applied to the motor field-winding to phase-lock XR-2208 multiplier input (pin 3), as shown in Figure 23.
the motor speed to the input reference frequency.
The demodulated signal is then low-pass filtered by ca-
paCitor C1 at the multiplier output, and can be amplified
further to the desired audio level by using the op amp
section of the XR-2208.

In the carrier detector applications, the op amp is used

as a voltage comparator and produces a "high" or
"low" level logic signal at the op amp output when the
input carrier level reaches a detection threshold level
set by an external potentiometer. The output from the
carrier detector can then be used to enable the "logic-
output" stage of the XR-210 FSK modem.

The phase-locked AM or carrier detector system of Fig-

ure 23 shows a high degree of frequency selectivity, as
Figure 21_ Motor Speed Control Circuit determined by the monolithic PLL "capture" band-
width.
PRECISION PLL

A precision phase-locked loop may be constructed us-

ing an XR-2207 voltage controlled oscillator and an
XR-2208. (See Figure 22.) Due to the excellent tempera-
O'~~
ture stability and wide sweep range of the XR-2207 this .111-"0
".
PLL circuit exhibits especially good stability of center
frequency and wide lock range. In this application the
XR-2208 serves as a phase comparator and level shift-
er. Resistor RL adjusts the loop gain of the PLL, thus
varying the lock range. Tracking range may be varied Cc·CouPlIJrHlC*'AClto",
c,""".55("""'(1'01il

from about 1.5:1 up to 12:1. For large values of RL, tem-

perature stability of center frequency is better than Figure 23. Phase-Locked AM Demodulation Dr Carrier
30 ppm/cC. Detection

6-45
 XR-2228

Monolithic Multiplier/Detector
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2228 is a monolithic multiplier/detector circuit
especially designed for interfacing with integrated MUl TlPllER MUl TlrLlE R
OUTPUT OUTPUT
phase-locked loop (PLL) circuits, to perform synchro-
nous AM detection and triangle-to-sinewave conver- I 2 -Vee
sion. It combines a four-quadrant analog multiplier (or MUl TIPLIER
X·INPUlS
modulator) and a high-gain operational amplifier in a
L 3
single monolithic circuit.

As shown in the equivalent schematic diagram, the MUl TIPLIr R

Y·INPUTS
four-quadrant multiplier section is designed with fully
differential X- and Y-inputs and differential outputs. For
L_ 5 eOMP

maximum versatility, the multiplier and the operational OP AMP

amplifier sections are not internally connected. The op- Y·CAIN
OUTPUT

erational amplifier can also function as a pre-amplifier

'VEE
for low·level input signals, or as a post-detection ampli-
fier for synchronous demodulation, phase-detection or
X-CAIN
for sine-shaper applications.

FEATURES
Independent Multiplier and Op Amp Sections
Differential X and Y Inputs
Interfaces with all PLL and VCO Circuits
Wide Common Mode Range ORDERING INFORMATION
Wide Transconductance Bandwidth (100 MHz, Typ.)
Wide Supply Voltage Range (± 4.5V to ± 16V) Part Number Package Operating Temperature

XR-2228M Ceramic - 55°C to + 125°C

XR-2228N Ceramic - 40°C to + 85°C
APPLICATIONS XR-2228P Plastic -40°C to +85°C
XR-2228CN Ceramic O°C to + 70°C
Phase-Locked Loop Design XR-2228CP Plastic O°C to + 70°C
Phase Detection
Synchronous AM Detection
AM Generation
Triangle-to-Sinewave Conversion
Frequency Translation SYSTEM DESCRIPTION
The XR-2228 multiplier/detector contains a four quad-
rant multiplier and a fully independent operational am-
ABSOLUTE MAXIMUM RATINGS plifier. The four quadrant multiplier has fully differential
X and Y inputs and outputs. Both inputs have 3 MHz dy-
Power Supply ± 18 Volts namic response and 100 MHz transconductance band-
Power Dissipation width. The operational amplifier features high gain and
Ceramic Package 750mW a large common mode range. The device is powered by
Derate above + 25°C 6 mW/oC 4.5V to 16V split supplies.
Plastic Package 625 mW
Derate above +25°C 5 mW/oC For higher frequency applications, consider the XR-
Storage Temperature Range - 65°C to + 150°C 2208.

6-46
XR·2228
ELECTRICAL CHARACTERISTICS
Test Conditions: Supply Voltage = ± 15V, TA = 25°C, unless otherwise specified.
XR-2228M XR-2228/XR-2228C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS FIGURES CONDITIONS
I. GENERAL
Supply Voltage ±4.5 ±16 ±4.5 ±16 V dc See Figure 11
Supply Current 4 7 5 8 mA 1 Measured at Pin 15
II. MULTIPLIER/MODULATOR SECTION
Non-linearity No external offset trim
(Output Error in % of 0.3 0.5 0.5 1.0 % 2 Vy = ±10V, -10V < Vx <
Full Scale) +10V
0.3 0.5 0.5 1.0 % Vx = ±10V, -10V < Vy <
+10V
0.7 1.0 0.8 % how ::5 TA ::5 THIGH (Note 1)
f = 50 Hz
Feedthrough
a. With Offset Adj.
X-input 45 80 70 120 mVp-p 3 Vx = 20 Vp-p Vy =0
Y-input 60 100 90 150 mVp-p Vy = 20 Vp-p, Vx =0
b. No Offset Adj.
X-input 120 200 mVp-p Vx = 20 Vp-p, Vx = 0
Y-input 120 200 mVp-p Vy = 20 Vp-p, Vx = 0
Temperature Coefficient ±0.07 ±0.07 %IOC TLOW ::5 TA ::5 THIGH (Note 1)
of Scale Factor
Input Bias Current
X or Y inputs 2 6 3 8 J.l.A 1 Measured at Pins 2, 3, 4 or 5.
Input Resistance 0.5 1.0 1.0 MO 2 Measured at Pins 2, 3, 4 or 5.
Output Offset Voltage 50 80 80 140 mV 2 Measured across Pins 1 and 16

•
Avg. Temp. Drift 0.5 0.5 mV/oC TLOW ::5 TA s THIGH
Dynamic Response 4 See Definition Section
3-dB Bandwidth
X-input 1 3 1 3 MHz
Y-input 1 3 1 3 MHz
3° Phase-Shift 1 1 MHz
Bandwidth
1 % Absolute Error 30 30 kHz
Bandwidth
Transconductance 100 100 MHz
Bandwidth
Output Impedance 5 5 kO Measured looking into Pins 1
or 16
III. OPERATIONAL AMPLIFIER SECTION
Input Offset Voltage 1 3 2 6 mV 5 RS < 50n
Temp. Coef. of Input 6 20 9 30 J.l.V/oC how s TA ::5 THIGH
Offset Voltage
Input Offset Current 4 75 10 100 nA 5 IB1 - IB2
Input Bias Current 30 200 50 300 nA 5 IB1 + IB2
2
Voltage Gain 70 75 70 75 dB 5 RL ~ 2K, Vo = ±10V,
f = 20 Hz
Differential Input 0.5 3 3 MO 5
Resistance
Output Voltage Swing ±10 ±12 ±10 ±12 V RL ~ 2K, TLOW s TA
s THIGH
Input Common Mode +12 +14 +12 +14
Range -10 -12 -10 -12 V 5
Common Mode Rejection 70 90 70 90 dB 5 f = 20 Hz
Output Resistance 2 2 kO 5
Slew Rate 0.5 0.5 V/J.l.s 5 Gain = 1, RL ~ 2K,
CL s 100 pF Cc = 20 pF
Power Supply Sensitivity 30 30 J.l.VIV 5 RS s 10K
Note 1: TLOW = -55°C, THIGH = + 125°C for XR-2228M TLOW = O°C, THIGH = + 70°C for XR-2228C
TLOW = - 40°C, THIGH = + 85°C for XR-2228
CAUTION: When using only the op amp or only the multiplier section of the XR-2228, the input terminals to the
unused section must be grounded. Thus, when using the multiplier section alone, ground pins 13 and
14; when using the op amp section alone, ground pins 2, 3, 4 and 5.

6-47
 XR·2228

1....- - - - - - MUL TlPLIER ------.~I

EQUIVALENT SCHEMATIC DIAGRAM

6-48
XR·2228 +lIV .15V

0,'

ao,F
"OKt f '0;' :0.'
11°','
'OK
CE.'
'0':. V02

I"K I,'K

Figure 1. Test Circuit for Quiescent Supply Current, Figure 4. Tast Circuit for Multlpllar Smail-Signal Bandwidth
Multiplier Input Bias and Output Offset Voltage for X-Input (For V-Input, ravarse connactlons
batwaen Pins 2 and 5)

I.

~-----+~4r--~~--OVO

'B' 13

ADJUST ICALE
fACTOR FOR NULL IN EO
FOR EACH 'OllTlON OF S,

it:::,'

•
EO
LINEARITY. '1\ ERROR' :~

Figure 2. Llnaarlty Tast Circuit Figura 5. Tast Circuit for Op Amp DC Parameters
2CK

2QpF VZ

Figure 3. Tast Circuit for Faadthrough Measurement. X-Input Figura 6. Op Amp AC Tast Circuit
Feedthrough = Vz with S1, opan S2 closad.
V-Input Faadthrough = Vz with S1 closad, S2
opan.
DEFINITION OF MULTIPLIER TERMS OFFSET VOLTAGES: A four-quadrant analog multiplier
has three separate offsets: the X and Y input offsets
NONLINEARITY: Nonlinearity is the maximum deviation and the output offset. The transfer function of a practi-
of the output voltage from a straight-line transfer func- cal multiplier with scale factor K can be written as:
tion. It is measured separately for the X and Y inputs
and is specified as (%) of full scale output. Vz = K[(V x + CPx) (Vy + cPy)] + CPo

FEEDTHROUGH: The amount of peak-to-peak output volt- where CPx and CPy are the offset voltages associated
age present with one input grounded and a specified with the respective inputs, CPo is the offset voltage of
peak·to-peak input applied to the other input. Feed- the output. Vz is the multiplier output, Vx and Vy are the
through is a function of multiplier offsets and can be multiplier inputs. As shown in Figures 13 and 14, each
minimized by offset adjustment (see Figure 13). of these offset voltages can be nulled to zero by exter-
nal adjustments.

6-49
TYPICAL CHARACTERISTICS CURVES
XR·2228
5 mA r----,----,c------, 10 1.00

0.75

-10
~ ~INPUT

0.50

YINPUT~ """- r--

-
2mA t - - - - j - - - j - - - - j -20 0.25

1 mA'';::.VC---~'8:-:-V---:'12:::-:V--~'16V
-30 o
0.1 1.0 10 100 1000 -55 -25 0 +25 +50 +75 .100 +125
SUPPL y VOLTAGE, VOL TS FREOUENCV (MHz) T A • AMBIENT TEMPERATURE (~CI

Figure 7. Supply Current vs Supply Figure 8. Small·Signal Frequency Figure 9. Temperature Dependence of
Voltage Response for the Multiplier Output Nonlinearity for X or
Section. (Output Measured Y Inputs (See Figure 2)
at Pin 16-See Fig. 4)

12 +15 100
./ Cc ',
L~
R1 ' O. 0
./ +10 ........
80
V in
./ ~ / l "
""./
~

"z
+5

V
!
z
;;
60
R1 '

R1 '
son.cc' 0

sooulc c , 2.5nF
""-
~
~ ../
~ 40

~ c~ ~
........... PEAK·TO PEAK

~ ~

"
OUTPUT SWING R1 ' SK '5pF
6 -5 ~
"..
20

-12
'I'-.. I"-- -10 ""' .......
"--
R1 '-.C}' 20pF

-IS
,2 •• '6 ,8 '10 '12 '14 .16
-15
o ,5V ,10V !15V 100Hz
I 10kHz 100kHz
"1 MHz

SUPPLY VOLTAGE.VOL TS SUPPLY VOLTAGE. VOLTS FREQUENCY

Figure 10. Multiplier Input Dynamic Figure 11. Op Amp output Swing vs Figure 12. Op Amp Frequency
Range vs Power Supply Power Supply Response

XR-2228 related to the X and Y inputs as Vz = K (Vx . Vy). The

x scale factor K has the dimensions of (volts) - 1 and can

be adjusted externally.

In most arithmetic applications the multiplier and op

amp sections of the XR·2228 are interconnected as
shown in Figure 14. In such applications, over-all scale
factor K can be written as:

,.-.......-.., v OFFSET
AOJ
lOOK
75K

XOFFSET where Km is the gain constant of the multiplier section,

ADJ lOOK and Ka is the gain of the op amp stage in Figure 14. Vo
is the multiplier output across pins 1 and 16, and Vz is
the op amp output at pin 11. With reference to Figure
v
14, the gain constants can be expressed as:
Figure 13. Offset Adjustment
where C/>X and C/>V are the offset voltages associated with 25 . Rf
the respective inputs, c/>o is the offset voltage of the out· Km == - - (volts)- I; Ka ==--
put. Vz is the multiplier output, Vx and Vy are the mUlti- RxRy 6 + Ri
plier inputs. As shown in Figures 13 and 14, each of
these offset voltages can be nulled to zero by external where all resistors are in kilo·ohms.
adjustments.
Thus, overall scale factor K can be adjusted by varying
SCALE FACTOR, K: The constant of proportionality that Rx , Ry, Rf. For fine adjustment of the scale factor, K, an
relates the multiplier output to the X and Y inputs. If the additional potentiometer can be included into the cir-
offset terms are neglected, the multiplier output, Vz , is cuit, as shown in Figure 14.

6-50
XR·2228 XAND Y GAIN ADJUST (PINS 6, 7, 8, 9): The gains of the X
INPUT DYNAMIC RANGE: The maximum peak signal
which can be applied to the X or Y inputs for a given and Y sections of the multiplier are inversely propor-
supply voltage without impairing linearity. (See Figure tional to resistors Rx and Ry connected across the re-
10). spective gain terminals. The multiplier conversion gain,
Km , can be expressed as:
MULTIPLIER BANDWIDTH: Depending on the particular
application, a different definition of "multiplier band- Km == ~ (volts) - 1
width" may be used. The most commonly accepted RxRy
definitions are:
where Rx and Ry are in kO.
a) 3-dB Bandwidth: Frequency where the multiplier
output is 3-dB below its low frequency (f = 20 Hz) X AND Y OFFSET ADJUST (PINS 7 AND 8): Two of the gain-
level. control terminals, pins 7 and 8, are also used for adjust-
ing X and Y offsets. Figure 13 shows the typical adjust-
b) 3° Phase Shift Bandwidth: Frequency where the net ment circuitry which can be connected to these pins to
phase shift across the multiplier is equal to 3°. nUll-out input offsets.
c) 1 % Absolute Error Bandwidth: Frequency where the OP AMP INPUTS (PINS 13 AND 14): Pin 13 is the noninvert-
phase vector error between the actual and ideal out- ing and pin 14 the inverting inputs for the op amp sec-
put vectors is equal to 1 %. This frequency is tion. In most multiplier applications, these terminals are
reached when the net phase shift across the multi- connected to the multiplier outputs (pins 1 and 16).
plier is equal to 0.01 radian or 0.57°. Note: When the op amp section Is not used, these terminals
should be grounded_
d) Transconductance Bandwidth: Frequency where the
transconductance of the multiplier drops 3-dB below OP AMP COMPENSATION (PIN 12): The op amp section
its low frequency value. This bandwidth defines the can be compensated for unconditional stability with a
frequency range of operation for phase-detector and 20 pF capacitor connected between pin 12 and pin 11.
synchronous AM detector applications. For op amp voltage gains greater than unity, this com-
pensation capacitance can be reduced to improve slew
DESCRIPTION OF CIRCUIT CONTROLS rate and small signal bandwidth as shown in Figure 12.
MULTIPLIER INPUTS (PINS 2, 3, 4 AND 5): These four ter-
minals provide the differential inputs to the X- and
'{-sections of the multiplier, respectively. The output will
be a linear product of the two voltages, Vx and Vy, ap-
OP AMP OUTPUT (PIN 11): This terminal serves as tt16
output for the op amp section. It is internally protected
against accidental short circuit conditions, and can
sink or source 10 mA of current into a resistive load. In
II
plied differentially across pins (2,3) and (4,5). Typical in- most multiplier applications, pin 11 is the actual
put bias current at the multiplier inputs is approximately XR-2228 output, with the op amp inputs being connect-
3 p,A, for each of the four inputs. In circuit applications ed to the multiplier outputs.
requiring single-ended, rather than differential, input
signals, pins 3 and 4 can be shorted together and con- APPLICATIONS INFORMATION
nected to a common bias point.
PART I: ARITHMETIC OPERATIONS
MULTIPLIER OUTPUTS (PINS 1 AND 16): The differential
output voltage, Yo, across these terminals is propor- MULTIPLICATION
tional to the linear product of voltages Vx and Vy ap-
plied to the inputs. Vo can be expressed as: For most multiplication applications, the multiplier and
op amp sections are interconnected as shown in Figure
14 to provide a single-ended analog output with a wide
dynamic range. The circuit of Figure 14 provides a lin-
ear output swing of 10V for maximum input signals of
10V, with a scale factor K = 0.1. The trimming proce-
where all voltages are in volts and the resistors are in dure for the circuit is as follows:
kO. Rx and Ry are the gain control resistors for X and Y
sections of the multiplier. 1. Apply OV to both inputs and adjust the output offset
to OV using the output offset control.
The common-mode dc potential at the multiplier out-
puts is approximately 3 volts below the positive supply. 2. Apply 20V pop at 50 Hz to the X-input and OV to the
V-input. Trim the V-offset adjust for minimum peak-
In most analog computation operations, such as multi- to-peak output.
plication, division, etc., pins 1 and 16 are dc coupled to
the op amp inputs (pins 13 and 14). The final output, Vz , 3. Apply 20V pop to the V-input and OV to the X-input.
is then obtained from the op amp output at pin 11, as Trim X-offset adjust for minimum peak-to-peak out-
shown in Figures 14 and 15. put.

6-51
4. Repeat step 1.
XR·2228
and is common to all analog division circuits. The di-
vider circuit is trimmed as follows:
5. Apply + 10V to both inputs and adjust scale factor
for Vo = + 10V. This step may be repeated with dif- 1. Apply Vz = 0 and trim the output offset adjustment
ferent amplitudes and polarities of input voltages to for constant output voltage as Vx is varied from -
optimize accuracy over the entire range of input 1V to -10V.
voltages, or over any specific portion of input volt-
age range. 2. Keeping Vz = 0, and applying Vx = -10V, time the
V-offset adjust until Vo = O.
R,

3. Let Vz = Vx and/or Vz = - Vx and trim the X-offset

adjustment for constant output voltage as Vx is var-
ied from - 1V to - 10V.

4. If step 3 requires a large initial adjustment, repeat

steps 1, 2 and 3.
Vz v:~Y
5. Keeping Vz = \Ix, adjust the scale factor trim for Vo
= -10V as Vx is varied from -1V to -10V.

P/~RT II: ANALOG SIGNAL PROCESSING

PHASE DETECTION
The multiplier section of the XR-2228 can be used as a
linear phase-discriminator. A recommended circuit con-
Figure 14. Multiplication Circuit
nection for this application is shown in Figure 16. In this
300K case, the reference input (input 1) is applied to pin 2,
Vlo---~~------~
and the input signal whose phase is to be detected (in-
put 2) is applied to pin 5. For input signal amplitudes
24K 24K ~ 50 mV rms, the differential output voltage, Vo across
pins 1 and 16 is directly proportional to the phase differ-
ence, <p, between the two input signals. It can be ex-
pressed as
10 Vz
>-+.:..:.o---{) VO'
v,
20 pF

SK Where <p is the phase difference expressed in radians.

-=- ·15V 62K

~
lOOK
Y - OFFSET _OJ OUTPUT
OFFSET ADJ.
·15V
.15V ~ lOOK 100)(

t Y-OFFSETADJ ~ INP~ f---f---,

x
'15V

Figure 15. Dividing Circuit

VolOI

DIVIDING CIRCUIT
INP~ 1---+-_-'
Cc
Recommended circuit connection for performing ana-
log division is shown in Figure 15. This circuit uses the
multiplier in the feedback path of the op amp. For the
circuit shown, Vo = + 10 VzN x where Vx < 0 and Vz
can have either sign. Positive values of Vx are not al-
lowed, since this will reverse the polarity of the feed- INPUT 1 ~ v,· E'l,n I"":otl Cc ft COUPLING CAPACITOR
INPUT 2 ., V2 '" E2 .'" I..... of .01 CB .. BYPASS CAPACITOR
back loop, causing posiiive ieedback and latchup. OUTPUT' Vo '''''' 5{~ - 1)
o • PHASE DIFFERENCE IN RAOIANS

This latchup mode is nondestructive to the XR-2228, Figure 16. Phase-Detector Circuit

6-52
XR·2228
The capacitors C1 at pins 1 and 16 provide a low-pass Figure 19. The: triangle input signal is applied to the
filter with a time constant T 1 = R1 C1, where R1 = 5 X-input (pin 2). The multiplier section rounds off the
kO is the international impedance level at these pins. peaks of this input and converts it to a low distortion
sine wave.
If needed, the phase conversion gain can be increased
by using the op amp section of the XR-2228 to further For the component values shown in Figure 19, the rec-
amplify the output voltage, Vo(cp). The XR-2228 is suit- ommended input signal level at pin 2 is == 300 mV pp, in
able for phase detection of input frequencies up to 100 order to obtain a 2V pp signal at pins 1 or 16, with RX
MHz. set at approximately 1000. The dc level at pin 5 can be
used for adjusting the output amplitude, or providing
SYNCHRONOUS AM DETECTION amplitude modulation. The sensitivity of the output am-
plitude to the dc voltage level at pin 5 is inversely pro-
Figure 17 is a typical circuit connection for synchro- portional to the external resistor across pins 6 and 7.
nous AM detection for carrier frequencies up to 100
MHz. The AM input signal is applied to the multiplier X- If higher amplitude output signal is required, the op
and Y-input terminals (pins 3 and 4) simultaneously. amp section of XR-2228 can be used to provide addi-
tional amplification.
The Y-gain terminals (pins 6 and 7) are shorted, and this
section of the multiplier serves as a "limiter" for input PHASE-LOCKED AM DETECTION
signals ;::: 50 mVrms; the X-section of the multiplier op-
erates in its linear mode. The low-pass filter capacitors, The XR-2228 can be used in conjunction with anyone
C1, and at pins 1 and 16 are used to filter the carrier of the commercially available monolithic phase-locked
feedthrough. If desired, the op amp section can be loop (PLL) IC's to provide phase-locked AM detection.
used as an audio preamplifier to increase the demodu- In this manner, frequency-selective detection capabili-
lated output amplitude. ties of PLL circuits can be extended to AM signals.

~C~-+-<>--=-t-i
AM INPUT x M
•
V'N

Figure 17. Synchronous AM Detector

'0·840kHI 10' Co - 200 of 'I'd Rl

PRECISION PHASE-LOCKED LOOP DESIGN Figure 18. Precision PLL

A precision phase-locked loop may be constructed us-
ing an XR-2209 voltage controlled oscillator and an
XR-2228. (See Figure 18.) Due to the excellent tempera-
ture stability and wide sweep range of the XR-2209 this SINU$OIDAl
OUTPUT
PLL circuit exhibits especially good stability of center

x
frequency and wide lock range. In this application the
XR-2228 serves as a phase comparator and level shift- VlIUT
er. Resistor RL adjusts the loop gain of the PLL, thus
varying the lock range. Tracking range may be varied I---t"'"-o-·
from about 1.5: 1 up to 12: 1. For large values of RL, tem-
perature stability of center frequency is better than 30
7 8
ppm/DC.
LEVEL

TRIANGLE-TO-SINEWAVE CONVERSION ADJUST

AM
A triangular input can be converted into a low distortion CON fROll
Ih FOR
(THD < 1 %) sinusoidal output with the XR-2228. A rec- MIN HiD

ommended connection for this application is shown in Figure 19. Triangle-to-Sinewave Converter

6-53
Figure 20 shows the circuit connection diagram for a
XR·2228
two-chip AM and FM detection system, using the
XR-215 high-frequency PLL in conjunction with the
XR-2228 multiplier/detector. Because of the high-
frequency capability of the XR-215, the circuit is useful
as a phase-locked AM detector for carrier frequencies
up to 20 MHz, and operates over a supply voltage range
of 10V to 20V.

The VCO section of XR-215 does not have a separate

"quadrature" output. However, this problem can be
overcome by driving the XR-2228 multiplier directly
from the timing capacitor terminals (pins 13 and 14) of
XR-215. The Y-input of the XR-2228 is operated with
maximum gain, since the Y-gain control terminals (pins Figure 20. Phase·Locked AM Detection Using XR·215
6 and 7) are shorted together. This causes the triangu- Monolithic PLL and XR·2228 Multiplier/Detector
lar waveform across the timing capacitor, CO, to be con- The Y-inputs (pins 4 and 5) are driven differentially from
verted to an effective "quadrature" drive. the VCO timing capacitor Signal (available at pins 13
and 14 of the PLL IC) which is AC coupled to pins 4 and
The modulated input signal is simultaneously applied to 5 of the XR-2228 multiplier input. the differential DC
both circuits through coupling capacitors. The phase- voltage level at the multiplier output terminals (pins 1
detector inputs of the XR-215, as well as the multiplier and 16) is offset by means of an external resistor, RA
X-inputs of the XR-2228, are biased at approximated This initial offset causes the op amp output of the XR-
one-half of VCC, by means of an external resistive di- 2228 to settle to a known state when there is no carrier
vider. or tone signal to be detected. With the op amp input
connections as shown in Figure 21, the op amp output
In Figure 20, Co sets the VCO frequency of the XR-215. (pin 11) would be at a "low" state when the PLL is not
In the case of FM demodulation, R1 and C1 serve as locked on a tone, and goes to a "high" state (I.e., near
the post-detection filter for the detected FM signal and + VCC) when the PLL circuit is "locked" on to an input
RF1 sets the gain of the FM post-detection amplifier. tone. The output logic polarity can be reversed simply
by reversing the op amp inputs.
The Y-input of the XR-2228 is operated in its switching
mode, with the Y-gain terminals (pins 6 and 7) shorted The filter capacitor, CA, connected across pins 1 and
together. The AM and/or FM signal is simultaneously 16 of the multiplier outputs, serves as the post-
applied to both circuits through coupling capacitors; detection low-pass filter. The value of CA is chosen to
the output of the multiplier, at pin 16, is AC coupled to provide a compromise between the response time and
the op amp section of the XR-2228, which 'serves as the the spurious noise rejection characteristics of the cir-
post-detection amplifier for the demodulated AM signal. cuit: increasing CA improves the noise rejection char-
In the circuit, RX sets the amplifier demodulation gain, acteristics of the circuit, but slows down the response
C3 serves as the low-pass post-detection filter. time.

A detailed description of the circuit operation, and the A detailed description of the principle of operation of
design equations for calculating the external compo- the circuit of Figure 21 is given in Exar's Application
nent values are given in Exar's Application Note AN-13, Note AN-12 entitled: "Designing High Frequency
entitled "Frequency Selective AM Detection using Phase-Locked Loop Carrier-Detector Circuits".
Monolithic Phase-Locked Loops."

PHASE·LOCKED LOOP TONE DETECTION

The XR-2228 multiplier/detector can be used in con-
junction with the XR-210 or the XR-215 high-frequency
---
~~.;::~,

:"--t~'~
i+'.J

--1 I'~=
PLL circuits, to provide high-frequency tone or carrier-
detect systems. The generalized circuit connection for I II GI-'·-+-----.
such an application is given in Figure 21. The circuit, as
I
shown, can operate with a single power supply, from HIGH'IIfOU("C't' I
10V, to 20V, or with split supplies in the range of ± 5V to I
± 10V. In the case of split power supplies, the resistor
'HAn lOCk'OlOQf' IJ

C"
,
string biasing the input terminals of the XR-2228 is not
necessary and can be eliminated by connecting node A _______ -.1
of Figure 21 to ground. ~".

The input signal is AC coupled, with separate coupling Figure 21. Recommended Circuit Connection of the XR·2228
capacitors, both to the input of the particular PLL cir- with the XR·210 or the XR·215 High·Frequency
cuit to be used and to the X-input terminal (pin 2) of the Phase· Locked Loops for Tone or Carrier·Detector
XR-2228. Application

6-54
 Section 6 - Instrumentation Circuits
Phase-Locked Loops . . . . . . . . . . . . 6-55
Fundamentals of Phase-Locked Loops 6-56
Applications of PLL ICs . . . . . . . . 6-57
Choosing the Right PLL Circuit 6-59
XR-210 Modulator/Demodulator . . . 6-60
XR-215 Monolithic Phase-Locked Loop 6-60
XR-2211 FSK DemodulatorlTone Decoder 6-65
XR-2212 Precision Phase-Locked Loop 6-82
XR-2213 Precision Phase-Locked LooplTone Decoder 6-89

II

6-55
Fundamentals of Phase-Locked Loops
The phase locked loop provides frequency selective is always smaller than the lock range and Is related to
tuning and filtering without the need for coils or induc- the low-pass filter bandwidth. It decreases as the filter
tors. As shown in Figure 1, the PLL in its most basic bandwidth Is reduced.
form Is a feedback system comprised of three basic
functional blocks: a phase comparator, low-pass filter The lock and the capture ranges of a PLL can be illus-
and voltage controlled oscillator (VeO). trated with reference to Figure 2, which shows the typi-
cal frequency-to-voltage characteristics of a PLL. In the
The basic principle of operation of a PLL can briefly be figure, the input is assumed to be swept slowly over a
explained as follows: With no input signal applied to the broad frequency range. The vertical scale corresponds
system, the error voltage Vd is equal to zero. The veo to the loop error voltage.
operates at a set frequency, fo, which is known as the
free-running frequency. If an input signal is applied to In the upper part of Figure 2, the loop frequency is be-
the system, the phase comparator compares the phase ing gradually increased. The loop does not respond to
and frequency of the input signal with the veo frequen- the signal until it reaches a frequency f1, correspond-
cy and generates an error voltage, Ve(t), that is related ing to the lower edge of the capture range. Then, the
to the phase and frequency difference between the two loop suddenly locks on the input, causing a negative
signals. This error voltage is then filtered and applied to jump of the loop error voltage. Next, Vd varies with
the control terminal of the veo. If the input frequency, frequency with a slope equal to the reciprocal of the
fs, is sufficiently close to fo, the feedback nature of the veo voltage-to-frequency conversion gain, and goes
PLL causes the veo to synchronize, or lock, with the through zero as fs = f o . The loop tracks the input until
incoming signal. Once in lock, the veo frequency is the input frequency reaches f2, corresponding to the
identical to the input signal, except for a finite phase dif- upper edge of the lock range. The PLL then loses lock,
ference. and the error voltage drops to zero.

Two key parameters of a PLL system are its lock and If the input frequency is now swept slowly back, the cy-
capture ranges. They can be defined as follows: cle repeats itself as shown in the lower part of Figure 2.
The loop recaptures the signal at f3 and traces it down
Lock range: The range of frequencies in the vicinity of fo, to f4. The frequency spread between (f1, f3) and (f2, f4)
over which the PLL can maintain lock with an input sig- corresponds to the total capture and lock ranges of the
nal. It is also known as the tracking or holding range. system; that is, f3 - f1 = capture range and f2 - f4 =
Lock range Increases as the over-all gain of the PLL is lock range. The PLL responds only to those input sig-
increased. nals sufficiently close to the veo frequency, fo, to fall
within the "lock" or "capture" range of the system. Its
Capture range: The band of frequencies in the vicinity of performance characteristics, therefore, offer a high de-
fo where the PLL can establish or acquire lock with an gree of frequency selectivity, with the selectivity char-
input signal. It is also known as the acquisition range. It acteristics centered about fo .

t-- t:.tL--l
Vd t I . :'0 ~ I-~ FREOUENCY

M V'" I,

-I I
LOCK RANGE I
I+-- 2,',l l ---.J
I CAPTURE RANGE
: ..... 261,-1
I. FREOUENCY

Figure 1. The basic phase locked loop consists of three func- Figure 2. Typical PLL frequency-to-voltage transfer character-
tional blocks: a phase comparator, a low pass filter istics are shown for increasing (upper diagram) and
and a voltage-controlled oscillator. decreasing (lower diagram) Input frequency.

6-56
Applications of PLL Ie's
The basic concept of the phase locked loop (PLL) has Applications for PLLs Abound
been around since the early 1930's and has been used
for a variety of applications in instrumentation and As a versatile building block, the PLL covers a wide
space telemetry. However, before the advent of mono- range of applications. Some of the more important are
lithic integration, cost and complexity considerations the following:
limited its use to precision measurements requiring
very narrow bandwidths. In the past few years, the ad- FM demodulation: In this application, the PLL is locked on
vantages of monolithic integration have changed the the input FM signal, and the loop-error voltage, Vd(t) in
phase locked loop from a specialized design technique Figure 1 (see Box), which keeps the veo in lock with
to a general-purpose building block. Therefore, what is the input signal, represents the demodulated output.
"new" at this point is not the concept of the PLL, but its Since the system responds only to input signals within
availability in a low-cost self contained monolithic Ie the capture range of the PLL, it also provides a high de-
package. gree of frequency selectivity. In most applications the
quality of the demodulated output (i.e., its linearity and
signal/noise ratio) obtained from a PLL is superior to
that of a conventional discriminator.
In many ways, this is similar to the case of the monolith-
ic operational amplifier, which, until less than a decade FSK demodulation: Frequency-shift keyed (FSK) signals
ago, was an expensive building block. Today, with the are commonly used to transmit digital information over
advent of monolithic technology, it has become a basic
telephone lines. In this type of modulation, the carrier
building block in nearly every system design. The
signal is shifted between two discrete frequencies to
monolithic phase locked loop also offers a similar po-
encode the binary data. When the PLL is locked on the
tential. In fact, many of the applications of the PLL out-
input signal, tracking the shifts in the input frequency,
lined in this article become economically feasible only
the error voltage in the loop, Vd(t), converts the fre-
because the PLL is now available as a low-cost Ie build-
quency shifts back to binary logic pulses.
ing block.
Signal conditioning: When the PLL is locked on a noisy In-
put signal, the veo output duplicates the frequency of
the desired input but greatly attenuates the noise, unde- •
Today, over a dozen different integrated PLL products sired sidebands and interference present at the input. It •
are available from a number of Ie manufacturers. Some is also a tracking filter since it can track a slowly vary-
of these are designed as "general-purpose" circuits, ing input frequency.
suitable for a multitude of uses; others are intended or
optimized for special applications such as tone detec- Frequency synthesis: The PLL can be used to generate
tion, stereo decoding and frequency synthesis. This ar- new frequencies from a stable reference source by ei-
ticle is intended as a brief survey of the expanding field ther frequency multiplication and division, or by fre-
of monolithic phase locked loops. Its purpose is to fa- quency translation. Figure 3 shows a typical frequency
miliarize the reader with their individual characteristics, multiplication and division circuit, using a PLL and two
capabilities and applications. programmable counters. In this application, one of the
counters is inserted between the veo and phase com-
parator and effectively divides the veo frequency by

PLL OFFSET
PROGRAMMABLE - - - - - - - - - -, INPUT
COUNTER I I PLl.

I I
I I
I I
I 1
I I
I I I
I _____ J _ _ _ _ _ _ _ _1
' " -_ _ _ OUTPUT

fll:r fA" fl

Figure 4. Frequency translation can be accomplished with a

Figure 3. A frequency multiplier/divider can be constructed phase locked loop by adding a multiplier and an ad-
using a phase locked loop. ditional low-pass filter to the basic PLL.

6-57
the counter's modulus N. When the system is in lock,
the veo output is related to the reference frequency,
PLL
fR, by the counter moduli M and N as:
AMOR

fo = (~) fR
TONE
INPUT

By adding a multiplier and an additional low-pass filter

to a PLL (Figure 4), one can form a frequency transla-
tion loop. In this application, the veo output is shifted
from the reference frequency, fR, by an amount equal
to the offset frequency, f1, i.e., fo == (fR + f1)'

Data synchronization: The PLL can be used to extract syn-

chronization from a composite signal, or can be used to
synchronize two data streams or system clocks to the DEMODULATED
OUTPUT
same frequency reference. Such applications are use-
ful in peM data transmission, regenerative repeaters,
eRT scanning and or drum memory read-write synchro-
nization. Figure 5. AM and tone detection are possible by adding three
functional blocks to the basic phase locked loop.
AM detection: The PLL can be converted to a synchro-
nous AM detector with the addition of a non-critical achieved using a PLL system, as shown in Figure 6.
phase-shift network, an analog multiplier and a low- The veo section of the monolithic PLL is separated
pass filter. The system block diagram for this applica- from the phase-comparator and used to generate a volt-
tion is shown in Figure 5. age controlled reference frequency, fRo The motor shaft
and the tachometer output provide the second signal,
In this application, as the PLL tracks the carrier of the frequency fM, which is compared to the reference fre-
input signal, the veo regenerates the unmodulated car- quency. The controller is a power amplifier which drives
rier and feeds it to the reference input of the multiplier the speed-control windings of the motor. Thus, the mo-
section. In this manner, the system functions as a syn- tor and tachometer combination essentially functions
chronous demodulator with the filtered output of the as a veo which is phase locked to the voltage con-
multiplier representing the demodulated audio informa- trolled reference frequency, fRo
tion.
Stereo decoding: In commercial FM broadcasting, sup-
Tone detection: In this application, the PLL is again con- pressed carrier AM modulation is used to superimpose
nected as shown in Figure 5. When a signal tone is the stereo information on the FM signal. To demodulate
present at the input, within a frequency band corre- the complex stereo signal, low-level pilot tone is trans-
sponding to the capture range of the PLL, the output dc mitted at 19 kHz (1/2 of actual carrier frequency). The
voltage is shifted from its tone-absent level. This shift is PLL can be used to lock onto this pilot tone, and regen-
easily converted to a logic signal by adding a threshold erate a coherent 38 kHz carrier which is then used to
detector with logic-compatible output levels. demodulate the complete stereo signal. A number of
highly specialized monolithic circuits have been devel-
Motor speed control: Many electromechanical systems, oped for this application. A typical example of monolith-
such as magnetic tape drives and disc or drum head ic stereo decoder circuits using the PLL principle is the
drivers, require precise speed control. This can be XR-1310 stereo demodu lator Ie.

L ________ _

ANALOG CONTROL
INPUT

Figure 6. Very precise motor speed control is possible with a phase locked loop system of this type.

6-58
Choosing the Right PLL Circuit
At the onset of his design, the user of monolithic PLL o Center frequency stability.
products is faced with the key question of choosing the o LogiC compatible output.
phase-locked loop IC best suited to his application. The o Control of VCO conversion gain.
broad line of PLL products offered by Exar cover a widE! Center frequency stability is essential to insure that the
range of applications. It is often difficult to determine a VCO frequency range stays within the signal band over
a glance the best circuit for a given application. The the operating temperature range. A logic compatible
purpose of this section is to review some of the key per- output is desirable to avoid the need for an external
formance requirements, from an applications point of voltage comparator (slicer) to square the output pulses.
view, and help answer the question, "What is the best It is particularly convenient if the output conforms to
PLL product for the job?" RS-232C standard, thereby eliminating the need for a
separate line-driver circuit. Control of the VCO's conver-
Table 2 gives a brief listing of some of the major classes sion gain allows the circuit to be used for both large de-
of PLL applications, and lists the recommended circuits viation FSK signals (such as 1200 baud operation) as
for each. A further discussion of the key performance well as for small deviation (75 baud) FSK signals.
parameters associated with each application are also
listed below. For FSK decoding at low frequencies (i.e., below 300
kHz) the XR-2211 is by far the optimum circuit to use
FM demodulation: Essentially all the PLL circuits listed in because of its frequency stability and carrier-detect ca-
Table 1 can be used for FM demodulation. However, it is pability. For FSK detection at higher frequencies (up to
often possible to narrow the choice down to 2 or 3 cir- 10 MHz) the XR-210 is the recommended circuit.
cuits, based on the particular performance criteria. In
general, there are three key performance parameters Frequency synthesis: This application requires a PLL cir-
which should be examined: cuit with the loop opened between the VCO output and
the phase comparator input, so that an external fre-
o Quality of demodulated output: This is normally quency divider can be inserted into the feedback loop
measured in terms of the output level, distortion, of the PLL. This requirement is satisfied by XR-S200,
and signal/noise ratio for a given FM deviation. XR-210, XR-215 and the XR-2212 PLL circuits.

o VCO frequency range and frequency stability: For For frequency synthesis at low frequencies (i.e., with
reliable operation, VCO upper frequency limit (see maximum output frequency less than 300 kHz) the •
Table 1) should be at least 20 % above the FM carri- XR-2212 is by far the best suited circuit since it has the •
er frequency. VCO frequency stability is important, best VCO stability and interfaces easily with all logic
especially if a narrow-band filter is used in front of families. For operation above 300 kHz, either the
the PLL, or multiple input channels are present. If XR-210 or the XR-215 PLL IC's can be used for frequen-
the VCO exhibits excessive drift, the PLL can drift cy synthesis; however the XR-215 offers the highest fre-
out of the input signal band as the ambient tempera- quency capability.
ture varies.
Signal conditioning: Most signal conditioning applications
o Detection threshold: This parameter determines require very narrow-band operation of the PLL. This in
minimum Signal level necessary for the PLL to lock turn may require the use of active filters within the loop
and demodulate an FM Signal of given deviation. (between the phase detector and the VCO). The PLL cir-
cuits which allow active filers to be inserted into the
In most FM demodulation applications, it is also desir- loop are the XR-S200 and the XR-2212. Both of these
able to control the amplitude of the demodulated out- circuits already contain an op. amp. on the chip for ac-
put. This feature is provided in some of the PLL circuits tive filtering. For low frequencies (i.e. below 300 kHz)
(such as the XR-215 and the XR-2212) by means of a the XR-2212 is the best suited circuit because of its ad-
variable-gain amplifier contained on the chip. justable tracking bandwidth and excellent frequency
stability. For higher frequencies the XR-S200 is the rec-
For low-frequency FM detection (below 300 kHz carrier ommended circuit.
frequency) the XR-2212 is recommended because of its
versatility and temperature stability. For FM demodula- Tone decoding: The PLL circuits especially designed for
tion at frequencies above 300 kHz, the XR-215 offers this application are the XR-567, the XR-L567, the
the best performance because of its high frequency ca- XR-2567 and the XR-2211. The XR-2211 offers the high-
pability. est frequency stability, and independent control of sys-
tem bandwidth and response time, among the three c;-.
FSK decoding: Frequency-shift keying used in digital cuits. The XR-567 has a relatively high input threshold
communications is very similar to analog FM modula- ("'" 20 mV, rms) and may require input preamplification;
tion. Therefore, any PLL IC can be used for FSK decod- however it requires fewer external components that the
ing, provided that its input sensitivity and the tracking XR-2211. The XR-2567, which contains two indepen-
range are sufficient for a given FSK signal deviation. dent 567-type tone decoders on the same chip may be
Some of the basic requirements and desirable features more economical to use in multiple-tone detection sys-
for a PLL used in FSK decoding are: tems.

6-59
 XR·210
FSK Modulator/Demodulator
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-210 is a highly versatile monolithic phase-
locked loop system, especially designed for data com- VOLTAGE
munications. It is particularly well suited for FSK COMPARATOR +Vcc
INPUT
modulation/demodulation (MODEM) applications, fre-
quency synthesis, tracking filters, and tone decoding. r
PHASE
VCO
OUTPUT
The XR-21 0 operates over a power supply range of 5V DETECTOR
to 26V, and over a frequency band of 0.5 Hz to 20 MHz. OUTPUTS
l
The circuit can accommodate analog signals between L '--04 ......""----.... 1 VCO
TIMING
300 p.V and 3V, and can interface with conventional CAPACITOR
INPUT
DTl, TIL, and ECl logic families. #1
J
BIAS l
VCO GAIN
AND SWEEP
INPUT CONTROLS
FEATURES #2
J
VCO
Wide Frequency Range 0.5 Hz to 20 MHz GROUND
KEYING
(-VEEi
Wide Supply Voltage Range 5V to 26V INPUT

Digital Programming Capability LOGIC VCO

OUTPUT FINE-TUNE
RS-232C Compatible Demodulator Output
DTl, TIL and ECl logic Compatibility
Wide Dynamic Range 300 p.V to 3V
ON-OFF Keying & Sweep Capability
Wide Tracking Range ± 1 % to ±50% ORDERING INFORMATION
Good Temperature Stability 200 ppm/oC
High-Current logic Output 50 mA Part Number Package Operating Temperature
Independent "Mark" and "Space"
XR-210M Ceramic - 55°C to + 125°C
Frequency Adjustment
XR-210CN Ceramic O°C to + 70°C
VCO Duty Cycle Control

APPLICATIONS
Data Synchronization
Signal Conditioning
FSK Generation
Tone Decoding
Frequency Synthesis SYSTEM DESCRIPTION
FSK Demodulation
Tracking Filter The XR-210 is made up of a stable wide-range voltage-
FM Detection controlled oscillator (veo) , exclusive OR gate type
FM and Sweep Generation phase detector, and an analog voltage comparator. The
Wideband Discrimination VCO, which produces a square wave as an output, is ei-
ther used in conjunction with the phase detector to
form a phase-locked loop (Pll) for FSK demodulation
and tone detection or as a qenerator in FSK modulation
schemes. The phase detector when used in the Pll
ABSOLUTE MAXIMUM RATINGS configuration produces a differentional output voltage
with a 6 KO output impedance, which when capacitively
Power Supply 26 Volts loaded forms a single pole loop filter. The voltage com-
Power Dissipation 750 mW parator is used to sense the phase detector output and
Derate Above + 25°C 6.0 mW/oC produces the output in the FSK demodulation connec-
Storage Temperature - 65°C to + 150°C tion.

6-60
XR·210
ELECTRICAL CHARACTERISTICS
Test Conditions: V + = 12V (single supply), TA = + 2SoC, Test circuit of Figure 1 with Co = 0.02 /-IF, S1, S2, Ss closed, S3, S4,
S6, S7 open, unless otherwise specified.

SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS

GENERAL CHARACTERISTICS
VCC Supply Voltage
Single Supply S 26 V dc See Figure 1
Split Supply ±2.S ±13 V dc See Figure 2
ICC Supply Current 9 12 16 mA See Figure 1, S2 open
fUL Upper Frequency Limit 1S 20 MHz See Figure 1, S1 open, 84 closed
fLL Lowest Practical Operating O.S Hz Co = SOO /-IF
Frequency
VCO SECTION
Stability
TC Temperature 200 SOO ppm/oC f = 10 kHz, V+ ~ 10V, 0 < TA < 7SoC
PSR Power Supply O.OS O.S %N 10V < V+ < 24V
fSW Sweep Range S:1 8:1 S3 closed, S4 open, 0 < Vs < 6V
See Figure S, V+ = 12V
Vo Output Voltage Swing 1.S 2.S V pop Ss open
DC Duty Cycle Asymmetry ±1 ±3 % Ss open
TR Rise Time 20 ns 10 pF to ground at Pin 15, Ss open
TF Fall Time 40 ns 10 pF to ground at Pin 15, Ss open
PHASE DETECTOR SECTION
KD Conversion Gain 2 V/rad Yin > SO mV rms, see Figure 8
Zo Output Impedance 6 kO Measured looking into Pin 2 or 3
VOOS Output Offset Voltage 3S 1S0 mV Measured across Pin 1 and 3, Yin = 0,
Ss open

•
VOLTAGE COMPARATOR SECTION
AVOL Open Loop Voltage Gain 66 80 dB f = 20 Hz
Z,N Input Impedance O.S 2 MO Measured looking into Pin 1
VOS Input Offset Voltage 1 mV
18 Input Bias Current 80 nA
CMRR Common Mode Rejection 90 dB
lOGIC OUTPUT SECTION
I
SR Slew Rate 1S V//-Isec RL = 3 kO, CL = 10 pF, S2 closed
IOL "1" Output Leakage Cu rrent 0.02 10 /-IA Vo = +24V
VOL "0" Output Voltage 0.2 0.4 V 'L = 10 mA
ISINK Current Sink Capability 30 SO mA Vo s 1V

PRINCIPLES OF OPERATION EQUIVALENT SCHEMATIC DIAGRAM

Description of Controls
Phase-Detector Inputs (Pin 4 and 6):
One input to the phase detector is used as the signal in-
put; the remaining input should be ac coupled to the
VCO output (Pin 15), to complete the PLL (see Figure 1).
For split supply operation, these inputs are biased from
ground as shown in Figure 2.

Phase-Detector Bias (Pin 5):

This terminal should be dc biased as shown in Figures
1 and 2, and ac grounded with a bypass capacitor. The

6-61
bias resistor in series with this pin should be half as
XR·210
Fine Tune Control (Pin 9):
large as those in series with Pin 4 and 6. For a given choice of timing capacitor. CO. the VCO fre-
quency can be further fine-adjusted to a desired fre-
quency, f1' by means of a trimmer resistor, Rr. connect-
Phase-Detector Outputs (Pin 2 and 3):
ed from Pin 9 to Pin 7. as shown in Figure 6. The fine
The low-frequency (or dc) voltage across these pins
tuned VCO ffequency, f1' is related to RT as:
corresponds to the phase difference between the two
Signals at the phase-detector inputs (Pin 4 and 6).
These differential phase-detector outputs are internally
connected to the VCO control terminals. Pin 3 is also in-
f1 ::z 220
Co
0 + 0.1) Hz
RT
terna"y connected to the reference input of the voltage
comparator section. where Co is in JtF, and RT is in kO.

VCO Timing Capacitor (Pin 13 and 14):

In normal use, the low-pass loop-filter capacitor, C1, is
connected between Pin 2 and 3. The 6 kO impedances The VCO free-running frequency, fo, is inversely propor-
of the two outputs add to 12 kO in the single-pole RC tional to the timing capacitor, CO, connected between
Pin 13 and 14. With Pin 9 and 10 open-circuited, the
low-pass loop filter. Pin 2 is externally connected to the
voltage comparator input (Pin 1) through an RC low- VCO frequency is related to Co as:
pass filter.
fa ::z 220 Hz
Co
Frequency-Keying Input (Pin 10):
The VCO frequency can be varied between two discrete where Co is in JtF.
frequencies, f1 and f2, by connecting an external resis-
tor, RX, to this terminal. Referring to Figure 6, the VCO VCO Output (Pin 15):
frequency is proportional to the sum of currents, 11 and The VCO produces approximately a 2.5V pop square
12, th rough the transistors, T 1 and T2, on the monolithic wave output signal at this pin. The dc output level is ap-
chip. These transistors are biased from a fixed internal proximately 2 volts below VCC. This pin should be con-
reference. The current, 11, is set internally, and is parti- nected to Pin 7 through a 10 kO resistor to increase the
ally contro"able by the fine-tune adjustment, RT. The output current drive capability. For high-voltage opera-
current, 12, is set by the external resistor, RX, connect- tion (VCC > 20V), a 20 kO resistor is recommended. It
ed between Pin 10 and Pin 7. For any Co setting, the is also advisable to connect a 5000 resistor in series
VCO frequency, f2' with RX connected to Pin 10, can be with this output, for short-circuit protection.
expressed as:

f2 = f1 0 ~:)
+ Hz
Using the frequency-keying control, the VCO frequency
can also be stepped in a binary manner by applying a
logic Signal to Pin 10, as shown in Figure 6. For high-
level logic inputs, the transistor, T2, is turned off, RX is
where f1 is the frequency with Pin 10 open-circuited, effectively switched out of the circuit, and the VCO fre-
and RX is in kO. Note that f2 can be fine-tuned to a de- quency is shifted from f2 to f1.
sired value by the proper choice of RX.
Voltage Comparator Input (Pin 1):
VCO Sweep Input (Pin 12): This pin provides the Signal input to the voltage compar-
The VCO frequency can be swept over a broad range ator section. The comparator section is normally used
by applying an analog sweep voltage, Vs to Pin 12 (see for post-demodulation slicing and pulse shaping. Nor-
Figure 5). The impedance level looking into the sweep mally, Pin 1 is connected to Pin 2 through a 15K exter-
input is approximately 500. Therefore, for sweep appli- nal resistor, as shown in Figures 1 and 2. The input im-
cations, a current limiting resistor, RS, should be con- pedance level at this pin is approximately 2 MO.
nected in series with this terminal. Typical sweep char-
acteristics of the circuit are shown in Figure 5. The VCO Logic Driver Output (Pin 8):
temperature dependence is minimal when the sweep This pin provides a binary logic output corresponding to
the polarity of the input signal, at the voltage compara-
input is not used, and should be left open-circuited.
tor inputs. It is a bare-collector type stage with high-
CAUTION: For safe operation of the circuit, the maxi- current sinking capability.
mum current, IS, drawn from the sweep terminal should
be limited to 5 mA or less, under all operating condi- Definition of Terms
tions.
Phase-Detector Gain, Kd:
Kd is the output voltage from the phase detector per ra-
veo Conversion Gain (Pin 11): dian of phase difference at the phase-detector inputs
The VCO voltage-to-frequency conversion gain, KO, is (Pin 4 and 6). Kd is proportional to the input signal for
inversely proportional to the value of the external gain- low-level inputs (:s 25 mV rms), and is constant at high-
control resistor, RO, connected across Pin 11 and 12. input levels (see Figure 8).

6-62
XR·210
.".,..1 1'- I~ L.,,: v' OR
GROUND

002
,F l---!:-<~l-OG-o,C
ouTPUT
Jlf

\'CODutflOVt
tOCOuNtl1i

01 ",F

Figure 2. Test Circuit for Split Supply Operation

Figure 1. Test Circuits for Single Supply Operation

VCO Conversion Gain, KO:

Ko'" 700 (radians/sec)/volt
CoRa
where Co is in /LF and RO is in kG. For most applica- D£MODULATID
0,11.1 F
tions, recommended values for RO range from 1 kG to OUTPUT
Fs~H-+---<>-'-I1--i
10 kG. INPUT J1

•
When the XR-210 is connected as a PLL, its lock range
can be controlled by varying the VCO gain control resis- 0.1",
tor, RO, across Pin 11 and 12. For input signals greater
than 30 mV rms, the PLL loop-gain is independent of
signal amplitude, but is inversely proportional to RO' 10~

Figure 7 shows the dependence of lock range, ± ~fL,

on RO.

Lock Range (~wL): Figure 3. Circuit Connection for FSK Demodulation

The range of frequencies in the vicinity of fa over which (Single Supply)
the PLL can maintain lock with an input signal. If satura-
tion or limiting does not occur, the lock range is equal to
the loop gain; i.e., dWL = KT = KdKo.

Capture Range (dwC):

The band of frequencies in the vicinity of fa where the +5
PLL can establish or acquire lock with an input signal. It
is also known as the acquisition range. It is always
~
smaller than the lock range, and is related to the low-
pass filter bandwidth. It can be approximated by a para-
metric equation of the form:
w
(!l
Z
ct
0
-- ~ -
I/~
J:
(J

dwC ,.. dWL IF(jdwC) I >

(J
z
w
where IF(jdwC) I is the low-pass filter magnitude re- ::>
0 -5
sponse at w = dwC. For a simple lag filter, it can be ex- w
pressed as: a:
u.
0

I
(J
>
-10
APPLICATIONS INFORMATION o 5 10 15 20 25
TOTAL SUPPLY VOLTAGE (VOLTS)
FSK Demodulation
Figure 3 shows a generalized circuit connection for Figure 4. veo Frequency Variation as a Function of Supply
FSK demodulation. The circuit is connected as a PLL Voltage

6-63
 6 80
XR·210
:0
~ 5
!J _0
40
>-
(,J
z
w 4 / ~
w'
t:l
20
::>
"a:
w
u. 3 - / Z
<t
a:
~
10

/
(,J
0 0
w ...J
N
:i 2 ...J
V IN = 1V rms
/
<t <t
~ I-
a: 0 fa = 2 MHz
I-
0
z
/
0 1
+2 0 -2 -4 -6 -8 -10 1 10 100
NET APPLIED SWEEP VOLTAGE, VS-VSO RO' Kn
(VOLTS)
Figure 7. Total Lock Range, ± AIL, versus VCO Gain Control
Resistor, RO

10.0
z
o
~­
ffi~
>-
2 0 1.0 /
0<1:
(,Je:
V

/
a:~
O...J
~g '" 2Vlrad
a:-
~ ~~ 0.1 I
(NOTE: VSO ~J VCC - 5V = Open Circuit Voltage at pin 12) 02

Figure 5. Frequency Sweep Characteristics as a Function 01

Net Applied Sweep Voltage (Pin 10 Open)
~«
cnt:l
<I:
:r:
Q, 0.01
/ HIGH LEVEL INPUT
CONS,ANT = y' rms

0.1 10 100 1000 10,000

LOW LEVEL INPUT AMPLITUDE (mV, rms)

INTERNAL
Figure 8. Phase Detector Conversion Gain, Kd, versus Input
BIAS Amplitude
+SV "'1

OVI FSK
INPUT
,. '2
and space frequencies of the input signal. Typical com-
ponent values for 300 baud (103-type) and 1200 baud
(202-type) MODEM applications are listed below:

','- OPERATING TYPICAL COMPONENT

Co ,+-
220 ( 0.' )
RT
CONDITIONS VALUES
Figure 6. veo Fine-Tune (Pin 9) and Frequency-Keying 300 Baud
(Pin 10) Controls Low Band: f1 = 1070 Hz AO = 5.1 kO, Co = 0.22 ",F

f2 = 1270 Hz C1 = C2 = 0.047 ",F,

system, by ac coupling the VCO output (Pin 15) to Pin 6. C3 = 0.033 ",F
The FSK input is applied to Pin 4. When the input fre- High Band: f1 = 2025 Hz AO = 8.2 kO, Co = 0.1 ",F
quency is shifted, corresponding to a data bit, the polar-
ity of the dc voltage across the phase-detector outputs f2 = 2225 Hz C1 = C2 = C3 =0.033 ",F
(Pin 2 and 3) is reversed. The voltage comparator and
the logic driver section convert this dc level shift to a bi- 1200 Baud
nary pulse. The capacitor, C1, serves as the PLL loop
filter, and C2 and C3 as post-detection filters. The tim- f1 = 1200 Hz C1 = 0.033 ",F,
C3 = 0.02 ",F
ing capacitor, CO, and fine-tune adjustments are used
f2 = 2200 Hz C2 = 0.01 ",F
to set the VCO frequency, fo, midway between the mark
6-64
 ~EXAR XR·215

Monolithic Phase-Locked Loop

The XR-215 is a highly versatile monolithic phase- FUNCTIONAL BLOCK DIAGRAM
locked loop (PLL) system designed for a wide variety of
applications in both analog and digital communication
systems. It Is especially well suited for FM or FSK de-
modulation, frequency synthesis and tracking filter ap-
plications. The XR-215 can operate over a large choice
of power supply voltages ranging from 5 V to 26 V and a
wide frequency band of 0.5 Hz to 35 MHz. It can ac-
commodate analog signals between 300 microvolts
and 3 volts and can interface with conventional DTL,
TIL, and ECL logic families.

FEATURES
Wide Frequency Range: 0.5 Hz to 35 MHz
Wide Supply Voltage Range: 5V to 26V
Digital Programming Capability
DTL, TIL and ECL Logic Compatibility

•
Wide Dynamic Range: 300 p.V to 3V
ON-OFF Keying and Sweep Capability
Wide Tracking Range: Adjustable from ± 1 % to ± 50% ORDERING INFORMATION
High-Quality FM Detection: Distortion 0.15%
Signal/Noise 65dB Part Number Package Operating Temperature
I

XR-215CN Ceramic O°C to 70°C

APPLICATIONS
FM Demodulation SYSTEM DESCRIPTION
Frequency Synthesis
FSK Coding/Decoding (MODEM) The XR-215 monolithic PLL system consists of a bal-
Tracking Filters anced phase comparator, a highly stable voltage-
Signal Conditioning controlled oscillator (VCO) and a high speed operation
Tone Decoding amplifier. Figure 1 depicts the functional block diagram
Data Synchronization of the circuit. The phase comparator outputs are inter-
Telemetry Coding/Decoding nally connected to the VCO inputs and to the non-
FM, FSK and Sweep Generation inverting input of the operational amplifier. A self-
Crystal Controlled Detection contained PLL System is formed by simple AC coupling
Wldeband Frequency Discrimination the VCO output to either of the phase comparator In-
VOltage-to-Frequency Conversion puts and adding a low-pass filter to the phase compara-
tor output terminals.

The VCO section has frequency sweep, on-off keying,

sync, and digital programming capabilities. Its frequen-
ABSOLUTE MAXIMUM RATINGS
cy is highly stable and is determined by a single exernal
Power Supply 26 volts capacitor. The operational amplifier can be used to for
Power Dissipation 750 mW audio preamplificatlon in FM detector applications or
as a high speed sense amplifier (or comparator) in FSK
Derate above + 25°C 5 mW/oC
Temperature demodulation.
Storage

6-65
ELECTRICAL CHARACTERISTICS
XR·215
supply), TA = 25°C, Test Circuit of Figure 2 with Co
Test Conditions: V + = 12V (single = 100 pF, (silver-mica) S1,
S2, S5, closed, S3, S4 open unless otherwise specified.

LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
I-GENERAL CHARACTERISTICS
SUPPLY VOLTAGE
Single Supply 5 26 V dc See Figure 2
Split Supply ±2.5 ±13 V dc See Figure 3
Supply Current 8 11 15 mA See Figure 2
Upper Frequency Limit 20 35 MHz See Figure 2, Sl open, S4 closed
Lowest Practical Operating
Frequency 0.5 Hz Co = 500 "F
VCO SECTION:
Stability:
Temperature 250 600 ppmloC See Figure 2, O°C S TAs 75°C
Power Supply 0.1 %N V+ > 10V
Sweep Range 5:1 8:1 S3 closed, S4 open,
0< Vs < 6V
See Figure 9, Co = 2000 pF
Output Voltage Swing 1.5 2.5 V _ S5 open
pp
Rise Time 20 ns
Fall Time 10 pF to ground at Pin 15
20 ns
PHASE COMPARATOR SECTION:
Conversion Gain 2 V/rad Yin > 50 mV rms (See
characteristic curves)
Output Impedance 6 kO Measured looking into Pins 2 or 3
Output Offset Voltage 20 100 mV Measured across Pins 2 and 3
Yin = 0, S5 open
OP AMP SECTION:
Open Loop Voltage Gain 66 80 dB S2 open
Slew Rate 2.5 VI" sec AV = 1
Input Impedance 0.5 2 MO
Output Impedance 2 kO
= 30 kO from
~i,P
Output Swing 7 10 RL Pin 8 to ground
Input Offset Voltage 1
Input Bias Current 80 nA
Common Mode Rejection 90 dB
II-SPECIAL APPLICATIONS
A) FM Demodulation
Test Conditions: Test circuit of Figure 4, V + = 12V, input signal = 10.7 MHz FM with ~f = 75 I-:Hz, fmod = 1 kHz.
Detection Threshold 0.8 3 mVrms 500 source
Demodulated Output Amplitude 250 500 mVrms Measured at Pin 8
Distortion (THO) 0.15 0.5 %
AM Rejection 40 dB Yin = 10 mV rms, 30% AM
Output Signal/Noise 55 65 dB
B) Tracking Fiber
Test Conditions: Test circuit of Figure 5, V+ = 12V, fo = 1 MHz, Vln = 100 mV rms, 500 source.
Tracking Range (% of fo) ±30 ±50 See Figures 5 and 25

Discriminator Output
~Vout
50 mV/% Adjustable - See applications
~flfo information

EQUIVALENT SCHEMATIC DIAGRAM

6·66
XR·215
DESCRIPTION OF CIRCUIT CONTROLS veo output (pin 15) to complete the PLL (see Figure 2).
For split supply operation, these inputs are biased from
PHASE COMPARATOR INPUTS (PINS 4 AND 6) ground as shown in Figure 3. For single supply opera-
tion, a resistive bias string similar to that shown in
One input to the phase comparator is used as the signal Figure 2 should be used to set the bias level at approxi-
input; the remaining input should be ac coupled to the mately VecJ2. The dc bias current at these terminals is
nominally 8 p.A.
R,
R,
PHASE COMPARATOR BIAS (PIN 5)

This terminal should be dc biased as shown in Figures

2 and 3, and ac grounded with a bypass capacitor.
l)[MOD

~'O OufPur
OI",F

vco
OUTPUT
ITOCOUNTFAI

o 1 .. ~+- ____ ~'N'---o

f)l(iNA1~
orSCRIMII\tA,TQR

',"VI 1J. 01 F
XR·215
OUTPuT

Figure 2_ Test Circuit For Single Supply Operation veo

OUTPuT

•
c( COUp\ I~u (ArA.CI rOR
CH H·t'J'A ....... CAPA,CIT(IH

Figure 5. Test Circuit For Tracking Filter

XR215 1. P
10 s <>-, I!,m! -0;. ·800r-----------------~
·~6V
c,c,E
_
y •• 12Y

r
t-
~ -400 ~~~"A':"""~~_ RO = & Kil
~
15 venCIlII"II!
L<-

SI(;NAl
INPUT 01 /-Ir 01 jJr
• I (I COlJ~~ I f III

a
u
!501~ "'"\... 2< 2< 10<
SUURClI 01
"r 400

Figure 3. Test Circuit For Split-Supply Operation 800L-________- L__________ ~ ________ ~

10 KHI 100 KHI 1 MHI 10MHI

'12v 01;.1f
fRE~UENCY

Figure 6. Typical VCO Temperature Coefficient Range as a

Function of Operating Frequency (pin 10 open)
107r-~~-----------------------_,
18

RX 7501! BETWEEN PINS 9 ANI) 10

Cl 106
0
u
UJ 5
u 10
z
veo
;:
OUTPUT U 104
~
<{
u
<:l
103
Z
6< ~
'IN ;: 10 2
JOI"' 10
10 10 2
VCO FREQUENCY (Hzl
Figure 4. Test Circuit For FM Demodulation Figure 7. VCO Free Running Frequency vs Timing Capacitor

6-67
 PHASE COMPARATOR OUTPUTS (PINS 2 AND 3)
l00dB~----~------'-------------~R~I-----'
XR·215
The low frequency (or dc) voltage across these pins 80 dB OPEN lOOP RESPONSE
corresponds to the phase difference between the two VOUT
signals at the phase comparator inputs (pins 4 and 6).
The phase comparator outputs are internally connected
to the veo control terminals (see Figure 1). One of the Cl
Z
~
WdB~~--_T------~~
1
w
outputs (pin 3) is internally connected to the non- ~ 40 dB \----::::.....--r-------t--------1r--"......
inverting input of the operational amplifier. The low-pass I-
...J
filter is achieved by connecting an Re network to the o
phase comparator outputs as shown in Figure 14. > 20 dB \-----.:=----..--....:....--,--------1f----........

vcn TIMING CAPACITOR (PINS 13 AND 14) OdB~~~_T--~--,-----~r_----~

The veo free-running frequency, fo, is inversely propor-

tional to timing capacitor eO connected between pins -20 dB L....L....L......J...L.L......L.--l-"-u........L.--"-.L.L.L...-L...-"-I.-'-'--'----'-...J..U
13 and 14. (See Figure 7). 100 H 1 KHz 10 KHz 100 KHz IOMHz
FREQUENCY

VCO OUTPUT (PIN 15) Figure 10. XR-215 Op Amp Frequency Response
The veo produces approximately a 2.5 Vp_p output sig-
nal at this pin. The dc output level is approximately 20V), a 20 kO resistor is recommended. It is also advis-
2 volts below Vee. This pin should be connected to pin able to connect a 5000 resistor in series with this out-
9 through a 10 kG resistor to increase the output cur- put for short circuit protection.
rent drive capability. For high voltage operation (Vee>
VCO SWEEP INPUT (PIN 12)
"z"
;c The veo Frequency can be swept over a broad range
"z
0 by applying an analog sweep voltage, VS, to pin 12 (see
.n_
o:z 10 Figure 9). The impedance level looking into the sweep
>~
ZO
0"
input is approximately 500. Therefore, for sweep appli-
UC[
0: III cations, a current limiting resistor, RS, should be con-
0>-
~o 01
nected in series with this terminal. Typical sweep char-
..
o:~
acteristics of the circuit are shown in Figure 9. The veo
~
8 temperature dependence is minimum when the sweep
III input is not used.
i 001
01 10 100 1000
lOW LEVEl INPUT AMPLITUDE ImV. ,m,I CAUTION: For safe operation of the circuit, the maxi-
mum current, IS, drawn from the sweep terminal should
Figure 8. Phase Comparator Conversion Gain, Kd. versus be limited to 5 mA or less under all operating condi-
Input Amplitude tions.

ON-OFF KEYING: With pin 10 open circuited, the veo

can be keyed off by applying a positive voltage pulse to
the sweep input terminal. With RS = 2 kO, oscillations
will stop if the applied potential at pin 12 is raised
3 volts above its open-circuit value. When sweep, sync,
~ 4 or on-off keying functions are not used, RS should be
>
u left open circuited.
z
':l J

~
~ 2

l
'A;~(;:15:::CT
::; INTE ANAL
<{ BIAS
~
o 1 Bias Pins 1,4,5,6 to VCC/2 13V INPUT
z
ov I· I,
6001l

+2 -2 -4 -6 -6 -10 -12 I, 'I (1' g:)

NET APPLIED SWEEP VOLTAGE. Vs - VSO (VOLTS)

Figure 9. Typical Frequency Sweep Characteristics as a

Function of Applied Sweep Voltage

(Note: VSO == VCC - 5V = Open Circuit Voltage at pin 12) Figure 11. Explanation of VCO Range-Select Controls

6-68
RANGE-SELECT (PIN 10) tem comprised of three basic functional blocks: phase
comparator, low-pass filter and voltage-controlled oscil-
The frequency range of the XR-215 can be extended by lator (VCO). The basic prinCiple of operation of a PLL
connecting an external resistor, RX, between pins 9 and can be briefly explained as follows: with no input signal
10. With reference to Figure 11, the operation of the applied to the system, the error voltage Vd, is equal to
range-select terminal can be explained as follows: The zero. The VCO operates at a set frequency, fo, which is
VCO frequency is proportional to the sum of currents 11 known as the "free-running" frequency. If an input sig-
and 12 through transistors T1 and T2 on the monolithic nal is applied to the system, the phase comparator
chip. These transistors are biased from a fixed internal compares the phase and frequency of the input signal
reference. The current 11 is set internally, whereas 12 is with the VCO frequency and generates an error voltage,
set by the external resistor RX' Thus, at any Co setting, Ve(t), that is related to the phase and frequency differ-
the VCO frequency can be expressed as: ence between the two Signals. This error voltage is then
filtered and applied to the control terminal of the VCO. If
fo = f1 0 ~:)
+
the input frequency, fs, is sufficiently close to fo, the
feedback nature of the PLL causes the VCO to synchro-
nize or "lock" with the incoming signal. Once in lock,
where f1 is the frequency with pin 10 open circuited the VCO frequency is identical to the input signal, ex-
and RX is in kO. External resistor RX (:::::: 7500) is recom- cept for a finite phase difference.
mended for operation at frequencies in excess of
5 MHz. A LINEARIZED MODEL FOR PLL

The range select terminal can also be used for fine tun- When the PLL is in lock, it can be approximated by the
ing the VCO frequency, by varying the value of RX' Simi- linear feedback system shown in Figure 13. ¢s and ¢o
larly, the VCO frequency can be changed in discrete are the respective phase angles associated with the in-
steps by switching in different values of RX between put signal and the VCO output, F(s) is the low-pass filter
pins 9 and 10. response in frequency domain, and Kd and Ko are the
conversion gains associated with the phase compara-
DIGITAL PROGRAMMING tor and VCO sections of the PLL.

•
Using the range select control, the VCO frequency can DEFINITION OF XR-215 PARAMETERS FOR
be stepped in a binary manner, by applying a logic sig- PLL APPLICATIONS
nal to pin 10, as shown in Figure 11. For high levellc~ic
inputs, transistor T2 is turned off, and RX is effectively VCO FREE-RUNNING FREQUENCY, fa
switched out of the circuit. Using the digital program-
ming capability, the XR-215 can be time-multiplexed be- The VCO frequency with no input signal. It is deter- I

tween two separate input frequencies, as shown in mined by selection of Co across pins 13 and 14 and can
Figures 18 and 19. be increased by connecting an external resistor RX be-
tween pins 9 and 10. It can be approximated as:
AMPLIFIER INPUT (PIN 1)

This pin provides the inverting input for the operational

amplifier section. Normally it is connected to pin 2
fo =
200
Co
0+ 0.6)
RX
through a 10 kO external resistor (see Figure 2 or 3). where Co is in ILF and RX is in kO. (See Figure 7).
AMPLIFIER OUTPUT (PIN 8)
II\PUT
SIGNAL
This pin is used as the output terminal for FM or FSK
demodulation. The amplifier gain is determined by the
external feedback resistor, RF, connected between pins
1 and 8. Frequency response characteristics of the am-
plifier section are shown in Figure 10.

AMPLIFIER COMPENSATION (PIN 7)

Figure 12. Black Diagram of a Phase-Lacked Loop
The operational amplifier can be compensated by.a sin-
gle 300 pF capacitor from pin 7 to ground. (See Figure
10).

BASIC PHASE-LOCKED LOOP OPERATION

PRINCIPLE OF OPERATION

The phase-locked loop (PLL) is a unique and versatile

circuit technique which provides frequency selective
tuning and filtering without the need for coils or induc- Figure 13. Linearized Madel of a PLL as a Negative
tors. As shown in Figure 12, the PLL is a feedback sys- Feedback System
6-69
 lAG·FllTER
XR·215 lAG·lEAD FilTER
PHASE COMPARATOR GAIN Kd
The output voltage from the phase comparator per radi-
an of phase difference at the phase comparator inputs
(pins 4 and 6).

VCO CONVERSION GAIN Ko

I
Fhl-'.2R,C.,
LJ
The VCO voltage-to-frequency conversion gain is deter-
mined by the choice of timing capacitor Co and gain
control resistor, RO connected externally across pins 11
and 12. It can be expressed as

Ko == 700 (radians/sec)lvolt
Fhl· i. ~e·I~~RlA2j
CORO

where Co is in J.l.F and RO is in kO. For most applica- Figure 14_

tions, recommended values for RO range from 1 kO to
10 kG. and 3. The low-pass filter components can be connect-
ed either between pins 2 and 3 or, from each pin to
LOCK RANGE (dwL) ground. Typical filter configurations and corresponding
filter transfer functions are shown in Figure 14 where
The range of frequencies in the vicinity of fo, over
R1 (6 kO) is the internal impedance at pins 2 and 3.
which the PLL can maintain lock with an input signal. It
is also known as the "tracking" or "holding" range. If
APPLICATIONS INFORMATION
saturation or limiting does not occur, the lock range is
equal to the loop gain, i.e. dWL = KT = Kd 1<0. FM DEMODULATION
CAPTURE RANGE (dwc) Figure 15 shows the external circuit connections to the
XR-215 for frequency-selective FM demodulation. The
The band of frequencies in the vicinity of fa where the choice of Co is determined by the FM carrier frequency
PLL can establish or acquire lock with an input signal. It (see Figure 7). The low-pass filter capacitor C1 is deter-
is also known as the "acquisition" range. It is always mined by the selectivity requirements. For carrier fre-
smaller than the lock range and is related to the low- quencies of 1 to 10 MHz, C1 is in the range of 10 Co to
pass filter bandwidth. It can be approximated by a para- 30 CO. The feedback resistor RF can be used as a
metric equation of the form: "volume-control" adjustment to set the amplitude of
the demodulated output. The demodulated output am-
dwC == dWL IF(jdWC) I plitude is proportional to the FM deviation and to resis-
where I F(j.l1wcl is the low-pass filter magnitude re- tors RO and RF For ± 1 % FM deviation it can be ap-
sponse at w = dwC. For a simple lag filter, it can be ex- proximated as:
pressed as:
VOUT == RoRF 0 ~.:)
+ mY, rms

where T 1 is the filter time constant.

AMPLIFIER GAIN AV
The voltage gain of the amplifier section is determined
by feedback resistors RF and Rp between pins (8,1)
and 2,1) respectively. (See Figures 2 and 3). It is given Cc
f~ ~i--+-<>"--+-~
by:

-RF
AV = - - ' - - -
'1'
R1 + Rp

where R1 is the 6 kO internal impedance at pin 2, and

Rp is the external resistor between pins 1 and 2.

LOW·PASS FILTER Cc COUPLING CAPACITOR

Cs BYPASS CAPACITOR

The low-pass filter section is formed by connecting an

external capacitor or RC network across terminals 2 Figure 15. Circuit Connection for FM Demodulation

6-70
 Note that for 300 Baud operation the circuit can be
XR·215
time-multiplexed between high and low bands by
switching the external resistor RX in and out of the cir-
cuit with a control signal, as shown in Figure 11.

FSK GENERATION

The digital programming capability of the XR-215 can

be used for FSK generation. A typical circuit connec-
tion for this application is shown in Figure 21. The VCO
frequency can be shifted between the mark (f2) and
space (f1) frequencies by applying a logic pulse to pin
10. The circuit can provide two separate FSK outputs: a
low level (2.5 Vp _p) output at pin 15 or a high amplitude
(10 Vp _p) output at pin 8. The output at each of these
terminals is a symmetrical squarewave with a typical
second harmonic content of less than 0.3 %. BINARY
RAr>..iG£ SELECT
IOPTIONAl!

Figure 22. Circuit Connection For Frequency Synthesis

follows: The counter divides down the oscillator fre-

01 .. f

," o---II--l~-O=--+--l
quency by the programmable divider modulus, N. Thus,
I~PuT when the entire system is phase-locked to an input sig-

1 (II".
nal at frequency, fs, the oscillator output at pin 15 is at a
frequency (Nf s), where N is the divider modulus. By
proper choice of the divider modulus, a large number of

•
discrete frequencies can be synthesized from a given
reference frequency. The low-pass filter capacitor C1 is
normally chosen to provide a cut-off frequency equal to
0.1 % to 2% of the signal frequency, f s .

The circuit was designed to operate with commercially

available monolithic programmable counter circuits us-
Figure 20. Circuit Connection for FSK Demodulation ing TIL logic, such as MC4016, SN5493 or equivalent.
The digital or analog tuning characteristics of the VCO
can be used to extend the available range of frequen-
cies of the system, for a given setting of the timing ca-
pacitor CO.
+ ~Il.
Typical input and output waveforms for N = 16 opera-
H

! ""
fi"""" tion with fs = 100 kHz and fo = 1.6 MHz are shown in
Figure 23.

TRACKING FILTER/DISCRIMINATOR
The wide tracking range of the XR-215 allows the sys-
J1JUL
" ',I
tem to track an input signal over a 3:1 frequency range,
FSK OUTPUT
(LOW LlVlLI
"
i'" J,
"t·,'".
".
0

Figure 21. Circuit Connection For FSK Generation

FREQUENCY SYNTHESIS

In frequency synthesis applications, a programmable

counter or divide-by-N circuit is connected between the Figure 23. Typical Input/Output Waveforms For N = 16
VCO output (pin 15) and one of the phase detector in- Top: Input (100 kHz)
puts (pins 4 or 6), as shown in Figure 22. The principle Bottom: VCO Output (1.6 MHz)
of operation of the circuit can be briefly explained as Vertical Scale 1 V/cm

6-71
XR·215 1~~~--------------~~~
RO' 21(0

100

I)ISCHIMINArOR 10
outPuf

1.0 o~~-..JL..--~....J...~~----I.---:012.0
NORMALIZED TRACKIN(; RANGE. 111101

Figure 25. Tracking Range vs Input Amplitude (Pin 10

300pF
Open Circuited)

Cc COUPLING C•..,ACITOR
C. BVPASS CAPACITOR

Figure 24. Circuit Connection For Tracking Filter Applications

centered about the VCO free running frequency. The

tracking range Is maximum when the binary range·
select (pin 10) Is open circuited. The circuit connec·
tlons for this application are shown In Figure 24. Typical
NORMALIZEO FREOUENCY.I," o
tracking range for a given Input Signal amplitude Is
shown In Figure 25. Recommended values of external
components are: 1 kO < RO < 4 kO and 30 Co < C1 < Figure 26. lYplcal Discriminator Output Characteristics For
300 Co where the timing capacitor Co Is determined by Tracking Filter Applications
the center frequency requirements (see Figure 7).
The phase'comparator output voltage Is a linear mea·
sure of the VCO frequency deviation from Its free·
running value. The amplifier section, therefore, can be
used to provide a filtered and amplified version of the
loop error voltage. In this case, the dc output level at
pin 15 can be adjusted to be directly proportional to the
difference between the VCO free·runnlng frequency, fo,
and the Input signal, fs. The entire system can operate
as a "linear discriminator" or analog "frequency·
meter" over a 3:1 change of input frequency. The dis·
criminator gain can be adjusted by proper choice of RO
or RF For the test circuit of Figure 24, the discriminator
output Is approximately (0.7 RORF) mV per % of fre·
quency deviation where RO and RF are In kO. Output
non·llnearity Is typically less than 1 % for frequency de·
viations up to ± 15 %. Figure 27 shows the normalized
output characteristics as a function of Input frequency,
with RO = 2 kO and RF = 36 kO.

CRYSTAL·CONTROLLED PLL Figure 27. lYplcal Circuit Connection For Crystal·Controlied

FM Detection
The XR·215 can be operated as a crystal·controlled
phase·locked loop by replacing the timing capacitor the crystal frequency. For this application the crystal
with a crystal. A circuit connection for this application should be operated in its fundamental mode. Typical
is shown in Figure 26. Normaliy a small tuning capaci· pull-in range oj the circuits is ± 1 kHz at 10 MHz.
tor (== 30 pF) is required In series with the crystal to set There is some distortion on the demodulated output.

6-72
XR·215
where aI/ resistors are in kO and RX is the range exten- f,.
CHANNEL I
tMHI
sion resistor connected across pins 9 and 10. For cir-

1~",~
cuit operation below 5 MHz, RX can be open circuited.
For operation above 5 MHz, RX "" 7500 is recom-
mended. C"ANNEL 2

Typical output signal/noise ratio and harmonic distor-

tion are shown in Figures 16 and 17 as a function of FM
deviation, for the component values shown in Figure 4.

MULTI-CHANNEL DEMODULATION

The ac digital programming capability of the XR-215 al-

lows a single circuit be time-shared or multiplexed be- ll,
tween two information channels, and thereby selective-
ly demodulate two separate carrier frequencies. Figure
18 shows a practical circuit configuration for time-
\~

:E '0"2
~'.
'II •\

multiplexing the XR-215 between two FM channels, at Figure 18. Time-Multiplexing XR-215 Between Two
1 MHz and 1.1 MHz respectively. The channel-select Simultaneous FM Channels
logic signal is applied to pin 10, as shown in Figure 18
with both input channels simultaneously present at the
PLL input (pin 4). Figure 19 shows the demodulated out-
put as a function of the channel-select pulse where the
two inputs have sinusoidal and triangular FM modula-
tion respectively.
0;
~100r-""'''''''''''''''''''''''''''''''''''''''''--~
is '0' 10M",
~

•
'mOd & 1 kHl
~ V1N =-20mV rrn s
<:> 80 (TEST CIRCUIT OF FIGURE 41
iii
::>
>-
::>
o
Figure 19. Demodulated Output Waveforms for
8 60 Time-Multiplexed Operation

~
o
Top: Demodulated Output BoHom: Channel Select
:< Sinewave - Channel 1 Pulse
~ ~~~OI~"''''''-::"~'''''-.-':::--'''''--:-::::--'''''-:-:''
100",. Triangle Wave - Channel 2

Figure 16. Output Signal/Noise Ratio as a Function of FM 3) is ac grounded and serves as the bias reference for
Deviation the operational amplifier section. Capacitor C1 serves
1"",--.....- - - - - - - - - . . , as the PLL loop filter, and C2 and C3 as post-detection
'0 IOMHI filters. Range select resistor, RX, can be used as a fine·
',nod lUil tune adjustment to set the VCO frequency.
V 1N 20rnV rnl~
V OU1 CONSTANT \.II') V p "
ITEST CIRCUIT OF FIGURE 'J Typical component values for 300 baud and 1200 baud
operation are listed below:

OPERATING TYPICAL COMPONENT

'~":-:-Ul-'".....-·-::10:-1·,...........~1O::'"',,--..J.
HY-"-~.
IUO'
CONDITIONS VALUES
FHEUUENCY DEVIATION' 'II"
300 Baud
Figure 17. Output Distortion as a Function of FM Deviation
Low Band: f1 = 1070 Hz RO = 5 kO, Co = 0.17 JlF
f2 = 1270 Hz C1 = C2 = 0.047 JlF,
FSK DEMODULATION C3 = 0.033 JlF
Figure 20 contains a typical circuit connection for FSK High Band: f1 = 2025 Hz RO = 8 kO, Co = 0.1 JlF
demodulation. When the input frequency is shifted, cor·
responding to a data bit, the dc voltage at the phase
f2 = 2225 Hz C1 = C2 = C3 = 0.033 JLF
comparator outputs (pins 2 and 3) also reverses polari- 1200 Baud RO = 2 kO, Co = 0.12JlF
ty. The operational amplifier section is connected as a
comparator, and converts the dc level shift to a binary f1 = 1200 Hz C1 = C3 = 0.003 JlF,
output pulse. One of the phase comparator outputs (pin f2 = 2200 Hz C2 = 0.01 JlF

6-73
 XR·2211

FSK Demodulator/Tone Decoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications. It
is particularly well suited for FSK modem applications.
It operates over a wide supply voltage range of 4.5 to
tVcc l
TIMING
CAPACITOR
20V and a wide frequency range of 0.01 Hz to 300 kHz.
It can accommodate analog signals between 2 mV and
INPUT

LOCK
J
3V, and can interface with conventional DTL, TIL, and OETECT TIMING
RESISTOR
FILTER
ECl logic families. The circuit consists of a basic PLl LOOP
for tracking an input signal within the pass band, a GROUND DET
OUT
quadrature phase detector which provides carrier de-
tection, and an FSK voltage comparator which provides LOCK
ra REF
VOLTAGE
OUT
DETECT
FSK demodulation. External components are used to in- OUTPUTS 0
dependently set center frequency, bandwidth, and out- L NC

put delay. An internal voltage reference proportional to DATA FSK

OUTPUT
the power supply provides ratio metric operation for low COMPINPUT

system performance variations with power supply

changes.
ORDERING INFORMATION
The XR-2211 is available in 14 pin DIP ceramic or
plastic packages specified for commercial or military Part Number Package Operating Temperature
temperature ranges.
XR-2211 M Ceramic -55°C to + 125°C
XR-2211CN Ceramic O°C to + 70°C
FEATURES XR-2211CP Plastic ooe to + 70 0 e
XR-2211N Ceramic -40°C to +85°e
Wide Frequency Range 0.01 Hz to 300 kHz XR-2211P Plastic - 40°C to + 85°e
Wide Supply Voltage Range 4.5V to 20 V
DTllTILlECL logic Compatibility SYSTEM DESCRIPTION
FSK Demodulation, with Carrier Detection
Wide Dynamic Range 2 mV to 3 V rms The main PLL within the XR-2211 is constructed from
Adjustable Tracking Range (± 1 % to ± 80%) an input preamplifier, analog multiplier used as a phase
Excellent Temp. Stability 20 ppm/oC, typo detector, and a precision voltage controlled oscillator
(VeO). The preamplifier is used as a limiter such that in-
put signals above typically 2mV RMS are amplified to a
APPLICATIONS constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
FSK Demodulation (unfiltered) produces sum and difference frequencies of
Data Synchronization the input and the VCO output, f input + f input (2f input)
Tone Decoding and f input - f input (0 Hz) when the phase detector out-
FM Detection put to remove the "sum" frequency component while
Carrier Detection passing the difference (DC) component to drive the
VCO. The VCO is actually a current controlled oscillator
with its nominal input current (fO) set by a resistor (RO)
ABSOLUTE MAXIMUM RATINGS to ground and its driving current with a resistor (R1)
from the phase detector.
PO'v'Jer Supply 20V
Input Signal Level 3V rms The other sections of the XR-2211 act to: determine if
Power Dissipation the veo is driven above or below the center frequency
Ceramic Package 750 mW (FSK comparator); produced both active high and active
Derate Above TA = +25°C 6 mV/oC low outputs to indicate when the main PLL is in lock
Plastic Package (quadrature phase detector and lock detector compara-
Derate Above TA = + 25°C tor).

6-74
XR·2211
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, V+ = V- = 6V, TA = +25°C, C = 5000 pF, R1 = R2 = R3 = R4 = 20 kO,
RL = 4.7 kO. Binary Inputs grounded, S1 and S2 closed, unless otherwise specified.

XR-2211 12211 M XR-2211C

PARAMETER MIN TYP MAX MIN TYP MAX UNITS CONDITIONS

GENERAL
Supply Voltage 4.5 20 4.5 20 V
Supply Current 4 7 5 9 mA RO ~ 10 kO. See Fig. 4
OSCILLATOR SECTION
Frequency Accuracy ±1 ±3 ±1 % Deviation from fO = 1/ROCO
Frequency Stability R1 = 1/2
Temperature ±20 ±50 ±20 ppm/oC See Fig. 8.
Power Supply 0.05 0.5 0.05 %N V+ = 12± W. See Fig. 7.
0.2 0.2 %N V+5 ± 0.5V. See Fig. 7.
Upper Frequency Limit 100 300 300 kHz RO = 8.2 kO, Co = 400 pF
Lowest Practical
Operating Frequency 0.01 0.01 Hz RO = 2 MO, Co = 50 /LF
Timing Resistor, RO See Fig. 5.
Operating Range 5 2000 5 2000 kO
Recommended Range 15 100 15 100 kO See Figs. 7 and 8.
LOOP PHASE DETECTOR SECTION

•
Peak Output Current ± 150 ±200 ±300 ± 100 ±200 ±300 /LA Measured at Pin 11.
Output Offset Current ±1 ±2 /LA
Output Impedance 1 1 MO
Maximum Swing ±4 ±5 ±4 ±5 V Referenced to Pin 10.
QUADRATURE PHASE DETECTOR Measured at Pin 3. I

Peak Output Current 100 150 150 ~

Output Impedance 1 1 MO
Maximum Swing 11 11 V pp
INPUT PREAMP SECTION Measured at Pin 2.
Input Impedance 20 20 kO
Input Signal
Voltage Required to
Cause Limiting 2 10 2 mV
rms
VOLTAGE COMPARATOR SECTIONS
Input Impedance 2 2 MO Measured at Pins 3 and 8.
Input Bias Current 100 100 nA
Voltage Gain 55 70 55 70 dB RL = 5.1 kO
Output Voltage Low 300 300 mV IC = 3 mA
Output Leakage Current 0.01 0.01 /LA Vo = 12V
INTERNAL REFERENCE
Voltage Level 4.9 5.3 5.7 4.75 5.3 5.85 V Measured at Pin 10.
Output Impedance 100 100 0 AC Small Signal
Maximum Source Current 80 80 /-LA

6-75
PRINCIPLES OF OPERATION
XR·2211
Reference Voltage, VR (Pin 10): This pin is internally biased
at the reference voltage level, VR: VR = V + 12 - 650
Signal Input (Pin 2): Signal is ac coupled to this terminal. mY. The dc voltage level at this pin forms an internal
The internal impedance at Pin 2 is 20 KO. Recom- reference for the voltage levels at Pins 5, 8, 11 and 12.
mended input signal level is in the range of 10 mV rms Pin 10 must be bypassed to ground with a 0.1 IJ.F ca-
to 3V rms. pacitor for proper operation of the circuit.

Ouadrature Phase Detector Output (Pin 3): This is the high Loop Phase Detector Output (Pin 11): This terminal provides
impedance output of quadrature phase detector and is a high impedance output for the loop phase detector.
internally connected to the input of lock detect voltage The PLL loop filter is formed by R1 and C1 connected
comparator. In tone detection applications, Pin 3 is con- to Pin 11 (see Figure 2). With no input signal, or with no
nected to ground through a parallel combination of RD phase error within the PLL, the dc level at Pin 11 is very
and CD (see Figure 2) to eliminate the chatter at lock nearly equal to VR. The peak voltage swing available at
detect outputs. If the tone detect section is not used, the phase detector output is equal to ± VR.
Pin 3 can be left open circuited. 510 KII R8 RL

Lock Detect Output, 0 (Pin 5): The output at Pin 5 is at

"high" state when the PLL is out of lock and goes to
"low" or conducting state when the PLL is locked. It is
an open collector type output and requires a pull-up re-
sistor, RL, to V + for proper operation. At "low" state, it
can sink up to 5 mA of load current.

Lock Datect Complement, ij (Pin 6): The output at Pin 6 is

the logic complement of the lock detect output at Pin 5.
This output is also an open collector type stage which
can sink 5 mA of load current at low or "on" state.

FSK Data Output (Pin 7): This output is an open collector

logic stage which requires a pull-up resistor, RL, to V+
for proper operation. It can sink 5 mA of load current.
When decoding FSK signals, FSK data output is at Figure 2. Generalized Circuit Connection for FSK and Tone
"high" or "off" state for low input frequency, and at Detection
"low" or "on" state for high input frequency. If no input
signal is present, the logic state at Pin 7 is indetermi- veo Control Input (Pin 12): VCO free-running frequency is
nate. determined by external timing resistor, RO, connected
from this terminal to ground. The VCO free-running fre-
FSK Comparator Input (Pin 8): This is the high impedance quency, fO, is:
input to the FSK voltage comparator. Normally, an FSK
post-detection or data filter is connected between this fO = _1_Hz
terminal and the PLL phase detector output (Pin 11). RaCo
This data filter is formed by RF and CF of Figure 2. The
threshold voltage of the comparator is set by the inter- where Co is the timing capacitor across Pins 13 and 14.
nal reference voltage, VR, available at Pin 10. For optimum temperature stability, RO must be in the
range of 10 KO to 100 KO see Figure 8).
LOOP DATA
FILTER FILTER FSK
This terminal is a low impedance point, and is internally
biased at a dc level equal to VR. The maximum timing
current drawn from Pin 12 must be limited to ~ 3 mA for
proper operation of the circuit.

veo Timing Capacitor (Pins 13 and 14): VCO frequency is

inversely proportional to the external timing capacitor,
CO, connected across these terminals (see Figure 5).
Co must be nonpolar, and in the range of 200 pF to 10
IJ.F.
veo Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with RO at Pin
12 (see Figure 9).

LOCK DETECT LOCK DETECT veo Free-Running Frequency, fO: XR-2211 does not have a
FILTER COMP separate VCO output terminal. Instead, the VCO out-
Figure 1. Functional Block Diagram of a Tone and FSK puts are internally connected to the phase detector
Decoding System Using XR-2211 sections of the circuit. However, for set-up or adjust-
6-76
ment purposes, VCO free-running frequency can be
XR·2211
one-pole post-detection filter for the FSK data output.
measured at Pin 3 (with CD disconnected), with no in- The resistor RB (= 510 Kn) from Pin 7 to Pin 8 intro-
put and with Pin 2 shorted to Pin 10. duces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
DESIGN EQUATIONS
(See Figure 2 for definition of components.) Recommended component values for some of the most
commonly used FSK bands are given in Table 1.
1. VCO Center Frequency, fO:
Design Instructions:
fO = 1/ROCO Hz
The circuit of Figure 9 can be tailored for any FSK de-
2. Internal Reference Voltage, VR (measured at Pin coding application by the choice of five key circuit com-
10): ponents: RO, R1, CO, C1 and CF For a given set of FSK
mark and space frequencies, f1 and f2' these parame-
VR = V+/2 - 650 mV ters can be calculated as follows:

3. Loop Low-Pass Filter Time Constant, T: a) Calculate PLL center frequency, fO:

T = R1C1 fa = f1 + f2
2
4. Loop Damping, t:
b) Choose value of timing resistor RO, to be in the
t = 1/4 ;-§Q range of 10 Kn to 100 Kn. This choice is arbitrary.
V"C1
5. Loop Tracking Bandwidth, ± <If/fO:
<If/fO = RO/R1
r-IIT:~::~~
I~t--r-~tl >
t----~--
TO PHASE
DETECTOR

I I I I I
'LL " 10 tz 'lH

6. FSK Data Filter Time Constant, TF:

TF = RFCF

7. Loop Phase Detector Conversion Gain, K¢: (K¢ is

the differential dc voltage across Pins 10 and 11,
per unit of phase error at phase detector input):

K¢ = 02VRf7r volts/radian
VIN MINIMUM ~ -]
v+ [ -10K ± 2.8 mV
8. VCO Conversion gain, KO: (KO is the amount of (PEAK) Rx + 20K
change in VCO frequency, per unit of dc voltage
change at Pin 11):
Figure 3. Desensitizing Input Stage
KO = -1IVRCOR1 Hz/volt
The recommended value is RO == 20 Kn. The final
9. Total Loop Gain, Kr- value of RO is normally fine-tuned with the series po-
tentiometer, RX.
KT = 271"K¢KO = 4/COR1 rad/sec/volt
c) Calculate value of Co from design equation (1) or
10. Peak Phase Detector Current IA from Figure 6:
IA = VR (volts)/25 mA Co = 1/ROfO

d) Calculate R1 to give a <If equal to the mark space

APPLICATIONS INFORMATION deviation:
FSK DECODING:

Figure 9 shows the basic circuit connection for FSK de- e) Calculate C1 to set loop damping. (See design equa-
coding. With reference to Figures 2 and 9, the func- tion No.4.):
tions of external components are defined as follows: RO
and Co set the PLL center frequency, R1 sets the sys- Normally, t "'" 1/2 is recommended.
tem bandwidth, and C1 sets the loop filter time con-
stant and the loop damping factor. CF and RF form a Then: C1 = CO/4 for t = 1/2

6-77
 XR·2211
f) Calculate Data Filter Capacitance, CF

For RF = 100 KO, RS = 510 KO, the recommended

.. ",
,
value of CF is:

CF z 3/(Saud Rate) /LF

Note: All calculated component values except RO can

be rounded to the nearest standard value, and RO can
be varied to fine-tune center frequency, through a se-
ries potentiometer, RX. (See Figure 9.)

15

:c
!. 1000
g
II:
'0 1Hz)
II:
~ 10
U
~

~ Figure 6. VCO Frequency vs Timing Capacitor

Q.
~
1/1

1.02
'0 = 'I kHz 5

~
R • 10 RO
5
ti 1.0 1
z
III
~
o :~. ~""" l,....oo-' ~ ~
""" ~ --i.
~
10 12 14 1. 1. 20 22 24 III 1.00 3
ff 4
SUPPlY VOlTAGE. v+ (VOlTS) o
III
:lc 0.99
:- ~ ~,..

Figure 4. Typical Supply Current vs V + (Logic Outputs

~
II:
o
/
2)
V CURVE
1
RO
51<
2 10 I<
Open Circuited) Z 0." I--
I
1
3
4
301<
100 K
0.97 5 lOOK
4 10 12 14 11 1. 20 22 24
1.0 _--...--...-....-...---.----T'-.,........,....,......--, v+ (VOLTS I

Figure 7. Typical fO vs Power Supply Characteristics

...
..! 0.1 ~.....--+~t-~~
8

100 1000 10.000 -25 o 25 50 100

'0 1Hz) TEMPERATURE reI

Figure 5. VCO Frequency vs Timing Resistor Figure 8. Typical Center Frequency Drift vs Temperature

6-78
XR·2211 y+
0.1 ~F

y+

DATA
OUTPUT

-1- 510 KII

Figure 10. External Connectors for FSK Demodulation with

Figure 9. Circuit Connection for FSK Decoding
Carrier Detect Capability

Design Example: Note: Data Output is "Low" When No Carrier is Present.

75 Baud FSK demodulator with mark space

frequencies of 1110/1170 Hz:
The minimum value of the lock detect filter capacitance
Step 1: Calculate fO: fO (1110 + 1170) (1/2) = Co is inversely proportional to the capture range, ±
~fc. This is the range of incoming frequencies over
1140 Hz
which the loop can acquire lock and is always less than
Step 2: Choose RO - 20 KO (18 KO fixed resistor in the tracking range. It is further limited by C1. For most
series with 5 KO potentiometer) applications, ~fc > ~f/2. For RO = 470 KO, the approx-
imate minimum value of CD can be determined by:
Step 3: Calculate Co from Figure 6: Co = 0.044 /LF

•
CD (/LF) ~ 16/capture range in Hz .
Step 4: Calculate R1: R1 = RO (2240/60) = 380 KO
With values of CD that are too small, chatter can be ob-
Step 5: Calculate C1: C1 = CO/4 = 0.011 /L F served on the lock detect output as an incoming signal
frequency approaches the capture bandwidth. Exces-
Note: All values except RO can be rounded to nearest sively large values of CD will slow the response time of
standard value. the Jock detect output.

TONE DETECTION:
Table 1. Recommended Component Values for
Commonly Used FSK Bands. (See Circuit ilf Figure 9.) Figure 11 shows the generalized circuit connection for
tone detection. The logic outputs, Q and Q at Pins 5 and
FSK BAND COMPONENT VALUES 6 are normally at "high" and "low" logic states, respec-
tively. When a tone is present within the detection band
300 Baud Co = 0. 039 /L F CF = 0.005/LF of the PLL, the logic state at these outputs become re-
f1 = 1070 Hz C1 = 0.01 /LF RO = 18 KO versed for the duration of the input tone. Each logic out-
F2 = 1270 Hz R1 = 100 KO put can sink 5 mA of load current.
300 Baud Co = 0.022/LF CF = 0.005/LF
f1 = 2025 Hz C1 = 0.0047/LF RO = 18 KO v+
f2 = 2225 Hz R1 = 200 KO
1200 Baud Co = 0. 027 /L F CF = 0.0022 jLF
f1 = 1200 Hz C1 = 0.01 /LF RO = 18 KO
f2 = 2200 Hz R1 = 30 KO
Co
FSK DECODING WITH CARRIER DETECT:

The lock detect section of XR-2211 can be used as a

*
carrier detect option, for FSK decoding. The recom-
mended circuit connection for this application is shown

0*
lOGIC
in Figure 10. The open collector lock detect output, Pin lOGIC
"Lf' OUTPUT Q
6, is shorted to data output (Pin 7). Thus, data output OUTPUT..J"""L

will be disabled at "low" state, until there is a carrier

within the detection band of the PPL, and the Pin 6 out-
put goes "high," to enable the data output. Figure 11. Circuit Connection for Tone Detection

6-79
Both logic outputs at Pins 5 and 6 are open collector
XR·2211
type stages, and require external pull-up resistors AL 1 b) Choose Co for fO = 1 kHz (from Figure 6): Co =
and AL2, as shown in Figure 11. 0.05 "F.

e) Calculate A1: A1 = (AO)(1000/20) = 1 MO.

With reference to Figures 2 and 11, the functions of the
external circuit components can be explained as fol-
lows: AO and Co set VCO center frequency; A1 sets the
d) Calculate C1: for r = 112, C1 = 0.25, Co =
0.013 "F.
detection bandwidth; C1 sets the low pass-loop filter
time constant and the loop damping factor. AL 1 and e) Calculate CO: Co = 16/38 = 0.42 "F.
AL2 are the respective pull-up resistors for the a and
Qlogic outputs. f) Fine-tune center frequency with 5 KO potentiometer,
AX·

Design Instructions:

The circuit of Figure 11 can be optimized for any tone

detection application by the choice of the 5 key circuit
LINEAR FM DETECTION:
components: AO, A1, CO, C1 and CO. For a given input,
the tone frequency, f8, these parameters are calcu- XA-2211 can be used as a linear FM detector for a wide
lated as follows: range of analog communications and telemetry appli-
cations. The recommended circuit connection for this
application is shown in Figure 12. The demodulated
a) Choose AO to be in the range of 15 KO to 100 KO. output is taken from the loop phase detector output (Pin
This choice is arbitrary. 11), through a post-detection filter made up of AF and
Cf=, and an external buffer amplifier. This buffer amplifi-
b) Calculate Co to set center frequency, fO equal to fs er is necessary because of the high impedance output
(see Figure 6): Co = 1/AOfS at Pin 11. Normally, a non-inverting unity gain op amp
can be used as a buffer amplifier, as shown in Figure
c) Calculate A1 to set bandwidth ±Af (see design 12.
equation No.5):

r---t----P"----o y+

Note: The total detection bandwidth covers the fre-

quency range of fO ± Af.

d) Calculate value of C1 for a given loop damping 0.1 ~F

factor; Co

12 11 -:

r
Normally == 1/2 is optimum for most tone detector ap-
RO

plications, giving C1 = 0.25 CO.

Increasing C1 improves the out-of-band signal rejec-

tion, but increases the PLL capture time.

e) Calculate value of filter capacitor CO. To avoid chat-

ter at the logic output, with AD = 470 KO, Co must
be:

CO("F) ~ (16/capture range in Hz)

Figure 12. Linear FM Detector Using XR-2211 and an External
Increasing Co slows down the logic output response
Op Amp. (See Section on Design Equation for Com-
time. ponent Values.)

The FM detector gain, i.e., the output voltage change

per unit of FM deviation can be given as:
Design Examples:
Vout = A1 VA/100 AO Volts/% deviation
Tone detector with a detection band of 1 kHz ± 20 Hz:
where VA is the internal reference voltage (VA = V +12
a) Choose AO = 20 KO (18 KO in series with 5 KO po- - 650 mY). For the choice of external components A1,
tentiometer). AO, CO, C1 and Cf=, see section on design equations.
6-80
XR-2211
EaUIVALENT SCHEMATIC DIAGRAM

V+ r----------,----------,------------------T-------i
,
REF
VOLTAGE
OUTPUT
10

20K

L __________ ~ _________ ~ ________________ ~ ______ ~

INTERNAL VOLTAGE INPUT PREAMPLIFIER QUADRATURE LOCK DETECT

REFERENCE AND UMITER PHASE DETECTOR COMPARATOR

------------------,--------,
I I
I I
I I
I I
I I

•
I FSK I
I COMPARATOR I
LOOP I INPUT I
~~EJrEpc.:rOA I I 7
I
I
I
I
~-- 12 I
I

~L
~ I ~R~:'~OR
____________ ~ ___________________ I ________ ~ ~
I

VOlTAGE COHTlIOlLED LOOP PHASE DnECTOR FSK COMPARATOR

OSCILLATOR

6-81
 XR·2212

Precision Phase-Locked Loop

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2212 is an ultra-stable monolithic phase-locked
loop (PLL) system especially designed for data commu-
nications and control system applications. Its on board
reference and uncommitted operational amplifier, to-
gether with a typical temperature stability of better
than 20 ppm/oC, make it ideally suited for frequency
synthesis, FM detection, and tracking filter applica-
tions. The wide input dynamic range, large operating
voltage range, large frequency range, and ECL, DTL,
and TIL compatibility contribute to the usefulness and
wide applicability of this device.

FEATURES
Quadrature VCO Outputs
Wide Frequency Range 0.01 Hz to 300 kHz
Wide Supply Voltage Range 4.5V to 20V
DTLITIL/ECL Logic Compatibility ORDERING INFORMATION
Wide Dynamic Range 2 mV to 3 Vrms
Adjustable Tracking Range (± 1 % to ±80%) Part Number Package Operating Temperature
Excellent Temp. Stability 20 ppm/oC, Typ. XR-2212M Ceramic - 55°C to + 125°C
XR2212CN Ceramic O°C to + 70°C
XR-2212CP Plastic O°C to + 70°C
XR-2212N Ceramic - 40°C to + 85°C
XR-2212P Plastic - 40°C to + 85°C

APPLICATIONS
SYSTEM DESCRIPTION
Frequency Synthesis
Data Synchronization The XR-2212 is a complete PLL system with buffered
FM Detection inputs and outputs, an internal reference, and an un-
Tracking Filters commited op amp. Two VCO outputs are pinned out;
FSK Demodulation one sources current, the other sources voltage. This
enables operation as a frequency synthesizer using an
external programmable divider. The op amp section
can be used as an audio preamplifier for FM detection
or as a high speed sense amplifier (comparator) for
FSK demodulation. The center frequency, bandwidth,
and tracking range of the PLL are controlled indepen-
ABSOLUTE MAXIMUM RATINGS dantly by external components. The PLL output is di-
rectly compatible with MOS, DTl, ECl, and TIL logic
Power Supply 18V families as well as microprocessor peripheral systems.
Input Signal Level 3 Vrms
Power Dissipation The precision PlL system operates over a supply volt-
Ceramic Package: 750 mW age range of 4.5 V to 20 V, a frequency range of 0.01
Derate Above TA = + 25°C 6 mW/oC Hz to 300 kHz, and accepts input signals in the range of
Plastic Package: 625 mW 2 mV to 3 Vrms. Temperature stability of the VCO is typi-
Derate Above TA = + 25°C 5 mW/oC cally better than 20 ppm/oC.

6-82
XR·2212
ELECTRICAL CHARACTERISTICS
= + 12V, TA = + 25°C, RO
Test Conditions: V + = 30 kO, Co = 0.033 J-LF, unless otherwise specified. See Figure 2 for
component designation.

XR-221212212M XR-2212C
PARAMETERS
MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL
Supply Voltage 4.5 15 4.5 15 V
Supply Current 6 10 6 12 mA RO ~ 10 KO. See Fig. 4
OSCILLATOR SECTION
Frequency Accuracy ±1 ±3 ±1 % Deviation from fO = 1/ROCO
Frequency Stability R1 = 00
Temperature ±20 ±50 ±20 ppm/DC See Fig. B.
Power Supply 0.05 0.5 0.05 %/V V+ = 12 ±1 V. See Fig. 7.
.2 .2 %/V V+ = 5 ±0.5 V.
See Fig. 7.
Upper Frequency Limit 100 300 300 kHz RO = B.2 KO, Co = 400 pF
Lowest Practical
Operating Frequency 0.01 0.01 Hz RO = 2 MO, Co = 50 J-LF
Timing Resistor, RO See Fig. 5.
Operating Range 5 2000 5 2000 KO
Recommended Range 15 100 15 100 KO See Fig. 7 and B.
OSCILLATOR OUTPUTS
Voltage Output Measured at Pin 5.
Positive Swing, VOH 11 11 V
Negative Swing, VOL .B .4 .5 V
Current Sink Capability 1 1 mA

II
Current Output Measured at Pin 3.
Peak Current Swing 100 150 150 J-LA
Output Impedance 1 1 MO
Quadrature Output Measured at Pin 15.
Output Swing 0.6 0.6 V I
DC Level 0.3 0.3 V Referenced to Pin 11.
Output Impedance 3 3 KO
LOOP PHASE DETECTOR SECTION Measured at Pin 10.
Peak Output Current ±150 ±200 ±300 ± 100 ±200 ±300 J-LA
Output Offset Current ±1 ±2 J-LA
Output Impedance 1 1 MO
Maximum Swing ±4 ±5 ±4 ±5 V Referenced to Pin 11.
INPUT PREAMP SECTION Measured at Pin 2.
Input Impedance 20 20 KO
Input Signal to Cause Limiting 2 10 2 mVrms
OP AMP SECTION
Voltage Gain 55 70 55 70 dB RL = 5.1 KO, RF = 00
Input Bias Current 0.1 1 0.1 1 J-LA
Offset Voltage ±5 ±20 ±5 ±20 mV
Slew Rate 2 2 V/J-Lsec
INTERNAL REFERENCE Measured at Pin 11.
Voltage Level 4.9 5.3 5.7 4.75 5.3 5.85 V
Output Impedance 100 100 0

6-83
 LOO'
XR·2212 >o.F
FILTER

()~ O(MOO
OUTPUT

-0
veo CURRINl OU1PUl veo OUAORA1URI OUl'Ul

Figure 1. Functional Block Diagram of XR·2212 Precision Figure 2. Generalized Circuit Connection for FM Detection,
PLL System Signal Tracking or Frequency Synthesis
r-------
I
I
I
I
I
I
I
I
ir.=~~~~~==~~~~~~

Figure 3. Simplified Circuit Schematic of XR·2212

TYPICAL CHARACTERISTICS

· /
"L .,,:..-- ....... ~
/L ~~v
~-- ;;.::~ ~~~
• f-- ~ ......
t::: ------
--
· •• 0 12 14
SUWU' VOUAGl. Y.IVO"'"
'1 I' JO U J4
'OIHli

Figure 4. Typical Supply Current vs V + Figure 5. VCO Frequency vs Timing Figure 6. VCO Frequency vs Timing
(LogiC Outputs Open Circuited) Resistor Capacitor

Figure 7. Typical fO vs Power Supply Characteristics Figure 8. Typical Center Frequency Drift vs Temperature

6-84
DESCRIPTION OF CIRCUIT CONTROLS VCO Timing CapaCitor (Pins 13 and 14): VCO frequency is
inversely proportional to the external timing capacitor,
Signal Input (Pin 2): Signal is ac coupled to this terminal. CO, connected across these terminals (see Figure 5).
The internal impedance at Pin 2 is 20 KO. Recom- Co must be nonpolar, and in the range of 200 pF to
mended input signal level is in the range of 10 mV to 5V 10 IlF.
peak-to-peak.
VCO Quadrature Output (Pin 15): The low-level C::::: 0.6 Vpp)
VCO Current Output (Pin 3): This is a high impedance (MO) output at this pin is at quadrature phase (i.e. 90° phase-
current output terminal which can provide ± 100 IlA offset) with the other VCO outputs at pins 3 and 5. The
drive capability with a voltage swing equal to V + . This dc level at pin 15 is approximately 300 mV above YR.
output can directly interface with CMOS or NMOS logic The quadrature output can be used with an external
families. multiplier as a "lock detect" circuit. In order not to de-
grade oscillator performance, the output at pin 15 must
VCO Voltage Output (Pin 5): This terminal provides a low- be buffered with an external high-impedance low-
impedance (::::: 500) buffered output for the VCO. It can capacitance amplifier. When not in use, pin 15 should
directly interface with low-power Schottley TIL. For in- be left open-circuited.
terfacing with standard TIL circuits, a 7500 pull-down
resistor from pin 5 to ground is required. For operation Phase Detector Input (Pin 16): Voltage output of the VCO
of the PLL without an external divider, pin 5 can be dc (pin 5) or the output of an external frequency divider is
coupled to pin 16. connected to this pin. The dc level of the senSing
threshold for the phase detector is referenced to YR. If
Op Amp Compensation (Pin 6): The op amp section is fre- the signal is capacitively coupled to pin 16, then this pin
quency compensated by connecting an external capac- must be biased from pin 11, through an external resis-
itor from pin 6 to the amplifier output (pin 8). For unity- tor, RS (RS :::::: 10 KO). The peak voltage swing applied to
gain compensation a 20 pF capacitor is recommended. pin 16 must not exceed (V + - 1.5) volts.
Op Amp Inputs (Pins 7 and 9): These are the inverting and
PHASE-LOCKED LOOP PARAMETERS:
the non-inverting inputs for the op amp section. The
common-mode range of the op amp inputs is from + 1V
Transfer Characteristics:
to (V + - 1.5) volts.
Figure 9 shows the basic frequency to voltage charac-
Op Amp Output (Pin 8): The op amp output is an open-
teristics of XR-2212. With no input signal present, fil-
collector type gain stage and requires a pull-up resistor,
tered phase detector output voltage is approximately
RL, to V + for proper operation. For most applications,
equal to the internal reference voltage, VR, at pin 11.
the recommended value of RL is in 5 kO to 10 kO range.
The PLL can track an input signal over its tracking
bandwidth, shown in the figure. The frequencies fTL
Phase Detector Output (Pin 10): This terminal provides a
and fTH represent the lower and the upper edge of the
high-impedance output for the loop phase-detector. The
tracking range, fO represents the VCO center frequency.
PLL loop filter is formed by R1 and C1 connected to Pin
10 (see Figure 2). With no input signal, or with no
phase-error within the PLL, the dc level at Pin 10 is very ~
nearly equal to YR. The peak voltage swing available at f
the phase detector output is equal to ± YR. ... 2V R

~
:)
Reference Voltage, VR (Pin 11): This pin is internally bi- 0
a:
ased at the reference voltage level, VR:VR = V + 12-
~
VR

650 mY. The dc voltage level at this pin forms an inter-

nal reference for the voltage levels at pins 10, 12 and 0

16. Pin 1 must be bypassed to ground with a 0.1 IlF ca-

pacitor, for proper operation of the circuit.
~
'Tl '0
INPUT SIGNAL FREOUENCY
VCO Control Input (Pin 12): VCO free-running frequency is
determined by external timing resistor, RO, connected Figure 9. Phase Detector Output Voltage (Pin 10) as a
from this terminal to ground. For optimum temperature Function of Input Signal Frequency. Note: Output
stability, RO must be in the range of 10 KO to 100 KO Voltage is Referenced to Internal Reference Voltage
(see Figure 8). VR at Pin 11

VCO Frequency Adjustment: VCO can be fine-tuned by

connecting a potentiometer, RX, in series with RO at Pin Design Equations:
12 (see Figure 10).
(See Figure 2 and Figure 9 for definition of compo-
This terminal is a low-impedance point, and is internally nents.)
biased at a dc level equal to YR. The maximum timing
current drawn from Pin 12 must be limited to s 3 mA for 1. VCO Center Frequency, fO: fO = 1/ROCO Hz
proper operation of the circuit.

6-85
2. Internal Reference Voltage, VR (measured at Pin 11)
XR·2212
VR := V+/2 - 650 mV OlMOO
t-<>.:-~~---o~,

3. Loop Low-Pass Filter Time Constant, r: r = R1C1 ",

."2112

.
4. Loop Damping, r: r = ~co
1/4- ·c
C1

where N is the external frequency divider modular

(See 2). If no divider is used, N := 1.

5. Loop Tracking Bandwidth, ± ~f/fO: ~f/fO = RO/R1

6. Phase Detector Conversion Gain, Kcp: (Kq, is the dif- "'x 'IHI TUNf
ferential dc voltage across Pins 10 and 11, per unit
of phase error at phase-detector input) Kcp
- 2VRhr volts/radian
Figure 10. Circuit Connection for FM Demodulation
7. VCO Conversion Gain, KO: (KO is the amount of
change in VCO frequency, per unit of dc voltage a) Choose VCO center frequency fO to be the same as
change at Pin 10. It is the reciprocal of the slope of FM carrier frequency.
conversion characteristics shown in Figure 9). KO
= -1NRCOR1 Hz/volt b) Choose value of timing resistor RO, to be in the
range of 10 KG to 100 KG. This choice is arbitrary.
8. Total Loop Gain, KT: The recommended value is RO == 20 KO. The final
value of RO is normally fine-tuned with the series po-
KT := 2'1!-KcpKO = 4/COR1 rad/sec/volt tentiometer, RX.

9. Peak Phase-Detector Current, IA; available at pin 10. c) Calculate value of Co from design equation (1) or
from Figure 6:
IA := VR (volts)/25 rnA
Co = 1/ROfO
APPLICATION INFORMATION
d) Choose R1 to determine the tracking bandwidth, ~f
FM DEMODULATION: (see design equation 5). The tracking bandwidth, ~f,
should be set significantly wider than the maximum
XR-2212 can be used as a linear FM demodulator for input FM signal deviation, ~fSM. Assuming the
both narrow-band and wide-band FM signals. The gen- tracking bandwidth to be "N" times larger than
eralized circuit connection for this application is shown ~fSM' one can re-unite design equation 5 as:
in Figure 10, where the VCO output (pin 5) is directly
connected to the phase detector input (pin 16). The de- ~f RO ~fSM
modulated signal is obtained at phase detector output
-=-=N--
fO R1 fO
(pin 10). In the circuit connection of Figure 10, the op
amp section of XR-2212 is used as a buffer amplifier to Table I lists recommended values of N, for various
provide both additional voltage amplification as well as values of the maximum deviation of the input FM
current drive capability. Thus, the demodulated output signal.
signal available at the op amp output (pin 8) is fully buf-
fered from the rest of the circuit.
Recommended value of
In the circuit of Figure 10, ROCO set the VCO center fre- % Deviation of FM Bandwidth Ratio, N
quency, R1 sets the tracking bandwidth, C1 sets the Signal (~fSM/fO) (N = ~f/ ~fSM)
low-pass filter time constant. Op amp feedback resis-
tors RF and RC set the voltage gain of the amplifier sec- 1 % or less 10
tion. 1 to 3% 5
1 to 5% 4
Design Instructions: 5 to 10% 3
10 to 30% 2
The circuit of Figure 10 can be tailored to any FM de- 30 to 50% 1.5
modulation application by a choice of the external com-
ponents RO, R1, RC, Rf=, Co and C1. For a given FM TABLE I
center frequency and frequency deviation, the choice Recommended values of bandwidth ratio, N, for various
of these components can be calculated as follows, values of FM Signal frequency deviation. (Note: N is the
using the design equations and definitions given on ratio of tracking bandwidth ~f to max. signal frequency
page 1-34, 1-35 and 1-36. deviation, ~fSM).

6-86
XR .. 2212
e) Calculate C1 to set loop damping (see design equa- N is the modulus of the external frequency divider. Con-
r
tion 4). Normally, = 1/2 is recommended. Then, C1 versely, the VCO output frequency, f1 is equal to NfS.
r
= CO/4 for = 1/2.
In the circuit configuration of Figure 11, the external
f) Calculate RC and RF to set peak output signal ampli- timing components, RO and CO, set the VCO free-
tude. Output signal amplitude, Vout, is given as: running frequency; R1 sets the tracking bandwidth and
C1 sets the loop damping, i.e., the low-pass filter time

(~:~M) (VR) (:~) [RC R: RF]

constant (see design equations).
Vout =
r---~--------------~~V·

In most applications, RF = 100 KO is recommended;

then RC, can be calculated from the above equation
to give desired output swing. The output amplifier 0.1
can also be used as a unity-gain voltage follower, by 0-;
INPUT 12
open circuiting RC (i.e., RC = 00). SIGNAL
XRl]'l

" 16
Note: All calculated component values except RO
can be rounded-off to the nearest standard value,
and RO can be varied to fine-tune center frequency,
through a series potentiometer, RX. (See Figure 10.) OUTPUT' 1 • N"

Design Example: V+
lK

Demodulator for FM signal with 67 kHz carrier frequen- • 14Sl90 OR C".I'v'rlAR

cy with ± 5 kHz frequency deviation. Supply voltage is
+ 12V and required peak output swing is ± 4 volts. Figure 11. Circuit Connection for Frequency Synthesizer

Step a) fa is chosen as 67 kHz.

The total tracking range of the PLL (see Figure 9),
Step b) Choose RO = 20 KO (18 KO fixed resistor in se- should be chosen to accommodate the lowest and the
ries with 5 KO potentiometer).

Step c) Calculate CO; from design Eq. (1).

Co = 746 pF
highest frequency, f max and fmin, to be synthesized.
A recommended choice for most applications is to
choose a tracking half-bandwidth ~f, such that:

~f ,.. f max - fmin.

II
Step d) Calculate R1' For given FM deviation, ~fSMIfO If a fixed output frequency is desired, i.e. Nand fS are
= 0.0746, and N = 3 from Table l. fixed, then a ± 10% tracking bandwidth is recom-
mended. Excessively large tracking bandwidth may
Then: cause the PLL to lock on the harmonics of the input sig-
nals; and the small tracking range increases the "lock-
RO/R1 = (3)(0.0746) = 0.224 up" or acquisition time.
or: If a variable input frequency and a variable counter
modulus N is used, then the maximum and the mini-
R1 = 89.3 KO.
mum values of output frequency will be:
Step e) Calculate C1 = (CO/4) = 186 pF.
f max = Nmax (fS)max and fmin = Nmin (fS)min·
Step f) Calculate RC and RF to get ± 4 volts peak out-
put swing: Let RF = 100 KO. Then, Design Instructions:

RC = 80.6 KO. For a given performance requirement, the circuit of

Figure 11 can be optimized as follows:
Note: All values except RO can be rounded-off to near-
est standard value. a) Choose center frequency, fO, to be equal to the out-
put frequency to be synthesized. If a range of output
FREQUENCY SYNTHESIS frequencies is desired, set fa to be at mid-point of
the desired range.
Figure 11 shows the generalized circuit connection for b) Choose timing resistor RO to be in the range of 15
frequency synthesis. In this application an external fre- KO to 100 KO. This choice is arbitrary. RO can be fine
quency divider is connected between the VCO output tuned with a series potentiometer, RX'
(pin 5) and the phase-detector input (pin 16). When the
circuit is in lock, the two signals going into the phase- c) Choose timing capacitor, Co from Figure 6 or Equa-
detector are at the same frequency, or fS = f1/N where tion 1.

6-87
d) Calculate R1 to set tracking bandwidth (see Figure
XR·2212
e) Calculate C1 to obtain desired loop damping. (See
9, and design equation 5). If a range of output fre- r
design equation 4). For most applications, = 1/2 is
quencies are desired, set R1 to get: recommended, thus:

Af = f max - fmin.

If a single fixed output frequency is desired, set R1 Note: All component values except RO can be rounded-
to get: off to nearest standard value.
Af = 0.1 fO.

6-88
 XR·2213

Precision Phase-Locked Loop/Tone Decoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK OIAGRA'M
The XR-2213 is a highly stable phase-locked loop (PLL)
system designed for control systems and tone detec-
tion applications. It combines the features of the XR-
2211 and XR-2212 into a single monolithic IC. The cir-
cuit consists of a high stability VCO, input preamplifier,
phase detector, quadrature phase detector, and high
gain voltage comparator. Initial VCO frequency accu-
racy and supply rejection are an order of magnitude
better than industry standards like the 567 decoder. An
on board reference contributes to reliable operation
and complementary outputs aid applicability.

FEATURES
Wide Frequency Range 0.01 Hz to 300 kHz
Wide Supply Voltage Ran~ 4.5 V to 15 V

•
Uncommitted VCO Q and Q Outputs ORDERING INFORMATION
Wide Dynamic Input Voltage Range 2mV to 3 V RMS
Excellent VCO Stability 20 PPM/DC Typ. Part Number Package Operating Temperature

XR-2213CN Ceramic O°C to + 70°C I

XR-2213CP Plastic O°C to + 70°C
XR-2213N Ceramic -40°C to + 85°C
XR-2213P Plastic _40DC to + 85°C
APPLICATIONS
Tone Detection
Frequency Synthesis
FM Detection
Tracking Filters SYSTEM DESCRIPTION
The XR-2213 is a complete PLL system including cir-
cuitry enabling dedicated tone detection capability
over a frequency range of 0.01 Hz to 300 kHz. Supply
voltage may range from 4.5 V to 15 V.
ABSOLUTE MAXIMUM RATINGS
The input preamplifier has a dynamic range of 2 mV to
Power Supply 15 V 3 Vrms. The high stability VCO, with buffered comple-
Input Signal Level 3 V RMS mentary outputs, typically features better than 20 ppm/
Power Dissipation °C temperature drift and 0.05%1V supply rejection. An
Ceramic Package: 750 mW on board voltage reference is provided, and can sink 2
Derate Above TA = +25 DC 6 mW/oC mA. The complementary lock detect outputs are each
Plastic Package: 625 mW capable of sinking more than 7 rnA. All system parame-
Derate Above TA = + 25°C 5 mW/cC ters are independantly determined by external compo-
Storage Temperature - 55°C to + 150 cC nents.

6-89
 ELECTRICAL CHARACTERISTICS
XR·2213
Test Conditions: VCC= + 12V, TA == + 25°C, RO == 10 kD, Co = 0.1 ItF, unless otherwise specified. See Figure 2 for
component designation.

XR·2213/2213M XR-2213C
PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS
GENERAL
Supply voltage 4.5 15 4.5 15 V
Supply current 9 11 9 12 mA Ro ~ 10KD
OSCILLATOR SECTION
Frequency accuracy ±1 ±3 ±1 % Deviation from
fo == _1_
RoC o
R1 == x
Frequency stability
Temperature 20 50 20 PPM/oC
Power supply 0.05 0.5 0.05 %/V V+ = 12V ± 1V
Upper frequency limit 100 300 300 kHz Ro == 8.2KO,
Co == 400pF
Timing resistor Ro
operating range 5 2000 KD
Recommended range 10 100 KO
OSCILLATOR OUTPUT
Voltage output
Positive swing 9.5 11.5 2.5 4.5 V IL::::; 100itA
Negative swing 0.4 0.8 0.4 0.8 V IL = 2mA
LOOP PHASE DETECTOR SECTION
Peak output current ± 150 ±200 ± 100 ±200 itA
Output offset current ±1 ±2 itA
Output impedance 1 1 MO
Maximum swing ±4 ±5 ±4 ±5 V Referenced to
VREF
INPUT PREAMP SECTION
Input impedance 20 20 KD
Input signal to cause limiting 2 10 2 MVRMS
Internal Reference
Voltage level 4.9 5.3 5.7 4.75 5.3 5.85 V
Output impedance 100 100 0

PRINCIPLES OF OPERATION
Figure 2 shows the standard connection for tone detec- flow in R1 with all of the current in RO coming from Pin
tion. The input signal at Pin 4 is amplified and squared- 13. This point is defined as the center frequency, fO, of
up by the preamp before it is fed to the loop phase de- the PLL and is calculated by:
tector. The VCO Q output provides the other loop phase
detector input. The VCO provided in the XR-2213 is ac- *fO = _1_
tually a current controlled oscillator, ICO. The input to ROCO
the ICO, Pin 13, is internally biased at VREF, with the If the input frequency is increased, the phase shift will
current drawn from this pin controlling the frequency of decrease causing the voltage at Pin 6 to decrease. Cur-
operation of the ICO. The resistor RO from Pin 13 to rent will now flow from Pin 13 to both RO and R1, caus-
ground v'IlIl provide a constant CUiient which wiii be ing an increase in ICO input current and thus an output
made up of the current from Pin 13 and the current frequency increase. If the phase detector swings all the
from R1 or the phase detector output. The phase detec- way to 0 volts, the current in R1, will be:
tor output, filtered by C1, will provide a voltage to R1,
which is proportional to the phase difference between VREF
IR1 = - -
the input frequency and the ICO frequency. The rela- R1
tionship between this voltage and phase difference is
shown in Figure 3. If the phase difference is 90°, Pin 6 *This condition will also occur if no input Signal is ap-
will be at VREF, and therefore there will be no current plied to Pin 4.

6-90
 XR·2213

VCC

RI.

LOCK OETECT
OUTPUTS

INTERNAL
VOLTAGE
REFERENCE

Figure 2. Generalized Circuit Connection for Tone Detection

PHASE SHIFT
BETWEEN
Vpo to ± At
'0' ~'AND 'I
The capture range of the PLL, which is always less than
the tracking range, is described by:

[AWl
ilWc = 21l"Af c = ~----;--7-

7 = R1C1'00P time constant

fc = capture range

~
fL
Figure 3. PLL Input/Output Relationships ilfc == ---
21l"R1C 1

At fa, the current from Pin 13 was: The internal voltage reference provides a voltage equal
to:

VREF == VCC -.7 V

2
If the ratio of Pin 13 current at fa and the change, il,
from fa is written, the tracking range can be deter- This reference can sink up to 2 rnA, but source only 100
mined: J.LA.

The quadrature phase detector will provide a high level,

VREF - VCC, at Pin 8 whenever a frequency within the PLL
AfL R1 RO RO capture range is present at Pin 4. This will drive the
- = -- = - or AfL = - lock-detect outputs for a tone-detection indication. The
fa VREF R1 R1
response of the lock-detect section can be controlled
RO by the capacitor, CO, from Pin 8 to ground. The mini-
mum value of Co is calculated by the formula:
If the input frequency was decreased, At will have the
same magnitude in the opposite direction. The tracking Co (J.LF) ~ 16 fc = capture range in Hz
range of the PLL will then be: fc

6-91
 XR·2213
RD = 470 KQ is suitable for most applications. 9. Loop capture range, ± Afc:

~
The input to the phase detector may be directly con- fL
nected to the VCO output in the stand-alone connec- Afc = ---Hz
tion. If the VCO is not connected to the phase detector, 211" R1C 1
the signal driving this pin must have sufficient ampli- 10. Lock detect filter capacitor:
tude to drive the pin above and below a voltage equal to
VREF. For low level signals, Pin 5 should be connected
to VREF through a 10 KO resistor and the signal capac i-
tively coupled to Pin 5. The impedance into Pin 5 is ap-
proximately 100 KO and this pin is clamped for swings
above VREF + 2 V.
APPLICATIONS INFORMATION
DESIGN EQUATIONS
Figure 2 shows the XR-C453 connected for tone detec-
Refer to Figure 2 for component definitions. tion. The input signal is capacitively coupled to Pin 4
and may range from 2 mV to 3 V RMS. The VCO Q out-
1. VCO center frequency, fa: put is directly connected to the phase detector input,
Pin 5. The detection bandwidth is set by the ratio of RO
fa = _1_Hz and R1 and the loop time constant, T. This corresponds
ROCO to the capture range of the PLL. The lock-detect output,
Pins 9 and 10, will give an active high and low indica-
2. Internal voltage reference, VREF tion when a tone in the detection bandwidth is present.

VCC
VREF = - - .7 V V
2 DESIGN EXAMPLE:

3. Loop tracking range, ± AfL: 20 kHz tone detector with a ± 1 kHz detection band.

A. Choose RO = 15 KO, 12 KO resistor plus 50 potenti-

ometer.

4. Loop low-pass filter time constant, T: B. Calculate Co = _1_ .0033 {tF

fORO
T = R1C1 sec.
Co
C. Calculate C1 = - =:: .001 JlF
5. Loop damping, r: 4

r = l ~co D. Calculate R1 = fa -
RO
= 300 KO
4 C1 Afc
6. Loop phase detector conversion gain, K</>:
E. Calculate CD = 16 =:: 0.01 JlF
fc
K = _ 2 VREF volts
<I> 11" radian F. Fine tune fa with Rx , 5 K potentiometer.
7. VCO conversion gain, KO: The complete circuit is shown in Figure 4.

KO =_ 1 Hz Figure 5 shows the connection for a frequency synthe-

VREF COR1 volt sizer. Here an input frequency of 10kHz produces an
output frequency of 40 kHz. The VCO center frequency,
8. Total loop gain, Kr: fa, is set for 40 kHz. The divide by four will then provide
the phase detector input with 10kHz. The lock range is
KT = KOKO = _4_ Hz set to approximately 10% of fa. For larger divider ra-
COR1 tios, C1 should be increased to minimize phase jitter.

6-92
XR·2213
Vcc~----------------~---.--------------------------------------------------------------.---,

10K 10K

OUTPUTS

~--+-------------~~~Q

GNO~------------~--+---~-------------------------------------------------+----~~~
INPUT Q Q

•
300 kU
19 kHz" 'I " 21 kHz VCC 0
19 kHz> II > 21 kHz 0 VCC

Figure 4. Tone Detector

.. 4

10 ~-I- ______+-__________________ ~

'o~-I-------+----------------------+---;

.1/,F

10KU

SKU

600pF

lOOK

GND~--------~----------------~----~~----------------------------------------------------~
-=- 'I = 10 kHz. 10 = 40 kHz,lCl = IC2 = v, DM7473 DUAL JK FLlP·FLOP

Figure 5. Frequency Synthesizer

6-93
6-94
 Section 6 - Instrumentation Circuits
Tone Decoders . . . . . . . . . . . . . . · 6-95
XR-567 Monolithic Tone Decoder · 6-96
XR-567A Precision Tone Decoder · 6-106
XR-L567 Micropower Tone Decoder · 6-108
XR-2567 Dual Monolithic Tone Decoder · 6-115

II
I

6-95
 XR·567

Monolithic Tone Decoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-567 is a monolithic phase-locked loop system
designed for general purpose tone and frequency de-
coding. The circuit operates over a wide frequency OUTPUT
fll HR
band of 0.01 Hz to 500 kHz and contains a logic com-
patible output which can sink up to 100 milliamps of
lOW PASS
load current. The bandwidth, center frequency, and out- lOOP Fll HR
put delay are independently determined by the selec-
tion of four external components.

The circuit consists of a phase detector, low-pass filter,

and current-controlled oscillator which comprise the
basic phase-locked loop; plus an additional low-pass
filter and quadrature detector that enables the system
to distinguish between the presence or absence of an
input signal at the center frequency.
ORDERING INFORMATION
FEATURES Part Number Package Operating Temperature
XR-567M Ceramic -55°C to +125°C
Bandwidth adjustable from 0 to 14 %.
XR-567CN Ceramic O°C to + 70°C
Logic compatible output with 100 mA current sinking
XR-567CP Plastic O°C to + 70°C
capability
High stable center frequency.
Center frequency adjustable from 0.01 Hz to 500 kHz
Inherent immunity to false signals SYSTEM DESCRIPTION
High rejection of out-of-band signals and noise The XR-567 monolithic tone decoder consists of a
Frequency range adjustable over 20:1 range by exter- phase detector, low pass filter, and current controlled
nal resistor. oscillator which comprise the basic phase-locked loop,
plus an additional low pass filter and quadrature detec-
tor enabling detection on in-band signals. The device
APPLICATIONS has a normally high open collector output capable of
sinking 100 mA.
Touch-ToneQ!l Decoding
Sequential Tone Decoding The input signal is applied to Pin 3 (20 kO nominal input
Communications Paging resistance). Free running frequency is controlled by an
Ultrasonic Remote-Control RC network at Pins 5 and 6 and can typically reach 500
Telemetry Decoding kHz. A capacitor on Pin 1 serves as the output filter and
eliminates out-of-band triggering. PLL filtering is ac-
complished with a capacitor on Pin 2; bandwidth and
ABSOLUTE MAXIMUM RATINGS skew are also dependant upon the circuitry here. Band-
width is adjustable from 0 % to 14 % of the center fre-
Power Supply 10 volts quency. Pin 4 is + VCC (4.75 to 9V nominal, 10V maxi-
Power DisSipation (package limitation) mum); Pin 7 is ground; and Pin 8 is open collector out-
Ceramic Package 385 mW put. pulling low when an in-band signal triggers the
Plastic Package 300 mW device.
Derate Above + 25°C 2.5 mW/oC
Temperature In applications requiring two or more 567-type devices,
Operating consider the XR-2567 dual tone decoder. Where center
XR-567M - 55°C to + 125°C frequency accuracy and drift are critical, compare the
XR-567CN/567CP O°C to + 70°C XR-567 A. Investigate employing the XR-L567 in low
Storage - 65°C to + 150°C power circuits.

6-96
XR·567
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = + 5V. TA = 25°C, unless otherwise specified. Test circuit of Figure 2.
LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
GENERAL
Supply Voltage Range 4.75 9.0 V dc
Supply Current
Quiescent XR-567M 6 8 mA RL = 20kO
XR-567C 7 10 mA RL = 20 kO
Activated XR-567M 11 13 mA RL = 20 kO
XR-567C 12 15 mA RL = 20 kO
Output Voltage 15 V
Negative Voltage at Input -10 V
Positive Voltage at Input VCC + 0.5 V

CENTER FREQUENCY
Highest Center Frequency 100 500 kHz
Center Frequency Stability
Temperature TA = 25°C 35 ppm/oC See Figure 9
o < TA < 70°C ±60 ppm/oC See Figure 9
-55 < TA < + 125°C ± 140 ppm/oC See Figure 9
Supply Voltage
XR-567M 0.5 1.0 %/V fo = 100 kHz
XR-567C 0.7 2.0 %/V fo = 100 kHz

DETECTION BANDWIDTH

•
Largest Detection Bandwidth
XR-567M 12 14 16 % of fo fo = 100kHz
XR-567C 10 14 18 % of fo fo = 100 kHz
Largest Detection Bandwidth Skew
XR-567M 1 2 % of fo
XR-567C 2 3 % offo
I
Largest Detection Bandwidth Variation
Temperature ±0.1 %/OC Vin = 300 mV rms
Supply Voltage ±2 %/V Vin = 300 mV rms

INPUT
Input Resistance 20 kO
Smallest Detectable Input Voltage 20 25 mVrms IL = 100 mA, fi = fo
Largest NO-Output Input Voltage 10 15 mVrms IL = 100 mA, fi = fo
Greatest Simultaneous Outband
Signal to Inband Signal Ratio +6 dB
Minimum Input Signal to Wideband
Noise Ratio -6 dB Bn = 140 kHz

OUTPUT
Output Saturation Voltage 0.2 0.4 V IL = 30 mA, Vin = 25 mV rms
0.6 1.0 V 'L = 100 mA, Vin = 25 mV rms
Output Leakage Current 0.01 25 p,A
Fastest ON-OFF CYCling Rate fo/20
Output Rise Time 150 ns RL = 500
Output Fall Time 30 ns RL = 500

6-97
 XR·567
DEFINITION OF XR·567 PARAMETERS If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
CENTER FREQUENCY fo voltage change across C3 reaches the threshold volt-
age. In certain applications, the delay may be desirable
fo is the free-running frequency of the current- as a means of suppressing spurious outputs. Con-
controlled oscillator with no input signal. It is deter- versely, if the value of C3 is too small, the beat rate at
mined by resistor R1 between pins 5 and 6, and capaci- the output of the quadrature detector (see FunctionEd
tor C1 from pin 6 to ground fo can be approximated by Block Diagram) may cause a false logic level change
at the output. (Pin 8)
fo == _1_
R1 C 1 The average voltage (during lock) at pin 1 is a function
of the inband input amplitude in accordance with the
where R1 is in ohms and C1 is in farads. given transfer characteristic.

DETECTION BANDWIDTH (BW) Vcc

<5V

The detection bandwidth is the frequency range cen-

~~F_+__~________~
tered about fo, within which an input signal larger than
the threshold voltage (typically 20 mV rms) will cause a
logic zero state at the output. The detection bandwidth
corresponds to the capture range of the PLL and is de- 0.01 IJF 3
termined by the low-pass bandwidth filter. The band- 0---1
width of the filter, as a percent of fo, can be determined
by the approximation XA 567

BW = 1070
jI
-
i
foC2
0.005 I 0.02

where Vi is the input signal in volts, rms, and C2 is the 1

capacitance at pin 2 in poF.

LARGEST DETECTION BANDWIDTH 2.4K

The largest detection bandwidth is the largest frequen-

cy range within which an input signal above the thresh- • Adlust lor 10 100 kHz c'
I,: 100 kHI. '5V
old voltage will cause a logical zero state at the output. 1°·0033
The maximum detection bandwidth corresponds to the
lock range of the PLL.
Figure 2. XR·567 Test Circuit
DETECTION BAND SKEW

The detection band skew is a measure of how accu-

rately the largest detection band is centered about the
center frequency, fo . It is defined as (f max + fmin - 2
fo)lfo, where f max and fmin are the frequencies corre-
sponding to the edges of the detection band. If neces-
sary, the detection band skew can be reduced to zero INPUT 0---1
by an optional centering adjustment. (See Optional
Controls). LOW PASS
XA 567
F I L TE A .-----<J--i

DESCRIPTION OF CIRCUIT CONTROLS

OUTPUT FILTER - C3 (Pin 1)

Capacitor C3 connected from pin 1 to ground forms a

simple low-pass post detection filter to eliminate spuri-
ous outputs due to out-of-band signals. The time con-
stant of the filter can be expressed as T3 = R3C3,
where R3 (4.7 kO) is the internal impedance at pin 1.

The precise value of C3 is not critical for most applica-

tions. To eliminate the possibility of false triggering by
spurious signals, it is recommended that C3 be C!!: 2 C2,
where C2 is the loop filter capacitance at pin 2. Figure 3. XR·567 Connection Diagram

6-98
XR·567
TYPICAL CHARACTERISTIC CURVES
25 15 106

<{
20
_0

..
0
~
, ~
~
E
I
.... I 10 "-'\ J:
10 5

~
15 J:
....
Cl
u
0
'\\
a ;:
~
;a 1\~,
i
10
....
'"
~
J: 10 4
"i'-.I'-.........
.....
, r--.
N
u
s 0

I'- ............. C
3

o~--~--~--~--~--~--~ C2
4 10
o
100 Hz 1 KHz 10 KHz 100 KHz 1 MHz 10 12 14 16

SUPPLY VOLTAGE - VOLTS CENTER FREOUENCY BANDWIQTH - % OF fO

Figure 4. Supply Current Versus Supply Figure 5. Largest Detection Bandwidth Figure 6. Detection Bandwidth as a
Voltage Versus Operating Frequency Function of C2 and Ca

300 15 14
t; 3.0
z
:l
250 12.5 12 ~ 2.0
~ ~
~ ~ 1 1 Vcc = 4.75V"
1.0
I~
_0

"Zz '-

•
10

--=
..0 ......
--
200 10

;::::..- ........
~ ~/
;..-~
I 8
"
~
150 7.5 -1.0

~
I VCC= 5.75V
I
6
i: ~
Cl
z r-- r-. -2.0

'"
100 5.0
;a 4
VCC = 7.0V /
~ -3.0
r-
50 2.5 2
r--
5 -4.0
BANDWIDTH AT 25"C
o
o :;:; -5.0
-75 -50 -25 +25 +50 +75 +100 +125 -75 -50 -25 25 50 75 100 125

TEMPERATURE H'CI
BANOWIDTH - % OF fa TEMPERATURE - °C

Figure 7. Bandwidth Versus Input Signal Figure 8. Bandwidth Variation with Figure 9. Frequency Drift with
Amplitude (C2 In #-IF) Temperature Temperature

100
-'-. ----- 1.0 1000

'- --- -
~
"""- 0.9
.........
........... 0.8
/ 500
400
'\.
"

/ 300
'\.
......
,
"
S 0.7
'\.
"
~ Cl
/ 200

-100
........... ~
!
I
0.6

0.5
V 100
'\ "ANDWIDTH LIMITED
BY C2

"', "
>
~
u
u
0.4
V
V
50
1\ l\.. '\
< 0.3 40
I'\.
-200
0.2
V 30
.""'-BANDWIDTH LIMITED BY

....- ./
20
~ERNAL RESISTOR
0.1
IM'~'M~MI Cf
-300 o ..... 1-- 10
4.5 5.0 5.5 6.0 6.5 7,0 1 2 3 4 5 10 20 3040 50 100 1 2 345 10 20 3040 50 100

SUPPL Y VOLTAGE - VOLTS CENTER FREQUENCY - kHz BANDWIDTH 1% of fol

Figure 10. Temperature Coefficient of Figure 11. Power Supply Dependence of Figure 12. Greatest Number of Cycles
Center Frequency (Mean and S.D.) Center Frequency Before Output

6-99
LOOP FILTER - C2 (Pin 2)
XR·567
Capacitor C2 connected from pin 2 to ground serves as
a single pole, low-pass filter for the PLL portion of the INPUT
XR-567. The filter time constant is given by T2 = R2C2,
where R2 (10 kO) is the impedance at pin 2.

The selection of C2 is determined by the detection

bandwidth requirements, as shown in Figure 6. For ad-
ditional information see section on "Definition of
XR-567 Parameters".
OUTPUT
The voltage at pin 2, the phase detector output, is a lin-
ear function of frequency over the range of 0.95 to 1.05
fo, with a slope of approximately 20 mV/% frequency
deviation. Response to 100 mV rms tone burst.
RL = 100 ohms.
INPUT (Pin 3)

The input signal is applied to pin 3 through a coupling

capacitor. This terminal is internally biased at a dc level
2 volts above ground, and has an input impedance level
of approximately 20 kO.

TIMING RESISTOR R1 AND CAPACITOR C1 (Pins 5 and 6)

The center frequency of the decoder is set by resistor

R1 between pins 5 and 6, and capacitor C1 from pin 6
to ground, as shown in Figure 3.

Pin 5 is the oscillator squarewave output which has a

magnitude of approximately VCC - 1.4V and an aver-
age dc level of VCC/2. A 1 kO load may be driven from
this point. The voltage at pin 6 is an exponential triangle Response to s~mc input tone burst with wideband noise.
waveform with a peak-to-peak amplitude of 1 volt and
~= - 6 dB R L = 100 ohms
an average dc level of VCC/2. Only high impedance
loads should be connected to pin 6 to avoid disturbing Noise Bandwidth = 140 Hz
the temperature stability or duty cycle of the oscillator.
Figure 13. Typical Response
1. R1 and C1 should be selected for the desired center
LOGIC OUTPUT (Pin 8) frequency by the expression fo :::::; 1/R1C1. For opti-
Terminal 8 provides a binary logic output when an input mum temperature stability, R1 should be selected
signal is present within the pass-band of the decoder. such that 2kO :s R1 :s 20 kO, and the R1C1 product
The logic output is an uncommitted, "base-collector" should have sufficient stability over the projected
power transistor capable of switching high current operating temperature range.
loads. The current level at the output is determined by
2. Low-pass capacitor. C2. can be determined from the
an external load resistor, RL, connected from pin 8 to
Bandwidth versus Input Signal Amplitude graph of
the positive supply.
Figure 7. One approach is to select an area of oper-
When an in-band signal is present, the output transistor ation from the graph. and then adjust the input level
at pin 8 saturates with a collector voltage less than 1 and value of C2 accordingly. Or. if the input ampli-
volt (typically 0.6V) at full rated current of 100 rnA.
If tude variation is known. the required foC2 product
can be found to give the desired bandwidth. Con-
large output voltage swings are needed, RL can be con-
nected to a supply voltage, V +, higher than the VCC stant bandwidth operation requires Vi > 200 mV
supply. For safe operation, V + :s 20 volts. rms. Then. as noted on the graph. bandwidth will be
controlled solely by the foC2 product.
OPERATING INSTRUCTIONS
3. Capacitor C3 sets the . lnd edge of the low-pass filt-
SELECTION OF EXTERNAL COMPONENTS er which attenuates frequencies outside of the de-
tection band and thereby eliminates spurious out-
A typical connection diagram for the XR-567 is shown puts. If C3 is too small, frequencies adjacent to the
in Figure 3. For most applications, the following proce- detection band may switch the output stage off and
dure will be sufficient for determination of the external on at the beat frequency. or the output may pulse off
components R1, C1, C2, and C3· and on during the turn-on transient. A typical mini-
mum value of C3 is 2 C2.

6-100
 XR·567
Conversely, if C3 is too large, turn-on and turn-off of losing information due to turn·on transient or output
the output stage will be delayed until the voltage chatter is about 10 cycles/bit, which corresponds to an
across C3 passes the threshold value. information transfer rate of fo/10 baud.

PRINCIPLE OF OPERATION C2 = 130 , C3 = 260 J-tF

fa fa
The XR-567 is a frequency selective tone decoder sys-
tem based on the phase-locked loop (PLL) principle. In situations where minimum turn-off time is of less im-
The system is comprised of a phase-locked loop, a portance than fast turn-on, the optional sensitivity ad-
quadrature AM detector, a voltage comparator, and an justment circuit of Figure 14 can be used to bring the
output logic driver. The four sections are internally inter- quiescent C3 voltage closer to the threshold voltage.
connected as shown in Figure 1. Sensitivity to beat frequencies, noise, and extraneous
signals, however, will be increased.
When an input tone is present within the pass-band of
+V
the circuit, the PLL synchronizes or "locks" on the in-

r::::,
put signal. The quadrature detector serves as a lock in-
dicator: when the PLL is locked on an input signal, the
dc voltage at the output of the detector is shifted. This
IA
LJ-L3I
dc level shift is then converted to an output logic pulse XR-567
by the amplifier and logic driver. The logic driver is a
C3
"bare collector" transistor stage capable of switching
R
100 mA loads.

The logic output at pin 8 is normally in a "high" state,

DECREASE
SENSITIVITY
INCREASE
SENSITIVITY I-=- -=-
until a tone that is within the capture range of the de-
·V
coder is present at the input. When the decoder is
locked on an input signal, the logic output at pin 8 goes
to a "low" state. RB
,
DECREASE
SENSITIVITY

XR 567
t

•
2.5K
The center frequency of the detector is set by the free- INCREASE
running frequency of the current-controlled oscillator in SENSITIVITY
the PLL. This free-running frequency, fa, is determined
by the selection of R1 and C1 connected to pins 5 and
6, as shown in Figure 3. The detection bandwidth is de- SILICON
termined by the size of the PLL filter capacitor, C2; and DIODES FOR
the output response speed is controlled by the output TEMPERATURE
COMPENSATION
filter capacitor, C3. }
10PTIONALJ

OPTIONAL CONTROLS
PROGRAMMING Figure 14. Optional Sensitivity Connections

Varying the value of resistor R1 and/or capacitor C1 will CHATTER

change the center frequency. The value of R1 can be
changed either mechanically or by solid state switches. When the value of C3 is small, the lock transient and ac
Additional C1 capacitors can be added by grounding components at the lock detector output may cause the
them through saturated npn transistors. output stage to move through its threshold more than
once, resulting in output chatter.
SPEED OF RESPONSE
Although some loads, such as lamps and relays will not
The minimum lock-up time is inversely related to the respond to chatter, logic may interpret chatter as a se-
loop frequency. As the natural loop frequency is low- ries of output signals. Chatter can be eliminated by
ered, the turn-on transient becomes greater. Thus maxi- feeding a portion of the output back to the input (pin 1)
mum operating speed is obtained when the value of ca- or, by increasing the size of capacitor C3. Generally, the
pacitor C2 is minimum. At the instant an input signal is feedback method is preferred since keeping C3 small
applied its phase may drive the oscillator away from the will enable faster operation. Three alternate schemes
incoming frequency rather than toward it. Under this for chatter prevention are shown in Figure 15. Gener-
condition, the lock-up transient is in a worst case situa- ally, it is only necessary to assure that the feedback
tion, and the minimum theoretical lock-up time will not time constant does not get so large that it prevents op-
be achievable. eration at the highest anticipated speed.

The following expressions yield the values of C2 and SKEW ADJUSTMENT

C3, in microfarads, which allow the maximum operating
speeds for various center frequencies. The minimum The circuits shown in Figure 16 can be used to change
rate that digital information may be detected without the position of the detection band (capture range) with-

6-101
 XR·567
Figure 18 shows the proper method of reducing the
loop gain for reduced bandwidth. This technique will im-
prove damping and permit faster performance under
XR 567
narrow band operation. The reduced impedance level
at pin 2 will require a larger value of C2 for a given cut-
off frequency.
+V .V

~
L
XR-567

RA
200 TO lK XR·567

"'''~ ,':,
'OPT IONAl - PE RMITS
lOWER VALUE OF C I -=-
Figure 15. Methods of Reducing Chatter
+V
J
~JR
3 20K

UNLATC"

l::1ir
CA PREVENTS LATC" UP
XR-567 W"EN POWER SUPPL Y IS
TURNED ON

C2 Figure 17. Output Latching

I
R
LOWERS '0 RAISES '0
tV

Vl
200
~
cr:
XR·567
> 150
E
w
RAISES '0 <.:J
~
I-
-'
0 100
SILICON
>
DIODES I-
FOR
~
TEMPERATURE z
} COMPENSATION 50
(OPTIONAL)

Figure 16. Connections to Reposition Detection Band 6 8 10 12 14 16

in the largest detection band (or lock range). By moving

DETECTION BAND % 0' '0
the detection band to either edge of the lock range, in- +v
put signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscil- PI N 2 - ......--"IJV'~~
lator. 567

OUTPUT LATCHING

In order to latch the output of the XR-567 "on" after a

signal is received, it is necessary to include a feedback OPTIONAL SILICON
DIODES FOR
resistor around the output stage, between pin 8 and pin TEMPERATURE
1, as shown in Figure 17. Pin 1 is pulled up to unlatch COMPENS.t..T!O!'!
the output stage.

BANDWIDTH REDUCTION

The bandwidth of the XR-567 can be reduced by either

increasing capaCitor C2 or reducing the loop gain. In- NOTE ADJUST CONTROL FOR SYMMETRY OF
creasing C2 may be an undesirable solution since this DETECTION BAND EDGES ABOUT '0
will also reduce the damping of the loop and thus slow
the circuit response time. Figure 18. Bandwidth Reduction

6-102
XR·567 +VCC
PRECAUTIONS
1. The XR-567 will lock on signals near (2n + 1) fo and O.1IJ F
produce an output for signals near (4n + 1) fo, for n
= 0,1,2 - etc. Signals at 5 fo and 9 fo can cause an
unwanted output and should, therefore, be attenu-
.r 01 = 2N2906

ated before reaching the input of the circuit.

2. Operating the XR-567 in a reduced bandwidth mode
of operation at input levels less than 200 mV rms
results in maximum immunity to noise and out-band C3

signals. Decreased loop damping, however, causes 8 vo

the worst-case lock-up time to increase, as shown
by the graph of Figure 12.

3. Bandwidth variations due to changes in the in-band

signal amplitude can be eliminated by operating the
XR-567 in the high input level mode, above 200 mV. VI
11'
-=-
0----1
Cc
XR-567

6
The input stage is then limiting, however, so that out-
band signals or high noise levels can cause an ap-
parent bandwidth reduction as the in-band signal is
suppressed. In addition, the limited input stage will
create in-band components from subharmonic sig-
nals so that the circuit components from subhar- +VCC
monic signals so that the circuit becomes sensitive Figure 19. Dual Time Constant Tone Decoder
to signals at fo/3, fo/5 etc.
can be used to detect the presence of the carrier sig-
4. Care should be exercised in lead routing and lead nal. The output of the XR-567 is used to turn off the FM
lengths should be kept as short as possible. Power demodulator when no carrier is present, thus acting as
supply leads should be properly bypassed close to a squelch. In the circuit shown, an XR-215 FM demodu-
the integrated circuit and grounding paths should be lator is used because of its wide dynamic range, high
carefully determined to avoid ground loops and un- signal/noise ratio and low distortion. The XR-567 will
desirable voltage variations. In addition, circuits re- detect the presence of a carrier at frequencies up to
quiring heavy load currents should be provided by a 500 kHz.
separate power supply, or filter capacitors increased
01j.1F
to minimize supply voltage variations. '6V -..-H--..--..--..--,
ADDITIONAL APPLICATIONS 300 pF 2CXX1pF

DUAL TIME CONSTANT TONE DECODER

For some applications it is important to have a tone de-
coder with narrow bandwidth and fast response time.
This can be accomplished by the dual time constant
DEMODULATED
tone decoder circuit shown in Figure 19. The circuit has OuTPUT

two low-pass loop filter capacitors, C2 and C'2. With no

input signal present, the output at pin 8 is high, transis-
tor 01 is off, and C'2 is switched out of the circuit. Thus
the loop low-pass filter is comprised of C2, which can
be kept as small as possible for minimum response
time.

When an in-band signal is detected, the output at pin 8

will go low, 01 will turn on, and capacitor C'2 will be
switched in parallel with capacitor C2. The low-pass filt-
er capacitance will then be C2 + C'2. The value of C'2
can be quite large in order to achieve narrow band-
width. Notice that during the time that no input signal is
being received, the bandwidth is determined by capaci-
tor C2.

NARROW BAND FM DEMODULATOR WITH

CARRIER DETECT
For FM demodulation applications where the bandwidth
is less than 10% of the carrier frequency, an XR-567 Figure 20. Narrow Band FM Demodulator with Carrier Detect

6-103
DUAL TONE DECODER
XR·567
other. Due to the internal biasing arrangement the
actual phase shift between the two outputs is typi-
In dual tone communication systems, information is cally 80°.
transmitted by the simultaneous presence of two sepa-
rate tones at the input. In such applications two XR-567
units can be connected in parallel, as shown in Figure
21 to form a dual tone decoder. The resistor and capaci-
tor values of each decoder are selected to provide the
desired center frequencies and bandwidth require-
ments.

Figure 22. OSCillator Output Waveform Available From CCO

Section.
Top: Square Wave Output at Pin 5:
Amplitude = (V + -1.4V), pp.,
Avg. Value = V+ 12
Bottom: Exponential Triangle Wave at Pin 6:
Amplitude = 1V pp., Avg. Value = V+ 12

v-
v+
C', I C'2 JJ c·:!
O.1fl..F
Figure 21. Dual Tone Decoder
-:F 3

VOUT
PRECISION OSCILLATOR

The current-controlled oscillator (CeO) section of the

XR-567 provides two basic output waveforms as shown
in Figure 22. The squarewave is obtained from pin 5,
and the exponential ramp from pin 6. The relative phase veo
TERMINAL
relationships of the waveforms are also provided in the (:!:6%)
figure. In addition to being used as a general purpose
oscillator or clock generator, the ceo can also be used
for any of the following special purpose oscillator appli-
cations:

1. High-Current Oscillator
1
The oscillator output of the XR-567 can be amplified
using the output amplifier and high-current logic out- Figure 23. Precision Oscillator to Switch 100 mA Loads
put available at pin 8. In this manner, the circuit can
switch 100 mA load currents without sacrificing os- 3. Oscillator with Frequency Doubled Output
cillator stability. A recommended circuit connection
for this appiication is shown in Figure 23. TI,8 oscil- The ceo fiequency can be dOUbled by applying a
lator frequency can be modulated over ± 6 % in fre- portion of the squarewave output at pin 5 back to the
quency by applying a control voltage to pin 2. input at pin 3, as shown in Figure 25. In this manner,
the quadrature detector functions as a frequency
2. Oscillator with Quadrature Outputs doubler and produces an output of 2 fo at pin 8.

Using the circuit connection of Figure 24 the XR-567 FSK DECODING

can function as a precision oscillator with two sepa-
rate squarewave outputs (at pins 5 and 8, respec- XR-567 can be used as a low speed FSK demodulator.
tively) that are at nearly quadrature phase with each In this application the center frequency is set to one of

6-104
XR·567
the input frequencies, and the bandwidth is adjusted to
leave the second frequency outside the detection band.
When the input signal is frequency keyed between the
in-band signal and the out-band signal, the logic state of
the output at pin 8 is reversed. Figure 26 shows the
FSK input (f2 = 3 f1) and the demodulated output sig-
nals, with to = f2 = 1 kHz. The circuit can handle data
rates up to fo/10 baud.

V+ V+

4
Figure 26. Input and Output Waveforms for FSK Decoding
3 XAb67 8 Top: Input FSK Signal (12 == 3f1)
Bottom: Demodulated Output
'1 6 S

CONNECT PIN 3
TO /8V TO
INVERT OUTPUT

Ie,
Figure 24. Oscillator with Quadrature Output

EQUIVALENT SCHEMATIC DIAGRAM

•

1
Figure 25. Oscillator with Double Frequency Output

6-105
 XR·567A

Precision Tone Decoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-567 A provides all the necessary circuitry for
constructing a variety of tone detectors and frequency
decoders. Phase-locked loop circuit techniques are
OUTPUT OUTPUT
used to provide operation from 0.01 Hz tp 500 kHz. FILTER
The circuit also features an input preamp, a high-current
LOW-PASS
logic output, and programmable output delay. LOOP FILTER
GROUND

The XR-567A, available in an a-Pin DIL package, is de- INPUT "I

TIMING
RESISTOR
signed to offer improved frequency accuracy and drift AND
characteristics over the standard industry 567. These CAPACITOR
+Vcc
changes offer improved overall circuit performance, .J
while reducing initial circuit adjustments.

FEATURES ORDERING INFORMATION

Programmable Detection Bandwidth 0% to 14% Part Number Package Operating Temperature
Logic Output 100 mA XR-567AM Ceramic - 55°C to + 125°C
Wide Center XR-567ACN Ceramic O°C to + 70°C
Frequency Range 0.01 Hz to 500 kHz XR-567ACP Plastic O°C to + 70°C
High Rejection
of Out-ot-Band Signals and Noise
Direct Replacement for standard 567 SYSTEM DESCRIPTION
Inherent immunity to
out-ol-band signals & noise The XR-567 A is an improved version of the popular 567
tone decoder. Center frequency accuracy is guaran-
teed by design modifications and testing to 5 %, and is
APPLICATIONS typically better than 2 %. Temperature drift of the cen-
ter frequency is also improved. Thus, in most applica-
Tone Detection tions, no trimming is required.
Touch-Tone(\!l Decoding
Communications Paging The XR-567 A monolithic tone decoder consists of a
Ultrasonic Remote Control phase detector, low pass filter, and current controlled
Precision Oscillator oscillator which comprise the basic phase-locked loop,
Wireless Intercom plus an additional low pass filter and quadrature detec-
Carrier-Tone Transceiver tor enabling detection of in-band signals. The device
FSK Demodulation has a normally high open collector output capable of
Dual Time Constant Tone Detector sinking 100 rnA.

The input signal is applied to Pin 3 (20 kO nominal input

ABSOLUTE MAXIMUM RATINGS reSistance). Free running frequency is controlled by an
RC network at Pins 5 and 6 and can typically reach 500
Power Supply 10 volts kHz. A capacitor on Pin 1 serves as the output filter and
Power Dissipation eliminates out-ot-band triggering. PLL filtering is ac-
"'01: ..... IA/
Ceramic Package vVv IIIVY compiished with a capacitor on Pin 2; bandwidth and
Plastic Package 300mW skew are also dependant upon the circuitry here. Band-
Derate above 25°C 2.5 mW/oC width is adjustable from 0 % to 14 % of the center fre-
Operating Temperature Range quency. Pin 4 is + VCC (4.75 to 9V nominal, 10V maxi-
XR-567AM -55°C to + 125°C mum); Pin 7 is ground; and Pin a is open collector out-
XR-567 ACN/ACP O°C to + 70°C put, pulling low when an in band signal triggers the
Storage Temperature Range - 65°C to + 150°C device.

6-106
XR·567A
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee = + 5V. TA = 25° e, unless otherwise specified.
LIMITS
PARAMETER: MIN TYP MAX UNITS CONDITIONS
GENERAL
Supply Voltage Range 4.75 9.0 Vdc
Supply Current
Quiescent XR·567 AM 6 8 mA RL = 20 kO
Quiescent XR·567 AC 7 10 mA RL = 20 kO
Activated XR·567AM 11 13 mA RL = 20 kO
Activated XR·567 AC 12 15 mA RL = 20 kO
Output Voltage 15 V
Negative Voltage at Input -10 V
Positive Voltage at Input VCC +0.5 V
CENTER FREQUENCY
Highest Center Frequency 100 500 kHz
Center Frequency Stability
Temperature TA = 25°C 35 ppm/DC
o < TA < 70°C ±60 ppm/DC
-55 < TA < +125°C ±120 ppm/DC
Supply Voltage
XR·567AM 0.5 1.0 %N to = 100 kHz
XR·567AC 0.7 2.0 %N to = 100 kHz
Initial Accuracy ±2.0 ±5.0 % 10 = 80 kHz
Center Frequency 1.06 I = 1/Rc
DETECTION BANDWIDTH
Largest Detection Bandwidth
XR-567AM 12 14 16 % otto to = 100 kHz

•
XR-567AC 10 14 18 % otto to = 100 kHz
Largest Detection Bandwidth Skew
XR-567AM 1 2 % otto
XR·567AC 2 3 % otto
Largest Detection Bandwidth Variation
Temperature ±0.1 %/oC Vin = 300 mV rms
Supply Voltage ±1 ±2 %N Yin = 300 mV rms
INPUT
Input Resistance 20 kO
Smallest Detectable Input Voltage 20 25 mVrms IL = 100 mA, ti = to
Largest No-Output Input Voltage 10 15 mVrms IL = 100mA,fi =to
Greatest Simultaneous Outband
Signal to Inband Signal Ratio +6 dB
Minimum Input Signal to Wideband
Noise Ratio -6 dB Bn = 140 kHz
OUTPUT
Output Saturation Voltage 0.2 0.4 V IL = 30 mA, Yin = 25 mV rms
0.6 1.0 V IL = 100 mA, Vin = 25 mV rms
Output Leakage Current 0.01 25 p.A
Fastest ON/OFF Cycling Rate fo/20
Output Rise Time 150 ns RL = 500
Output Fall Time 30 ns RL = 500

6-107
 XR·L567

Micropower Tone Decoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-L567 is a micropower phase-locked loop (PLL)
circuit designed for general purpose tone and frequen-
OU1PUl
cy decoding. In applications requiring very low power FILnR
dissipation, the XR-L567 can replace the popular 567-
type decoder with only minor component value
LOW PASS
changes. The XR-L567 offers approximately 1/10th the LOOP fiLTER
power dissipation of the conventional 567-type tone de-
coder, without sacrificing its key features such as the
oscillator stability, frequency selectivity, and detection
threshold. Typical quiescent power dissipation is less
than 4 mW at 5 volts. It operates over a wide frequency
band of 0.01 Hz to 60 kHz and contains a logic compati-
ble output which can sink up to 10 milliamps of load
current. The bandwidth, center frequency, and output
delay are independently determined by the selection of
four external components.
ORDERING INFORMATION
Part Number Package Operating Temperature
FEATURES
XR-L567CN Ceramic O°C to + 70°C
Very Low Power Dissipation (=:: 4 mW at 5V). XR-L567CP Plastic O°C to + 70°C
Bandwidth Adjustable from 0 to 14 %.
Logic Compatible Output with 10 mA Current Sinking
Capability.
Highly Stable Center Frequency. SYSTEM DESCRIPTION
Center Frequency Adjustable from 0.01 Hz to 60 kHz.
Inherent Immunity to False Signals. The XR-L567 monolithic circuit consists of a phase de-
High Rejection of Out-of-Band Signals and Noise. tector, low pass filter, and current controlled oscillator
Frequency Range Adjustable Over 20:1 Range by Ex- which comprise the basic phase-locked loop, plus an
ternal Resistor. additional low pass filter and quadrature detector ena-
bling detection of in-band signals. The device has a nor-
mally high open collector output.
APPLICATIONS
The input signal is applied to Pin 3 (100 k!l nominal in-
Battery-Operated Tone Detection put resistance). Free running frequency is controlled by
Touch-Toneilli Decoding an RC network at Pins 5 and 6. A capacitor on Pin 1
Sequential Tone Decoding serves as the output filter and eliminates out-of-band
Communications Paging triggering. PLL filtering is accomplished with a capaci-
Ultrasonic Remote-Control tor on Pin 2; band-width and skew are also dependant
Telemetry Decoding upon the circuitry here. Pin 4 is + VCC (4.75 to 8V nomi-
nal, 10V maximum); Pin 7 is ground; and Pin 8 is the
open collector output, pulling low when an in-band sig-
ABSOLUTE MAXIMUM RATINGS nal triggers the device.

Power Supply 10 volts The XR-L567 is pin-for-pin compatible with the standard
Power Dissipation (package limitation) XR-567-type decoder. Internal resistors have been
Ceramic Package 385 mW scaled up by a factor of ten, thereby reducing power
Plastic Package 300 mW disSipation and allowing use of smaller capacitors for
Derate Above + 25°C 2.5 mW/oC the same applications compared to the standard part.
Operating Temperature O°C to + 70°C This scaling also lowers maximum device center fre-
Storage Temperature - 65°C to + 150°C quency and load current sinking capabilities.

6-108
 XR·L567
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = + 5V. TA = 25°C, unless otherwise specified. Test Circuit of Figure 1.

LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
General
Supply Voltage Range 4.75 8.0 V
Supply Current
Quiescent 0.6 1.0 mA RL = 20 kO
Activated 0.8 1.4 mA RL = 20 kO
Center Frequency
Highest Center Frequency 10 60 kHz
Center Frequency Drift
Temperature TA = 25°C -35 ppm/DC See Figures 10 and 11
o < TA < 70°C -150 ppm/DC See Figures 10 and 11
Supply Voltage 0.5 3.0 %N fo = 10kHz, Vec = 5.25 ± 0.5V
Detection Bandwidth
Largest Detection Bandwidth 10 14 18 % of fo fo = 10 kHz
Largest Detection Bandwidth Skew 2 3 % of fo See Figure 13 for Definition
Largest Detection Bandwidth Variation
Temperature ±0.1 %/oC Yin = 300 mV rms
Supply Voltage ±2 %N Yin = 300 mV rms
Inputs
Input Resistance 100 kO

•
Smallest Detectable Input Voltage 20 25 mVrms IL = 10 mA, fi = fo
Largest No-Output Input Voltage 10 15 mVrms IL = 10 mA, fi = fo
Greatest Simultaneous Outband
Signal to Inband Signal Ratio +6 dB
Minimum Input Signal to Wideband
Noise Ratio -6 dB Bn = 140 kHz
I

Outputs
Output Saturation Voltage 0.2 0.4 V IL = 2 mA, Yin = 25 mV rms
0.3 0.6 V IL = 10 mA, Yin = 25 mV rms
Output Leakage Current 0.01 25 p.A
Fastest On/Off Cycling Rate fo/20
Output Rise Time 150 ns RL = 1 kO
Output Fall Time 30 ns RL = 1 kO

EQUIVALENT SCHEMATIC DIAGRAM PRINCIPLES OF OPERATION

The XR-L567 is a frequency selective tone decoder sys-
tem based on the phase-locked loop (PLL) principle.
The system is comprised of a phase-locked loop, a
quadrature am detector, a voltage comparator, and an
output logic driver.

When an input tone is present within the pass-band of

the circuit, the PLL synchronizes or "locks" on the in-
put signal. The quadrature detector serves as a lock in-
dicator: when the PLL is locked on an input signal, the
dc voltage at the output of the detector is shifted. This
dc level shift is then converted to an output logic pulse
by the amplifier and logic driver. The logic output at Pin
8 is an "open-collector" NPN transistor stage capable
of switching 10 mA current loads.

6-109
 XR·L567
The logic output at Pin 8 is normally in a "high" state, Vee
until a tone that is within the capture range of the de-
coder is present at the input. When the decoder is
locked on an input signal, the logic output at Pin 8 goes
to a "low" state.

Figure 3 shows the typical output response of the cir-

cuit for a tone-burst applied to the input, within the de- OUTPUT
tection band.

The center frequency of the detector is set by the free-

running frequency of the current-controlled oscillator in
the PLL. This free-running frequency, fo , is determined
by the selection of R1 and C1 connected to Pins 5 and
6, as shown in Figure 2. The detection bandwidth is de-
termined by the size of the PLL filter capacitor, C2 (see
Figure 10); and the output response speed is controlled
by the output filter capacitor, C3. Figure 2. XR-L567 Generalized Connection Diagram

DEFINITION OF DEVICE PARAMETERS Largest Detection Bandwidth

Center Frequency fo The largest detection bandwidth is the largest frequen-
cy range within which an input Signal above the thresh-
fo is the free-running frequency of the current- old voltage will cause a logical zero stage at the output.
controlled oscillator with no input signal. It is deter- The maximum detection bandwidth corresponds to the
mined by resistor R1 between Pins 5 and 6, and capaci- lock range of the PLL.
tor Cl from Pin 6 to ground. fo can be approximated by
Detection Band Skew
fo "" _1_Hz
R1 C 1 The detection band skew is a measure of how accu-
rately the largest detection band is centered about the
where R1 is in ohms and C1 is in farads. center frequency, f o . This parameter is graphically illus-
trated in Figure 4. In the figure, fmin and f max corre-
Detection Bandwidth (BW) spond to the lower and the upper ends of the largest de-
tection band, and f1 corresponds to the apparent cen-
The largest detection bandwidth is the frequency range ter of the detection band, and is defined as the
centered about f o , within which an input Signal larger arithmetic average of fmin and f max and fa is the free-
than the threshold voltage (typically 20 mV rms) will running frequency of the XR-L567 oscillator section.
cause a logic zero state at the output. The detection The bandwidth skew, ~fx, is the difference between
bandwidth corresponds to the capture range of the PLL these frequencies. Normalized to fo , this bandwidth
and is determined by the low-pass loop filter at Pin 2. skew can be expressed as:
Typical dependence of detection bandwidth on the filt-
er capacitance and the input signal amplitude is shown Bandwidth Skew = ~fx = (f max + fmin - 2fo)
in Figures 10 and 11, or may be calculated by the ap- fa 2fo
proximation
Vi (RMS)
BW (%) "" 338
INPUT
Vee
~'F+. +5V

20kO

XR·l567

OUTPUT
OUTPUT

47kO Response to 100 mV rms tone burst.

Rl
Cl
RL = 1K ohms
·Adjust lor 10 = 10 kHI
fj'" tOt,Hz. +5V ~ O.OO22,.F

Figure 3. Typical Output Response to 100 mV Input

Figure 1. XR-L567 Test Circuit Tone-Burst

6-110
XR·l567
If necessary, the detection band skew can be reduced stant of the filter can be expressed as T3 = R3C3,
to zero by an optional centering adjustment. (See Op- where R3 (47 kG) is the internal impedance at Pin 1.
tional Controls.)
If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
LARGEST DETECTION
BAND voltage change across C3 reaches the threshold volt-
OUTPUT
lOGIC LEVEL
I.- -I age. In certain applications, the delay may be desirable

[:.." -
as a means of suppressing spurious outputs. Con-

LJ Imln
-I ~
II
10 11 'm••
FREQUENCY
versely, if the value of C3 is too small, the beat rate at
the output of the quadrature detector may cause a
false logic level change at the output (Pin 8).

'0 :z PlL free-running frequency 'rna. + 'min The average voltage (during lock) at Pin 1 is a function
11 = Cenler Ireq. 01 deteellon band = - - 2 - of the in-band input amplitude in accordance with the
given transfer characteristic.
Figure 4. Definition of Bandwidth Skew
Logic Output (Pin 8)
DESCRIPTION OF CIRCUIT CONTROLS
Terminal 8 provides a binary logic output when an input
Input (Pin 3) signal is present within the pass-band of the decoder.
The logiC output is an uncommitted, open-collector
The input signal is applied to Pin 3 through a coupling power transistor capable of switching high current
capacitor. This terminal is internally biased at a dc level loads. The current level at the output is determined by
2 volts above ground, and has an input impedance level an external load resistor, RL, connected from Pin 8 to
of approximately 100 kG. the positive supply.

Timing Resistor R1 and Capacitor C1 (Pins 5 and 6) When an in-band Signal is present the output transistor
at Pin 8 saturates with a collector voltage of less than
The center frequency of the decoder is set by resistor 0.6V at full rated output current of 10 mA. If large out-
R1 between Pins 5 and 6, and capacitor C1 from Pin 6 put voltage swings are needed, RL can be connected to
to ground, as shown in Figure 2. a supply voltage, V +, higher than the VCC supply. For
safe operation, V + ::s; 15 volts.
Pin 5 is the oscillator squarewave output which has a
magnitude of approximately VCC - 1.4V and an aver- OPERATING INSTRUCTIONS
age dc level of VCC/2. A 5 kG load may be driven from
this point. The voltage at Pin 6 is an exponential triangle Selection of External Components
waveform with a peak-to-peak amplitude of .,. (VCC -
1.3)/3.5 volts and an average dc level of VCC/2. Only A typical connection diagram for the XR-L567 is shown
high impedance loads should be connected to Pin 6 to in Figure 2. For most applications, the following proce-
avoid disturbing the temperature stability or duty cycle dure will be sufficient for determination of the external
of the oscillator. components R1, C1, C2, and C3·

Loop Filter-C2 (Pin 2) 1. R1 and C1 should be selected for the desired center
frequency by the expression fo .,. 1/R1C1. For opti-
Capacitor C2 connected from Pin 2 to ground serves as mum temperature stability, R1 should be selected
a single pole, low-pass filter for the PLL portion of the such that 20 kG ::s; R1 ::s; 200 kG, and the R1C1 pro-
XR-L567. The filter time constant is given by T2 = duct should have sufficient stability over the project-
R2C2, where R2 (100 kG) is the impedance at Pin 2. ed operating temperature range.

The selection of C2 is determined by the detection 2. Low-pass capacitor, C2, can be determined from the
bandwidth requirements, as shown in Figure 10. For Bandwidth versus Input Signal Amplitude graph of
additional information see section on "Definition of De- Figure 10. One approach is to select an area of op-
vice Parameters." eration from the graph, and then adjust the input lev-
el and value of C2 accordingly. Or, if the input ampli-
The voltage at Pin 2, the phase detector output, is a lin- tude variation is known, the required f oC2 product
ear function of frequency over the range of 0.95 fo to can be found to give the desired bandwidth. Con-
1.05 fo, with a slope of approximately 20 mV/% fre- stant bandwidth operation requires Vi > 200 mV
quency deviation. rms. Then, as noted on the graph, bandwidth will be
controlled solely by the f oC2 product.
Output Filter-C3 (Pin 1)
3. Capacitor C3 sets the band edge of the low-pass fil-
Capacitor C3 connected from Pin 1 to ground forms a ter which attenuates frequencies outside of the de-
simple low-pass post detection filter to eliminate spuri- tection band and thereby eliminates spurious out-
ous outputs due to out-of-band signals. The time con- puts. If C3 is too small, frequencies adjacent to the

6-111
detection band may switch the output stage off and
XR·L567
der this condition, the lock-up transient is in a worst
on at the beat frequency, or the output may pulse off case situation, and the minimum theoretical lock-up
and on during the turn-on transient. A typical mini- time will not be achievable.
mum value for C3 is 2 C2.
The following expressions yield the values of C2 and
Conversely, if C3 is too large, turn-on and turn-off of C3, in microfarads, which allow the maximum operating
the output stage will be delayed until the voltage speeds for various center frequencies where fo is Hz.
across C3 passes the threshold value.
C2 = ~, C3 = 26 JtF
Precautions fo fo
1. The XR-L567 will lock on signals near (2n + 1) fo The minimum rate that digital information may be de-
and produce an output for signals near (4n + 1) fo, tected without lOSing information due to turn-on tran-
for n = 0,1 ,2-etc. Signals at 5 fo and 9 fo can sient or output chatter is about 10 cycles/bit, which cor-
cause an unwanted output and should, therefore, be responds to an information transfer rate of fo/10 baud.
attenuated before reaching the input of the circuit. In situations where minimum turn-off is of less impor-
tance than fast turn-on, the optional sensitivity adjust-
2. Operating the XR-L567 in a reduced bandwidth ment circuit of Figure 5 can be used to bring the qui-
mode of operation at input levels less than 200 mV escent C3 voltage closer to the threshold voltage. Sen-
rms results in maximum immunity to noise and out- sitivity to beat frequencies, noise, and extraneous
band signals. Decreased loop damping, however, signals, however, will be increased.
causes the worst-case lock-up time to increase, as
shown by the graph of Figure 13.
+V

r:;:::J
3. Bandwidth variations due to changes in the in-band
signal amplitude can be eliminated by operating the
XR-L567 in the high input level mode, above 200 mV.
The input stage is then limiting, however, so that out-
l::firCl
XR·L567

band signals or high noise levels can cause an ap-

parent bandwidth reduction as the in-band signal is DECREASE INCREASE
SENSITIVITY _
suppressed. In addition, the limited input stage will SENSITIVITY

create in-band components from subharmonic sig- +V

DECREASE
nals so that the circuit becomes sensitive to signals SENSITIVITY
at fo/3, fo/5 etc.

4. Care should be exercised in lead routing and lead

XR·L567 t-~IV'v-</~: t
INCREASE
lengths should be kept as short as possible. Power SENSITIVITY

supply leads should be properly bypassed close to

SILICON
the integrated circuit and grounding paths should be
carefully determined to avoid ground loops 'and un-
desirable voltage variations. In addition, circuits re-
quiring heavy load currents should be provided by a
I DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)

separate power supply, or filter capacitors increased

to minimize supply voltage variations.
Figure 5. Adjustable Sensitivity Connections
OPTIONAL CONTROLS
Chatter
Programming
When the value of C3 is small, the lock transient and ac
Varying the value of resistor R1 and/or capacitor C1 will components at the lock detector output may cause the
change the center frequency. The value of R1 can be output stage to move through its threshold more than
changed either mechanically or by solid state switches. once, resulting in output chatter.
Additional C1 capacitors can be added by grounding
them through saturated npn transistors. Although some loads, such as lamps and relays will not
respond to chatter, logic may interpret chatter as a se-
Speed of Response ries of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input (Pin 1)
The minimum lock-up time is inversely related to the or, by increasing the size of capacitor C3. Generally, the
loop frequency. As the natural loop frequency is low- feedback method is preferred since keeping C3 small
ered, the turn-on transients becomes greater. Thus will enable faster operation. Three alternate schemes
maximum operating speed is obtained when the value for chatter prevention are shown in Figure 6. Generally,
of capacitor C2 is minimum. At the instant an input sig- it is only necessary to assure that the feedback time
nal is applied, its phase may drive the oscillator away constant does not get so large that it prevents opera-
from the incoming frequency rather than toward it. Un- tion at the highest anticipated speed.

6-112
XR·l567
+V +V +V 15

~ ..... !\
\4.
0 "\
~

::
b
I
10
I\. ,
~
0
z
c
m
~
en
RA w
u
2K 10 101( a:
'OPTIONAL - PERMITS ...c
LOWER VALUE OF C,
o
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
Figure 6. Methods of Reducing Chatter CENTER FREQUENCY

Skew Adjustment Figure 9. Largest Detection Bandwidth Versus

Operating Frequency
The circuits shown in Figure 7 can be used to change
the position of the detection band (capture range) with-
in the largest detection band (lock range). By moving
the detection band to either edge of the lock range, in-
put signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on Ii:"
:1
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscil-
.
I

lator. 7... 1~~~-4--+-~~~4--4~

+v ~

~J
Ii:"

•
:1
~ 103~~-4~~~~--4--+~

l::Jir 02-~-1
CTI:R
::.
I
N

LO .... ERS 10 '::"

C2
1 ': "
RAISES 10
~

8 10 12
C3
C2
14 16
+v
BANDWIDTH - % OF 10

Figure 10. Detection Bandwidth as a Function

RAISES 10 of C2 and C3
lK
SILICON
OIOOES FOR
TEMPERATURE
}
COMPENSATION
(OPTIONAL)

'::"

Figure 7. Detection Band Skew Adjustment

300
CHARACTERISTIC CURVES ~
2.5 r-~r--~---r--"---'-----' en 250
::I 8200 1600 730 410 260 160 130 ~
IX:
>
2.0 E 200
c I
E W
I U
~ <I 150
z
w
a:
1.5 :0
a: > 100
:l ~
OPTIONAL
u :l
1.0 D. SENSITIVITY
...
>-
IL
l!: 50
ADJUSTMENT
D.
:l • ..., ---IL.--_+_-.- REQUIRED
en 0.5
10 12 14 16
BANDWIDTH - •• OF '0
10

SUPPLY VOLTAGE - VOLTS

Figure 11. Bandwidth Versus Input Signal Amplitude
Figure 8. Supply Current Versus Supply Voltage (C2 in J.LF)

6-113
 15
XR·L567
1000
14
12.5 12 500
S
10
400
300
""-
II.
0 10 ..... 200
r\.
~BANDWIDTH
~
, 8 III
'\ BY C2
LIMITED

--
III
:z:
l-
7.5 ...J
U
100
6
1\
"
e )-

i u
e 5.0 50
z 4 40 BANDWIDTH_
c( " LIMITED BY_
III ~ 30
2.5 2
:--
20 "- r<. /EXTERNAL
RESISTOR-
BANDWIDTH AT 25°C (MINIMUM C2)
10
-75 -50 -25 0 +25 +50 +75 +100 +125 1 2 3 4 5 10 20304050 100
TEMPERATURE. 'C BANDWIOnl (0/0 OF '0)

Figure 12. Bandwidth Variation With Temperature Figure 13. Greatest Number of Cycles Before Output

1.0 100
0.9
u
0.8 J ~a.
I
5
0
>
0.7
0.6 I
a.
~ -100
a:
-"\
l, I o
0.5 ci -200
-.,;~
u
u
..,
>
e
0.4
III
...a:
III -300
!\
<l
0.3
0.2 "a: -400
c(

~
\
c(
0.1
o -500
0.1 0.20.30.40.5 1.0 2 3 4 5 10 -25 2S 50 75
CENTER FREQUENCY - kHz TEMPERATURE. C

Figure 14. Power Supply Dependence of Center Frequency Figure 15. Typical Center Frequency Drift With Temperature
(V+ = 5V, R1 = 80 kO, fo = 1 kHz)

)-
u
ffi
:l
a
III
...
a: --.... r---...
a:
III
~ ... r-....
~
I-
Z
f"'o = f':
"1\\ ,
III 1 kH;t
~ -1

~ ~
o I
'0 = 10 ~Hz"'"
-
III
~ -2 v+ 5V

'"
:z:
u -3
j
I

~ -4
S. -25 o 25 50 75
TEMPERATURE. 'C

Figure 16. Typical Frequency Drift as a Function of

Temperature

6-114
 XR·2567

Dual Monolithic Tone Decoder

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2567 is a dual monolithic tone decoder of the
567-type that is ideally suited for tone or frequency de-
coding in multiple-tone communication systems. Each
decoder of the XR-2567 can be used independently or
both sections can be interconnected for dual opera-
tion. The matching and temperature tracking charac-
teristics between decoders on this monolithic chip are
superior to those available from two separate tone de-
coder packages.
The XR-2567 operates over a frequency range of 0.01
Hz to 500 kHz. Supply voltages can vary from 4.5V to
12V, with internal voltage regulation provided for sup-
plies between 7V and 12V. Each decoder consists of a
phase-locked loop (PLL), a quadrature AM detector, a
voltage comparator, and a logic compatible output that
can sink more than 100 mA of load current.
Operating Temperature
The center frequency of each decoder is set by an ex- XR-2567M - 55°C to + 125 DC
ternal resistor and capacitor which determine the free- XR-2567C ODC to + 70 DC
running frequency of each PLL. When an input tone is Storage Temperature - 65 DC to + 150 DC

•
present within the passband of the circuit, the PLL
"locks" on the input signal. The logic output, which is
ORDERING INFORMATION
normally "high", then switches to a "low" state during Part Number Package Temperature Range
this "lock" condition.
XR-2567CN Ceramic ODC to + 70 DC
FEATURES XR-2567CP Plastic ODC to + 70 DC I

Replaces two 567 -type decoders

Excellent temperature tracking between decoders SYSTEM DESCRIPTION
Bandwidth adjustable from 0 to 14 % The XR-2567 dual monolithic tone decoder consists of
Logic compatible outputs with 100 mA sink capability two independant 567-type circuits and an on board volt-
Center frequency matching (1 % typ.) age regulator. Each decoder has a phase detector, low
Center frequency adjustable from 0.01 Hz to 500 kHz pass filter, and current controlled oscillator which com-
Inherent immunity to false triggering prise the basic phase locked loop, plus an additional
Frequency range adjustable over 20:1 range by low pass filter and quadrature detector enabling detec-
external resistor. tion of in-band signals. Both devices have normally high
APPLICATIONS open collector outputs capable of sinking 100 mA.
Touch-Tone~ Decoding Full-Duplex Carrier-Tone The input signal is applied to Pin 14 (device A) or Pin 11
Sequential Tone Decoding Transceiver (device B), both with 20 kG nominal input resistance.
Dual-Tone Decoding/ Wireless Intercom Free running frequency is controlled by an RC network
Encoding Dual Precision at Pins 1 and 16 (device A) or Pins 8 and 9 (device B). A
Communications Paging Oscillator capacitor on Pin 2 (A), or Pin 7 (B) serves as the output
Ultrasonic Remote- FSK Generation and filter and eliminates out-of-band triggering. PLL filtering
Control and Monitoring Detection is accomplished with a capacitor on Pin 15 (A), or Pin
10 (B); bandwidth and skew are also dependant upon
ABSOLUTE MAXIMUM RATINGS the circuitry here. Bandwidth is adjustable from 0% to
Power Supply 14% of the center frequency. Pin 13 is +VCC (4.75 to
With Internal Regulator 14V 12V nominal, 14V maximum); Pin 7 is ground; and Pin 3
Without Regulator (Pins 12 and 13 shorted) 10V (A) or Pin 6 (B) is the open collector output, pulling low
Power Dissipation when an in-band signal triggers the device.
Ceramic Package 750 mW Voltage supplies below 7V necessitate bypassing the
Derate Above + 25°C 6 mW/oC internal regulator. This is accomplished by shorting Pin
Plastic Package 625 mW/oC 12 to VCC; for supplies over 7V, a bypass capacitor of
Derate Above + 25°C 5.5 mW/oC at least 1 IJ.F should AC ground Pin 12.

6-115
 XR·2567
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee = + 5V, TA = 25° e, unless otherwise specified.Test circuit of Figure 2, 81 closed unless
otherwise specified.

LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
GENERAL
Supply Voltage Range
Without Regulator 4.75 7 Vdc See Figure 5, S1 closed.
With Internal Regulator 6.5 12 Vdc See Figure 5, S1 open.
Supply Current (both decoders) See Figure 7, 8
Quiescent XR·2567M 12 16 mA RL = 20 kO
XR-2567C 14 20 mA RL = 20 kO
Activated XR-2567M 22 26 mA RL = 20 kO
XR-2567C 24 30 mA RL = 20 kO
Output Voltage 15 V
Negative Voltage at Input -10 V
Positive Voltage at Input VCC+0.5 V
CENTER FREQUENCY (each decoder section)
Highest Center Frequency 100 500 kHz
Center Frequency Stability
Temperature TA = 25°C 35 ppmloC See Figure 14
OO<TA<+70°C ±60 ppmloC See Figure 14
-55°<TA<+125°C ±140 ppmloC See Figure 14
Supply Voltage
Without Regulator
XR-2567M 0.5 1.0 %N to = 100 kHz
XR-2567C 0.7 2.0 %N to = 100 kHz
With Internal Regulator
XR-2567M 0.05 %N to = 100 kHz, VCC = 9V
XR-2567C 0.1 %N to = 100 kHz, VCC = 9V

DETECTION BANDWIDTH
(each decoder section)
Largest Detection Bandwidth
XR-2567M 12 14 16 % otto to = 100 kHz
XR-2567C 10 14 18 % otto to = 100 kHz
Largest Detection Bandwidth Skew
XR-2567M 1 2 % otto
XR-2567C 1 3 % otto
Largest Detection Bandwidth Variation
Temperature ±0.1 %IOC Yin = 300 mV rms
Supply Voltage ±2 %N Vin = 300 mV rms
INPUT (each decoder section)
Input Resistance 20 kO
Smallest Detectable Input Voltage 20 25 mVrms I L = 100 mA, ti = to
Largest No-Output Input Voltage 10 15 mVrms I L = 100 mA, ti = to
Greatest Simultaneous Outband
Signal to Inband Signal Ratio +6 dB
Minimum Input Signal to Wideband
Noise Ratio -6 dB Noise BW = 140 kHz
OUTPUT (each decoder section)
Output Saturation Voltage = 30 mA, Yin = 25 mV rms
II
0.2 0.4 V IL
0.6 1.0 V IL = 100 mA, Vin = 25 mV rms
Output Leakage Current 0.01 25 p.A
Fastest ON-OFF Cycling Rate tn/20
Output Rise Time 150 ns RL = 500
Output Fall Time 30 ns RL = 500
MATCHING CHARACTERISTICS
Center Frequency Matching 1 % to = 10 kHz
Temperature Dritt Matching ±20 ppmloC O°C<TA <70°C
±50 ppmloC - 55°C<TA < 125°C

6-116
 The largest detection bandwidth is the largest frequen-
cy range within which an input signal above the thresh-
old voltage will cause a logical zero state at the output.
The maximum detection bandwidth corresponds to the
lock range of the PLL.

The detection band skew is a measure of how accu-

rately the largest detection band is centered about the
center frequency, fo . It is defined as (f max + fmin -
2fo)/fo, where f max and fmin are the frequencies corre-
sponding to the edges of the detection band. If neces-
OUTPUT
sary, the detection band skew can be reduced to zero
OUTPUT
B by an optional centering adjustment. (See Optional
! Controls.)

Figure 2. Test Circuit DESCRIPTION OF CIRCUIT CONTROLS

INPUT (Pins 11 and 14)

The input signal is applied to Pins 14 and/or 11 through

a coupling capacitor, Cc . These terminals are internally
biased at a dc level 2 volts above ground and they have
an input impedance level of approximately 20 kO.

TIMING RESISTOR R1 AND CAPACITOR C1 (Pins 1, 8, 9,

and 16)

The center frequency, fo, of each decoder section is set

•
by a resistor Rl and a capacitor Cl. R1A is connected
between Pins 1 and 16 in decoder section A, and Rl B
between Pins 8 and 9 of decoder section B. C1A is con-
Response to 100 mV rms tone burst nected from Pin 1 to ground, and Cl B from Pin 8 to
RL c 100 ohms ground, as shown in Figure 4. R1 and Cl should be se·
lected for the desired center frequency by the expres-
Figure 3. XR-2567 Typical Response sion fo "'" 1/R1Cl. For optimum temperature stability, I
Rl should be selected such that 2 kO :::;; R1 :::;; 20 kO,
and the Rl Cl product should have sufficient stability
over the projected operating temperature range.

DEFINITIONS OF XR-2567 PARAMETERS

fo is the free-running frequency of the current-
controlled oscillator of the PLL with no input signal. It is
determined by resistor Rl and capacitor Cl; fo can be
approximated by

where Rl is in ohms and Cl is in farads.

The detection bandwidth is the frequency range cen-

tered about fo, within which an input signal larger than
the threshold voltage (typically 20 mV rms) will cause a
"logic zero" state at the output. The detection band-
Cc COUPLING CAPACITOR SI OPlN FOR 7V TO 12V
width corresponds to the capture range of the PLL and CB BYPASS CAPACITOR
OPERATION CLOSED
FOR 4.SV TO 7V OPERATION
is determined by the low-pass bandwidth filter. The
bandwidth of the filter, as a percent of fo, can be deter-
mined by the approximation Figure 4. Circuit Connection Diagram

~
BW"", 1070 -
i For decoder section A, the oscillator output can be ob-
foC2 tained at either Pin 1 or 16. Pin 16 is the oscillator
squarewave output which has a magnitude of approxi-
where Vi is the input signal in volts, rms, and C2 is the mately VCC - l.4V and an average dc level of VCC/2. A
capacitance in J1.F at Pins 10 or 15. 1 kO load may be driven from this point. The voltage at
6-117
TYPICAL CHARACTERISTICS
XR·2567
1000 ,..--""T""---r----,--.,.....--, 1.0

0.9

800 0.8
I
i
I 5 0.7
I
z
0 600 ~ 0.6
I 40

II
~ I 0.5 30~~--+-~~
iii
15 400 >~ o.~
~ ~ 0.3
I
~
200 0.2
V
10~~~-4--+--+-~-4
o. 1 lL
o ... r- ~
4 6 8 10 12 1 2 3 4 5 10 20 30 40 50 100 5 7 B 10
SUPPLY VOLTAGE. V' IVOLTS) CENTER FREQUENCY - kH, SUPPLY VQLTAGE. V' IVDLTS)

Figure 5. Internal Power Dissipation Figure 6. Power Supply Dependence Figure 7. Total Supply Current vs.
vs. Supply Voltage. Both Units of Center Frequency Supply Voltage for Operation Without
Activated, RL = 20 k Internal Regulator (Pins 12 and 13
Shorted)
60 5

1
1
50 I\.
\
250
1 1 1 1 1 1 )(
%

... RECOMMENDED OPERATING RANGE

..
o
.. ~ ~:
z
a:
WITH REGULATOR
I 10 I\. N

:J
u
...o
%

" ~150
~
>-
:J ~ g
.
..J

...0
§ roo
~

10 11 12
o 4 6 10 12 14 16
l00H. 1 KHz 10 KHz 100 KHz 1 MHz
SUPPLY VOLTAGE. V' IVOLTS) CENTER FREQUENCY BANDWIDTH - " OF '0

Figure 8. Total Supply Current vs. Figure 9. Largest Detection Figure 10. Bandwidth vs. Input
Supply Voltage for Operation with Bandwidth Signal Amplitude (C2 In ",F)
Internal Regulator (Pins 12 and 13
Not Connected)
1000 108 15

500
400
"' :~ 12.5 12

..
300
200 "' I\. %
105
_0

0 10
-
'\
~ ~~
'{ANDWIDTH LIMITED
BYC 2
~ ~
100 :r
~
7.5
1\

"
0

50 ~ -,,-
~
- r-
40 % 10· 6.0
'\.
30
~ "", r'-.. ~
i'-- ~
-
20 '\. ANDWIDTH LIMITED BY 2.5
I\:ERNAL RESISTOR .......... C3
IMI~'M~M,Cf) BANDWIDTH AT 25'C
""'- C2
2 3 4 5 10 20 30.050 100 103 0
o 10 12 14 16 -75 -50 -25 25 50 '75 +100 +125
BANDWID'TH '" 0"0) TEMPERATURE -'C
BANDWIDTH - " OF '0

Figure 11. Greatest Number of Figure 12. Detection Bandwidth as a Figure 13. Bandwidth Variation With
Cycles Before Output Function of C2 and C3 Temperature
~ 3.0
'0.' kHz
15 2.0
a: Vce· 4.75V~

l 1-:: ~ .-
1.0
"zZ
~ ::::..~ r,...-
r~ l7 ........
!~::: I
Vee· 5.75V

VCC· 7.0V/
[>....
r'\.
~ -3.0

~ -4.0
I I
0
'<J -5.0
-75 -50 -25 0
I I
25 50 75 100 125
SUPPLY VOLTAGE - VOLTS
TEMPERATURE T I'C)

Figure 14. Frequency Drift With Figure 15. Temperature Coefficient of

Temperature Center Frequency (Mean and S.D.)
6-118
pin 1 is an exponential triangle waveform with a peak- LOGIC OUTPUT (Pins 3 and 6)
to-peak amplitude of 1 volt and an average dc level of
VCC/2. Only high impedance loads should be connect- Output terminals 3 and 6 provide a binary logic output
ed to Pin 1 to avoid disturbing the temperature stability when an input signal tone is present within the
or duty cycle of the oscillator. For section B, Pin 9 is the detection-band of each respective decoder section.
squarewave output and Pin 8 the exponential triangle The logiC outputs are uncommitted "bare-collector"
waveform output. power transistors capable of switching high current
loads. The current level at the output is determined by
LOOP FILTER, C2 (Pins 10 and 15) an external load resistor, RL, connected from VCC to
Pins 3 or 6.
Capacitors C2A and C2B connected from Pins 15 and
10 to ground are the single-pole, low-pass filters for the When an in-band signal is present, the output transistor
PLL portion of decoder sections A and B. The filter time at Pins 3 or 6 saturates with a collector voltage less
constant is given by T2 = R2C2, where R2 (10 kO) is the than 1 volt (typically 0.6V) at full rated current of 100
impedance at Pins 10 or 15. The selection of C2 is de- mAo If large output voltage swings are needed, RL can
termined by the detection bandwidth requirements and be connected to a supply voltage, V + higher than the
input signal amplitude as shown in Figures 10 and 12. VCC supply. For safe operation, V + ::;; 15 volts.
One approach is to select an area of operation from the
graph and then adjust the input level and value of C2 REGULATOR BY-PASS (Pin 12)
accordingly. Or, if the input amplitude variation is
known, the required foC2 product can be found to give This pin corresponds to the output of the voltage regu-
the desired bandwidth. Constant bandwidth operation lator section. For circuit operation with a supply voltage
requires Vi > 200 mV rms. Then, as noted in Figure 10, greater than 7V, Pin 12 should be ac grounded with a
bandwidth will be controlled solely by the foC2 product. bypass capacitor ~ 1 p.F. For circuit operation over a
(For additional information, see Optional Controls Sec- supply voltage range of 4.5 to 7V, the voltage regulator
tion, "Speed of Response" and "Bandwidth Reduc- section is not required; Pin 12 should be shorted to
tion".) VCC·

Pins 10 and 15 correspond to the PLL phase detector GROUND TERMINALS (Pins 4 and 5)
outputs of sections A and B, respectively. The voltage
To eliminate parasitic interaction, each decoder section
level at these pins is a linear function of frequency over
has a separate ground terminal. The internal regula-
the range of 0.95 to 1.05 fo, with a slope of approxi-
tor shares a common ground with decoder section A
mately 20 mV/% frequency deviation.
(Pin 4).
OUTPUT FILTER, C3 (Pins 2 and 7)
Independent ground terminals also allow additional
Capacitors C3A and C3B connected from Pins 2 and 7 flexibility for split supply operation. Pin 4 can be used as
to ground form low-pass post detection filters for sec- V -, and Pin 5 as ground, as shown in Figure 16. When
tions A and B respectively. The function of the post de- the circuit is operated with split supplies, the positive
tection filter is to eliminate spurious outputs caused by supply should always be > 6V, and the dc potential
out-of-band Signals. The time constant of the filter can across Pins 13 and 14 should not exceed 15 volts.
be expressed as T3 :::: R3C3, where R3 (4.7 k) is the in-
ternal impedance at Pins 2 or 7.
v' 'FOR OPERATION WITH vt 0:: 7V,
The preCise value of C3 is not critical for most applica- SHORT PINS 12 ANO 13

tions. To eliminate the possibility of false triggering by

spurious signals, a minimum value for C3 is 2C2, where
C2 is the loop filter capacitance for the corresponding
decoder section. If C3 is smaller than 2C2, then fre-
quencies adjacent to the detection band may switch
the output stage "off" and "on" at the beat frequency,
or the output may pulse "off" and "on" during the turn-
on transient.
(NOTE DC vOLTAGE ATPIN4
If the value of C3 becomes too large, the turn-on or MUST ALWAYS BE ' .. PIN !II

turn-off time of the output stage will be delayed until the

voltage change across C3 reaches the threshold volt-
age. In certain applications, this delay may be desirable Figure 16. Split-Supply Operation Using Independent Ground
as a means of suppressing spurious outputs. (For addi- Terminals of Units A and B. Unit A Operates
tional information, see Optional Controls Section, Between V+ and V - ; Unit B Operates Between
"Speed of Response" and "Chatter".) V + and Ground

6-119
 XR·2567 v' v' v'
OPTIONAL CONTROLS
SPEED OF RESPONSE ".
200 TO 11(

The minimum lock-up time is inversely related to the

loop frequency. As the natural loop frequency is low-
ered, the turn-on transient becomes greater. Thus, max-
imum operating speed is obtained when the value of ca- ".
200 TO 11(

pacitor C2 is minimum. At the instant an input signal is 'OPTIONAL - PE AMITS

LOWER VALUE OF C,
applied, its phase may drive the oscillator away from
the incoming frequency rather than toward it. Under Figure 18. Methods of Reducing Chatter
this condition, the lock-up transient is in a worst case
situation, and the minimum theoretical lock-up time will
not be achievable. SKEW ADJUSTMENT
The following expressions yield the values of C2 and The circuits shown in Figure 19 can be used to change
C3, in microfarads, which allow the maximum operating the position of the detection band (capture range) with-
speeds for various center frequencies. The minimum in the largest detection band (or lock range). By moving
rate that digital information may be detected without the detection band to either edge of the lock range, in-
losing information due to turn-on transient or output put signal variations will expand the detection band in
chatter is about 10 cycles/bit, which corresponds to an one direction only. Since R3 also has a slight effect on
information transfer rate of fo/1 0 baud. the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscil-
C2 = 130, C3 = 260 lator.
fo fa
v'
In situations where minimum turn-off time is of less im- "I lOW£RS'o
portance than fast turn-on, the optional sensitivity ad- ~-"N---<: ~~K 1
justment circuit of Figure 17 can be used to bring the RAISES to

quiescent C3 voltage closer to the threshold voltage. ~~

Sensitivity to beat frequencies, noise, and extraneous SIl'CON
DtODES

signals, however, will be increased. '0'

TEMPERATURE
} COMPENSAT10~
(OPTIONALI

"
DfCfltASt
v' SENSITlvlTV
Figure 19. Connections to RepOSition Detection Band

EMXA~iS67

DECREASE
SENSITIVITY
'lOJ\7

Ie,
"=
RC
INCREASE
SENSITIVITy

~\~g~iFOR
} TfMPERA,TURE
COMPENSATIO~
IOPTIONA.l\
OUTPUT LATCHING

After a signal is received, the output of either decoder

section can be latched "on" by connecting a 20 kG re-
sistor and diode from the "output" terminal to the "out-
Figure 17. Optional Connections for Sensitivity Control put filter" terminal as shown in Figure 20. The output
stage can be unlatched by raising the voltage level at
the output filter terminal.

CHATTER
v' v' v'

When the value of C3 is small, the lock transient and ac

components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.

Although some loads, such as lamps and relays will not

respond to chattei, "logic" may inierpret chatter as a C" PREVENTS LATCH UP
WHE'NPOWERSUPPlV,S
TUFlNEOON.
series of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input or, by
increasing the size of capacitor C3. Generally, the feed-
Figure 20. Output latching
back method is preferred since keeping C3 small will
enable faster operation. Three alternate schemes for POSITIONING OF DETECTION BANDS
chatter prevention are shown in Figure 18. Generally, it
is only necessary to assure that the feedback time con- Figure 21 defines the respective band-edge and band-
stant does not get so large that it prevents operation at center frequencies for sections A and B of the dual tone
the highest antiCipated speed. decoder.

6-120
XR·2567
Frequencies fL and FH with appropriate subscripts re- 0

PINIO
fer to the low and the high band-edge frequencies for 051<09,.; ,4k 19K 25K l2K <OK OR,S RA,

decoder sections A and B, and fa is the center frequen- / / // /

cy. 0
( / II /IOK f'

'.
I I /'/ v/ /'
J I /Z v,o< OP1IO,..AlSILtCON
OIOO(S FOR

lilL Ih V'OOK
T['w'IP(RATURE
COVPENSATIQ"'l

/' .,- v r"1

I
DETECTION HANO
OF UNIT A. I I
DETECTION BAND
OF UNIT a I ~ /- A

!~ (!.9i !) '.C1,.~:r; (~O~~.~)

6

ll~
o
o 'I .. 6 8 10 12 14 16 NOH ADJUST CO"lTROL fOR SYMMETRV OF
DETECTION BAIljO EDGES ASOUT '"
OEreCTIONBANO -%011 0

5 foA 'oB __

FREQUENCY
Figure 22. Bandwidth Reduction

(a) Independent Detection of "TWo Separate Tones

APPLICATIONS
DUAL-TONE DETECTION

In most dual-tone detection systems, the decoder out-

put is required to change state only when both input
FREQUENCY
tones are present simultaneously. This can be imple-
mented by setting the detection bandwidth of each of
(b) Addition of Detection Bandwidth for Wide· Band the XR-2567 decoder sections to cover one of the input
Detection tones; and then connecting the respective outputs
through a NOR gate, as shown in Figure 23. In this
TOTAL OETECTION
case, the output of the NOR gate will be "high" only
r-
BANO

-j when bath input tones are present simultaneously.

~ foA foB
FREQUEf-ICV

(c) Subtraction of Bandwidths for Narrow·Band Detection

Figure 21. Positioning of Detection Bands

The two sections can be interconnected to form a sin-

gle tone detector with an overall detection bandwidth
equal to the sum or the difference of the detection
bands for the two individual detector sections. For ex-
ample, if the individual decoder sections are intercon-
nected as shown in Figure 25, then the total detection
bandwidth would be approximately equal to the sum of
the respective bandwidths as shawn in Figure 21 (b). 1/4 SN7402
Similarly, if the decoders are interconnected as shawn
in Figure 23, then the overall detection band would be
equal to the difference, or the overlap, between the reo Figure 23. Connection for Decoding Dual-Tone Encoded Input
spective bandwidths as shawn in Figure 21(C). Signals

BANDWIDTH REDUCTION
Figure 24 shows additional circuit configurations which
The bandwidth of each decoder can be reduced QY ei- can be used for decoding multiple·tone input signals. In
ther increasing the loop filter capacitor C2 or reducing Figure 24(a), the output of Unit A is connected to the
the loop gain. Increasing C2 may be an undesirable so- output filter (Pin 7) of Unit B through the diode 01. If no
lution since this will also reduce the damping of the input tone is present within the detection-band of Unit
loop and thus slow the circuit response time. A, then its output (pin 3) is "high", which keeps diode
D1 conducting and "disables" Unit B by keeping its out·
Figure 22 shows the proper method of reducing the put (pin 6) "high". If an input tone is present within the
loop gain for reduced bandwidth. This technique will im- detection-band of Unit A, Pin 3 is law, diode D1 is re-
prove damping and permit faster performance under verse biased, and decoder B is no longer disabled. If
narrow band operation. Bandwidth reduction can also under these conditions an input signal is present within
be obtained by subtracting overlapping bandwidths of the detection-band of Unit B, then its output at Pin 6
the two decoder sections (see Figures 21(c) and 23). would be "low". Thus, the output at Pin 6 is "law" only

6-121
 XR·2567
when input tones within the detection-band of A and B SEQUENTIAL TONE DECODING
are present simultaneously.
Dual-tone decoder circuits can also be used for se-
The dual-tone decoder circuit of Figure 24(b) makes quential tone decoding where one tone must be present
use of the split-ground feature of the XR-2567. The out- before the other for the circuit to operate. This can be
put terminal of Unit A is used as a "switch" in series achieved by making the output filter capacitance, C3,
with the ground terminal (Pin 5) of Unit B. If the input of one of the sections large with respect to the other.
tone A is not present, Pin 3 is at its high-impedance For example, in the circuits of Figures 24(a) and 24(b), if
state, and the ground terminal of Unit B is open- C3A is chosen to be much larger than C38 (C3A ?;
circuited. When the input tone A is present, Pin 3 goes C38), then Unit A will remain "on" and activate 8 for a
to a low-impedance state and Unit B is activated. In this finite time duration after tone A is terminated. Thus, the
manner, the output of Unit 8 will be "low" only when circuit will be able to detect the two tones only if they
both tones A and 8 are present. are present sequentially, with tone A preceding tone 8.

In the circuit connection of Figure 24(b), Unit 8 does The circuit of Figure 24(a) can also be modified for se-
not draw any current until it is activated. Therefore, its quential tone decoding by addition of a diode, D2, be-
power dissipation in a stand-by condition is lower than tween pins 3 and 6. Once activated by Unit A, Unit 8
other dual-tone decoder configurations. However, due will stay "on" as long as tone 8 is present, even though
to finite series resistance between Pin 3 and ground tone A may terminate. Once tone 8 disappears, the cir-
when Unit 8 is activated, the output current sink capa- cuit is reset to its original state and would require tone
bility is limited to s 10 rnA. A to be present for activation.

HIGH-SPEED NARROW-BAND TONE DECODER

The circuit of Figure 23 can be used as a narrow-band

tone decoder by overlapping the detection bands of
Units A and 8 (see Figure 21 (c». The output of the NOR
gate will be high only when an input signal is present
within the overlapping portions of the detection band.
To maintain uniform response within the pass-band, the
input signal amplitude should be ?; 80 mV rms. For
minimum response time, PPL filter capacitors C2A and
C28 should be:

C2A = C28 == ~~F

fa (Hz)

Under this condition, the worst-case output delay is

v' o---'\NI.~+--D+--+---l "'" 10 to 14 cycles of the input tone.
1.0Kll I ~-AN\___ - - - o v'
t.--W~ The practical matching and tracking tolerances of indi-
vidual units limit the minimum bandwidth to "'" 4 % of fa.
(a)
WIDE-BAND TONE DECODER

Figure 25 is a circuit configuration for increasing the

detection bandwidth of the XR-2567 by combining the
respective bandwidths of individual decoder sections. If
the detection bands of each section are located adja-
cent to each other as shown in Figure 21(b), and if the
two outputs (pins 3 and 6) are shorted together, then
the resulting bandwidth is the sum of individual band-
widths. In this manner, the total detection bandwidth
can be increased to 24 % of center frequency. To main-
tain uniform response throughout the pass band, ii-Ie in-
put signal level should be ?; 80 mV, rms, and the re-
spective pass-bands of each section should have
"'" 3 % overlap at center frequency.

TONE TRANSCEIVER

The XR-2567 can be used as a full-duplex tone trans-

(b)
ceiver by using one section of the unit as a tone detec-
tor and the remaining section as a tone generator.
Figure 24. Additional Dual-Tone Decoding Circuits Since both sections operate independently, the circuit

6-122
 XR·2567
"

RECEIVER
!OUTPUT

i'lL TRANSMITlER
OUTPUT

!--+-'-C}----4--<I! 1Ulf

Cc • COUPLING CAPACITOR

Figure 25. Wide-Band Tone Detection

Cc • COUPLING CAPACITOR
can transmit and receive simultaneously. A recom-
mended circuit connection for transceiver applications
is shown in Figure 26. In this case, Unit A is utilized as
Figure 26. Tone Transceiver
the receiver, and Unit B is used as the transmitter. The
transmitter section can be keyed "on" and "off" byap-
plying a pulse to pin 8 through a disconnect diode D1.
The oscillator section of Unit B will be keyed "off" when
the keying logic level at pin 8 is at a "low" state.

•
The output of the transmitter section (Unit B) can also Your
be frequency modulated over a + 6 % deviation range
by applying a modulation signal to pin 10.

HIGH CURRENT OSCILLATOR

I

The oscillator output of each section of XA-2567 can be •• FOR Vee"-: 711

amplified using the high current logic driver sections of SHQRTPIN 12TOPIN 13.

the circuit. In this manner, each section of the circuit

can switch 100 mA loads, without sacrificing oscillator
stability. A recommended circuit connection for this ap- Figure 27. Precision Oscillator with High Current Output
plication is shown in Figure 27. The oscillator frequency Capability
can be modulated over ± 6 % of fo by applying a control
voltage to pins 15 or 10.

6-123
6-124
 Cross References & Ordering Information

I Telecommunication Circuits

Data Communication Circuits

Computer Peripheral Circuits

I Industrial Circuits

I Instrumentation Circuits

I Special Function Circuits

I User Specific Linear ICs

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information
--------
Authorized Sales Representatives & Distributors
.1
1

7
 Section 7 - Interface Circuits
Display Drivers . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
XR-2271 Fluorescent Display Driver . . . . . . . . . . . 7-2
XR-2272 High Voltage 7-Digit Display Driver . . . . . . 7-4
XR-2284/2288 High Voltage AC Plasma Display Drivers 7-7
XR-6118/6128 Fluorescent Display Drivers . . . . . . . 7-11
High Current Drivers . . . . . . . . . . . . . . . . . . . . . . 7-15
XR-2001/2002/2003/2004 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
XR-2011/2012/2013/2014 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . .. 7-20
XR-2200 Hammer Driver . . . . . . . . . . . . . . . . . . . . . . 7-24
XR-2201/2202/2203/2204 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . 7-26

7-1
 XR-2271

Fluorescent Display Driver

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2271 is a monolithic 7-digit or 7-segment dis-
play driver designed to interface MaS logic with fluores-
cent displays. It features active high logic and low input
current. Each XR-2271 is capable of driving seven digits
or segments of a display panel and provides complete
input and output isolation. Since the output pull up re-
sistors are incorporated on chip, no external parts are
required to interface fluorescent displays.

INPUTS

FEATURES
Active High Logic
Low Input Current
Complete Input Output Isolation
Output Pull Up Resistors On Chip
No External Parts Required To Drive
Fluorescent Displays

APPLICATIONS
Fluorescent Display Driver
MaS Logic/High-Voltage Interface ORDERING INFORMATION
Part Number Package Operating Temperature
XR-2271CN Ceramic O°C to + 70°C
XR-2271CP Plastic O°C to + 70°C

ABSOLUTE MAXIMUM RATINGS (Note 1)

SYSTEM DESCRIPTION
VSS - V - 50V Max.
inpui io V- 50V Max. The XR-2271 fluorescent display driver requires no ad-
Outputs to V- 50V Max. ditional components to interface seven segment fluo-
ISS 20 mA Max. rescent displays to MaS Logic. The output is an emitter
Power Dissipation TA :S 25°C 625 mW Max. follower and can switch up to 50V at 20 mA. All inputs
Derate above 25°C 5 mW/oC are protected to 50V and pull up resistors are inte-
Storage Temperature -65°C to + 150°C grated onto the device.

7-2
ELECTRICAL CHARACTERISTICS (TA = + 25°C, VSS = OV, V- -40V, Note 2)
XRII2271
PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS
Logical "1"
-1.2 0 V Vin on
Va = -2.0V
Input Voltage 10 = -7.5 mA
Logical "0"
Input Voltage
-6 V Vin off Vo = V- +2V
Logical "1"
0.25 0.8 mA lin on
Vin = -1.2V
Input Current Va = -2.0V
Logical "0"
Va = V- +2V
Input Current
-50 0 50 p.A lin off Vin = -6V
-90 p.A Vin = -15V
Logical "1"
Vo on Va on
Output Voltage -2.0 -0.9 0 V
Logical "0"
Output Voltage
-40 -38 V Vo off Vin = -6V

Output Pull Vin = -6V

45 KO RO
Down Resistance Note 3
Vo = -5V
Output Pull
350 p.A IS Vin = -6V
Down Current
Note 3
Power Supply -1.2 -1.4 mA I-off All inputs -6V
Current -7 -12.0 mA I-on All inputs - 1.2V

AC Parameters (TA = +25°C, Test Circuit Figure 2)

PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS

Output on CL = 25 pF

•
1 5 p.S td
Delay Time RL = 10 KO
Output on
0.5 2 p.S tr
CL = 25 pf
Rise Time RL = 10K
Output off CL = 25 pF
0.8 5 p.S ts
Storage Time RL = 10 KO

Output off 0.6 2.0 p.S

CL = 25 pF
Fall Time 2 25 p.S tf RL = 10K
RL = 00
Note 1. The "Absolute Maximum Ratings" are those values beyond which the device may be damaged.
Note 2. All voltages measured with respect to VSS unless otherwise noted. Positive current flow is into a device pin.
Note 3. The output pull down resistance is an N channel junction FET. For Vo ,.. V - it is resistive, and for IVo -
(V - ) I > 20V, it is current sink.
12v

15
'NPUT~ lV ., 3V

I I
r----- .v I I 'R I I

-+I~ ~~

:'__ +___ ;.
INPUT
I ov-- f- _____ """ I
115-91
OlHPUT
I~'DI
~ I II

ton tolt

I
I
I
I TYPICAL
l2~~~E~ __ _
1
v-

EQUIVALENT SCHEMATIC DIAGRAM Figure 2. XR-2271 AC Parameter Test Circuit

7-3
 XR-2272

High-Voltage 7-Digit Display Driver

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2272 is a monolithic high voltage display driver
array specifically designed to drive gas-filled digit dis-
plays. The circuit is made up of seven independent digit
driver sections in the same monolithic package. Its
main application is to act as buffer interface between
MOS outputs and the anodes of a gas discharge panel.
The XR-2272 is particularly well suited to interfacing
with Panaplex II type displays.

FEATURES
Active Low Inputs
High Breakdown Voltage
Low Power Dissipation
Complete Input-Output Isolation
On-Chip Pull-Up Resistors
Versatility for Display Interface

APPLICATIONS
Gas Discharge Display Driver
Panaplex Display Driver
MOS Logic to High-Voltage Interface

ORDERING INFORMATION

Part Number Package Operating Temperature

ABSOLUTE MAXIMUM RATINGS
XR-2272CN Ceramic O°C to + 70°C
Supply Voltage ( - VEE) - 75V Max. XR-2272CP Plastic O°C to + 70°C
Output on Current Each Output - 20 mA Max.
Output on Current All Combined - 50 mA Max.
Positive Supply Current Iss 60 mA Max.
Input Current ± 3 mA Max. SYSTEM DESCRIPTION
Input Voltage - VEE, Min., VSS, Max.
Package Power Dissipation, 25°C 625 mW (Plastic) The XR-2272 high voltage display driver features seven
Derating above 25°C 5 mW/oC independent sections, each capable of switching - 75
Operating Temperature Range O°C to + 700C V at up to 20 mA. Each has active low inputs and mono-
Storage Temperature Range - 65°C to 150°C lithic pull-up resistors. The output is an emitter follower.

7-4
 XR·2272

r----- - - --.
I
,
I
I
I I
I I
I I
I I
I I
I I
INPUT OUTPUT
(9-15) (2-8)
I I
I I
I I
I TYPICAL
U...9~7~~VERS _ J
I
•
EQUIVALENT SCHEMATIC DIAGRAM

7-5
 XR·2272
ELECTRICAL CHARACTERISTICS (TA = +25°C, VSS = OV, V- - 60V, Note 1)
PARAMETERS MIN TYP MAX UNITS SYMBOL CONDITIONS
Input Off Voltage -1.8 -1.2 V Vin off 10 = -5 p,A
Input Off Current -20 p,A lin off Vin = -1.2V
10 = -5 p,A
Input On Voltage -6 V Vin on Va = -1.4V
10 = -15 mA
Input On Current -600 -250 -100 p,A lin on Va = -1.4V
10 = -15mA
Output Off Voltage -60 -48 V Va off Vin = -1.2V
Output On Voltage -1.4 -0.9 0 V Va on Vin = -6V
10 = -15 mA
Output Pull 45 KO RO Vin = -6V
Down Resistance Note 2
Output Pull 350 p,A IS Va = -5V
Down Current Vin = -6V
Note 2
Supply Current
Off State 1 150 p,A 1- All inputs at - 1.2V
One Segment On 0.35 2 mA l- One input at - 6V
All Segments On 2.2 6 mA 1- All inputs at - 6V

AC Parameters (TA = + 25°C, Test Circuit Figure 2)

Output on Delay Time 1 5 p,S td CL = 25 pF
RL = 10 KO
Output on Rise Time 0.5 2 p,S tr CL = 25 pF
RL = 10 K
Output off Storage Time 0.8 5 p,S ts CL = 25 pF
RL = 10 KO
Output off Fall Time 0.6 2.0 p,S tf CL = 25 pF
2 25 p,S RL = 10K
RL = 00
..
Note 1. All voltages measured with respect to VSS unless otherWise noted. Positive current flow IS Into a device
pin.
Note 2. The output pull down resistance is an N-Channel junction FET. For Va "" V - it is resistive, and for IVa -
(V -) I > 20V, it is a current sink.

-12V

-3\1. 7/
INPUT

m1
'"'"' -
I I
.I
OUTPUT

f' f"'
I

OUTPUT
ov
i '0
t----j
I
"I-'-R.,.,--6-V.""
~
!-
I
I
-3v

;-t~~_'! -1
I
I
I
-60V 40V
- - - -.....--,
I __
I

1 ___

I
- -+- --- --
:

! '011
t-~ f--------- -+

Figure 2. XR-2272 AC Parameter Test Circuit Figure 3. AC Test Waveforms

7-6
 XR-2284/2288

High-Voltage AC Plasma Display Drivers

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS
The XR-2284 and the XR-2288 are high voltage display
driver arrays especially designed for interfacing with ac NC NC

plasma display systems. The XR-2284 contains four in-

dependent driver channels, whereas its dual version, l
OUTPUTS
the XR-2288, contains eight driver channels. Each driv-
er array can be used for either the segment or the col- J
umn (or digit) drive, and several arrays can be TOGGLE
INPUT
"stacked" together to drive a large number of display
segments.

All four channels of the XR-2284 are driven by a com-

mon ac toggle voltage; however, the XR-2288 has two NC

independent toggle inputs, one for each of the four

channels in the IC. The XR-2284 and the XR-2288 are
designed for 360 volt ac plasma systems and have min-
imum stand-off voltages of 90 volts. The XR-2284C and
the XR-2288C are designed for 240 volt plasma sys-
tems, and have minimum stand-off voltages of 60 volts.

The circuits can operate with ac toggle frequencies up

to 200 kHz, and each driver channel can sink or source
100 mA of capacitive load current. For proper opera-
tion, the substrate terminals of all drivers must be

•
grounded through an external disconnect diode, DX, as
shown in the schematic diagram.

FEATURES
High Stand-off Voltage
90 V minimum for XR-2284/XR-2288
60 V minimum for XR-2284C/XR-2288C
Very Low AC Standby Power
("'" 25 mW/channel at 100 kHz)
Zero DC Standby Power
100 mA Output Drive Capability
TIL and CMOS Compatible Inputs
Digital or Segment Drive Capability Power Dissipation
XR-2284P/XR-2284CP 625 mW
APPLICATIONS XR-2288P/XR-2288CP 900 mW
Derate above + 25°C 5 mW/oC
High Voltage AC Plasma Panels Storage Temperature - 65°C to 150°C
High Voltage Pulsed Displays
Pulsed AC Switching ORDERING INFORMATION
Part Number Package Operating Temperature
ABSOLUTE MAXIMUM RATINGS
XR-2284P Plastic O°C to 70°C
Toggle Input Voltage XR-2284CP Plastic O°C to 70°C
XR-2284P/XR-2288P ±90V peak XR-2288P Plastic O°C to 70°C
XR-2284CP/XR-2288CP ±60B peak XR-2288CP Plastic O°C to 70°C

7-7
XR·2284/2288
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, with external diode DX = IN4002 or equivalent, TA = 25°C, unless otherwise
specified. (See operating precautions.)

XR-2284/XR-2288 XR-2284C/XR-2288C
PARAMETERS MIN TYP MAX MIN TYP MAX UNIT SYMBOL CONDITIONS
Maximum Toggle Voltage ±90 ±60 V pp VT Peak-to-peak
AC voltage-
See Figure 3.
Output Current Capability
Max Sourcing Current 100 150 100 120 mA Isource 12 % Duty Cycle
Max Sinking Current 100 120 100 120 mA Isink 12 % Duty Cycle
Output Voltage See Figure 4.
High Output) (VT-4) (VT-4) Vpeak VOHS
(selected)
High Output 4V 4V VOHN
(non-selected)
Low output (-VT+2) (-VT+2) Vpeak VOL
Maximum Toggle 200 100 200 kHz fT
Frequency
High-Level Input 2 1.4 2 1.4 V VIH
Low-Level Input 1.2 0.8 1.2 0.8 V VIL
Input Current 8 16 8 16 mA liN See Figure 3.
Switching Characteristics See Figure 4.
Rise Delay 500 500 nsec trd
Fall Delay 500 500 nsec tfds
(selected)
Fall Delay 500 500 nsec tfdn
(non-selected)

IMPORTANT OPERATING PRECAUTIONS

nel does not exceed 100 mA. This can be done by limit-
1. External diode DX with reverse breakdown voltage ing the slewrate of toggle voltage to:
~ VT must be included in all circuit applications. This
diode decouples or "floats" the IC from the circuit dVT) max s 100 mA,
ground during the negative excursions of the toggle (
dt CL
voltage, Vr.
where CL is the total load capacitance, including the
2. the rise and fall times of toggle voltages, VT, must be capacitance of the display elements, driven by the par-
held to a value such that output current of each chan- ticular output.

TOGGLE
~====~====~======~/r-=====~\==
ov - - - I/I -_ _ _-\-\\_ _ _ _/+-__--l\~

5V INPUT ~~ ==I=.=t======:)===--=l::.======~

150PF

\
l *
T
Dx~
r 150PF 100K

Figure 1. Generalized Test Circuit Figure 2. Typical Timing Waveforms

7-8
FUNDAMENTALS OF AC PLASMA DISPLAYS
Ac plasma display offer significant advantages over
other alpha-numeric displays such as fluorescent or
LEO type panels. Some of these advantages are the
low cost of the display itself, its wide viewing angle, and
the ease of formatting in the selection of display seg-
ments anc digits. Plasma systems typically require high
voltage (200V or higher) ac drivers operating at rela-
tively high frequencies (100 kHz and up). Although the VIN-----,
OV
plasma display panel is a capacitive load and does not
(bllnput Yoltage. VIN
draw dc current, the display driver output is required to
provide a high output drive current (typically 50 to 100
mA), during the rising and the falling edges of the toggle
voltage, so that the driver output can still follow the ac V~O"+VT
toggle voltage at high frequencies. OV I

The ac plasma displays normally require a net voltage

= -VT
in excess of 200 volts across the display to turn it on. In
DE· ACTIVATED
practice, this is achieved by "pulsing" the display with CHANNEL IACTIVATEOI
two out-of-phase toggle voltages (VT) , such that a net CHANNEL
peak-to-peak voltage of 2VT appears across the select- (el Channel output Yoltage. VOUT
ed display portion to make it turn on. Thus, in control-
Figure 3. Timing Diagram of Circuit Waveforms
ling the plasma display, one must control the amplitude
of two peak-to-peak toggle swings, one on the
pearing across the entire plasma panel.
"segment-side" and the other on the "digit-side" of the
display, where each toggle swing is equal to only one-
CIRCUIT DESCRIPTION
half of the total voltage swing needed to light up the dis-
play. For example, for 240 volt ac plasma display sys- Both the XR-2284 and the XR-2288 are multichannel
tems, the toggle voltage used (VT) would be 120 volts; driver circuits, packaged in 14 and 20-pin dual-in-line IC
and for 360 volt display systems, 180 volt toggle voltage packages respectively. The XR-2284 is a four-channel
will be needed. display driver, whereas the XR-2288 is an eight-channel
circuit, made up of two four-channel driver chips in the

•
PRINCIPLES OF OPERATION same dual-in-line package. Thus, the XR-2288 has two
toggle voltage and substrate inputs; one for each of the
The XR-2284 and the XR-2288 ac plasma display driver two four-channel IC chips sharing the same package.
circuits control the drive voltage applied to the segment
or the digit section of an ac plasma panel. The equivalent circuit diagram for a typical driver chan-
nel is shown in the schematic. All the channels have
Figure 3 shows the timing waveforms associated with
their own independent inputs and outputs, but share a
the ac plasma driver circuit, for the case of a 360 volt common toggle or clock input and a common substrate
display system (Le., VT = ±90V = 180V pp). In normal or ground connection. The circuit is designed as a se-
operation, all of the driver channels are driven by a ries connection of two controlled-switches, or SCR's.
common ac toggle voltage (VT) shown in Figure 3(a).
The transistors, 03 and 02, form one of the controlled-
When the control input to a driver channel, Vin, is at
switches, and 01 and 04, form the second controlled-
"high" state, as shown in Figure 3(b), its output would
switch. The internal junction capacitance, Cj' causes
be clamped nearly to ground and would follow the neg-
ative excursions of the toggle voltage, Vr- This pro-
COUMOHTO COfIIMON TO
duces only 1/2 of the required peak-to-peak voltage AUDRIYERS AUDAlYERS
'COM_TO
across the particular display segment, which is not COfIIMON TO
AUORIYERS ALL DRIYERS

enough to light it. However, if Vin is at a "low" state, the :~

driver output, Vout, would be enabled and follow close~y
the peak-to-peak excursions of the toggle voltage. This
would then cause the nearly full peak-to-peak swing of
the ac drive to appear across the selected display seg-
ment.

It should be noted that due to the external blocking di-

ode Ox of Figure 1, the monolithic IC substrate is com-
pletely decoupled from ground during the negative ex-
cursion of the toggle voltage and the internal diode, 02,
of the schematic diagram causes the output to follow
the toggle voltage within one diode drop. In this man-
ner, the IC has to withstand only one-half of the total ac Figure 4. Generalized Connection Diagram XR-2284 and
signal swing, or the one-fourth of the total voltage ap· XR-2288.

7-9
XR·2284/2288
the respective controlled-switches to be turned on dur-
ing the positive and negative edges of the toggle input, I I I I I I II
Vr
I I. I I. I I. I I.
An external diode, DX with a brekdown voltage ~ VT, is
used to "float" the substrate or decouple it from ground
during the negative excursions of the toggle voltage.
This external decoupling diode is common to all chan-
nels, and can serve more than one IC package, as
shown in Figure 4. In this manner, many driver IC's, ei-
TOGGLE
ther of the four-channel (XR-2284) or the eight-channel VOLTAGE
VT --"""*-+---"'''-''-'-'''---j-' VT
(XR-2288) type, can be "stacked" to drive a large num- COMPLEMENTARY
TOGGLE VOLTAGE
ber of display segments or columns, with only one com-
mon blocking diode and a common toggle input, as
shown in the Figure 4.
NOT!: EXTERNAL OIOOE. Ox (1N4002 OR EQUIVALENT) SHOULD
BE SEPARATE FOR DIGIT AND SEGMENT SIDES
Under dc conditions, i.e., with no ac toggle drive, the
driver IC's do not dissipate any appreciable standby Figure 5. Typical Circuit Connection for Driving 7-8egment
power. However, when the ac toggle voltage, Vr. is ap- 4-Dlglt Display with Decimal Point
plied and a particular channel is enabled, then the cor-
responding output can follow the peak-to-peak toggle swing of the toggle voltage, VT, is chosen so that the fir-
voltage and sink or source up to 100 mA of capacitive ing voltage, Vf, necessary for the display to light up,
load current to the plasma panel. falls into the range of:

APPLICATIONS 3 VT < Vf < 4 Vr

Driving Seven-Segment Displays In this manner, only the selected and enabled display
cells will have an energizing voltage ~ Vf.
Figure 5 illustrates a four digit, seven-segment plasma
display panel with decimal point. The entire display can Driving Alpha-Numeric Displays
be driven by one XR-2288 driver for the segment side
and one XR-2284 driver for the digit side. The segment Figure 6 shows the circuit connection for driving an
and the digit drivers each must have their external dis- eight digit, 16-segment alpha-numeric display. The
connect diode, DX, as shown in the figure. The seg- number of digits can be increased by connecting addi-
ment and the digit sides of the display are driven by out- tional XR-2284 or XR-2288 driver arrays into the digit
of-phase toggle signals, VT and VT, which cause a total side. These additional arrays can be directly "stacked"
firing voltage of four VT to appear across the enabled using the same external disconnect diode, DX, and the
display segment. Segments not enabled will have a net same toggle voltage drive lines already present on the
voltage of three VT across them. The peak-to-peak digit side.

EQUIVALENT SCHEMATIC DIAGRAM

QUTPUT

NOTE: EXTERNAL DtOOE.

INPUT LJ--t«~f-"'"
Ox. IS nEQUIREO FOR
PROPER OPERATION.

NOTI: UTEiItMAL DeQC)E., Ox (1JiMOO'2 OfIIOUNALlHTlIHOULD

.. ,,'.uu.n RMIt DIOIT AM) MOMon M)(I

Figure 6. Circuit Configuration for Driving 16-8egment

Alpha-Numeric Display Panel -=- - one channel only -

7-10
 XR-6118/6128

Fluorescent Display Drivers

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-6118 and the XR-6128 are high-voltage display
driver arrays which are designed to interface between
low-level digital logic and vacuum fluorescent displays.
Each circuit consists of eight independent signal chan-
nels comprised of Darlington output stages and
common-emitter type inputs. All stages on the chip
share common power supply and ground connections.
Both device types are capable of driving digits and/or
segments of fluorescent displays, and all of the eight
outputs can be activated simultaneously.
INPUTS OUTPUTS

FEATURES
Direct Replacement for Sprague UDN-6118A,
UDN-6128A, and UDN-6118P-2 (60V)
Digit or Segment Drive Capability

•
Low Input Current ORDERING INFORMATION
Integral Output Pulldown Resistors
Low Power Part Number Package Operating Temperature
High Output Breakdown Voltage XR-6118P Plastic O°C to + 70°C
XR-6128P Plastic O°C to + 70°C
XR-6118P-2 Plastic O°C to + 70°C

SYSTEM DESCRIPTION

ABSOLUTE MAXIMUM RATINGS The XR-6118 and XR-6128 fluorscent display drivers
can switch up to 85V and 40 mA. Inputs are protected
Supply Voltage, VBB 85V to 20V. The XR-6118 is compatible with TIL, Schottky
Output Voltage, VOUT 85V TIL, DTL and 5 Volt CMOS logic families. The XR-6128
Input Voltage, VIN 20V is intended for use with PMOS or CMOS logic families
Output Current, lOUT 40 mA operating with supply voltages of 6V to 15V. The two de-
Power Dissipation, (TA S 25°C) 1W vice types differ only in their input threshold levels (See
Derate Above 25°C 8 mW/oC Figure 1). With either device type, the output load is ac-
Operating Temperature O°C to +85°C tivated when the inputs are pulled toward positive sup-
Storage Temperature - 55°C to + 150°C ply. Output pulldown resistors are included on the die.

7-11
XR·6118/6128
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA = 25°C, VSS = 80V) Full Temp. Range O°C to + 70°C, XR-6118A only.

XR-6118A XR-6128A
SYMBOL PARAMETERS MIN TYP MAX MIN TYP MAX UNIT CONDITIONS
ICEX Output Leakage
Current 15 15 p.A VIN = 0.4 V
VOUT Output ON Voltage lOUT = 25 mA
77 77 V VIN = 2.4 V (XR-6118)
VIN = 4 V (XR-6128)
Input On Voltage 2.4 15 4.0 15 V lOUT = 25 mA
Input ON Current 650 1150 p.A VIN = 5 V (XR-6118)
VIN = 15 V (XR-6128)
Supply Current
ISS(OFF) Off Condition 100f.LA 100 p.A ALL Inputs Open
ISS(ON) On Condition 9 9 mA VIN = 2.4 V (XR-6118)
(ALL Inputs)
lOUT Output Pulldown 1100 1100 p.A ALL Inputs Open
Current VOUT = 80 V

Vaa
SEGMENT SELECT
XR.fi118128

dp

----------~o-----------o

VFIL
08

Figure 2. Typical Multiplexed Fluorescent Display Drive Application

7-12
 XR·6118/6128
+Vaa

3& K

OUTPUT
INPUT RIN"
~~I,/\,---'-"""''''''

One of Eight (*) For XA-6118

Stages AIN = 10K, AS = 30 K
For XA-6128:
AIN = AS = 20 K

EQUIVALENT SCHEMATIC DIAGRAM

7-13
7-14
 Section 7 - Interface Circuits
High Current Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
XR-2001/2002/2003/2004 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
XR-2011/2012/2013/2014 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
XR-2200 Hammer Driver . . . . . . . . . . . . . . . . . . . . . . 7-24
XR-2201/2202/2203/2204 High Voltage, High Current Darlington
Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . 7-26

• I

7-15
 XR-2001 /2/3/4

High-Voltage, High-Current Darlington

Transistor Arrays
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2001/2002/2003/2004 are high-voltage, high-
current Darlington transistor arrays consisting of seven
silicon NPN Darlington pairs on a common monolithic
substrate. All units feature open collector outputs and
integral protection diodes for driving inductive loads.
Peak inrush currents of up to 600 mA are allowed,
which makes the arrays ideal for driving tungsten fila-
ment lamps. The outputs may be paralleled to achieve
high load current capability although each driver has a
INPUTS
maximum continuous collector current rating of 500
mA. The arrays are directly price competitive with dis-
crete transistor alternatives.

FEATURES
Peak Inrush Current Capability of 600 mA.
Internal Protection Diodes for Driving Inductive Loads
Excellent Noise Immunity
Direct Compatibility with Most Logic Families
OpPosing Pin Configuration Eases Circuit Soard Layout
ORDERING INFORMATION
Part Number Package Operating Temperature
XR-2001CN Ceramic O°C to + 70°C
APPLICATIONS
XR-2002CN Ceramic O°C to + 70°C
XR-2003CN Ceramic O°C to + 70°C
XR-2004CN Ceramic O°C to + 70°C
Relay Drivers
High Current Logic Drivers SYSTEM DESCRIPTION
Solenoid Driver
The XR-2001 interfaces with bipolar digital logic (with
external current limiting), or with CMOS or PMOS di-
rectly.

The XR-2002 was specifically designed to interface with

14V to 25V PMOS devices.
ABSOLUTE MAXIMUM RATINGS TA = 25°C
The XR-2003 permits operation directly with CMOS or
Output Voltage, VCE 50V TIL operating at a supply voltage of 5 volts. Interface
Input Voltage,VIN 30V requirements beyond the scope of standard logic
Continuous Collector Current, IC buffers are easily handled by the XR-2003.
(Each Driver) 500mA
Continuous Sase Current, IS (Each Driver) 25mA The XR-2004 requires less input current than the XR-
Power Dissipation, PD (Each Driver) 1.0W 2003 and the input voltage is less than that required by
(Total Package) See graph the XR-2002. The XR-2004 operates directly from
Derate Above 25°C 16 mW/oC PMOS or CMOS outputs using supply voltages of 6 to
Storage Temperature Range - 55°C to + 150°C 15 volts.

7-16
ELECTRICAL CHARACTERISTICS
XR·2001/2/3/4
Test Conditions: TA 25°C, unless otherwise specified.

LIMITS
SYMBOL PARAMETERS MIN TYP MAX UNITS CONDITIONS
ICEX Output Leakage Current 100 p,A VCE = 50 V, TA = 70°C
XR-2002 500 p,A VCE = 50 V, TA = 70°C, VIN = 6V
XR-2004 500 p,A VCE = 50 V, TA = 70°C, VIN = 1V
VCE Collector-Emitter Saturation 1.25 1.6 V IC = 350mA, 18 = 500p,A
Voltage 1.1 1.3 V IC = 200mA, 18 = 350p,A
0.9 1.1 V IC = 100mA, 18 = 250p,A
liN Input Current (on)
XR-2002 0.85 1.25 mA VIN = 17V
XR-2003 0.93 1.35 mA VIN = 3.85V
XR-2004 0.35 0.5 mA VIN = 5V
1.0 1.45 mA VIN = 12V
liN Input Current (oft) 50 65 p,A IC = 500p,A, TA = 70°C
VIN Input Voltage
XR-2002 13 V VCE = 2 V, IC = 300mA
XR-2003 2.4 V VCE = 2 V, IC = 200mA
2.7 V VCE = 2 V, IC = 2S0mA
3.0 V VCE = 2 V, IC = 300mA
XR-2004 5.0 V VCE = 2 V, IC = 12SmA
6.0 V VCE = 2 V, IC = 200mA
7.0 V VCE = 2 V, IC = 275mA
8.0 V VCE = 2 V, IC = 3S0mA
hFE D-C Forward Current Transfer
Ratio
XR-2001 1000 VCE = 2 V, IC = 350mA

•
GIN Input Capacitance 15 30 pF
IR Clamp Diode Leakage Current SO p,A VR = 50V
VF Clamp Diode Forward Voltage 1.7 2.0 V IF = 350mA
tpLH Turn-On Delay 0.25 1.0 p,S 0.5 EIN to 0.5 EOUT
tpHL Turn-Off Delay 0.25 1.0 p,S 0.5 EIN to 0.5 EOUT

SCHEMATIC DIAGRAMS (One of 7 Identical Drivers is shown for each device.)

XR-2001 XR-2002 OUTPUT 1(1.1'
,-----.----1~-.-__O OUTPUT 10-16

INPUT I·T 0--....---£

INPUT 1·7

T.2K

3K

XR-2004 OUTPUT 10·16 XR-2003 OUTPUT 1(1.18

INPUT 1·7

IO.5K

7.2K
INPUT 1·7

2.7K
1:.
3K 3K

7-17
 XR·2001/2/3/4
CHARACTERISTIC CURVES
(a) XR-2002 (b) XR-2004 (c) XR-2003
2.5

J 2.0 r-.,.-~-~---'-.....-"----'
...v
~ 2.0

I y .,. I
2,0
.......... ......
~ 1.5 ~ ~-+-+--+----+--+---+-~ 1,5
~I'~"\. 10-'
~:<
1.5
.,.,'
!
alt-
"'V 'G"\.,~
1~1'1...... ..
!
~ 1.0
,;r--'"
a:: v ......
1.0 1,0
A~EA DF NORMAL
a0.5 V .......1--'
a:
B 0.5 F-,=-io-"-F'------+----+--+---+---I 0,5
~l\\'
~ OPERATION WITH _
STANOARO OR

i 0
i! o~~-~-~~--~-~~ o
SCHOTTKY TTL

12 14 16 18 20 22 24 26 5 7 • • 10 11 12 U 2.5 U U U U ~ U U
INPUT VOLTAGE - V,N INPUT VOLTAGE - V,N INPUT VOLTAGE - V,N

Figure 1. Input Current as a Function of Input Voltages

600
/
600 /
/
~/
/ / /
/
!:J /
/'
V ~ 400
I /
c
I
I L ~ ;' /
E 400
/~~~
... II
!
I ,,'t" ffia:: CJ~I /
~ /1 ~o" a::
:>
~I
q,'</
/
tf'ci''/ /J~O+
u
B a:: /
a:
~ ,,~ I
~'t"
".:;s
o...
~ 200
I /
K
..,'t"
~ 200 ~. L'
o
u
/
/j ~ o
u
/ /
MAXIMUM REOUIRED
INPU1T CURRENl

/' / / V
-,.. "V I
// 400
0.5 1.0 1.5 2,0 200 600
SATURATION VOLTAGE - VCE (SAT) INPUT CURRENT IN ~A - liN

Figure 2. Collector Current as a Function of Saturation Figure 3. Collector Current as a Function of Input Current
Voltage. 2.0

~
'\DEVICE LIMIT

III
\ ,
~
C
~ 1.5 \~'?o
~ ~
a!:
z

'~\
0
1=
cDo
u
~ 400
DEVICE LIMIT SERIES XR·2000
r--~'""'T"-~~"""T---r--'""1C"--"-----'---"'I:"""----'
iii
III
is
%. ~ .,(>~ (t'
II:
:cc ~ "0<1\ -"
i
~
350 t---+~~+-'-...:--t-~-+--t--"~-+---+----1
0
Do
W
t.O
", \
a:
~ 3OOr--~----~~~--~~-~~--+----~~~
1:1
C
III:
U " . . f'.
" \~
u
a:
o
"'
Do
W
..J ~.t:\ \~
~\
~ 250t---+---+---~~~_r~~t_~~----+_~~
,1',
III
~ 0,5
\ '
o
CJ ~C
>t

~~ 200 t----+----+---t----+---t---""......=-.....;;;~.....:::_1 '. ,

NUMBER OF OUTPUTS '~
i SI;~~~~~~~~LY ~,
~ ,5020·~--:30:':----47':0---~50::-----:1IO'=---~7=0----~1IO:----:!:1IO::---~,00
C PER CENT DUTY CYCLE 50 tOO 150
AMBIENT TEMPERATURE IN 'C

Figure 4. Peak Collector Current as a Function of Duty Cycle Figure 5. Allowable Average Power Dissipation as a Function
and Number of Outputs of Ambient Temperature

7-18
 TYPICAL APPLICATIONS
XR·2001/2/3/4
XR-2002

TTL
OUTPUT

Figure 6. PMOS to Load Figure 7. TTL to Load

XR-2004

XA-2003

•
+Vcc

Rp

CMOS TTL
OUTPUT OUTPUT

Figure 8. Buffer for Higher Current Loads Figure 9. Use of Pull-up Resistors to Increase Drive Current

7-19
 XR-2011/12/13/14

High·Voltage, High·Current Darlington

Transistor Arrays
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-2011/2012/2013/2014 are high-voltage, high-

current Darlington transistor arrays consisting of seven
silicon NPN Darlington pairs on a common monolithic
substrate. All units feature open collector outputs and
integral protection diodes for driving inductive loads.
Peak inrush currents of up to 750 mA are allowed,
which makes the arrays ideal for driving tungsten fila-
ment lamps. The outputs may be paralleled to achieve
higher load current capability although each driver has
a maximum continuous collector current rating of 600
mAo The arrays are directly price competitive with dis- INPUTS

crete transistor alternatives.

FEATURES

Peak Inrush Current Capability of 750 mA

Internal Protection Diodes for Driving Inductive Loads
Excellent Noise Immunity
Direct Compatibility with Most Logic Families
Opposing Pin Configuration Eases Circuit Soard Layout

APPLICATIONS

Relay Drive
High Current Logic Driver SYSTEM DESCRIPTION

The XR-2011 device is a general purpose array to be

ABSOLUTE MAXIMUM RATINGS TA = 25°C used with bipolar digital logic (with external current lim-
iting), or with CMOS or PMOS directly. Output pins op-
Output Voltage, VCE 50V posite input pins facilitates circuit board layout.
Input Voltage, VIN 30V
Continuous Collector Current, IC (Each Driver)600 mA The XR-2012 was specifically designed to interface
Continuous Sase Current, IS (Each Driver) 25 mA with 14 to 25 volt PMOS devices. The input current is
Power Dissipation, PD (Each Driver) 1.0 W limited to a safe value by a Zener diode and resistor in
(Total Package) See graph series.
Derate Above 25°C 16.67 mW/oC
Storage Temperature Range - 55°C to + 150°C A 2.7 kO series base resistor to each Darlington pair in
the XR-2013 permits operation directly with CMOS or
TTL operating with a 5 volt supply. Interface require-
ORDERING INFORMATION ments beyond the scope of standard logic buffers are
easily handled by the XR-2013.
Part Number Package Type Operating Temperature
The XR-2014 requires less input current than the XR-
XR-2011 CN Ceramic O°C to + 70°C 2013 and the input voltage is less than that required by
XR-2012 CN Ceramic O°C to + 70°C the XR-2012. The XR-2014 has a 10.5 kO series input
XR-2013 CN Ceramic O°C to + 70°C resistor, permitting operation directly from PMOS or
XR-2014 CN Ceramic O°C to + 70°C CMOS outputs using supply voltages of 6 to 15 volts.

7-20
ELECTRICAL CHARACTERISTICS (TA 25°C unless otherwise noted)
XR 201 ~ I~ 2/13/14
a

LIMITS
SYMBOL PARAMETERS MIN TYP MAX UNITS CONDITIONS

ICEX Output Leakage Current 100 Il A VCE = 50 V, TA = 70°C

XR-2012 500 Il A VCE = 50 V, TA = 70°C, VIN = 6V
XR-2014 500 Il A VCE = 50 V, TA = 70°C, VIN = 1V

VCE Collector-Emitter Saturation 1.7 1.9 V IC = 500mA, 18 = 600ilA

Voltage 1.3 1.6 V IC = 350mA, 18 = 500ilA
1.1 1.3 V IC = 200mA, 18 = 350llA
liN Input Current (on)
XR-2012 0.82 1.25 mA VIN = 17V
XR-2013 0.93 1.35 mA VIN = 3.85V
XR-2014 0.35 0.5 mA VIN = 5V
1.0 1.45 mA VIN = 12V

liN Input Current (off) 50 65 Il A IC = 500llA, TA = 70°C

VIN Input Voltage

XR-2012 17 V VCE = 2 V, IC = SOOmA
XR-2013 2.7 V VCE = 2 V, IC = 250mA
3.0 V VCE = 2 V, IC = 300mA
3.5 V VCE = 2 V, IC = SOOmA
XR-2014 7.0 V VCE = 2 V, IC = 27SmA
8.0 V VCE = 2 V, IC = 350mA
9.5 V VCE = 2 V, IC = SOOmA

hFE D-C Forward Current Transfer

Ratio
XR-2011 1000 VCE = 2 V, IC = 350mA

CIN

IR
Input Capacitance

Clamp Diode Leakage Current

Clamp Diode Forward Voltage

15

2.1
30

50

2.5
PF

Il A
V
VR

IF =
= 50V

500mA
II
VF

tpLH Turn-On Delay 0.25 1.0 Il S 0.5 EIN to 0.5 EOUT

tpHL Turn-Off Delay 0.25 1.0 Il S 0.5 EIN to 0.5 EOUT

·'L:____
SCHEMATIC DIAGRAMS (One of 7 Identical Drivers is shown for each device.)
OUTPUT 11).\1
XA-2011

INPUT 1-7 O- t- -oV \r~r-L. . . J\IV\,.- +- '~ .~~ .... 3_ -+---0

XA-2014 OUTPUT 11).\1 XA-2013 OUTPUT 11).\1

INPUT 1-1 INPUT 1·1

IO.5K 2.1K

3K 3K

7-21
XR·2011/12/13/14
CHARACTERISTIC CURVES
(a) XR-2012 (b) XR-2014 (c) XR-2013
2.5

J ~ 2.0
j
./
V
y
2.0
2.0
_....
11.5
f

....... - f
•E 1.5 ........... ! 1.5

~~ ~;c~ .-
:/

-----
~..y 1"'~c
!
~
ffi
..\"
1"' .....
!
!ZII! .. ~. ~
!Z...
cz: 1.0
-~.

... -
1.0 1.0
-;=p\ct.!:..
........... ~ -"';1;""
cz:
A~EA OF NORMAL
,."
cz: 10- .....
B
acz: ..../ '
cz:
......... ;:)
L...- ~OPERAnON WITH _
0.5 ~ 0.5
f-- ~ 0.5 \'I: ,\'
~ ;:)
STANDARD OR
;:)
.... .... ! SCHOTTXY TIL
! 0 ! 0 o
12 14 1& 1. :zo 22 24 2& 5 7 • I 10 11 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
INPUT VOLTAGE - VIN INPUT VOLTAGE - VIN INPUT VOLTAGE - VIN

Figure 1. Input Current as a Function of Input Voltages

600
/
I
/ I
/ / 9
1
I
!J}
I /
/
/

/
/ 1 400
f
I /
1400 !
,/ /
/W~
/ ....'t' !Z...
v~J /
'~/
cz:
cz: :$1
ItCJ~1 ... ~
;:)
u
cz:
.... 1 V
~/ e; ~ ~ 200 I
1
/
// 4'
~. j
o
u
/
-'
/
K MAXIMUM REQUIRED

/ INPUT CURRENT

~.
/'
i / / V
0.5
-'"
",

1.0 1.5 2.0

// 200 400 600
SATURAl10N VOLTAGE - VCE (SAT)
INPUT CURRENT IN #'A - liN

Figure 2. Collector Current as a Function of Saturation Figure 3. Collector Current as a Function of Input Current
Voltage 2.0

~
\OEVICE LIMIT

til
\ \
DEVICE LIMIT - SERIES XR·lOIO
~r-~~~--r-~-r----~--~~--~---.----,
~
C
~ I.S
\ \Cb ~
u
!
z ~ ~
~~\
~ 450 ~r-'H--T---f'r---+~:--+----+----+"~-t----t 0
1=
•~
~
c
; 400r---H--T-~~--~----+-~-+----+----t--~d
til
is
~o. ~ 'f'c ~
...~ +.,.
~
II:
C'~
1.0

" \.1\
a:
II:
i3 350 r---+~~~--l>,M--~oi----_+-
II:
...CJf
C
\
t lie
U
, \~o
~ 300 r---+----~--"~+- •.......
8 -:'11\' \~
\.
,j

~
, '\
ID
~ 0.5
\
~ :~ t - - - t - - - : ...'l----t-~-.po,.::--_+...::o.,;;:::___+_-__+:::oo...,=___! \'
9
,j
c c
~
~ ~~--~--+--_+---+---~~--~~_4----~
'.\0
c
.. ~
~,
,502~0----~~---4~O---···50~--~~----~ro----~80---~~----,~OO
so 100 ISO
PER CENT DUTY CYCLE AMBIENT TEMPERATURE IN °C

Figure 4. Peak Collector Current as a Function of Duty Cycle Figure 5. Allowable Average Power Dissipation as a Function
and Number of Outputs of Ambient Temperature

7-22
TYPICAL APPLICATIONS
XR·2011/12/13/14
XR-2013
XR-2012 +Vcc

t LAMP
TEST

TTL
OUTPUT

Figure 6. PMOS to Load Figure 7. TTL to Load

XR-2014

+Vcc XR-2013

II
Rp

CMOS
OUTPUT

Figure 8. Buffer for Higher Current Loads Figure 9. Use of Pull-up Resistors to Increase Drive Current

7-23
 XR-2200

Hammer Driver
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2200 is an array of five Darlington transistor
pairs which are capable of driving high-current loads
such as solenoids, relays, and LED's. Each of the five
circuits contained on the XR-2200 is capable of sinking
up to 400 mA. The XR-2200 was specifically designed
for use with 14 V to 25 V PMOS devices.

FEATURES
Output Capability of 400 mA for Each Driver
Drivers may be used in parallel for increased output
drive capability.
Input is directly compatible with PMOS outputs

APPLICATIONS
Printing Calculator Hammer Driver
High Current LED Driver
Solenoid and Relay Driver
Tungsten Lamp Driver ORDERING INFORMATION
High Current Switch
Part Number Package Type Operating Temperature
XR-2200 CP Plastic - 25°C to + 70°C

ABSOLUTE MAXIMUM RATINGS

Collector to Base Voltage 30V
Collector to Emitter Voltage 30V
Emitter to Base Voltage 5.5V SYSTEM DESCRIPTION
Collector Current 450 mA
Input Terminal Breakdown 30V The XR-2200 hammer driver contains five Darlington
Voltage (plus) connected transistor pairs, each capable of switching
Input Terminal Breakdown -0.5V 30V. All five emitters are connected to a common
Voltage (minus) ground (Pin 7). With a guaranteed current gain of 2000,
Power Dissipation 550mW each section of the XR-2200 can sink 400 mA.

7-24
ELECTRICAL CHARACTERISTICS (TA = 25°C)
XR·2200
LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Power Supply Voltage 26 Vdc
Output Leakage Current 100 p.A VCE = 26 V, VIN = 0 V
Output Current 400 mA
One Driver
Output Current See Figure 2
5 Drivers
Output Saturation Voltage 2.2 Vdc lOUT = 400 mA
VIN = 17 V
lOUT = 200 mA
VIN=17V
Current Gain 2000 VCE = 3 V
lOUT = 200 mA
Input Current 0.7 mA VIN = 17 V
lOUT = 0 mA

500

OUTPUT

400
, 1\
INPUT 0----""""-.--£ 300
25 K

\~ PULSE FREOUENCY '" 10 Hz

•
200

25 K 2K ...............r--
100

20 40 60 80 100

% DUTY CYCLE

Figure 1. Schematic Diagram (1 of 5 Circuits Shown) Figure 2. Maximum Permissible Output Current per Driver vs
Duty Cycle with 5 Drivers Pulsed Simultaneously.
V+

LOAD

PMOS 115 XR·2200

PMOS 115 XR·2200
GATE
GATE
DIODES ARE 1N4002
OR EOUIVALENT

Figure 3. Circuit Connection for Driving Non-Inductive Loads Figure 4. Circuit Connection for Driving Inductive Loads.
NOTE: The XR-2200 may be damaged if the di-
odes are omitted when driving an inductive
load.

7-25
 XR-2201/2/3/4

High·Voltage, High·Current Darlington

Transistor Arrays
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2201, XR-2202, XR-2203, and XR-2204
Darlington transistor arrays are comprised of seven sil-
icon NPN Darlington pairs on a single monolithic sub-
strate. All units feature open-collector outputs and inte-
gral protection diodes for driving inductive loads. Peak
inrush currents of up to 600 mA are allowable, making
them also ideal for driving tungsten filament lamps. Al-
though the maximum continuous collector current rat-
ing is 500mA for each driver, the outputs may be paral-
leled to achieve higher load current capability.

FEATURES
High Peak Current Capability-600mA
Internal Protection Diodes for Driving Inductive Loads
Directly Compatible with TTL, CMOS, PMOS, and DTL ORDERING INFORMATION
Logic Families
Exact Replacement for Sprague Types ULN-2001A, Part Number Package Operating Temperature
ULN-2002A, ULN-2003A, and ULN2004A XR-2201CP Plastic O°C to +85°C
XR-2202CP Plastic O°C to +85°C
XR-2203CP Plastic O°C to +85°C
XR-2204CP Plastic O°C to +85°C

SYSTEM DESCRIPTION
APPLICATIONS
The XR-2201 is compatible with most common logic
Relay Drivers forms, including PMOS, CMOS, and TTL. It requires a
Solenoid Drivers current-limiting resistor placed in series with the input
High Current Inverters to limit base current to less than 25mA.

The XR-2202 is designed for direct compatibility with

14V-25V PMOS devices.

The XR-2203 is compatible with TTL or CMOS operating

ABSOLUTE MAXIMUM RATINGS TA = 25°C at 5 volts. Each input has a series base resistor to limit
the input current to a safe value.
Output Voltage, VCE 50V
Input Voltage,VIN 30V The XR-2204 is designed for direct operation from
Emitter-Base Voltage, VEBO 6V CMOS or PMOS outputs utilizing supply voltages of 6 to
Continuous Collector Current, IC (Each Driver) 500mA 15V.
Continuous Base Current, IB (Each Driver) 25mA
Power Dissipation, PD (Each Driver) 1.0W With all four devices, the load should be connected be-
(Total Package) 2.0W tween the driver output and + VCC. For protection from
Derate Above 25°C 16.67 mW/oC transient voltage spikes, Pin 9 should be connected to
Storage Temperature Range - 55°C to + 150°C +VCC·

7-26
ELECTRICAL CHARACTERISTICS
XR·2201/2/3/4
Test Conditions: TA = 25°C unless otherwise noted

LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Output Leakage Current 100 ILA VCE = 50 V, TA = 70°C
XR-2202 500 ILA VCE = 50 V, TA = 70°C, VIN = 6V
XR-2204 500 ILA VCE = 50 V, TA = 70°C, VIN = 1V
Collector-Emitter Saturation 1.25 1.6 V IC = 350mA, 18 = 500ILA
Voltage
1.1 1.3 V IC = 200mA, 18 = 350ILA
0.9 1.1 V IC = 100mA, 18 = 250ILA
Input Current
XR-2202 0.85 1.3 mA VIN = 17V
XR-2203 0.93 1.35 mA VIN = 3.85V
XR-2204 0.35 0.5 mA VIN = 5V
1.0 1.45 mA VIN = 12V
Input Current 50 65 ILA IC = 500ILA, TA = 70 c C
Input Voltage
XR-2202 13 V VCE = 2V, IC = 300mA
XR-2203 2.4 V VCE = 2V, IC = 200mA
2.7 V VCE = 2V, IC = 250mA
3.0 V VCE = 2V, IC = 300mA
XR-2204 5.0 V VCE = 2V, IC = 125 mA
6.0 V VCE = 2V, IC = 200mA
7.0 V VCE = 2V, IC = 275mA
8.0 V VCE = 2V, IC = 350mA
D-C Forward Current Transfer
Ratio XR-2201 1000 VCE = 2V, IC = 350mA
Input Capacitance 15 30 pF

II
Turn-On Delay 1.0 5 ILS 0.5 EIN to 0.5 EOUT
Turn-Off Delay 1.0 5 ILS 0.5 EIN to 0.5 EOUT
Clamp Diode Leakage Current 50 ILA VR = 50V
Clamp Diode Forward Voltage 1.7 2 V IF = 350mA

SCHEMATIC DIAGRAMS (One of 7 Identical Drivers is shown for each device.)

OUTPUT 10- 16
.----__....--0 OUTPUT 10-16

INPUT 1-7 v--r---,..

XR-2201 XR-2202

r-------_ _ _ _-O r-------_ _ _ _-O

OUTPUT 10- 16 OUTPUT 10-16

XR-2203 XR-2204

7-27
7-28
Cross References & Ordering Information

Telecommunication Circuits

Data Communication Circuits

Computer Peripheral Circuits

Industrial Circuits

Instrumentation Circuits

Interface Circuits

User Specific Linear ICs

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

8
 Section 8 - Special Function Circuits
XR-S200 Multi-Function PLL System . 8-2
XR-1310 Stereo Demodulator ........ . 8-11
XR-2216 Monolithic Compandor . . . . . . . . 8-13
XR-2264/2265 Pulse-Proportional Servo Circuit 8-17
XR-2266 Monolithic Servo Controller . . . . . 8-20
XR-2917 Frequency-to-Voltage Converter .. . 8-28
XR-4151 Voltage-to-Frequency Converter .. . 8-38
XR-9201 8-Bit Microprocessor Compatible Digital-to-Analog Converter 8-43
XR-13600 Dual Operational Transconductance Amplifier . . . . . . . . 8-51

8-1
 XR-S200

Multi-Function PLL System

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-S200 integrated circuit is a highly versatile,
multipurpose circuit that contains all of the essential
functions of most communication system designs on a
single monolithic substrate. The function contained in
the XR-S200 include: 1. a four quadrant analog mUlti-
plier, 2. a high frequency voltage controlled oscillator
(VeO) and 3. a high performance operational amplifier.

The three functions can be used independently, or di-

rectly interconnected in any order to perform a large
number of complex circuit functions, from phase-
locked loops to the generation of complex waveforms.
The XR-S200 can accommodate both analog and digital
signals, over a frequency range of 0.1 Hz to 30 MHz,
and operate with a wide choice of power supplies ex-
tending from ± 3 volts to ± 30 volts.

FEATURES
Wide VCO Frequency Range 0.1 Hz to·30 MHz
Wide Supply Voltage Range ± 3V to ± 30 V
Uncommitted Inputs and Outputs for Maximum
Flexibility
Large Input Dynamic Range
UP AMP
CUMP

APPLICATIONS
Phase-locked loops
FM demodulation
Narrow and wideband FM
Commercial FM-IF
TV sound and SCA detection
FSK detection (MODEM) ABSOLUTE MAXIMUM RATINGS
PSK demodulation
Signal conditioning Power Supply 30 Volts
Tracking filters Power Dissipation 900 mW
Frequency synthesis Derate above + 25°C 5 mW/oC
Telemetry coding/decoding Temperature
AM detection Operating - 55°C to + 125°C
Quadrature detectors Storage - 65°C to + 150°C
Synchronous detectors Input Signal Level, Vs 6 V,p-p
Linear sweep & AM generation
Crystal controlled
Suppressed carrier
Double sideband
Tone generation/detection
ORDERING INFORMATION
Waveform generation Operating Temperature
Part Number Package
Single/square/triangle/sawtooth
Analog multiplication XR-S200 Ceramic O°C to + 70 0 e

8-2
ELECTRICAL SPECIFICATIONS (T = 25°C, VSUPPLY = ± 10V)
XR·S200
LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
MULTIPLIER SECTION: See Figure 2, Rx = Ry = 15k, Pins 1,2,6,23, 24 Grounded.
Output Offset Voltage ±40 ±120 mV Vx = Vy = 0, Via = IV3 - V41
Input Bias Current 5 15 IlA Measured at pins 5 and 7
Input Offset Current 0.1 1.0 IlA Measured at pins 5 and 7
Linearity
(Output error, % 1.0 % - 5 < Vx < + 5, Vy == ± 5V
of full scale) 1.5 % - 5 < V~ < + 5, Vx = ± 5V
Scale Factor, KM 0.1 - KM = 2 1RxRy (Adjustable)
Input Resistance 0.3 1.0 MO f = 20 Hz, Measured at pins 5 and 7
3 dB Bandwidth 3 6 MHz CL :s 5 pF
Phase detection B.W. 50 100 MHz Rx = Ry = 0
Differential Output Swing ±4 ±6 V pop Measured across pins 3 and 4
Output Impedance
Single Ended 6 kO Measured at pins 3 and 4
Differential 12 kO
OPERATIONAL AMPLIFIER SECTION: See Figure 10 and 11, RL = 20k, CL = 550 pF.
Input Bias Current 0.08 0.5 IlA
Input Offset Current 0.02 0.2 IlA
Input Offset Voltage 1.0 6.0 mVdc
Differential Input Impedance Open loop, f = 20 Hz
Resistance 0.4 2.0 MO
Capacitance 1.0 pF
Common Mode Range ±8 V
Common Mode Rejection 70 90 dB f = 20 Hz
Open Loop Voltage Gain 66 80 dB
Output Impedance 2 kO
Output Voltage Swing ±7 ±9 V RL ~ 20 kO
Power Supply Sensitivity 30 IlVN Rs :s 10 kO
Slew Rate 2.5 V/llsec Av = 1, CL = 10 pF

•
VCO SECTION: See Figure 11, RL = 10k, fa = 1 MHz.
Upper Frequency Limit 15 30 MHz Co = 10 pF
Sweep Range 8:1 10:1 - fo = 10kHz, See Figure 14
Digital Controls Off
Linearity
(distortion for .2 1.0 % Digital Controls Off
ilf/f = 10%)
Frequency Stability VCC > 8V, fa = 1 MHz
Power Supply 0.08 0.5 %N Sweep Input Open
Temperature 300 650 ppm/oC
Analog Input Impedance Measured at pins 23 and 24
Resistance 0.1 0.5 MO
Capacitance 1.5 pF
Output Amplitude 3 V pop Squarewave
Output Rise Time 15 ns CL = 10 pF, RL = 5 kG
Fall Time 20 ns
Input Common Mode Range +6 +8 Vdc
-4 -6 Vdc
CAUTION: When using only some of the blocks within the XR-S200, the input terminals to the unused section must
be grounded (for split-supply operation); or connected to an ac ground biased at V + /2 (for single supply
operation).

8-3
XR·S200
XR-S200 ANALOG MULTIPLIER SECTION
The analog multiplier in the XR-S200 (Figure 2) provides
linear four-quadrant multiplication over a broad range of
input signal levels. It also serves as a balanced modula- lOOt<.
tnr, phase comparator, or synchronous detector. Gain is
externally adjustable. Nonlinearity is less than 2 % of lOOK SCAl t
fACTOR
full scale output. ADJUST

OUTPUl
TYPICAL APPLICATIONS OF MULTIPLIER SECTION
• Analog multiplication/division
• Phase detection
• Balanced modulation/demodulation
• Electronic gain control
• Synchronous detection
• Frequency doubling

ANALOG MULTIPLICATION
Figure 3. Analog Multiplication
The XR-S200 multiplier section can be combined with
the amplifier section to perform analog multiplication
without the need for dc level shifting between input and
output. The amplifier functions as an operational ampli-
fier with a single-ended output at ground level when
connected as shown in Figure 3.

lK
CB
X R ·S200
MULTIPLIER
SECTION
I OUTPuT

lK

X-INPUT
SIGNAL INPuT

XR-S200
MULTIPLIER
SECTION VRltl "ERcoswot Cc " COuPLING CAPACITOR
X-v GROUND
Vsltl 0 Escoslwot. ~I CB 0 BYPASS CAPACITOR

-= vy --r----r----r--"
Figure 4. XR-S200 Multiplier Section as a Phase Comparator

Y-INPUT

normally a high level reference signal and the other in-

Figure 2. XR-S200 Multiplier Section put a low level information s.ignal. Since the XR-S200
multiplier section offers symmetrical response with re-
PHASE COMPARATOR spect to the X and Y inputs, either input can be used as
the carrier or signal input. For low input levels, the con-
For phase comparison, a low-level reference signal is version gain is proportional to the input signal ampli-
normally applied to one input and a high-level reference tude. For high level inputs, (VS > 40 mV, rms) Kef> is
or carrier signal to the other input, as in Figure 4. The constant and approximately equal to 2V/rad.
signal.may be applied to either the X or Y input, since
the response is symmetrical. SUPPRESSED-CARRIER AM

If the tv'v'O inputs, VR(t) and VS(t) are at the sarno fre- The multiplier generates suppressed-carrier AM signals
quency, then the de voltage at the output of the phase when connected as in Figure 6. Again, the symmetrical
comparator can be related to the phase angle ef> be- response allows the X or Y inputs to be used inter-
tween the two signals as changeably as the carrier or modulation inputs. The X
and Y offset adjustments optimize carrier suppression.
Vef> = Kef>cOSef> Gain control resistors RX and Ry typically range from 1
KO to 10 KO, depending on input signal amplitudes. The
where Kef> is the conversion gain in volts per radian (Fig- values shown give approximately 60 dB carrier sup-
ure 5). For phase comparator applications, one input is pression at 500 kHz and 40 dB at 10 MHz.

8-4
DOUBLE-SIDEBAND AM GENERATION
XR·S200
BK
The connection for double-sideband AM generation is +lOV
shown in Figure 7. The dc offset adjustment on the
modulation input terminal sets the carrier output level, MODULATION
INPUT
while the dc offset of the carrier input governs symme-
try of the output waveform. The modulation input can - 10V O----+----t
also be used as a linear gain control (AGC) , to control
amplification with respect to the carrier input signals. 1K
XR -5200
MULTIPLIER
z SECTION
~
"z 1K
4 -
~a:
~~ 1.0 lOOK
00 +10V
U« 12
a: a:
oUi
f-f- -10V
«-'
~~ 0.1
~- Figure 7. Double Sideband Amplitude Modulation Using
o
u XR-S200 Multiplier Section
w
VJ
«
~ 0.01 L..-_ _---\._ _ _-'--_ _........._ _- ' - - ' -_ _---'

01 10 100 1000
LOW LEVEL INPUT AMPLITUDE ImV. rmsl

Figure 5. Phase Comparator Conversion Gain Versus Input

Amplitude

+VCC

22 10 11

MODULATION
~""""'-----4
INPUT lK

•
XR-S200
MULTlI'LIER
SECTION
lK

Figure 7-1. AM Modulation, 95% AM, fc = 50 kHz,

fm = 1 kHz I

11

Figure 6. Suppressed Carrier Modulation Using XR-S200

Multiplier Section

FREQUENCY DOUBLING
XR 5200
Figure 8 shows how to double a sinusoidal input signal MULTIPLIE R
SECTION
of frequency ts to produce a low-distortion sinewave
output of 2f s. Total harmonic distortion is less than
0.6% with an input of 4V, pop, at 10 kHz and an output
of 1V, pop, at 20 kHz. The multiplier's X and Y offsets are
100KL-..,...._ _...,_--...,_---'
nulled as shown to minimize the output's harmonic
content.

SYNCHRONOUS AM DETECTION 75K

Vs :; Ess,nwst
A typical synchronous AM detector is shown in Figure Va - Eosm 2wsl
9. The signal is applied to the multiplier common input
and the X and Y inputs are grounded. Since the Y input Figure 8. Multiplier Section as Frequency Doubler

8-5
XR·S200
operates at maximum gain with Ry = 0, the detector l00dB~----~-----r----~----~~--~

gain and demodulated output linearity are determined

by RX' An RX range of 1 KO to 10 KO is recommended
for carrier amplitudes of 100 mV, pop; or greater. The
multiplier output can be low-pass filtered to obtain the
demodulated output. Figure 9-1 shows the carrier and
modulated waveforms for a 30% modulated input sig-
nal with a 10 MHz carrier and 1 kHz modulation.

6K
20 cHll-.-.;::...........,........:---,..-------i----.....

+10V
22 11

50 -20 cHI " -.......~........~...............................................................................""

100Hz 1 KHz 10 KHz 100 KHz 10 1011Hz
FREOUENCY

MULTIPLIER
XR-S200
Figure 10. Amplifier Section Frequency Response
SECTION

XR-S200 OSCILLATOR SECTION

The voltage-controlled oscillator section, (Figure 11) is
an exceptionally versatile design capable of operating
from a fraction of a cycle to.in excess of 40 MHz. Fre-
quencies can be selected and controlled by three meth-
Figure 9_ Synchronous AM Detector ods, and used in various combinations for different ap-
plications:

1. External timing capacitor eO tunes the veo to a cen-

ter frequency between 0.1 Hz and 40 MHz. The free-
running frequency is inversely proportional to eO.
(see Figure 12)

2. Two digital control inputs allow four discrete frequen-

cies to be selected at any center frequency. The dig-
ital inputs convert the logic signal voltages to inter-
nal control currents. (see Figure 13)

3. A sweep voltage, applied through a limiting resistor

RS is used for frequency sweeping, on-off keying,
and synchronization of the veo to a sync pulse. (see
Figure 14)

The voltage-to-frequency conversion of the veo sec-

tion is highly linear. In addition, the conversion gain can
be controlled through the analog control input. Gain is
Figure 9-1_ Synchronous AM Demodulation inversely proportional to Ro. When the digital controls
are also used, gain decreases as the frequency is
XR-S200 AMPLIFIER SECTION stepped up.

This multi-purpose function (Figure 10) can be used as The veo interfaces easily with Eel or TIL logic. It can
a general-purpose operational amplifier, high-speed be converted to a highly stable crystal-controlled oscil-
comparator, or sense amplifier. It features an input im- lator by simply substituting a crystal in place of the tim-
pedance of 2 megohms, high voltage gain, and a slew ing capacitor, eO.
rate of 2.5V/microsecond. The frequency response
curves for the amplifier section are also shown in Fig- Typical performance characteristics of the veo section
ure 10. are shown in Figures 12, 13, and 14.

8-6
 EXPLANATION OF
XR·S200
veo DIGITAL CONTROLS
The VCO frequency is proportional to the total charging
current, 1,-; applied to the timing capacitor. As shown in
Figure 15, IT is comprised of three separate compo-
nents: 10, 11, and 12, which are contributed by transis-
tors TO, T 1, and T2, respectively. With pins 15 and 16
open circuited, these currents are interrelated as

Currents 11and 12 can be externally controlled through

pins 16 and 15 respectively. By increasing the dc level
at either of these pins, T 1 or T 2 can be turned "off" and
11 or 12 can be reduced to zero. With reference to Fig-
ure 15, this can be done by applying a 3 volt logic pulse
FREQ. TUNE -VEE DIGITAL to these pins, through disconnect diodes D1 and D2. In
(SWEEP) INPUT CONTROL this manner, the VCO frequency can be stepped in four
INPUTS discrete intervals, over a frequency range of 2.5:1, as
shown in Figure 13.
Figure 11. XR-S200 Oscillator Section
DIGITAL CONTROL "OFF"
106 r--------------------, PINS 15 & 16
CONNECTED TO
GROUND THROUGH
1 k!l
105
/ ' DIGITAL CONTROLS ··OW
V1
- 1511108 1 Hz
0 1'---
o Co IpFI
~ 10 4
:7.
3c;:
~ 10 3
0
u DIGITAL CONTROLS
1211108 1 Hz
102
'0' -CQiPFI

10
10 3 10 4 10 5 106 10 7

•
108
FREOUENCY. '0 IHzl
Figure 12. veo Frequency as a Function of Timing
Capacitor, Co 12 14 20
NEGATIVE SWEEP VOLTAGE. Vs VOLTS

Figure 14. Voltage Sweep Characteristics

3.0

10 ; 100
_° 2 .5
~:
u
~
::>

~ 2.0 I 10 ; 101 1.3V

INTERNAL
BIAS 2R

I
0
u
>
'0 ~ '10
§ 1.5
:::;
«
:2
ex:
0
z 1.0
I 10 ; 111
12
0< 1.0V
1> 30V

0.5
0 01 10 11 12 -VEE IMOST NEGATIVE
DIGITAL INPUT CODE '----.......- - - -......--<> OR POINTI
GROUND

Figure 13. VCO Digital Tuning Characteristics Figure 15. Explanation of VCO Digital Controls

8-7
XR·S200
TYPICAL APPLICATIONS OF VCO SECTION FREQUENCY-SELECTIVE FM DEMODULATION

• Voltage/frequency conversion For FM demodulation, the PLL connection is used (Fig-

• Phase-locked loops ure 17.) The multiplier, with its gain terminals shorted,
• Frequency synthesis serves as the phase detector, and the veo and filter
• Signal conditioning govern the operating frequencies.
• Carrier generation
• Synchronization The gain block is used as an audio preamplifier to set
• Sweep and FM generator the demodulated output signal level. Volume is con-
• Crystal oscillator trolled by the variable feedback resistor R7. If R6
• Waveform generator equals R7, the dc output level will be very close to
• Keyed oscillator ground, for circuit operation with split power supplies.
C3 is the amplifier's compensation capacitor. Ra and
APPLICATIONS OF THE XR-S200 SYSTEM e2 set the output de-emphasis time constant TO, which
is normally 75 J,tsec. for commercial FM applications (fo
PHASE-LOCKED LOOP = 10.7 MHz).
A self-contained phase-locked loop is formed by con- FSK DETECTION
necting the XR-S200 as outlined in Figure 16.
FSK signals are detected and demodulated with the
In most PLL applications, the amplifier is available for PLL connection, as well. It is shown in Figure 18 as a
functions useful outside the loop, since the phase com- monolithic MODEM suitable for 8ell1 03 or 202 type da-
parator (multiplier section) and veo provide sufficient ta sets operating at data rates to 1aOO baud. An input
conversion gain. In this case, the amplifier gain does frequency shift corresponding to a data bit causes the
not enter the PLL gain expression. Assuming unity dc multiplier's dc voltage output to reverse polarity. The dc
gain for the filter, the PLL loop gain is KT = Kcp KO level is changed to a binary output pulse by the gain
where Kcp and KO are the multiplier and veo conversion block, connected as a voltage comparator.
gains, respectively.

vco
ouTPuT

R"

Figure 16. XR-S200 as a Phase-Locked Loop

C1 COlJPlINl; CAPACI IUH

C BYPASS CAPACITOR
B

Figure 18. FSK Detection

FREQUENCY SYNTHESIZER

Frequency synthesis is performed in Figure 19 by a

phase-locked loop closed with a programmable counter
or digital divide-by-N circuit inserted into the feedback
loop. The veo frequency is divided by N, so that when
Figure 17. Circuit Connection for FM Detection the circuit locks to an input signal at frequency fs, the

8-8
oscillator output is Nf s . A large number of discrete fre-
XR·S200
quencies can be synthesized from a given reference
frequency by changing N.

SOUAREWAVE
OuTPuT
13V l-lpi

TRIANGLE OR
SINEWAVE
OUTPUT
16VppJ

Figure 21. Waveform Generator Typical Circuit Connection

Diagram

Figure 19. Frequency Synthesizer

TRACKING FILTER AND WIDEBAND DISCRIMINATOR

In tracking filter applications, the XR-S200 again forms

a PLL system (Figure 20). When the PLL locks on an in-
put signal, it functions as a "frequency-filter" and pro-
duces a filtered version of the input signal frequency at
the VCO output. Since it can track the input over a
broad range of frequencies around the VCO free-
running frequency, it is also called a "tracking filter".
The system can track input signals over a 3:1 frequen-
cy range.

•
WAVEFORM GENERATOR

The XR-S200 can also be interconnected to form a ver-

satile waveform generator. The typical circuit shown in
Figure 21 generates the basic periodic square (or saw-
tooth) waveform. The multiplier section, connected as a Figure 21-1. Basic Waveforms Available from XR-S200
linear differential amplifier, convert the differential saw-
tooth waveform input into a triangle wave output at pins 3 and 4. The waveform adjustment pot across pins 8
and 9 can be used to round the peaks of the triangle
waveform and convert it to a low distortion sinewave
(THD<2%). Terminals 3 and 4 can be used either dif-
ferentially or single endedly to provide both in-phase
and out-of-phase output waveforms.

The output frequency can be swept or frequency modu-

lated by applying the proper analog control input to the
circuit. For linear FM modulation with relatively small
frequency deviation (Aflf < 10 %) the modulation input
can be applied across terminals 23 and 24. For large
deviation sweep inputs, a negative going sweep volt-
age, Vs , can be applied to pin 18.

This allows the frequency to be voltage-tuned over ap-

proximately a 10: 1 range in frequency. The digital con-
trol inputs (15 and 16) can be used for frequency-shift-
keying (FSK) applications. They can be disabled by con-
Figure 20. Recommended Circuit Connection for Tracking necting them to ground through a current-limiting
Filter Application (fo = 1 MHz) resistor.

8-9
XR·S200 AM & FM SIGNAL GENERATION
MOCULATED
OUTPUT
The oscillator and multiplier sections can be intercon-
nected as a general purpose radio-frequency signal
generator with AM, FM and sweep capability as shown
in Figure 22.

The oscillator section can be used as a vOltage-tuned,

variable frequency oscillator, or as a highly stable carri-
er or reference generator by connecting a reference
crystal across terminals 19 and 20. In this case, a small
capacitor (typically 10 to 100 pF) fine tunes the crystal
AM o------j
MODULATION C
c frequency. The multiplier section introduces the ampli-
INPUT.1 20K
tude modulation on the carrier signal generated by the
veo. The balanced nature of the multiplier allows sup-
pressed carrier as well as double sideband modulation
(Figures 22-1 and 22-2). Typical carrier suppression is
in excess of 40 dB for frequencies up to 10 MHz.
Figure 22. Circuit Connection for AM/FM or Crystal·
Controlled AM Generator Application If a timing capacitor is used instead of a crystal, the os-
cillator section can provide highly linear FM or frequen-
cy sweep. The digital control terminals of the oscillator
are used for frequency-shift-keying.

Figure 22·1. Double Sideband AM Output Waveform

fcarrier = 3.688 MHz fmod = 1 kHz Figure 22·2. Suppressed Carrier AM Output Waveform
(90% modulation) fcarrler = 3.688 MHz fmod = 1 kHz

EQUIVALENT SCHEMATIC DIAGRAM

8-10
 XR-1310

Stereo Demodulator
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-1310 is a unique FM stereo demodulator which
uses phase-locked techniques to derive the right and
POWER
left audio channels from the composite signal. Using a SUPPLY
YCO
CONTROL
phase-locked loop to regenerate the 38 kHz subcarrier,
it requires no external L-C tanks for tuning. Alignment is COMPOSITE LOOP
INPUT FILTER
accomplished with a single potentiometer.
COMPOSITE; LOOP
OUTPUT FILTER

PHASE
LEFT OUTPUTI
DEEMPHASIS 11 DETECTOR
INPUTS
FEATURES RIGHT OUTPUTI PILOT
DEEMPHASIS MONITOR
Requires No Inductors
Low External Part Count LAMP THRESHOLD
Simple, Noncritical Tuning by Single DRIVER FILTER

Potentiometer Adjustment
THRESHOLU
Internal Stereo/Monaural Switch with FILTER
100 mA Lamp Driving Capability
Wide Dynamic Range: 600 mV (RMS)
Maximum Composite
Input Signal
Wide Supply Voltage Range: 8 to 14 Volts
Excellent Channel Separation ORDERING INFORMATION
Low Distortion
Excellent SCA Rejection Part Number Package Operating Temperature
XR-1310CP Plastic - 40°C to + 85°C

APPLICATIONS
FM Stereo Demodulation
Stereo Indicator
SYSTEM DESCRIPTION
The XR-131 0 is a complete stereo demodulator specifi-
cally designed for transforming a composite FM stereo
signal into its left and right channel components.

The composite FM stereo input signal, from the receiv-

•
er detector, is applied to the buffer amplifier, Pin 2. Buf-
fered output (gain = 1) is applied to the L + R, L - R de-
coder.

ABSOLUTE MAXIMUM RATINGS The VCO of the PLL runs at 76 kHz, four times the 19
kHz pilot frequency. Free-running frequency is set by
(TA = + 25°C unless otherwise noted) the parallel RC circuit on Pin 14. The VCO output drives
Power Supply Voltage 14V a controlled switch which allows demodulation. When
Lamp Current 75 mA the PLL is locked, the lamp driver open collector output
(nominal rating, 12 V lamp) (Pin 6) can sink up to 100 mA.
Power Dissipation 625 mW
(package limitation) Left and right channel outputs are taken from Pins 4
Derate above TA = + 25°C 5.0 mW/oC and 5 respectively. De-emphasis is performed by the
Operating Temperature -40 to +85°C RC circuit here; slightly higher gain is possible by in-
Range (Ambient) creasing the resistor size, but the RC product should
Storage Temperature Range -65 to + 150°C remain constant.

8-11
XR·1310
ELECTRICAL CHARACTERISTICS
Test Conditions: Unless otherwise noted; VCC* = + 12 Vdc, TA = + 25°C, 560 mV (RMS) (2.8 Vp-p) standard multiplex
composite signal with L or R channel only modulated at 1.0 kHz and with 100 mV (RMS) (10% pilot
level), using circuit of Figure 1.

PARAMETERS MIN TYP MAX UNIT

Maximum Standard Composite Input Signal (0.5% THO) 2.8 Vp-p
Maximum Monaural Input Signal (1.0% THO) 2.8 Vp-p
Input Impedance 50 kn
Stereo Channel Separation (50 Hz - 15 KHz) 30 40 dB
Audio Output Voltage (desired channel) 485 mV (RMS)
Monaural Channel Balance (pilot tone "off") 1.5 dB
Total Harmonic Distortion 0.3 %
Ultrasonic Frequency Rejection 19 kHz 34.4 dB
38 kHz 45
Inherent SCA Rejection 80 dB
(f = 67 kHz; 9.0 kHz beat note measured with
1.0 kHz modulation "off")
Stereo Switch Level
(19 kHz input for lamp "on ") 13 20 mV (RMS)
Hysteresis 6 dB
Capture Range (permissable tuning error of internal ±3.5 %
oscillator, reference circuit values of Figure 1)
Operating Supply Voltage (loads reduced to 2.7 kn for 8.0 14 Vdc
8.0-volt operation)
Current Drain (lamp "off") 13 mAde
*Symbols conform to JEDEC Engineering Bulletin No.1 where applicable.

Vee
o.os .. F

14
470pF
2.0 .. F 0.25 .. F
INPUT 0---} 13 16K

0.02 .. F
12
lK 5K

XR-1310 11

3.9K
19 kHz ':'"
10
MONITOR

0.02,.F

STEREO
LAMP
(100 mAl

Figure 1. Typical Application

8·12
 XR-2216

Monolithic Compand~r
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2216 is a monolithic audio frequency compan-
dor designed to compress or expand the dynamic
range of speech or other analog signals transmitted
through telecommunication systems. The monolithic
circuit can be connected as either a compressor or an AMPLIFIER
expander, the choice being determined by the external COMPENSATION
circuitry. AMPLIFIER
OUTPUT
REFERENCE AMPLIFIER
LEVEL NON· INVERTING
SCALE SET INPUT

FILTER

LOW LEVEL
TRACKING
TRIM
FEATURES
VCC
Functions as either a Compressor or an Expander AC/DC
Wide Dynamic Range: 60 dB CONVERTER
INPUT
Wide Supply Range: 6 to 20 Volts
EXPANDER
Excellent Transfer Function Tracking INPUT
Low Power Supply Drain
Controlled Attack and Release Times
Low Noise and Low Distortion

APPLICATIONS
Telephone Trunk-Line Compandor
Speech/Data Compression and Expansion
Telecommunication Systems
Mobile Communications
Model Data Processing
ORDERING INFORMATION

Part Number
XR-2216CN
XR-2216CP
Package
(16 Pin DIP)
Ceramic
Plastic
Operating Temperature
- 40°C to
- 40°C to
+ 60°C
+ 60°C
•
SYSTEM DESCRIPTION
The XR-2216 is comprised of four basic blocks: (1) an
internal voltage reference; (2) an AC/DC converter
which converts AC signal input to a DC current level;
ABSOLUTE MAXIMUM RATINGS (3) an impedance converter whose impedance level is
a function of 8. DC control signal; and (4) a high gain op-
Supply Voltage 20V erational amplifier.
Power Dissipation
Ceramic Package 750 mW The XR-2216 is deSigned to accommodate a wide
Derate above + 25°C 6 mW/oC range of system configurations. It can be operated with
Plastic Package 625 mW positive or negative single supply systems, or dual
Derate above + 25°C 5 mW/oC power supplies over a power supply range of 6 volts to
Storage Temperature - 60°C to + 150°C 20 volts.

8-13
XR·2216
ELECTRICAL CHARACTERISTICS
Test Conditions: Vc = + 12V, TA = 25°C
COMPANDOR
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Power Supply Voltage 6 20 VDC
Nominal Power Supply Voltage 12 18 VDC
Power Supply Current, No Signal Input 3 mA
Gain Change Over Frequency Tolerance -1 +1 dB 300 - 3500 Hz
Distortion Measured at -4 dB·
Input Level at 1 KHz 3 % THD
Attack Time Measured at -10 dB
Input Level 5 ms To 90 % of Final Value
Decay Time Measured at -10 dB
Input Level 5 ms To 10% of Final Value
Transfer Characteristics··
Compandor Output With Input Levels of:
-4 dBm 3.5 +6 7.5 dBm
-8 dBm -0.5 +2 3.5 dBm
-10 dBm -1.5 0 +1.5 dBm
- 14 dBm (reference) -4 dBm
-24 dBm -15.5 -14 -12.5 dBm
-34 dBm -25.5 -24 -22.5 dBm
-44 dBm -36.5 -34 -32.5 dBm
-54 dBm -49 -44 -42.5 dBm
-64 dBm -59 -54 -52.5 dBm

COMPRESSOR
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Input Impedance 50 'k ohm
Output Impedance 50 ohm
Output Signal Level for -10 dBm
Input at 1 KHz -10 dBm
Output Voltage Swing 0 dB
Output Noise, Input AC Grounded 30 dBrnc
Compressor Transfer Characteristics··
Compressor Output With Input Levels of:
-4dBm -7 dBm
-8 dBm -9 dBm
-10 dBm -10 dBm
-14 dBm (reference) -12 dBm
-24 dBm -17 dBm
-34 dBm -22 dBm
-44 dBm -27 dBm
-54 dBm -32 dBm
-64 dBm -37 dBm

EXPANDER
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Input Impedance 50 k ohm
Output Impedance 50 ohm
Output Signal Level for - 10 dBm 0 dBm
Output Voltage Swing +8 dB
Output Noise Input AC Grounded +5 dBrnc
Expander Transfer Characteristics··
Expander Input Leve!s Required for
Output of:
+6dBm -7 dBm
+2dBm -9 dBm
OdBm -10 dBm
- 4 dBm (reference) -12 dBm
-14dBm -17 dBm
-24dBm -22 dBm
-34 dBm -27 dBm
-44dBm -32 dBm
-55dBm -37 dBm
Notes: '0 dBm = 0.775 Vrms (1 mW across 600 ohm load) • * Recommended transfer characteristics.

8-14
 EQUIVALENT SCHEMATIC DIAGRAM
XR·2216

CIRCUIT DESCRIPTION
The analog signal compressor/expander or "compan- system is comprised of four basic blocks: (1) an internal
dor" circuits are among the most fundamental building voltage reference; (2) an ac/dc converter which con-
blocks in telecommunication systems. These circuits verts ac signal input to a dc current level; (3) an imped-
are intended to compress or expand the dynamic range ance converter whose impedance level is a function of
of speech or other analog signals transmitted through a dc control signal; and (4) a high gain operational am-
telecommunication systems. plifier.

Figure 1 shows the simplified block diagram of a typical The XR-2216 is designed to accommodate a wide
speech transmission system, using the compression/ range of system configurations It can be operated with
expansion or "companding" technique. The dynamic positive, or negative, single-supply systems, or with bal-
range of the input signal is first compressed at the anced power supplies, over a power supply range of
transmitting end; then transmitted through the system, 6 volts to 20 volts.
and finally expanded back to the original amplitude at
the receiving end. Thus, the "compressor" and the "ex- Some of its key features are: low external component
pander" sections of a compand or system perform re- count, excellent transfer function, tracking, low power
ciprocal functions. In a bi-directional transmission sys- supply drain, controlled attack and release times, low
tem, there is a compandor at each end of the line which noise and low distortion.
compresses the out-going signal, or expands the in-

•
coming signal by an equal amount. EXPANDER (Figure 3)
Figure 2 shows the typical transfer characteristics of Figure 3 shows the external circuit connections and
compressor and expander circuits commonly used in components necessary to operate XR-2216 as an ex-
telecommunication systems. In the compressor, the pander. An input signal is applied to Pin 7 which is the
output amplitude varies 1 dB for every 2 dB change of
input amplitude; the reverse is true for the expander. ACIDC converter input. The AC/DC converter converts
the AC signal input to a dc current level which in turn
The functional block diagram of XR-2216 compandor is controls the transconductance of the impedance con-
shown on Page 1, in terms of the monolithic circuit verter. Part of the input signal is applied to the imped-
package. The XR-2216 is designed to be connected as ance converter by connecting Pins 8 and 10. Thus the
either a compressor or an expander, the choice being signal current at Pin 11 is proportional to the product of
determined by the external circuitry. The monolithic the input signal and its average value.

INPUT
,.... SIGNAL
COMPRESSOR -- TRANSMISSION
SYSTEM -
.- SIGNAL
EXPANDOR -1 TT
600n
16°on
Figure 1_ Simplified Block Diagram of a Speech Transmission System USing Companding Technique

8-15
XR·2216
The output signal current is then fed to the operational
amplifier by connecting Pins 11 and 16, and the output
signal voltage is directly proportional to the signal cur- -10 Iv
rent flowing into Pin 16. The output signal of the ex-
pander is available at Pin 2. In this operation, the refer- -20
V
V f
ence level is set by the trim pot R1, and the trim pot R2 COMPRES/

provides a means for trimming low level tracking. -30 I

In the connection of Figure 3, the input signals of - 37
dBm to - 7 dBm are expanded to 60 dB output range
-40
,/
/'
V
with up to 0 dBm power matched output to 6000 load.
-50 /
COMPRESSOR (Figure 4) -60
/ EtPANfER

-80 -70 -60 - 50 -40 -30 -20 -10 0

Figure 4 shows the typical circuit connection for com- INPUT (dBm)
pressor operation. It is just a non-inverting voltage am- Figure 2. Transfer Characteristics of Compressor a
plifier whose input level is proportional to the product of Expander Circuits
the incoming signal and the impedance of the imped-
ance converter which is inversely proportional to the
amplifier output. Consequently, the output signal at Pin EXPANDER
2 is proportional to square root of the input signal. OUTPUT o-JVVI,r-,

In this operation, just like expander operation, the refer-

ence level is set by the trim pot R1 and low level track-
ing is adjusted by the trim pot R2. In the connection of
Figure 4, the output change is 1 dB for 2 dB input
VCC
change. The output range can be adjusted to - 37 dBm
to - 7 dBm for input signals of 60 dB dynamiC range.

Note: Attack and Decay Times:

l00"F ~C
The speed with which gain changes to follow changes
in input signal levels is determined by the capaCitor C1
and the resistor R1. A small capacitor will yield rapid re- Figure 3. External Connections for Operation Expander
sponse but will not fully filter low frequency signals. Any
ripple on the gain control signal will modulate the signal
passing through the impedance converter. In an ex-
pander and compressor application, this would lead to
a 3rd harmonic distortion, so there is a tradeoff to be
made between fast attack and decay times, and distor-
tion.

COMPRESSOR
OUTPUT

TYPICAL PERFORMANCE CURVES Figure 4. External Connections for Compressor Operation

~ .1 t--t-t--t-t::::;;;j;;;;;;;:;:t:=
'"
~ tll--~-+---t--+-+--/~ ",-
o
~... ~
...
O~-+-~~~~--T-~-~

:J
~ o~~-,~~-~-y~ ~ -1 I----¥-b"-I----t---r-T A. -15 C
'"o
z0{
~ -11---+-+---t--r-+-~-,
i-2
Z
~
REHR(NCE LEVEL
U
T A • 25 C_INPUT' -14dBm

8 -3 - ~~~~~C~~ • 0
-10 dBrn RO • 600n
-2~~ __~~__~~~~~ -4~~ __ ~~ __ ~ __ ~~ __ ~

-70 -60 -50 -40 -30 -20 -10 -70 -60 -so -40 -30 -20 -10
COMPRESSOR INPUT SIGNAL. dBm600n EXfANDER OUTPUT SIGNAL dB COMPANDOR INPUT SIGNAL, dBm 600n

Figure 5. XR-2216 Compressor Output Figure 6. XR-2216 Expander Input Figure 7. XR-2216 Compandor
Error vs. Input Signal Amplitude Error vs. Output Signal Amplitude Tracking Error vs. Input Signal

8-16
 XR-2264/2265

Pulse-Proportional Servo Circuit

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2264 and 2265 are Monolithic circuits designed
for use in pulse-proportional servo systems. They have
been specifically designed for Radio Control applica-

!~'"
tions. These devices are capable of controlling posi- VCC
tions in direct proportion to the width of input pulses. STRETCHER
RC
The 2264 can interface directly with servo motors re- BOOST
OUT
quiring up to 350mA of drive current. The 2265 with
open collector outputs can drive relays, optical coup-
OUT VR£G
lers and triacs, directly. Both the 2264 and 2265 can
drive external PNP transistors for applications requiring
high current output drive. GROUND GROUND

The XR-2264 or 2265, combined with a servo motor and

a feedback potentiometer form a closed-loop system.
These devices have internal one-shot multivibrators.
The pulse width of this one-shot is controlled by the ser-
vo potentiometer. When an input pulse is applied, the
OUT

BOOST
OUT
!""'
RC NO

motor is turned "on" in the direction necessary to make Vce PULSE

the internal one-shot pulse width equal to the incoming IN
pulse width. Because the transfer characteristics of the
XR-2264 and 2265 can be controlled by the selection of
external components, it can be used in many industrial
and radio controlled servo-system applications.
ORDERING INFORMATION
Part Number Package Operating Temperature
FEATURES
Wide Supply Voltage Range (3.0V to 6.0V)
Bi-directional Operation with Single Supply
Separately-Adjustable Dead Band and Pulse Stretching
2264 - 350mA Source and Sink on chip.
XR-2264 CP
XR-2265 CP
Plastic Dual-
In-Line
- 10°C to + 50°C

II
500mA with External PNP
2265 - 500mA Sink Capability on chip. SYSTEM DESCRIPTION
500mA Sink or Source Capability with external PNP
Figure 3 shows the circuit connection diagram for the
XR-2264. The external component values shown are
selected for a pulse width range of 1 to 2 msec, a frame
time of 12.5 msec, and a dead band* that is suitable for
APPLICATIONS use with small radio-controlled servos. However, with a
proper choice of external components, the characteris-
Remote Control Toys tics of these devices can be adapted to provide opti-
Robotics Applications mum performance for a broad range of hobby and in-
dustrial servo control applications.

The shaft of potentiometer R2 is connected to the servo

ABSOLUTE MAXIMUM RATINGS output shaft; the voltage on the wiper provides position-
al feedback to the one-shot multivibrator of the XR-2264
Supply Voltage 6.5V or 2265. The one-shot pulse width range is set by the
Power Dissipation 550 mW product of R1 and C1; R1 should be kept in the range of
Storage Temperature Range - 65°C to + 150°C 8KO to 16KO. For operation over a range of pulse widths

8-17
 XR·2264/2265
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 5.0V, TA = 25°C

LIMIT
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Supply Voltage 3.2 5.0 6.5 V
Supply Current 4.5 10.0 mA Measured into Pins 1 & 7
Regulated Output Voltage 2.0 2.2 2.4 V Voltage at Pin 12
Input Current 0.1 mA
Input Voltage Range 2.4 6.0 V
Pulse Timing Error ±300 ItSec Initial Setting 1.07 sec;
Curcuit of Figure 3

OUTPUT CHARACTERISTICS

LIMIT

DEVICE PARAMETER MIN TYP MAX UNITS CONDITIONS

2264 Output Current Range 0 500 mA I sink
Output Current Range 0 350 mA I source
VCE 0.25 V I sink 500mA
VCE (VCC - VOH) 1 V I source 350mA
2265 Output Current Range 0 500 mA I sink
VCE 0.25 V I sink 500mA

of less than 2 to 1, the value of potentiometer R2 may

be reduced; the value of the 2.2KO resistor to ground
should be increased by about the same amount.

The voltage on C2 provides the input signal for the Sch-

mitt trigger. In order for the motor to be driven, pin 14
must remain low, long enough to pull C2 down to the
lower threshold via R3. The motor will be turned off only
after pin 14 has turned off and C2 has charged to the
upper Schmitt trigger threshold through R4. Thus, the
dead band is controlled by C2 (R3 + Ri) where Ri is the
"on" resistance at Pin 14. The pulse stretching is con-
trolled by the product of C2 and R4. Figure 4 shows the
effect of R3 and R4 upon the dead band and pulse- A. TRANSMITTED
SIGNAL
. .f.IIl.............I-III-I...._ _...
stretching performance of the XR-2264 with C2 F
0.22JtF. !

*Note: The "Dead band" is the narrow region about a

given shaft position which 2264 will not produce a
Stretched Pulse larae enouah to drive the motor. Some
dead band width is necessary because the motor shaft
has inertia; otherwise, the motor would never stop
"hunting" its target position. Figure 2. Radio Control System

8-18
 XRII2264/2265

-200 - ISO - 120 -so INPUT P.W. - OUTPUT P.W .• SEC

- ISO - 140 - 100 -60 SO so 100 120 1.0 ISO ISO 200

c
A 7Ml 1!)1(
*NOTE: XR-2264 01 and 02 optional; only needed for B -11
• XJ01I 751(
C 1]1(
Servos requiring 500mA drive current.
**NOTE: XR-2265 01 and 02 needed if output current
source is required.
Figure 3. Connection Diagram of XR-2264 and XR-2265 Servo Figure 4. XR-2264 and XR-2265 Output vs. Input Showing
ControllC Dead Band. Circuit of Figure 3

8-19
 XR-2266

Monolithic Servo Controller

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-2266 is a monolithic servo controller specifi-
PULSE STRETCHER
cally designed for radio controlled model cars. The de- SPEED SERVO
vice is capable of controlling speed in forward or re- PULSE STRETCHER
verse, direction of turn, backup lights, and turn signals STEERING SERVO

with programmable flash rate. Supply voltage may CAPACITOR FOR

STEERING SERVO
S"EED SERVO
OUTPUT
range from 3.5V to 9V.
CAPACITOR FOR SPEED SERVO
SPEEOSERVO OUTPUT

REFERENCE GENERATOR 5 t--I---t-...... BACKUP

LIGHT

SERVO POT INPUT 6 I-.=.;:t::====~ VCC

DIRECTIONAL SIGNAL STEERING SERVO

TIME CONSTANT OUTPUT

BLINKER OUTPUT 8 STEERING SERVO

OUTPUT

FEATURES BLINKER OUTPUT 9 GROUND

Internal Channel Divider

Internal Steering Servo with Direct Drive for
Servomotor and Turn Signal Indicators
Directional Signal Time Constant
Externally Settable
Variable Speed Control with Direct Drive
for Backup Lights
Wide Supply Range (3.5 - 8.0 volts)
Steering and Speed Servos Independently ORDERING INFORMATION
Programmed
Part Number Package Operating Temperature
XR-2266 Plastic O°C to + 70°C

SYSTEM DESCRIPTION
APPLICATIONS "
The XR-2266 is a monolithic servo controller system
Radio Controlled Cars specifically designed for radio-controlled model cars.
The integrated circuit is a self-contained system made
up of two servo controller channels: one controls the
direction and speed of travel, the other provides the
steering function. The circuit contains an internal chan-
nel separator section which automatically steers the in-
coming control signal to the appropriate servo control-
ler channel.

The entire servo controller system is available in an 18-

Pin dual-in-line package, with terminals provided for ac-
ABSOLUTE MAXIMUM RATINGS cessory controls such as turn indicator signals and
backup lights. The entire system is fabricated on a
Supply Voltage 9V monolithic chip, using low-power integrated injection
Power Dissipation 1100 mW logic (12L) technology along with precision analog cir-
Derate above TA = 25°C 6 mW/oC cuitry. It operates with supply voltages in the range of
Storage Temperature Range -65°C to + 150°C 3.5 volts to 8 volts.

8·20
ELECTRICAL CHARACTERISTICS
XR·2266
Test Conditions: VCC = 6 Volts TA = 25°C unless otherwise specified

LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Supply Current 30 mA
Operating Supply Range 3.5 6.0 8.0 V
Input Threshold 0.7 V
Reference Generator Output Current 100 p,A Measured at Pin 6
Directional Detector
Pin 5 Voltage 55 % Voltage at Pin 6 (Blinker "off")
Pin 5 Voltage 61 % Voltage at Pin 6 (Pin 8 Blinker "on")
Pin 5 Voltage 48 % Voltage at Pin 6 (Pin 9 Blinker "on")
Output Current 100 mA
Steering SERVO
Output Soruce Current 350 mA Pin 11 or 12
Output Sink Current 350 mA Pin 11 or 12
Reverse Detector
Output Current 100 mA Pin 14
Speed Control Servo
Output HIGH Voltage VCC-1V V Pin 15 or 16
Output Low Voltage 0.2 V Pin 15 or 16
Output Impedance 700 (} Pin 15 or 16

II

8-21
XR·2266
PRINCIPLES OF OPERATION tection circuit has also been built into the IC to detect
when the car is going in reverse and turn on the backup
The theory of operation can be explained with refer- lights.
ence to the block diagram of Figure 2 and the timing di- SYSTEM BLOCKS
agram of Figure 3. The direction and speed information
are encoded onto a carrier by either Amplitude Modula- The XR-2266 is comprised of three independent sys-
tion (illustrated Curve A) or Frequency Modulation (not tems internally connected as in Figure 4 to perform the
shown). This signal is received and demodulated into complete car function. These blocks are the channel di-
Waveform B. The timing of Waveform B is as follows: TF vider, steering servo and a speed control circuit. (While
is the frame time and determines the frequency with a total understanding of these circuits is not necessary
which the servos are controlled. TS is a space pulse a fundamental knowledge of the operation of each
used to separate the channel information of T 1 and T2. block will be an asset to any servo design.)
The width of T1 and T2 contain the steering and speed
information respectively.

Waveform B is applied to the input of the XR-2266. This

signal is integrated into Waveform C which is then
squared to form D. Waveform D is used as a reset to the
channel divider circuit. The channel divider circuit trig- CHANNEL
DIVIDER
gers on the leading edge of the input signal and gener-
ates two outputs; one for steering and the other for the
speed control; Waveforms E and F, respec"vely.

Waveform E is applied to the input of Servo No.1 which

serves as the positional control for the steering wheel. Figure 4. Three Primary Systems of XR·2266
The servo pot on the linkage forms a closed loop sys-
tem with the servoamplifier to position the front wheels
to the required position. The servo pot is also connect- Channel Divider: The function of the channel divider is to
ed to the directional indicator circuit which determines decode the channel information from the demodulated
whether the wheels are turned enough to enable the input signal and to synchronize the receiver to the
blinker lights. transmitter. The synchronization is required to assure
that the decoded input is applied to the correct servo.
Waveform F is the input to the variable speed control The generation of the synchronization Signal is illus-
servo. This servo determines the error between the in- trated in Figure 3 and can be explained as follows: The
put signal and the preset nominal value and applies input signal B is integrated by the RC time constant on
drive to the motor proportional to this difference. A de- pin 2 to form waveform C. This integrated Signal is then
squared to form the synchronization signal D. This sig-
nal resets the channel divider when high, guaranteeing
that the first input be directed to the channel one servo
and the second input be directed to the channel two
servo, as illustrated by waveforms E and F, respectively.
The width of the input signals is determined by the time
interval between two successive positive gOing edges
of waveform B. After the channel two input ends, the in-
tegrator charges up to the reset level and enables
channel one for the next rising edge of the input signal.
The time constant for the integrator is externally set by
the RC time constant on pin 2. It is recommended that
the time constant be chosen such that the reset occurs
midway between the input frame time.

:
~LJLJI
••
t:.Tlt!2~ ••
______________~~~_____________~~_________ ••
Tsl f.o- IF I
~ ~ ~
~ \ \~--------~
L--Jrl rl r1~ _______________________
~ ___~rl rl rt~ _________________
Figure 3. Timing Diagram

8·22
Steering Servo: The block diagram of the steering ser- Speed Control Circuit: The channel two output Waveform
voamplifier is illustrated in Figure 5. The primary func- F from the channel divider, as shown in Figure 7, is ap-
tion of this block is to control the position of the front plied to the input of the speed control servo. This circuit
wheels of the car in direct proportion to the input pulse is similar to the steering control servo with the excep-
width. The XR-2266 has the additional feature of being tion that it is operated in an open loop configuration.
able to detect the magnitude and direction of the posi- Thus, the duty cycle of the output drive increases until
tion of the wheels from their center position and if it is a maximum drive is reached. The drive characteristics
greater than an externally preset amount, to activate a for the speed control are set independently of the steer-
blinker circuit for the appropriate turn-direction. The op- ing by an RC time constant on pin 18. Due to the high
eration of the steering servoamplifier can be explained power motors required for speed control, an external
with reference to the block diagram of Figure 5 and tim- driver transistor must be used. A typical connection for
ing diagram Figure 6. On the leading edge of the input these transistors is illustrated in Figure 7. The speed
signal an internal one-shot is triggered. The one-shot control amplifier also features an additional output for
generates an output pulse whose width is directly pro- the backup lights. This output is obtained from the di-
portional to the present position of the shaft of the ser- rectional logic which determines whether the car is go-
vomotor. The position information is supplied via the ing in the forward or reverse direction. The motor termi-
servo pot. The width of these two pulses are then com- nals could also be reversed and the output used to
pared and two error signals are generated; one is the drive the front headlights when the car is going forward.
directional error which is used to determine the output The output for the driver lamps is an open collector
drive direction and the other is the magnitude error transistor and is capable of sinking 100 mA. Since this
which is applied to the pulse stretcher section which is an open collector output, care should be taken to
determines whether the error was of sufficient magni- avoid any possible shorting to the VCC pin, as this will
tude to enable the output driver stage. If the dead band damage the device.
is exceeded, the error pulse of several microseconds is
then stretched to several milliseconds of output drive.
The dead band is required to assure that the motor
does not oscillate about its center point. The XR-2266
has internal driver transistors that are capable of sink-
ing or sourcing 350 mA. The positional information from
the servo pot is also applied to a window comparator
and the output of this circuit determines the deviation
of the steering wheel from its center position. If this is
greater than the preset amount, the blinker signals are
activated. The time constant of the blinkers is set by the
capacitor on pin 7. The blinker outputs are open collec-
tor type capable of sinking 100 mA each. Figure 7. Speed Control Servo System with Connection for
External Driver Transistors

DESCRIPTION OF CONTROLS
Input (Pin 1): 1 he demodulated output from the receiver
is applied to this pin. The threshold for the input is ap-
proximately 0.7V. It is recommended that a 0.0022 /LF
II
capacitor be connected from this paint to ground to
eliminate any RF Signal at the input.

Reset Integrator (Pin 2): The function of this pin is to syn-

chronize the servo control to the transmitter. This as-
Figure 5. Steering Servo System sures that the steering and speed control signals are
not interchanged. The time constant used for this cir-
cuit is dependent upon the frame time of the input sig-
nal. For a 15 millisecond frame, the value for R1 is 510K
and for C1, 0.1 /LF. Other frame rates may be used, in
which case the RC time constant may be determined by
the following equation:

where
TF = Frame Time
X = Number of Servos
TN = Nominal Pulse Width for Servos
VCC = Nominal Supply Voltage
Figure 6. Timing Diagram

8-23
XR·2266
Timing Cap for Steering Servo (Pin 3): The capacitor on this Pulse Stretcher (Pin 17 & 18): The RC time constant on pin
pin is used to determine the nominal one-shot time con- 17 and pin 18 is used to set the dead band and the max-
stant for the steering control. The capacitor value is imum drive pulse to the steering servo and speed con-
chosen by the following equation: trol servo, respectively. The dead band time is deter-
mined by:

TdB = (51.4)(C)
where R2 is a 1 K potentiometer and Rp is the servo pot,
nominally 5K. This yields 0.47 JlF for C2. RF is a damp- The maximum drive time is determined by:
ing resistor that provides a momentum feedback to pre-
vent the servo from overshooting. The recommended TMD = RC1n [(Vcc - .73e-(1x10 -6/C))/(VCC - .66)]
values for RF are 100K to 700K, depending on the re-
quired loop damping. Power Supply (Pin 13 & 10): The battery should be con-
nected from pin 13 (VCe) to pin 10 (ground). The operat-
Timing Cap for Speed Control (Pin 4): This capacitor deter- ing power supply range is 3.5 to 9 volts. A 100 JlF ca-
mines the nominal one-shot time constant for the speed pacitor is recommended across the power supply ter-
control servo. The capacitor value is determined by: minals.

APPLICATION EXAMPLE
Reference Generator (Pin 5): Pin 5 is used to generate the The method for determining the component values for
reference level for the speed and steering servos and any servo application can be obtained by the following
also control the degree of turning before the directional design rules. These equations will yield values suitable
indicators are activated. This pin is directly connected for proper operation and can later be adjusted to suit
to one end of the servo pot with the other connected to particular applications. For the example chosen, the
a 1 K pot or fixed resistor to ground. This 1K pot is used frame time is 15 ms and the pulse width is nominally
to adjust the dead time for the directional indicators. In 1.4 ms with a deviation of 500 Jls. Dead band is chosen
noisy environments, pin 5 should be bypassed to to be 30 Jls and 80 Jls for the steering and speed control
ground via a 0.001 JlF capacitor. sections, respectively. The servo pot is a 5K pot and the
operating supply voltage is 6 volts.
Steering Positional Input (Pin 6): The wiper of the servo pot
is connected to this pin to supply the positional informa- Procedure:
tion to the one-shot of the steering servo. In noisy envi-
ronments this pin should be bypassed to ground via a 1. To determine the time constant of the integrator on
0.002 JlF capacitor. pin 2, use the following formula with R1 assumed to
be between 100K and 1M. In this example we set C1
Directional Signal Time Constant (Pin 7): The capacitor con- = 0.1 JlF and calculate R1.
nected to this pin determines the time constant for the
directional indicators. The ratio of 'ON' to 'OFF' is ap- R1 = [TF - X(TN)]/2C 11n[VCC/(VCC - .66)]
proximately 2:1 and the frequency is determined by:
This yields R1 "" 510K
F(Hz) = 81/C4 (JlF)
2. C3 and R2 setting (using a 1 K pot) is determined by
Outputs for Directional Indicators (Pin 8 & 9): These pins are the following: First approximate R2 to be one half of
used to drive the directional signal indicators. These its value and solve for C3.
are open collector outputs that can sink a maximum
current of 100 mA. C3 = 1.3TN/(R p + R2/2)

Steering Motor Drive (Pin 11 & 12): These outputs connect C3 "" .33 JlF
directly to the steering servomotor and are capable of
sinking or sourcing 350 mA. C3 = 0.25 JlF

Output for Backup Lights (Pin 14): This terminal is acti- Select nearest standard value for C3 and calculate
vated when the car is driving in the reverse direction. R2 value
This is an open collector output with a maximum cur-
rent of 100 mA. R2 = (1.3TN/C3) - Rp

Note: by reversing the motor leads, this terminal could R2 "" 5150
be used to control front headlights when the car is mov-
ing forward. 3. C2 is determined by the following: Use value for R2
as calculated above.
Output for Speed Control (Pin 15 &16): These pins are used
to drive an external power bridge to control the speed C2 = TN/(R2 + Rp/2)
of the car. A typical connection is illustrated in Figure 7.
C2 "" .47 JlF

8-24
4. C4 determines the blinker frequency, for a frequency 9. Set RF = 510K. To
XR·2266
adjust value see Table I.
of 2 times per second.
The complete circuit with the calculated values is illus-
C4(Hz) = 81/F(Hz) trated in Figure 8. The circuit layout is illustrated in Fig-
ure 9.
C4 "" 47.0 IlF
Table I lists the recommended values for the servo ap-
5. C5 determines the dead band time for the steering plication outlined above and describes the result if im-
servo for most car applications. This is chosen to be proper values are used.
approximately 30 Ils. Solving for C5 yields:

C5 = TdS/51.4

C5 "=' .471lF

6. R5 is selected via the formula

R5 = TMD/[C1 n(Vcc - .73e - (1x1 0 - 6/4C))IVCC - .66)]

R5 = 910K

7. C6 is chosen with the same formula as C5 except

dead band is set to approximately 80 Ils. This gives
the system better speed control.

Figure 8. Typical Application Schematic

8. R6 is chosen via the same equation as R5.

R6 = TMD/[C1 n(VCC- .73e-(1X10- 6/C))IVCC - .66)]

R6 = 430K
XR-2266 ,~ Vee GND
. IN

1·~6,_J',',.','
: "',";,;::-. -: ~ '. ~ ~ '.-
'O"~; • 1 • '

-Rlf+&:Cl
-II- C2
•
~
--fl-- C3

05 ~I-- .001

+ --II-- .0022

---i ....... 33 j.tF-e4

---fH-:, "f'" IK
100. ;,' F' :,-,.:.<
:.~~ .' .
.,.,,:
-

';<:,,:

GND MO MO BL Vee so so GND WF WL WL DR SA

Figure 9. Printed Circuit Board Layout (4x)

8-25
XR·2266
TABLE I

COMPONENT
NUMBER VALUES EFFECTS
R1 Small The integrator rise time becomes too fast and the fall time becomes too slow.
510K Therefore, the integrator may reset too soon.
Large The integrator rise time becomes too slow and the integrator may not reset
before the next input.
Recommended 200K - 700 K carbon film R25 series.
RF Small Too much negative feedback occurs, causing the response of the servo to be
510K too slow.
Large Almost no negative feedback occurs and a large positional overshoot results.
Recommended 100K - 800K should be selected by the actual test results (dependent upon
motor gears and linkage used). Carbon film R25 series.
R5 Small The pulse stretcher gain becomes too small and this reduces output drive time
910K causing wheels to turn slowly.
Large The pulse stretcher gain becomes too large and the motor tends to oscillate
(hunt) about its position.
Recommended 500K - 1M, largely dependant upon the value of C5, frame time and maximum
deviation of the input pulse width. The equation for determining the nominal
value is given in the "Description of Controls" section for pins 17 and 18.
R6 Small The pulse stretcher gain becomes too small and the maximum speed of the car
430K is reduced.
Large The pulse stretcher gain becomes too large and the car speed becomes hard to
control. It is either 'ON' full, or 'OFF'.
Recommended 400K - 700K, depending on the value of the capacitor; since this is for the
speed, the dead band width is set larger and pulse stretcher gain is set high.
Carbon film R25 series.

~~
Recommended This is the servo pot connected to the steering linkage, a B type volume
potentiometer is recommended.
R2 Recommended This potentiometer is used to set both the neutral position for the speed control
1K and the range of operation for the directional indicators. A temperature stable
carbon type is recommended.
C1 Small The charging time tends to be short and the discharging time constant tends to
0.1 p.F be long, therefore, the integrator may reset too soon.
Large The charging time tends to become long and the integrator may not reset before
the next input.
Recommended If R1 = 510K, C1 should be between 0.047 p.F to 0.22 p.F. Mylar recommended.

8-26
 XR·2266
COMPONENT
NUMBER VALUES EFFECTS
C2 Small The width of the one-shot for the steering servo becomes too small and the front
0.47 J.tF wheels may turn fully in one direction.
Large The width of the one-shot for the steering servo becomes too large and the front
wheels may turn fully in one direction.
Recommended If the nominal input width is 1.4 ms, 0.47 J.tF is recommended. For operation
with other conditions, see "Description of Controls" section for pin 3. Tantalum
type is recommended.
C3 Small The width of the one-shot for the speed control servo becomes too small and
0.33 J.tF drive occurs in only one direction.
Large The width of the one-shot for the speed control servo becomes too large and
drive occurs only in one direction.
Recommended If the nominal input width is 1.4 ms, 0.33 J.tF is recommended. For operation
with other conditions, see "Description of Controls" section for pin 4. Tantalum
type is recommended.
C4 Recommended This capacitor determines the direction signal time constant. The capacitor
33 J.tF value is determined by the equation in the "Description of Controls" section for
pin 7.
Cs Small Dependent upon the value of RS. Generally the pulse stretcher gain becomes
0.47 J.tF smaller, thus, slowing down the general speed and making acute turns slower.
This also decreases dead band causing hunting about its position.
Large Depending on the value of RS, the pulse stretcher gain becomes extremely
large and although turning speed improves, the hunting condition becomes
worse. This also increased dead band causing the motor to jump position.
Recommended In case of RS = 910K, 0.1 J.tF to 0.68 J.tF is suitable. Tantalum type is
recommended.
C6 Small Depending on the value of R6, the pulse stretcher gain becomes smaller and
1 J.lF you cannot achieve 100 % drive; also, the dead band is reduced and the neutral
position on the stick may be eliminated.

•
Large The pulse stretch gain increases causing rapid increase in speed, once the
dead band is exceeded; also, the dead band increases causing a long amount
of neutral position in the control stick.
Recommended In case of R2 = 430K, 0.68 to 2.2 J.lF is suitable. Tantalum type is
recommended.
C7 Recommended As mentioned in the "Description of Controls" section for pin 2, this value
2200 pF should be between 0.001 and 0.01 J.lF. Ceramic or mylar is the best choice.
C8 Recommended As mentioned in the "Description of Controls" section for pin 5, this value
1000 pF should be between 0.01 and 0.001 J.tF. Ceramic or mylar are recommended.
C9 Recommended Same as above.
C1Q Recommended As mentioned in the "Description of Controls" section for pin 10 and 13, this
100 J.tF capacitor helps to stabilize the power supply when the car is running. If
operation becomes intermittent, this value should be increased. Recommended
10 to 470 J.lF tantalum.

8-27
 XR-2917

Frequency-to-Voltage Converter
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

The XR-2917 Frequency-to-Voltage Converter is a high

accuracy converter consisting of input comparator with
40 mV hysteresis, charge pump, Zener regulator, and out-
put op amp and transistor. Designed for tachometer and +TACH
NC
motor control applications, it features excellent linearity IN
and high current output. TIMING NC

Output voltage is a simple function of the Zener regulator

voltage (VZ), a resistor (Rl) and capacitor (Cl) which are LOAD GND
connected to the charge pump, and the input freq uency
(fin). Ripple reduction is implemented by addition of one NON -TACH
capacitor (C2) which is used to achieve frequency doubling. INVERTING IN
The output transistor can swing to ground, sink a load EMITIER INVERTING
current of 40 mA. and offers a maximum VCE of 28 V. OUT
Stable and accurate frequency to voltage or current con-
version is ensured by the on-chip Zener regulator which is NC Vz
connected across the power leads. The Zener may be used
with any supply voltage (up to 28 V) when a suitable COLLECTOR
NC
OUT
resistor is connected between the Zener and the supply.

The XR-2917 may be operated with a ground referenced

input or differential tachometer input with uncommitted
op amp inputs. The ground referenced configuration is SYSTEM DESCRIPTION
most basic, allowing the realization of single speed, fre-
quency switching, and buffered frequency-to-voltage or The XR-2917 converts an input frequency to a propor-
current conversion applications. Differential input con- tional output voltage. Differential inputs provide hysteresis
figurations allow the tachometer to be floated, while for excellent noise rejection and the capability of setting
uncommitted op amp inputs free the op amp for imple- the comparator's input switching level. Inputs should not
mentation of active filter conditioning of the tachometer be taken below ground without some lead resistance.
output.
The output of the comparator is fed into a charge pump
The XR-2917, available in a 14 Pin DIP, operates from a where current is pumped through a timing capacitor (Cl).
single power supply of up to 28 V. This same current is mirrored in the load resistor (Rl)
where a filter capacitor (C2) may be used to integrate cur-
rent pulses and provide a proportional voltage across the
FEATURES
load resistor. The result is a voltage across the load resis-
tor which is a function of the supply Voltage, input fre-
Design Simplicity: VOUT = fin x Vz x Rl x Cl
quency, timing capacitor, and load resistor:
Frequency Doubling to Decrease Output Ripple
On-Chip Zener for Functional Stability
Excellent Linearity
Floating Output Drive Transistor Provides
The size of the integrating capacitor (C2) is dependent
40 mA Source or Sink
only on the requirements of response time and output
Ground Referenced Tachometer Input Wh ich
ripple.
Interfaces Directly with Variable Reluctance
Milgnetic Pickups.
The output op amp and transistor are then used to buffer
the output drive capability of the part. Thus, the final con-
version equation is:
ORDERING INFORMATION
Va = Vz x fin x Cl x Rl x K
Part Number Package Operating Temperature
XR-2917CN Ceramic O°C to +70°C where K is the gain provided by the tachometer section,
XR-2917CP Plastic O°C to +70°C and is typically unity.

8-28
XR-2917

ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = +12 V, TA = 25°C, unless otherwise specified.

SYMBOL PARAMETERS MIN. TYP. MAX. UNIT CONDITIONS

TACHOMETER

VT Threshold Voltage ±10 ±15 ±40 mV VIN=250mV@1 KHz

VH Hysteresis Voltage 30 mV
VOS Input Offset Voltage 3.5 10 mV
IB Input Bias Current 0.1 1 pA VIN = ±50 mVOC
VOH Minimum High Level
Output Voltage 5.1 V VIN = +125 mVOC
VOL Maximum Low Level
Output Voltage 1.2 V VIN = -125 mVOC
IT,lL Charge Pump Currents
(Tim ing, Load Pins) 140 180 240 pA VT = VL = 6.0 V
IOL3 Output Leakage Current
(Pin 3) 0.1 pA IT=OV,VT=OV
Linearity 0.3 1.0 % Note 1
K Gain Constant 0.9 1.0 1.1

OP AMP COMPARATOR

VOS Input Offset Voltage 3 10 mV VIN=6.0V

IB Input Bias Current 50 500 nA VIN = 6.0 V
VCM Input Common Mode
Voltage 0 VCC-l.5V V
AO Open Loop Voltage Gain 200 V/mV
lSI Output Transistor
Sink Current 40 50 mA Vc = 1.0 V
ISO Output Transistor

•
Source Current 10 mA VE = VCC -2.0V
VSAT Transistor Saturation Voltage 0.1 0.5 V lSI = 5 mA
1.0 V ISI=20mA
1.0 1.5 V lSI = 50 mA

ZENER REGULATOR

Vz Zener Voltage 7.56 V RDROP = 470n

rz Equivalent Zener Reistance 10.5 15 n
Temperature Stability +1 mVtC

DEVICE CHARACTER ISTICS

IS Supply Current 3.8 6 mA

Note 1: Non-linearity is the deviation of VOUT@ fin = 5 KHz from the line defined by VOUT @ fin:; 1 KHz and VOUT@ fin = 10
KHz with Cl = 0.001 pF, Rl = 68 k!l and C2 = 0.22 pF.

APPLICATIONS ABSOLUTE MAXIMUM RATINGS (ROROP = 470 m

Frequency-to-Voltage Conversion Power Supply Voltage (Pin 9) 28 V dc
Speedometers Input Voltage Range
Breaker Point Dwell Meters Tachometer 0.0 V to +28 V dc
Tachometers Op Amp and Output Transistor 0.0 V to +28 V dc
Speed Sensing and Control Supply Current 25 mA
Governors Storage Temperature Range -55°C to 150°C
Touch, Contact, or Delay Switching Operating Junction Temperature 150°C
Power Dissipation 500mW
Derate Above 25°C 5.3 mW/oC

8-29
 XR-2917

11

r--,
ZENER REGULA TOR

12o---+-",

- - - - - - - - - - --------1
I
I I
I I
I I
I I
I I
I I
I I
I I
I I
1 .".1 I
L __ -=: _____ J I I
INPUT HYSTERESIS AMPLIFIER I
L _____ _
----------~
CHARGE PUMP
EQUIVALENT SCHEMATIC DIAGRAM

Vee

r1-;::=~--<l ISINK

'----~---(') ISOURCE

Figure 1. Test Circuit

8-30
XR-2917

TYPICAL CHARACTERISTICS RDROP = 470 n, Vee = 12 V, unless noted_

TACHOMETER LINEARITY TACHOMETER LINEARITY

VS TEMPERATURE VS TEMPERATURE
1.0 1.0
a:
~ 0.9 Vcc =: 12V
- f = 200 Hz
o
a:
Vcc == 12V
0.9 f- f = 1000 Hz -+---t--+--t---I
a: a:
0 0.8 r- R1 = 70K w 0.8 f- R1 = 70K --+--+---1--+---1
a:
a: C1 = 50iJF >- C1 =
lOiJF
w 0.7 f- 0.7
>-
f- 0.6
a:
« 0.6
a:
~
w
z
w 0.5 :i 0.5
z Will"""""
0.4 a: 0.4
:i w
f- f-
W 0.3
::> 0.3
a. ~
f-
::> 0.2 o 0.2
::t:
0 (J
0.1 «
f-
0.1

0 o
-35 -15 5 25 45 65 85 -35 -15 5 25 45 65 85

TEMPERATURE (0C) TEMPERATURE (0C)

TACHOMETER INPUT HYSTERESIS

TACHOMETER LINEARITY VS R1 VS TEMPERATURE
1.0 40
;;-
r I I I I .s
~ 0.9
VCC = 12V (f)
38
a:
0
a:
a:
0.8 r f = 1000 Hz
R1C1 == 3.0-3.5ms·
enw
a:
36
34 ~
- .......
w
~~
w 0.7

-
f-
>- 0.6
(f) 32
f- >- ~
a: I
30 ~ ~~
~ 0.5 f-
w
z
:i 0.4
I"IIIIIIii ~ ::>
a.
~
28 ..
24V ~ ~ ~ """"""
/. ~ ~
f-
::>
a.
0.3
'" ~
a:
w
f-
26 16~
12V", ~
fI"
II
-
f- w 24
::>
0
0.2
0.1
"'" - 0
(J
~

I
22 8V4 fI"
I

0 « 20
f-
-35 -15 5 25 45 65 85
100K 200K 300K 400K 500K

R1 (Q) TEMPERATURE (0C)

OP AMP OUTPUT TRANSISTOR

OP AMP OUTPUT TRANSISTOR
CHARACTERISTICS (25°C)
CHARACTERISTICS
3.0 2.0
2.8 1.8
2.6 1.6
;;- 2.4 1.4
a:w ~
f- 2.2 -00IIIIII z 1.2
0
..... ~"'"
f-
f=
~ 2.0 ~ 1.0
>
w
....... ~
II""'" c:
:::> t..,., ~
0.8
()
()
1.8
I....I1II
......... >
f-
~
c.f)
0.6
~
~
> 1.6
I...- ~ ~ ~
1.4 0.4
~I"""
1.2 0.2
II"'"
1.0 ~
o 10 20 30 40 50 0 10 20 30 40 50
SOURCE CURRENT (rnA) SINK CURRENT (rnA)
8-31
 XR-2917

TYPICAL CHARACTERISTICS

TOTAL SUPPLY CURRENT ZENER VOLTAGE VS TEMPERATURE

8 7.66
7.64 ~
.,
7
7.62 \I
~
.s 6 J ~~
I--I-- ~ 7.60
~, ~~
,."
I- I...I1II
Z
w
a:
a:
5

4 J........ j...IIII
.... II""'"
w
~
«
I-
7.58
7.56
470Q ~~ ~
:::::l
(.)
>- L....II .....
..... jIIIIII'" ....J
0
> 7.54
t.... ~r- I~
a:
~ ~II""
....J 3 860Q
Q.. w
z 7.52
IJ I~~ ~
Q..
:::::l 2 w
en N
7.50
7.48
4r~ ~ 1°1°1

~~
o 7.46
6 8 10 12 14 16 18 20 22 24 26 28 -35 -15 5 25 45 65 85
SUPPLY VOLTAGE (V) TEMPERATURE (0C)

NORMALIZED TACHOMETER OUTPUT NORMALIZED TACHOMETER OUTPUT

g VS TEMPERATURE g 1.010
VS TEMPERATURE
I- 1.010 I-
:::::l
Q..
FREQUE~CY =11000 1Hz :::::l
Q..
1.008
FREQUENCY = 200 Hz
I-
1.008 I-
:::::l :::::l
1.006 0 1.006
0
a: a:
w 1.004 w 1.004
I- I-
w w
1.002 :2: 1.002
0
~
- 0
I 1.000
..... --....
I 1.000
(.)
« ~
~ (.)
« ~~
I- 0.998 I- 0.998
0
w 0.996
1/ 0
w
N
0.996 1/
N
:::i 4 :::i <III'"
« 0.994 « 0.994
~ :2:
a: 0.992 a: 0.992
0 0
z 0.990 z 0.990
-35 -15 5 25 45 65 85 -35 -15 5 25 45 65 85

TEMPERATURE (0C) TEMPERATURE CC)

TACHOMETER CURRENTS 12 AND 13 TACHOMETER CURRENTS 12 AND 13

VS SUPPLY VOLTAGE VS TEMPERATURE
280
..ojj~
280

260 260
~ ~ r--
240
~'" 240
~
'7

~
..:;!,
220

200
~~
~
'" ~
..:;!,
..f:l
220

200
28?

• ~,..
~ .....

L.,.,I ~ V -
..f:l
0
0 z 20V ~I""'"
z 180 « 180
« ~
I....- ~ ~
_N
_N
160 160

140 140
12V
III V ~
~

6V 4 ~
120 120
6 8 10 12 14 16 18 20 22 24 26 28 -35 -15 5 25 45 65 85

SUPPLY VOLTAGE (V) TEMPERATURE (0C)

8-32
XR-2917

PRINCIPLES OF OPERATION Response Time

Figure 1 shows the typical connection for the XR-2917 as a It should be noted that the time necessary for VOUT to sta-
frequency-to-voltage/current converter. The system consists bilize to a new voltage is a function of C2, thus as C2 in-
of a tachometer section, Zener regulator, charge pump, and creases, so does the response time of VOUT-
output op amp and transistor. I nput may be differential or
ground referenced single-ended, and output current may be Zener Regulator
sourced or sunk through the output transistor.
The on-board Zener provides a stable source voltage to
When using the XR-2917 in the differential mode, inputs to the XR-2917's internal systems, so that accurate conversion
the tachometer front-end should be protected by introduc- is possible independent of substantial supply voltage varia-
ing some current limiting resistance in the input lead. tions. A drop resistor should be placed between the raw
supply and the Zener such that the current supplied to the
Timing Capacitor part is equal to the current required at the average supply
voltage. As an example, with a raw supply which varies
The timing capacitor, C1, also provides compensation for from 9 V to 15 V (an average V SUPPLY of 12 V), a cur-
the charge pump. As such, it must be larger than 100 pF rent of approximately 3.8 mA is required. This can be
to ensure accurate operation. Values of C1 smaller than accomplished usinq a drop resistor, RDROP of 470 Q.
th is can cause an error current through the current mirror Following this procedure will minimize the Zener's voltage
of the charge pump and thus through R 1. variation.

Load Resistor

There is an additional constraint placed on the load resis-

tor, R 1. Since the output voltaqe is determined at Pin 3, DESCRIPTION OF INPUTS AND OUTPUTS
then
Pin Name Description
(1)
+ TACH IN The non-inverting input to the
13 is easily determined from the relationship tachometer input comparator.

2 TIMING The timing pin for the charge

•
pump. A timing capacitor is
Combining these two results gives the simplified design required.
equation
VOUT = Vz x fin x R 1 x Cl (2)
3 LOAD The load pin where the output
Thus, R 1 must be chosen to achieve maximum VOUT for voltage is generated.
fin.
Filter Capacitor An RC combination is typically
required here.
The choice of C2 is dependent upon the ripple voltage al-
lowable at the output of the transistor emitter, Pin 4. Since 4 NON-INVERTING The non-inverting input pin of
C 1 is used to set the current through R 1, and R 1 is chosen the output op amp.
to satisfy the equation
5 EMITTER OUT The emitter of the output drive
VOUT= R1 13 (3) transistor.
MAX
6 NC No connection.
and
Vz C1 VZfinC1 7 NC No connection.
Vripple= - x - x (1- - - - )pp (4)
2 C2 13 8 COLLECTOR OUT The collector of the output
drive transistor.
Maximum Input Frequency
9 Vz The Zener regulator voltage, and
The maximum input frequency is determined once C1 has the pin through which the part is
been chosen. It is determined by the relation connected to the supply voltaqe.
12
fin = (5) 10 INVERTING The inverting input pin of the
max C1 x Vz output op amp.

8-33
 XR-2917

11 -TACH IN The inverting input to the tacho-

meter input comparator.

12 GND Ground

13 NC No connection.

14 NC No connection.

APPLICATIONS
Frequency-to-Voltage Convertor

The basic frequency-to-voltage function of the XR-2917 is

illustrated in Figure 2. An input frequency is applied to Pin
1.

Figure 3. VOUT vs. Vr

Vee
A tachometer can be realized by providing the input fre-
quency via a variab~e reluctance ma~netic pick-up. The
maximum output voltage and input frequency, and the
output ripple voltaqe may be determined from equations
3 and 5, and equation 4 respectively.

Metering of the output can be performed by sensing current

through a current meter in series with the output transistor
co IIector or by tak ing the vo Itage off of the em itter.

Separation of the input comparator's inverting input from

VOUI
100k ground allows the desiqner to connect a diode to ground to
protect the input from transients.

Figure 2. Frequency-to-Voltage Converter The availability of the output op amp input pins further
provides the designer with the opportunity to filter the
siqnal and reduce output ripple.

The maximum output voltage is

Speed Switch

Some applications may require a method of determing an

VOUT = R1 13 = (10K)(170JIA) = 1.7V
MAX overspeed condition for switching purposes. Figure 4 illu-
strates the basic speed switch confiquration. The two 5K
where 13 = 170 JIA if VCC = 12 V, and ohm resistors from pin 9 to 10 and pin 10 to 11/12 bias
170JIA the output amplifier a % VZ. When the voltage at pin 4
12
fin = - - 1.12 KHz is greater than % VZ, the output of the amplifier will go
max C1 xVZ (0.02JIF)x(7.6 V) high and switch the output transistor into saturation.
Once in saturation, current will flow throuqh the load. The
The ripple volta~e is given by output transistor is the "switch."
Vz C1 VZ f in C 1
Vr =- x - x (1----)pp
Z C2 13

or

Vr = [0.076 x (1 - fin x 0.0009) 1pp

Figure 3 shows the relationship of both VOUT and Vr to

fin. VOUT and Vr are not of the same scale.
8-34
XR-2917

vee Since the XR-2917 draws approximately 5 mA as biased

with the 470 ohm resistor, and the output transistor can
sink about 40 mA. then 0.7V
Rsense= (40+5)mA "'16Q

A % watt resistor will suffice, while the transistor should

be chosen to pass the required load current. The collector
of the output transistor shou Id be connected between the
470 ohm resistor and Rsense. The trip voltage is a function
of Vz and is set as before.

An overspeed latch can be realized using a configuration

similar to that of Figure 4. The latch requires that the
load be voltage controlled, thus be connected between
the emitter of the output transistor and ground. Pins 3,
4, and 5 shou Id be tied together thus creating a positive
feedback situation which pulls the output, non-invertin~
input, and load voltages up to the maximum output
voltage of the part: this voltage is a function of output
transistor current (see Typical Performance Character-
LOAD ON WHEN istics). The output of the overspeed latch appears in
1 Figure 6.
FIN> 2RC 2

Figure 4. Basic Speed Switch Configuration

V OUT

From equation 2, it can be shown that the output transistor

will switch off when the input frequency (fin) ooes below
(2 RC2)-1. This confiouration. can be adiusted to trip
the switch at any fractional frequency of (RC2)-1 by
adjusting the voltage divider which is between pins 9 and
10, and pins 10 and 11/12. As an example, to trigger at

•
(3 RC2)-'I, place at 5K ohm resistor between pins 10 and
11/12, and a 10K ohm resistor between pins 9 and 10.

A remote speed switch can be implemented by placing a

current sensing resistor between the base and emitter of a
transistor. The resistor will be in series with the supply
line to the XR-29'7~ and the load to be switched will be
in series with this switch transistor's collector and the
RESET IS PERFORMED BY REMOVING Vee
supply voltage. When the voltage drop across the resistor
equals 700 mV, the transistor will turn on and pull current Figure 6. VOUT VS. fn"
through the load (see Figure 5).

VSUPPLY

The trip frequency is set as before, If R l' is the resistor

between pins 9 and 10, and R2 is the resistor between pins
10 and 11/12, then
R2
flatch = ( - - - ) (RC)-1
RSENSE R1 + R2

A variation of the overspeed latch is the overspeed ind i-

cator of Figure 7. In this case

68 + 150
Vee (TO XR-4917) ftrigger =[ ( ) (14n.56) 1 [(100K)(.033J,L) ]-1
68 + 150 + IK
Figure 5. Remote Speed Switch and the trigger frequency can be adjusted at Rand C2
or by using the voltage divider.
8-35
 XR-2917

14V

Hysteresis
470

Figure 9 illustrates one method of providing hysteresis.

68
The magnitude of hysteresis is given by
2K
(2K + 195K) VREF
150

or

VHYSTERESIS = 0.01 VREF

12V

FLASHING BEGINS AT fiN;' 100 Hz AND

INCREASES WITH FREQUENCY INCREASES.

Figure 7. Overspeed Indicator

When the voltage at pin 4 exceeds that set by the divider

off pin 10, the LED turns on. The transistor whose base
is connected to the anode of the LED will turn on and
discharge the capacitor at pin 4 and turn off the LED.
VREF

A delay switch can be implemented by removing resistor Figure 9. Hysteresis

R from pins 3/4 inFigure 4. Choosing C2 such that Shifting Response of Output Voltage

,:igure 10 illustrates a simple method of shifting the output

voltage up by a constant value, VSH I FT. The output vol-
Current w.ill not flow through the load until n consecutive tage for this circuit is given by
input cycles have occured.
VOUT = (Vz x fin x Rl x Cl) + VSHIFT
Capacitance Meter

Figure 8 is a capacitance meter. The ranqe of the meter

can be adjusted by adjusting R 1 in the equation

Cx = (2.2 x 10-3 ) (V-OUT/Rl)

Vee

470

110V. c ~047.'F
60 Hz

50k
OOOLF J lOOk
10k Your

200
CXI"'k +
5k -= IRII 10K VOUT
FOR eX - 2.2JtF to O.22JtF
VOUT-l TO 10V
R,-'00KO
Figure 10. Shifting Output Voltage
Figure 8. Capacitance Meter
8-36
XR-2917

A method of delaying the output response to the input

frequency is shown in Figure 11. There will be no change in
the output voltage until

At this point, equation 2 is valid .. Using the voltage divider

between pins 8 and 5, and 5 and ground, one may change
the level at which the output voltage will begin to react.
Vee
91Kn
SHIFTING VOUT RESPONSE TO fiN BY
CLAMPING VOUTMIN

VOUT

Figure 11. Delaying VOUT Response to fin

This circuit will not react until

•
VCC
fin = {--I (VZ x R1 x C1)-1
10

8-37
 XR-4151

Voltage-to- Frequency Converter

GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-4151 is a device designed to provide a simple,
low-cost method for converting a DC voltage into a pro-
portional pulse repetition frequency. It is also capable
of converting an input frequency into a proportional
CURRENT
output voltage. The XR-4151 is useful in a wide range of SOURCE OUTPuT
applications including AID and D/A conversion and da-
ta transmission.

FEATURES
Single Supply Operation (+ 8V to + 22V)
Pulse Output Compatible With All Logic Forms
Programmable Scale Factor (K)
Linearity ± 0.05 % Typical-Precision Mode
Temperature Stability ± 100% ppm/DC Typical
High Noise Rejection
Inherent Monotonicity
Easily Transmittable Output
Simple Full Scale Trim
Single-Ended Input, Referenced to Ground
Also Provides Frequency-to-Voltage Conversion
Direct Replacement for RC/RV/RM-4151 ORDERING INFORMATION
Part Number Package Operating Temperature
XR-4151P Plastic - 40 D C to + 85 D C
XR-4151CP Plastic ODC to + 70 DC

APPLICATIONS
Voltage-to-Frequency Conversion
AID and D/A Conversion
Data Transmission
Frequency-to-Voltage Conversion
Transducer Interface
System Isolation
SYSTEM DESCRIPTION
The XR-4151 is a precision voltage to frequency con-
vertor featuring 0.05 % conversion linearity, high noise
rejection, monotonicity, and single supply operation
from 8V to 22V. An RC network on Pin 5 sets the maxi-
ABSOLUTE MAXIMUM RATINGS mum full scale frequency. Input voltage on Pin 7 is
compared with the voltage on Pin 6 (which is generally
Power Supply 22V controlled by the current source output, Pin 1). Fre-
Output Sink Current 20 mA quency output is proportioned to the voltage on Pin 7.
Internal Power Dissipation 500mW The current source is controlled by the resistance on
Input Voltage - 0.2V to + VCC Pin 2 (nominally 14kO) with I = 1.9 VIR. The output
Output Short Circuit to Ground Continuous is an open collector at Pin 3.

8-38
ELECTRICAL CHARACTERISTICS
XR·4151
Test Conditions: (VCC = 15V, TA = + 25°C, unless otherwise specified)

LIMITS
PARAMETERS MIN TYP MAX UNITS CONDITIONS
Supply Current 2.0 3.5 6.0 mA 8V<VCC<15V
2.0 4.5 7.5 mA 15V<VCC<22V
Conversion Accuracy
Scale Factor 0.90 1.00 1.10 kHzlV Circuit of Figure 3, VI =
10V RS = 14. Ok
Drift with Temperature - ± 100 - ppm/oC Circuit of Figure 3, VI =
10V
Drift with VCC - 0.2 1.0 %IV Circuit Figure 3, VI = 1.0V
8V< VCC< 18V
Input Comparator
Offset Voltage - 5 10 mV
Offset Current - ±50 ±100 nA
Input Bias Current - -100 -300 nA
Common Mode Range
(Note 1) 0 o to VCC-2 VCC-3.0 V
One-Shot
Threshold Voltage, Pin 5 0.63 .667 0.70 x VCC
Input Bias Current, Pin 5 - -100 -500 nA
Reset VSAT - 0.15 0.50 V Pin 5, 1 = 2.2mA
Current Source
Output Current - 138.7 - p.A Pin 1, V = 0, RS = 14.0kO
Change with Voltage - 1.0 2.5 p.A Pin 1, V = OV to V = 10V
Off Leakage - 1 50.0 nA Pin 1, V = OV
Reference Voltage 1.70 1.9 2.08 V Pin 2
Logic Output
VSAT - 0.15 0.50 V Pin 3, 1 = 3.0mA
VSAT - 0.10 0.30 V Pin 3, 1 = 2.0mA
Off Leakage - .1 1.0 p.A

•
Note 1: Input Common Mode Range includes ground.

PRINCIPLES OF OPERATION charge, Q, into the RB-CB network. This process con-
tinues until VB > VI. When this condition is achieved,
SINGLE SUPPLY MODE VOLTAGE-TO-FREQUENCY CONVERTER the current source remains off and the voltage VB de-
cays until VB is again equal to VI. This completes one
In this application, the XR-4151 functions as a stand- cycle. The VFC will now run in a steady state mode. The
alone voltage-to-frequency converter operating on a current source dumps lumps of charge into the capaci-
single positive power supply. Refer to the functional tor CB at a rate fast enough to keep VB ~ VI. Since the
block diagram and Figure 3, the circuit connection for discharge rate of capacitor CB is proportional to VBI
single supply voltage-to-frequency conversion. The XR- RB, the frequency at which the system runs will be pro-
4151 contains a voltage comparator, a one-shot, and a portional to the input voltage.
precision switched current source. The voltage com-
parator compares a positive input voltage applied at pin AI
l00KII
7 to the voltage at pin 6. If the input voltage is higher,
the comparator will fire the one-shot. The output of the
one-shot is connected to both the logic output and the
precision switched current source. During the one-shot
period, T. the logic output will go low and the current
source will turn on with current I. At the end of the one
shot period the logic output will go high and the current
source will shut off. At this time the current source has
injected an amount of charge Q = lOT into the network
RB-CB' If this charge has not increased the voltage VB 'oLJLJ
,--l r ::"oCo ~
such that VB > VI, the comparator again fires the one- '0· KV,. WHERE 1(00._

shot and the current source injects another lump of Figure 3. VOltage-to-Frequency Converter

8-39
XR·4151
TYPICAL APPLICATIONS
op-amp prevents the voltage at pin 7 of the XR-4151
from going below O. Use a low-leakage diode here,
since any leakage will degrade the accuracy. This cir-
SINGLE SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER
cuit can be operated from a single positive supply if an
Figure 3 shows the simplest type of VFC that can be XR-3403 ground-sensing op-amp is used for the integra-
made with the XR-4151. The input voltage range is from tor. In this case, the diode can be left out. Note that
a to + 10V, and the output frequency is from a to 10 even though the circuit itself will operate from a single
kHz. The full scale frequency can be tuned by adjusting supply, the input voltage is necessarily negative. For
RS, the output current set resistor. This circuit. has the operation above 10kHz, bypass pin 6 of the XR-4151
advantage of being simple and low in cost, but It suff~rs with .01p.F.
from inaccuracy due to a number of error sources. Lin- FREQUENCY-TO-VOLTAGE CONVERSION
earity error is typically 1 %. A frequency offset will also
be introduced by the input comparator offset voltage. The XR-4151 can be used as a frequency-to-voltage
Also, response time for this circuit is limited by the pas- converter. Figure 5 shows the single-supply FVC config-
sive integration network RB CB. For the component val- uration. With no Signal applied, the resistor bias net-
ues shown in Figure 3, response time for a step change works tied to pins 6 and 7 hold the input comparator in
input from a to + 1OV will be 135 msec. For applications the off state. A negative going pulse applied to pin 6 (or
which require fast response time and high accuracy, positive pulse to pin 7) will cause the comparator to fire
use the circuit of Figure 4. the one-shot. For proper operation, the pulse width
must be less than the period of the one-shot, T == 1.1
PRECISION VOLTAGE-TO-FREQUENCY CONVERTER RO CO· For a 5V pop square-wave input the differentia-
tor network formed by the input coupling capacitor and
In this application (Figure 4) the XR-4151 is used with
the resistor bias network will provide pulses which cor-
an operational amplifier integrator to provide typical lin-
rectly trigger the one-shot. An external voltage compar-
a
earity of 0.05 % over the range of to - 10V. Offset is
ator can be used to "square-up" sinusoidal input sig-
adjustable to zero. Unlike many VF.C de~igns. whi?h nals before they are applied to the XR-4151. Also, the
lose linearity below 10mV, this cirCUIt retaIns lInearity
component values for the input signal differentiator and
over the full range of input voltage, all the way to OV.
bias network can be altered to accommodate square
waves with different amplitudes and frequencies. The
Trim the full scale adjust pot at VI == -1 OV for an output
passive integrator network RB CB filters the current
frequency of 10kHz. The offset adjust pot should be set
pulses from the pin 1 output. For less output ripple, in-
for 10Hz with an input voltage of - 10mV.
crease the value of CB.
The operational amplifier integrator improves linearity
For increased accuracy and linearity, use an operation-
of this circuit over that of Figure 3 by holding the output
al amplifier integrator as shown in Figure 6, the preci-
of the source, Pin 1, at a constant Ov. Therefore, the lin-
earity error due to the c'urrent source output conduc- sion FVC configuration. Trim the offset to give -10mV
out with 10Hz in and trim the full scale adjust for - 10V
tance is eliminated. The diode connected around the
out with 10kHz in. Input signal conditioning for this cir-
cuit is necessary just as for the single supply mode and
the scale factor can be programmed by the choice of
component values. A tradeoff exists between the
amount of output ripple and the response time, through
the choice or integration capacitor CI. If CI == 0.1 p.f the
ripple will be about 100mV. Response time constant TR
== RB CI· For RB == 100 kn and CI == 0.1 p.f, TR
10msec.
Vo VOLTAGE OUT~T
FREOUENCY INPUT
TO lOV
--u-L.rL
5 V p.p SOUAREWAVE

I,
1.022.<F

lOKI!

5.IKII

ROI.'KI!

tDKu 10Ku

Figure 4. Precision Voltage-to-Frequency Converter Figure 5. Frequency-to-Voltage Converter

8-40
 PRECAUTIONS
XR·4151
2. Set T = 1.1 ROCO = 0.75[1/fo] where fo is the de-
sired full scale frequency. For optimum performance
1. The voltage applied to comparator input pins 6 and 7 make 6.8kO >RO >680kO and 0.001p.f <CO
should not be allowed to go below ground by more < 1.0p.f.
than 0.3 volt.
3. a) For the circuit of Figure 3 make CB = 10 - 2
2. Pins 3 and 5 are open-collector outputs. Shorts be- [1/fo] Farads.
tween these pins and + VCC can cause overheating
and eventual destruction. Smaller values of CB will give a faster response
time, but will also increase the frequency offset
3. Reference voltage terminal pin 2 is connected to the and nonlinearity.
emitter of an NPN transistor and is held at approxi-
mately 1.9 volts. This terminal should be protected b) For the active integrator circuit make
from accidental shorts to ground or supply voltages.
Permanent damage may occur if the current in pin 2 CI = 5 x 10- 5 [1/fo] Farads.
exceeds 5mA.
The op-amp integrator must have a slew rate of at
4. Avoid stray coupling between pins 5 and 7; it could least 135 x 10- 6 [1/C1] volts per second where
cause false triggering. For the circuit of Figure 3, by- the value of C1 is in Farads.
pass pin 7 to ground with at least 0.01p.f. This is nec-
essary for operation above 10kHz. 4. a) For the circuit of Figure 4 keep the values of RB
and RB as shown and use an input attenuator to
give the desired full scale input voltage. /

b) For the precision mode circuit of Figure 4, set RB

= V10/100p.A where VIO is the full scale input
RB lOOK ..
voltage.
5001
Alternately, the op-amp inverting input (summing
Vo node) can be used as a current input with the full
>-,-4---AN'v---+--<I VOLTAGE OUTPUT
lOOU -IOV. Vo' 0 scale input current 110 = - 100p.A.

RIB 25Ku
\1- V+ 5. For the FVC's, pick the value of CB or CI to give the
~
100KlI optimum tradeoff between the response time and
output ripple for the particular application.

DESIGN EXAMPLE

I. Design a precision VFC (from Figure 5) with fa

100kHz and VIO = - 10V.

1. Set RS

2. T
= 14.0kO

= 0.75 [1/10 5] = 7.5p.sec

II
Let RO = 6.8kO and Co = 0.001 p.f.
3. CI = 5 x 10 5 [1/10 5] = 500pf.
Figure 6. Precision Frequency-to-Voltage Converter Op-amp slew rate must be at least

SR = 135 x 106 [1/500pf] = O.27V/p.sec

4. RS = 10V/100p.A = 100kO.
PROGRAMMING THE XR-4151 II. Design a precision VFC with fa = 1Hz and VIO =
10V.
The XR-4151 can be programmed to operate with a full
scale frequency anywhere from 1.0Hz to 100kHz. In the 1. Let RS = 14.0kQ
case of the VFC configuration, nearly any full scale in-
put voltage from 1.0V and up can be tolerated if proper 2. T = 0.75 [1/1] = 0.75 sec
scaling is employed. Here is how to determine compo-
nent values for any desired full scale frequency. Let RO = 680kO and Co = 1.0p.f.

1. Set RS = 14kO or use a 12k resistor and 5k pot as 3. CI =5 x 10- 5 [1/1]F = 50p.f.
shown in the figures. (The only exception to this is
Figure 4.) 4. RS = 100kQ.

8-41
XR·4151
III. Design a single supply FVC to operate with a supply 4. RS = 5V/100lo'A = 50kU.
voltage of 9V and full scale input frequency fo ==
83.3 Hz. The output voltage must reach at least 5. Output response time constant is TR :s 200
0.63 of its final value in 200msec. Determine the msec
output ripple. Therefore-

1. Set RS == 14.0kO Cs :S TR/RB = (200 x 10 - 3)/(50 x 103) = 41o'f

2. T == 0.75 [1/83.3] == 9msec Worst case ripple voltage is

Let RO == 82kO and Co = 0.1 Io'f. VR = (9mS x 1351o'A) I 41o'f = 304mY.

3. Since this FYC must operate from 8.0Y, we shall
make the full scale output voltage at pin 6 equal
to 5.0V.

EQUIVALENT SCHEMATIC DIAGRAM

8-42
 XR-9201

8-Bit Microprocessor Compatible

DigitalaTo-Analog Converter
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-9201 is a monolithic 8-Bit ",p compatible digital-
to-analog converter with differential current outputs. It
contains an internal data latch, making it suitable for in-
~Vee +Vee
terfacing with microprocessors. The chip contains a
stable voltage reference (2.0 V Nominal) which is exter-
V~H DB7
nally adjustable and can be used as a reference for oth-
er D/A and AID converters.
TRIM DB6

The XR-9201 features non-linearity of ± V2 LSB maxi-

mum (± .19% of full scale current). The internal volt- -VR" IN DBS

age reference maintains a temperature coefficient of

SO ppm/oC. .VR" IN DB4

10 DB3

10 DB2

FEATURES
CE DBI
8-Bit Resolution
Input Data Latches GROUND DBO
Internal Voltage Reference
Microprocessor Compatible
Non Linearity ± V2 LSB Maximum
Fu" Scale Current Stability ±SO ppm/oC
Reference Voltage Stability ±SO ppm/oC ORDERING INFORMATION

•
Differential Current Outputs
TIL Compatible Part Number Package Operating Temperature
XR-9201 CP Plastic 0° to + 70°C
SYSTEM DESCRIPTION
APPLICATIONS To convert the output currents of the digital-to-analog
converter to a voltage, an operational amplifier can be
Bipolar and UnipOlar D/A Conversion used as shown in Figure 12.
AID Conversion
Test Equipment Care must be taken in selecting an operational amplifi-
Measuring Instruments er to be used in D/A conversion. For accurate conver-
Programmable Current Source sion, the operational amplifier should have low input
Programmable Voltage Source offset voltage, low input bias and offset currents, and
fast settling times. Input offset voltage contributes a
DC error on the output and should be properly nulled.
Input bias current contributes to the D/A converter cur-
ABSOLUTE MAXIMUM RATINGS rent flowing through the feedback resistor, RFB, and al-
so causes a DC error on the output voltage. This error
+ VCC Positive Supply Voltage +6V can be reduced by the addition of a resistor equal in
- VCC Negative Supply Voltage -8.SV value to RFB from the noninverting input to ground.
Logic Input Voltages o to +6V Settling time is important because it rules how fast the
Power Dissipation SOO mW output reaches its prescribed voltage level. The OP-01
Derate Above 2SoC S mW/oC is suitable for D/A converter applications producing
Storage Temperature - SSoC to + 1S0°C negligible errors.

8-43
ELECTRICAL CHARACTERISTICS
XR·9201
Test Conditions: VCC = +5V, - VCC = -7V, TA = 25°C, IREF = 1.0 mA, unless otherwise specified.

SYMBOL PARAMETERS MIN TYP MAX UNIT CONDITIONS

Resolution 8 8 8 Bits
Monotonicity .8 8 8 Bits
Non-linearity ±0.5 LSB
±O,19 %IFS
+VCC Positive Supply 4,5 5,0 5,5 V
Voltage
-VCC Negative Supply -7,7 -7,0 -6,3 V
Voltage
VIH Data Input and Chip Enable 2,0 V
"High" Voltage
VIL Data Input and Chip Enable 0,8 V
"Low" Voltage
IIH Data Input and Chip Enable 500 /-LA
"High" Current
IlL Data Input and Chip Enable ±20 /-LA
"Low" Current
IFS Full Scale Output Current 1,914 1,992 2,070 mA IREF = 1,000 mA
IZO Zero Scale Output Current ±10 /-LA
TCIFS Full Scale Current ±50 ppm/oC O°C ::s; TA ::s; 75°C
Temperature Sensitivity
IFSS Full Scale Symmetry ±10 /-LA
VREF Internal Reference Voltage 2,005 V RADJ = 50 Kn
1,990 RADJ =0n
2,000 RADJ =6n
TCREF VREF Temperature Stability ±50 ppm/oC VREF = 2,00 V
+ICC Positive Supply Current 15 25 mA
-ICC Negative Supply Current -25 -15 mA
Positive Output +5,0 V
Voltage Compliance
Negative Output -1,0 V
Voltage Compliance
Maximum Full Scale 3 mA
Current
ts Settling Time 600 nsec
tsu Data Set-up Time 170 nsec
tH Data Hold Time 40 nsec
tw Minimum Chip Enable (CE) 170 nsec
Pulse Width
tD Propagation Delay Time 500 nsec

8-44
XR·9201

I
I
+VREF IN ------+-c--..
5 ....... I
I
I
I
-VREFIN • 1---1------4 I

i
I
I

:
___________________________________________________ .JI
:

Figure 2. Functional Block Diagram

85 81 eo CE

Figure 3A. Equivalent Circuit of Data Latches and Current Switches

8-45
3 TRIM
XR·9201
2 VREF 4 -VREF IN

+VREF IN

L-----~----~--~~--_+----~-VCC

XR·9201

Figure 3B. Equivalent Circuit of Voltage Reference and Input Amplifier

2.0 I------..... ~-.r"-"'" RTRIM. 6 Kil

-Vee. -7.0 V

°0~~--~--~6--~8~~10~~12--~1~.~~1~6~~18~-2~0-'
CURRENT OUT ON VREF (PIN 2) mA

Figure 5. VREF vs. Current Output

RTRIM =6 KII
-Vee = -7.0 V

(STAYS IN ORIGINAL STATE)

OUTPUT

+Vee (VOLTS)
Figure 4. Timing Diagram Figure 6. VREF vs. + VCC

8-46
 XR·9201
DEFINITIONS OF SWITCHING PARAMETERS

Settling Time (t s): Time required for output to reach to when CE goes "low", and still
its final value (to within ± .19% of obtain valid output data of the pre-
full scale output) after data is ap- vious input state. Data hold time
plied to the inputs. Chip enable, indicates that the input data does
CE, is held "high." not have to be present during the
latter part of the CE high state, and
still have valid output data.
Data Set-Up Time (tsu ): Minimum time required for
data to be present at the inputs
while CE is "high", in order to ob- Chip Enable Pulse Width (tw): Minimum pulse width
tain valid output data. It is mea- required for chip enable signal in
sured from when proper data is order to obtain valid output data.
applied to the inputs to when CE
goes "low".
Propagation Delay Time (td): Time required for output
to reach its final value (50 %) after
Data tlole Time (th): Maximum time required for data to CE is applied. It is measured from
be present at the inputs before CE the falling edge of the CE pulse to
goes "low", in order to obtain valid 50% of the output pulse under
output data. It is measured from minimum data set-up time condi-
when the input data changes state tions.

DESCRIPTION OF PIN CONTROLS

VREF (PIN 2): Internal voltage reference output pro- the D/A converter. Either the internal
vides + 2.00 V Nominal voltage. Can VREF (Pin 2) or an external VREF can
be used as reference voltage for oth- be connected to this pin. IREF is ap-
er circuitry. Maximum output current proximately equal to VREF/R. Maxi-
cCfability is approximately 9 mA with mum value for IREF is about 1.5 mA
V = 5.0 V. before internal saturation occurs.

TRIM (PIN 3): VREF can be adjusted by connecting To (PIN 6): Complement output current.
a 10 KO potentiometer between the
trim pin and ground. Temperature sta- 10 (PIN 7): Output current. The sum of To and 10

•
bility is optimized for VREF = 2.00 V is always equal to the full scale output
to 10-50 ppm/DC. current (IFS)'

- VREF IN (PIN 4): This pin is tied to ground through CE (PIN 8): Chip enable pin controls the input da-
a resistor, R, equal in value to that of ta into the internal data latch. The
Pin 5 and VREF latch is transparent in the "high"
state.
+ VREF IN (PIN 5): Reference voltage is connected
to this pin using a resistor, R, to pro- DBO-DB7 (PIN 10-17): Data input pins. DBO corre-
vide the reference current, IREF> for sponds to the LSB. DB7 corresponds
to the MSB.

2.000

+VCC z 5.0 V
~ 2.010 +VCC = 5.0 V -Vee = -7.0 V
o -Vcc = -7.0 V IREF = 1.000 mA
~
... RTRIM = 6 KII
~ 2.000
>

1.990

1.996_'-25--......---....25----'50~-7':-5--,...Loo----­
-25C O'C 25°C 50'C 75°C
AMBIENT TEMPERATURE ('C) AMBIENT TEMPERATURE rC)

Figure 7. VREF VS. Temperature Figure 8. IFS VS. Temperature

8-47
PRINCIPLES OF OPERATION
XR·9201
Figure 10 shows the basic configuration of the XR-9201
D/A converter. The input data bits to the chip can be
latched (stored) in the D/A by controlling the chip en-
able (CE) pin. When CE is "high" (>2.0 volts), the latch 1.0

is transparent and data bits present are passed

through the latch and directly control the D/A converter
switches. When CE is "low" « 0.8 volts), the data bits
within the latch are retained and remain there until CE +Vcc = 5.0 V
goes "high" again. When CE is "low", the data bits at 0.1
-vcc = -7.0 V
the inputs are ignored until CE goes "high". This inter-
val latch provides a useful interface with microproces-
sors.

The output currents, 10 and To, are related to IREF as 0,01 L......L==--...L....--'-_ _ _ _...I....-_ _ _--L._ _ _~
follows: 0.001 0.01 0.10 1.00
IREF (mA)
b7 b6 b5 b4 b3 b2 b1 bO ] Figure 9. IFS vs. IREF
10 = 21REF - + - + - + - + - + - + - +-
[ 2 4 8 16 32 64 128 256
CE 8·BIT DATA +5 V
Where: b n = 1 if Bit N is "High"
= 0 if Bit N is "Low"
b7 = MSB (Pin 17)
bO = LSB (Pin 10)
" - - - - - - 0 10
To is the complement current output of 10 , For all possi-
ble input data combinations,
IREF 1
10 + To = IFS = full scale output current. "'------0 10

where IFS = 2 IREF (~;~) 10 KII

The XR-9201 D/A converter contains an internal refer- -7V ~

ence voltage (VREF) with nominal value of 2.00V using Figure 10. Basic Configuration
a 6 KO resistor to ground. VREF can be adjusted using
a 10 KG potentiometer tied between Pin 3 and ground. board layout. Specifically, connilction between the cur-
For maximum temperature stability, VREF should be rent output terminals, 10 and 10 , and the operational
set to 2.00V. The maximum output current capability of amplifier inputs needs to be as short as possible so as
VREF is about 9 mA (see Figure 5) and can be used to to minimize capacitance at the node. Oscillations on
provide a reference voltage for other DACs, as well as the operational amplifier output may result with long
other circuitry. wires. A capacitor in the feedback loop of the opera-
tional amplifier can reduce these oscillations.
The reference current (lREF) for the D/A converter is
established by a resistor, R, connected between VREF ZERO AND FULL SCALE ADJUSTMENTS
and Pin 5 (+ VREF IN), or between an external refer-
ence source and Pin 5, and is approximately given as: Figure 13 shows a circuit for zero and full scale adjust-
ments. It allows the output voltage to be nulled with
VREF zero scale input conditions (0000,0000). This is done by
IREF = - -
R shorting out RFB and adjusting the vas adjust potenti-
ometer of the operational amplifier until the output
For IREF ::::; 1 mA. The maximum IREF allowed is about reads zero volts. This is performed with all digital bits
1.5 mA beyond which saturation occurs in the internal set to zeros. If To is the output being used, then all digi-
circuitry. To balance the internal operational amplifier, a tal bits are set to ones and the zero scale is adjusted.
resistor equal to R must be placed betvv'esn Pin 4
(- VREF IN) and ground. For full scale adjustment, all digital inputs are set to
ones and the IREF potentiometer, from Pin 2 to Pin 5, is
NOTE: adjusted until the output is at the desired voltage level
When operating the XR-9201 D/A converter with an op- (e.g., output is adjusted to 10.000 volts for nominal
erational amplifier, care must be taken with the PC 9.960 volts output).

8-48
XR·9201
+5 V

16 4 (MSB) ~ RF
SN 5 6 7 8
11 74193
CF
15
OP.Ql
':"
10 4·BIT
9 COUNTER 7

LSB

CE lOUT'
MSB +VCC 10 K
':"
-15 V

5 KI! 10 KII -VCC Vo = RF (IERROR)

RF = 10 KII
CF = .01 I'F

Figure 11. Relative Accuracy Test Circuit

II-BIT DATA

IREF
1 rnA
=1 EO

3 KII
FULL
SCALE
ADJUST
2 VREF

XR·9201
10

ZERO
SCALE
EO
•
o V' EO' 10 V FOR RFB = 5 KII. IREF = 1 rnA
-VCC ADJUST
IFS = 2(IREF) (2551256)

FOR OPERATION WITH NEGATIVE LOGIC D/A CONVERSION. I.E. ZERO FULL SCALE
(0000 0000) CORRESPONDING TO FULL SCALE OUTPUT. CONNECT THE INVERTING Figure 13. Full Scale and Zero Scale Adjustment
INPUT OF OP AMP TO 10 (PIN 6) AND CONNECT 10 (PIN 7) TO GROUND.

Figure 12. Digital-to-Analog Conversion: Unipolar Operation

Table 1. Unipolar Operation - Input/Output Relationship

B7 B6 B5 B4 B3 B2 B1 BO 10 (rnA) EO (V)
Positive Full Scale 1 1 1 1 1 1 1 1 1.992 9.960
Pas. Full Scale - LSB 1 1 1 1 1 1 1 0 1.984 9.922
Pas. Full Scale - MSB 0 1 1 1 1 1 1 1 0.992 4.961
Zero Full Scale + LSB 0 0 0 0 0 0 0 1 0.008 0.039

8-49
 Table 2. Bipolar Operation: Input/Output Relationship
XR·9201
B7 B6 B5 B4 B3 B2 B1 BO E1 (V) EO (V)
Full Scale Output 1 1 1 1 1 1 1 1 0.000 10.00
Full Scale - LSB 1 1 1 1 1 1 1 0 0.016 9.921
Zero Scale + MSB 1 0 0 0 0 0 0 0 1.984 0.078
Full Scale - MSB 0 1 1 1 1 1 1 1 2.000 0.000
Zero Scale + LSB 0 0 0 0 0 0 0 1 3.968 -9.844
Zero Scale 0 0 0 0 0 0 0 0 3.984 -9.922

.001 "F
BIPOLAR OUTPUT OPERATION
Figure 14 shows a basic bipolar output operation. For
~
full scale input (1111,1111) the output voltage is equal
to 1.0V. For zero scale input (0000,0000), output voltage
is equal to - 1.0V. Due to the internal circuitry of the
XR-9201, the current output terminals should not be
pulled below approximately - 1.0 volt. Therefore the cir·
cuit shown in Figure 14 would not function for Eo less
than - 1.0V. For bipolar operation with larger output
voltages, the circuit shown in Figure 15 is ~ecom·
mended. Note that the current outputs, 10 and 10 , are
held at zero volts for all digital inputs for greater accu-
racy.

RO = 17.S KII
ADJUST RO FOR -VOUT = -7 V
=
RA so KII
ADJUST RA FOR +VOUT = +5 V

Figure 15. Digital-to-Analog Conversion - Bipolar Operation

8·BIT DATA

8·BIT DATA

VREF

IREF =
0.5 rnA
1 EO
---
I rnA ~~---------'
IREF

-1.0 V' EO' 1.0 V

IE: 2(IREF) (RF)' 1.0 VOLT

- I

Figure 14. Digital-to-Analog Conversion - Bipolar Operation Eo =,* ( VREF - El )

VREF = 2 V. R = 2 K. RFB = 2 K. R2 = 50 K. Rl = 10 K

NOTE: (I + IRE F) MUST BE LESS THAN 6 rnA FOR PROPER OPERATION.

Figure 16. Regulated Supplies for XR-9201

8-50
 ~EXAR XR-13600
Dual Operational Transconductance
Amplifier
GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
The XR-13600 is a dual operational transconductance
(Norton) amplifier with predistortion diodes and non-
committed Darlington buffer outputs. BIAS BIAS
A B
The device is especially suitable for electronically con- DIODE DIODE
trollable gain amplifiers, controlled frequency filters, an BIAS BIAS
other applications requiring current or voltage adjust-
INPUT INPUT
ments. (+1
(+1

INPUT INPUT
H I -I

OUTPUT
FEATURES OUTPUT

Direct Replacement for LM-13600 and LM-13600 A

Transconductance Adjustable Over 4 Decades
Excellent Transconductance-Control Linearity BUFFER BUFFER
Uncommitted Darlington Output Buffers INPUT INPUT
On-Chip Predistortion Diodes
Excellent Matching Between Amplifiers BUFFER BUFFER
OUTPUT OUTPUT
Wide Supply Range: ± 2V to ± 18V

•
APPLICATIONS
Cu rrent-Controlled Amplifiers
Current-Controlled Impedances
Current-Controlled Filters
ORDERING INFORMATION
Current-Controlled Oscillators Part Number Package Operating Temperature
Multipliers/Attenuators
Sample and Hold Circuits XR-13600AP Plastic O°C to + 70°C
Electronic Music Synthesis XR-13600CP Plastic O°C to + 70°C

SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
The XR-13600 consists of two programmable transcon-
Supply Voltage (See Note 1) ±22 V ductance amplifiers with high input impedance and
Power Dissipation (TA = 25°C, see Note 2) 625 mW push-pull outputs. The two amplifiers share common
Derate Above 25°C 5 mW/oC supplies but otherwise operate independently. Each
DC Input Voltage +VCC to -VEE amplifier's transconductance is directly proportional to
Differential Input Voltage ±5 V its applied bias current. To improve signal-to-noise per-
Diode Bias Current (lD) 2 mA formance, predistortion diodes are included on the in-
Amplifier Bias Current (IB) 2 mA puts; the use of these diodes results in a 10 dB im-
Output Short Circuit Duration Indefinite provement referenced to 0.5% THD. Independent
Buffer Output Current (Note 3) 20 mA Darlington emitter followers are included to buffer the
Storage Temperature Range -65°C to + 150°C outputs.

8-51
 XR·13600
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, Supply Voltage = ± 15V, unless otherwise specified.
XR-13600A XR-13600C

PARAMETERS MIN TYP MAX MIN TYP MAX UNITS CONDITIONS

Input Offset Voltage (VOS) 0.4 2 0.4 5 mV
5 mV Over Temperature Range
0.3 2 0.3 5 mV IS = 5/LA
VOS Including Diodes 0.5 2 0.5 5 mV Diode Bias Current (I D) = 500 /LA
Input Offset Change 0.1 3 0.1 mV 5/LA :5IS:5500/LA
Input Offset Current 0.1 0.6 0.1 0.6 /LA
Input Sias Current 0.4 5 0.4 5 /LA TA = 25°C
1 7 1 8 /LA Over Temperature Range
Forward Transconductance
(9m) 7700 9600 12000 6700 9600 13000 /Lmho TA = 25°C
4000 5400 /L mho Over Temperature Range
gm Tracking 0.3 0.3 dS
Peak Output Current 3 5 7 5 p.A RL = 0, IS = 5/LA
350 500 650 350 500 650 p.A RL = 0, IS = 500/LA
300 300 /LA RL = 0, Over Specified Temp Range
Peak Output Voltage
Positive +12 +14.2 +12 +14.2 V RL = 00, 5 /LA :5 IS :5 500 /LA
Negative -12 -14.4 -12 -14.4 V RL = 00, 5 /LA :5 IS :5 500 /LA
Supply Current 2.6 2.6 mA IS = 500 /LA, Soth Channels
VOS Sensitivity
Positive 20 150 20 150 /LVIV ~ VOS/~ V +
Negative 20 150 20 150 /LVIV ~ VOS/~ V -
CMRR 80 110 80 110 dB
Common Mode Range ±12 ±13.5 ±12 ±13.5 V Referred to Input (Note 5)
Channel Separation 100 100 dS 20 Hz < f < 20 KHz
Diff. Input Current 0.02 10 0.02 100 nA IS = 0, Input = ± 4 V
Leakage Current 0.2 5 0.2 100 nA IS = 0 (refer To Test Circuit)
Input Resistance 10 26 10 26 KO
Open Loop Sandwidth 2 2 MHz
Slew Rate 50 50 V//LSec Unity Gain Compensated
Buff. Input Current 0.4 5 0.4 5 p.A (Note 5)
Peak Suffer Output Voltage 10 10 V (Note 5)

TEST CIRCUITS

-'5 V
LEAKAGE CURRENT TEST CIRCUIT DIFFERENTIAL INPUT CURRENT TEST CIRCUIT

Note 1. For selections to a supply voltage above ± 22 Note 4. These specifications apply for Vee == VEE
V, contact factory. 15V, TA = 25°C, amplifier bias current (IB) =
Note 2. For operating at high temperatures, the device 500 #LA, pins 2 and 15 open unless otherwise
may be derated based on a 150°C maximum specified. The inputs to the buffers are ground-
junction temperature and a thermal resistance ed and outputs are open.
of 175° C/W which applies for the device sol- Note 5. These specifications apply for VCC = VEE =
dered in a printed circuit board, operating in 15 V, IB = 500 #LA, ROUT == 5 kO connected
still air. from the buffer output to - VEE and the input
Note 3. Buffer output current should be limited so as to of the buffer is connected to the transconduct-
not exceed package dissipation. ance amplifier output.

8-52
TYPICAL PERFORMANCE CHARACTERISTICS
XR·13600
INPUT OFFSET VOLTAGE INPUT BIAS CURRENT
10'

-55'e
'J~~I~ IS ~

I
_+12S'C
10'
,1
Ifill
"
-I ~ v:
'IX 10'
11". I 25'C
-3 -
/ IIU
:5!j'(
1. lMlI
10
.~1~ :C;:
§§
pi"= .~ Illi
-7

-8 1\ " IIII!
la..A l000~A

AMPLIFIER BIAS CORMENT (lSi AMPLIFIEH BIAS CURRf.NT 1181 AMPlIfl(H BIASCURHENT "SI

PEAK OUTPUT VOLTAGE AND

PEAK OUTPUT CURRENT COMMON MODE RANGE LEAKAGE CURRENT
10' IS

VS"15~
10'
Ill~gUT I F i= I'IVIN • HVIN • VOUT." 3& V :::; ~
IU to-
"I~~MR I r-=I'-
111111111 II 1IIIII II 111111 <1251 14 1-1- to-- / "
10'
13.5
It~I~I, lSi) I-
10'

~
RLOAO·...,Q
+25>°C r--
T~fC
13 l - f-
-6S'c
II" V V
10'

i l- f- t- 10'

10
V
'"
0(
-13.6
fl-
VOUT
~I-
I-
10'
/ / OV

11111 -IU 1== '/

IIIIIIIV 111111 11111 10
// I I
_sooe -2S'C o°c 2S'C sooe 75°C 100'e 12S'C
AMPLIFIER BIAS CURR[~T !lSi AMPLIFIER BIAS CURRENT lIel AMBIENT TEMP!RATURE I1AI

INPUT LEAKAGE TRANSCONDUCTANCE INPUT RESISTANCE

10'~~
10'

1= ~
10'
~~ -
~+125'C PlNS2.15

•
PIN 2.15
t- OPEN
IlII OPEN mIT

I
V "lav
1 I NUIIII 1111111 111111

II
j 10'
~ 10'
- ..
I t=
1 F=
r- _.•
10' ; 10'

10&il~
- g
~~
f-

~§
-

~~
-56'C~
"'-"
+ZS·C
tUSee

I I
10'

r=
J..-
II1 I II 111111
111111 III
1111111
11111
111111111
I
I I II nil
1ooa.. A 10a..A
I~PUT DIFFERENTIAL VOLTAGE AMPLIFIER BIAS CURRENT lIel AM~llf IE. A !:lIAS CURHiNT Ual

AMPLIFIER BlA& VOLTAGE VI

AMPLIFIER 81AS CURRENT INPUT AND OUTPUT CAPACITANCE OUTPUT RESISTANCE
10'

1100
IIII ~;.' : 11'~1~
1-I •
T i ~ ~;~J~
. WJI I-~
1600

1400
.... 1fflr I _f-'
Vi'
t-
10'

+25~~' ,....
CIN
~
1200

1000
~rT III
Co

10'

100
!,W~ ..... f-

600
L..o-
~,..
10'
400
r--
200

'--
'"A 10",11 I 00" A 1000"A '"A 10"A I~A I.A 10.A 1oa.. A
AMPLIFIER BIAS CURRENT IIBI AMPLIFI!R BIAS CURRENT IIBI AMPLltl!R BIASCURHENT "Sl

8-53
XR·13600
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
DISTORTION VS DIFFERENTIAL
INPUT VOL TAGE VOLTAGE VS AMPLIFIER BIAS CURRENT OUTPUT NOISE VS FREOUENCY

VS· :t15V
RL -10KU

!I .~
20
~ , r--
f-

~
IABC • I mA ": I
-¥ ",: - Ig~i A \
VIN(pnk)

-20 t-+-f+HtfIf-+-f+Htflf7'9"-:: i 400

r-
-40 t-+-f+IttHl7'9.-H-HtfIf-+-++ 300
i'...
~ 200 ~
IB-lmA

~ r-
r- III I
~ Illl.l~lA
0.01 L--..........u..wl..u......II............
I.I..III..u..I.L.............................u.u "- III
10 1000 .lpA lpA l00IJA lD<lOj<A 10 100 lK 10K lOOK
DIFFERENTIAL INPUT VOLTAGE ImVppl AMPLIflEH BIAS CUHRENT.IS FREaUENCY (H.I

TYPICAL CIRCUIT CONNECTION

0.01 pF

62K
~
10K
INPUT o-~--J>.IV'I,.-----1r------~-"-t

5111

1.3K B,9
OUTPUT

10 K
-15V
O.oolpF

UNITY GAIN FOLLOWER

CIRCUIT DESCRIPTION approaches unity and the Taylor series of the 1n func-
tion can be approximated as:
The differential transistor pair 04 and 05 form a trans-
conductance stage in that the ratio of their collector KT 1n !§ == ~ 15 - 14
currents is defined by the differential input voltage ac- q 14 q 14
cording to the transfer function:

VIN = KT 1n!§ (1 )
14 == 15 == ~
2
q 14

where VIN is the differential input voltage, KT/q is ap- VIN [ (I:~~)] = 15 -14 (4)
proximately 26 mV at 25° C and 15 and 14 are the collec-
tor currents of transistors 05 and 04 respectively. With
the exception of 03 and 013, all transistors and diodes Collector currents 14 and 15 are not very useful by them-
are identical in size. Transistors 01 and O? with Diode selves and it is necessary to subtract one current from
D1 form a current mirror which forces the-sum of cur-
the other. The remaining transistors and diodes form
rents 14 and 15 to equal IS; three current mirrors that produce an output current
(2) equal to 15 minus 14 thus:

VIN [(IS)(q)] = lOUT (5)

where IS is the amplifier bias current applied to the gain 2KT
pin.
The term in brackets is then the transconductance of
For small differential input voltages the ratio of 14 and 15 the amplifier and is proportional to IS.

8-54
LINEARIZING DIODES APPLICATIONS
XR·13600
For differential voltages greater than a few millivolts, VOLTAGE CONTROLLED AMPLIFIERS (VCA)
Equation 3 is no longer accurate, and the transconduct-
ance becomes increasingly nonlinear. Figure 1 demon- Figure 2 shows how the linearizing diodes can be used
strates how the internal diodes can linearize the trans- in a voltage controlled amplifier. To understand the in-
fer function of the amplifier. For convenience assume put biaSing, it is best to consider the 13 KO resistor as a
the diodes are biased with current sources and the in- current source and use a Therenin equivalent circuit as
put signal is the form of current IS. Since the sum of 14 shown in Figure 3. This circuit is similar to Figure 1 and
and 15 is IS and the difference is lOUr. currents 14 and operates the same. The potentiometer in Figure 2 is ad-
15 can be written as follows: justed to minimize the effects of the control Signal at
the output.
30K
GAIN
.....--J\N'v---U CONTROL

RS 13K

- lOUT - 21S (IS)

"""iO OUTPUT
RA +-----0-1
Rill
30K

-VS

INPUT

Figure 2. Voltage Controlled Amplifier (VCA) Circuit

Figure 1. Linearizing Diodes

Since the diodes and the input transistors have identi-

cal geometries and are subject to similar voltages and
temperatures, the following is true:

10 I IB lout
-+ S - +-
KT1n_2_ _ =KT1n~
~ - lout

II
q !Q -
IS q RTH tiS

222 RTW RS
VTH

lout = IS (~)
10
for IIsl < ~
2
(6)
Figure 3. Equivalent VCA Input Circuit
Notice that in deriving Equation 6, no approximations
have been made and there are no temperature depen- For optimum signal-to-noise performance, IB should be
dent terms. The limitations are that the signal current as large as possible as shown by the Output Voltage vs.
not exceed 10/2 and that the diodes be biased with cur- Amplifier Bias Current graph. Larger amplitudes of in-
rents. In practice, replacing the current sources with put signal also improve the SIN ratio. The linearizing di-
resistors will generate insignificant errors. odes help here by allowing larger input signals for the
same output distortion as shown by the Oistortion vs.
CONTROLLED IMPEDANCE BUFFERS Oifferential Input voltage graph. SIN may be optimized
by adjusting the magnitude of the input signal via RIN
The upper limit of transconductance is defined by the (Figure 2) until the output distortion is below some de-
maximum value of IB (2 mA). The lowest value of IB for sired level. The output voltage swing can then be set at
which the amplifier will function therefore determines any level by selecting RL.
the overall dynamic range. At very low values of IB, a
buffer which has very low input bias current is desir- Although the noise contribution of the linearizing diodes
able. A FET follower satisfies the low input current re- is negligible relative to the contribution of the amplifi-
quirement, but is some what non-linear for large voltage er's internal transistors, 10 should be as large as possi-
wing. The controlled impedance buffer is a Oarlington ble. This minimizes the dynamic junction resistance of
which modifies its input bias current to suit the need. the diodes (re) and maximizes their linearizing action
For low values of IB, the buffer's input current is mini- when balanced against RIN. A value of 1 mA is recom-
mal. At higher levels of IB, transistor 03 biases up to mended for 10 unless the specific application demands
012 with a current proportional to IB for fast slew rate. otherwise.

8-55
XR·13600
STEREO VOLUME CONTROL I.
V1N:z RC
The circuit of Figure 4 uses the excellent matching of MOOULATION

the two XR-13600 amplifiers to provide a Stereo Vol-

ume Control with a typical channel-to-channel gain
tracking of 0.3 dB. Rp is provided to minimize the out- VOS

put offset voltage and may be replaced with two 5100

resistors in AC-coupled applications. For the compo- Vo
nent values given, amplifier gain is derived from Figure
2 as being:

Va = 940 x IB (mA)
VIN Figure 5. Amplitude Modulator
30 K

30 K
Vc
RC

10 K OUTPUT
VIN2 AMPLlTUOE
RIN

Figure 6. Four-Quadrant Multiplier

50K
10K

Figure 4. Stereo Volume Control

-:f IK

If Vc is derived from a second signal source then the Vo

circuit becomes an amplitude modulator or two-
quadrant multiplier as shown in Figure 5, where: 10 K

-15V
10 = -2IS (IB) = -21S VIN2 _ 21S (V = 1.4V)
10 10 RC 10 RC Figure 7. AGC Amplifier

The constant term in the above equation may be can- VOLTAGE CONTROLLED RESISTORS (VCR)
celled by feeding IS x IORC/2(V + 1.4 V) into 10. The
circuit of Figure 6 adds RM to provide this current, re- An Operational Transconductance Amplifier (aTA) may
sulting in a four-quadrant multiplier where RC is be used to implement a Voltage Controlled Resistor as
trimmed such that Va = OV for VIN2 = OV. RM also shown in Figure 8. A signal voltage applied at RX gener-
serves as the load resistor for 10. ates a VIN to the XR-13600 which is then multiplied by
the gm of the amplifier to produce an output current,
Noting that the gain of the XR-13600 amplifier of Figure thus:
3 may be controlled by varying the linearizing diode
current 10 as well as by varying IB, Figure 7 shows an _ R + RA
RX - - - -
AGC Amplifier using this approach. As Va reaches a gmRA
high enough amplitude (3VBE) to turn on the Darlington
transistors and the linearizing diodes, the increase in where gm "" 19.2 18 at 25°C. Note that the attenuation
10 reduces the amplifier gain so as to hold Va at that of Va by Rand RA is necessary to maintain VIN within
level. the linear range of the XR-13600 input.

8-56
 XR·13600
o---J\l\i"v----Ovc

200n

vo

10 K

Figure 11. Voltage Controlled Low-Pass Filter

Figure 8. Voltage Controlled Resistor, Single-Ended
Figure 12 shows a voltage controlled high-pass filter
which operates in much the same manner, providing a
Figure 9 shows a similar VCR where the linearizing di- single RC roll-off below the defined cut-off frequency.
odes are added, essentially improving the nose per-
formance of the resistor. A floating VCR is shown in Fig-
ure 10, where each "end" of the "resistor" may be at
any voltage within the output voltage range of the XR-
13600. ( VOs)
NUll

Figure 12. Voltage Control/ed High·Pass Filter

Additional amplifiers may be used to implement higher

order filters as demonstrated by the two-pole But-
terworth lowpass filter of Figure 13 and the state varia-
Figure 9. Voltage Controlled Resistor with Linearizing Diodes ble filter of Figure 14. Due to the excellent gm tracking
of the two amplifiers and the varied bias of the buffer

II
Darlingtons, these filters perform well over several dec-
ades of frequency.

Vc

Vo

'--------0 RX":: RA 0---------'

Figure 10. Floating Voltage Controlled Resistor lOOp'

VOLTAGE CONTROLLED FILTERS Figure 13. Voltage Controlled 2-Pole Butterworth Low-Pass
Filter
OTA's are extremely useful for implementing voltage
controlled filters, with the XR-13600 having the advan- VOLTAGE CONTROLLED OSCILLATORS (VCO)
tage that the required buffers are included on the I.C.
The VC La-Pass Filter of Figure 11 performs as a unity- The classic Triangular/Square Wave VCO of Figure 15 is
gain buffer amplifier at frequencies below cut-off, with one of a variety of Voltage Controlled Oscillators which
the cut-off frequency being the point at which Xcigm may be built utilizing the XR-13600. With the compo-
equals the closed-loop gain of (R/RA). At frequencies nent values shown, this oscillator provides signals from
above cut-off the circuit provides a single RC roll-off (6 200 kHz to below 2 Hz as IC is varied from 1mA to
dB per octave) of the input signal amplitude with a - 3 10nA. The output amplitudes are set by IA x RA Note
dB point defined by the given equation, where gm is that the peak differential input voltage must be less
again 19.2 x IB at room temperature. than 5 volts to prevent zenering the inputs.

8-57
XR·13600
15 K 360 0 or 180 0 for the inverter and 60 0 per filter stage.
O---~----------~~~-OVc
This veo operates from 5 Hz to 50 kHz with less than
to K
1 % THO.
IK
30 K
lO-'ASS
OUT

Figure 14. Voltage Controlled State Variable Filter

Vc

Figure 17. Sinusoidal VCO Using Two XR-13600 Circuits

Figure 18 shows how to build a veo using one amplifier

when the other amplifier is needed for another function.

Figure 15. Triangular/Square-Wave VCO 10 K

30 K
o----AJ'VV---t--ovc
A few modifications to this circuit produce the ramp!
pulse veo of Figure 16. When V02 is high, IF is added
to Ie to increase amplifier A 1's bias current and thus to
increase the charging rate of capacitor e. When V02 is
low, IF goes to zero and the capacitor discharge cur-
rent is set by Ie. vo

~~
VCO-~~~~------------------ __,

Figure 18. Single Amplifier YCO

ADDITIONAL APPLICATIONS
(V+-.8V1RZ
VPK·~
Figure 19 presents an interesting one-shot which draws
_ _ 100 K 2VPKC
~ ________________ ~~ ~~ __ ~ tH'~

no power supply current until it is triggered. A positive-

Rt
'L
2V'PKC
---;c- going trigger pulse of at least 2V amplitude turns on the
'e" ~'KD for IC«IF
amplifier through RS and pulls the non-inverting input
high. The amplifier regenerates and latches it output
high until capacitOi C chaiges to the voitage ievei on
Figure 16. Ramp/Pulse YCO the non-inverting input. The output then switches low,
turning off the amplifier and discharging the capacitor.
The capacitor discharge rate is speeded up by shorting
The voltage-controlled low-pass filter of Figure 11 may the diode bias pin to the inverting input so that an addi-
be used to design a high-quality sinusoidal yeo. The tional discharge current flows through 01 when the am-
circuit of Figure 17 employs two XR-13600 packages, plifier output switches low. A special feature of this tim-
with three of the amplifiers configured as low-pass filt- er is that the other amplifier, when biased from Va, can
ers and the fourth as a limiterlinverter. The circuit oscil- perform another function and draw zero stand-by power
lates at the frequency at which the loop phase-shift is as well.

8-58
 XR·13600
20 K
r -........- - - - ' V \ I \ r - - -__-i~
1K S TRIGGER
O.OI~f
n---JV\~--4

7MS

+-----oVo
Jl

10 K

Figure 21. Phase-Locked Loop

Figure 19. Timer With Zero Stand-By Power

The operation of the multiplexer of Figure 20 is very

straight-forward. When A1 is turned on it holds Vo
equal to VIN1 and when A2 is supplied with bias current
then it controls VO. Cc and RC serve to stabilize the
unity-gain configuration of amplifiers A1 and A2. The
maximum clock rate is limited to about 200 kHz by the
XR-13600 slew rate into 150 pF when the (VIN1 - VIN2) Vo
differential is at its maximum allowable value of 5 volts.

10 K

-5 V

Figure 22. Schmitt Trigger

Figure 20. Multiplexer

··12 V

Figure 23. Tachometer

•
represent the maximum low and maximum high output
The phase-locked loop of Figure 21 uses the four- voltage swing of the XR-13600. D1 added to provide a
quadrant multiplier of Figure 6 and the VCO of Figure discharge path for Ct and A1 switches low.
18 to produce a PLL with a ± 5 % hold-in range and an
input sensitivity of about 300 mV. The sample-hold circuit of Figure 24 also requires that
the Darlington buffer used be from the other (A2) half of
The Schmitt trigger of Figure 22 uses the amplifier out- the package and that the corresponding amplifier be bi-
put current into R to set the hysteresis of the compara- ased on continuously.
tor; thus VH = 2 x R x 18 will produce a Schmitt trig-
ger with variable hysteresis. The peak detector of Figure 25 uses A2 to turn on A1
whenever VIN becomes more positive than VO. A1 then
Figure 23 shows a tachometer or frequency-to-voltage charges storage capacitor C to hold Vo equal to VIN
converter. Whenever A 1 is toggled by a positive-going PK. One precaution to observe when using this circuit:
input, an amount of charge equal to (VH - VL) Ct is the Darlington transistor used must be on the same
sourced into Cf and Rt. This once per cycle charge is side of the package as A2 since the A1 Darlington will
then balanced by the current of VO/Rt. The maximum be turned on and off with A1. Pulling the output of A2
FIN is limited by the amount of time required to charge low through D1 serves to turn off A1 so that Va remains
Ct from VL to VH with a current of 18, where VL and VH constant.

8-59
 XR·13600 .s v o-.JV"0V"KV-_O +Sn SAMPLE the input signal. Because the output power of A1 is held
_S..J HOLD L constant, the RMS value is constant and the attenua·
VIN tion is directly proportional to the RMS value of the in·
put voltage. The attenuation is also proportional to the
diode bias current. Amplifier A4 adjusts the ratio of cur·
rents through the diodes to be equal and therefore the
Vo
voltage at the output of A4 is proportional to the RMS
value of the input voltage. The calibration potentiometer
-S V is set such that Va reads directly in RMS volts.
Cc 1'OOOPI
RCl,eoll

, K

-S V

Figure 24. Sample-Hold Circuit

PEAl( DETECT
100 •
-Ui~5031oLD V'UF

Figure 27. True RMS Converter Circuit

Vo The circuit of Figure 28 is a voltage reference of varia·

ble Temperature Coefficient. The 100 KO potentiometer
adjusts the output voltage which has a positive TC
above 1.2 volts, zero TC at about 1.2 volts and negative
··1~ V TC below 1.2 volts. This is accomplished by balancing
the TC of the A2 transfer function against the comple·
Figure 25. Peak Detector and Hold Circuit mentary TC of D1.

The ramp-and-hold of Figure 26 sources IB into capaci·

tor C whenever the Input to A1 is brought high, giving a
ramp'rate of about IV/ms for the component values
shown.

RAMP
UP
+6V

<lV
Jl -6V
RAMP
ENABLE

Figure 28. Delta VBE Reference

Figura 26. Ramp and Ho!d Circuit

The log amplifier of Figure 29 responds to the ratio of
current thru buffer transistors 03 and 04. Zero temper,
The true RMS converter of Figure 27 Is essentially an ature dependence for VOUT is ensured In that the TC of
automatic gain. control amplifier which adjusts its gain the A2 transfer function is equal and opposite to the TC
such that the AC power at the output of amplifier A1 is of the logging transistors 03 and 04.
constant. The output power of amplifier A1 is monitored
by squaring amplifier A2 and the average compared to The wide dynamic range of the XR·13600 allows easy
a reference voltage with amplifier A3. The output of A3 control of the output pulse width in the pulse·width
provides bias currellt to the diodes of A1 to attenuate modulator of Figure 30.

8-60
 XR·13600
_-_2_K_T---,13:<... __ 2KTVC
VIN1 =
q l2 ql2 RC

The voltage on the base of 01 is then

The ratio of the 01 to 02 collector currents is defined

by:
Figure 29. Log Amplifier
VS1 = KT 1nlC2 "" KT 1n!a
q IC1 q 11

Combining and solving for IS yields:

2(R1 + R2) Vc]

IS = (I)
1 exp [
12R1RC

This logarithmic current can be used to bias the circuit

of Figure 4 to provide temperature independent stereo
attenuation characteristic.

+1SV

Figure 30. Pulse Width Modulator

For generating IS over a range of 4 to 6 decades of cur-

rent, the system of Figure 31 provides a logarithmic
current out for a linear voltage in.

Since the closed-loop configuration ensures that the in-

put to A2 is held equal to OV, the output current of A1 is
equal to 13 = - VC/RC.

The differential voltage between 01 and 02 is attenu-

ated by the R1, R2 network so that A1 may be assumed
to be operating within its linear range. From equation
(5), the input voltage to A1 is:
-'5V

Figure 31. Logarithmic Current Source

II
. Vcco-------~--~------------------~----~------._~
II
06
BUFFER
INPUT

OIOOE BIAS
BUFFER
OUTPUT
OUTPUT

-I NPUT o---<l~-I "NPUT

3,14

AMP BIAS
INPUT C>--_--{

VEE
IISUBSTRATEI O~ (One
6 Channel Only)

EQUIVALENT SCHEMATIC DIAGRAM

8-61
8-62
 Cross References & Ordering Information

~TI_el_e_co_m__m_u_n_ic_a_t_io_n_C_i_rc_u_it_s__________________•
Data Communication Circuits •
--------
Computer Peripheral Circuits

Industrial Circuits

Instrumentation Circuits

Interface Circuits

Special Function Circuits

User Specific Digital ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

9
 Section 9 - User Specific Linear ICs - Full Custom/Semi-Custom
Semi-Custom Design Concept ..... . 9-2
Answers to Frequently Asked Questions 9-4
Economics of Semi-Custom Design 9-5
Converting Semi-Custom to Full Custom 9-6
Full Custom Development . . . . . 9-8
Testing of Semi-Custom ICs . . . . 9-9
Linear Semi-Custom Design . . . . 9-10
Linear Semi-Custom Design Cycle 9-11
Full Custom Designs . . . 9-12
Linear Master-Chips 9-14
XR-A100 Master-Chip . 9-16
XR-B100 Master-Chip . 9-17
XR-C100A Master-Chip 9-18
XR-D100 Master-Chip 9-19
XR-E100 Master-Chip 9-20
XR-F100 Master-Chip 9-21
XR-G 100 Master-Chip 9-22
XR-H 100 Master-Chip 9-23
XR-J100 Master-Chip 9-24
XR-L 100 Master-Chip 9-25
XR-M100 Master-Chip 9-26
XR-U100 Master-Chip 9-27
XR-V100 Master-Chip 9-28
XR-W100 Master-Chip 9-29
XR-X100 Master-Chip 9-30

•
XR-400 12L Master-Chip 9-31
Linear Master-Chip Components Electrical Characteristics 9-32
Linear Master-Chip Kit Parts . . . . . . . . . . . . . . . . . 9-34

9-1
SEMI·CUSTOM DESIGN CONCEPT
Traditionally, the development of custom IC's has been tive or cooperative development effort between Exar
a long and costly undertaking. The development time and the customer. In most cases, the cost and develop-
would normally run in excess of one year, design ment time for the program can be reduced even further,
changes are slow and costly, and it may take a long if the customer does the design and breadboarding of
time to get from the prototype stage to full production. his own semi-custom IC, using Exar Design Kits, in-
Because of these difficulties, the use of custom IC's struction manuals and layout sheets.
could be economically justified only when a very large
quantity of circuits, i.e., several hundred-thousand The semi-custom design approach is based on a num-
units, were required during the life of the end product. ber of standardized IC chips with fixed component loca-
In the past, these drawbacks have severely limited the tions. These standardized IC chips, called Master-
use of custom monolithic IC's. Chips, contain a large number of undedicated active
and passive components (i.e., transistors, resistors,
The semi-custom design concept, pioneered by Exar, logic gates, etc.). These integrated components can be
now overcomes this traditional problem. Exar makes interconnected in thousands of different ways with a
this possible by stocking wafers that are completely customizing interconnection pattern. Each different
fabricated except for the final process step of device in- metal interconnection pattern creates a new custom IC.
terconnection which metalizes all selected compo- The figures below show the magnified photograph of a
nents together in the required circuit configuration. This Master-Chip, both in its prefabricated form and after its
enables an engineer to design a metal mask based on customization with a special interconnection pattern.
his circuit which will interconnect the uncommitted This method is called semi-custom rather than full cus-
components on the prefabricated wafers, and thus con- tom, since only the last layer of tooling is changed to
vert them into customized chips corresponding to the customize an IC chip, and rest of the layers are stan-
customer's design. This unique method of IC design dard. As a result, the development phase is very short,
and development allows one to develop an almost un- far less expensive and risk free, compared to conven-
limited variety of custom linear or digital integrated cir- tional full or dedicated custom IC's. Similarly, if a design
cuits at very substantial cost savings. change or iteration is necessary, it can be readily ac-
commodated within a matter of weeks by simply gener-
The semi-custom program is intended for those cus- ating a new or modified interconnection pattern.
tomers seeking cost effective methods of reducing
component count and board size in order to compete Exar offers a wide choice of Master-Chips for linear and
more effectively in a changing marketplace. The pro- digital semi-custom design. Presently, Master-Chips are
gram allows a customized monolithic IC to be devel- available in linear bipolar, linear compatible 12L and
oped with a turnaround time of several weeks, at ap- CMOS technologies. Additional chips are under devel-
proximately 10% to 20% of the development costs for opment for a variety of special applications. The details
tooling associated with the conventional full custom de- of each of the presently available chips are discussed
signs. The semi-custom design concept is an interac- in the later section of this book.

Magnified Photograph of a Linear Master-Chip Before and After Customizing

9-2
DESIGN KITS
Exar offers three Design Kits: One for linear bipolar, one tomer and is essential to the success of the program. It
for 12L and one for CMOS. Since the general approach avoids any possible design pitfalls or misunderstand-
to semi-custom design is the same as that for full cus- ings. This early interaction also allows you to find out
tom, these design kits are valuable tools for both full some of the options or variations available in Exar's
custom and semi-custom design work. This is especial- semi-custom programs and choose the one which is
ly true in the case of linear design. Each of these kits best suited to your needs.
contain a comprehensive design manual, a set of semi-
custom layout sheets and a PC. board, IC sockets and The following is required by Exar's technical staff to pro-
other hardware for building your breadboard. The only vide you with an accurate feasibility study of your proj-
active components in these kits, that are meant for use ect. and a budgetary estimate of the development
in breadboarding, are the transistor arrays found in the costs, timetables and production pricing.
linear bipolar and 12L design kits. The logic blocks
found in the 12L design kit is meant to be used for pro- • A block diagram of circuit function and input/output
cess evaluation. Digital breadboarding can be done us- interface requirements.
ing the appropriate logic family such as 74 LXX, 74CXX
• A circuit schematic or logic diagram of your circuit.
or 4XXX. The kits are designed so that an engineer,
armed only with a background in discrete design, a cal-
• Preliminary or objective performance specifications
culator and a pencil, can design his own customized in-
and limits on critical circuit parameters (also possible
tegrated circuit. The technical material is presented in
tradeoffs which may be allowed).
a straight forward, no-nonsense format with iots of illus-
trative figures and all of the pertinent equations.
• Test specifications
After the circuit is designed, and before it is bread-
boarded, it is recommended that the customer send
Exar a schematic and a circuit description for an engi- • Packaging requirements.
neering evaluation. Normally, there is no charge for
such an evaluation. Exar has successfully completed • Production quantity requirements.
well over 850 custom design programs and our experi-
ence can provide valuable guidelines. Exar's Applica- • Desired development and production timetables.
tions Engineering department is ready and able to help
our semi-custom design program customers in both the • An indication of how much of the breadboarding, lay-
breadboard and layout stage. We can provide immedi- out, etc., can be done by you, the customer, using
ate answers to your circuit design or testing questions, Exar's Design Kits or standard logic blocks (74 LXX,
and speed your custom design on its way. 74CXX or 4XXX).

YOUR FIRST STEP Once the above data package is submitted to Exar, we
would review it and respond to you within a few days.
Your very first step, at the start of a semi-custom pro-
gram, should be to contact Exar for a preliminary analy- Normally, the test system development effort is initiated
sis and discussion of your needs. This can be done in parallel with chip development. Exar has a complete
even while the program is still at the thought stage. This computer controlled IC test facility and offers complete
initial review by Exar is performed at no cost to the cus- IC testing capability for production units .

•
CUSTOMER METAL FINISHED
LAVOUT MASK CHIP

Steps of Seml·Custom Design

9-3
FREQUENTLY ASKED QUESTIONS WHAT IF ADDITIONAL DESIGN CYCLES ARE NEEDED?
AND THEIR ANSWERS
If the customer desires to modify the design or layout
Based on our long experience with Exar's semi-custom after evaluation of the initial prototypes, a new design it-
Master-Chips, we have compiled a comprehensive eration cycle can be completed within five weeks for
glossary of the most often asked questions concerning the bipolar and CMOS designs, and within eight to ten
the program. The following is a list of these questions weeks for the 12L designs. Cost for this iteration is
and their answers. dependent on the complexity of modification.

WHAT IS THE COST OF THE BASIC PROGRAM? WHAT ABOUT PRODUCTION PRICING?
The cost of the semi-custom development program de- The production pricing of monolithic IC's depends upon
pends on how much of the design and layout is done by a number of important factors such as:
the customer. In general, the basic semi-custom pro-
gram is where the customer does the design, bread- a) Master-Chip type.
board evaluation and pencil layout on the Master-Chip
worksheet; and Exar does only the IC tooling and proto- b) Circuit complexity (i.e., yield).
type fabrication. This is the most economical and cost
c) Device performance and test requirements.
effective approach.

For bipqlar semi:custom designs, the developl"T!ent cost d) Special environmental screening requirements
of the basic program is in the range of $2,000 to (burn-in, hermeticity tests, etc.).
$8,000, starting with an accurate layout supplied by the
e) Package type required.
customer. The above prices also include the cost of 50
monolithic prototypes delivered at the completion of the In the case of a custom IC, it is impossible to anticipate
program. Additional prototypes are available at a nomi- the impact of these factors without detailed knowledge
nal cost, in minimum lots of 200 units. about the circuit and its application. Each custom IC,
by definition, has some unique requirement or feature
In the case of 12L or CMOS semi-custom designs, the
associated with it. After reviewing your specific needs,
basic development program costs are in the range of
particularly with regard to the circuit performance and
$4,200 to $8,500, depending on the layout complexity
quality requirements, Exar can provide you with a de-
and the particular Master-Chip used. This development
tailed proposal outlining the development costs and
cost also includes 25 monolithic prototypes. Additional
production pricing for your particular circuit.
prototypes are available at a nominal cost, in minimum
lots of 200 units each.
WHAT ABOUT THE TESTING OF SEMI-CUSTOM IC's?
WHAT IS THE DEVELOPMENT TIME? Exar will develop test software and fixtures to provide
Typical development time for the basic bipolar semi- fully tested production IC's. All production devices re-
custom program is four to six weeks, starting with the ceive 100% electrical test and screening to a mutually
customer's pencil layout and ending with the monolithic agreed upon device specification. In addition to the
prototypes. If Exar is required to do the IC layout or complete electrical testing, all of the production de-
breadboard evaluation, several additional weeks may vices are screened by Exar's Quality Assurance depart-
be required to complete the development program. ment to assure compliance with the agreed upon Ac-
ceptable Quality Level (AQL) standards.
In the case of 12L or CMOS semi-custom development
programs, the typical development time is eight to ten Exar can perform two basic types of tests for produc-
weeks, starting with the pencil layout of the Master- tion IC's: (1) parametric testing which measures a spe-
Chip worksheet. The 12L semi-custom program takes cific parameter value (normally current or voltage) and
slightly longer than bipolar or CMOS because it re- compares it against pre-established limits; (2) function-
quires three layers of custom tooling, rather than one, al testing which applies a series of operating conditions
to customize a prefabricated Master-Chip. and compares the circuit under test with a known good
device. These two types of tests can be performed both
as steady state (dc) or dynamic (ac) measurements.

9-4
ECONOMICS OF SEMI-CUSTOM DESIGN
In developing either linear or digital custom circuits, priced at $3.20 each, at the same 50,000 production
one is always confronted with the following key ques- level. Then, its amortized per unit price will be $3.30, or
tion: for a given product type and production require- approximately 20 % cheaper than a full custom.
ment, is it cheaper to develop a semi-custom or full
custom IC? Since the functional requirements of each The figure below gives a comparative graph of the am-
custom IC program vary greatly, there is no general an- ortized unit price for a typical full custom design, along
swer to the above question. However, based on Exar's with the equivalent in semi-custom form for various pro-
long experience in both full and semi-custom IC design duction quantities. For comparison purposes, the rela-
and depending on the overall production requirements, tive ratio of the amortized unit price is plotted along the
it is possible to establish some sound economic guide- vertical axis. If this ratio is greater than 1.0 then the
lines for choosing the most cost effective approach. semi-custom method is the more cost effective solu-
tion.
COST FACTORS INVOLVED
NO TWO IC's ARE THE SAME
Any custom IC development, whether full or semi-
custom, involves similar types of cost factors. These By definition, each custom IC type is unique. Therefore,
are: the cost comparison curve given below is shown as a
spread rather than a Single line. This is because, in ad-
1. Non recurring engineering (NRE) or development dition to the production quantity, the cost of monolithic
costs. IC's also depends on the circuit complexity, special test
requirements and the IC package type.
2. Cost or unit price of the product in production quan-
tities. The key information contained in the relative cost vs.
quantity figure can be summarized as follows:
In the case of monolithic IC's, particularly those which
have relatively limited production volume, the develop- 1. For a total production requirement of 50,000 pieces
ment costs may be a significant factor in the cost of the or less, the semi-custom approach is definitely the
end product. Therefore, when discussing the eco- most economical.
nomics of custom IC's for medium to low production
quantities, it is best to consider the cost tradeoffs in 2. For a production requirement of 200,000 pieces or
terms of the amortized unit price of the IC at a given more, the full custom design is more cost effectivo.
production volume. This amortized unit price is defined
as the actual cost of each unit including its share of the 3. For production quantity requirements in the 50,000
development cost. As an example, a full custom IC may to 200,000 piece range, the crossover point for the
cost $50,000 to develop and may be priced at $2.90 most economical approach will depend strongly on
each at a 50,000 piece total production level. Then, its the specifics of a particular Ie function; i.e., its spe-
true amortized unit price including development costs cial test, environmental screening, and package re-
will be $2.90 plus $1.00, or $3.90. Similarly, an equiva- quirements.
lent semi-custom IC may cost $5,000 to develop and be

l.O ,...........,.,.."...,."..,..,.

Typicil ··spread·· of cost

distribution depending
on circuit type, test Ind
scr&ening requiremllnts,
plcklge type, etc.

- - - - - + - - 1 - Cros
r&gion

1k lk 10k lOk 100tt lOOk 1000II

Total QUlntity of IC·s PurchlMd (in thousands'

TYPICAL COST VS QUANTITY COMPARISON OF FULL CUSTOM AND SEMI-CUSTOM DESIGNS

9-5
CONVERTING SEMI-CUSTOM TO FULL CUSTOM
Exar can offer you the combined advantages of semi- In this manner, the customer has the best of both
custom and full custom design programs. This is be- worlds with the combination of these two technologies.
cause Exar has a complete semiconductor manufactur- The quick turnaround advantage of semi-custom
ing facilities. This unique capability allows Exar to state Master-Chips provide prototypes and initial production
a custom development program using a combination of units, while the subsequent full custom design provides
semi-custom Master-Chips during the initial phases of a cost savings at high volume production. During this
customer's product, taking full advantage of the low transition, the customer is assured of a continuous flow
tooling cost and short development cycle. As the prod- of product through its production line.
uct matures and its market expands (resulting in higher
volume production run rates) Exar can convert the mul- In such a two-step development, the semi-custom pro-
tiple semi-custom chip approach into a single custom totypes often serve as a monolithic breadboard to opti-
IC, thus achieving a cost reduction and in many cases mize and debug the final design. This allows design iter-
a performance improvement. The significant advantage ations or changes to be made quickly and inexpensive-
of this type of program is that the risk associated with a ly. In fact, the only difference between the semi-cl,lstom
custom development is greatly reduced. The IC design and full custom chip is the actual size of the silicon
approach has been proven, production "bugs" are out chip.
of the product and your production line continues to
flow during the full custom chip development. Once the Once the design is satisfactory, conversion of a semi-
custom chip is completely characterized and found ac- custom to a full custom chip is very straight forward
ceptable, the semi-custom IC system in your product and relatively risk free. We simply remove the unused
can be phased out while the full custom IC is being electrical components from the chip to reduce the chip
phased in. size and pass the resulting cost savings on to you in the
form of a reduced unit price.
SEMI- AND FULL CUSTOM COMBINATION:
The two-step development capability; i.e., start as semi-
THE TWO-STEP DEVELOPMENT custom and finish as full custom, is a very powerful de-
In many custom development programs one is faced sign technique. It avoids the risks associated with a
conventional black box type of custom design where
with very short development times and a rapid transfer
one does not know until the very last day of develop-
into high volume production. Such a requirement does
ment whether the circuit works or if it can be manufac-
not leave room for lengthy development and design
tured.
change or iteration cycles associated with conventional
full custom IC design. The two-step program is faster and less expensive than
the conventional full custom development, since it
Exar combines full and semi-custom design capabili-
avoids costly and lengthy design iteration or modifica-
ties, and a complete wafer fabrication facility under one
tion cycles for a full custom IC. In addition, it gives the
roof, therefore, providing a unique solution to this prob-
customer a very high degree of assurance that the final
lem; initiallyqeveloping the prototypes in a semi-
full custom unit will work the first time.
custom form, and then converting them to full custom.

______________________ ~_~_J

SEMI·CUSTOM DESIGN AND ITS FULL CUSTOM EQUIVALENT

9-6
 ADVANTAGES OF SEMICUSTOM DESIGN

Significant lower costs Hybrids and discretes are quite expensive as com-
pared to semicustom ICs. Less inventory cost
also.

Higher reliability Than hybrids and discretes. Because one

semicustom IC replaces many components.

Quick turnaround Semicustom protos are delivered in less than

seven (7) weeks.

Lower development cost Less than half the full custom cost.

Iterations Are quick and less expensive than full custom

because only one mask needs to be changed.

Reduced real estate & power Because one IC is replacing many components.
Therefore, your PC board may shrink 60-80%.
Consequently, less power too.

Quick production ramp up Need 200,000 units in less than 12 weeks? Exar
can deliver using its semicustom Master-Chip®
approach.

Product security Semicustom IC is specifically designed for you;

it is not available to your competitors as an off-the-
shelf ITEM.

Reduced power, inventory cost, and production Because one custom IC replaces many discrete
cost components.

9-7
 FULL CUSTOM DEVELOPMENT
Exar offers a complete design and production capability els, operating frequency, timing diagrams, input/
for full custom IC development. This provides an excel- output impedances, power dissipation, etc.
lent complement to Exar's unique semi-custom capabil-
ity. Exar's full custom IC development and production 5. Production requirements and the desired develop-
capabilities offer complete flexibility to meet changing ment timetable.
customer needs or design problems. We can develop a
complete custom IC starting from your black box speci- 6. Packaging requirements.
fications, or reduce your working breadboard prototype
to a monolithic chip. Alternately, if you have the facili- 7. Level of screening required.
ties and resources to do the IC design and layout, Exar
will provide you with the device characteristics and IC IC FABRICATION FROM CUSTOMER'S TOOLING
layout rules for the particular process suitable to your
Exar has a complete in-house silicon wafer fabrication
design and review your IC layout for you. Then, Exar
and processing line at its main manufacturing plant in
can generate the IC tooling and fabricate your Ie proto-
Sunnyvale, California. This facility currently runs 3-inch
types.
silicon wafers and will soon add 4-inch capability, and is
also available for manufacturing custom IC's directly
YOUR FIRST STEP FOR FULL CUSTOM DESIGN from a set of customer supplied IC tooling, in coordina-
The following technical data package is required in or- tion with Exar's Mask Design department.
der for Exar to provide you with a quotation for your full If you have a set of IC tooling (masks and composite
custom development program:
overlays) or are contemplating having one designed for
you, Exar's technical staff will be glad to review it for
1. Circuit block diagram with subblocks.
you to assure compatibility with Exar's technology and
2. Circuit schematic or logic diagram. layout tolerances. Our wafer processing technology
and capabilities are compatible with the industry stan-
3. Description of circuit operation and pertinent appli- dards, and with the technologies of other leading IC
cation information. manufacturers.

4. Preliminary or objective device specification indicat- For additional information on Exar's wafer fabrication
ing minImax conditions and limits for the critical pa- services, contact Exar directly. We pride ourselves in
rameters; i.e., input/output voltage and current lev- our flexibility and quick response to your needs.

START

Circuit Function Full Custom

and Specs
Finalized by
- Feasibility
Study - Preliminary
Cost Estimate - Circuit
Design -
Customer
* ** *

Initial Breadboard
Design
.----- Production
Pricing
- Review f-- Construction
and Evaluation
f----
Computer
Simulation r--
** * * *

Pencil Prototype
Mask Mask
'--
Layout r-- Digitizing r--- Tooling I-- Wafer t---
Fabrication

* * * **

Prototype Prototype
Evaluation
by Customer
- Test and
Assembly
r--
**
*11 these steps are not done by Exar they should be done In consultation with Exar. Finish

**These steps must be done by Exar.

FLOW CHART OF TYPICAL FULL CUSTOM DEVELOPMENT

9-8
TESTING OF SEMI-CUSTOM IC's TEST INTERFACE DEVELOPMENT
All production units of semi-custom IC's are 100% The performance and characterization data derived
electrically tested and screened to test specifications from careful prototype evaluation is the basis upon
which have been mutually agreed upon between Exar which test hardware and software is developed. Exar
and the customer, using one of Exar's several comput- and the customer will jOintly determine the perform-
erized test systems. In addition, Exar's Quality Assur- ance expectations to be placed on this new IC, and
ance department performs an independent set of elec- once these specifications are agreed upon, Exar will
trical tests on randomly selected samples of production proceed with test development.
units, prior to shipment, to assure conformity with
Exar's Acceptable Quality Level (AQL) standards. Test development involves the design and construction
of a test interface circuit, probe card and automatic
EXAR's TEST CAPABILITIES handler hardware as well as writing the software which
allows Exar's test system to perform the desired elec-
Exar can perform two basic types of tests for produc- trical tests. All these elements are then brought togeth-
tion IC's: (1) parametric testing which measures a spe- er under actual production conditions for evaluation
cific parameter value (normally current or voltage) and and system debugging. This process can take from
compares it against pre-established limits; (2) function- four to six weeks to complete, depending on the sophis-
al testing which applies a series of operating conditions
tication and complexity of the test plan under develop-
and compares the circuit under test with a known good
ment. Test development begins concurrently with the
device. These two types of tests can be performed both
start of production wafers (which require approximately
as steady state (dc) or dynamic (ac) measurements.
6 weeks to process).

Exar provides 100% electrical testing of IC chips in wa-

fer form, using automated wafer probe stations, and in
packaged form, using automatic handlers. Exar's test SPECIFICATION AGREEMENT LETTER
facility currently has fifteen independent computer con-
With each new custom IC Exar issues a Specification
trolled test systems, with more being added as we
Agreement Letter. This specification states precisely
grow. Exar's automated test system compliment is
the test conditions, performance levels and environ-
comprised of:
mental requirements which each production IC must
• Teradyne A311 meet before it can leave our factory, and is the docu-
• Teradyne A312 ment upon which acceptability of the IC is judged. It is
• Teradyne A360 issued in duplicate and signed by responsible repre-
• Teradyne J273 sentatives from both companies prior to beginning pro-
• Fairchild 5000C duction. One copy is retained by the customer, the oth-
er is returned to Exar.
Testing is one of the most critical steps in IC produc-
tion. Therefore, to insure efficient and cost effective If, for some reason, changes in the IC's specification
testing of production IC's, it is essential that a prelimi- are required, a new Specification Agreement Letter will
nary test plan be prepared jointly between the cus- be issued by Exar reflecting these changes. No
tomer and Exar at an early stage of the custom devel- change, however, will be put into effect until both com-
opment. This preliminary test plan will lead to the final panies have signed the new agreement. This document

•
detailed test specifications, once the development pro- will then supercede all prior agreements and remain in
totypes are fully evaluated and characterized and the effect until both firms, again agree, a change is re-
circuit is ready to release to production. quired.

9-9
LINEAR SEMI·CUSTOM DESIGN
COMPONENT UTILIZATION LINEAR MASTER DESIGN KIT
The total number of components on the Exar Linear A Linear Master DeSign KIT, containing a wealth of IC
Master-Chips range from 110 on the XR-C100A to 882 design and layout knowledge, is available from Exar for
on the XR-W100. However, the number of these com- $59.00. This design KIT shows a step-by-step approach
ponents that are actually usable depends upon many to convert your existing discrete linear circuits into a
considerations. The first thing that must be evaluated is CUSTOM IC.
the general requirements of the finished circuit. Fac-
tors such as the number of pins that are required, This design manual explains in detail the Bipolar
breakdown· voltage as well as die size limitation im· Technologies employed. Component characteristics are
posed by packaging requirements, determine which of clearly detailed to assist you during your paper design.
the Master-Chips are suitable. This can impose limita· In addition to circuit design and layout examples this
tions on the number of available components. KIT includes Testing, Quality Assurance and Packag-
ing information.

Circuit characteristics also impose limitations upon the Also included in the Master DeSign KIT are breadboard-
number of usable components. For example, a circuit ing components (KIT parts). These KIT parts come from
whose package pin configuration can be chosen freely, the same Bipolar Process (20V, 36V, 75V) that wi" be
that handles small signals, low supply voltages, is in- used to integrate your circuit, thus minimizing any un-
sensitive to dc offset voltages, and whose various cir- foreseen processing risks.
cuit blocks follow one another with a minimum of inter-
connections between blocks, may be able to use over The KIT parts included in the Master Design KIT are
90 % of the components on the selected Master-Chip. for your preliminary survey. After you have selected a
particular Master-Chip for your design, then appropriate
On the other hand, in more complex designs requiring KIT parts will be mailed to you upon receipt of your order.
special layout or design considerations, the component
utilization may be as low as 50%. Examples of such TECHNICAL ASSISTANCE
cases are those where the package pin-outs are prede-
termined, or the choice of component locations on the If any special or unusual circuit design or layout prob-
die may be fixed due to thermal consideration, circuitry lems are encountered in the preparation of your semi-
symmetry or offset requirements. In certain cases the custom IC layout, Exar's technical staff wi" be glad to
series or parallel connection of several resistors to ob- review your design problem and provide technical guid-
tain a predetermined value, or paralleling several tran- ance. In many cases, it is beneficial to call Exar for a
sistors to increase their current handling capability, preliminary discussion of your custom IC needs even
may also limit the total component utilization. before you decide to buy a design kit.

BREADBOARDING
Over 850 custom programs have been completed to
date, using Exar's bipolar Master-chips. Thus, Exar's After a circuit has been deSigned and analyzed on pa-
Engineering department has a great wealth of experi- per, it is time to reduce the theoretical design to a func-
ence concerning the layout techniques utilizing the tioning circuit that wi" duplicate, as closely as possible,
Master-Chips. In many cases, it is advantageous for the the operation of the finished integrated circuit. This is
customer to call Exar for a free consultation regarding the purpose of breadboarding. A great deal of care
the choice of a particular Master-Chip which may be needs to be taken during this phase of IC development.
best suited for his application. Accurate breadboarding wi" not only allow you to gain
an accurate assessment of the performance you can
The bipolar Master-Chips are laid out to provide easy expect from the finished IC, but it wi" also allow you to
routing of metal interconnection paths. In addition, a discover circuit design flaws. A correctly connected,
muitipiicity oj low resistance crossunders are provided nonfunctional breadboard is a very vivid indication that
on the chip to simplify the interconnection layout. something has been overlooked. Changes can be made

9-10
on a breadboard in a couple of minutes with a pair of KIT PARTS
pliers and a hot soldering iron. Changes on an IC are
much more expensive and time consuming. The bread- Since the purpose of breadboarding is to build a circuit
board can be tested over temperature in a temperature that will duplicate, as closely as possible, the perform-
chamber and circuit performance can be measured ance of the finished IC, Exar has included with this de-
with worst' case resistor values. Preliminary test speci- sign kit a generous supply of kit parts. These kit parts
fications can also be readily developed from a properly are the same integrated components that you will find
functioning breadboard. Next to the initial paper de- on the finished IC. They are metalized and brought out
sign, breadboarding is the most important step in IC de- individually so that you can use them to connect your
velopment. circuit.

Generally speaking, the integrated resistor arrays need

only be used in circuits where certain characteristics of
these resistors, such as high frequency response or
temperature coefficients, are critical to circuit perform-
ance. In most cases, standard off-the-shelf carbon film
resistors are entirely adequate for breadboarding.
LINEAR SEMI-CUSTOM DESIGN CYCLE: SIX SIMPLE STEPS
The basic linear semi-custom design program involves only 6 single steps, from the beginning of circuit design to the
completion of monolithic prototypes. The first four of these steps can be done by either the customer in consultation
with Exar or by Exar. The last two are performed by Exar.

Step 1
Circuit design and Customer purchases Exar's Linear IC Design Kit, made up of a comprehensive De-
breadboard using sign Manual and monolithic kit parts. The circuit is designed, breadboarded and its
Linear Design Kit. performance evaluated using these kit parts. The electrical characteristics of the kit
parts Are virtually identical to the component which will be on the finished IC chip.
Thus, this step provides a true simulation of the final IC performance.

Step 2
Circuit layout After the completion of breadboard evaluation, a layout of the circuit on the selected
is prepared Master Chip by following the basic layout rules given in the Design Manual. The lay-
out is done simply by interconnecting appropriate device terminals with pen or pen-
cil lines on oversize drawings of the Master Chips supplied with the kit.

Step 3
Layout review Exar reviews the circuit layout and schematic to check the following:
a) That basic circuit function is feasible
b) No layout rules are violated
c) Circuit layout accurately represents the circuit schematic.

•
NOTE: Exar offers consulting service and design advice during these first three
steps.

Step 4
Exar generates custom Using the completed Master-Chip layout sheet, Exar generates a custom intercon-
interconnection pattern. nection pattern, or metal mask to be applied to pre-fabricated Master-Chip wafers.

Step 5
Exar fabricates customized Exar applies the custom interconnection patterns to pre-fabricated Master-Chip wa-
IC wafers. fers. During this customization process, the hardware and software necessary to
test the prototypes is made ready. After the wafers are customized, each die is test-
ed by an automatic tester.

Step 6
Exar assembles and The customized IC wafers are scribed or cut into individuallC chips. After a visual in-
delivers monolithic spection, several die that tested "good" are assembled in cerdip packages. These
prototypes. packaged devices are then tested again before shipment. Fifty assembled IC's, and
test data for correlation purposes, are sent to the customer in a prototype package
that includes a die photo, device schematic test details and a layout sheet.

9-11
~ FULL CUSTOM DESIGNS ~ THREE STEPS TO SUCCESS

EXAR offers direct full custom designs to its customers. Get EXAR To Work For You
However, recognizing the risks, costs, and longer turnaround
times involved in full custom development. EXAR also provides
full custom conversions. Step 1: Discuss Your Needs With EXAR

Full custom conversion is a two-step approach that provides We are proud of our quick and flexible response to your
the best of both worlds; quick turnaround time with minimum needs. During the conception stage of your project. our highly
risk of semi-custom arrays, and the efficient use of silicon with talented Design Engineers can go through the technical
full custom which invariably means reduced unit costs. options and variations available to you through EXAR. This
is done at absolutely no cost to you.
The first step is to implement customer's design on one
of EXAR's Master-Chips to take advantage of the fast integra- Step 2: Get a Quotation From EXAR
tion times as well as very easy, fast and low risk design iteration
cycle in comparison to full custom. This enables customers To help us get an accurate and complete quotation to you faster,
to design and penetrate their product into the market in a your request for quotation (RFQ) should contain:
short time frame and qualify the product for production
rapidly. In addition, any application or production problems o A block diagram of your application
that may require design iterations can be implemented at a o A schematic at discrete or transistor level
low cost and with a fast turn-around time. This way, all produc- o The circuit specifications
tion oriented problems are fully debugged and the device o Your volume requirements
is production proven in semi-custom form.
The more information you supply us, the sooner we can
The second step, then, would consist of a straightforward full respond. EXAR can also assist you in compiling this information.
custom conversion to minimize the chip size and hence the
unit cost when the device is in full production. This ensures a
risk free and a very smooth transition to shipping cost effective, Step 3: Relax and EnjoyThe Services Offered by EXAR
high volume products.
Depending on your requirements, a project may be started
with EXAR at YOUR desired level of involvement. EXAR engi-
~ STANDARD CELL LIBRARY neering having successfully completed over 1000 user specific
projects (automotive, industrial control. telecom, mode.ms,
EXAR has developed an extensive library of fully characterized computer peripherals, medical and switch capacitor filter
linear standard cells, and is in the process of expanding the applications), has the necessary expertise to be involved in
library continuously. EXAR presently has over 100 different. system design, IC design, layout or integration level. YOUR
fully characterized linear standard cells. CHOICE. In either case, throughout the development process,
a close contact is maintained between EXAR and your staff.
Linear standard cell technique allows customers to design an NO SURPRISES.
entire integrated circuit from base layer up, similar to a full
custom development without suffering from some of its dis- In addition to our extensive engineering expertise in various
advantages. Please contact EXAR for further information on user specific applications, as a standard IC manufacturer,
its Standard Cell library. EXAR brings years of accumulated engineering know-how
and expertise in telecommunications, computer peripherals,
Again, EXAR's state-of-the-art in-house wafer fabrication data communications, including switch capacitor filters and
facility is a key factor in providing highly reliable full custom modems, industrial control, and instrumentation to our
and standard cell products. customers. All this design expertise is available to you. Make
use of our easily acessible wealth of valuable engineering
~ DESIGN MANUALS AND KIT PARTS resources now.

A linear Master-Chip Design Manual is available from EXAR

for $59. This manual shows a step-by-step approach to the EXAR also offers a variety of DIGITAL GATE-arrays. These
design and layout of circuits. Itcovers one of the most com- include state-of-the-art dual metal 311 Si-GATE arrays for
prehensive and useful analog circuit design aids in the industry, high speed applications and metal gate CMOS arrays for high
including extensive device characterization, modelling, pre- voltage applications.
designed circuit examples and circuit building blocks as well
as layout examples. Also contained in this manual are bread-
board kit oarts which will be used to prove the performance
of your ci~cuit. These kit parts come from the same bipolar
process that will be used to integrate your circuit. Additional
kit parts are available at $2.50 each.
9-12
~ SERVICES OFFERED 5. Integration: This service involves generating silicon from
the layout sheet. After the Integration Package is ready, EXAR
Depending on the annual volume requirements of the cus- will take the layout sheet and digitize it. At this stage, EXAR will
tomer and the selectivity criteria, EXAR offers a wide variety check the digitized plots versus transistor level circuit sche-
of Engineering services. These services are briefly matic. After digitization, Design Rule Check (DRC) is performed
outlined below: to eliminate any violations. The final digitized plots are then
used to generate masks (working plates) using automated
1. System Design: This type of design service evolves from techniques.
the conceptual system description and specification. It requires
EXAR to come up with the system design using a block Finally, metallization and passivation (glass or nitride) masking
diagram approach. It requires definition of the functional steps are performed on EXAR's premises to finish fabrication
blocks and system implementation with discrete IC blocks to of the Master-Chip wafers. After the wafer fabrication is
verify the performance, as per the objective specs. Discrete completed, prototypes are built at EXAR's in-house Hi-Rei
IC implementation of each functional block and determination assembly facility.
of the product or circuit specifications required to meet the The prototypes are then fully evaluated and sent to the
system performance concludes the System Design. customer along with a prototype binder which includes all
pertinent information. These prototypes are for electrical
evaluation purposes only.
2. Circuit Design: In this type of service, the system is well-
defined by the customer in block diagrams and at the discrete
6. Wafer Foundry: In addition to all the services mentioned
IC level. EXAR determines the partitioning of the system and
above, EXAR offers wafer foundry services utilizing its
the definition of the product and objective specs. Then the
in-house state-of-the-art wafer fabrication line which includes
transistor level design of the circuit is implemented to meet
all diffusion processes, epi, ion implantation, and a wide
the IC specs. For circuit simulation, EXAR's Master-Chip
variety of deposition processes. Technologies offered cover all
models with SPICE/ ASPEC programs are also available.
bipolar processes, including 12L and high voltage, as well as
metal and silicon gate CMOS. Services are also available for
The circuit is breadboarded using the kit parts of the appro-
partial or full processing of wafers using customer owned
priate Master-Chip. A fully evaluated and finalized breadboard
emulsion or chrome tooling.
is submitted to the customer together with the evaluation
results and performance characteristics for approval.
1> CAE/CAD CAPABILITIES
3. Design Assistance: This service is intended as a joint
effort between EXAR and the customer's engineering staff. For years EXAR has been using CAE/CAD design tools
EXAR's Engineering Staff will work very closely with the extensively for digital gate arrays. Capitalizing on this exper-
customer to define the system and the objective IC specs to tise and implementing technical innovations, we are proud to
achieve the desired performance. EXAR's Engineering Staff be the first to introduce design automation utilizing CAE/CAD
will then provide the customer with a conceptual transistor tools into the area of linear semi-custom arrays. The linear
level paper design of the circuit. It will be the customer's CAE workstation concept. by eliminating the handcrafted
responsibility to breadboard and troubleshoot the circuit. layout methods, takes the black magic out of linear semi-
EXAR will provide "handholding" during this stage, and assist custom design. This new, fully-automated linear; semi-custom
the customer in determining the test specs and layout of the design methodology utilizes CAE/CAD Daisy "Gate Master"
circuit (optional). workstations and dual layer metal linear semi-custom arays.

Auto placement and auto routing workstations drastically

4. Layout: After the transistor level circuit schematic of the reduce the layout and digitizing turnaround times with
breadboard is finalized, the 200X Master-Chip layout sheets added reliability. This built-in "correct by construction concept"
or Electronic Layout Sheets are used to do the interconnect. is attained through on-line layout versus schematic (LVS)
Since the interconnections of the circuit on the Master-Chip check, design rule check (DRC), and electrical rule check
is an intbgral part of the design and can have a significant (ERC) features included in the design automation software.
effect on the performance of the circuit. all critical paths and An additional benefit of design automation is the achievement
matched circuit components must be identified and taken of higher packing density (higher percent utilization) which
into consideration in achieving an optimum layout. This layout enables EXAR to use smaller Master-Chips and to pass the
sheet along with the test specification of the circuit. provided 'cost savings on to our customers.
by the customer; and the pin-out (bonding diagram) form the
integration package.
t> MODELS AVAILABLE

For running simulations, SPICE model parameters (AC/DC)

are available on bipolar (20V, 36V and 75V) and Bi-FET
(36V, ion implant) processes. Contact EXAR for further
information.
9-13
EXAR LINEAR MASTER-CHIPS
The following section profiles the available Exar linear Master·Chips.

INDUSTRY STANDARD (20V) ARRAYS

A·100 B-100 C-100A 0-100 E·100 F-100 G-100 H-100 J-100 L-100 M-100
Transistors
NPN,small 58 69 23 50 48 93 58 73 36 76 137
NPN,100mA 2 2 2 4
NPN,200mA 2 4 2 2 4
NPN, low noise 4
PNP, single collector 18 12 8
PNP, dual collector 16 15 36 18 22 12 22 44
PNP, quad collector 4 8
PNP, venical 4
Schottky Diodes 15 16 6
15 N + Resistors 4 8 15

Base Resistors
2000 16 28 8 15 6 18 19 33 8 27 60
4500 43 44 18 30 41 88 68 87 34 106 188
9000 43 46 20 28 34 68 65 81 30 78 140
1 8KO 29 39 13 29 27 61 44 60 24 53 104
36KO 28 36 12 24 30 61 27 36 20 36 84
Total Base Resistance 214K 266K 94K 178K 206K 433K 266K 356K 159K 348K 712K

Pinch Resistors
30KO 4 6 2 5 9
100KCl 4
60KO 2 8 8 4 10 16
90KO 6
Pads 16 16 14 16 18 24 18 18 18 24 28
Die Size (mils) 73x83 85x85 56x62 80x81 82x82 98x115 90x90 95x80 ROx75 102x85 176x121

HIGH VOLTAGE (75V) BI·FET ARRAYS CELLULAR ARRAY

ARRAY X-100 U-100 V-l00 W-100 CA-100
Transistors Transistors Transistors
NPN, small 30 NPN,small 94 140 192 NPN,small 96
NPN,I00mA Supermatched small NPN's 16 NPN,100mA
NPN.200mA 4 NPN,100mA 2 NPN,200mA
PNP, dual collector 16 NPN,200mA 4 4 NPN, low noise
200 XU 1 J-fET (P-channel) 4 4 8 PNP, large
PNP, dual collector 40 56 60 PNP, dual collector 60
Base Resistors
PNP, (med. venical) 2 4 4 80 LV XU (5V Max)
5000 64
PNP, vertical 8 4 10 to substrate 16
lKO 27
280 N + Resistors 22
2KO 58 Base Resistors 160 N + Resistors 18
5KO 12 2800 40 40 24 200 N + Resistors 20
Total Base Resistance 234K 4500 158 112 100 300 N + Resistors
9000 56 72 100
N + Resistors
laKD 32 64 88 Base Resistors
50 14
36KO 32 56 72 4000 80
100 7 42
Total Base Resistance 305K 443K 559K 8000
200 7 42
2KO
Implant Resistors 24KD 32
Pinch Resistors
lKO 32 Total Base Resistance 226K
lOOK 0 Pinched 3
5KO 16 32 32
30K 0 Pinched 3
10KO 16 32 32 Implant Resistors
Pads 18
20KO 16 32 32 3KO 28
Die Size (mils) 115x95
50KO 16 32 28 9KD 38
Total Implant Resistance 1.36M 2.72M 2.55M 27KO 38
36KD 28
Cross Unders Total Implant Resistors 246M
150XU 9 4
50XU 8 Capacitors
300 LVXU (5V max) 8 Junction Cap
150 LVXU 4 4 (5V diff max 25pf)
MOS Capacitor
Capacitors (Max 10pf)
MOS capacitors 4 4 8 28
Pads
(10pF max)
Die Size (mils) 122x77
Pads 28 28 40
Die Size (mils) 110xl10 146x113 163x133

NOTE: LV-low voltage (5V max. to substrate) - XU-N+ cross under

12LARRAYS
Schottky Bi-Polar Max,Toggle Internal Note
Array-Name Gale Count' Bonding Pads Operating Voltage Ij = Injector Current -
I/O Interlaces Frequency Delay/Gate
XR-2oo 192 24 30 7V 60KHz U.bIlS @ IJ-lpA
XR-300 288 28 34 7V
400 KHz lOOns @ Ij= 1011
XR-400" 256 18 40 7V
XR-500 520 40 42 7V 2 MHz 50ns @lj= IOOIiA

'5 Output 12L gates

"XR-4oo also has PNP, NPN devices and diffused resistors to all -- .. analog and digital functions on the same chip

9-14
EXAR Master-ChipsTM

• I

9-15
XR-A100 Master-ChipTM
Chip Size: 73 x 83 mils NPN Transistors Pinch Resistors
Total Components: 276 Small Signal: 58 30kn: 4
Bonding Pads: 16 High Current: 2 (200 mA) 100kn: 4
Max. Operating Voltage: 20V PNP Transistors: 18 Diffused Resistors
Schottky Diodes: 15 2000.: 16 1.8kn: 29
4500.: 43 3.6kn: 28
9000.: 43
Total Base Resistance: 214kn

D
K"~"'~"
, kl!JlE, E,~~ I
'I~~!f~p~'
.--=-~-~

iii •
I 361( I
~,-
I 45011 _ 900ll.

,eb I. • !o:,_- .~: I

! .
r;t _I~II-
I ~ ,_4SOU_900f)

• c I
' 361(
1- PNP I ·.~n~ 90011.

XR-A100

9-16
XR-B100 Master-ClhipTM
Chip Size: 85 x 85 mils NPN Transistors Pinch Resistors
Total Components: 318 Small Signal: 69 30ko.: 6
Bonding Pads: 16 High Current: None 90ko.: 6
Max. Operating Voltage: 20V Dual PNP Transistors: 12 Diffused Resistors
Schottky Diodes: 16 2000.: 28 1.8ko.: 39
4500.: 44 3.6ko.: 36
9000.: 46
Total Base Resistance: 266ko.

II

XR-B100

9-17
XR-C100A Master-ChipTM
Chip Size: 56 x 62 mils NPN Transistors Pinch Resistors
Total Components: 124 Small Signal: 23 30kO: 2
Bonding Pads: 14 High Current: None Diffused Resistors
Max. Operating Voltage: 20V PNP Transistors: 8 2000: 8 1.8kO: 13
Schottky Diodes: 6 4500: 18 3.6kO: 12
9000: 20
Total Base Resistance: 94kO

~_ -=- -=- -= -=-- -=- ======--=---= - - - - - "II Ir=-=-::~----"-- - - - - - -I

I
I I
I
I
I
I
I
I
1

I
I
I
I

I I

XR-C100A

9-18
Chip Size: 80 x 81 mils NPN Transistors Pinch Resistors
Total Components: 210 Small Signal: 50 60kO: 2
Bonding Pads: 16 Dual PNP Transistors: 16 Diffused Resistors
Max. Operating Voltage: 36V 2000: 15 1.8kO: 29
4500: 30 3.6kO: 24
9000: 28
Total Base Resistance: 178kO

-------- - - - -

.::::::iI v

XR-D100

9-19
XR-E100 Master-ChipTM
Chip Size: 82 x 82 mils NPN Transistors Pinch Resistors
Total Components: 224 Small Signal: 48 30kO: 5
Bonding Pads: 18 Dual PNP Transistors: 15 Diffused Resistors
Max. Operating Voltage: 20V 2000: 6 1.8kO: 27
4500: 41 3.6kO: 30
9000: 34
Total Base Resistance: 206kO

XR-E100

9-20
XR-F100 Master-ChipTM
Chip Size: 98 x 115 mils NPN Transistors Pinch Resistors
Total Components: 462 Small Signal: 93 30kO: 9
Bonding Pads: 24 High Current: 4 Diffused Resistors
Max. Operating Voltage: 20V Dual PNP Transistors: 36 2000: 18 1.8kO: 61
4500: 88 3.6kO: 61
9000: 68
Total Base Resistance: 433kO

II
XR-F100

9-21
XR-G100 Master-ChipTM
Chip Size: 90 x 90 mils NPN Transistors Pinch Resistors
Total Components: 327 Small Signal: 58 60kO: 8
Bonding Pads: 18 High Current: 2 Diffused Resistors
Max. Operating Voltage: 20V PNP Transistors: 18 2000: 19 1.8kO: 44
Schottky Diodes: None 4500: 68 3.6kO: 27
9000: 65
Total Base Resistance: 266kO

- - - -- - -
I _ --I 1
I,.I.,I.}
I I I'~ L~'1>!', 1-<>-<.>-1 I
11i'!I,~'I~'1 ,'!I!'I~'I I
III I 1 I I
'. I ad a,1 , a l a-I'
111-(;-0-1 1-' 1
,a la'I.' ,a 1 ",-I
.'
111- ,~ -I 1- I
111,;la,la,1 I I I
,alia, I
1 1-<>-<>-1 1-' -I
II'I'!I,~'I~'I ,a 1 ",-I
1- .' I
1- - -I 1
111-<>-<>-1 1~<~~<~!C,
I!;I:,;I;,I;,I 1
II i'~ I ,,!'I ~'I I~ I,'!'I~~
1
III. '500 -'000 ,i_o
11
ol '50

XR·G100

9-22
Chip Size: 95 x 80 mils NPN Transistors Pinch Resistors
Total Components: 424 Small Signal: 73 60k!1: 8
Bonding Pads: 18 Medium: 2 Diffused Resistors
Max. Operating Voltage: 20V PNP Transistors 200!1: 33 1.8k!1: 60
Lateral: 22 450!1: 87 3.6k!1: 36
900!1: 81 15!1 (N+): 4
Total Diffused Resistor: 356k!1

•
XR-H100

9-23
XR-J100 Master-ChipTM
Linear, bipolar NPN Transistors Pinch Resistors
Chip Size: 80 x 75 mils Small Signal: 36 60kO: 4
Total Components: 188 Medium: 2 Diffused Resistors
Bonding Pads: 18 Dual PNP Transistors: 12 2000: 8 1.8kO: 24
Max. Operating Voltage: 20V 4500: 34 3.6kO: 20
9000: 30
Total Base Resistance: 159kO

XR-Jl00

9-24
Chip Size: 102 x 85 mils NPN Transistors Pinch Resistors
Total Components: 448 Small Signal: 76 60kO: 10
Bonding Pads: 24 Medium: 2 Diffused Resistors
Max. Operating Voltage: 20V Large: 2 2000: 27 1.8kO: 53
PNP Transistors 4500: 106 3.6kO: 36
Lateral: 22 9000: 78 150 (N+): 8
Quad Collector: 4 Total Base Resistance: 348kO

II
XR-L100

9-25
XR-M100 Master-ChipTM
Chip Size: 176 x 121 mils NPN Transistors Pinch Resistors
Total Components: 840 Small Signal: 137 60kO: 16
Bonding Pads: 28 Low Noise: 4 Diffused Resistors
Max. Operating Voltage: 20V Medium: 4 2000: 60 1.8kO: 104
Large: 4 4500: 188 3.6kO: 84
PNP Transistors 9000:140 150(N+):15
Lateral: 44 Total Base Resistance: 712kO
Quad Collector: 8
Large Vertical: 4

XR-M100

9-26
Transistors Implant Resistors Base Resistors Cross Unders (N +)
Total Components: 577 5kO: 16 2800: 40 150 XU: 9
NPN, small: 94 10kO: 16 4500: 158 150 LVXU: 4
NPN, 100 mA: 2 20kO: 16 9000: 56
Capacitors
J-FET (P-channel): 4 50kO: 16 1.8kO: 32
MOS Capacitors (1 OpF max): 4
PNP, dual collector: 40 Total Implant Resistance: 3.6kO: 32 Pads: 28
PNP, med. vertical: 2 1.36MO Total Base Resistance: 305kO Die Size (mils): 110x110
PNP, vertical: 8

NOTE: LV - low voltage (5V max. to substrate). XU - N + cross under.

cc
~f ~J ~~
0' - A 00 BB 'AA
•• 1 ++,

+
·
-./'-
Hi}
HH
~-
"",,--- ~,3;' ~~\ ~.."., ,+ .~.J:!t-\'
':: !r!f~~'
Ht,J,i~,
c c • \ <t c • C ~ ~ ,e
c.~... e
c ~" • c', ","
ii[H "
1:"\'

':. ~f It " '..

• e E ;".: ~ ~t~ ~~ c

~} it ..
,
C,>i';"'iC
L
§;:.

W'

\"""
• I

'U

• i\ i~
· mt
NiP
__ , ~1
, Q

-- ij
"II"
.,'.,

XR-U100

9-27
XR-V100 Master-ChipTM
Chip Size: 113 x 146 mils NPN Transistors Diffused Resistors Oxide Capacitor: 4 x 10 pF
Total Components: 740 Small Signal: 140 2800: 40 3.6kO: 56
Bonding Pads: 28 Large: 4 4500: 112 1.8kO: 64
Max. Operating Voltage: 36V PNP Transistors 9000: 72
Lateral: 56 Total Resistance: 443kO
Small Vertical: 4 Ion Implant
Medium Vertical: 4 50kO: 32 5kO: 32
JFET Transistors 20kO: 32 10kO: 32
P-Channel: 4 Total Resistors: 2.72 MO
Cross Under Resistors (N +)
50: 8
150: 4
LVXU (5V) 150: 4
LVXU (5V) 300: 8

••••

XR·V100

9-28
Chip Size: 163 x 133 mils NPN Transistors Diffused Resistors Oxide Capacitor: 8 x 10 pF
Total Components: 882 Small Signal: 196 2000: 24 1.8kO: 88
Bonding Pads: 40 Supermatched Small 4500: 100 3.6kO: 72
Max. Operating Voltage: 36V Signal: 16 9000: 100
Large: 4 Total Resistance: 559kO
PNP Transistors Ion Implant
Lateral: 60 50kO: 28 5kO: 32
Small Vertical: 10 20kO: 32 1kO: 32
Large Vertical: 4 10kO: 32
Total Implant Resistors:
2.55 MO
Cross Under Resistors (N +)
50:4

XR-W100

9·29
XR-X100 Master-ChipTM
Chip Size: 115 x 95 mils NPN Transistors Pinch Resistors
Total Components: 293 Small Signal: 30 30kO: 3
Bonding Pads: 18 High Current: 4 100kO: 3
Max. Operating Voltage: 75V PNP Dual Collector Diffused Resistors
Transistors: 46 (N+) 50: 14 1kO: 27
(N+) 100: 7 2kO: 58
(N+) 200: 7 5kO: 12
5000: 64
Total Base Resistance: 234kO

XR-X100

9-30
Chip Size: 119 x 149 mils NPN Transistors: 45 Diffused Resistors
5·0utput 12L Gates: 256 4-Collector PNP 700Q: 200
Bonding Pads: 40 Transistors: 12 2.5kQ: 116
Max. Operating Voltage: 7V Schottky·Bipolar 1/0 5kQ:20
Interfaces: 18 Total Resistance: 530k

..., I::: I::-~u'~ .1:

~LL~j
~-
p " I: L

Q LJ".!
.-
---t
"" ..;.! r" i
n II

~ GJ
~~::

GJ Gm]

f!!] GJ

[!] W
:".:.~:;;~.

W ~

~ GJ
II
GJ [;]
[!;] GJ ~ GJ ~ GJ ~ GJ ~

XR-400 12L

9-31
ELECTRICAL CHARACTERISTICS OF LINEAR MASTER-CHIP COMPONENTS
The following tables list the electrical characteristics of the circuit components available on Exar's linear Master-
Chips. Whenever applicable, the "worst case" tolerances and the parameter distributions are also listed.

WORST CASE
PARAMETERS TYPICAL VALUES a-LIMIT TOLERANCE
Small-Signal NPN Transistors
Current gain (hFE) @ 1 mA,5V 180 - 80-300
Temperature Coefficiency of hFE
- 55°C to 25°C +0.5%/oC - -
25°C to 125°C + 1 %/oC - -
Matching of hFE - 3% 10%
Breakdown voltage (LVCEO)
20-V Master-Chips 23V - 20-30V
36-V Master-Chips 40V - 36-50V
Collector-Base Leakage Current @ 20 V 1 nA - 0.1-50 nA
Cutoff Frequency (fT) @ 5 mA 500 MHz - -
Storage Time (t s) 50 nsec - -
Saturation Resistance (All except D100)
One collector contact 100 Ohms ±50 Ohms 60-160 Ohms
Two collector contacts 50 Ohms ±20 Ohms 30-80 Ohms
Saturation Resistance (D1 00 chip)
One collector contact 300 Ohms ± 100 Ohms 150-480 Ohms
Two collector contacts 150 Ohms ±50 Ohms 75-240 Ohms

High-Current NPN Transistors

Current Gain (hFE)

@ 1 mA,5V 180 - 80-300
@ 100 mA, 5V 100 - 50-200
Temperature Coefficient of hFE
- 55°C to 25°C +0.5%/oC - -
25°C to 125°C + 1 %/oC - -
Matching hFE - 3% 10%
Breakdown Voltage (LVCEO) 23V - 20-35V
COllector-Base Leakage Current @ 20V 20 nA - 1-500 nA
Cutoff Frequency (fT) 100 MHz - -
Storage Time (t s) 200 nsec - -
Saturation Resistance 5 Ohms ±10hm 3-8 Ohms

Lateral PNP Transistors

Current Gain (hFE) @ 100 p.A, 5V 20 - 5-80

Temperature Coefficient of hFE ± 1.0%/oC - -
Matching of hFE - 5% 15%
Breakdown Voltage (LVCEO)
20-V Master Chips 35V - 25V-40V
36-V Master Chips 45V - 36-60V
Collector-Base Leakage Current @ 20V 5 nA - 0.1 to 100 nA
Cutoff Frequency (fT) 5 MHz - -
Storage Time (ts) 500 nsec - -
Saturation Resistance 600 Ohms ± 100 Ohms 300-900 Ohms

TRANSISTORS CONNECTED AS DIODES

(Collector and Base Shorted)

Small NPN
Forward Voltage Drop @ 1 mA, 25°C 0.74V ±200 mV O.68-0.8V
Forward Voltage Matching - 2 mV 6 mV
Forward Voltage Tracking - 5p.V/oC 15p.V/oC
Lateral PNP
Forward Voltage Drop @ 200 p.A, 25°C 0.70V ±200 mV 0.62-0.76V
Forward Voltage Matching - 3 mV 5 mV
Forward Voltage Tracking - 8 p.V/oC 25 p.V/oC

9-32
 WORST CASE
PARAMETERS TYPICAL VALUES a-LIMIT TOLERANCE
NPN Base-Emitter Junctions Used
as Zener Diodes

Small NPN Transistors

Breakdown Voltage @ 100 !LA
20-V Master Chips 6.35V ±0.15V 5.9-6.8V
36-V Master Chips 6.7V ±0.2V 6.0-7.2V
Temperature Coefficient +2.5 mV/oC ±0.3 mV/oC 1.8-3.1 mV/oC

Schottky-Barrier Diodes
(A100/B100/C100 Only)

Forward Voltage Drop @ 10 !LA 0.36V ±0.02V 0.22 to 0.44V

Temperature Coefficient of Forward
Voltage Drop -1.5 mV/oC ±0.1 mV/oC ± 0.3 mV/oC
Reverse Breakdown Voltage 30V - 20-40V
Leakage Current @ 20V 200 nA - 1 nA-1 !LA

Diffused Resistors (All Master-Chips)

Absolute Values - ±10% ±25%

Temperature Coefficients
- 55°C to - 25°C -650 ppm/DC ± 100 ppm -
-25°C to O°C + 150 ppm/DC ±40 ppm -
O°C to 25°C +680 ppm/DC ±40 ppm -
25°C to 75°C + 1040 ppm/DC ±20 ppm -
75°C to 125°C + 1400 ppm/DC ±40 ppm -
Matching Between Resistors
Identical Values - ±0.8% ±2.4%
Non-Identical Values
200-450 - ±1.6% ±4.8%
200-900 - ±1.7% ±5.1%
200-1.8K - ±1.9% ±5.7%
200-3.6K - ±2.0% ±6.0%
450-900 - ±1.5% ±4.5%
450-1.8K - ±1.7% ±5.1%
450-3.6K - ±1.9% ±5.7%
900-1.8K - ±1.5% ±4.5%
900-3.6K - ±1.7% ±5.1%
1.8K-3.6K - ±1.5% ±4.5%

•
Pinch-Resistors

Absolute Value Tolerance ±50% - + 100 % to - 50 %

Matching Between Identical Resistors ±20% - -
Breakdown Voltage 6.4V - -
Temp. Coefficient + 6,000 ppm/DC - 8,000 ppm/DC

9-33
 KIT PARTS
Please Note: Large NPN == 200 ma
Medium NPN == 100 ma
Small NPN == 10 ma
* Absolute maximum ratings

Max
Item Kit Part No. Description Voltage Applicable for M:Jster·Chip
1. XR-A103 Two 200 ma, & 3 20V A-100, 8-100, C-100
Schottky transistors
2. XR-8101 5 small NPNs 20V A-100, 8-100, C-100
3. XR-8202 5 lateral PNPs 20V A-100, 8-100, C-100
single collector

4. XR-F101 5 small NPNs 20V

5. XR-F10S Four200 ma NPNs 20V
6. XR-F206 4 lateral PNPs
dual collector 20V All of these kit parts are useable for
7. XR-J114 7 small NPNs - common base 20V breadboarding the following Chips:
E-100, F-100, G-100, H-100, J-100,
S. XR-J117 3 Wilson current sources 20V L-100, and M-100.
NPNs
9. XR-J215 7 PNPs common base 20V
10. XR-J216 3 Wilson current source 20V
PNPs
11. XR-M111 4 small NPNs 20V
12. XR-M112 2 medium NPNs, 2 large 20V
vertical PNPs, 1 small NPN
13. XR-M210 2 quad collector PNPs 20V

14. XR-0101 5 small NPNs 36V 0-100

15. XR-0206 4 lateral PNPs 36V 0-100
dual collector

16. XR-W101 5 small NPNs 36V U-100, V-100, W-100

17. XR-W10S Four 200 ma NPNs 36V U-100, V-100, W-100
1S. XR-W111 4 small NPNs 36V U-100, V-100, W-100
19. XR-W206 4 lateral PNPs 36V U-100, V-100, W-100
dual collector
20. XR-W213 5 small, 2 large vertical 36V U-100, V-100, W-100
PNPs
21. XR-W421 4 P channel, JFets 36V U-100, V-100, W-100

22. XR-CA111 4 small NPNs 20V CA-100

23. XR-CA11S 2 large NPNs 20V CA-100
2 large PNPs
24. XR-CA206 4 dual collector PNPs 20V CA-100
25. XR-CA101 5 small NPNs 20V CA-100

26. XR-RN1 Resistor network Applicable to all Master-Chips except

U, V, andW100
27. XR-RN2 Resistor network Applicable to all Master-Chips except
U, V, and W1 00

2S. XR-X101 5 small NPNs 75V X-100

29. XR-X10S Four 200 ma NPNs 75V X-100
30. XR-X206 4 lateral PNPs 75V X-100
dual collector

9-34
 EXAR LINEAR KIT PARTS
101 103 108

8-101 A-103 F-108

F-101 W-108
0-101 X-108
W-101
X-101

111 112 114

J-114

•
M-111 M-112
W-111 2 Medium NPNs
2 Large Vertical PNPs
1 Small NPN

117 202 206

9-35
 EXAR LINEAR KIT PARTS
210 213 215

M-210 W-213 J-215

NOTE: 5 Small & 2 Large Vertical PNPs.
Resistance shown Is substrate
resistance between middle and
edge of die.
216 421

J-216 W-421
NOTE: Drain and Source
are Interchangeable.

Resistor Networks
RN1 RN2 RN3

NOTE: All resistors are the same value

9-36
 EXAR LINEAR KIT PARTS

111 118 206

r-------,. r------,

CA-111 CA-118 CA-206

•
CA-101

9-37
12L SEMI-CUSTOM DESIGN
Integrated Injection Logic (12L) technology extends the used with 12L Master-Chips to be generated simultane-
capabilities of semi-custom design to high complexity ously from a customer's pencil layout on the Master-
digital or combined analog/digital systems. Exar has Chip worksheet. This unique mask generation tech-
made this possible by the development of a family of nique, and the three-mask customizing method, are the
12L Master-Chips which combine a large number of 12L heart of Exar's 12L semi-custom program. In this man-
gates and Schottky bipolar transistors on the same ner, one is able to combine low cost, quick turnaround
chip. Similar to its bipolar counterpart, Exar's 12L semi- capabilities of semi-custom designs with the high func-
custom program also utilizes partially fabricated silicon tional density of 12L technology, and still make very effi-
wafers which are then customized by the application of cient use of the chip area.
special mask patterns.
WHEN TO USE DIGITAL SEMI-CUSTOM
Exar's 12L Master-Chips utilize bipolar input/output (I/O)
interface circuitry on the same chip with the high densi- The key application of 12L semi-custom design is to re-
ty 12L logic arrays. Thus, outwardly the 12L semi- place complex blocks of random logic with a Single
custom chip looks and performs exactly as a bipolar LSI monolithic chip. An entire digital subsystem comprised
chip, which can readily interface with TTL level signals. of many SSI or MSI chips, or discrete components, can
In other words, these gate array Master-Chips combine be put on a single 12L Master-Chip. This can provide
the high functional density advantages of 12L technolo- significant cost and space savings and greatly improve
gy with the interface and load drive capability of the bi- system reliability. The availability of bipolar input/output
polar circuitry on the same IC. This feature makes it interface circuitry on the same chip with the high densi-
very convenient to retrofit 12L LSI designs into existing ty 12L logic makes it very convenient to retrofit 12L de-
TTL type logic systems. signs into existing TTL logic systems. Therefore, semi-
custom 12L LSI designs provide cost effective solutions
ACHIEVING HIGH COMPLEXITY for complex custom LSI requirements, even at produc-
tion volumes as low as a few thousand pieces.
Traditionally, the application of semi-custom technology
to complex digital systems has been somewhat limited FEATURES OF 12L TECHNOLOGY
due to one key factor; in order to be economically feasi-
ble, a complex digital LSI circuit must achieve a high High Functional Density: 12L logic gates offer a much
functional density on the chip (high gate count per unit smaller size than their bipolar counterparts. Thus, a
of chip area). This requirement is not compatible with much higher degree of logic complexity or functional
the random interconnection concept which is key to the density can be achieved on a given IC chip.
semi-custom or Master-Chip design technique. Exar's
approach overcomes this limitation, by making use of
Easy to Interconnect: Unique structure and geometry of
121 gates make them ideal for semi-custom design. An
the unique layout and interconnection properties of (2L
entire array of gates can be easily customized and in-
gates, and by extending the customizing steps to mask
terconnected using only three masks without sacrific-
layers. In addition to the metal interconnection pattern,
ing high functional density.
Exar can achieve high packing density and still retain
the quick turnaround features and low cost of semi- Bipolar Compatible Processing: 12L is a direct derivative of
custom. conventional bipolar IC technology. Therefore, one can
combine bipolar devices on the same chip as 12L gates.
Exar's 12L Master-Chips are customized by not one but
This feature has the following key advantages:
three mask layers:
• Input/output section of 12L chips are bipolar. Thus,
1. A custom diffusion pattern to define gate outputs they can readily interface with existing logiC families
and custom underpasses for interconnection. or retrofit into existing systems.
2. A custom contact mask which opens contact win-
dows or activates only those devices actually used • Analog and digital functions can be combined on the
in the design. same chip. Ona of Exai's Master-Chips, the XR-400,
is specifically designed for such an application.
3. A custom metal interconnection mask which inter-
connects all the activated devices. Low Voltage Operation: 12L gates can operate with supply
voltages as low as one volt, and require only a single
FULLY AUTOMATED MASK GENERATION power supply.

Exar has developed a fully automated mask generation Low Current and Low Power Operation: Depending on
technique which allows all three custom mask layers speed requirements, 12L gates can operate with current
9-38
levels in the nanoampere range. This feature, along LOGIC CONVERSION TO 12L GATES
with its low voltage operation makes it ideal for applica-
tions in low power, battery operated systems. Converting conventional logic diagrams from their
NAND/NOR gate equivalents to 12L gates is a simple
Higher Reliability Than MOS: Since 12L gates have the and straightforward procedure. This information is con-
same basic features as bipolar transistors, they are not tained in the 12L Design Manual, which is available as a
subject to electrostatic burn-out problems associated part of Exar's 12L Design Kit. In addition, Exar has de-
with MOS transistors and do not require special han- veloped a large library of 12L logic subblocks corre-
dling precautions. sponding to popular logic functions, such as decoders,
flip-flops and counters, which greatly simplifies this
Wide Operating Temperature: 12L gates are not seriously conversion process.
affected by leakage currents as are their MOS counter-
parts. Thus, they can accommodate the full military
temperature range. DESIGNING WITH 12L MASTER-CHIPS
10,.1,.---y---r---,.--,----,
Exar currently has four 12L Master-Chips in production.
These are the XR-200, XR-300, XR-400 and the XR-500
Master-Chips. The XR-200, XR-300 and the XR-500 are
designed for digital systems. The XR-400 Master-Chip is
intended for systems requiring both analog and digital
functions.
>-
~
All four of these Master-Chips are fabricated with the
...~ ~LsnL
same manufacturing process. They differ only in their
f 10 nll---~,-,--h:-,,--+.:+---+----I
architecture and in the number of components. All of
O.',~ 1.0 PI
, -"', these chips are especially designed for Exar's unique
lnl~_~-~~-~- __~~~ three-mask customization process using fully auto-
I,.W 10,.W l00,.W 1 mW
POWERIGAn mated mask generation techniques.

COMPARISON OF SPEED AND "'OWER CAPABILITIES XR-200, XR-300 and XR-500 MASTER-CHIPS
OF VARIOUS LOGIC FAMILIES
These Master-Chips are primarily designed for applica-
THE BASIC 12L GATE tions requiring only digital signal processing. They con-
tain a large number of multiple output 12L gates along
The 12L logic technology is derived from the basic sin- with Schottky bipolar input/output buffers. Except for
gle input, multiple output inverter circuit shown below. the difference in size, all three chips have the same ar-
The logic functions are performed in a manner similar chitecture shown below. The 12L gates are arranged in
to the conventional open-collector logic. The outputs of array form at the center of the chip and the input/output
various gates are interconnected together in a wired- buffers are located along the periphery of the chip. The
AND configuration. Many sections of the 12L gate share bipolar 110 sections of the chips contain two identical
common semi-conductor regions. For example, the col- sets of resistor arrays located at opposite ends of the
lector of the pnp is the same as the base of the npn, chip which are used for biasing the injectors of the 12L
and the emitter of the npn is the same as the base of gates. The XR-200 contains 192 five-output 12L gates

•
the pnp. This leads to a very compact device structure and 24 110 buffers. The XR-300 contains 288 five-output
which occupies a correspondingly small chip area. As a 12L gates and 28 110 buffers. The XR-500 contains 520
result, the functional density of I2"L gates is comparable five-output 12L gates and 40 110 buffers. A detailed de-
to that of some MOS technologies and is approximately scription of the bipolar input/output interface circuitry is
5 times higher than conventional TTL logic. given further on in the text. I

THE BASIC 12L GATE

(a) Actual Gate (b) Equivalent Circuit (c) Logic Symbol

9-39
 BIPOLAR I/O INTERFACE
INPUT/OUTPUT
INTERFACE

LINEAR BIPOLAR
~--4- COMPONENTS -+----1

INPUT/OUTPUT
INTERFACE
BIPOLAR I/O INTERFACE

BASIC LAYOUT OF XR-200, XR-300 AND XR-500 BASIC LAYOUT OF XR-400 MASTER CHIP
MASTER CHIPS

XR-400 MASTER-CHIP Components on XR 12L Master-Chips

The XR-400 Master-Chip is designed primarily for appli- Quantity
cations requiring the combination of analog and digital
Component Type XR-200 XR-300 XR-400 XR-500
functions on the same chip. Thus, it is made up of both
a linear and a digital section. The digital section of the 5-0utput 12L Gates 192 288 256 520
chip has the same basic architecture as the XR-300. It Schottky-Bipolar
contains 256 five-output 12L gates and 18 Schottky bi- 1/0 Interfaces 24 28 18 40
polar 1/0 interface sections. The linear section of the Max Operating
chip is made up of an array of npn and pnp transistors Voltage 7V 7V 7V 7V
and resistors and is very similar to Exar's bipolar NPN Transistors 0 0 45 0
Master-Chips .. 4-Coilector PNP
Transistors 0 0 12 0
Diffused Resistors
COMPONENT UTILIZATION 700n 0 0 200 0
2.5 K 0 0 116 0
The unique three-mask customizing technique used in 5K 0 0 20 0
Exar's 12L Master-Chips makes them very efficient for Bonding Pads 30 34 40 42
both ease of logic layout and component utilization. Chip Size (mils) 98 x 119 106 x 144 119 x 149 122 x 185
One of the three customizing mask steps is a custom
diffusion step which allows the placement of low resist-
ance crossunders, or underpasses, selectively on the
chip. This technique provides the designer with virtually
two layers of interconnection on the chip and, thus,
greatly simplifies the logic layout and improves the
component utilization efficiency. Normally, in the case
of random combinational logic, one can easily utilize
60% to 80% of the total gates available on a given 12L
Master-Chip. In the case of sequential and repetitive
logic circuits, the gate utilization is normally as high as
80% to 100%.

In the case of the XR-400 Master-Chip, which combines

analog circuit components and digital gates on the
same chip, the three-mask customizing technique is
applicable to the digital section, while the analog sec-
tion of the chip is customized with one mask in the
same way as the linear Master-Chips.

9-40
 THE 12L GATE ARRAY SECTION
--11'---_---' 6~~
I ! .. -"'- 12 LGATES This section of the 12L Master-Chip is made up of logic

j I ~ cells which contain a number of multiple output 12L in-

verters grouped together. The figure below shows a typ-
ical layout of such a cell made up of eight multiple out-
Ii ~
~'N
ADJACENT
CELL
put inverters which share a common set of four injec-
tors. The basic gate cells forming the 12L gate array are
i ~
made up of p-type injectors and p-type gate fingers

i ~~~~
j which serve as the base regions of the 12L gates. The

j
·· ....
..
six dots on each gate area indicate the possible loca-
tions (or sites) for gate inputs or outputs. The particular
· ...
i j
~'- . . . use of these sites as an input or output is determined
by two custom masks. An n-type collector diffusion
mask defines the locations of outputs and a custom
contact mask opens the appropriate input and output
II DOTS INDICATE LocL,,,,, 0 contacts. Finally, a third custom mask is applied to
form the metal interconnections between the gates and
BASIC 8 GATE CELL PRIOR TO CUSTOMIZATION the gate cells. The custom n-type diffusion step, which
determines the locations of gate outputs, is also used
__ • METAL INnACQNNECTIOftil
for forming low resistivity underpasses between the
o - INJECTOIII CONTACT gate cells. The area between each of the gate cells can
o -GATE OUTPUT
accommodate two or three parallel underpasses in the
D -GATElfrWUT

[>----ovv..-<J -UNC'.'A" horizontal or vertical direction. Since the n-type diffu-

'---_----'I L- sion which forms these underpasses is a part of the
customizing step, the location and length of each un-
derpass can be chosen to fit a given interconnection
• • 0,
requirement. This method provides the designer with
virtually all of the advantages and capabilities of multi-
layer interconnection paths on the surface of the chip
INJECTO"
IUS and allows approximately 80 % of the gates on the chip
to be utilized in a typical logic layout.
The custom logiC interconnections can be easily laid
out in pencil on a layout sheet by simply interconnect-
ing the desired gate sites with a pencil line and appro-
priately defining the function of the site as an input, out-
put, injector contact or an underpass. The function of
each of the potential sites is defined by simply drawing
an appropriate symbol on it, such as a circle for an out-
put and a square for an input, as defined in the example
SAMPLE PENCIL LAYOUT ON MASTER CHIP below.
WORKSHEET

METAL
INTERCONNECTION

INJECTOR
BUS
• I

I I I I
SAMPLE LAYOUT OF 8 GATE CELL AFTER
CUSTOMIZING WITH N+ COLLECTOR DIFFUSION,
CONTACT MASK AND METAL INTERCONNECTION
PATTERN

9-41
 BIPOLAR INPUT IOUTPUT INTERFACE SECTION
li=iI
ID~S'
The bipolar input/output interface sections of the 12L
Master-Chips are located along the periphery of the

R7=
500 II ~
[§
BONDING
PAD
01
chips. The component locations in a typical 110 cell are
shown in the adjacent figure. Each 110 cell is designed
to be either an input or an output interface depending

ID~S'
on the choice of the metal interconnection pattern ap-

:';ij C. AS
[@
= 2.5 K
~
I @)
A4 = 2.5 K
02
plied to the cell. Furthermore, two adjacent cells can
be combined together to provide a three-state type out-
put buffer. Some of the basic input and output circuit
configurations available from the 110 interface are
shown below. In the case of a three-state output config-
~---....,
uration, one would also utilize several gates from the
12L logic section to perform the necessary gating func-
tions.

Each input/output interface cell contains one bonding

A2 = 10 K AI = 10 K pad, several resistors of varying values, a clamp diode
to substrate and two npn transistors with optional
A TYPICAL SCHOTTKY-BIPOLAR INPUT 10UTPUT Schottky diode clamps. Each npn transistor is capable
INTERFACE CELL of sinking 5 mA of current with Schottky diode clamps
and 10 mA of current without, at a saturation voltage of
~ O.5V. The breakdown voltage of the bipolar 110 sec-
tion is 7V.

INPUT 10K

5K
20K

10K

FAOM 12L GATES -----I. OUTPUT

(a) Inpul Inlerlace Circuli (b) Oulpul Inlerlace C,rcu,i

10K
15K 10K

DATA INPUT
FAOM 12L --'---<l
GATES OUTPUT

TAI·STATE
ENABLE
CONTAOL

I~I----GATING ADDITIONAL
----~--- ~~~F~~A
TAl-STATE

(c; Tfi-Siili.e Output inicriace Circuit

TYPICAL BIPOLAR INPUT/OUTPUT INTERFACE CIRCUITS AVAILABLE FROM 1/0 INTERFACE CELL

9-42
Cross References & Ordering Information

Telecommunication Circuits

Data Communication Circuits

Computer Peripheral Circuits

Industrial Circuits

Instrumentation Circuits

Interface Circuits

Special Function Circuits

User Specific Linear ICs

Application Notes

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

10
 Section 10 - User Specific Digital ICs - Full Custom/Semi-Custom
Semi-Custom Solutions (Gate Arrays) . . . . . . . . . . . . . . . . . . . . . . . . 10-2
30,000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-3
CM Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-7
Full Custom Solutions (Standard Cells) . . . . . . . . . . . . . . . .. 10-7
A3000 Standard Cell Family . . . . . . . . 10-10
Full Custom Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

•
10-1
SEMI-CUSTOM SOLUTIONS (Gate Arrays)
Designing USICs using semi-custom approach is a well- In the second case, a design engineer may be in the
known way to achieving cost-effective product with a process of designing a completely new system. In this
quick turn-around. A CMOS semi-custom solution for case, the system can be designed in such a way that
USICs can be approached in two ways. it can be easily partitioned into one or more arrays.
Once again, EXAR's custom-engineering department
In one case, a customer may already have a working will be happy to provide assistance in selecting the
system on which it is necessary, for example, to reduce appropriate array along with price and delivery information.
the manufacturing costs by incorporating a CMOS gate- EXAR plans to offer its soft macro library in both a
array to simplify a complex printed circuit board. The PC-like environment and on popular workstations so
task in this case is to determine what portion, if not all, that the schematic-capture can be performed elec-
of this PC board can be incorporated into an array. tronically, thereby eliminating chances of an error and
EXAR otters a very wide range of arrays to accomplish this. expediting the development cycle. Dial-up services will
be available to help perform logic and circuit analYSis
The partitioning of the system and the choice of which using our powerful CAD/CAE tools in-house.
array to use must be carefully considered with cost,
packaging, versatility and testability in mind. EXAR's Also, if a customer so desires, the breadboards can be
custom-engineering department will be happy to assist built using SSI and MSI packages from one of the popu-
a customer in his selection, or perform a design review lar logic families such as 74LXX, 74CXX or 4XXX. These
of the system at no cost and suggest array and partition- logic families are recommmended for breadboarding due
ing alternatives. This design review will include a quota- to their standard nature as well as their universal avail-
tion for the development charges and production pricing ability. EXAR custom-engineering will, once again, be
of the array, as well as an approximation of the develop- happy to assist in translating these into EXAR's soft-
ment time that will be required to build the prototypes. macro library.

A typical semi-custom development flow is shown in

the figure 1. Listed below are the steps to be performed
at each stage.

System Design • Logic Design • Logic Simulation • Layout ~ Integration

D Conceptualization D System Partitioning D Schematic Capture D Auto-Place D PG Tape

D System-Block Diagram D LogiC Design D Logic Simulation D Auto-Route D Working Plates
D Objective Specs D Fault Simulator D Timing Verification D Wafer Processing
D Netlist Generation D DRC/ERC/LVS D Packaging
D Testing

Figure 1, Semi-Custom Development Flow

ADVANTAGES OF A SEMI·CUSTOM SOLUTION:

Lower Product Cost: With greater design integration, Reduced Power Consumption: Reduced capacitive loads
product costs are reduced. and CMOS technology also means the power consump-
tion is significantly lower.
Reduced Chip Count: Standard SSI and MSI parts are
incorporated into a single chip, significantly reducing Smaller Products: Reduced chip count also means less
the chip count. Darts and less board soace. The re!';ult i!'; R nhv!':iCRllv
smaller product which offers the sa-~e s~l~ii~~:·· _.. ,
Improved Reliability: Fewer pins and solder joints im-
prove the reliability. Design Integrity: A User Specific IC provides protection
against improper and unauthorized copying of the final
Improved Speed: Reduced junction and node capaci- product.
tances allows circuits to run at higher clock speeds.

10-2
30,000 SERIES
The XR-30,000 series of silicon-gate CMOS gate-arrays The 30,000 series are implemented using a state-of-the-
has been developed for high speed digital applications, art 3 micron Si-gate CMOS, p-well processing technol-
with clock speeds as high as 25 MHz. ogy. Special features like dual metal layers allow
improved routability and impressive performance gains
The series is composed of six different arrays ranging in both functionality and percentage utilization of the array.
in gate-count from 156 to 3025 gates. The number of
1/0 pins on these arrays range from 22 to 98 and these The arrays use a set of common base layers, so the
are all tri-statable. customization begins with the first contact and metal
mask layers. This allows stocking of the wafers, finished
until just before the first contact mask. Implementation
is geared to provide a short turn-around time.

XR·30,OOO SERIES

ABSOLUTE MAXIMUM RATINGS

ITEM SYMBOL RATING UNIT

Supply Voltage VOO -0.3-6.5 V

Input Voltage Yin -0.3-VOO + 0.3 V
Output Voltage Vout -0.3 - VOO + 0.3 V
Storage Temperature Tstg -55-150 °C

OPERATING RANGE

ITEM SYMBOL RATING UNIT

Supply Voltage VOO 5 ± 0.25 V

Input Voltage Yin O-VOO V
Output Voltage Vout O-VOO V
Operating Temperature Topr 0-75 °C

I/O CHARACTERISTICS: VDO = 5V; TA = 25°C

RATING

•
ITEM SYMBOL MIN TYP MAX UNIT CONDITION

Input Voltage V,L 0.8 V

VIH 2.0 V

Output Voltage VOL 0.8 V 10L = 2mA

VOH 2.4 V 10H = O.4mA*

AC CHARACTERISTICS: (TA = 25°C)

RATING
ITEM SYMBOL TYP UNIT CONDITION

Average Propagation tpd 3.0 ns Inverter with fanout

Oelay = 2;VOO + 5V

Toggle Frequency ft 25 MHz VOO = 5V

10-3
Si-GATE CMOS ARRAYS (DUAL METAL)

GATE TOTAL MAX

ARRAY NAME COUNT* I/O TRISTABLE BONDING OPERATING TOGGLE INTERNAL

30015 156 22 22 24
30030 288 30 30 32
30045 460 38 38 40 5V 35 MHz <3nS
30080 793 50 50 52
30155 1548 70 70 72
30300 3025 98 98 100

* 2 input NAND equivalent

Basic Cell Input/Output Cell

~~~~~--~~~-
.......,.......I""I""I'''II'''II''''II..........,P''rP'~ -
- - -- - - -
- - - - - - - -
-- - - -
~--~~~~~~
........'I"T"II"''I''T''II'''rrri
"*'"&.LI...I..I..&................u..&.ILL&J - - - - - - - - - - _ _ ~.LLL.LLLU.Af

~PlrTrTTTT'1'TT'1rTT'1rTT'1 - - - - - - - - - - - - rTTl'TT'l'TT"l'T'I'i
.......................&.LI...............~ - - - - - - - - - - - - ............................u.&f

""""rT"I"'rT"I"'l""I""I'T'Y"Y"II"'II""IIT9"'I - - - - - - - - - - - - rTTl'TT'l'TT"rT"I'i
tA-A"................................'-L&.L&.U- - - - - - - - - - - - L&.L.LLL.LLL&..L1.4

.......,.......I""I""I'''II'''II''''II..........,P''rP'~ - - - - - - - - - - - - rrTTTTl'TT'rnoi
tA-A"................................'-L&.L&.U - - - - - - - - - - - - L&.L.LLL.LLL&..L1.4

.......,.......I""I""I'''II'''II''''II..........,P''rP'~ - - - - - - - - - - - - rrTTTTl'TT'rrri
........................................'-L&.L&.U - - - - - - - - - - - - L&.L.LLL.LLL&..L1.4

Figure 2. Chip Layout

10-4
 ----~~-----+--VDD

INPUT

GND
Figure 3. Basic 2-input Gate Cell Figure 4. Input Buffer

--------~--VDD - - - - - -.......- V DO

OUTPUT

---------4~- GND ------~~- GND

Figure 5. Output Buffer Figure 6. Tristate Output Buffer

• I

*Input and output buffers have other possible configurations also.

10-5
XR-30,OOO SOFT-MACROS LIST

FUNCTION

Single Inverter
Double Inverter
Single Buffer
Double Buffer
AND Buffer Non-Inverting Input Buffer
OR Buffer Inverting TTL Compatible Input Buffer
Input Protection
Inverting Input Buffer
2 Input NOR Gate Schmitt-Trigger Non-Inverting Input Buffer
3 Input NOR Gate Schmitt-Trigger Non-Inverting Input Buffer
4 Input NOR Gate With Pull-Up Resistance
6 Input NOR Gate
B Input NOR Gate Inverting Output Buffer
9 Input NOR Gate Non-Inverting Output Buffer
12 Input NOR Gate Tri-State Output Buffer
16 Input NOR Gate Inverting Open Drain Output Buffer
NAND Output Buffer

2 Input NAND Gate Bidirectional Tri-State I/O Buffer

3 Input NAND Gate Unused 1/0 Cell
4 Input NAND Gate Inverting Bidirectional Buffer
61nput NAND Gate Bidirectional Buffer with Tri-State Output
Blnput NAND Gate
9 Input NAND Gate Schmitt-Trigger
12 Input NAND Gate 2 to 1 Multiplexer
161nput NAND Gate Open Drain N Channel Transistor
Open Drain P Channel Transistor
2-AND-NOR
2-0R-NAND
2-2-AND-NOR
2-2-0R-NAND

Exclusive OR Gate
Exclusive OR Buffer
Exclusive NOR Gate
Exclusive NOR Buffer

RS Latch (NAND)
RS Latch (NOR}
R1 R2S1 S2 Latch (NAND)
R1 R2S1 S2 Latch (NOR)

D Latch
D Latch with Reset
D Latch with Set and Reset
D Flip-Flop
D Flip-Flop with Reset
D Flip-Flop with Set and Reset

10-6
eM SERIES
EXAR's CM series of digital gate-arrays is composed The CM series is implemented using an 8 micron metal-
of four members: CMA, CMS, CMC and CMD - these gate CMOS, p-well processing technology. Implementa-
range in size from 140 to 460 gates. tion is geared to provide a short turn-around time.

Each of the CM series array is completely prefabricated As compared to 30,000 series, CM series can operate
just like the 30,000 series, except for the final fabrication over a much wide supply range, VDD = 3-15V. The
step of device interconnection. clock speeds though, because of the larger geometries,
are slower than the XR-30,000 series.
XR·CM SERIES

ABSOLUTE MAXIMUM RATINGS

ITEM SYMBOL RATING UNIT

Supply Voltage VDD -0.3to +15.0 V

Input Voltage Yin -0.3to VDD + 0.5 Vdc V
Output Voltage Vout -0.3toVDD + 0.5Vdc V
Storage Temperature Tstg -55 -150 °c

OPERATING RANGE

ITEM SYMBOL RATING UNIT

Supply Voltage VDD 3-15 V

Input Voltage Yin O-VDD V
Output Voltage Vout O-VOD V
Operating Temperature Topr 0-75 °C

1/0 CHARACTERISTICS: VDD = 5V; TA = 25°C

RATING
ITEM SYMBOL MIN TYP MAX UNIT CONDITION

Output Voltage VOL 0 0.1 V VDD = 5.0V

(Low Level) 0 0.1 V VDD = 10.0V
0 0.1 V VDD = 15.0V

Output Voltage VOH 4.95 5.0 V VDD = 5.0V

•
(High Level) 9.95 10.0 V VOO = 10.0V
14.95 15.0 V VDD = 15.0V

AC CHARACTERISTICS: (TA = 25°C)

I

RATING
ITEM SYMBOL TYP UNIT CONDITION

Average Propagation tpd 21 ns VOD = 5.0

Delay (Inverter with 11 ns VDD = 10.0
fanout = 2) 8 ns VOO = 15.0

Toggle Frequency ft 2.5 MHz VOD = 5.0

5.0 Mhz VOO = 10.0
8.0 MHz VDD = 15.0
10·7
METAL GATE CMOS ARRAYS

ARRAY NAME GATECOUNT* TOTAL I/O TRISTABLE I/O BONDING PADS

CMA 140 29 15 32
CMS 202 34 16 38
CMC 270 40 22 44
CMD 416 46 30 50

* 2 input NAND equivalent

10-8
 FULL-CUSTOM SOLUTIONS (Standard Cells)
Full-custom solutions offer the ultimate in design flexibil-
ity and cost reductions. This approach allows single-chip
integrations of diverse function types that cannot be
realized using any other approach. In addition, the die-
size and hence the unit-cost for the final product
is considerably lower than a semi-custom design.
However, since the development cost and lead times
are longer, this approach is better suited for large pro-
duction quantities or designs that cannot be realized
using the semi-custom approach.

A typical full-custom development flow is shown in Figure

1. Listed below are the steps to be performed at each
stage. It should be noted that in full-custom develop-
ments, working plates (masks) must be generated for
all layers, unlike semi-custom, where only the inter-
connect layers need to be generated.

System DeSign • Logic DeSign • Logic Simulation • Layout • Integration

o Conceptualization 0 System Partitioning 0 Schematic Capture 0 Auto-Place o PG Tape
o System-Block Diagram 0 Logic Design 0 Logic Simulation 0 Auto-Route o Working Plates*
o Objective Specs 0 Fault Simulator 0 Timing Verification o Wafer Processing
o Netlist Generation ODRC/ERC/LVS o Packaging
o Testing
Figure 1. Full-Custom Development Flow *(AII Levels)

•
ADVANTAGES OF FULL-CUSTOM SOLUTION:
(Standard Cell Approach)
Flexibility in Design: Layout customized from bottom Lower Product Cost: For higher production quantities the
layer up. product cost in even lower than the gate arrays, this in
spite of the higher NRE charges.
Improved Turnaround: Predefined cells and auto place-
ment/routing. Macro Cells: The ultimate in the flexibility and integration
is the ability to incorporate proven macro functions in
Higher Success Rate: Sophisticated CAD software the standard cells.
eliminates missing or incorrect connection. Guaranteed
functionality of the predefined cells.

10-9
A3000 STANDARD CELLS
A3000 STANDARD·CELLS

EXAR has developed an extensive library of full-charac- The dual-metal layer capability gives a significant perfor-
terized standard cells. Standard cell technique allows mance advantage by reducing RC delays on signal lines.
the design of an entire integrated circuit from base layer In addition, smaller die-size also gives the customer a
up, similar to a hand-crafted full-custom development reduced unit cost.
without suffering from some of its severe disadvantages.
The standard cell library is undergoing continual expan-
The design can be fully simulated on EXAR's in-house sion and upgrade. Further enhancements under devel-
VAX system. Placement, routing and timing verification opment include analog functions, a micro-controller
is performed using state-of-the-art CAO/CAE tools. macro-cell, EEPROM cells and many additional digital
functions.

A3000 SERIES
ABSOLUTE MAXIMUM RATINGS = TA = 25°C
ITEM SYMBOL RATING UNIT

Supply Voltage VOO -0.3 -6.5 V

Input Voltage Vin -0.3 - VOO + 0.3 V
Output Voltage Vout -0.3 - VOO + 0.3 V
Operating Temperature Topr -20 -75 °C
Storage Temperature Tstg -55-150 °C

OPERATING RANGE

ITEM SYMBOL RATING UNIT

Supply Voltage VOO 5 ±0.25 V

Input Voltage Vin O-VOO V
Output Voltage Vout O-VOO V
Operating Temperature Topr 0-75 °C

1/0 CHARACTERISTICS: VDD = 5V; TA = 25°C

RATING
ITEM SYMBOL MIN TYP MAX UNIT CONDITION

Input Voltage VIL 0.8 V

VIH 2.0 V

Output Voltage VOL 0.8 V IOL = 2mA

VOH 2.4 V IOH = O.4mA*

10-10
A3000 STANDARD-CELLS LIST

1. 2 Input AND - 2 Input OR - Invert 29. Latch with Reset and Set
2. 2 Input AND 30. Left End Cell
3. 3 Input AND 31. 2 Input MUX
4. 4 Input AND 32. 2 Input NAND, One Input Inverted
5. 5 Input AND 33. NAND Set-Reset Latch
6. Bidirectional Buffer with Pad 34. 2 Input NAND
7. Buffered Enable Transmission Gate 35. 3 Input NAND
8. Schmitt-Trigger Buffer 36. 4 Input NAND
9. Tri-State Buffer 37. 5 Input NAND
10. Tri-State Buffer with Inverted Enable 38. 2 Input NOR, One Input Inverted
11. Clock Buffer 39. NOR Set-Reset Latch
12. Clock with Reset Flip-Flop 40. 2 Input NOR
13. D Flip-Flop with Reset 41. 3 Input NOR
14. D Flip-Flop with Reset and Set 42. 4 Input NOR
15. D Flip-Flop with Set 43. Output Buffer with Pad
16. D Flip-Flop 44. Output Buffer with Test Pad
17. 2 Input Exclusive OR 45. Output Buffer with Test Pad
18. 2 Input Exclusive NOR 46. 2 Input AND - 2 Input OR - Invert
19. Input Buffer, Input Normally Low 47. 2 Input OR
20. Schmitt-Trigger Input Buffer 48. 3 Input OR
21. Input Buffer with Pad 49. 4 Input OR
22. Tri-State Inverter 50. Right End Cell
23. Tri-State Inverter with Inverted Enable 51. T Flip-Flop with Reset
24. Inverter 52. Vertical Route Through
25. Inverting Clock Buffer 53. VDD Pad
26. Inverted Enable Transmission Gate 54. VSS Pad
27. Latch 55. Op Amp
28. Latch with Reset

II
I

10-11
FULL-CUSTOM CONVERSIONS (Two Step Approach)
Recognizing the risk, cost and longer turn-around times
involved in a full-custom development, EXAR also offers
full-custom conversion to its customers.

USing this approach, the design is first implemented on

one of EXAR's numerous arrays to bring the product to
market in a short time-frame and qualify for production.
In addition, any design iterations, if required, can be
implemented at a low cost.

The second step then consists of a straightforward full-

custom conversion to minimize the chip size and unit
cost when the device is in full production. This ensures
a risk free and smooth transition to shipping cost-effec-
tive, high volume products.

Full-custom conversion thus is a two-step approach that

provides the best of both worlds: quick turn-around time
(with minimum risk) of gate-arrays and the silicon effi-
ciency of full-custom solution (standard-cell approach)
with lower unit cost.

10-12
 Cross References & Ordering Information

Telecommunication Circuits
1 0 . . . -_ _ _ _ _ _ II1II
aData
. . Communication
- -_ Circuits _ __ II1II
~C_o_m_p_u_t_er__Pe_r_ip_h_e_r_al_C_i_rc_u_it_s________________~11111
aIndustrial
. . - -_ Circuits _ __ II1II
1IIIII
~ln_s_t_ru_m__en_t_a_ti_o_n_C_i_rc_u_it_s_____________________
Interface Circuits II1II
~----------------------------
1IIIII
~s_p_e_c_ia_I_F_u_n_ct_io_n__C_ir_c_u_it_s____________________
~u_s_e_r_s_p_e_ci_fi_c_L_in_e_a_r_lc_s_____________________ 1IIIII
User Specific Digital ICs

Quality Assurance & Reliability

Packaging Information

Authorized Sales Representatives & Distributors

11
 Section 11 - Application Notes
Applications Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . · 11-2
AN-01 Stable FSK Modem Featuring the XR-2207, XR-2206 and XR-2211 · 11-7
AN-02 XR-C240 Monolithic PCM Repeater . . . . . . . . . . . . . . . . .11-13
AN-03 Active Filter Design with IC Op Amps . . . . . . . . . . . . . . · 11-20
AN-04 XR-C277 Low Voltage PCM Repeater IC . . . . . . . . . . . . . · 11-28
AN-05 Three Stage FSK Modem Design using XR-2207 and XR-2211 · 11-35
AN-06 Precision PLL System using the XR-2207 and XR-2208 · 11-41
AN-07 Single Chip Frequency Synthesizer Employing the XR-2240 · 11-45
AN-08 Dual Tone Decoding with XR-567 and XR-2567 . . . . . . . . . · 11-47
AN-09 Sinusoidal Output from XR-215 Monolithic PLL Circuit · 11-50
AN-10 XR-C262 High Performance PCM Repeater IC . . . . . . . . . . · 11-53
AN-11 A Universal Sine Wave Converter using the XR-2208 and XR-2111 · 11-61
AN-12 Designing High Frequency Phase-Locked Loop Carrier Detector Circuits · 11-65
AN-12 Frequency Selective AM Detection using Monolithic Phase-Locked Loops · 11-68
AN-14 High Quality Function Generator System with the XR-2206 .. · 11-72
AN-15 An Electric Music Synthesizer using the XR-2207 and XR-2240 · 11-76
AN-16 Semi-Custom LSI Design with 12L Gate Arrays . . . . · 11-78
AN-17 XR-C409 Monolithic 12L Test Circuit . . . . . . . . . . . . . . . · 11-84
AN-18 Designing Wide-Tracking Phase-Locked Loop Systems . . . . . · 11-88
AN-19 Clock Recovery System . . . . . . . . . . . . . . . . . . . . . . · 11-92
AN-20 Building a Complete FSK Modem using XR-2211 and XR-2206 · 11-95
AN-21 Precision Narrow-Band Tone Decoder . . . . . . . . . . . . . . · 11-98
AN-22 XR-210, XR-215, XR-S200 Phase-Locked Loops . . . . . . . . . 11-101
AN-23 High Performance Frequency-to-Voltage Converter using the XR-2211 11-110
AN-24 Digitally Programmable Phase-Locked Loop ...... . 11-112
AN-25 Full Duplex 1200 BPS/300 BPS Modem System 11-115
AN-26 High Speed FSK Modem Design . . . . . . . . . . . . . . 11-119
AN-27 High Frequency TTL Compatible Output from the XR-215
Monolithic PLL Circuit . . . . . . . . . . . . . . . . . . . . . . 11-125
AN-28 XR-212AS Modem System . . . . . . . . . . . . . . . . 11-128
AN-29 XR-212ACS Performance Testing . . . . . . . . . . . . . 11-132
AN-30 Speakerphone Design using XR-T6420-1 and XR-T6421 11-134
AN-31 PCM Line Interface using XR-T5680 . . . . . . . . 11-138

•
AN-32 PCM Short Haul Line Interface using XR-T5681 .. 11-143
Implement Bell T1 C PCM Repeater using Just Two ICs
by M. Kursat Kimyacioglu, EXAR Corp., article reprint 11-148

11-1
Applications Guide
Exar's line of monolithic IC products cover a wide range
of applications. This Applications Guide is intended as
B
a brief selection guide for the IC user, to assist him in
finding the Exar product most suited to his application. Bar-Graph Display XR-2276, XR-2277,
XR-2278, XR-2279
Battery Charger Timing XR-2242, XR-2243
The application categories, or classes, are listed in al·
Battery Operated Instruments
phabetical order, dictionary style, to allow the user to 10' (Low-Power)
cate the product he needs at a glance. In certain appli· Timing XR-L555, XR-L556,
cations, two of Exar's products used in combination XR-2243
may be necessary to perform the complete function. In Tone Detection XR-L567
such a case, these products are grouped together as a Bit-Pattern Generation XR-2240
pair. For example, to make a complete FSK modem may
require the XR-2206 Modulator and the XR-2211 Decod·
er. Thus, in the Applications Guide shown below, both of
these products will be grouped under the Modem cate·
c
gory as XR-2206/XR-2211.
Carrier Detection (See AM and
In many of the applications, more than one product Tone Detection)
High-Frequency (> 1 MHz) XR-215/XR-2228
type is recommended. In such cases, the user can Low-Frequency « 1 MHz) XR-567 A, XR-2211,
choose the device best suited to his specific applica' XR-L567
tion by either consulting with Exar's Applications de· Low-Power XR-L567
partment, or by reviewing the electrical specifications Carrier-Tone Transceiver XR-2567
of the individual devices involved. Clock Generation (See Oscillators)
Low-Frequency « 1 MHz) XR-555, XR-2209,
XR-2242
Low-Power XR-L555, XR-L556,
*ADVANCED INFORMATION XR-2243
High-Frequency XR-205
Phase Locked XR-215, XR-2212,
A XR-2213
Clock Extraction
Phase Locked XR-210, XR-215,
Active Filters XR-084, XR-094,
XR-2212, XR-2213
XR-096, XR-346,
XR-3403, XR-4202 PCM Signal Clock XR-C262, XR-C277
Acoustical Couplers (See Modems) XR-2206, XR-2207, Clock Pattern Generation XR-2240
XR-2211 Clock Synchronization
AID Conversion (Pulse Counting Type) XR-2240 High-Frequency (> 1 MHz) XR-210, XR-215
Low-Frequency « 1 MHz) XR-2212, XR-2213
Amplitude Detection
Commandor (Speech/Data) XR-2216
Phase-Locked AM Detection XR-215/XR-2228,
XR-2212/XR-2228 Current-to-Frequency Converter XR-2206, XR-2207,
Synchronous AM Detection XR-S200, XR-2208, XR-2209
XR-2228 Current Drive XR-2247, XR-2247A
Amplitude Level Detection XR-2276, XR-2277,
XR-2278, XR-2279
Amplitude Modulated Oscillator XR-205, XR-2206
Crystal Controlled AM Oscillator XR-S200, XR-205 D
Amplitude Modulation XR-2206, XR-2208,
XR-2228, XR-13600 Darlington Arrays
Analog Computation (High-Current, High-Voltage) XR-2200, XR-2201,
Analog MultiplicationlDivision XR-2208, XR-2228 XR-2202, XR-2203,
Analog Square/Square-Root OperationXR-2208 XR-2204, XR-2001,
Analog·To-Frequency Conversion XR-2209, XR-4151 XR-2002, XR-2003,
Analog Sample-Hold XR-13600/XR-082 XR-2004, XR-2011,
Analog Semi-Custom DeSign XR-A100, XR-B100, XR-2012, XR-2013,
(Master Chips) XR-C100, XR-D100, XR-2014
XR-F100, XR-G100, Data Synchronization
XR-X100 High-Frequency (> 1 MHz) XR-210, XR-215
ApplianCe Timing XR .. 555, XR·55G, Low-Frequency « 1 MHz) XR-2212, XR-2213
XR-558, XR-559, DC/DC Converter (See XR-1524, XR-2524,
XR-2240, XR-2242, Switching Regulators) XR-3524, XR-1525A,
XR-2243 XR-1527A,
Audio Amplifier/Preamp XR-5532, XR-5534 XR-2525A,
Audio Level Detector XR-2276, XR-2279 XR-3525A,
Automatic Gain Control (AGC) XR-2208, XR-2216, XR-2527A,
XR-2228, XR-13600 XR-3527A

11-2
Detector High-Frequency (> 1 MHz) XA-215
FM XA-215, XA-2122 Low-Frequency « 1 MHz) XA-2212, XA-4151,
FSK XA-210, XA-2211, XA-2213
XA-14412, XA-2122 Frequency Division XA-320, XA-555,
Tone XA-567, XA-L567, XA-2240, XA-2242,
XA-2211, XA-2567, XA-2243
PSK XA-2122, XA-2123 Frequency Doubling XA-2208, XA-2228
Amplitude Level XA-2276, XA-2279 FM Detection
Amplitude Modulation XA-2208 High-Frequency (> 1 MHz) XA-215
Differential Multiplier XA-2228 Low-Frequency « 1 MHz) XA-215, XA-2212,
Digital Sample/Hold XA-2240 XA-2213
Digital Semi-Custom Design {l2L, FM Generation
CMOS Gate Arrays) High-Frequency (> 1 MHz) XA-S200, XA-205
Complete Digital Design {l2L) XA-200, XA-300, Low-Frequency « 1 MHz) XA-2206, XA-2207,
XA-500 XA-2209, XA-8038
Complete Digital Design (CMOS) CMA, CMB, CMC, Frequency Multiplication (Synthesis)
CMD High-Frequency (> 1 MHz) XA-S200, XA-215
Combined Analog/Digital Design XA-400 Low-Frequency « 1 MHz) XA-2212, XA-2213
Display Driver Frequency Translation
Fluorescent XA-2271, XA-2272, High-Frequency (> 1 MHz) XA-215/XA-2228
XA-6118, XA-6128 Low-Frequency « 1 MHz) XA-2212/XA-2228
Bar-Graph XA-2276, XA-2277, FrequencyNoltage (FN) Converter
XA-2278, XA-2279 Wideband XA-4151
Plasma Displays XA-2284, XA-2288 Narrow-Band XA-2212, XA-2213
Division (Analog) XA-2208 FSK Detection (Decoding)
Division (Frequency) XA-2240 High-Frequency (> 1 MHz) XA-210
Dual Operational Amplifiers Low-Frequency « 1 MHz) XA-2211, XA-14412,
Dual-741 Type XA-1458, XA-4558, FSK Generation (Encoding)
XA-4739 High-Frequency (> 1 MHz) XA-210
Low-Noise XA-5532, XA-5533 Low-Frequency « 1 MHz) XA-2206, XA-2207,
Bipolar FET XA-082, XA-083 XA-14412, XA-2121
Transconductance XA-13600 Sinusoidal Output XA-2206, XA-14412,
Dual Oscillator XA-556, XA-2556, XA-2121
XA-2567 Multiple Frequency Levels XA-2207
Low-Power XA-L556 FSK Modem (Modulator/ XA-2211/XR-2206
Dual Tone Detector XR-2567 Demodulator) XR-2211/XR-2207,
XR-14412,
XR-2121/XR-2122

Electronic Gain Control XR-2208, XR-2216, G

XR-2228, XR-13600
Expandor (SpeechfData) XR-2216 Gate Arrays (See XR-200, XR-300,
Digital Semi-Custom) XR-400, XR-500
CMA, CMB, CMC,
F CMD
Generator (See XR-205, XR-2206,
Function Generators) XR-8038
Filters Ground-Sensing Op Amps XR-3403
Active Filters XR-084, XR-094, Gyrator Design XR-094, XR-346,
XR-346, XA-3403, XR-3403, XA-4202,
XR-4202 XR-13600
Tracking Filters (Phase Locked) XR-S200, XR-215,
XR-2212
Switched Capacitor XR-2120, XR-2103
Floppy Disk H
Read Amplifier XR-3470A, XR-3470B
Write Amplifier
Fluorescent Display Driver
Medium Voltage (:s 50V)
High-Voltage (>50V)
Bar-Graph Display
XR-2247, XR-2247A

XR-2271, XA-2272
XR-6118, XR-6128
XA-2276, XR-2277,
XR-2278, XR-2279
Hammer Driver (See High-
Current Drivers)

High-Voltage Driver
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-6118, XR-6128,
XA-2284, XR-2288
II
I

Frequency Detection (See

Tone Detection)
High-Frequency (> 1 MHz) XA-215/XR-2228
Low-Frequency « 1 MHz) XA-567, XR-2211,
XR-2213
Multiple Frequency XR-2567 Indicator, Amplitude (See
Frequency Discriminator (See AM Detector, Level Detector) XA-2208, XA-2228,
FN Converter) XR-2276, XR-2279

11-3
Indicator, Frequency (See XR-215, XR-2212, XR-4136, XR-4212,
Frequency Detector) XR-4151 XR-4741
Intercom XR-2206/XR-2211, Programmable Quad Op Amp XR-094, XR-095,
XR-2567 XR-096, XR-346,
Interval Timing XR-555, XR-L555, XR-4202
XR-556, XR-L556, Ground Sensing Quad Op Amp XR-3403
XR-558, XR-559 Ultra Low-Noise Op Amp XR-5532, XR-5333,
XR-5534
Bipolar FET Op Amps
Dual Bipolar FET XR-082, XR-083
L Quad Bipolar FET XR-084
Programmable Bipolar FET XR-094, XR-095,
LED Driver XR-2200, XR-2201, XR-096
XR-2202, XR-2203, Operational Transconductance
XR-2204 Amplifier (OTA) XR-13600
Linear-Ramp Generation XR-320, XR-2207 Oscillators (See Function Generators)
Linear-Sweep Oscillator XR-2206, XR-2207, High-Frequency Oscillator XR-205, XR-210,
XR-2209 (>1 MHz) XR-215
Line Compandor XR-2216 Low-Frequency Oscillator XR-2206, XR-2207,
Line Driver (RS-232C Spec) XR-1488 «1 MHz) XR-2209, XR-8038,
Line Receiver (RS-232C Spec) XR-1489A XR-8038A
Long Delay Generation XR-2242, XR-2243 High-Current Output Oscillator XR-567
Low-Power Oscillator XR-L555 Low-Cost Oscillator XR-555, XR-L555
Low-Power PLL XR-L567 Low-Power Oscillator (Single) XR-L555, XR-L567
Low-Power Timer XR-L555, XR-L556, Low-Power Oscillator XR-L556, XR-2243
XR-2243 Dual Oscillator XR-558, XR-559
Low-Voltage Timer/Oscillator XR-L555, XR-L556, Sinusoidal Output XR-205, XR-2206,
XR-2243 XR-8038
FSK Keyed Oscillator XR-2206, XR-2207
Oscillator with Quadrature Outputs XR-2212

M
P
Micropower Circuits (See Low-Power)
Micropower Oscillator XR-L555, XR-L556 PCM Repeater (See Regenerator) XR-C240, XR-C262,
Micropower Tone Decoder (PLL) XR-L567 XR-C277
Micropower Timer XR-L555, XR-L556, Phase-Comparator (Phase-Detector) XR-2208, XR-2228
XR-2243 Phase-Locked Loop
Missing Pulse Detection XR-320, XR-555, High-Frequency (> 1 MHz) XR-S200, XR-210,
. XR-L555
XR-215
Modem Filter Design XR-346, XR-3403, Low-Frequency « 1 MHz) XR-567, XR-L567,
XR-4202, XR-2120, XR-2567, XR-2211,
XR-2103 XR-2212, XR-2213
Modem (Frequency-Shift Keyed) XR-210, XR-2206, Ultra-Stable XR-2211, XR-2212
XR-2207, XR-2211, FM Detector XR-215, XR-2212
XR-14412, FSK Detector XR-210, XR-2211
XR-21211XR-2122 Tone Detector XR-567A, XR-L567,
(Phase-Shift Keyed) XR-2121/XR-2122 XR-2567
XR-2123 Low-Power XR-L567
Modulators (See Multipliers) AM Detector XR-215/XR-2228,
Amplitude Modulator XR-205, XR-2206 XR-2212/XR-2228
FSK Modulator XR-2206, XR-2207, Stero Decoder XR-1310
XR-2121 Plasma Display Driver XR-2284, XR-2288
Frequency Modulator XR-205, XR-2206, Power Supply Supervision XR-1543
XR-2209 Power-On-Reset XR-320, XR-555,
PSK Modulator XR-2121 *, XR-2123 XR-L555
Phase Modulator XR-2212 Precision Oscillator XR-2206, XR-2209,
Motor-Speed Control XR-2208, XR-2212, XR-8038A
XR-2213 Precision PLL XR-2212, XR-2213
Multi-Function PLL XR-S200 Process Controller XR-2206/XR-2211,
Multiplier, Analog XR-2208, XR-2228 XR-2240, XR-4151
Programmable Op Amp (See
Op Amps)
0 Quad Bipolar XR-346, XR-346-2,
XR-4202
Quad Bipolar FET XR-094, XR-095,
Operational Amplifiers XR-096
Single Op Amp XR-5534 Programmable Oscillator XR-2206, XR-2207
Dual Op Amp XR-082, XR-083, Programmable Timer XR-2240
XR-1458, XR-4558, PSK Generator (Bipolar-phase XR-205, XR-2206,
XR-4739 and Quad-phase XR-2228, XR-2121 ,
Quad Op Amp XR-084, XR-3403, XR-2123

11-4
Pulse Blanking XR-556, XR-2556 Low-Frequency « 1 MHz) XR-2212, XR-2213
Pulse-Code Modulation (PCM) XR-C240, XR-C262, Simultaneous AM/FM Detection XR-215/XR-2228,
Regenerator XR-C277 XR-2212/XR-2228
Pulse Counting XR-2240 Simultaneous AM/FM Generation XR-205, XR-2206
Pulse Generation XR-320, XR-555, Sine Wave Converter XR-2212/XR-2228
XR-L555, XR-556 Sine Wave Generator XR-205, XR-2206,
Pulse-Position Modulation (PPM) XR-320 XR-8038, XR-8038A
Pulse-Proportioned Servo Controller XR-2264, XR-2265, Solenoid Driver (See XR-2200, XR-2201,
XR-2266 Relay Driver) XR-2202, XR-2203,
Pulse Shaping XR-555, XR-556, XR-2204
XR-558, XR-559 Speech Compandor XR-2216
Pulse Stretching XR-320, XR-555, Square-Root Extraction XR-2208
XR-556 Squaring (Analog) XR-2208, XR-2228
Pulse-Width Modulation (PWM) XR-320, XR-555 Stable PLL XR-2211, XR-2212
Pulse-Width Modulating Regulator XR-1524, XR-2524, Stereo Demodulator (Decoder) XR-1310
XR-3524, XR-1525A, Suppressed Carrier AM Generator XR-205, XR-2206,
XR-2525A, XR-2208, XR-2228
XR-3525A, Sweep Generation (See XR-320, XR-2207
XR-1527A, Saw-Tooth Generation)
XR-2527A, Switching Regulators XR-1524, XR-2524,
XR-3527A XR-3524, XR-1525A,
XR-2525A, XR-3525A,
XR-1527 A, XR-2527 A,
Q XR-3527 A, XR-2230,
XR-494, XR-495
Synchronization (Clock Frequency) XR-215, XR-2212
Quadrature AM Detector XR-2208, XR-2228 Synchronous AM Detection XR-215/XR-2228,
Quadrature-Output Oscillator XR-2212 XR-2212/XR-2228

R T

Radio-Controlled Servo Driver XR-2264, XR-2265, Telecommunication Circuits

XR-2266 PCM Repeater (T1-type) XR-C240, XR-C262,
Radio-FM I.F. Demodulation XR-215 XR-C277
-AM I.F. Detection XR-2228 Speech Compandor XR-2216
Relay Driver (See XR-2200, XR-2201, Tone Decoder (PLL-type) XR-567, XR-L567,
Hammer Driver) XR-2202, XR-2203, XR-2211, XR-2567
XR-2204 Tone Encoder XR-2206, XR-2207
Remote-Control Timer/Sequencer XR-L555, XR-L556, Timing Circuits (Timers)
XR-2240 General Purpose Timers - Single XR-320, XR-555
Remote-Control Transceiver XR-567 A, XR-L567, General Purpose Timers - Dual XR-556, XR-2556
XR-2567 General Purpose Timers - Quad XR-558, XR-559
Reset Controller (See XR-L555, XR-L556 Low-Power Timers XR-L555, XR-L556,
Power-On Reset) XR-2243
Long Delay Timer XR-2242, XR-2243
Programmable Timer XR-2240
S Tone Decoder (PLL-type)
General Purpose - Single XR-567A
General Purpose - Dual XR-2567
Sample/Hold (See Bipolar XR-082, XR-084 Precision XR-2211, XR-2213
FET Op Amps) Low-Power XR-L567
Saw-Tooth Generator XR-320, XR-2207 Tone Encoder XR-2206, XR-2207
Semi-Custom Design XR-A100, XR-B100, Tracking Filter
Linear Master-Chips XR-C100, XR-D100, High-Frequency (> 1 MHz) XR-S200, XR-215
XR-E100, XR-F100, Low-Frequency « 1 MHz) XR-2212, XR-2213
XR-G100, XR-H100, Tracking Regulator XR-1468, XR-4194,

•
XR-L100, XR-M100, XR-4195
XR-U100, XR-V100, Transceiver (Wireless Intercom) XR-2567
XR-W100, XR-X100 Triangle-to-Sine Wave Converter XR-2208, XR-2228
Digital (12L) Master-Chips XR-200, XR-300, Triangle Wave Oscillator XR-2206, XR-2207,
XR-400, XR-500 XR-2209, XR-8038
Digital (CMOS) Master-Chips CMA, CMB, CMC, TV Sound Detection XR-215
CMD
Sequential Timing XR-566, XR-L566,
XR-588, XR-559
Sequential Tone Decoding XR-567 A, XR-L567
U
XR-2567
Servo ControlierlDriver XR-2264, XR-2266 Ultra Low-Frequency Oscillator XR-2242, XR-2243
Signal Conditioning Ultrasonic Remote Control XR-567, XR-2211,
High-Frequency (> 1 MHz) XR-S200, XR-215, XR-2567
XR-2212 Universal Sine Wave Converter XR-2212/XR-2228

11-5
 VOltage-to-Frequency (V/F) XR-2209, XR-4151
v Conversion

Voltage-Controlled Amplifier XR-2208, XR-2228, W

XR-13600
Voltage-Controlled Oscillator (VCO) Waveform Generator (See Oscillators)
High-Frequency (> 1 MHz) XR-S200, XR-205 High-Frequency (> 1 MHz) XR-205
Low-Frequency ( < 1 MHz) XR-2206, XR-2207, Low-Frequency « 1 MHz) XR-2206, XR-2209,
XR-2209, XR-S038A XR-S03S, XR-S03SA
Ultra-Stable XR-2206, XR-2207, Waveform Shaping/Modulation XR-2208, XR-222S
XR-2209 Wideband Discriminator (FM)
Sinusoidal Output XR-2206, XR-S03S, High-Frequency (> 1 MHz) XR-S200, XR-215
XR-S03SA Low-Frequency « 1 MHz) XR-2212, XR-4151
Wide Linear Sweep XR-2207, XR-2209 Wireless Intercom XR-215, XR-567A,
VOltage-to-Current Conversion XR-13600 XR-2212

11-6
 AN·01

Stable FSK Modems featuring

the XR·2207, XR·2206 and XR·2211
INTRODUCTION The circuit connection for the XR-2206 FSK Generator
is shown in Figure 1. The data input is applied to Pin 9.
Frequency-shift keying (FSK) is the most commonly A high-level signal selects the frequency (1/R6C3) Hz; a
used method for transmitting digital data over telecom- low level signal selects the frequency (1!R7C3) Hz, (re-
munications links. In order to use FSK, a modulator! sistors in ohms and capacitors in farads). For optimum
demodulator (modem) is needed to translate digital 1's stability, R6 and R7 should be within the range of 10 kO
and O's into their respective frequencies and back to 100 kO. The voltage applied to Pin 9 should be select-
again. This application note describes the design of a ed to fall between ground and V +.
modem using state-of-the-art Exar devices specifically
intended for modem application. Note: Over and under voltage may damage the device.

The devices featured in this application note are the Potentiometers, Ra and R9, should be adjusted for mini-
XR-2206 and XR-2207 FSK Modulators, and the mum total harmonic distortion. In applications where
XR-2211 FSK demodulator with carrier detect capabili- minimal distortion is unnecessary, Pins 15 and 16 may
ty. Because of the superior frequency stability of these be left open-circuited and Ra may be replaced by a
devices (typically 20 ppm!oq, a properly designed mo- fixed 2000 resistor.
dem will be virtually free of the temperature and
voltage-dependent drift problems associated with many
other designs. In addition, the demodulator perform-
ance is independent of incoming signal strength varia- 5.1K

tion over a 60 dB dynamic range. Because bias volt-

ages are generated internally, the external parts count
is much lower than in most other designs. The modem
designs shown in this application note can be used with
mark and space frequencies, anywhere from several
Hz to 100 kHz.

PRINCIPLES OF OPERATION + 12Y C>--1f--------i

THE XR-2206 FSK MODULATOR

FEATURES

Typically 20 ppm!OC Temperature Stability

Choice of 0.5% THD Sine Wave, Triangle,
or Square Wave Output
Phase-Continuous FSK Output
Inputs are TIL and CMOS Compatible

•
R6B
Low-Power Supply Sensitivity (0.01 %) Y+

Low-Power Supply Sensitivity (0.01 %/V)

Split or Single Supply Operation
Low External Parts Count Figure 1. The XR-2206 Sinusoidal FSK Generator.
The XR-2206 is ideal for FSK applications requiring the
spectral purity of a sinusoidal output waveform. It offers In applications where a triangular output waveform is
TIL and CMOS compatibility, excellent frequency stabil- satisfactory, Pins 13 through 16 may be left open-
ity, and ease of application. The XR-2206 can typically circuited.
provide a 3-volt p-p sine wave output. Total harmonic
distortion can be trimmed to 0.5 %. If left untrimmed, it The output impedance at Pin 2 is about 6000, with ac
is approximately 2.5 %. coupling normally being used.

11-7
AN·01
THE XR-2207 FSK MODULATOR +12V

FEATURES
RL
S.lK 4.7K
Typically 20 ppm/oC Temperature Stability
Phase-Continuous FSK Output
Provides Both Triangle and Square Wave Outputs
Operates Single-Channel or Two-Channel Multiplex
Inputs are TIL and CMOS Compatible
Split- or Single-Power Supply Operation
Low-Power Supply Sensitivity (0.15 % IV)
Low External Parts Count

The XR-2207 is a stable FSK generator which is de-

signed for those applications where only a triangle or
square wave output is required. It is capable of either
single-channel or two-channel multiplex operation, and
can be used easily with either split- or single-power Figure 2. The XR-2207 FSK Modulator Single-Supply
supplies. Operation.
+6V
Figure 2 shows the XR-2207 using a single-supply and
Figure 3 shows split-supply operation. When used as an
FSK modulator, Pin 8 and 9 provide the digital inputs.
When the 2207 is used with a split-supply, the threshold
,...,.,~"'----p,..,,-~~~ NI/M F~K
at these pins is approximately + 2 volts, which is a level IUUL OUTPUT
that is compatible with both TIL and CMOS logic forms.
When used with a single-supply, the threshold is near
mid-supply and is CMOS compatible. Table 1 shows
how to select the timing resistors, R1 through R4, to de- DATA INPUT

termine the output frequency based on the logic levels L--_~

...",.-~ ENABLE/DISABLE OR
CHANNEL SELECT
applied to Pin 8 and 9. For optimum stability, the values
of R1 and R3 should be selected to fall between 10 kO
and 100 kO.

With Pin 8 grounded, Pin 9 serves as the data input. A Figure 3. The XR-2207 FSK Modulator Split-Supply Operation.
high-level signal applied to Pin 8 will disable the oscilla-
tor. When used in this manner, Pin 8 of the XR-2207
serves as the channel select input. For two-channel Table 1.
multiplex operation, Pin 4 and 5 should be connected XR-2207 FSK Input Control Logic
as shown by the dotted lines. (For single channel opera-
tion, Pin 4 and 5 should be left open-circuited.)
Logic Level Active
Timing Output
The XR-2207 provides two outputs: a square wave at Pin 8 Pin 9 Resistor Frequency
Pin 13 and a triangle wave at Pin 14. (For safe opera-
tion, current into Pin 13 should be limited to 20 mA.)
When used with a split-supply, the triangle wave peak- L L Pin 6 -1-
to-peak amplitude is equal to V - and the dc level is Co R1
near ground. Direct coupling is usually used. With a _1_ + _1_
single-supply, the peak-to-peak amplitude is approxi- L H Pins 6 and 7
Co R1 Co R2
mately equal to one-halflV +, the dc level is approxi-
mately at mid-supply, and ac coupling is usually neces- 1
H L Pin 5
sary. In either case, the output impedance is typically Co R3
100 and is internally protected against short circuits.
H H Pin 4 and 5 _1_ + _1_
The square wave output has an npn open-collector con- -
figuration. When connected as shown in Figure 2 and 3,
this output voltage will swing between V + and the volt- Units: Resistors - Ohms; Capacitors - Farads;
age at Pin 12. Frequency - Hz

11-8
 AN·01
Tho XR·2211 FSK DEMODULATOR

FEATURES The XR-2211 has three npn open-collector outputs,

each of which is capable of sinking up to 5 mA. Pin 7 is
Typically 20 ppm/DC Temperature Stability the FSK data output, Pin 5 is the Q lock-detect output
Simultaneous FSK and Carrier-Detect Output which goes low when a carrier is detected, and Pin 6 is
Outputs are TTL and CMOS Compatible the Q lock-detect output which goes high when lock is
Wide Dynamic Range (2 mV to 3V rms) detected. If Pin 6 and 7 are wired together, the output
Split or Single Supply Operation signal from these terminals will provide data when FSK
Low-Power Supply Sensitivity (O.05%N) is applied, and will be LOW when no carrier is present.
Low External Parts Count
If the lock-detect feature is not required, Pins 3, 5 and 6
may be left open-circuited.
The XR-2211 is an FSK demodulator which operates on
the phase-locked loop principle. Its performance is vir-
tually independent of input signal strength variations,
over the range of 2 mV to 3V rms.

Figure 4 shows the circuit connection for the XR-2211.

The center frequency is determined by fa = (lIC1 R4)
Hz, where capacitance is in farads and resistance is in
ohms. Calculation for fa should fall mid-way between
the mark and space frequencies.

The tracking range (± .::1f) is the range of frequencies

over which the phase-locked loop can retain lock with a
swept input signal. This range is determined by the for-
mula: .::1f = (R4fO/R5) Hz . .::1f should be made equal to,
or slightly less than, the difference between the mark
and space frequencies. For optimum stability, choose Figure 4: The XR·2211 FSK Demodulator with Carrier
an R4 between 10 kO and 100 kO. Detect

The capture range (± .::1fc) is the range of frequencies

over which the phase-locked loop can acquire lock. It is VpO l..-- Lock R a n g e - - - - J
always less than the tracking range. The capture range I I
is limited by C2, which, in conjunction with R5, forms :--~1~-~14
the loop filter time constant. In most modem applica-
tions, .::1fc = (80%-99%).::11.
2 VREF

r--~L~: I

The loop-damping factor m determines the amount of

1-;----:1----
I I

I I VREF
overshoot, undershoot, or ringing present in the phase- I ~~-------
locked loop's response to ~ step change in frequency. it I

is determined by r = 114 C1/C2. For most modem ap-

I I
...j.. - - 1- -
plications, choose r ::= 1/2.
%VREF- - -

!
IS
I
'0

•
The FSK output filter time constant (TF) removes chat-
ter from the FSK output. The formula is: TF = RFCF
Normally calculate TF to be approximately equal to [0.3/
(baud rate)] seconds.

The lock-detect filter capacitor (CD) removes chatter XR·2211 TRACKING CHARACTERISTICS
from the lock-detect output. With RD = 510 kO, the
minimum value of CD can be determined by: CD(JLf) ::= As seen above, the XR-2211 produces at its phase de-
16/capture range in Hz. tector output a voltage VPD, which has a peak to peak
value equal to about VREF for a frequency swing from
fM (mark) to FS (space). The DC level VpD will be about
Note: Excessive values of CD will unnecessarily slow
the lock-detect response time. VREF (V2'+ - .65).

11·9
AN·01
CIRCUIT DESIGN DESIGN EXAMPLES
Table 2 shows recommended component values for the I. Design a modem to handle a 10 kilobaud data rate, using
three most commonly used FSK bands. In many in- the minimum necessary bandwidth.
stances, system constraints dictate the use of some
non-standard FSK bands. The XR-2206/XR-2207/XR- A. Frequency Calculation
2211 combination is suitable for any range of frequen- Because we want to use the minimum possible
cies from several Hertz to 100 kiloHertz. bandwidth (lowest possible upper frequency) we
will use a 55:100 frequency ratio. The frequency
Here are several guidelines to use when calculating difference, or 45% of the upper frequency, will
non-standard frequencies: be 83 % of 10,000. We therefore chose an upper
frequency:
• For maximum baud rate, choose the highest upper
frequency that is consistent with the system band- 83 x 10,000 = 18.444 kHz "" 18.5 kHz.
width. 45
• The lower frequency must be at least 55 % of the up- and the lower frequency:
per frequency (less than a 2:1 ratio).
0.55 x 18.5 kHz = 10.175 kHz.
• For minimum demodulated output pulse-width jitter,
select an FSK band whose mark and space frequen- B. Component Selection
cies are both high, compared to the baud rate. (Le., 1. For the XR-2207 FSK modulator, set Rl "" 30
for a 300 baud channel, mark and space frequencies kO. Now, select a value of Co to generate
of 2025 Hz and 2225 Hz would result in significantly 10.175 kHz with Rr
less pulse-width jitter than 300 Hz and 550 Hz).
10.175 kHz = 1/(C o x 30,000); Co = 3300pF.
• For any given pair of mark and space frequencies,
there is a limit to the baud rate that can be achieved. To choose R2:
When maximum spacing between the mark and
space frequencies is used (where the ratio is close to 18.500 khz - 10.175 kHz = 8.325 kHz =
2:1) the relationship l/CoR2; R2 = 36 kO.

mark-space frequency difference (Hz) A good choice would be to use 10 kO potentiom-

---'-----'---=--------'---'- > 83 % eters for R1A and R2A, and to set Rl B = 24 kO
maximum data rate (baud) -
and R2B = 30 kO.
should be observed.
2. For the XR-2206, we can make R7 equal to
For narrower spacing, the minimum ratio should be Rl, and C3 equal to Co above. To determine
about 67%. R6:

The values shown in Table 2 may be scaled proportion- 18.5 kHz = 1/R6C3; R6 = 16 kO
ately for mark and space frequencies, maximum baud
rate, and (inversely) capacitor value. It is best to retain Use at 10 kO potentiometer for R6A and set
(approximately) the resistor values shown. R6B = 13 kO.

Table 2.
Recommended Component Values lor Typical FSK Bands

FSK Band XR·2207 XR·220S XR·2211

Baud R1A R1B R2A R2B

Rate
'L IH RaA RaB R4A R4B Co RSA RSB R7A R7B Ca R4A R4B R5 Cl C2 CF CD

300 1070 1270 10 20 100 100 .039 10 18 10 20 .039 10 18 100 .039 .01 .005 .05
300 2025 2225 10 18 150 160 .022 10 16 10 18 .022 10 18 200 .022 .0047 .005 .05
1200 1200 2200 20 30 20 36 .022 10 16 20 30 .022 10 18 30 .027 .0033 .0022 .01

Units: Frequency - Hz; Resistors - kO; Capacitors - JLF

11-10
 3. For the XR-2211 demodulator, we need to
AN·01
III. Design a 2 channel multiplex FSK modulator to operate at
first determine R4 and C1. First, fo = (fL + the following pairs of mark and space frequencies: 600 Hz
fH)/2 = (10.175 + 18.500)/2 = 14.338 kHz. and 900 Hz, and 1400 and 1700 Hz (each of these chan-
If we make R4 = 25 kO, then 1/(C1 x 25,000) nels could handle about 400 baud).
= 14,338; C1 = 2790 pF ::::: 2700 pF. With
that value of C1, the precise value of R4 is For this task, we will use the XR-2207. The only real
now 25.8 kO. Select R4B = 18 kO and use a consideration here is that, if pOSSible, we want to
10 kO for R4A keep the following resistances all between 10 kO
and 100 kO: R1, R1/R2, R3 and R3/R4. The ratio be-
tween the maximum and minimum frequencies is
C. Frequency Component Selection
less than 3:1, so we should have no trouble meeting
1. To calculate R5, we first need our .:lf, which is
this criterion. If we set our maximum frequency with
18,500 - 10.175, or 8.325 kHz:
an R of about 20 kO, we have: 1700 = 1/
8325 = (25,800 x 14,338)/R5 (Co x 20,000); Co = 0.029 Ilf which is approxi-
R5 = 44.4 kO :::::47 kO. mately equal to 0.033 pof.

Calculating R1 using 600 Hz and 0.033 Ilf, we get

2. To determine C2 use = 1/2 = 1/4r C1/C2.
R1 = 50,5 kO. We can use R1 B = 47 kO and R1A =
Then, C2 = 1/4C1; C2 = 670 pF:
10 kO. For R2, we get 101 ko. Use R2B = 91 kO and
3. To select CF, we use TF = [0.3/(baud rate)] R2A = 20 kO. To determine R3, use: 1400 Hz = 11
seconds: R3Co, which gives us R3 = 21.6 kO. Use R3B = 18
kO and R3A = 5 kO. R4 must generate a 300 Hz
TF = 0.3/10,000 = 30 Ilsec. shift in frequency, the same as R2. Therefore, set
R4 equal to R2·
with V+
SINEWAVE
RL
RF = 100 kO, CF = 300 pF OUTPUT
"\J't O---+-----".---=~21 4.7K

D. Lock Range Selection saUAREWAVE

To select CD, let us start with the actual lock S.IK
l.!.!}-:=::-----4--o
FSK OUT

range:
DATA INP:S-"
1..4_ _J.ij-'--=-------O'2
.:If = R4fo/R5 Hz = 7870 Hz

If we assume a capture range of 80 %: 10K

.:lfC = 6296 Hz

therefore, our total capture range of ± .:lfC is

12,592 Hz. Our minimum value for CD is (16/
FSK IN 0----1
12,592) Ilf or 0.0013 Ilf.

E. Completed Circuit Example

See Figure 5. S.IK

II. Design a 3 kilobaud modem to operate with low output jit-

ter. The bandwidth available is 13 kHz.

For this modem, we can take the values from two

for the 300 baud modem operating at 1070 Hz and
R~ Optional Vpp Output Adjus, •

:: :~':!;I~I~~JUII } 'or .5·1. THO

'C ,
1270 Hz, multiply our baud rate and mark and R. x } 2.5". THO
space frequencies by ten, and divide all capacitor R.200n

values on the table by ten. Resistor values should Figure 5: Full Duplex FSK Modem Using XR-2206 and
be left as they are. XR-2211. (See Table 2 for Component Values.)

11-11
AN·01
Adjustment Procedure
The only adjustments that are required with any of the the lock range. There are several ways that fo can
circuits in this application note are those for frequency be monitored:
fine tuning. Although these adjustments are fairly sim-
ple and straightforward, there are a couple of recom- 1. Short Pin 2 to Pin 10 and measure fo at Pin 3
mendations that should be followed. with CD disconnect;

The XR-2207: Always adjust the lower frequency first 2. Open RS and monitor Pin 13 or 14 with a high-
with R1 B or R3B and a low level on Pin 9. Then with impedance probe; or
a high level on Pin 9, adjust the high frequency us-
ing R2B or R4B. The second adjustment affects on- 3. Remove the resistor between Pin 7 and 8, and
ly the high-frequency, whereas the first adjustment find the input frequency at which the FSK out-
affects both the low- and the high-frequencies. put changes state.

The XR-2206: The upper and lower frequency adjust- Note: Do NOT adjust the center frequency of the XR-2211
ments are independent, and the sequence is not by monitoring the timing capacitor frequency with every-
important. thing connected and no Input signal applied.
The XR-2211: With the input open-circuited, the loop- For further information regarding the use of the XR-
phase detector output voltage is essentially unde- 2207, XR-2206 and XR-2211 refer to the individual prod-
fined and VCO frequency may be anywhere within uct data sheets.

11-12
 AN-02

XR·C240 Monolithic PCM Repeater

INTRODUCTION

The XR-C240 is a monolithic repeater circuit for Pulse- SIGNAL FLOW -

Code Modulated (PCM) telephone systems. It is de-

I
signed to operate as a regenerative repeater at 1.544
Mega bits per second (Mbps) data rates on T-1 type
PCM lines. The device is packaged in hermetic 16-pin
II
DIP package and is designed to operate over a temper-
ature range of - 40°C to + 85°C. It contains all the ba-
sic functional blocks of a regenerative repeater system
including Automatic Line Build-out (ALBO) and equali-
zation, and is insensitive to reflections caused by cable

~II lie
discontinuities. Compared to conventional repeater de-
signs using discrete components, the XR-C240 mono-
lithic repeater IC offers greatly improved reliability and
performance and provides significant savings in power _ SIGNAL FLOW
consumption and system cost.
Figure 1. Block Diagram of a Bi-directional Digital
THE T-1 REPEATER SYSTEM: Repeater System.

The T-1 Repeater Line is designed to provide a trans-

mission capability for 24 two-way voice frequency sig-
nals which are transmitted digitally using a Pulse-Code The XR-C240 monolithic IC replaces about 90% of the
Modulation (PCM) technique. The system operates at a electronic components and circuitry within the "digital
data rate of 1.544 Mbps, with bipolar data pulses. It can repeater" sections of Figure 1. Thus, a bi-directional re-
operate on either pulp- or polyethylene-insulated paired peater system would require two XR-C240 ICs, one for
cable that is either pole mounted or buried. Operation is each direction of information flow.
possible with a variety of wire gauges, provided that the
total cable loss at 772 kHz is less than 36 dB. Thus, the Figure 2 shows the functional block diagram of one of
system can operate satisfactorily on nearly all paired the digital repeater sections, along with the external
cables which are used for voice frequency trunk cir- zener regulator. The basic system architecture shown
cuits. in the figure is the same as that utilized in the design of
the XR-C240 monolithic IC.
The transmission system is designed to operate with
both directions of transmission within the same cable
sheath. The system performance is limited primarily by
near-end crosstalk produced by other systems operat-
ing within the same cable sheath. In order to insure that

f('M
BIPOLAR
the probability of a bit error is less than 10- 6, the max-

•
imum allowable repeater spacing, when used with 22-
gauge pulp cable, is approximately 6000 feet.

The details of the T-1 type PCM systems are well cov-
ered in the literature listed in References 1 through 5.

Figure 1 shows the block diagram of a bi-directional

PCM repeater system consisting of two identical digital
regenerator or repeater sections, one for each direction
of transmission. These repeaters share a common
power supply. The dc power is simplexed over the
paired cable and is extracted at each repeater by Figure 2. Functional Block Diagram of a Digital PCM
means of a series zener diode regulator. Repeater Section.

11-13
AN·02
In terms of the functional blocks shown in Figure 2, the The supply currents IA and IB drawn from the two sup-
basic operation of the repeater can be briefly explained ply voltages applied to the chip are specified to be with-
as follows: in the following limits:

The bipolar signal, after traversing through a dispersive, a. Current from 8.2V supply voltage, IA
noisy medium is applied to a linear amplifier and auto-
matic equalizer. It is the function of this circuit to pro- 1.1mA ~ IA ~ 2.5mA
vide the necessary amount of gain and phase equaliza-
tion and, in addition, to band limit the signal in order to b. Current from 4.3V supply voltage, IB:
optimize the performance of the repeater for near-end
crosstalk produced by other systems operating within 6mA ~ IB ~ 11mA
the same cable sheath.
The external components necessary for proper opera-
tion of the circuit are shown in Figure 5, in terms of the
The output signals of the preamplifier which are bal-
anced and of opposite phases are applied to the clock
extraction circuit and also to the pulse regenerator. The
signals applied to the clock extraction circuit are recti-
fied and then applied to a high-Q resonant circuit. This
resonant circuit extracts a 1.544 MHz frequency com-
ponent from the applied signal. The extracted signal is
first amplified and then used to control the time at
which the output signals of the preamplifier are sam-
pled and also to control the width of the regenerated
pulse.

It is the function of the pulse regenerator to perform the

sampling and threshold operations and to regenerate
the appropriate pulse. The regenerated pulse is in turn
applied to a discrete switch which is used to drive the
next section of the paired cable.

REFERENCES ON PCM REPEATERS:

1. Mayo, J. S., "A Bipolar Repeater for Pulse Code Sig-
nals," B.S.T.J., Vol. 41, January, 1962, pp. 25-97.
2. Aaron, M. R., "PCM Transmission in the Exchange
Plant," B.S.T.J., Vol. 41, January, 1962, pp. 99-143. Figure 3. Package Diagram of XR-C240 Monolithic
3. Davis, C. G., "An Experimental Pulse Code Modula- PCM Repeater.
tion System for Short-Haul Trunks," B.S.T.J., Vol. 41,
January, 1962, pp. 1-25.
4. Fultz, K. E., and Penick, D. B., "The T-1 Carrier Sys- V++
tem," B.S.T.J., Vol. 44, September, 1965, pp. 1405-
1452. +
10 + IA
5. Tarbox, R. A, "A Regenerative Repeater Utilizing Hy- 3.9V
brid IC Technology," Proceedings of International + _18
Communications Conference, 1969, pp. 46-5 -
B.2V
46-10.
XR-C240

OPERATION OF THE XR-C240 +

The XR-C240 combines all the functional blocks of a

t 15
4.3V 300!1
PCM repeater system in a single monolithic IC chip.
The pin connections for each of the functional circuits ~ 13
within the repeater chip are shown in Figure 3, for a
16-pin duai-in-iine (DIP) package.

The circuit is designed to operate with two positive sup-

ply voltages, V++ and V+ which are nominally set to Figure 4. Recommended supply Voltage Connection
be 8.2V and 4.3V, respectively. Figure 4 gives a typical for XR-C240 (Note: See Figure 6 for
recommended power supply connection for the circuit. Recommended bypass capacitors).

11-14
 AN·02

"Set Cl to obtain r•• on.nt

link 'r~ulncy 0' l.S4-4MHz

PEAK

311
DETECTOR

DATA
THRESHOLD LOGIC
GATE

Figure 5. External Components Necessary for Circuit Operation.

OUTPUT

4.3V 8.2V
C17
0.1
• I

POWER TO REPEATER
SECTION NO.2

Figure 6. A Typical Circuit Connection for XR-C240 in 1.544 MHz T-1 Repeater System.

11-15
AN·02
system block diagram. Note that all the blocks shown in DESCRIPTION OF CIRCUIT OPERATION:
Figure 6 are a part of the monolithic IC; and the num-
bered circuit terminals correspond to the IC package This section gives a brief description of the internal cir-
pins (see Figure 4). cuitry contained within the XR-C240 monolithic IC.

Figure 6 shows a practical circuit connection for the The circuit diagram of the preamplifier section is shown
XR = C240 in an actual PCM repeater application for in Figure 7. This section is designed as a two-stage dif-
1.544 Mbps T-1 Repeater application. For simplification ferential amplifier with a broadband voltage gain of
purposes, the lightening protection circuitry and the 52db. The differential outputs of the preamplifier (Pins 4
second repeater section are not shown in the figure. and 5) are internally connected to the peak-detector,

V+ =4.3V

PEAK
DETECTOR
INPUT
B

~--~VV~----~------~16

Figure 7. Circuit Diagram of Preamplifier Section. Figure 9. Automatic Line Build-Out (ALBO) Section.

INPUT
PEAK FULL WAVE THRESHOLD FROM
GND 6 DETECTOR RECTIFIER DETECTOR PREAMP
r-------~,------~ ,---....
A- A+

~ 1 1 l l
R14
11
B
~
R13
f Ij
D
Vv'V
R12 j j """ Rl1 j 11
15
v+ = 4.3V
Figure 8. Circuit Diagram of Threshold-Detector, FUll-Wave Rectifier and Peak-Detector Sections.

11-16
full-wave rectifier and the threshold detector sections
AN·02
of the second gain stage is "integrated" by the phase-
of the XR-C240 as shown in Figure 8. shift capacitor, C1, externally connected to Pins 11 and
12. (See timing diagrams of Figure 13.) The nominal val-
The peak-detector output (terminal B of Figure 8) is in- ue of this capacitor is in the 30 to 40pf range. The trian-
ternally connected to the Automatic Line Build-out gular waveform across Pins 11 and 12 is at quadrature
(ALBO) section of the circuit and controls the DC bias phase with the sinusoidal voltage swing across the L-C
current through the ALBO diodes 019 through 020. as tank circuit. This waveform is then used to generate the
shown in Figure 9. "strobe" signal, Cp , and the clock pulse Cf/J' which is
applied to the data latches of the logic section.
The full-wave rectifier output (output D of Figure 8) is in-
The strobe and clock pulses out of the clock-
ternally connected to the clock-extractor section of the
repeater and provides the excitation signal for the L-C regenerator section are applied to the output data
tuned tank circuit (Pin 14) of the injection locked oscilla- latches shown in Figure 11. The two parallel output R-S
tor. The threshold-detector outputs (G + and G - of flip-flops are driven by the differential inputs (G + and
Figure 8) provide the differential logic drive to the data G -) from the data comparator of Figure 8. T~ two
sets of differential data signals, F1, F1 and F2, F2 are
latches of the logic section of XR-C240.
then applied to the output driver amplifier shown in Fig-
ure 12. The high-current outputs of the driver stage
The clock-extractor section of XR-C240 is designed as (Pins 8 and 9) are connected to the center-tapped out-
an injection locked oscillator as shown in the circuit put transformer as shown in Figure 5. The voltage
schematic of Figure 10. The excitation is applied to the swing across the output is one diode drop (VBE) less
emitter of 023, through terminal D which is internally than the supply voltage spread, i.e.:
connected to the output of the threshold comparator.
This signal in turn controls the current in the resonant Peak Output Swing = (V++) - (V+) - (VBE) = 3.2V
L-C tank circuit connected to Pin 14. The sinusoidal
waveform across the tank is then amplified and The output stage is designed to work into a nominal
squared through the cascaded differential gain stages load impedance of 100 ohms, and can handle peak
made up of 031, 032 and 035, 036. The output swing load currents of 30mA.

,..--_ _ _ _ _ _---r-<l'O v·· :

8.2V

Figure 10. Circuit Diagram of Clock Extractor Section.

•
11-17
AN·02 Cp C r-_--_------1---r----{10 V++ = B.2V

G+

Fl-+--+-'"
Fl ~-+--+-- ..

~:TERNAL
BIAS} -+-...---I;:.......::!.!..-----[
Va = ~~~RNAL H---+~~-+----+£

Figure 11. Data Output Latches (Logie Section). Figure 12. Output Driver Section.

11-18
 AN·02
ELECTRICAL CHARACTERISTICS
(Measured at 25°C with V + + = 8.2V, V + = 4.3 V, unless specified otherwise.)

LIMITS
PARAMETER MIN. MAX. UNITS CONDITIONS
Supply Voltage:
V+ + 7.79 8.61 V Measured at Pin 10
V+ 4.085 4.515 V Measured at Pins 7 and 15

Supply Current: See Figure 4

IA 1.1 2.5 mA Supply = 8.2V
18 6 11 mA Supply = 4.3V
Total Current 7.1 13.5 mA

Preamplifier
Input Offset Voltage, VOS 15 mV
Open Loop Differential Gain, AO 50 54 db
Input Bias Current, IB 4 [.LA
Input Offset Current, lOS 2 [.LA
Input Impedance, Rin 50 kO

Comparator Thresholds See Figure 8

Measured Differentially Across
Pins 4 and 5
Peak Detector (ALBO)
Threshold ± 1.3 ± 1.6 V
FUll-Wave Rectifier Threshold ±0.9 ±1.15 V
Data Threshold ±0.28 ±0.48 V

Clock Extractor Section See Figure 10

Tank Drive Impedance 50 kG At Pin 14
Tank Drive Current
"Zero" Signal Current 12 24 [.LA
"One" Signal Current 80 220 [.LA
Recommended Tank Q 100
Phase Shifter Offset Voltage -18 +18 mV Voltage applied to Pins 7 and 14
to reduce differential voltage
across Pins 11 and 12 to zero.

Output Drive Section See Figure 12

Voltage levels referenced to Pin 7
Outout Voltaae Swina ::10 v Q, -1nno
 AN·03
Active Filter Design with Ie OP Amps
INTRODUCTION
This application note will assist the designer in select- Since the operational amplifier plays such a key role in
ing the optimum filter for his application. It begins with the active filter, its characteristics are of prime impor-
a table of transfer functions, and network defining tance. By using operational amplifiers as the basic gain
equations, for the high-pass, low-pass, bandpass, and stage of the active filter, problems previously encoun-
band-reject filters. A guide to the three types of filter re- tered due to low-input impedance, high-output imped-
sponses will be presented, along with illustrations of ance and low-gain are virtually eliminated. Operational
several filter realizations, with their respective merits amplifiers provide the required response for various fil-
and limitations. Finally, the entire contents are brought ter types. Some of the more popular filters are multiple
together, to provide the designer a complete working feedback, state variable, bi-quad and Sallen Key, which
schematic of an active filter in a modem configuration, can be used to obtain high-pass, bandpass and low-
utilizing the XR-4202 Quad Programmable Operational pass filter functions. They are capable of giving the de-
Amplifier, along with the XR-2206 Waveform generator, signer all of the standard filter responses, i.e., But-
and the XR-2211 Precision Tone Decoder. terworth, Chebychev, and Bessel.

PRINCIPLES OF OPERATION
The XR-4202 Quad Programmable Operational Ampli- There are many single, dual, and quad operational am-
fier is a basic building block for active filters, and is plifiers that can be used to implement the filters dis-
ideally suited for most filter applications. The XR-4202 cussed. Table 1 lists some standard operational am-
provides the user the flexibility to externally program - plifiers and compares their important characteristics.
the gain-bandwidth product, the supply current, the in- Table 2 gives the designer a brief review of the basic
put bias current, the input offset current, the input transfer functions and network defining equations. Note
noise, and the slew rate. The user, therefore, can trade- that a family of curves exists for all filters except first or-
off bandwidth for supply current or optimize the noise der low-pass and high-pass. This is due to the presence
figure. Likewise, other amplifier characteristics can be of loop damping. This point will be expanded upon in
programmed for a specific need. the next section on filter responses.

Table 1.

DEVICE CHARACTERISTICS XR-4202 XR-3403 XR-4136 XR-4558 741 UNITS

Slew Rate 1.5 .6 1.6 1 .5 VIpS

Gain-Bandwidth Product 3.5 1 3 3 1 MHz

Input Offset Current 10 30 10 5 20 nA

Input Bias Current 80 200 80 40 80 nA

Supply Current (max) 6.0 7.0 4.0 5.7 2.8 mA

Note: All values typical unless otherwise specified.

11-20
 Low Pass High Pass
Table 2.
Transfer Functions and Equations
Band Pass
AN·03
Howo Ho a wos
H(s) == s + wo H(S)=~
s + wo H(5) == 52 + awoS + wo2
. _[ Ho2wo ] '/2
[HOw)) - 2 2 (H(jw)1 == [Ho2wo2 ]
w + wo
w 2 + wo 2

Ib = Tan- 1 .:::....
wo
o ==..!!. -Tan -1 w
2 wo

Ib ==..!!. -Tan- 1 (20w + V402 -1)

2 wo

- Tan-1 (20W - V40 2 - 1)

wo

(HOw))

-20

~ r-+-------r-------~ +90 F;;t:;=::::::::=-i----t-l

10 10

Low Pass Second Order High Pass Second Order Band Reject

H(s) = (s2 + w( 2 )Ho

H(s) == s2 + awoS + wo2 H(s) == s2 + awoS + wo2 s2 + (twoS + wo 2

Ib == 1T - Tan -1 [l (2 ;) + V4- lt
2) ] Ib==:::: -Tan- 1 20w+ V40 2_1
2 wo

-Tan-'[V2 2w + V4
w()
-a2] -Tan- 1 [~2(wwo - V4 - ( 2)J -Tan -1 (2Qw - '1'402 - 1)
wo

Q=10
IHIJ···I(

•
-40

90

-180 L-.L______l......:::::::===~~
10 10

Definition of terms:

wo == Cutoff frequency 2 1TfO Wc == Center frequency 0==1/a==~

w1 w2 -
a == Loop damping W1 == Lower cutoff frequency ¢ == Phase
s == fI + jw complex frequency w2 == Upper cutoff frequency
[HOw)] == Magnitude response
H(s) == Transfer function

11-21
AN·03
Filter Responses ment change. Although these parameters are only di-
rectly applicable to an infinitesimal change, they are
Once the transfer function has been determined, the easily used to evaluate performance for 1 % changes,
next step in filter design is to decide upon the desired and many times are used for element changes up to
response. As previously mentioned, the damping of the 10%. Examples will be given later in this section that
filter determines its characteristics near cutoff. There will help clarify this parameter.
are three basic types of responses which are depicted
in Table 3, along with their characteristics. In the case
Table 3.
of Butterworth and Bessel, the response has been
fixed. However, for the Chebychev the ex is chosen for
the particular response desired. This is done by using a FIL TER AMP.
TYPE ex BASIC FEATURES RESPONSE
nomograph such as the one shown in Figure 1. To use a
nomograph the information required is: Amax (maxi- Bessel V3 Best time dela'/
mum ripple in the passband), Amin (minimum attenua-

'""
Smoothest phase
tion in the stop band), and fls (ratio of the Amin band- response
width to the Amax bandwidth). These terms are illus-
trated in Figure 2. Once these terms are known, the Butterworth Vi. Maximally flat
nomograph is used by locating Amax, and drawing a amplitude response

straight line through Amin to the left-hand side of the

graph. From this point, a horizontal line is drawn to the
intersection of fl s. The minimum order of the transfer
function will be the number of the curve passing above
Chebychev Ciln
Vary
Passband ripple
Fast cutoff slope
L\
this point. Once this is done, the ex and wo for each
stage is found by consulting the Chebychev network pa- Ami.
rameter tables for the desired passband ripple, and the
number of poles. Such tables can be found in standard
filter handbooks.

Amin

Figure 2. Ratio of Amin Bandwidth to Amax Bandwidth.

The filter realizations presented here are to be used as

a basic guide to help the designer become more adept
at designing filters. State-variable and multiple feed-
back filters will be discussed, and the relative merits of
each will be given. It will also be shown that many of
the commonly used filters are actually specific cases
for the filters mentioned.

Figure 3 illustrates a typical multiple feedback connec-

tion with the non-inverting input grounded. To minimize
offset, this point should be returned to ground via a re-
sistor whose value is equal to the impedance at the in-
verting input. The transfer function for this circuit is
given by Eq. 1. Each element represents a single resis-
tor or capacitor. To realize the transfer function, each
admittance parameter is replaced by 1/R for a resistor
and SC for a capacitor. An example will help to clarify
this point. If the desired response is a high pass, the
Figure 1. Nomograph to Select Desired Response. form of the characteristic equation is given in Table 2.
To transform Eq. 1 into the high-pass characteristic,
then Y 1, Y3, and Y4 become capacitors and Y2 and Ys
Filter Realizations resistors. (It should be obvious that a low-pass function
could have been fabricated by letting Y2 and Ys be ca-
There are numerous ways of realizing the transfer func- pacitors, and similarly, a bandpass function could have
tions discussed. Each method has its own relative mer- been realized by making Y3 and Y4 capacitors.) The
it. The configuration selected depends primarily on the terms of the network function, for the high-pass filter
specific application and the desired sensitivity parame- shown in Figure 4, are given in Table 4 along with their
ters. Sensitivity parameters are a means of relating the sensitivity parameters. The transfer function for Figure 4
resultant change in a transfer function, due to an ele- is given by Eq. 2.

11-22
 AN·03
+
>---4---{) +

Figure 3. Multiple Feedback Connection with Noninverting

Input Grounded.
Figure 4. Network Function for the High-Pass Filter.

lower sensitivity to component tolerances. The most

Eq. 1 commonly used filter for this purpose is the state-
variable.

The state-variable synthesis approach is used in most

present day Universal Active Filters (UAF). With this
Eq.2 method, the actual nth order polynominal of the trans-
EO - (C1 /C4)s2
fer function is simulated as it would be with an analog
- (s) == - - ; : ; - - - - - - - - - - - - - - - - computer. When using the state-variable approach, all
E1 s2 + s(1/RS)(C1/C3C4 + 1/C4 + 1/C3) + 1/R2RSC3C4 three outputs (high-pass, low-pass, and bandpass) are
available simultaneously. The sensitivities, with respect
to component tolerances, are typically less than or
As can be seen from the sensitivity parameters, there is equal to one, and the sensitivity of 0, with respect to
a high degree of circuit sensitivity due to the compo- amplifier gain, can equal zero with high amplifier gain.
nent tolerances. Due to the interaction of components, Because of the high amplifier gain requirement, these
the tuning of this circuit may be rather involved. How- filters tend to be limited to the audio range. The cost of
ever, with tight component tolerances, these circuits reducing the circuit element sensitivities is the need to
give the designer very predictable results. Due to the use n + 2 operational amplifiers to synthesize an nth or-
high input impedance and low-output impedance, sev- der transfer function. For this reason, this type of con-
eral of these stages may easily be cascaded to achieve figuration may not be cost effective in the synthesis of
a higher order function. What is desired is to have a low-O, high-pass, and low-pass filters.

Table 4.

Parameter Defining Equation Sensitivity

C1
HO = C4 SC HO = -SC HO = 1
1 4

Note: The sen-

a ~R2 (C1 ~C3 ~C4) Sc a = -1 - - -1 - C1
- + 1) sitivity of HO

•
= R5 ..JC3C4 + C4 + C3 3 2 awOR5C3 C3 with this im-
plies that if C1
Sc 1 1
01=----- (C1
-+ 1) changes by
4 2 awOR5C4 C3 1% HO will al-
so change by
1 C1 1%. The de-
SCa=---- fining equa-
1 awOR5 C3C4
tion for a sen-
1 sitivity param-
SR2a = -SR5 a = "2 eter is:

xdY
Sx Y =
Ydx

Wo ( 1 )V2 SA wO = SR wo = Sc wO = Sc wO = - .!
2 5 3 4 2
= R2 R5C3C4

11-23
AN·03
Table 5.

Output Parameters Defining Equation Sensitivity

1 + R3/R4
HO SR1 HO = -SR2 HO = -1/(1 + R2/R1)
1 + R1/R2
/R
SR3 HO = -SR H 0 = 1- ( R3 4 )
4 HO 1 + R1/R2

Low ( R ) Y2
"'0 SR3"'0 = SRs"'O = SR6"'0 = SC1"'0 = SC2"'0 = -SC4"'0 = - Y2
Pass R3 RSR: C 1C2
Eq.3

a 1 + R4/R3 C3 R6C2) Y2 +
R4 R3
SR4 a = -SR3 a = -1/2
1 + R2/R1 R4RSC1 RSC1 a"'0(1 + R2 /R 1)
1
SR1 a = -SR3 a =
1 + R1R2
SR6a = SC2 a = -SRSa = -SC1a = Y2

1 + R4/R3
HO SR H O = -SR HO = -1/(1 + R2/R1
1 + R1/R2 1 2

~
/R
R4 3 )
SR3 HO = -SR HO = (
4 HO 1 + R1/R2
High .
Pass "'0 SAME AS LOW PASS
Eq.4

a C++ 1
/R
R2/R1
R C
R4 3)C3 6 2) Y2
R4RSC1
SR4 a = -SR3 a = -1/2 +
R4 /R 3
RSC1 a"'0(1 + R2 /R 1)
1
SR1 a = -SR2 a =
1 + R1R2

SR6 a = SC2a = - SRSa = -SC1a = Y2

R2
HO SR HO = -SR HO = -1
R1 1 2

"'0 SAM E AS LOW PASS

Band R
Pass 0= 1/a + R2 /R 1)C4 SC 1)'/2 SRsO = SC1 0 = -SR6 0 = -SC2 0 = 1/2
Eq.S C+ R4 /R 3 R3 R6C2
R4 /R 3
SR4 0 = SR3 0 = 1/2 -
RSC1 a"'0(1 + R2 /R 1)
1
SR2 0 = -SR 0 =
1 1 + R1/R2

11-24
Figure 5 shows a typical state-variable configuration
AN·03
whose characteristic equations are given by Eq. 3, FSK MODULATOR
XR·2206
Eq. 4, and Eq. 5. These equations all have the same de- 600
LINE
nominator, and the numerator is determined by the TERM
point at which the output is taken. This form may also
be used to simulate a band-reject function by summing
the high-pass and low-pass outputs. The defining equa- FSK DEMODULATOR
tions and sensitivity parameters are given in Table 5. It is XR·2211

noted here that the bi-quad is actually a slight variation

of a second order state-variable.
Figure 6. FSK System.

In this system, the digital data to be transmitted is used

to key the XR-2206. The frequency-shift keyed output of
the XR-2206 is then sent through the hybrid and out on-
to the line. (The hybrid is used to obtain isolation be-
tween data transmitted and data received, and may al-
so be used to amplify the received signal.) In full duplex
operation, this system must be able to receive and
transmit, simultaneously. Due to line losses, the re-
ceived signal may range from - 12 dBm to - 48 dBm.
The output level of the transmitter is typically - 6 dBm
(allowing for a 6 dB loss in the hybrid). Due to line mis-
Figure 5. Typical State-Variable Configuration. match, the hybrid may only provide 10 dB of isolation to
the filter. Therefore, the levels at the input of the filter,
Eq.3 assuming a gain of 6 dB from the line through the hy-
brid, is - 6 and - 42 dBm for the desired signal, and
- 16 dBm from the local oscillator. This means that in a
worst case situation, the input level of the received sig-
nal is - 42 dBm, with the level of the local oscillator
26 dB above this. For the XR-2211 to operate with a
low-bit error rate, the input should be 6 dB higher than
the interfering signal. This implies that the stopband,
Amin, from Figure 2 is 32 dB. The XR-2211 has an inter-
Eq.4 nal preamplifier with a dynamic range of greater than
60 dB, and requires a minimum input level of - 38 dBm
to cause limiting. If we choose a filter to have a pass-
band ripple of 1 dB, and an overall gain of 5 dB, the in-
put conditions of the XR·2211 will be satisfied. The fil-
ters introduce a phase shift that is only linear for ap-
proximately 1/2 and 113 of the passband; therefore, a
bandwidth of 400 Hz is used for the filter. The general
shape of the filter is shown in Figure 7.
Eq.5

Modem Filter

A typical application for an active filter is the input

stage of a frequency demodulator. Any noise or spuri-
ous signals at this point would affect the overall quality
1170 1925

Figure 7. General Filter Shape.

2325 2980
•
of the output. A more specific example can be cited by Note: The values used in this filter are based on a mo-
considering the FSK system shown in Figure 6. dem using an XR-2206 as the modulator, and
(Frequency-shift keying is a means of transmitting digi- XR-2211 as the demodulator. If digital techniques
tal information, primarily through telecommunications are used, the filter parameters may be different,
links.) This type of system is thoroughly covered in Ex- due to the harmonics generated by digital syn-
ar's Application Note, AN-01, and will only be briefly dis- thesis of a sine wave, and higher signal-to-noise
cussed here. requirements of the demodulator.

11-25
AN-03
To find the minimum number of poles required for this
Eq.7 ex"'1 0 1)2 _ 1
response, the nomograph in Figure 1 is used. The point ( 20
falls between a 2- and 3-pole filter. The values of "'0 + ex 0
are determined from the tables, for a 3rd order Cheby-
chev response with 1 dB ripple. M = 1.0955
Where M = "'1 = "'0 = .!l = !Q f1 = 2317.6
From the tables: "'0 "'2 fo f2 f2 = 1931.1

"'0 = .997098 for Section 3 the real pole is transformed into a com-
complex pole
ex = .495609 plex pole pair.
"'0 = .494171 - real pole.
20 0
03 = - = 10.7
The geometric center is "'0 = .../"'3"'2 or "'/f3 f 2 = fO ex"'B

and f3 = fo ·
The filter 00 = _fO_ = .../(1925)(2325) = 5.28892 The 3 filter stages are now defined:
f3 - f2 2325 - 1925
f1 = 2317.6 01 = 21.49
f2 = 1931.1 02 = 21.49
The 0 of each section of the filter is determined by
f3 = 2115.56 03 = 10.7
Equation 6.
Eq.6 In this example, the multiple feedback approach is used
since 3-pole pairs can be generated with 3 op amps, 6
capacitors, and 9 resistors; an equivalent filter could
have been designed with the state-variable. but this
would have required 9 op amps to realize. The actual
2 a1 w1 2 filter is shown in Figure 8. All capacitor values are cho-
00 sen to be .01 JtF (5%), and all resistors are 1 %. The
values for this filter and a low-band filter are shown in
Table 6.
01 = 21.49 = 02. Section two is a reflection of section
one, about fo . The center frequencies are found by Figure 9 shows a complete Originate or Answer mo-
Eq.7. dem. The values for the XR-2206 and XR-2211 are given

Figure 8. Modem Filter.

Table 6.

fo "'0 00 R1 R2 R2 C1 C2 Ho

A 1931.1 12.1335K 21.49 88.6K 192 354K .01 .01 2

Originate B 2317.6 14.562K 21.49 74K 160 295K .01 .01 2
C 2115.6 13.293K 10.7 40K 355 161K .01 .01 2

A 1362.26 10.115K 11.827 58.5K 421 234K .01 .01 2

Answer B 975.51 6129.3 11.827 96.5K 421 386K .01 .01 2
C 1152.78 7.243K 5.832 40.3K 1219.5 161K .01 .01 2

11-26
in Table 7. For an originate modem, the transmitting
AN·03
The first op-amp is connected as an active hybrid which
frequencies are 1070 and 1270, and the receiving should supply a minimum of 10 dB isolation, from trans-
frequencies are 2025 and 2225, for a space and mark, mit to receive, while adding 6 dB from the line to the
respectively. receiver.

Figure 9. Originate or Answer Modem.

Table 7. Recommended Component Values for Typical FSK Bands

Component Values

FSK Band XR·2206 XR·2211

Baud
Rate fL fH R6A R6B R7A R7B C3 RX RC RA Co CA CF Co
Originate 1070 1270 10 18 10 20 .039 10 18 100 .039 .01 .005 .05

Answer 2025 2225 10 16 10 18 .022 10 18 200 .022 .0047 .005 .05

Units: Frequency - Hz; Resistors - kO; Capacitors - J-LF.

•
I

11·27
 AN-04
XR·C277 Low·Voltage PCM Repeater IC
INTRODUCTION
The XR-C277 is a monolithic repeater circuit for Pulse- tem would require two XR-C277 IC's, one for each di-
Code Modulated (PCM) telephone systems. It is de- rection of information flow.
signed to operate as a regenerative repeater at 1.544
Mega bits per second (Mbps) data rates on T-1 type Figure 2 shows the functional block diagram of one of
PCM lines. It is packaged in a hermetic 16-pin CERDIP the digital repeater sections, along with the external
package and is designed to operate over a temperature zener regulator. The basic system architecture shown
range of - 40°C to + 85°C. It contains all the basic in the figure is the same as that utilized in the design of
functional blocks of a regenerative repeater system in- the XR-C277 monolithic IC.
cluding Automatic Line Build-Out (ALBO) and equaliza-
tion, and is insensitive to reflections caused by cable In terms of the functional blocks shown in Figure 2, the
discontinuities. basic operation of the repeater can be briefly explained
as follows:
The key feature of the XR-C277 is its ability to operate
with low supply voltages (6.3 volts and 4.4 volts) with a The bipolar signal, after traversing through a dispersive,
supply current of less than 13 mA. Compared to con- noisy medium, is applied to a linear amplifier and auto-
ventional repeater designs using discrete components, matic equalizer. It is the function of this circuit to pro·
the XR-C277 monolithic repeater IC offers greatly im- vide the necessary amount of gain and phase equaliza-
proved reliability and performance and provides signifi- tion and, in addition, to band limit the signal in order to
cant savings in power consumption and system cost. optimize the performance of the repeater for near-end
crosstalk produced by other systems operating within
the same cable sheath.
FUNDAMENTALS OF PCM REPEATERS
The output signals of the preamplifier which are bal-
Figure 1 shows the block diagram of a bi-directional anced and of opposite phases are applied to the clock
PCM repeater system consisting of two identical digital extraction circuit and also to the pulse regenerator. The
regenerator or repeater sections, one for each direction signals applied to the clock extraction circuit are recti-
of transmission. These repeaters share a common fied and then applied to a high-Q resonant circuit. This
power supply. The DC power is simplexed over the resonant circuit extracts a 1.544 MHz frequency com-
paired cable and is extracted at each repeater by ponent from the applied signal. The extracted signal is
means of a series zener diode regulator. The XR-C277 first amplified and then used to control the time at
monolithic IC replaces about 90% of the electronic which the output signals of the preamplifier are sam-
components and circuitry within the digital repeater pled and also to control the width of the regenerated
sections of Figure 1. Thus, a bi-directional repeater sys- pulse.

SIGNAL F L O W - -

DIGITAL
REPEATER

/I II

~ 11-'L...--~_ErEATE_n---,J II r-
- - - - SIGNAL FLOW

Figure 1. Block Diagram of a Bi-Directional Digital Re- Figure 2. Functional Block Diagram of a Digital PCM Re-
peater System peater System

11-28
It is the function of the pulse regenerator to perform the V++
AN·04
sampling and threshold operations and to regenerate
the appropriate pulse. The regenerated pulse in turn ap-
plied to a discrete output transformer which is used to 10011 10
drive the next section of the paired cable.
18 15
Additional References on PCM Repeaters: 6.3V

1. Mayo, J. S., "A Bipolar Repeater for Pulse Code Sig- 4.4V
nals," B.S.T.J., Vol. 41, January, 1962, pp. 25-97.
2. Aaron, M. R., "PCM Transmission in the Exchange
Plant," B.S.T.J., Vol. 41, January, 1962, pp. 99-143.
3. Davis, C. G., "An Experimental Pulse Code Modula-
tion System for Short-Haul Trunks," B.S.T.J., Vol. 41, Figure 4. Recommended Supply Voltage Connection for
January, 1962, pp. 1-25. XR-C277 (Note: See Figure 6 for Recom-
4. Fultz, K. E. and Penick, D. B., "The T-1 Carrier Sys- mended Bypass Capacitors)
tem," B.S.T.J., Vol. 44, September, 1965, pp. 1405-
1452.
5. Tarbox, R. A., "A Regenerative Repeater Utilizing Hy- The circuit is desi¥ned to operate with two positive sup-
brid IC Technology," Proceedings of International ply voltages, V + and V + which are nominally set to
Communications Conference, 1969, pp. 46-5 - 46- be 6.3V and 4.4V, respectively. Figure 4 gives the rec-
10. ommended power supply connection for the circuit.

OPERATION OF THE XR-C277 The supply currents 1A and 1B drawn from the two sup-
ply voltages applied to the chip are specified to be with-
The XR-C 277 combines all the functional blocks of a in the following limits:
PCM repeater system in a single monolithic IC chip.
The pin connections for each of the functional circuits
within the repeater chip are shown in Figure 3, for a 16-
pin dual-in-line package. a. Current from 6.3V supply voltage, IA

2.5 mA :::;; IA :::;; 4.0 mA

ALBO
OUTPUT
b. Current from 4.4V supply voltage IB:

PRE AMP { 2 7 mA :::;; IB :::;; 9 mA

INPUTS

4
PRE AMP The external components necessary for proper opera-
OUTPUTS {
tion of the circuit are shown in Figure 5, in terms of the
system block diagram. Note that all the blocks shown in
ANALOG
GROUND
Figure 5 are a part of the monolithic IC; and the num-
DIGITAL
bered circuit terminals correspond to the IC package
GROUND pins (see Figure 3).
(+) DRIVER
OUTPUT Figure 6 shows a practical circuit connection for the
XR-C277 in an actual PCM repeater application for
1.544 Mbps T-1 Repeater application. For simplification
Figure 3. Package Diagram of XR-C277 Monolithic PCM purposes, the lightning protection circuitry and the sec-
Repeater ond repeater section are not shown in the figure.

II

11-29
AN·04

3.5K

INPUT

311

3.3 ~H 556

0.0039 ~F

'SET Cl TO OBTAIN RESONANT

TANK FREOUENCY OF 1.544 MHz.

I
Figure 5. External Components Necessary for Circuit Operation in 1.544 MHz T-1 Repeater

0.0226 I,F
430!! 3K

3K 120!!
3.3 pH

30!!
I
XR·C277

30'!

I O4
. I'f

-=-
1-=-
3.5K 5.1K

-=- -=- -=- -=-

Figure 6. Typical Circuit Connection of XR-C277 in 1.544 MHz T-1 Repeater System. (Note: Set Land Cto Form a High
o Tank Resonant at 1.544 MHz. It is Recommended that 08100, and C:= pF for most applications).
11-30
DESCRIPTION OF CIRCUIT OPERATION
AN·04
Preamplifier Section (Fig. 7): Automatic Line Build-Out (ALBO) Section (Fig. 8):
The circuit diagram of the preamplifier section is shown The ALBO function is achieved by controlling the dy-
in Figure 7. This section is designed as a two-stage dif- namic impedance of ALBO diodes (021 and 022). The
ferential amplifier with a broadband differential voltage current which sets this dynamic impedance is supplied
gain of 52 dB. The differential outputs of the preamplifi- through 021 and is controlled by the peak-detector out-
er, Pins 4 and 5, are internally connected to the peak- put level applied to base of 023.
detector, full-wave rectifier and the data threshold de-
tector sections of the XR-C277. V+ '" 4.4V

V+ ; 4.4V 7~--+-------------------~

Figure 8. Automatic Line Build-Out (ALBO) Section

GND

Figure 7. Circuit Diagram of Preamplifier Section

II

11-31
AN·04
Data-Threshold Detector; FUll-Wave Rectifier and Peak rent through the ALBO diodes 021 through 022, as
Detector Sections (Figure 9): shown in Figure 8.

The level detector and peak rectifier sections of the XR- The full-wave rectifier output is internally connected to
C277 are made up of two sets of gain stages which are the clock-extractor section of the repeater and provides
driven differentially with the (A +) and (A020 - ) outputs the excitation signal for the loC tuned tank circuit (Pin
of the preamplifier section. The outputs of the data 14) of the injection locked oscillator. The detection
threshold comparators, 0 + and 0 - activate the data thresholds of the comparators are set by the resistor
latches shown in Figure 11. chains (R45, R47, R51, RSS) and (R46, R48, RS2, RS6)·
The resistor ratios are chosen such that the data
The peak-detector output, terminal B of Figure 9, is in- threshold is 50% of the ALBO threshold; and the clock
ternally connected to the Automatic line Build-Out (AL- extractor threshold is 73% of the ALBO threshold.
BO) section of the circuit and controls the dc bias cur-

FROM PREAMP OUTPUT

V+
A- A+

D+} TO DATA
0- LATCHES

DATA THRESHOLD
DETECTOR
I...---........
R45 Me

Me
TO CLOCK
A47 EXTRACTOR

FULL-WAVE
REcnFlER
{
AU
8
R51
TO "LBO

PEAK DETECTOR

R55

L---________~------------------------------~------------~_oQND •
Figure 9. Data-Threshold Detector, FUll-Wave Rectifier and The Peak Detector Sections of XR-C277

11-32
Clock Extractor Section (Figure 10):
AN .. 04
The clock-extractor section of XR-C277 is designed as of the second gain stage is integrated by the phase-
an injection locked oscillator as shown in the circuit shift capacitor, C1, externally connected to Pins 11 and
schematic of Figure 10. The excitation is applied to the 12. See timing diagrams of Figure 13. The nominal val-
emitter of 01 B, from the output of the full-wave rectifier. ue of this capacitor is in the 30 to 40 pF range. The tri-
This signal in turn controls the current in the resonant L- angular waveform across Pins 11 and 12 is at quadra-
C tank circuit connected to Pin 14. The sinusoidal ture phase with the sinusoidal voltage swing across the
waveform across the tank is then amplified and L-C tank circuit. This waveform is then used to generate
squared through two cascaded differential gain stages the strobe signal, Cp , and the clock pulse CeI>' which are
made up transistors 03 through Og. The output swing applied to the data latches of the logic section.

LC
v+ = 4.4V TANK V+ + = 6.3V 30-40 pF

12 --H- - 11
Cl

R7

Rl R2 R3 R4 R5 R6

Cp

INPUT
FROM
FULL
WAVE
RECTIFIER

RIg R17 R22 R23

RIgA R24 R26

Figure 10. Circuit Diagram of Clock Extractor Section

Data-Latch and Output Driver Sections

(Figures 11 and 12):
which is the same as the extracted clock pulse width

•
The data-latch section consists of two parallel flip-flops, (See timing diagram of Figure 13.)
driven by the D + and D - inputs from the data-
threshold detector. When the D + input is at a low state, The outputs of the two data latches drive the two output
the sampling or strobe pulse, Cp , is steered through driver stages shown in Figure 12. The high-current out-
047 Aand sets Flip-Flop 1, on the leading edge of Cpo puts of the driver stage, Pins 8 and g, are connected to
Conversely, when D - input is at a low state, the sam- the center-tapped output transformer as shown in Fig-
pling pulse is steered through 047B to set Flip-Flop 2. ure 5. The voltage swing across the output is one diode
Each flip-flop section is then reset at the trailing edge of drop (VBE) less than the supply voltage at Pin 10. The
the clock pulse input, CeI>' The flip-flop outputs, (F 1, F 1) output stages are designed to work into a nominal load
and F2, F2) are then used to drive the output drivers. impedance of 100 ohms, and can handle peak load cur-
This logic arrangement results in an output pulse width rents of 30 mA.

11-33
AN·04
V+ + = 6.3V

RIOS RI06 RI02 RIOl

R6S R66 R61 R10 R11 R12

GND

Figure 11. Data-Latch Section of XR-C277 Figure 12. Output-Driver Section

INPUT
SIGNAL

OSCILLATOR
WAVEFORM
(PIN 14)

I INTEGRATED
lA. /'\ /'\ A OSCILLATOR

1 V V V "
WAVEFORM
(PIN II OR 12)

I
STROBE PULSE
Cp

REGENERATED
CLOCK PULSE

-. Cp

REGENERATED

u
BIPOLAR
OUjPUi
(PINS 8 AND 9)

Figure 13. Typical Timing Waveforms for a 1-0-1

Input Data Pattern

11-34
Three-State FSK Modem Design
using XR-2207 and XR·2211
INTRODUCTION operating a number of separate FSK modulator!
demodulator (modem) stations over a common set of
This application note describes the design principle, telephone lines, and address them one at a time from
and the operation of three-state frequency-shift keyed the CPU. The simplified block diagram of such a pro-
(FSK) modems for industrial process control systems. cess controlled system is shown in Figure 1. In many
Compared to conventional bi-state modems, which uti- such cases, such a process control system also makes
lize only the mark and space frequencies, the three- use of the distributed-intelligence concept by employ-
state modems utilize a third frequency, the carrier sig- ing a separate data acquisition system at each control
nal, for additional command and control functions. This station. Such an intelligent data acquisition system is
carrier-control feature allows each modem system con- normally made up of a microprocessor, along with its AI
nected to a central processor (CPU) to be interrogated D and D!A converter circuitry, which will interface with
or activated, one at a time, without interference from the sensors and the control machinery. An FSK modem
the other modem transmitters or receivers within the will interface with the telephone wires going back to the
same system. central command unit, the CPU.

The design and operation of conventional bi-state FSK

In the conventional operation of FSK modems, they op-
modems using the XR-2206 modulator, and the XR-
erate in their bi-state mode, i.e., the information to be
2211 demodulator, are covered in Exar's Application
transmitted or received is available in two states, corre-
Note, AN-01. This application note extends these basic
sponding to either a mark or a space frequency. In a
concepts to the design of FSK modulators or demodu-
complex process control system, such as the one
lators with three-state operation capability.
shown in Figure 1, the versatility of the system can be
PRINCIPLES OF OPERATION greatly enhanced by operating the FSK modulatorl
demodulator in three-state mode, where the information
In a wide variety of industrial process control applica- to be transmitted or received is available in three
tions, it is necessary to have a number of separate sen- states, i.e., a mark or space frequency, or a carrier sig-
sors and controllers activated by a centralized com- nal, which is normally a tone having a frequency half-
puter or processing unit (CPU). This can be achieved by way between the mark and space frequencies.

VALVE VALVE VALVE

MOTOR

CARRIER
CONTROL

PHONE LINE OR DEDICATED LINE

II
DATA IN
XR-2211
FSK
CENTRAL RECEIVER
PROCESSING CHANNEL
UNIT (CPU) SELELCT
XR-2207 FSK
DATA OUT TRANSMITTER

Figure 1. Simplified Block DIagram of a Complex Process Control System with Multiple FSK Modems.

11·35
AN-05
Figure 2 shows a detailed block diagram of a complete dem system (Figure 2) is concentrated in three discrete
three-state FSK modem system. The system is made frequencies in each of the transmit- and receive-bands.
up of five blocks: These are:

(a) FSK transmitter or encoder which converts the Transmit-Band (transmitter output):
input data or logic signals into transmitted
mark, space, and carrier tones. fT1 = Transmitter mark frequency
(b) FSK receiver or decoder which converts the fT2 = Transmitter space frequency
frequency signals sent over the telephone
lines into binary logic signals. fTO = Transmitter carrier or center frequency

(c) Transmitter bandpass filter which band-limits Receive-Band (receiver input):

the frequency output of the transmitter to the
allocated transmitter bandwidth. fR1 = Receiver mark frequency

(d) Receiver bandpass filter which limits the in- fR2 = Receiver space frequency
coming Signals to those frequencies which fall
within the allocated receiver bandwidth. fRO = Receiver carrier or center frequency
(e) A line hybrid, or a 4-wire to 2-wire transformer, Normally, the mark and space frequencies are chosen
which isolates or decouples the transmitter to be near the opposite edges of the receive- or
output from the receiver input. transmit-band, and the carrier frequency is chosen to
be at the center of the corresponding band.
CARRIER CONTROL

When activated by the enable/disable control, the

three-state transmitter generates either the FSK mark/
space frequencies, fT1 and fT2, or the carrier frequen-
cy, fTO. The carrier frequency is activated by the carrier
(A)
THREE-STATE ACTIVE control input, and can override the input data.
TRANSMITTER FILTER
(XR-2206) (B)
ENABLE/DISABLE
CONTROL
The three-state receiver provides two outputs: A binary
data output, when activated by the input mark/space
frequencies, fR1 and fR2, and a logic signal, to control
or enable the transmitter when the receiver-carrier fre-
quency, fRO, is present. As an option, it may have a
dual-mode operation capability which can provide seri-
al data outputs for half-bandwidth deviations of the in-
THREE-STATE
RECEIVER
put signal, i.e., for FSK Signals comprised of center-to-
ACTIVE

n DATA
OUTPUT
(XR-2111)
(C)
FILTER
(0)
mark or center-to-space frequency shifts. The data out-
puts corresponding to this mode of operation are
shown as outputs, D1 and D2 of Figure 2.
01 CIRCUIT OPERATION
0-------
OPTIONAL 'SEE EXAR APP NOTE
OUAL/MODE MONITOR
OUTPUTS
AN-03 FOR ACTIVE
FILTER DESIGN_
The generalized three-state modem system of Figure 2
0----------
02
can operate in a multiplicity of modes. Some of these
are outlined below:
Figure 2. Block Diagram of a Three-State FSK Modem System.
Answerback Under CPU Control
The first 2 blocks, the FSK transmitter and the receiver,
are the essential part of the modem system. The re- The modem will be in a standby mode with the transmit-
maining three blocks, namely the active filters and the ter disabled, and the receiver in a standby condition
line-hybrid, are support circuits, depending on the with its data output disabled. It will be activated only
frequency-band requirements or the necessary tele- when an interrogate tone at the receiver center fre-
phone line interconnections. Detailed descriptions and quency, fRO, is transmitted by the control modem unit
design examples for these active filters are given in Ex- associated \A!ith the CPU (see Figure 1). This tone is de-
ar's Application Note, AN-03. tected by the receiver; it activates the transmitter via its
enable/disable control, and instructs the local micro-
The three-state modem is designed to operate in two processor to transmit its status information via the local
separate frequency bands: A transmit-band for the transmitter. This data is transmitted as an FSK signal
transmitted data, and a receive-band for the incoming made up of the transmit mark and space frequencies
frequencies. In certain operating modes, such as the fT1 and fT2. When the information transmission is com-
half-duplex operation, these frequency bands may be plete, or when the interrogate tone is discontinued, the
one and the same. In its most general case, the fre- entire modem system again reverts back to its standby
quency information associated with the three-state mo- mode.

11-36
Receive Under CPU Control
AN-OS
ing resistors, to produce four discrete frequencies
which are selected according to the binary logic levels
In this mode of operation, the transmitter remains dis- at the keying terminals.
abled, the receiver is at its standby mode with its data
+Vcc BIAS
output disabled. When the FSK data is sent by the CPU
modem transmitter, at the mark/space frequencies, fR1
and fR2, the data output is enabled, and the decoded
binary data is fed into the local microprocessor. Since TRIANGLE
WAVE
the center receive-frequency, fRO, is not transmitted, OUTPUT
TIMING~·­
the transmitter remains disabled. CAPACITOR -:-. --o---t----i

Priority-Transmit Request
BINARY o---t--~
KEYING 9
In an emergency situation, the local transmitter can be INPUTS o---t--~

activated by its carrier-control input, which causes it to

transmit a tone, fTO, at its center frequency. When this
tone is received by the CPU, it will be treated as a priori-
4 56 7
TIMING
ty request to transmit information; the CPU will immedi- RESISTORS GROUND VEE

ately interrogate the corresponding local modem by

sending out its address tone at frequency, fRO.

Dual-Channel Receive -VEE o-------+-+--+-~--------'

Figure 3. Functional Diagram of XR-2207 Monolithic

As an option, the receiver can provide serial data out-
FSK Generator.
puts, through separate terminals, D1 and D2 of Figure
2, for half-bandwidth deviations of the input FSK sig-
nals. In this mode, the input data will be in the form of The frequency of oscillation is set by an external timing
center-to-mark frequency shifts for one channel, and capacitor, and by the combination of one or more of the
center-to-space shifts for the other. This mode of opera- external timing resistors, R1 through R4. The keying ter-
tion allows two separate sets of data or control instruc- minals switch these external resistors in and out of the
tions to be transmitted within the same channel band- circuit and thus control the operating frequency. Table 1
width, provided that only one of these channels is used shows the four discrete frequencies which can be ob-
at anyone time. tained as a function of four logic states at Pin 8 and 9. It
should be noted that the frequency is inversely propor-
Dual-Channel Transmit tional to the timing resistor connected to the activated
timing pin. For example, if only one of the timing pins,
As an option, the transmitter can also transmit two sep- say Pin 5, is activated and its associated resistor, R3, is
arate channels, using half-bandwidth deviations of the left open-circuited (Le., R3 = 00) the oscillator will be
transmit signal. In this case, the outgoing data will be keyed OFF since this corresponds to a zero-frequency
encoded with center-to-mark transitions of the transmit- state.
ter frequency in one of the channels, and center-to-
space transitions in the other. However, similar to the Table 1.
case of the receiver, only one or the other, and not both, Output Frequency of the XR-2207
of these half-bandwidth channels can be on at a given as a Function of the Keying Logic.
time.
Logic Level Active
XR-2207 As A Three-State FSK Transmitter Timing Output
Pin 8 Pin 9 Resistor Frequency
The XR-2207 is a monolithic voltage-controlled oscilla-

•
tor (VCO) circuit with excellent temperature stability. It 1
provides simultaneous triangle and square wave out- L L Pin 6 --
puts, and can be keyed to anyone of four prepro- Co R1
grammed frequencies by means of external logic sig-
nals. These four discrete frequencies are prepro- L H Pin 6 and 7 _1_ + _1_
grammed by the choice of four external timing Co R1 Co R2
resistors.
1
Figure 3 shows a functional block diagram of the XR- H L Pin 5 --
2207 monolithic FSK generator chip. The circuit is com- Co R3
prised of four functional blocks: A variable-frequency
oscillator which generates the basic periodic wave-
forms; four current switches actuated by binary keying H H Pin 4 and 5 _1_ + _1_
inputs, and buffer amplifiers for both the triangle and Co R3 Co R4
square wave outputs. The internal current switches
transfer the oscillator current to any of four external tim- (* Frequency in Hz, R in Ohms and C in Farads.)

11-37
AN-OS +12V

S.lK RL
4.7K

N'1M FSK
OUTPUT
L--4------------------~JLrul
1-----+---,
XR·2207

..-r-__- r - r - - - - - - - - - - - o A
i;p~~ATA
ENABLE DISABLE

1--+-----0 CARRIER
C CONTROL

Figure 4. Three-State FSK Transmitter Using the XR-2207.

Figure 4 shows the recommended circuit connection of Table 2.

the XR-2207, for its operation as a three-state FSK Three-State Transmitter Operating Modes
transmitter. The three resistors, R1, R2 and R4, are as a Function of Control Inputs
used to set the three discrete frequencies to be trans-
mitted in accordance with the frequency expressions Control
given in Table 1, where: Input Level Level Transmitter Transmitter
States at at Output Operating
A 8 C Pin 9 Pin 9 Frequency Mode
fT1
L L L L H OFF Transmitter

H L L L H OFF Off
It should be noted that Pin 5 is left open circuited (Le., L H L L L Transmit
fT1
R3 = 00). This allows the circuit to be keyed OFF, or dis-
abled, by applying a high-logic state to Pin 8, and a low- H H L H L fT2 Data
logic state to Pin 9 (see Table 1).
L L H H H fTO Transmit

The functions of the three control terminals can be de- L H H H H fTO Carrier
scribed as follows:
H H H H H fTO Only
a. FSK Data Input: The serial binary data is applied to
this terminal. With the carrier control at low- and
enable/disable control at high-state, the binary da-
ta causes the transmitter to generate the mark XR-2211 As A Three-State Receiver
and space frequencies, fT1 and fT2.
The XR-2211 is a monolithic FSK demodulator which
b. Enable/Disable Control: When this input is at low- operates on the phase-locked loop principle. In addition
state, the transmitter is disabled. to the basic PLL system, the monolithic chip also con-
tains a quadrature-detector circuit which produces a
c. Carrier-Control: When this terminal is at high-state, logic signal when a carrier signal, or tone, is present
the transmitter generates a continuous tone at fre- within the capture range of the PLL. A simplified func-
quency, fTO. tional block diagram of the circuit is shown in Figure 5.

With the external logic circuitry shown in Figure 4, Basic Bi-State Operation
carrier-control can override both the enable/disable or
the FSK data inputs. A detailed truth-table of the circuit The basic operation of the XR-2211, in conventional bi-
outputs is given in Table 2, for various states of the state modems, is described in detail in Exar's Applica-
three control inputs. tion Note, AN-01. It will be briefly reviewed below.

11-38
 +VCC
./. DEl VCO
VCO
TIMING
FSK
COMP
+12V
AN·OS
OUTPUT INPUT CAP INPUT

a LOCK DETECT OUTPUT

a LOCK·DETECT OUTPUT

4 GROUND

Figure 5. Functional Block Diagram of XR-2211 FSK and Figure 6. XR-2211 as a Bi-State Receiver with Tone-
Tone Detector. Detection Capability.
The basic circuit connection for the XR-2211 for bi-state always less than the tracking range. The capture range
FSK detection is shown in Figure 6. The center frequen- is limited by C2, which, in conjunction with R5, forms
cy is determined by fa = (1/C1 R4) Hz, where capaci- the loop-filter time constant. In most modern applica-
tance is in farads and resistance is in ohms. Calcula- tions, .!lfc is chosen to be z 80% to 95 % of the track-
tions for fa should fall midway between the mark and ing range, .!If.
space frequencies.
The bi-state FSK data filter, made up of RF and CF, re-
The tracking range (± .!If) is the range of frequencies moves the jitter from the demodulated FSK signal. Simi-
over which the phase-locked loop can retain a lock with larly, the lock-detect filter capacitor (CD) removes chat-
a swept input signal. This range is determined by the ter from the lock-detect output. With RO = 510 kO, the
formula: minimum value of CD can be determined by: CO(/Lf)
z 16/capture range in Hz. The XR-2211 has three npn
.!If = (R4fo/R5) Hz. open-collector outputs, each of which is capable of
sinking up to 5 mAo Pin 7 is the FSK data output, Pin 5 is
.!If should be made equal to, or slightly less than, the the Q lock-detect output which toes low when a carrier
difference between the mark and space frequencies. is detected, and Pin 6 is the Q lock-detect output which
For optimum stability, the recommended range of val- goes high when lock is detected. If Pin 6 and 7 are
ues for R4 is between 10 kO and 100 kO. wired together, the output signal from these terminals
The capture range (± Md is the range of frequencies will provide data when FSK is applied, and will be low
over which the phase-locked loop can acquire lock. It is when no carrier is present.

+12V

RA
VA

FSK SII~~~~ 0---+--------,

01

•
10K 10K 02

I RX

VB

Ry 1/2 OF
XR·4558
fro DETECTOR OUTPUT
(TRANSMITTER ENABLE, DISABLE)
-=
Figure 7. Circuit Connection for Operating XR-2211 as a Three-State FSK Receiver.

11-39
AN-OS
Three-State Operation
The XR-2211 FSK demodulator circuit can be made to The output of Pin 11 is filtered by RK and CK, and is
operate as a three-state receiver (see Block B of Figure used to drive the external voltage comparators. The
2), using the circuit configuration shown in Figure 7. outputs of these comparators are then connected
With reference to the Figure, the basic operation of the through the external logic gates, to produce the carrier-
circuit can be described as follows: The basic FSK de- detect or the enable/disable signal. The resulting logic
coding function, converting the incoming mark and output will be noramlly at a low state, and will go high
space signals at frequencies fR1 and fR2, is performed only when the carrier signal, fRO, is present. This logic
in the same manner as in the bi-state case, and the re- signal is normally used for transmitter enable/disable
sulting output is available at Pin 7 of XR-2211. Pin 7 is control, as shown in Figure 2.
connected to the tone-detect output, and then gated by
the complement of the carrier-detect output. Thus, the The logic level changes, at the external comparator out-
data output terminal will be enabled only when the mark puts, correspond to mark-to-carrier or space-to-carrier
and space frequencies are present, but not when the frequency shifts (see Figure 8); thus, these outputs can
receive-carrier, fRO, is present. be utilized as optional dual-mode monitor outputs, D1
and D2 of Figure 2.
The external voltage comparators shown in Figure 7 are
added to the circuit to distinguish PLL output voltage
levels corresponding to various input frequencies. The I- TOTAL TRACKING BANDWIDTH-l
function of the XR-2211 frequency-to-voltage transfer
characteristics can be understood by referring to Pin 11 I--~I ~I--l
in Figure 8. The voltage levels and polarities shown are
relative to the XR-2211 internal reference voltage, V1Q,
at Pin 10. The mark and space frequencies, fR1 and
fR2' generate the maximum dc level shifts. VR1 and
1
:;
VA1
VA
VR2, sensed by the internal FSK comparator (see Fig-
>
ure 5) which is internally biased from the reference volt-
age, V1Q.

The external comparators, Compo A and Compo B of Fig-

ure 7, are biased at voltage levels, VA and VB, approxi-
mately halfway between VR1 and VR2, to trip at fre-
quencies fA and fB, which are halfway between mark-
to-center and space-to-center frequency shifts. This
biasing is achieved with the external resistive dividers,
RA, RB, RX, and Ry of Figure 7, which generate the ref- - - - - - - INPUT SIGNAL FREQUENCY

erence voltage levels, VA and VB, with respect to the

XR-2211 internal reference at Pin 10. It should be noted Figure 8. XR-2211 Frequency-to-Voltage Transfer
that the value of the resistors (RA + RB) and (RX + Ry) Characteristics. (Note: V11 and V10 are
must be as large as possible (typically in excess of 100 the dc voltage levels at Pins 11 and 10,
kO) to avoid disturbing the voltage level at Pin 10. respectively. )

11-40
 AN-06
Precision PLL System using
the XR·2207 and the XR·2208
INTRODUCTION
The phase-locked loop (PLL) is a versatile system block,
suitable for a wide range of applications in data com-
INPUT
SIGNAL -VS(t)
PHASE
COMPARATOR
V.(t)
t-------
LOW PASS
FILTER
.'-'

munications and signal conditioning. In most of these

applications, the PLL is required to have a highly stable
and predictable center frequency and a well-controlled Vo(t)
bandwidth. Presently available monolithic PLL circuits '0 Vd
often lack the frequency stability and the versatility re- VCO

quired in these applications.

This application note describes the design and the ap- Figure 1. Block Diagram of a Phase-Locked Loop.
plication of two-chip PLL system using the XR-2207 and
the XR-2208 monolithic circuits. The XR-2207 is a preci-
sion voltage controlled oscillator (VeO) circuit with ex- the veo to synchronize or "lock" with the incoming sig-
cellent temperature stability (± 20 ppm/oe, typical) and nal. Once in lock, the veo frequency is identical to the
linear sweep capability. The XR-2208 is an operational input signal, except for a finite phase difference.
multiplier which combines a four quadrant multiplier
and a high gain operational amplifier in the same pack- Two key parameters of a phase-locked loop system are
age. Both circuits are designed to interface directly its "lock" and "capture" ranges. These can be defined
with each other with a minimum number of external as follows:
components. Their combination functions as a high per- Lock Range = The band of frequencies in the vicinity
formance PLL, with the XR-2207 forming the veo sec- of fo over which the PLL can maintain lock with an input
tion of the loop, and the XR-2208 serving as the phase- signal. It is also known as the "tracking" or "holding"
detector and loop amplifier. range. Lock range increases as the overall loop gain of
the PLL is increased.
As compared with the presently available single-chip Capture Range = The band of frequencies in the vicini-
PLL circuits such as the XR-21 0 or the Harris HI-2820, ty of fo where the PLL can establish or acquire lock with
the two-chip PLL system described in this paper offers an input signal. It is also known as the "acquisition"
approximately a factor of 10 improvement in tempera- range. The capture is always smaller than the lock
ture stability and center frequency accuracy. The sys- range. It is related to the low pass filter bandwidth and
tem can operate from 0.01 Hz to 100 kHz, and its per- decreases as the low pass filter time constant in-
formance characteristics can be tailored to given de- creased.
sign requirements with the choice of only four external
components. The PLL responds to only those input signals sufficient-
ly close to the veo frequency, fO, to fall within the
DEFINITIONS OF PLL PARAMETERS "lock" or "capture" ranges of the system. Its perform-
ance characteristics, therefore, offer a high degree of
The phase-locked loop (PLL) is a unique and versatile frequency selectivity, with the selectivity characteris-
feedback system that provides frequency selective tun- tics centered about fO. Figure 2 shows the typical
ing and filtering without the need for coils or inductors.

•
frequency-to-voltage transfer characteristics of the
It consists of three basic functional blocks; phase com- PLL. The input is assumed to be a sine wave whose fre-
parator, low-pass filter, and voltage-controlled oscillator, quency is swept slowly, over a broad frequency range
interconnected as shown in Figure 1. With no input sig- covering both the "lock" and the' "capture" ranges of
nal applied to the system, the error voltage, Vd, is equal the PLL. The vertical scale corresponds to the filtered
to zero. The veo operates at a set "free-running" fre- loop error voltage, Vd, appearing at the veo control ter-
quency, fo. If an input signal is applied to the system, minal.
the phase comparator compares the phase and fre-
quency of the input signal with the veo frequency and As the input frequency, fS, is swept up (Figure 2(a)) the
generates an error voltage, Ve(t) , that is related to the system does not respond to the input signal until the in-
phase and frequency difference between the two sig- put frequency reaches the lower end of capture range,
nals. This error voltage is then filtered and applied to feL. Then, the loop suddenly locks on the input signal,
the control terminal of the veo. If the input signal fre- causing a positive jump in the error voltage Vd. Next,
quency, fS, is sufficiently close to fo, feedback causes Vd varies at a slope equal to the reciprocal of veo

11-41
 AN-06
j+-.lll-j PRECISION PLL USING XR-2207 AND XR-220B
(+) The XR-2207 VCO and the XR-2208 operational multipli-
er can be inter-connected as shown in Figure 3, to form
Ir-----'--'~-__._------ FREQUENCY
a highly stable PLL system. The circuit of Figure 3 oper-
_ INCREASING
FREQUENCY I.
ates with supply voltages in the range of + 12V to
(-) + 26V; and over a frequency range of 0.01 Hz to 100
(a) kHz. In the PLL system of Figure 3, all the basic per-
'll ICl '0 ICH 'lH formance characteristics of the PLL can be controlled
I I I I I and adjusted by the choice external 4 components
identified as resistors RO and R1' and the capacitors Co
(+)
and C1, Co and RO control the VCO center frequency;
R1 and C1 determine the tracking range and the low
Vd 0 I---"Ir--'-----''''r---r-------- FREQUENCY pass filter characteristics. The two-chip PLL system
- - - DECREASING
FREQUENCY I. can be readily converted to split supply operation by
(-)
(b)
inter-connecting the circuit as shown in Figure 4. The
PLL circuit of Figure 4 operates over a supply voltage
Figure 2. Frequency to Voltage Transfer Characteristics of a range of ± 6 volts to ± 13 volts.
PLL System; (a) Increasing Input Frequency; (b)
Decreasing Input Frequency. For best results, the timing resistor RO should be in the
range of 5k to 100k, and R1 > RO' Under these condi-
voltage·to-frequency conversion gain, (K v), and goes tions, the basic parameters of the PLL can be easily
through zero at fs = fO. The loop tracks the input fre- calculated from the design equations listed in Table 1.
quency until fs reaches the upper edge of the lock
range, fLH. Then the PLL loses lock, and the error volt- Design Example
age drops to zero. If the input frequency is swept back
As an example, consider the design of a PLL system us-
slowly, from high towards low frequencies the cycle re-
ing the circuit of Figure 3, to meet the following nominal
peats itself, with the characteristics shown in Figure
2(b). The loop captures the signal at the upper edge of performance specifications:
the capture range, fCH, and tracks it down the lower a) Center Frequency = 10kHz
edge of the lock range, fLL. With reference to the fig-
b) Tracking Range = 20% (9 kHz to 11 kHz)
ure, the "lock" and the "capture" ranges can be de-
c) Capture Range = 10% (9.5 kHz to 10.5 kHz)
fined as:
Solution:
Lock Range = .::lfL = fLH - fLL
Capture Range = .::lfC = fCH - fCL a) Set Center Frequency:
Choose RO = 10k (Arbitrary choice for
The gain parameters associated with the PLL are de-
5k< RO< 100k)
fined as follows:
Then, from equation 1 of Table 1:
Phase Detector Gain, K<p: Phase detector output per unit of
phase difference between the two signals appearing at Co = (1!fORO) = 0.01 JLF
the phase detector inputs. It is normally measured in
volts per radian. b) Set Lock Range:
From equation 2 of Table 1:
VCO Conversion Gain, Kv: VCO frequency change per unit
of input voltage. It is normally measured in radians! R1 = (0.45) RO = 45k
sec.lvolt.
c) Set Capture Range:
Loop Gain, KL: Total d c gain around the feedback loop. It Since capture range is significantly smaller than
is equal to the product of K<p and Kv. Lock range, equation 8(a) applies.
Loop Damping Factor, r.
Defines the response of the loop Solving equation 8(a) for C1, one obtains:
error voltage Vd, to a step change in frequency. If t< 1,
the loop is underdamped; and the error voltage Vd will C1 = 0.032 JLF
exhibit an underdamped response for a step change of
signal frequency. PRECISION SINE WAVE OUTPUT PLL USING XR-220B
AND XR-2206
The lock range of the phase-locked loop is controlled by
the loop gain, KL. The capture range and the damping The interconnection of the XR-2208 and XR-2206 as
factor are controlled by both the loop gain and the low shown in Figure 5 forms a precision phase·locked loop
pass filter. system with a sine wave output. The phase-locked loop

11-42
characteristics are adjusted with the same four exter-
AN·OS
typically 2.5 % unadjusted with R4 == 2000 and R5
nal components as previously described. Equation 2 in open, and 0.5% adjusted using R4 and R5. Sine wave
Table 1 is modified to: amplitude is adjusted by R3 with the conversion gain
equalling typically:
(2) Lock Range (~fL/fO) == (0.5) (RO/R1)

This change is because the reference of the XR-2206 is 60mVp_p

internally set. The clamp network with 01 has been
KO of R3
added to adjust the swing to the VCO to compensate for
this reference. The sine wave characteristics are ad- The phase-locked loop input characteristics allow lock-
justed by R4 and R5, which adjust sine-shaping and ing to input signal levels of 50 mV RMS to 2V RMS.
symmetry respectively. Sine wave distortion levels are
Table 1
Phase-locked loop Design Equations·

(1) Center Frequency: fO == _1- Hz (7) Loop Damping: == _1_ == ~ 2CO

ROCO 2~KL C1

(2) Lock Range: (~fL/fO) == (0.9)(RO/R1)

(8) Capture Range:

(3) Phase Detector Gain: K¢ == 0.5 VCC volts/radian a) Underdamped Loop (t< 1/2):
Where VCC == V + for split supply; VCC == V + /2
for single supply.
(~fc/fO) R
== 0.8 O
Co
-
R1 C1
(4) VCO Conversion Gain:
b) Overdamped Loop (t> 1):
KV == 1 rad/sec/volt
2 VCCCOR1 (~fc/fO) == 0.8(RO/R1)

(5) Loop Gain: KL = K¢KV = 0.25 sec - 1

COR1 *See Figures 3 and 4 for component designation.

(6) Low Pass Filter Time Constant: T == C1 R1 sec.

2

y+ V+ 5.1K 10K

y+

5.1K
SQUARE WAVE
5.1K OUTPUT

:>--+--013 J1J
2K
"----+---0 14

5.1K
RO

12
M TRIANGLE
OUTPUT

5.1K
Cc

0-----1
SIGNAL
INPUT
5.1K

Cc '" COUPLING CAPACITOR

CB '" BYPASS CAPACITOR

Figure 3. Circuit Interconnections for Single Supply

Operation.

11-43
AN·06
V+

10K 16
SQUARE WAVE
10K OUTPUT

lK
rLfl
13

S:~~~~ 0---1 t-~.---,

Cc 8 9
XR·2208

10
1 Cl

RO
14
M TRIANGLE
OUTPUT

V- V-

Figure 4. Circuit Interconnections for the Precision PLL System using the XR-2207 and the XR-2208 Monolithic Circuits.
(Split-Supply operation, ± 6V to ± 13V.

+12V
,..
5.1K

.-- R3l:
-ir->o
~

5.1K
16
<> 1 ) 2 >13 )
14
25K
4
)
5 6
5.1K

20K
<~I-
5 r----..... -r--.
INPUT
SIGNAL
e>--1 II

~~
, 2K

I
4

,..3
X
I""""~-
1>
XR·2208
11
'"'
2K

Ql
2N2904l
>~
Rl Rl
7

- / "
VCO
'1'
......

XR·2206
~i
11

2
-
SQUARE WAVE
'"' OUTPUT
SINE WAVE
OUTPUT

',~";Jr,
6 7 8 9 10 ,-Cl
> <> <) 12
=~l"F
) ~ Ro 10K
5.1K
'-- '- 40K

l"F
R5 500 R4
GND '"'

--
Figure 5.

11-44
 AN-07

Single-Chip Frequency Synthesizer

Employing the XR-2240
INTRODUCTION
The XR-2240 monolithic timerlcounter contains an 8-bit set frquency, fS (fs = 1/RC), where Rand C are the ex-
programmable binary counter and a stable time-base ternal components at pin 13. The 8-bit binary counter
oscillator in a single 16-pin IC package. Although the can be programmed to divide the time-base frequency
circuit was originally designed as a long-delay timer ca- by an integer count, N, and generate an output pulse
pable of generating time delays from microseconds to train whose frequency is:
weeks, it also offers a wide range of other applications
beyond simple time-delay generation. One such unique 1
application is its use as a single-chip, frequency syn- fa = fS--
thesizer, where it can generate over 2,500 discrete fre- 1 + N
quencies from a single reference frequency input.

The operation of the XR-2240 as a frequency synthesiz- Frequency Multiplication by "M":

er is possible because of the ability of the circuit to both
multiply and divide the input frequency reference. It Frequency multiplication is achieved by synchronizing
can, simultaneously, multiply the input frequency by a the time-base oscillator with the harmonics of the input
factor, "M," and divide it by a factor "N + 1," where sync or reference Signal. Thus, if the time-base oscilla-
both M and N are adjustable integer values. Therefore, tor is made to free-run at "M" times the input frequen-
the circuit can produce an output frequency, fo, related cy, it can be made to synchronize the "M"th harmonic
to the input reference frequency fR as: of the input reference signal. Typical capital range of
the circuit is better than ± 3 %, for values of 1 ::::; M::::; 10;
M and since the time-base is accurate to within ± 0.5 % of
f = fR-- the external R-C setting, lock-up does not present a
o 1 + N problem for a given harmonic lock setting.

Figure 1 shows the circuit connection for operating the

XR-2240 timerlcounter as a self-contained frequency A
synthesizer. The integer values M and N can be exter- ,-----'--------
lK Rl
nally adjusted over a broad range:

1 ::::; M ::::; 10 1::::; N ::::; 225

The multiplication factor M is obtained by locking on the

harmonics of the input frequency. The division factor N
is determined by the pre-programmed count in the bina-
ry counter section. The principle of operation of the cir-
cuit can be best understood by briefly examining its ca-
pabilities for frequency division and multiplication sepa-
rately.

Frequency Division by (1 + N):

When there is no external reference input, fR, the time-
base oscillator section of the XR-2240 free-runs at its Figure 1

11-45
AN·07
Circuit Operation: circuit to maintain a periodic output waveform. For the
component values shown in Figure 1, the circuit can
With reference to Figure 1, the operation of the synthe- operate with the timing components Rand C in the
sizer circuit can be briefly explained as follows: The ref- range of:
erence input frequency, fR, is applied to the time-base
sync terminal (pin 12) through a 5.1 KO series resist- 0.005 J.tF=:;;C=:;;.1 J.tF; 1 KO=:;;R=:;; 1 MO
ance and a coupling capacitor. The recommended
waveform for the input frequency, fR, is a 3 Vpp pulse The XR-2240 is a low-frequency circuit. Therefore, the
maximum output frequency is limited to ,., 200 kHz, by
train with a pulse width in the range of 30 % to 80 % of
the time-base period, T. The multiplication factor M is the frequency capability of the internal time base oscil-
lator.
chosen by the potentiometer R1 which sets the time-
base period T (T = RC). If no external reference is used,
A particularly useful application of the simple synthesiz-
then M is automatically equal to 1.
er circuit of Figure 1 is to generate stable clock fre-
quencies which are synchronized to an external refer-
The divider modulus, N, is chosen by shorting various
counter outputs to a 3K common pull-up resistor. The ence, such as the 60 Hz line frequency. For example,
output waveform is a pulse train with a fixed pulse one can generate a 100 Hz reference synchronized to
width, T = RC, and a period TO = (N + 1)RC. 60 Hz line frequency simply by setting M = 5 and N =
2 such that:
The external R-C network between the output and the
trigger and reset terminals of the XR-2240 is a non- M 5
critical delay network which resets and re-triggers the
fo = fR - - = (60)-- = 100 Hz
1+N 1+2

11-46
 AN·OS
Dual Tone Decoding with
XR·567 and XR·2567
INTRODUCTION
+y +y
Two integrated tone decoders, XR-567 units, can be
connected (as shown in Figure 1A) to permit decoding
of simultaneous or sequential tones. Both units must be RL
on before an output is given. R1C1 and R'1C'1 are cho- TONE 1 20 K
sen, respectively, for Tones 1 and 2. If sequential tones DECODER 8 t--+-----,

(1 followed by 2) are to be decoded, then C3 is made

very large to delay turn-off of Unit 1 until Unit 2 has
turned on and the NOR gate is activated. Note that the
wrong sequence (2 followed by 1) will not provide an 1/48005
output since Unit 2 will turn off before Unit 1 comes on.
Figure 1B shows a circuit variation which eliminates
the NOR gate. The output is taken from Unit 2, but the
0---1 C2 C3

*~
Unit 2 output stage is biased off by R2 and CR1 until ac-
INPUT
I
tivated by Tone 1. A further variation is given in Figure +y +v '. 8005

1C. Here, Unit 2 is turned on by the Unit 1 output when

Tone 1 appears, reducing the standby power to half. R2 20K
Thus, when Unit 2 is on, Tone 1 is or was present. If TONE 2
Tone 2 is now present, Unit 2 comes on also and an out- DECODER
put is given. Since a transient output pulse may appear 5 6
+v +v
-=-

TONE 1
DECODER I II
Figure 1A. Detection of Two Simultaneous or
Sequential Tones
+v +v

INPUT
I-=- +v I- I +v
OUTPUT
-
t INPUT
5 6 7 2 1

0---) +v
TONE 2
DECODER
OUTPUT
TONE 1
DECODER
7
-=- 5 6 2 1

I II I II
-=-
Figure 1B Figure 1C

11-47
AN·08
DIGIT

III

III

0-1
0.546

III

III

COMPONENT VALUES (TYPICAL)

R, 6.8 to '5 K ohm
R2 4.7 K ohm
R3 2.0 K ohm
C, 0.' mId
C2 1.0 mId 6 V
C3 2.2 mId 6 V
C4 250 6 V

Figure 2. Low-Cost Touch Tone@ Decoder

11-48
during Unit 1 turn-on, even if Tone 2 is not present, the
AN-OS
the R2 resistors of the two 567's which are being acti-
load must be slow in response to avoid a false output vated. Capacitor C4 (optional) decouples the ac cur-
due to Tone 1 alone. rents at the common pOint.

The XR-2567 Dual Tone Decoder can replace two inte- LOW COST FREQUENCY INDICATOR
grated tone decoders in this application.
Figure 3 shows how two tone decoders set up with
overlapping detection bands can be used for a go/no/go
HIGH SPEED, NARROW BAND TONE DECODER frequency meter. Unit 1 is set 6 % above the desired
sensing frequency and Unit 2 is set 6% below the de-
The circuit of Figure 1 may be used to obtain a fast, nar-
sired frequency. Now, if the incoming frequency is with-
row band tone decoder. The detection bandwidth is in 13 % of the desired frequency, either Unit 1 or Unit 2
achieved by overlapping the detection bands of the two will give an output. If both units are on, it means that the
tone decoders. Thus, only a tone within the oveJlap por-
incoming frequency is within 1 % of the desired fre-
tion will result in an output. The input amplitude should
quency. Three light bulbs and a transistor allow low
be greater than 70 mV rms at all times to prevent detec-
cost read-out.
tion band shrinkage and C2 should be between 130/fo
+V
and 1300/fo mfd where fo is the nominal detection fre-
quency. The small value of C2 allows operation at the
maximum speed so that worst-case output delay is only
about 14 cycles.

TOUCH-TONE DECODER
ON
FREOUENCY
Touch-Tone decoding is of great interest since all sorts
of remote control applications are possible if you make
use of the encoder (the push-button dial) that will ulti-
mately be part of every tone. A low-cost decoder can be INP~
made as shown in Figure 2. Seven 567 tone decoders, 100·1000 mV rms I II
their inputs connected in common to a phone line or
-=-
acoustical coupler, drive three integrated NOR gate
HIGH
packages. Each tone decoder is tuned, by means of R1
and C1, to one of the seven tones. The R2 resistor re-
duces the bandwidth to about 8 % of 100 mV and 5 % at
50 mV rms. Capacitor C4 decouples the seven units. If 5 6 2 1

you are willing to settle for a somewhat slower re-

sponse at low input voltages (50 to 10 mV rms), the
bandwidth can be controlled in the normal manner by
selecting C2, thereby eliminating the seven R2 resistors
and C4. In this case, C2 would be 4.7 mfd for the three
lower frequencies or 2.2 mfd for the four higher fre-
quencies.

The only unusual feature of this circuit is the means of

bandwidth reduction using the R2 resistors. As shown
in the 567 data sheet under Alternate Method of Band-
width Reduction, the external resistor RA can be used
to reduce the loop gain and, therefore, the bandwidth.
Resistor R2 serves the same function as RA except that

•
instead of going to a voltage divider for dc bias it goes SENSING
CENTER FREOUENCY
to a common point with the six other R2 resistors. In ef-
fect, the five 567's which are not being activated during Figure 3. Frequency Meter with Low-Cost Lamp
the decoding process serve bias voltage sources for Readout

11-49
 AN-09

Sinusoidal Output from XR·215

Monolithic PLL Circuit
INTRODUCTION
In a wide range of communication or signal condition- system is formed by simply ac coupling the veo output
ing applications, it is necessary to obtain a sinusoidal to either of the phase comparator inputs and adding a
output signal which is synchronized to a desired refer- low-pass filter to the phase comparator output termi-
ence or clock input. This can be achieved by using the nals. The XR-215 can operate over a large choice of
XR-215 type monolithic PLL circuit and an additional power supply voltages ranging from 5 volts to 26 volts
sine-shaping network. and a wide frequency band of 0.5 Hz to 35 MHz. It can
accommodate analog signals between 300 microvolts
When a periodic input signal is present within the cap- and 3 volts and can interface with conventional DTL,
ture range of the XR-215 PLL, the system will lock on TIL and EeL logic families.
the input; and the veo section of the PLL will synchro-
nize with the input frequency. The output of the oscilla- Figure 2 shows the simplified circuit schematic of the
tor section of the PLL can then be converted to a low XR-215 phase-locked loop Ie. The veo part of XR-215,
distortion sine wave by a relatively simple sine-shaping shown in the center section of Figure 2, is an emitter-
circuit. coupled multivibrator circuit, whose frequency is set by
an external capacitor, eO, connected across the timing
terminals (Pins 13 and 14). In this type of an oscillator,
GENERAL DESCRIPTION
the differential voltage waveform across the timing ca-
Figure 1 contains a functional block diagram of the XR- pacitor, eO, is a linear triangle, with a peak-to-peak am-
215 monolithic PLL system. The circuit consists of a plitude of 1.4 volts. This output amplitude across the
balanced phase comparator, a highly stable voltage- timing capacitor is independent of supply voltage.
controlled oscillator (VeO) and high speed operational
This triangular waveform can be shaped into a low dis-
amplifier. The phase comparator outputs are internally
tortion sine wave by passing it through a simple differ-
connected to the veo inputs and to the non-inverting
ential gain stage, as shown in Figure 3. By adjusting the
input of the operational amplifier. A self-contained PLL
potentiometer Rg of Figure 3, the input transistors
T 1and T2 of the differential stage can be brought to the
verge of cutoff at the positive and the negative extremi-
PHASE VCO ties of the input triangle wave. This causes the peaks of
COMPARATOR RANGE TIMING
• Vee OUTPUTS SELECT CAPACITOR the triangle waveform to be rounded, resulting in a
nearly sinusoidal output waveform from the differential
stage. If the transistor characteristics and the current
levels in the differential gain stage are well matched,
one can reduce the total harmonic distortion (THD) of
PHASE the sinusoidal output waveform to less than 3 %.
COMPARATOR
INPUTS L----l1-'2{) ~NC~U~WEEP
The sine-stlaper circuit of Figure 3 can be designed by
PHASE L-_-+-":o ~~~~:~~ using the XR-D101 NPN transistor array, which pro-
COMPARATOR CJ...=-J---...J
BIAS vides five identical NPN transistors in a single Ie pack-
age. Figure 4 shows the package diagram of XR-D101
chip, in terms of its 16-pin DIP package.

OPAMP The five independent transistors contained in the XR-

OUTPUT
OPAMP
D101 transistor array can be interconnected, as shown
COMPENSATION in Figure 5, to form the differential sine wave-shaping
circuit of Figure 3. The inputs of the sine-shaper can be
Figura 1. Functional Block Diagram of XR·215 directly connected to the timing capacitor terminals
Monolithic PLL Circuit (Pins 13 and 14) of the XR-215 PLL.

11·50
 AN·09 16

I .o--______
t-o P~:~.E -------1+1..1-------VCO-------1~14g----- OP. AMP. -----I~I

Figure 2. Simplified Schematic of XR-215

,...---------__<1-----0 V+ (12 V)

5.1 K

~
FROMINPUTl
PINS
13 AND 14
OF
XR-215 -_IIK>-----{
NV SINUSOIDAL
OUTPUT

•
12 K
. - - - - -.....-..J\"IV\,---O V + (12 V)

1K

Figure 3. A Simple Triangle-to-Sine Wave Converter Using a Differential Gain Stage

11-51
AN-09
OPAMP
INPUT

PHASE
I VCO OUTPUT

COMPARATOR
OUTPUTS

l l
VCO
TIMING
CAPACITOR
PHASE
COMPARATOR
INPUTS J
PHASE
VCO SWEEP
COMPARATOR
INPUT
BIAS

PHASE
VCO GAIN
COMPARATOR
CONTROL
INPUTS

OPAMP RANGE
COMPENSATION SELECT

OPAMP
OUTPUT

PIN 8 = SUBSTRATE

Figure 4. Package Diagram for XR-D101 Matched NPN Transistor Array

WAVE FROM ADJ.·

14

5.1 K

FROM PINS XR-D101

13 AND 14
OF 16
XR-215 NPN
15 TRANSISTOR ARRAY
SINUSOIDAL
OUTPUT

10 12 11
12 K
V+(12V)o---~~~---<r-----~----+---~

"."~

·ADJUST RQ FOR MINIMUM HARMONIC DISTORTION.

Figure 5. Use of XR-D101 Transistor Array to Obtain Sinusoidal Output from XR-215 PLL

11-52
 AN-10
XR·C262 High·Performance
PCM Repeater IC
INTRODUCTION
The XR-C262 is a monolithic repeater circuit for Pulse- SIGNAL FLOW - - - -
Code Modulated (PCM) telephone systems. It is de-
signed to operate as a regenerative repeater at 1.544
Megabits per second (Mbps) data rates on T-1 type PCM
lines. It is packaged in a hermetic 16-pin CERDIP pack-
age and is designed to operate over a temperature
II
range of -40°C to + 85°C. It contains all the basic func-
tional blocks of a regenerative repeater system includ-
ing Automatic Line Built-Out (ALBO) and equalization,
"
and is insensitive to reflections caused by cable discon-
tinuities.

The XR-C262 operates with a single 6.8-volt power sup-

ply, and with a typical supply current of 13 mAo It pro- ~II lie
vides bipolar output drive with high-current handling ca-
_ - - - SIGNAL FLOW
pability. The clock extractor section of XR-C262 uses
the resonant-tank circuit principle, rather than the
injection-locked oscillator technique used in earlier Figure 1. Block Diagram of a Bi-Directional Digital
monolithic repeater designs. The bipolar output drivers Repeater System.
are designed to go to "off" state automatically when
there is no input signal present. Compared to conven- can operate on either pulp- or polyethylene-insulated
tional repeater designs using discrete components, the paired cable that is either pole-mounted or buried. Op-
XR-C262 monolithic repeater IC offers greatly improved eration is possible with a variety of wire gauges, provid-
reliability and performance and provides significant ed that the total cable loss at 772 kHz is less than 36
savings in power consumption and system cost. dB. Thus, the system can operate satisfactorily on near-
ly all paired cables which are used for voice frequency
This application note outlines the basic design princi-
trunk circuits.
ples and the electrical characteristics of the XR-C262
monolithic repeater IC. In addition, circuit connections The T-1 type transmission system is designed to oper-
and applications information are provided for its utiliza- ate with both directions of transmission within the same
tion in T-1 type 1.544 Megabit PCM repeater systems. cable sheath. The system performance is limited pri-
marily by near-end cross-talk produced by other sys-
FUNDAMENTALS OF PCM REPEATERS tems operating within the same cable sheath. In order
to insure that the probability of a bit error is less than
The Pulse-Code Modulation (PCM) telephone systems
10- 6 , the maximum allowable repeater spacing, when
are designed to provide a transmission capability for
used with 22-gauge pulp cable, is approximately 6000 ,
multiple-channel two-way voice frequency Signals feet.
which are transmitted in a digital PCM format. In order
to minimize error rates, and provide transmission over
The XR-C262 monolithic IC replaces about 90% of the

II
long distances, this digital Signal must be regenerated electronic components and circuitry within the digital
at periodiC intervals, using a regenerative repeater sys-
repeater sections of Figure 1. Thus, a bi-directional re-
tem. Figure 1 shows the block diagram of a bi-
peater system should require two XR-C262 ICs, one for
directional PCM repeater system consisting of two
each direction of information flow.
identical digital regenerator or repeater sections, one
for each direction of transmission. These repeaters
OPERATION OF THE XR-C2S2
share a common power supply. The DC power is sim-
plexed over the paired cable and is extracted at each The XR-C262 monolithic repeater is packaged in a 16·
repeater by means of a series zener diode regulator. pin dual-in-line hermetic package, and is fabricated us-
In the United States, the most widely used PCM tele- ing bipolar process technology. The functions of the cir-
phone system is the T-1 type system which operates at cuit terminals are defined in Figure 2, in terms of the
a data rate of 1.544 Mbps, with bipolar data pulses. It monolithic Ie package.

11-53
AN·10 blocks shown within the dotted area are included on the
XR·C262
monolithic chip. The numbers on the circuit terminals
correspond to the pin numbers of the 16-pin IC package
containing the repeater chip. In terms of the system
block diagram of Figure 3, the overall repeater opera-
tion can be briefly explained as follows.

The bipolar PCM signals which are attenuated and dis-

torted due to the preceding transmission medium are
applied to the input of a preamplifier (Block 1) through
an Automatic Line Build-Out (ALBa) circuit. The imped-
ance, Z1, corresponds to the passive section of the AL-
Ba network. The preamplifier section, along with the
passive equalizer networks Z2 and Z3 connected in
feedback around it, provides gain to compensate for
line losses and band-limiting to reject unwanted noise
as well as gain and phase equalization to shape re-
ceived pulses.

The ALBa circuitry provides attenuation and shaping to

automatically adjust for varying cable characteristics.
The output of the preamplifier is controlled to swing be-
tween two established peak levels. This is accom-
Figure 2. Package Diagram of XR-C262 Monolithic PCM plished by feedback circuitry, and is similar in concept
Repeater. to automatic gain control. When the preamplifier output
passes through the peak thresholds it is detected by
A more detailed system block diagram for the monolith- the peak detector (Block 2) and produces a Signal
ic repeater system is given in Figure 3. The system which is used to control a feedback loop establishing

PCM INP:T~ II
SIGNA~

CTR. TAP

CB = BYPASS CAP.
I CB
INPUT

CB = COUPLING CAP.
- 0-t-
I
I 0-t-
ANALOG

+vcc 0--+--
, IIDIGITAL
XH-C:lb:l
I
rO
MONOLITHIC REPEATER
~ :~~ENERATED
IANALOG I COUTPUT

GROUND
{
&+-,
DIGITAL I
DRIVER
(13)
'

L ______________ J
Figure 3. Detailed Block Diagram of the XR-C262 Monolithic Repeater System.

11-54
the attenuation and shaping of the AlBO network. The DATA AND CLOCK
AN·10
THRESHOLDS
actual circuit design associated with this function is de-
scribed in more detail in the discussion of peak detec-
tion and AlBO circuitry.

The output of the preamplifier drives a set of data com-

parators which are internally biased from a voltage ref- PREAMP OUTPUT,
erence (Block 4) and the precision voltage divider net- "EYE" PATTERN
work (Block 5). Thus, the preamplifier output is "sliced"
at various voltage levels to eliminate the effects of the
baseline noise. This output is full-wave rectified and
amplified through Block 6 of Figure 3. The resulting sig-
nal has a strong Fourier component at the clock fre-
quency and is used to drive a high Q (::::::: 100) resonant
circuit tuned to that frequency. The output of the reso-

~
nant circuit is transformer-coupled to a zero-crossing
RESONATOR
detector and clock limiter (Block 10). The resultant out-
put is the desired recovered timing. This resonant cir- I I I I DRIVING
WAVEFORM
cuit is driven by a low impedance amplifier, and the re- I I I I
sulting clock edges are in phase with the peak of the re-
ceived pulses. I I I I
I I I I
The regeneration of the data is achieved through the
I I I I
two data comparators (Blocks 7 and 8) and the ECl I I
latches (Block 9) which function as tracking flip-flops.
The positive and negative data paths are separate; and,
I I I I
with the exception of the data limiter and slicer levels, I I I I
identical in design. The preamplifier output is sliced at I I I I RESONATOR
about 45 percent of the peak voltage and its amplitude OUTPUT
WAVEFORM
is limited to provide digital data pulses. The data is ap-
plied to one of the inputs to the tracking flip-flop, whose
I
state is latched and unlatched by the clock. During ac- I
quisition, the flip-flop acquires data; during hold, further I
data transitions are ignored and the state of the flip-flop
output determines whether an output pulse is transmit- I
ted. The implication of using the clock to perform data I
sampling is that path delays of the data and clock must CLOCK
LIMITER
be controlled to be equal. The monolithic integrated cir- WAVEFORM
cuit technology affords this control. The advantage of
this technique is that the need for clock shifting or
strobe pulse generating circuitry for accurate sampling Figure 4. Timing Diagrams of Voltage Waveforms within
alignment is eliminated. Actual circuit implementation the Clock Regeneration Section.
resulted in a 40-nsec misalignment of clock and data.
This 40-nsec error in sampling time amounts to less
than 0.4 dB degradation in SNR performance. Figure 4
shows the idealized timing and signal waveforms within es will not latch in the "on" state. When no input signal
the circuit. is present, the absence of clock is sensed and the out-
put drivers are held in the "off" state.
The output drivers use latched data and clock to pro-

•
duce an output pulse-width which is accurately con- Figure 5 shows a practical circuit connection for the
trolled by the duration of the clock. Non-saturating out- XR-C262 in an actual PCM repeater application for
put drivers (Blocks 12 and 13) insure that output pulse 1.544 Mbps T-1 repeater system. For simplification pur-
rise and fall times are less than 100 nsec. The zero in- poses, the lightening protection circuitry and the sec-
put shut-down circuitry (Block 11) guarantees that in ond repeater section for the reverse channel are not
the event incoming data disappears, the output switch- shown in the figure.

11-55
 AN·10 430 ",H

18 pF
SIGNAL
IN
/I
2 K!!

6.8 V 4.7 "F

NOTE
~ = ANALOG GROUND

m = DIGITAL GROUND

~0.47"F

Figure 5. A Recommended Circuit Connection Diagram for T-1 Type Repeater Application.

DESCRIPTION OF CIRCUIT OPERATION

data-comparator sections. The circuit exhibits a high
Preamplifier Section (Figure 6): differential input resistance ('" 106 ohms) and a low out-
put impedance ('" 80 ohms). It has a nominal voltage
The circuit diagram of the preamplifier section is shown gain of 69 dB at DC and ~ 50 dB at 1 MHz. The frequen-
in Figure 6. This section is designed as a single-stage cy response of the circuit exhibits a single-pole roll-off
characteristic.
high-gain amplifier with differential inputs and a single-
ended output. The amplifuer output is internally con- ANA~~~ __ --1~ ____________________----'

nected to the peak-detector, full-wave rectifier and the

01
ANALOG
+vcc----~--~--.----.--~~---.--~

+ PEAK
THRESHOLD
VOLTAGE
+ INPUT

ANALOG
BIAS

~~~~~~ ---.......--------........------------~
Figure 6. Circuit Diagram of Preamplifier Section. Figure 7. Circuit Diagram of the Peak-Detector and the
ALBO Sections.
11-56
Peak-Detector and ALBO Section (Figure 7): Threshold Circuitry (Figure 9):
AN·10
The peak-detector circuit is designed to detect the Threshold circuitry is a low impedance voltage-divider
peaks of the preamplifier output, provided that these circuit corresponding to Block 5 of Figure 3, and it es-
peaks exceed the internal detection threshold levels. tablishes the fixed levels required for data, clock and
This peak information is then low-pass filtered and is peak detection. It is important that the thresholds are
used to control the current in a diode string which acts insensitive to temperature variations, and that they are
as a variable-loss or "variolosser' element in a feed- of sufficiently low impedance to guarantee that there is
back path. In the circuit, the comparators conduct no threshold variation due to changing signal condi-
whenever the preamp output exceeds the ( + ) threshold tions. The reference voltages of the peak-detector, da-
in a positive direction or the (-) threshold in a negative ta, and clock thresholds are set by a resistor chain
direction. Transistor 05 then injects a pulse of current which divides down the voltage of the on-chip zener di-
into the ALBO filter. In the steady state, DC level across ode. The ratios of data threshold to peak-detector
the ALBO filter controls the current through the diode threshold and that of clock threshold to peak-detector
string; and the dynamic resistance of the diodes acts threshold are both set at 45 percent. In the actual cir-
as the variolosser element. The usable linear resist- cuit implementation, as shown in Figure 10, a com-
ance range in this application is almost three orders of pound connection of PNP's and NPN's are used to re-
magnitude ranging from 11 0 to """ 6 KO. duce the output impedance of the reference levels. The
currents through the NPN and PNP transistor strings
Data Latches (Figure 8): are set so as to insure that the base emitter voltage
drops of the NPN's and PNP's are nominally the same.
The data latches are required to be impervious to data The output impedance of the resulting reference volt-
transitions in the latch mode, and to be "transparent," age taps are about 300 ohms. The center tap of the buf-
(i.e., tracking the input data) during the tracking mode. fered divider is brought to a separate package terminal
Figure 8 shows the basic circuit configuration used in (Pin 14 of Figure 3) for biaSing the preamplifier input.
the XR-C262, which meets the above-mentioned per-
+Vcc
formance requirements. During the time when the
clock pulse is high, the acquisition transistors 01 and 9
ON·CHIP ZENER
02 are differentially switched with data transitions, and V+

the data is coupled to the respective bases of 03 and

04. When the clock pulse goes low at the sample time
(see Figure 4), the information is regeneratively latched
into 03 and 04. While the clock is low, further data tran-
sitions have no effect upon the state of the flip-flop. A Rl
more detailed description of the timing waveforms is
given in Figure 13.
DIGITAL Vcc
--~----~--------------~--~
R2

R3
03
04

R4

CLOCK --If------..:::..=...£
~a=2--t__ DATA

"Fo.....---t--Ci:OcK
RS

R6
•
DIGITAL
GROUND -=
Figure 8. Circuit Configuration for Tracking Data Figure 9. Internal Voltage-Divider Network for
Latches. Comparator Threshold Setting.

11-57
 AN·10

I 1 _ - . - ZERO-CROSSING -----J ~--___ LI .. ITER ~-=-

~
DETECTOR I I ..... PlIFIER

CLOCI(
..... PllFIER - - - - - - -

Figure 10. Circuit Diagram of the Clock Recovery Section.

Clock Recovery Section (Figure 10): PNP transistors is used to control the level of the clock
into the output switches. This technique uses the band-
Clock recovery circuity consists of a full-wave rectifier, pass characteristics of the timing recovery resonant
an external L-C resonant circuit, a zero crossing detec- circuit to reject out of band signals, thus minimizing the
tor, and limiting amplifier, as shown in Figure 10. The chance of producing output pulses with no input signal
fUll-wave rectifier circuit, comprising of cross-coupled and the presence of nOise. Figure 11 shows the basic
transistor pairs 01 through 04 has a net voltage gain of implementation of the zero-input protection circuit.
2, which is obtained by setting R1 = R2 = (1/2)R3. The 01 and 02 function as a simple retriggerable one-shot.
rectified output is then buffered by the Darlington The transistor 02 is a lateral PNP device with a limited
emitter-follower stage made up of 05 and 06, and ap- frequency capability and long storage-time delay. The
plied to the external L-C resonant circuit. 06 is operated existence of the 1.544 MHz clock causes 02 to satu-
at a high bias current level to provide an output imped- rate and remain in saturation while clock pulses are
ance of less than 150. This low impedance is required present. The comparatively long time constant associ-
to insure that the L-C tank-drive circuitry looks like a ated with 02 coming out of saturation (=:: 5 J'sec) in-
voltage source. sures that, when data is present, the zero input protec-
tion has no effect upon operation. When data disap-
The inductor of the resonant tank circuit is also a trans- pears there is no clock to ret rigger the one-shot, thus
former which couples the sine wave signal to the zero 02 comes out of saturation, causing 03 to saturate
crossing detector and limiting amplifier. The zero cross- which pulls the respective clock lines high, and dis-
ing detector is a differential amplifier with a nominal ables both output drivers in their "off" state.
voltage gain of 20 and input impedance of 4 MO. The
sine wave from the resonant circuit is sliced to produce +Vcc--~~-------.------------~~----~
a square wave with sharp transitions at the zero cross-
ings. This eliminates timing variations that may be
caused by amplitude changes of the sine wave signal.
The output of the zero crossing detector is further en-
hanced by the limiter which is another differential pair CLOCK ----If----~:.:.["

with a nominal voltage gain of 30. The output of this am-

plifier is a 1.5 V peak-to-peak square wave clock which
drives the data latches and the output drivers.

Zero-Input Protection Circuit (Figure 11):

The zero input protection circuitry accomplishes the
dual task of preventing the output switches from latch-
ing in an "on" state, as well as reducing the likelihood
of output pulses with no input signal. The data, clock,
and regenerator circuitry are all balanced DC coupled
circuits. Controlling the steady state, no-signal condi-
tion of these circuits without building an unacceptable
offset into the path is not practical. Instead, a retrigera- Figure 11. Zero-Input Shutdown Circuit for Output
ble one-shot that uses the saturation characteristics of Protection.
11-58
Output Drive Circuitry (Figura 12):
AN·10
the internal clock signals shown as Waveforms (7) and
(8). Waveform (9) shows the output of one of the data
The output drive circuitry is made up of two identical latches (Figure 8) as a function of the clock and data in-
channels as indicated in the block diagram of Figure 2. puts. The output of the latch tracks + DATA when the
The circuit configuration for each of these driver sec- clock is low, and stays latched in that condition when
tions is shown in Figure 12. The output would follow the the block goes high. The output drive at Pin 9, which is
data input from the latches only when the clock input is shown as Waveform (10) will then go low only when the
at a "high" state, i.e., with Q2 off and Q3 on. In this Waveforms (8) and (9) are low. Waveform (11) shows the
manner, the output pulse-width is controlled by the second output available at Pin 11. These two outputs
clock. To provide the fast turn-on and turn-off of the out- are then differentially combined by the output trans-
put drivers, all the transistors operate in a nonsaturat- former (see Figure 3) to provide the regenerated bipolar
ing state. Q4 forms an active clamp to reduce voltage output pulses shown in Waveform (1.2) of Figure 13.
swing at the base of Q6, and the clamp diode DS pre-
vents the saturation of the output driver Q7. Because of
the biasing scheme mentioned above, the amplitude of
the clock and the latched data are insensitive to supply (1)
PREAMP
OUTPUT
voltage and temperature changes. Thus, the variations
of the regenerated pulse-width over temperature and
supply are minimized.
(2) (+)OATA
INPUT -~-t----~----'r--'------'

(3) (+) DATA

DATA
LATCHES
(4)+-_ _..A
-----4 (-) DATA

(5)+-_ _'""1

LC-TANK
(II) +--+-"~-+-~r---+-----\~+-~-f--" ~~~~

(7)
CLOCK

(8)

Figure 12. Circuit Configuration for the Output Drivers. DATA LATCH
OUTPUT
(8)
Timing Waveforms (Figure 13): (+) DRIYER
OUTPUT
(PIN 8)
Figure 13 illustrates the relative time and phase rela-
(10)
tionships between the signal levels at various points
(-) DRIYER
within the circuit. For the purpose of illustration an input (11) ----1
..... OUTPUT
data pattern comprised of a string of "ONE"s is as- (PIN 11)

sumed, which looks like a nearly sinusoidal input after (12)

having traveled through a dispersive transmission me- BIPOLAR
dium such as a long cable. Waveform (1) is the output OUTPUT

II
FROM
of the preamplifier; Waveforms (2) through (5) are the lCMFR
outputs of the two data comparators driven by the pre-
amplifier output (see Figure 3). Waveform (6) is the low-
level clock signal obtained from the resonant tank cir-
cuit, at Pin 16 which is then amplified and sliced by the Figure 13. Timing Diagram of Circuit Waveforms for a
clock-recovery circuit (see Figure 11) and appears as 1·1·1 Input Data Pattern.

11-59
AN·10
ElECTRICAL CHARACTERISTICS + Vcc = 6.8 Volts, TA = - 40°C to + 85°C.
LIMITS
CHARACTERISTICS MIN. TYP. MAX. UNITS CONDITIONS
Supply Current
Digital Current 7 10 13 mA Measured at Pin 12
Analog Current 2 3.5 5 mA Measured at Pin 8
Total Current 13 17 mA

Preamplifier
Input Offset Voltage -15 +15 mV Measured between Pins 3 and 5
DC Gain 60 69 74 dB
Output High Level 4.3 V Measured at Pin 1
Output Low Level 0.5 V Measured at Pin 1

Clock Recovery Section

Clock Drive Swing (High) 5.1 V Measured at Pin 13
Clock Drive Swing (Low) 3.8 V Measured at Pin 13
Clock Bias 3.8 4 4.2 V Measured at Pin 15
Clock Source Input Current 0.5 4 p.A Measured at Pin 16

Comparator Thresholds Measured at Pin 1 relative to Pin 14

ALBO Threshold 0.75 0.9 1.1 V
Clock Threshold 0.323 0.4 0.517 V

Internal Reference Voltages

Reference Voltage 5.2 5.45 5.55 V Measured at Pin 2
Divider Center Tap 2.6 2.78 2.85 V Measured at Pin 14

ALBO Section
Off Voltage 10 75 mV Measured at Pin 7
On Voltage 1.2 1.7 V Measured at Pin 7
On Impedance 15 n Measured at Pin 7
Filter Drive Current 0.7 1 1.5 mA Drive current available at Pin 6

Output Driver Section Measured at Pins 9 and 11

Output High Swing 5.9 6.8 V RL = 400 n
Output Low Swing 0.6 0.7 0.9 V IL == 15 mA
Leakage Current 100 p.A Measured with output in off state
Output Pulse Width 294 324 354 nsec
Output Rise Time 100 nsec
Output Fall Time 100 nsec
Pulse Width Unbalance 15 nsec

ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION

Supply Voltage +10 V Part Number Package Operating Temperature

Power Dissipation 750 mW XR-C262 CERDIP - 40°C to + 85°C
Derate above + 25°C 6 mW/oC
Storage Temperature Range - 65°C to + 150°C

~:::::::: Ii
PACKAGE !NFORMATION

I• 1 '!?~
0.7SO
• I
f~~'
.L
0.135
(1.165

-11- ~ I- ~090
b 0.200

j~.'15 0.135

\.-0 to 15 0015
0.020 0.110
~ ~070
0.115

11-60
 EXf.i
" 1
;
1
R,
-,I
,;.
'
AN-11

A Universal Sine Wave Converter using the

XR·2208 and the XR·2211
INTRODUCTION tion then can be connected to a triangle-to-sine wave
converter which converts it to a low-distortion sine
A universal sine wave converter is a system block wave. The output of the triangle-to-sine converter is
which can convert any periodic input signal waveform then applied to a variable-gain amplifier which sets the
to a low-distortion sine wave, whose frequency is identi- desired output amplitude. Since the oscillator section of
cal to the repetition rate of the periodic input signal. the PLL is always running, the circuit also contains a
Such universal sine wave converters find applications "lock-detect" section which enables the output amplifi-
in communications and telemetry systems. They are er only when there is an input signal. Thus, with no in-
particularly useful for converting transducer output put signal present within the bandwidth of the PLL, the
waveforms, or pulses, into clean sine wave signals over lock-detect section will keep the output amplifier in the
a band of frequencies. This conversion to sine wave is "off" state, and the circuit will not produce an output
often necessary to reduce the required system band- signal.
width for signal transmission by eliminating the harmon-
ic frequencies of the signal.

In the cases where the input frequency is known, and ARBITR"RY

does not change, the universal sine wave converter PERIODIC

INPUT

can be replaced by a simple high-Q filter, tuned to the

input frequency. However, in many cases the input
frquency, or the repetition rate, is not constant, but var-
ies as a function of time or input data. In such cases a
fixed-frequency filter is not feasible, and one is forced
to use a universal sine wave converter which is essen-
tially a "tracking regenerative filter".
Figure 1. Basic Concept of a Regenerative Sinewave Converter.
In this application note, the design principle and the
performance characteristics of a regenerative sine
wave converter circuit is described. The circuit oper- CIRCUIT DESIGN
ates on the phase-locked loop (PLL) principle and can
be implemented using the XR-2211 monolithic PLL tone The basic regenerative sine wave converter system of
decoder and the XR-2208 multiplier IC. Figure 1 can be easily implemented using the XR-2211
monolithic tone decoder and the XR-2208 monolithic
PRINCIPLES OF OPERATION multiplier IC's, with only a minimum number of external
components.
Figure 1 shows the functional block diagram of a regen-
erative sine wave converter system, comprised of four The XR-2211 is a monolithic PLL circuit especially de-
functional blocks: (1) a phase-locked loop (PLL), (2) a signed for FSK and tone detection. Thus, it contains the
sine-shaper, (3) a keyed amplifier, and (4) a lock-detect complete PLL and lock-detect sections (Blocks 1 and 4 '
circuit. With reference to the figure, the principle of op- of Figure 1) on the same chip. Its overall block diagram •
eration of the entire system can be briefly explained as is shown in Figure 2. The circuit is packaged in a 14-pin
follows: dual-in-line package; and the functions of the circuit ter-
minals are given in Figure 3 in terms of the monolithic
When a periodic input Signal is present at the input, IC package. In the sine wave converter application, the
within the tracking range of the PLL, the circuit would FSK detector portion of the circuit is not used; only the
"lock" to the input signal; and the output of the voltage- basic phase-locked loop and the lock-detector sections
controlled oscillator (VCO) section of the PLL will dupli- are utilized. Figure 4 illustrates the necessary external
cate the frequency of the input signal. However, the components for its application in the sine wave con-
VCO output waveform will have a fixed wave shape verter system. The oscillator section of the XR-2211 is
(normally a triangle wave) independent of the input an emitter-coupled multivibrator which oscillates by
waveform or amplitude. The output of the oscillator sec- charging and discharging the external timing capacitor,

11-61
AN·11
+VCC
l
TIMING
CAPACITOR
INPUT
J
LOCK·DETECT TIMING
FILTER RESISTOR

LOOP
GROUND 9-DET.
OUT.
REF.
LOCK
DETECT
LOCK
DETECT LOCK
I Q VOL TAGE
FILTER COMP OUT.
DETECT
OUTPUTS

Figure 2. Block Diagram of XR-2211 Phase-Locked Loop FSK La

and Tone Decoder IC. DATA FSK
OUTPUT COMP.INPUT

Co' {connected across pins 13 and 14) through internal

constant-current stages. Thus, the output waveform, figure 3. Package Diagram of XR-2211 PLL Circuit.
taken differentially across the timing capacitor, is a lin-
ear triangle wave. This waveform can then be convert-
ed to a low-distortion sine wave by the XR-2208 multipli-
er.

The XR-2208 is a monolithic multiplier circuit which

contains a four-quadrant analog multiplier, an op amp,
and a unity-gain buffer amplifier in a 16-pin dual-in-line
package. Its functional block diagram and equivalent
circuit schematic are given in Figures 5 and 6, respec-
tively.

+VCC
MULTIPLIER Figure 4. External Circuit Connections for XR-2211 for Slne-
OUTPUTS HIGH FREQ. wave Converter Application.
L OUTPUT
X
INPUT
OP AMP
INPUTS
COMMON
J
Y
INPUT COMPo

OP AMP

Y-GAIN
r OUTPUT

l
X-GAIN X-GAIN

Figure 5. Diagram of XR-2208 Operational Multiplier. Figure 6. Simplified Circuit Schematic of the XR-2208
Operational Multiplier.

11-62
 AN·11
Figure 7 shows the recommended circuit connection of of the 500 kO potentiometer, RF The DC voltage level of
the XR-2211 and the XR-220B to form a universal sine the op amp output is set at the reduced supply voltage
wave converter circuit. In the figure, a non-crital zener (Le., Vcc - Vz)·
diode (V z :::::: 6V to 7V) is used to reduce the supply volt-
age applied to XR-2211, to facilitate DC coupling be- The lock-detect output of the XR-2211 (pin 6) is shorted
tween the two chips. The frequency of the VCO section to the mid-point of the resistive divider at pin 15 of the
of the XR-2211 is set by the timing components Ro and XR-220B. With no input signal present at the input with-
Co. In this application, a fixed value of Ro = 10KO is in the lock range of the XR-2211, pin 6 is at a "low"
recommended, giving a center frequency, fa value of: state. Thus it acts as a shorting switch to ground and
disables the op amp section of the XR-220B. When a
100 periodic input signal appears at the circuit input and the
fa = - - - H z XR-2211 establishes lock with the signal; the lock-
Co (JLF) detect output at pin 6 goes to a "high" or nonconduct-
ing state and enables the output op amp of the XR-
The triangle wave oscillator output of the XR-2211 PLL 220B; and a low-distortion sine wave output is obtained
is attenuated through a resistive divider made up of two at the output (pin 11 of XR-2208).
10KO resistors, and a variable 10KO potentiometer, Rx.
The attenuated triangle wave across Rx is then applied The circuit of Figure 7 can operate as a sine wave con-
differentially to the X-input (pins 4 and 5) of the XR- verter, over a frequency band between two frequencies
220B. The 1000 external resistor across Y-gain setting fH and fL corresponding to the upper and lower lock
terminals (pins 6 and 7) causes the Y-input of the multi- ranges of the PLL. With the components shown in the
plier to be slightly overdriven, and thus causes the figure, this corresponds to approximately ± 30% band-
peaks of the triangle input rounded into a low-distortion width around the center frequency, fa, for inputs with
sine wave. close to 50% duty cycle. For periodic inputs with less
than 50% duty cycle, this lock range is reduced further.
The distortion of the sine wave is minimized by adjust- For example, for inputs with 20% duty cycle, this band-
ing Rx , which sets the traingle wave amplitude. The out- width drops to about ± 10% of center frequency. The
put is available at the unity-gain buffer terminal (pin 15) operation of the circuit with input signals having less
of the XR-220B. This output is then level-shifted toward than 10% (or more than 90 %) duty cycle is not practi-
ground, through two 10KO resistors, and is AC coupled cal. The minimum input level required for circuit opera-
to the inverting input of the op amp section of XR-220B. tion is 10 mV rms. The ci rcuit can generate a nearly
The gain of the op amp is externally adjusted by means sinusoidal output with input signals from very low

Vz
6.7V
Vee = 15V

SINUSOIDAL
OUTPUT

•
RX ~ Distortion Adj. Potentiometer Cc ~ Coupling Capacitor
RF ~ Output Amplitude Adj. Pot. (;;;'0.1/lF)

Figure 7. Recommended Circuit Connection for the Regenerative Sinewave Converter.

11-63
AN·11
frequencies up -to 100 kHz. Typical distortion char- typical example of input and output waveforms for sine
acteristics of the output are shown in Figure 8, as a converter circuit of Figure 7, operating at 1 kHz input
function of frequency of operation. Figure 9 shows a repetition rate, with a noisy input signal.

VOUT' 3V, pp.

10kH:r 100kHl

FREOUENCY_

Figure 8. Output Distortion vs Frequency. Figure 9. Typical Input-Output Waveforms.

(Top: Noisy Input Signal; BoHom: Sinusoidal Output.)
Scale: Vertical: 1 Volt/Div.
Horizontal: 1 m Sec.lDiv.

11-64
 AN-12
Designing High-Frequency Phase-Locked
loop Carrier-Detector Circuits
INTRODUCTION
The phase-locked loop (PLL) system can be converted This type of tone detection technique is a special case
to a frequency-selective tone- or carrier-detection sys- of the synchronous AM detection principle, discussed
tem by the addition of a quadrature detector section to in detail in Exar's Application Note AN-13. The key dif-
the basic PLL. Such a carrier-detect system serves as a ference between the tone detection and the synchro-
lock indicator for the PLL and produces a logic signal at nous AM detection application is that, in the case of the
its output when there is a tone or a carrier signal tone detection, a binary logic output is produced, corre-
present within the lock range of the phase-locked loop. sponding to the presence or the absence of the desired
input tone, rather than an analog demodulated signal.
A number of monolithic tone-decoder les have been de-
veloped which implement the quadrature-detection XR-210 and XR-215 HIGH FREQUENCY PLL CIRCUITS
technique for detection of low frequency tones, such as
those used for telephone dialing or ultrasonic remote The XR-210 and the XR-215 are high frequency phase-
control. However, because of the particular PLL de- locked loop detector and demodulator circuits. Their
signs used in these monolithic detectors, their applica- functional block diagrams are shown in Figures 2 and
tions are limited to frequencies below 100 kHz. This ap- 3. Both circuits are packaged in 16-pin dual-in-line
plication note describes a circuit approach, using the packages and contain high frequency veo and phase-
XR-210 or the XR-215 high frequency PLLs, along with detector sections. The XR-215 chip also contains an op-
the XR-2228 monolithic multiplier/detector, which ex- erational amplifier. In the case of the XR-210, this op
tends phase-locked loop tone detection capabilities to amp section is replaced by a high-gain voltage compar-
frequencies up to 20 MHz. ator which drives an open-collector type logic output.
The XR-210 is particularly intended for FSK demodula-
PRINCIPLES OF OPERATION tion and can operate up to 20 MHz. The XR-215 is de-
signed for linear FM detection and is suitable for fre-
The basic block diagram of a phase-locked loop tone quencies up to 35 MHz. Except for the frequency capa-
detector system is shown in Figure 1. Such a detector bility of the veo, the oscillator and the
system produces a logic-level signal at its output, when phase-comparator sections of both circuits are quite
the PLL is locked on an input signal. It is made up of similar.
two main sections:
The veo section of the XR-21 0 or the XR-215 does not
1. A PLL section which synchronizes or locks on the in- provide a separate quadrature output, which is 90 0
put signal. phase-shifted with respect to the basic veo output (Pin
15). However, the triangular output available across the
2. A quadrature detector section made up of a phase- veo timing capacitor terminals (Pins 13 and 14) can
detector, a low-pass filter and a voltage-comparator.

The principle of operation can be briefly described as PHASE·LOCKED LOOP

follows: When the PLL is locked on an input signal, its r--------------.,

voltage-controlled oscillator (VeO) section produces a !
set of input signals, 4>1 and 4>1, which are 90 0 apart in

•
TONE OR DEMODULA TEO
phase, but have the same frequency as the input signal CARRIER FM OR FSK
INPUT OUTPUT
to be detected. One of these signals, 4>1, is used to
drive the PLL phase detector; the other output, which is
called the "quadrature output" is used to drive a quad-
rature phase-detector, as shown in Figure 1. If the PLL
is locked on the input signal, then the input signal and
the veo signal applied to the quadrature phase-
detector are coherent in phase and frequency. This DH
causes a De level shift at the low-pass filtered output of
TONE DETECT
the quadrature phase-detector and makes the voltage QUADRATURE DETECTOR OUTPUT
comparator output change its output logic state. Thus,
an output logic signal is produced indicating the lock Figure 1. Functional Block Diagram of a PLL Tone- or
condition of the PLL. Carrier-Detector System.

11-65
 AN·12 PHASE VCO
COMPARATOR RANGE TIMING (I) VCO OUTPUT
OUTPUTS SELECT CAPACITOR WAVEFORM
(PIN 15)

(b) WAVEFORM ACROSS

""""--~
VCO
___ OUTPUT /\/\/\/\ VCO TIMING

VV~
PHASE CAPACITOR
COMPARATOR 6 (PINS 11 end 12)

nnnn
INPUTS

PHASE 5 (e) ,"SLICED" VERSION

II VCO GAIN
COMPARATOR 0-:-+-----' OF TIMING

SLrU LrL
CONTROL
BIAS CAPACITOR
WAVEFORM

Figure 4. Timing Diagram of VCO Output Waveforms

- VEE OP AMP OP AMP OP AMP Available from XR-210 or XR-215 High-Frequency
INPUT COMPENSATION OUTPUT
PLL Circuits.
Figure 2. Functional Block Diagram of XR-210
High-Frequency FSK Modulator IDemodulator.
MULTIPLE OP AMP OP AMP
PHASE VCO OUTPUTS INPUTS COMPARATOR
COMPARATOR VCO TIMING +VCC
OUTPUTS CONTROLS CAPACITOR 1S 1 16 14 13 12

VCO
15 OUTPUT
PHASE '.---r--v
COMPARATOR 6 12 VCO SWEEP ___----"--1'--'-1~ OP AMP
INPUTS L----II---o AND GAIN OUTPUT
~--+-.:...:..o CONTROLS
PHASE
COMPARATOR 0.:...+-----' 8 LOGIC
FOUR·QUADRANT
BIAS OUTPUT
MULTIPLIER

8 7 a t 10

COMPARATOR -VEE Y GAIN X GAIN

INPUT SET SET

Figure 3. Functional Block Diagram of XR-215 Figure 5. Functional Block Diagram of XR-2228
High-Frequency Phase-Locked Loop. MultiplierIDetector.

serve as such a quadrature output if it is amplified and given in their respective data sheets, only the external
"sliced" externally, as shown in the timing diagram of circuitry associated with the XR-2228 is shown in the
Figure 4. figure, The circuit, as shown, can operate with a single
power supply, from 10 V to 20 V, or with split supplies in
XR-222B MULTIPLIER/DETECTOR CIRCUIT the range of ± 5 V to ± 10 V. In the case of split power
supplies, the resistor string biasing the input terminals
The XR·2228 is comprised of a four·quadrant multiplier of the XR-2228 is not necessary and can be eliminated
and a high·gain op amp on a single monolithic chip. It is by connecting node A of Figure 6 to ground.
packaged in a 16-pin dual·in·line package and has the
functional block diagram shown in Figure 5. It contains The input signal is AC coupled, with separate coupling
independent and fully differential X· and Y·inputs which capacitors, both to the input of the particular PLL cir·
makes it easy to interface with the XR-210 or the XR· cuit to be used, and to the X·input terminal (Pin 2) of the
215 type PLL circuit for carrier·detection applications. XR-2228.
In the tone· or carrier·detect application, the multiplier
section of the XR-2228 is used as the quadrature The Y·inputs (Pins 4 and 5) are driven differentially from
phase·detector section of the block diagram of Figure the VCO timing capacitor signal (available at Pins 13
1. The op amp is used as a high·gain voltage compara· and 14 of the PLL IC) which is AC coupled to Pins 4 and
tor which converts the differential voltage level 5 of the XR-2228 multiplier input. The multiplier input
cr1anges at the rnuiiipiier outputs into logic level output siage "slices" ihis signal io produce ihe quadraiure fre·
signals. quency waveform shown in Figure 4(c).

CIRCUIT OPERATION The differential DC voltage level at the multiplier output

terminals (Pins 1 and 6) is offset by means of an exter·
Figure 6 shows the generalized circuit connection of nal resistor, RA, as shown in Figure 6. This initial offset
the XR-2228, along with either the XR-210 or the XR· causes the op amp output of the XR-2228 to settle to a
215 high frequency PLL IC, for tone· or carrier· known state when there is no carrier or tone signal to
detection application. Since the external connections be detected. With the op amp input connections as
for the XR-210 or the XR-215 are the same as those shown in Figure 6, the op amp output (Pin 11) would be

11-66
 AN·12
f
"VCC

1 15

I:
I"F
~
3 K
10 K
RA I XR-2228 H

~ SL
I-T-f -=- A ~
14
INP 11 CARRIER-
UT-N#-
SIGN AL 3 K : DETECT

o 1
.1.
13
12 QUTPUT

l~, ~
16 9

---_4
T""' l T
CA RX

1 8
I I
I . 1
XR-210
OR
I
I
I
.A
10 K

10 K
2

3
X
MULTIPLIER
7
I
XR-21S
HIGH FREQUENCY
I 6
13 I
PHASE-LOCKED LOOP L
0.1 "F

1c~
I II
II 4
5 ~O
II
II
I
~
14
0.1 "F 10 K
I 10 K
_ _ _ _ _ _ _ _ _ ...J >
_.....
I 2
"F

Figure 6. Recommended Circuit Connection of the XR-2228 with the XR-210 or the XR-215 High-Frequency Phase-Locked Loops
for Tone- or Carrier-Detector Application.

at a "low" state when the PLL is not locked on a tone, 1000

and goes to a "high" state (near + VCe) when the PLL

circuit is locked on to an input tone. The output logic
I;;
polarity can be reversed simply by reversing the op
amp inputs.
.E.
UJ 800 /'
Q
;:) /'
5
The filter capacitor, CA, connected across Pins 1 and
16 of the multiplier outputs, serves as the post-
detection low-pass filter (Slock 5 of Figure 1). The time
A.
~
C
oJ
cz 600
/
constant of this filter is equal to (CA RS where RS (=:: 8
KO is the internal resistance of the IC at Pins 1 and 16.
The value of CA is chosen to provide a compromise be-
"iii
I-
;:)
A.
! 400
/
V
UJ
tween the response time and the spurious noise rejec- oJ
CD
tion characteristics of the circuit: increasing CA im- C
I-
()
proves the noise rejection characteristics of the circuit, UJ

but slows down the response time.

t;j
Q 200 ./
The detection threshold (minimum detectable input sig-
~
;:)
~
Z
V RA =1'0 KII

•
nal amplitude) varies inversely with the multiplier gain- i
setting resistor RX' Figure 7 shows the typical detect- 11< 2K 3K 4K 5K
able signal level, as a function of RX, with the output
RX IN 1<1I
offset resistor, RA, equal to 10 KO. Note that the mini-
mum detectable input signal, with RX = 0, is approxi- Figure 7. Minimum Detectable Input Carrier Level, as a I

mately 100 mV, rms. Function of Multiplier Gain Setting Resistor, RX'

11-67
 AN-13
Frequency-Selective AM Detection using
Monolithic Phase-Locked Loops
INTRODUCTION
This application note describes the use of monolithic The phase-locked loop AM detectors also operate on a
phase-locked loop (PLL) circuits In detection of similar principle: the PLL is made to "lock" on the carri-
amplitude-modulated (AM) signals. The detection capa- er frequency of the input AM signal; then the VCO out-
bilities of a PLL system, which is a frequency-selective put of the PLL will regenerate the unmodulated coher-
FM demodulator, can be extended to cover AM signals ent carrier signal necessary for detection. When this
simply by the addition of an analog multiplier (or mixer) signal is mixed with the input AM signal and the result-
and a low-pass filter to the basic phase-locked loop. ing composite signal is passed through a low pass filter,
This technique of AM demodulation, which is called one obtains the demodulated output. Figure 2 gives a
synchronous AM detection, offers significant perform- block diagram of such an AM detector system. Com-
ance advantages over conventional peak-detector type pared to the basic synchronous AM detector system of
AM demodulators, in terms of its dynamic range and Figure 1, the phase-locked loop AM detector of Figure 2
noise characteristics. also has one added feature: the output of the PLL con-
trol voltage (Le., output of the PLL low-pass filter) can
This application note outlines some of the fundamental be used as an FM detector or a frequency discrimina-
principles of synchronous AM detectors, and gives de- tor. Thus, such a system is capable of simultaneous AM
sign examples using the XR-2228 multiplier/detector IC and FM detection. In other words, the frequency and
in conjunction with the XR-215 and the XR-2212 mono- the amplitude modulation information present on the in-
lithic PLL circuits. put signal can be separately and simultaneously de-
modulated. The particular design and application exam-
PRINCIPLES OF OPERATION ples given in this application note fall into this category.

The phase-locked loop AM detector circuits operate on AM SIGNAL

INPUT
the so-called "coherent AM detection" principle, where
the amplitude modulated input signal is mixed with an
unmodulated "coherent" carrier signal, and then low-
---- X
Vm(t)cos(OO·

MULTIPLIER
Vo(+)
t--
b ~
DEMODULATED
OUTPUT
KOVm(t)

pass filtered to produce the desired demodulated out- LOW PASS

FILTER
put signal. Figure 1 gives a simplified block diagram of r
such a detector system. UNMODULATED
CARRIER SIGNAL
Ec cos lUot
The amplitude-modulated input signal can be described
by an expression of the form: Figure 1 Block Diagram of a Synchronous AM Detector.
Input Signal = Vm(t) cos wot
where Vm(t) is the modulated amplitude of the input sig-
nal and Wo is the input signal frequency expressed in
radians. If this signal is linearly multiplied with an un-
modulated signal which has the same frequency and
phase as the input signal, then the output of the mUlti-
plier, VO(t), is a composite signal of the form: AMORFM
INPUT

VO(t) = KO Vm(t) [1 + cos (2 wot)]

where KO is the gain of the multiplier circuit. If the
above signal is then passed through a low-pass filter, to ~~--~
eliminate the double-frequency term, the resulting out- I DEMODULATED
AM OUTPUT
put signal is: I MULTIPLIER LOW PASS I
L _____ ~E~ _ _ ..J
SYNCHRONOUS DETECTOR
Vout = Output Signal = KO Vm(t)

which corresponds to the detected AM information. Figure 2. The Basic Phase-Locked Loop AM Detector.

11-68
 MULT. OPAMP
AN·13
OPAMP
XR-2212 AND XR-2228 MONOLITHIC CIRCUITS • Vee OUTPUTS INPUTS COMP
0016 Q 0 12
C'4
The XR-2212 monolithic PLL is made up of an input pre- 1'5 1 '3

I
amplifier, a phase-detector, a high-gain differential am-
plifier and a stable voltage-controlled oscillator (VCO)
as shown in Figure 3. The key feature of the XR-2212

-:::~
,-,2
PLL is the temperature stability and the frequency ac- X·INPUTS '--
curacy of its VCO section; it offers 20 ppm/oC typical 01- -
temperature stability and a frequency accuracy of ±
1 % for an external RC setting. The oscillator section of
4
r-
('\.5 X -
-/
4..0 OPAMP
OUTPUT

FOUR·QUADRANT
the XR-2212 contains a separate "quadrature output" MULTIPLIER
terminal (Pin 15) which is particularly intended for inter-
facing with a synchronous AM detector such as the XR- I

2228. 6 7
()( )
8
C(
9 10~
Y·GAIN X·GAIN
The XR-2228 multiplier/detector IC is specifically in- SET SET

tended as a basic building block for synchronous AM

Figure 4. Functional Block Diagram of XR-2228
detection. It contains a four-quadrant analog multiplier
Multiplier/Detector IC.
and a high-gain op amp on the same chip, as shown in
the functional block diagram of Figure 4.
AM/FM DETECTION USING THE XR-2212 PLL

• Vee
PHASE DET
INPUT
PHASE DET
OUTPUT
OP AMP
INPUTS
OP AMP
eOMP
Figure 7 shows a generalized circuit connection dia-
gram for a two-chip AM and FM detection system, utiliz-
ing the XR-2212 PLL and the XR-2228 multiplier/
detector. The XR-2212 section serves as the basic FM
detector. The quadrature output of its VCO (Pin 15) is
AC coupled to the Y input of the XR-2228.
OPAMP
OUTPUT
The Y input of the XR-2228 is operated in its switching
mode, with the Y gain terminals (Pins 6 and 7) shorted
together. The AM and/or FM signal is simultaneously
veo applied to both circuits through coupling capacitors;
vOLTAGE
OUTPUT
and all the mutliplier inputs are DC biased from the in-
ternal reference output of the XR-2212 (Pin 11). The out-
put of the multiplier, at Pin 16, is AC coupled to the op
amp section of the XR-2228, which serves as the post-
detection amplifier for the demodulated AM signal.
veo TIMING veo
QUADRATURE CAP INPUT
OUTPUT (TIMING
RESISTOR)
The circuit configuration shown in Figure 7 can operate
with a single power supply, over the supply voltage
Figure 3. Functional Block Diagram of XR-2212 Precision range, of 10V to 20V. Its operation or performance can
Phase-Locked Loop. be tailored for any particular AM and FM detection ap-
plication by the choice external components shown in
the figure, over a carrier frequency band of 1 kHz to
XR-215 HIGH FREQUENCY PHASE-LOCKED LOOP
PHASE VCO
COMPARATOR RANGE TIMING
The XR-215 is a high frequency phase-locked loop cir- • Vcc OUTPUTS SELECT CAPACITOR

cuit capable operating with input signal frequencies up

•
to 35 MHz. It is comprised of a high frequency VCO, a
phase-detector and an op amp section, as shown in the
block diagram of Figure 5.
. ? - - - - t - v veo OUTPUT
PHASE
Unlike the XR-2212 PLL, the VCO section of the XR-215 COMPARATOR
INPUTS ~-+--0 ~Ncp~iwEEP
does not have a separate quadrature output terminal.
However, such a quadrature oscillator signal can be ob- PHASE
VCO GAl'"
CONTROL
COMPARATOR
tained by amplifying and "slicing" the triangle wave- BIAS
form available across the timing capacitor (Pins 13 and
14) of the XR-215 oscillator section. Figure 6 shows the
relative phase relationship of these oscillator wave-
forms available from the circuit. The desired quadrature
output signal (curve C of Figure 6) can be obtained by OP AMP
INPUT
OP AMP
COMPENSATION
OP AMP
OUTPUT
directly connecting one pair of the differential inputs of
the XR-2228 directly across the timing capacitor termi- Figure 5. Functional Diagram of XR-215 High-Frequency
nals of the XR-215. Phase-Locked Loop.

11-69
AN·13
veo OUTPUT This tracking bandwidth, ~f, is the band of frequen-
(a) WAVEFORM
(PIN 15) cies in the vicinity of fa, over which the PLL can
maintain lock.

c) C1 sets the loop-damping factor for the PLL. For

1\ /\ /\ /\ WAVEFORM ACROSS

(b) V V V \/\ vea TIMING CAP

jPINS 11 AND 12) most applications, C1 is chosen to be equal to one-
half of CO.

(c) ~
nnnn
U U U L
SLICED VERSION
OF TIMING CAP
WAVEFORM
d) R2 and C2 form a low-pass filter for the detected FM
signal. The 3 dB frequencing, f2' of this low-pass fil-
ter is:
Figure 6. Timing Diagrams of VCO Output Waveforms from
XR-215 Monolithic Phase-Locked Loop.

300 kHz. The functions of these external components

are as follows: Normally, f2 is chosen to be equal to the demodu-
lated FM information bandwidth.
a) RO and Co set the VCO center frequency for the XR-
2212 PLL circuit. The center frequency, fa, is given e) RC and RF1 set the gain of the op amp section of
as: the XR-2212 as:
1
fa = - -
ROCO RF1
AV=1+--
The VCO frequency fa is chosen to be equal to the RC
carrier frequency of the input signal. RO is normally
chosen to be in the range of 10 kG to 100 kG. This This op amp section serves as the post-detection
choice is arbitrary. For most applications RO "" 20 amplifier for the demodulated FM signals.
kG is recommended. Once fa is given and RO is cho-
sen, the Co can be calculated from the above equa- f) RX sets the multiplier gain for the X input and RF2
sets the gain of the op amp section of the XR-2228.
tion.
Thus, the demodulated AM signal output swing, Vout,
b) R1 determines the tracking bandwidth of the PLL. for a given input Signal of peak amplitude of VM and
For a required tracking bandwidth, ~f (see Figure 9 modulation index of m (0 :s m :s 1) can be approxi-
of XR-2212 data sheet) and fa, R1 can be calculated mated as:
as:

R fa Vout = (VM)m RF2

oM 4 RX

---=r==-D DEMODULATED
t----"r;A.lV'v--_--Q,..!.2....._ _ _ _ _ ---j~f_--F._::,MOUTPUT

c r
2~ R2

yo,"VCC

~~T
C1

1 ~

AMN
SIGNAL
INPUT
RO

1
Figure 7. A Two-Chip AM/FM Detector System USing the XR-2212 Phase-Locked Loop and the XR-2228 MultiplierIDetector.

11-70
 Thus, for example, a 100 mV peak input signal with
AN-13
input carrier level, the value of RF2 to get one
30% AM modulation (m = 0.3) will give a demodu- volt demodulated output is: RF2 = 67 kO.
lated output of 150 mV peak, with RF2 = 100 kO and
RX = 5 kO, at Pin 11 of the XR-2228. Step 5) Calculate C3 to get 3 kHz bandwidth for post-
detection filter: C3 z 0.01 p.F.
g) C3, in conjunction with the 5 kO internal impedance
of the multiplier output (Pin 16) serves as the low-
AM DETECTION USING THE XR-215 PLL
pass post-detection filter for the demodulated AM Figure 8 shows the circuit connection diagram for a
signal. two-chip AM and FM detection system, using the XR-
215 high-frequency PLL in conjunction with the XR-
For further explanation and description for the system 2228 multiplier/detector. Because of the high-frequency
design equations, the reader is referred to the XR-2212 capability of the XR-215, the circuit of Figure 8 is useful
and the XR-2228 data sheets. as a phase-locked AM detector for carrier frequencies
Design Example up to 20 MHz, and operates over a supply voltage range
of 10V to 20V.
Design an AM demodulator for 100 kHz carrier frequen-
cy with a detection (tracking) bandwidth of ± 4 %. The The VCO section of XR-215 does not have a separate
demodulated information bandwidth is 3 kHz and an quadrature output. However, this problem can be over-
output level of one volt peak is required for a one volt come by driving the XR-2228 multiplier directly from the
peak input with 30 % modulation. timing capacitor terminals (Pins 13 and 14) of XR-215.
The Y input of the XR-2228 is operated with maximum
Using the circuit of Figure 7, one proceeds as follows: gain, since the Y gain control terminals (Pins 6 and 7)
Since FM detection is not required in this example, are shorted together. This causes the triangular wave-
components R2, C2, RC and RF1 are not essential to form across Co to be converted to an effective quadra-
circuit operation. R2 and RC can be short-circuited, C2 ture drive as indicated by the timing diagram of Figure
and RF1 can be left open-circuited. The rest of the com- 6. The modulated input signal is simultaneously applied
ponent values are calculated as follows: to both circuits through coupling capacitors. The
phase-detector inputs of the XR·215, as well as the mul-
Step 1) Set fO = 100 kHz by choosing RO = 20 kO and tiplier X inputs of the XR·2228, are biased at approxi·
calculating Co from paragraph (a) above. mately one-half of VCC, by means of an external resis-
tive divider.
1
Co = - - = 500 pF
ROtO In Figure 8, Co sets the VCO frequency of the XR-215.
In the case of FM demodulation, R1 and C1 serve as
Step 2) Determine R1 to set tracking bandwidth to ± the post-detection filter for the detected FM signal and
4%, from paragraph (b): R1 = 500 kO. RF1 sets the gain of the FM post-detection amplifier.

Step 3) Calculate C1 :C1 :::;: CO/2 :::;: 250 pF. The mode of operation of the XR-2228 is virtually the
same as that described in conn~ction with Figure 7: RX
Step 4) From paragraph (t), calculate the value of RX sets the multiplier demodulation gain; C3 serves as the
and RF2. For a typical choice of RX = 5 kO, low-pass post-detection filter. The values of RX, RF2
and m = 0.3 (30% modulation) with one volt and C3 are calculated as given in paragraphs (f) and (g).
AM/FM
SIGNAL
INPUT o>---I-------------.c 1o
=oKV---------------,

~--~~~~~~~_D
R,
+Vcc

;~~F ICI

•
2K

2K
+Vcc
I

IK

2K

4.8J1F
B.2K

3K
Cc = COUPLING CAPACITOR

Figure 8. Circuit Connection for a High-Frequency AM and FM Detector Using the XR-215 and XR-222B.

11-71
 AN-14
High-Quality Function Generator System
with the XR-2206
INTRODUCTION
Waveform or function generators capable of producing (a) Frequency Ranges: The function generator system is
AM/FM modulated sine wave outputs find a wide range designed to operate over four overlapping frequen-
of applications in electrical measurement and labora- cy ranges:
tory instrumentation. This application note describes
1 Hz to 100 Hz
the design, construction and the performance of such a 10 Hz to 1 kHz
complete function generator system suitable for labora- 100 Hz to 10 kHz
tory usage or hobbyist applications. The entire function 1 kHz to 100 kHz
generator is comprised of a single XR-2206 monolithic
IC and a limited number of passive circuit components. The range selection is made by switching in differ-
It provides the engineer, student, or hobbyist with a ent timing capacitors.
highly versatile laboratory instrument for waveform gen-
eration at a very small fraction of the cost of conven- (b) Frequency Setting: At any range setting, frequency
tional function generators available today. can be varied over a 100:1 tuning range with a po-
tentiometer (see R13 of Figure 1).
GENERAL DESCRIPTION
(c) Frequency Accuracy: Frequency accuracy of the XR-
The basic circuit configuration and the external compo- 2206 is set by the timing resistor R and the timing
nents necessary for the high-quality function generator capaCitor C, and is given as:
system is shown in Figure 1. The circuit shown in the
figure is designed to operate with either a 12 V single f = 1/RC
power supply, or with ± 6 V split supplies. For most ap-
The above expression is accurate to within ± 5 % at
plications, split-supply operation is preferred since it
any range setting. The timing resistor R is the series
results in an output dc level which is nearly at ground
combination of resistors R4 and R13 of Figure 1.
potential. The timing capacitor C is anyone of the capacitors
The circuit configuration of Figure 1 provides three ba- C3 through C6, shown in the figure.
sic waveforms: since, triangle and square wave. There
(d) Sine and Triangle Output: The sine and triangle output
are four overlapping frequency ranges which give an
amplitudes are variable from 0 V to 6 Vpp. The am-
overall frequency range of 1 Hz to 100 kHz. In each
plitude is set by an external potentiometer, R12 of
range, the frequency may be varied over a 100: 1 tuning
Figure 1. At any given amplitude setting, the trian-
range.
gle output amplitude is approximately twice as high
as the sinewave output. The internal impedance of
The sine or triangle output can be varied from 0 to over
the output is 600 n.
6 V (peak to peak) from a 600 ohm source at the output
terminal. (e) Sinewave Distortion: The total harmonic distortion of
sinewave is less than 1 % from 10Hz to 10kHz and
A squarewave output is available at the sync output ter-
less than 3 % over the entire frequency range. The
minal for oscilloscope synchronizing or driving logic cir-
selection of a waveform is made by the triangle/sine
cuits.
selector switch, S2.
TYPICAL PERFORMANCE CHARACTERISTICS
(I) Sync Output: The sync output provides a 50 % duty
The performance characteristics listed below are not cycle pulse output with either full swing or upper
guaranteed or warranted by Exar. However, they repre- half swing of the supply voltage depending on the
sent the typical perfOimance characierisiics measured choice of sync output terminals on the printed cir-
by Exar's application engineers during the laboratory cuit board (see Figure 1).
evaluation of the function generator system shown in
Figure 1. The typical performance specifications listed (g) Frequency Modulation (External Sweep): Frequency can
below apply only when all of the recommended assem- be modulated or swept by applying an external con-
bly instructions and adjustment procedures are fol- trol voltage to sweep terminal (Terminal I of Figure
lowed: 1). When not used, this terminal should be left open-

11-72
 AN·14
AMPLITUDE

R12
AM INPUT

OUTPUT

,------R Q ----------------,
V-~~~----4r------~~~~--.-------------------~--------------,
I
-6V I
I Cl 10"/l0V
Rl
R7
I
GND is T RX
30K lK
I
I
Ji1 I 10" + ~~
DC
OFFSET
I

V+~~10_V~+-~~~R~2~100~K~--------~_4
+6V

1------~---------_+_--9_ SYNC OUTPUT

(FULL SWING)

C7
R6 10,,/6V
SI SK

L-----------------~'IAr---+----------_+_~:>_ SYNC OUTPUT

R3 R4
RS SK (HALF SWING)
lK 9K
I
I
L ________ I
I
-.J
V-
R13 1M
SWEEP
INPUT

FREQUENCY
NOTE:

1. For Single Supply Operalion Lif1 GND Conneclion Keeping R12 Across Terminals Rand S Intact. and Connect
Terminal A to GND.

2. For Maximum Output. RX may be open. RX = 68 Kll is Recommended lor External Amplitude Modulation.

Figure 1. Circuit Connection Diagram for Function Generator. (See Note 1 for Single Supply Operation.)

circuited. The open circuit voltage at this terminal is inversely proportional to the timing capacitor connect-
approximately 3V above the negative supply voltage ed across Pins 5 and 6 of the XR-2206 circuit. Nominal
and its impedance is approximately 1000 ohms. capacitance values and frequency ranges correspond-
ing to switch positions of S1 are as follows:
(h) Amplitude Modulation: The output amplitude varies lin-
early with modulation voltage applied to AM input Position Nominal Range Timing Capacitance
(terminal Q of Figure 1). The output amplitude
1 1 Hz to 100 Hz 1 J.LF
reaches its minimum as the AM control voltage ap-
2 10 Hz to 1 kHz 0.1 J.LF
proaches the half of the total power supply voltage.

•
3 100 Hz to 10 kHz 0.01 J.LF
The phase of the output signal reverses as the am- 4 1 Hz to 100 kHz 0.001 J.LF
plitude goes through its minimum value. The total
dynamic range is approximately 55 dB, with AM If additional frequency ranges are needed, they can be
control voltage range of 4V referenced to the half of added by introducing additional switch positions.
the total supply voltage. When not used, AM termi-
nal should be left open-circuited. Triangle/Sine Waveform Switch, S2: Selects the triangle
or sine output waveform.
(i) Power Source: Split supplies: ± 6 V, or single supply: +
12 V. Supply Current 15 mA (see Figure 3). Trimmers and Potentiometers
EXPLANATION OF CIRCUIT CONTROLS: Dc Offset Adjustment, R9: The potentiometer used for
adjusting the dc offset level of the triangle or sine out-
Switches put waveform.

Range Select Switch, S1: Selects the frequency range Sinewave Distortion Adjustment, R1 0: Adjusted to mini-
of operation for the function generator. The frequency is mize the harmonic content of sinewave output.

11-73
AN·14
Sinewave Symmetry Adjustment, R11: Adjusted to opti- Capacitors:
mize the symmetry of the sinewave output.
C1, C2, C7 Electrolytic, 10 JLF, 10V
Amplitude Control, R12: Sets the amplitude of the trian- C3 Mylar, 1 JLF, nonpolar, 10%
gle or sinewave output. C4 Mylar, 0.1 JLF, 10%
C5 Mylar, 0.01 JLF, 10%
Frequency Adjust, R13: Sets the oscillator frequency C6 Mylar, 1000 pF, 10%
for any range ~etting of S1. Thus, R13 serves as a fre-
quency dial on a conventional waveform generator and Resistors:
varies the frequency of the oscillator over an approxi-
mate 100 to 1 range. R1 30 KO, 1/4 W, 10%
R2 100 KO, 1/4 W, 10%
Terminals R3, R7 1 KO, 1/4 W, 10%
R4 9 KO, 1/4 W, 10%
A. Negative Supply -6V R5, R6 5 KO, 1/4 W, 10%
B. Ground R8 300 KO, 1/4 W, 10%
C. Positive Supply + 6V RX 62 KO, 1/4 W, 10% (RX can be eliminated
D. Range 1, timing capacitor terminal for maximum output)
E. Range 2, timing capacitor terminal
F. Range 3, timing capacitor terminal
G. Range 4, timing capacitor terminal Potentiometers:
H. Timing capacitor common terminal
R9 Trim, 1 MO, 1/4 W
I. Sweep Input
R10 Trim, 1 KO, 1/4 W
J. Frequency adjust potentiometer terminal
R11 Trim, 25 KO, 1/4 W
K. Frequency adjust potentiometer negative
supply terminal
L. Sync output (1/2 swing) The following additional items are recommended to
M. Sync output (full swing) convert the circuit of Figure 1 to a complete laboratory
K Triangle/sine waveform switch terminals instrument:
O. Triangle/sine waveform switch terminals
P. Triangle or sinewave output Potentiometers:
Q. AM input
R. Amplitude control terminal R12 Amplitude control, linear, 50 KO
R13 Frequency control, audio taper, 1 MO
PARTS LIST
Switches:
The following is a list of external circuit components
necessary to provide the circuit interconnections S1 Rotary switch, 1-pole, 4 positions
shown in Figure 1. S2 Toggle or slide, SPST

(a) Split Supply PC Board Layout (b) Single Supply PC Board Layout

Figure 2. Recommended PC Board layout for Function Generator Circuit of Figure 1.

11-74
 Case: Any simple power supply having reasonable regulation
may be used. Figure 3 gives some recommended
7" X 4" X 4" (approx.) Metal or Plastic power supply configurations.
(See Figures 4(a) and 4(b).)
Precaution: Keep the lead lengths small for the range
Power Supply: selector switch.
Dual supplies ± 6 V or single + 12 V ADJUSTMENT PROCEDURE
Batteries or power supply unit
(See Figures 3(a) and 3(b).) When assembly is completed and you are ready to put
the function generator into operation, make sure that
Miscellaneous: the polarity of power supply and the orientation of the
IC unit are correct. Then apply the dc power to the unit.
Knobs, solder, wires, terminals, etc.
To adjust for minimum distortion, connect the scope
BOARD LAYOUT probe to the triangle/sine output. Close S2 and adjust
the amplitude control to give non-clipping maximum
Figures 2(a) and 2(b) show the recommended printed- swing. Then adjust R10 and R11 alternately for mini-
circuit board layout for the function generator circuit of mum distortion by observing the sinusoidal waveform. If
Figure 1. a distortion meter is available. you may use it as a final
check on the setting of sine-shaping trimmers. The min-
RECOMMENDED ASSEMBLY PROCEDURE imum distortion obtained in this manner is typically less
than 1 % from 1 Hz to 10kHz and less than 3 % over
The following instructions and recommendations for the entire frequency range.
the assembly of the function generator assume that the
basic PC board layout of Figure 2(a) or 2(b) is used in
the circuit assembly.

All the parts of the generator, with the exception of fre-

quency adjust potentiometer, amplitude control potenti-
ometer, triangle/sine switch and frequency range select
switch, are mounted on the circuit board.
"'2) Ii +6 V

05
6V
GNO

Install and solder all resistors, capaCitors and trimmer 06

6V
resistors on the PC board first. Be sure to observe the
-6 V
polarity of capaCitors C1, C2, C7. The timing capacitors
51 R2
C3, C4, C5 and C6 must be non-polar type. Now install

-
IC1 on the board. We recommend the use of an IC sock- (a) Zener Regulaled Supply
et to prevent possible damage to the IC during solder-
ing and to provide for easy replacement in case of a
malfunction.

rt:
~ ~ ~ -I f!---<>+6 V
The entire generator board along with power supply or ..c-o GNO
batteries and several switches and potentiometers will
fit into a case of the type readily available at electronic
-- + ~--
6 V
-l-~-~V
-

hobby shops. It will be necessary to obtain either output

(b) Bal1ery Power Supply
jacks or terminals for the outputs and am and frequen-
cy sweep inputs.
11: Filament Transformer
Install the frequency adjust pot, the frequency range Primary 115V/Seoondary 12.6 VCT. 0.5A
01 - 04: IN4001 or Similar
select switch, the output amplitude control pot, the 05. 06: IN4735 or similar
power switch, and the triangle/sine switch on the case. Rl. R2: 5111, 1/2W, 10%

Next, install the PC board in the case, along with a

power supply. Figure 3. Recommended Power SupplV Configurations.

11-75
 AN-15
An Electronic Music Synthesizer using the
XR·2207 and the XR·2240
INTRODUCTION Figure 3 shows the circuit connection for the electronic
This application note describes a simple, low-cost "mu- music or time synthesizer system using the XR-2207
sic synthesizer" system made up of two monolithic IC's and the XR-2240. The XR-2207 produces a sequence of
and a minimum number of external components. The tones by oscillating at a frequency set by the external
electronic music synthesizer is comprised of the XR- capacitor C1 and the resistors R1 through R6 connect-
2207 programmable tone generator IC which is driven ed to Pins 4 through 7. These resistors set the frequen-
by the pseudo-random binary pulse pattern generated cy or the "pitch" of the output tone sequence. The
by the XR-2240 monolithic counter/timer circuit. counter/timer IC generates the pseudo-random pulse
patterns by selectively counting down the time-base
PRINCIPLES OF OPERATION frequency. The counter outputs of XR-2240 (Pins 1
through 8) then activate the timing resistors R1 through
All the active components necessary for the electronic R6 of the oscillator IC, which converts the binary pulse
music synthesizer system is contained in the two low- patterns to tones. The time-base oscillator frequency of
cost monolithic IC's, the XR-2207 variable frequency the counter/timer sets the "beat" or the tempo of the
oscillator and the XR-2240 programmable counter/ music. This setting is done through C3 and RO of Figure
timer. Figure 1 shows the functional block diagram of 3.
the XR-2207 oscillator. This monolithic IC is comprised
of four functional blocks: a variable-frequency oscillator The pulse sequence coming out of the counter/timer IC
which generates the basic periodic waveforms; four can be programmed by the choice of counter outputs
current switches actuated by binary keying inputs; and (Pins 1 through 8 of XR-2240 connected to the program-
buffer amplifiers for both the triangle and squarewave ming pins (Pins 4 through 7) of the XR-2207 VCO. The
outputs. The internal current switches transfer the os- connection of Figure 3 is recommended since it gives a
cillator current to any of four external timing resistors to particularly melodic tone sequence at the output.
produce four discrete frequencies which are selected
according to the binary logic levels at the keying termi- The pseudo-random pulse pattern out of the counter-
nals (pins 8 and 9). timer repeats itself at 8-bit (or 256 count) intervals of
the time-base period. Thus, the output tone sequence
The XR-2240 programmable counter/timer is comprised continues for about 1 to 2 minutes (depending on the
of an internal time-base oscillator, a control flip-flop and "beat") and then repeats itself. The counter/timer re-
a programmable 8-bit binary counter. Its functional sets to zero when the device is turned on; thus, the mu-
block diagram is shown in Figure 2, in terms of the 16- sic, or the tone sequence, always starts from the same
pin IC package. The eight separate output terminals of point when the synthesizer is turned on.
the XR-2240 are "open-collector" type outputs which
can either be used individually, or can be connected in
a "wired-or" configuration. V·

TRIANGLf WAVE 10/2

OUT

TIMING
r SOUAREWAVE
OUT
10/4
TIME BASE
OUTPUT
CAPACITOR

L '0/8 TIMING R.C

BIAS 10/16 MODULATION

'0/32 TRIGGER

Figura 1_ Functional Block Diagram of XR·2207 Oscillator Figura 2. Functional Block DIagram of XR·2240 Counter!
Circuit. Timer.

11-76
 AN·15
RS R9
+12V

VOLUME
CONTROL
R21
R7

14

XR-2207

SPEAKER

+12V RO THRU R6 = lOOK

R7 = 10 Kr2
C4
IlllF

XR-2240

+12V
+ 1K
C2 C3
I 0.111'J:: 10 IJ.F

Figure 3. Circuit Connection Diagram for the Music Synthesizer.

11-77
 AN-16
Semi-Custom LSI Design with 12L
Gate Arrays
INTRODUCTION The 12L logiC technology is developed around the basic
single-input, multiple-output inverter circuit shown in
In designing semi-custom monolithic LSI, one uses a Figure 2. A recommended circuit symbol for this gate
partially fabricated silicon wafer which is "customized" circuit is also defined in the figure. Most terminals of
by the application of one or more special mask pat- the 12L gate share the same semi-conductor region (for
terns. This technique greatly reduces the design and example, the collector of the PNP is the same as the
tooling cost and the prototype fabrication cycle associ- base of the NPN; and the emitter of the NPN is the
ated with the conventional full-custom IC development same as the base of the PNP). This leads to a very com-
cycle; and thus makes custom IC's economically feasi- pact device structure, and results in very high packing
ble even at low production volumes. density in monolithic device fabrication. Figure 3 illus-
trates the basic device structure and the cross-section
Until recently, the application of semi-custom design for a bipolar-compatible 12L gate. Since the individual
technology to complex digital systems has been some- 12L gates do not require separate P-type isolation diffu-
what limited due to one key factor: to be economically sions, they can be placed in a common N-type tub. This
feasible, a complex digital LSI chip must achieve a high feature greatly enhances the packing density on the
functional density on the chip (i.e., high gate count per chip since it eliminates the need for separate isolation
unit chip area). Traditionally, this requirement is not pockets for individual gates. With conventional photo-
compatible with the random interconnection concept masking and diffusion tolerances, gate densities of
which is key to the semi-custom or master-slice design greater than 200 gates/mm 2 can be readily achieved in
approach. This paper describes a new approach to the full-custom layout. Using the semi-custom approach
master-slice concept which overcomes this age-old which is outlined in this paper, one can maintain a pack-
problem. It achieves packing densities approaching ing density of greater than 120 gates/mm 2 even with
those of full-custom digital LSI layout while still main- random metallization or interconnection requirements.
taining the low-cost and the quick turn-around attrib- This offers at least a factor of four improvement over
utes of semi-custom IC design. This is achieved by conventional bipolar master-slice technology and ap-
making use of unique layout and interconnection prop- proximately a factor of two improvement over MOS
erties of 12L gates, and by extending the mask- master-slice approach in terms of gate-density and chip
programming to additional mask layers besides the area utilization.
metal interconnection.

FEATURES OF 12L TECHNOLOGY

10", rc----~---,.------r----r---__,

Integrated Injection Logic (12L) is one of the most signif-

icant recent advances in the area of monolithic LSI
technology. Compared to other monolithic LSI technolo-
1 "' k----4----f----r--+---i-
gies, 12L offers the following unique advantages:

High Packing Density

Bipolar Compatible Processing
Low Power and Low Voltage Operation
Low (Power x Delay) Product 54L TTL

,
54LS TTL
Figure 1 gives a comparison of the speed and power
capabilities of various logic families, including 12L. 54H TTL

Since 12L technology is a direct extension of the con-

"-
O~l ,,
PI
"
1 P\ I' ,
10 PI, •
ventional bipolar Ie technology, it readily lends itself to '.
n' L-_ _- L_ _~I.....__ __:""__ ___::''''-:::--~~
" '. , Eel.
10K
Eel
111
combining high-density digital functions on the same 1
l,uW 10/olW 100jJW 1mW 10mW 100mW
chip along with conventional Schottky-bipolar circuitry. POWER/GATE
The availability of bipolar input-output interface on the
same chip along with the high-density 12L logic makes it
very convenient to retrofit custom 12L designs into Figure 1. Comparison of Speed and Power Capabilities of
many existing logic systems. Various Logic Families.

11-78
 Table 1
C1
List of Components on XR-300 and XR-500
Semi-Custom Chips

Ao--.......- - - I Chip Type

Component Type XR-300 XR-500

(a) (b) Multiple Output 12L Gates 288 520

Input/Output Buffers 28 40
Figure 2. Equivalent Circuit (a), and a Recommended Schottky - NPN Transistors 56 80
Symbol (b) for an ItL Gate. Resistors 168 240
Bonding Pads 34 42
Chip Size (mils) 104 x 140 122x 185

A 0----+---1

"
,----------------------------~

['I~ II ~============~
Figure 4. Basic Architecture of XR-300 and XR-500 12L Gate
Arrays.

a) The 12L Gate Matrix:

This section of the 12L gate array is made up of 8-
- - to",,,!,,,,,!,,,,,,,,,,,,,,," - - - ,_ _ _ _ _ 1)(II'I~_ _ _' gate "cells." These cells contain eight multiple-
output 12L inverters which share a common set of
Figure 3. Basic Device Structure for Bipolar Compatible 12L. four injectors. Figure 5 shows a basic 8-gate cell
section within the 12L gate section, prior to custom i-
DESIGNING WITH 12L GATE ARRAYS zation. The basic 8-gate cells forming the 12L gate
matrix are made up of P-type injectors and gate-
A number of 12L gate arrays have been developed at fingers which serve as the base regions of the 12L
Exar utilizing bipolar-compatible integrated injection gates. The six dots on each gate area indicate the
logic technology. The most recent additions to this fami- possible locations or sites for gate input or outputs.
ly of products are the XR-300 and the XR-500 gate array The particular use of these sites as an input or an
chips which are specifically intended for semi-custom output is determined by two custom masks: an N-
IC designs involving complex digital systems. These type collector diffusion mask which defines the loca-
chips contain a large number of mUltiple-output 12L tions of outputs, and a custom contact mask which
gates along with Schottky-bipolar input/output buffers. opens the appropriate input and output contact. Fi-
Table I gives a summary of the components available nally, a third custom mask is applied to form the met-
on each of these chips. al interconnections between the gates, and the gate
cells. The custom N-type diffusion step, which deter-
Figure 4 shows the basic layout architecture of the XR- mines the locations of gate outputs, is also used for
300 and the XR-500 gate array chips. As indicated in forming low-resistivity underpasses between the
the figure, each chip is made up of two sections: (a) the gate-cells. The area between each of the gate cells
12L gate matrix; and (b) the Schottky-bipolar input! can accommodate two or three parallel under-
output interface. In addition, the bipolar I/O section con- passes in the horizontal and the vertical directions,
tains two identical sets of resistor arrays, located at op- respectively. Since the N-type diffusion which forms
posite ends of the chip, which are used for biasing the these underpasses is a part of the customizing step,
injectors of the 12L gates. The basic features of each of the location and the length of each unaerpass can
the sections of the gate array chips are outlined below: be chosen to fit a given interconnection require-

11-79
AN·16
ment. This method provides the designer with virtu· ures 8, 9 and 10, as a function of the injector current
ally all the advantages and capabilities of multi-layer per gate. As indicated in Figure 8, the average
interconnection paths on the surface of the chip; and power-delay product for a four-output gate is approxi-
allows approximately 80% of the gates on the chip mately 0.5 pJ at low currents; and the typical propa-
to be utilized
----J' 1
in--a typical
.
random-logic layout.
J ' - 1'--_ _ __
gation delay, tpd, at injector currents in excess of
100ILA/gate is approximately 50 nsec for the output

.J.
·1· . . •~·. 1 P·TVPE "FINGER"
DIFFUSION
12L GATES
FOR furthest from the injector. Figure 9 shows the two
components of the total propagation delay, namely
the turn-on and turn-off delay, as a functon of the in-

I~I ADJACENT
jector bias. At low injector currents (Le., Ii :S 10ILA),
turn-on delay is the dominant factor. For high-speed
SYMBOLS
= MeUl1 Interconnection
CELL
(> " Inltctor Cont.c!

··1'11
.' c
Q • G.tt OutPut
t:I • G.tt Input

Hi
~·Unc1.rp."

· · ·I'~ · ·I~· ·
:•. :.1= .

i· ~· · · · ·
)t1fl; I..-i----.---..I

\··/:/i(·j\······ .:. . ...-f-...........~~~

INJECTOR
DOTS INDICATE LOCATION OF BUS
INPUT/OUTPUT SITES
Figure 5. Basic B·Gate Cell Before Customization.
The custom logic interconnections can be easily laid
out in pencil on a layout sheet by simply intercon-
necting the desired gate "sites" with a pencil line
and appropriately defining the function of the site as
an input, output, injector contact or an underpass.
Figure 6 shows a typical example of such a logic lay-
out. The corresponding symbols defining the func- ~ I r-
tion of the sites on the layout are also identified in Figure 6. Sample Pencil Layout on a Logic Cell.
the figure. For convenience, an underpass is indi-
--1
cated with a resistor symbol, connecting two trian-
gles corresponding to the terminal points of the un-
derpass.
METAL
Figure 7 shows the sample layout of the same 8-gate INPUT
INTE RCONNEC'TION

cell, after its customization with a selective N-type

collector diffusion, contact-window cut and the met- DIFFUSED
al interconnection patterns. UNDERPASS

Typical electrical characteristics of the 12L gates

within the gate matrix are listed in Table 2. Typical op- INJECTOR
erating characteristics of the gates are given in Fig- BUS

Table 2
Typical G!'!!!racteristics of !2L Gates

Parameter

Output Sink Current. 10

Output Sat. Voltage. VOL
Input Threshold
Pwr.-Delay Product 01+ = IV)
Typical Characteristics at Various Inlector Currents
11=100 nA
300 nA
3 mV
0.48 mV
0.6 pJ
11=1 p.A
8p.A
3mV
0.54 mV
0.6 pJ
'1=10 p.A
80 p.A
4 mV
0.60 mV
1.0 pJ
'1=100 p.A
600 p.A
10mV
0.66 mV
3 pJ
J
-----, r-
Average Prop Delay 6 p'sec 0.6 p'sec 200 nsec 50 nsec
Max. Toggle Freq (D F/F) 6 kHz 60 kHz 400 kHz 3 MHz Figure 7. Sample Layout of B·Gate Cell After Customizing it
Input OFF Current 01IN = 0) 150 nA 1.5 p.A 15 p.A 130 p.A
Output Breakdown Voltage 3V 3V 3V 3V with N + Collector Diffusion, Contact Mask and
Metal Interconnection Pattern.

11-80
 operation with Ij :::;; 50 p-A, turn-off delay becomes the
AN·16
For operating with current levels below 1 p-Algate, an
dominant limitation in speed. Typical toggle rate of a external current setting resistor can also be used.
D-type flip-flop as a function of injector current is
shown in Figure 10. As indicated in the figure, toggle The component layout of a typical bipolar inputl
rates of 3 MHz are obtained at injector current levels output interface cell is shown in Figure 11. Such an
of approximately 100 p-A per gate. 1/0 interface cell contains one bonding-pad, several
- --- - ------------, diffused resistors of varying values, two Schottky-
I clamped NPN transistors and a clamp diode to the
I substrate. Each of the NPN bipolar transistors are
capable of sinking 1OmA of output current, with typi-
I cally a saturation voltage of 0.5V. The breakdown
voltage of the bipolar output transistors is 6V; how-
I ever, modified versions of the XR-300 and XR-500
12L gate arrays are also available with output break-
I
down voltage in excess of 15V. Figure 12 shows
some of the most commonly used input and output

10n~OLlA--------------- ~
Figure 8. Propagation Delay Characteristics of 12L Gates as a BONDING
l I
Function of Injector Current. PAD i

R2 = 10K
Figure 11. A Typical Schottky-Bipolar Input/Output Interface
Figure 9. Average Turn-On and Turn-Off Delay vs. Injector Cur- Cell.
rent.
>- 10MHz
U ~---TO 12L GATES
~
:::l
a
UJ
a: I MHz
u.
UJ
oJ 500
~
~ 200
0
t- 100 kHz
:i
:::l 50
~
X 20
<t

•
:i 10 kHz
O.OIIlA lilA 10ilA 100ilA I mA (a) Input Interface Circuit
INJECTOR CURRENT PER GATE ,------+-- v+
Figure 10. Maximum Toggle Rate of D-Type Flip-Flop as a
Function of Injector Current. 5K
b) Schottky-Bipolar 1/0 Section:

The Schottky-bipolar input/output interface sections OUTPUT

are located along the periphery of the XR-300 and FROMI2LGATE ____~~
the XR-500 gate array chips. In addition, this bipolar
section of the chip contains two sets of resistor ar-
rays located at opposite ends of the chip (see Figure
4) for programming or setting the injector current
levels for the 12L gates. By proper tapping of these
resistor arrays, the injector currents of the gates can (b) Output Interface Circuit
be set to any value between 1 p-A to 100 p-A per gate. Figure 12. Tyipcal Bipolar 1/0 Interface Circuits.

11-81
AN·16
interface circuit configurations available from the the appropriate array worksheet. This pencil layout is
basic bipolar 1/0 cell. done on a blank worksheet where the gate input and
output locations are shown as target dots (see Figure
SEMI-CUSTOM DESIGN CYCLE 5). During the layout, an appropriate symbol is placed
over the corresponding dot on the gate outline, and the
The semi-custom LSI design program utilizing the XR- interconnections and the underpasses between the
300 and XR-500, is devised for maximum versatility, to gates are indicated by pencil lines and with the symbols
suit varying customer needs or capabilities. Figure 13 defined in the layout example of Figure 6. In this layout,
gives an outline of the six basic steps associated with a the bipolar I/O cells do not need to be internally inter-
typical 12L semi-custom program. The sequence of connected. Since these cells are standardized, it is only
these steps are also outlined below: necessary for the designer to specify if a particular I/O
cell is to be used as an input or an output.
( 1) I-'easihility H.eview
and
Step 3. Computerized Mask Artwork Generation:
Logic Conversion to 12 L Cates

(2 )
t Using a specially developed computerized mask gener-
ation technique, the three layers of necessary custom
Ie tooling (i.e., for custom N-type diffusion, contact win-
Pencil Layout on Cate Array Worksheets dow cut; and the metal interconnections) can be auto-
matically generated by a single "digitizing" step from
the pencil layout. This simultaneous and automated

(3 ) •
Computerized Mask Artwork
Ceneration
generation of the three custom mask layers greatly re-
duces the tooling cost and turnaround time, and avoids
mask errors.

., Step 4. Mask fabrication:

The photographic tooling plates, or "masks," are fabri-
(4) Mask I:abrication cated by a pattern-generation technique from the digi-
N+/Contact/Metal Masks tized coordinate information stored in the computer.

~ Step 5. Customizing Prefabricated Wafers:

The prefabricated 12L wafers containing the P-type base
(5) Customizing Pre-I:ab Wafers: diffusion and the gate "fingers" (see Figure 5) are cus-
Collector Diff./Contact and Metal tomized into completed monolithic LSI chips using the
custom Ie tOOling generated in Steps 3 and 4.

(6 )
t Step 6. AssemblylTest and Prototype Delivery:
Assem hly /Test and
Prototype Delivery The completed monolithic chips are first evaluated on
the finished Ie wafer, and later assembled, electrically
tested and delivered as the completed prototypes.
Figure 13. Sequence of Steps Associated with a Semi-
Custom LSI Development Cycle. In many cases, the first two steps indicated in the flow
chart of Figure 13, can be done by the customer, in con-
Step 1. Feasibility Review and Logic Conversion: sultation with Exar, using Exar's 12L Design Kit and the
design instruction manual. Whenever pOSSible, such an
Starting with the customer's logic diagram (preferably approach is recommended, since it greatly reduces the
reduced to flip-flops and gates) the first step is a de- development costs and the turnaround time.
tailed review of the system requirements with regards
to the overall gate count, I/O requirements, operating Typical development cycle containing all the steps out-
speeds, etc., to assure feasibility of integration, and to lined in the flow chart of Figure 13, takes about 8 to 12
choose the most economical gate array chip to be weeks, depending on the circuit complexity, and wheth-
used. If the results of this review indicate feasibility, the er the customer or Exar does the logic conversion and
next step is to convert the logic diagram into 12L gates. pencil layout.
At this state, a computer simulation of the logic dia-
gram may also be performed, if deemed necessary. Figure 14 shows the photo-micrograph of a typical
semicustom LSI chip, fabricated using the technology
Step 2. Pencil Layout on Gate Array Worksheets: outlined in this paper. As indicated in the figure, the use
of 3-mask customization step results in an efficient lay-
Once the logic diagram is converted to 12L gates, the out and utilization of the available active devices within
next step will be to make a pencil layout of the circuit on the 12L gate array.

11-82
 AN·16
tremely high development costs (typically in the range
of $50,000 to $100,000) associated with full custom de-
signs make the amortized unit cost of full custom IC's
far more expensive than semi-custom designs, at low
production quantities. Similarly, for the lower chip cost
of full custom IC's make this approach more economi-
cal for high production volumes. Typical cross-over
point between the economics of the full or semi-custom
technology comes about in the quantity range of
50,000 pieces to 150,000 pieces, as implied by the illus-
tration of Figure 15. However, it should be noted that
Figure 15 is only a typical "case study," and that the ac-
tual cross-over point for a given program will depend on
the circuit complexity, performance and test require-
ments. and the type of IC package used.

III
o
U

]
'~

oE
<l:

10K lOOK
Figure 14. Photo-Micrograph of a Typical Semi-Custom Total Quantity of Units Purchased
12L LSI Chip. Figure 15. A Comparison of Relative Cost Advantages of Semi-
Custom and Full Custom LSI Products. (NOTE: Am-
ECONOMICS OF SEMI-CUSTOM DESIGN ortized cost per unit includes the development
cost.)
In developing custom LSI circuits, one is confronted by
the following key question: for a given production re- CONVERTING SEMI-CUSTOM TO FULL CUSTOM
quirement, is it cheaper to develop a full or semi- It is often possible to start a development program us-
custom IC? Since the performance and functional re- ing the semi-custom technOlogy, such as the 12L gate
quirements of custom IC's vary greatly, there is no gen- arrays described in this paper, and later change to a full
eral answer to the above question. However, based on custom design when the production quantities increase
the overall production requirements it is possible to es- beyond the cost cross-over point illustrated in Figure
tablish some economic guidelines for deciding which 15. Such two-phase approach often combines the best
custom IC technology to use, and when. advantages of each of the semi- and full custom tech-
nologies. For example, the initial development can be
One of the main advantages of semi-custom LSI design done in a semi-custom manner, using Exar's 12L gate
over conventional full custom IC development is the arrays, and thus take full advantage of the low tooling

•
greatly reduced development cost. This development cost and the short development cycle. As a customer's
cost generally amounts to 10% to 30 % of that required product matures and its market expands, resulting in
for a complete custom IC design. However, since the higher volume production run rates, Exar can convert
semi-custom design technique tends to waste some of the multiple semi-custom chip approach into a Single
the IC chip area due to random interconnections, the custom IC, achieving a cost reduction and in many
unit price of a semi-custom LSI chip in volume produc- cases a performance improvement. The significant ad-
tion is slightly higher (approximately 10% to 30 %) then vantage of this type of program is that the risk associ-
a full or complete custom design. Therefore, to decide ated with a custom development is greatly reduced; the
which is the most economical approach, it is best to Ie design approacn has been proven, and the deSign
compare the estimated amortized unit cost per device "bugs" are removed at the semi-custom stage thus
for various production quantities. Figure 15 gives such eliminating the need for lengthy re-design cycles at the
a comparison for a "typical" custom LSI chip, as a full custom level. Once the semi-custom chip is com-
function of total production requirement. The total am- pletely characterized in the user's system, and is used
ortized cost per unit is defined as the total cost of the for the initial production runs, it can be gradually
development plus the production purchase, divided by "phased-out" by a full custom design without interrupt-
the total number or quantity of units purchased. The ex- ing the user's production line.

11-83
 AN-17

XR·C409 Monolithic 12L Test Circuit

INTRODUCTION
The XA-C409 monolithic IC is a test circuit for evalua- sections of XA-C409 is set by the external bias resistor,
tion of speed and performance capabilities of Exar's In- AB, as:
tegrated Injection Logic (l2L) technology. It is intended
V+ - Vbe
to familiarize the 12L user and the digital system design- (1 )
er with some of the performance features of 12L, such AB
as its high-frequency capability and power-speed tra-
deoffs.
where Vbe (== O.7V) is the transistor base-emitter volt-
Figure 1 shows the package diagram of the XA-C409 age drop.
12L test circuit. It is comprised of five separate evalua-
tion blocks as shown in the figure. Blocks 1 and 2 are The total injector current, IT, is shared among 16 indi-
Ootype flip-flops which are internally connected as fre- vidual1 2 L gates forming the frequency-divider sections.
quency dividers. Each of these dividers provide buf- Thus, the operating current of each gate, Ij, is equal to
fered open-collector outputs. Blocks 3, 4, and 5 are 8- 1/16 of the total injector bias, or:
stage ring-oscillators with buffered outputs to be used
for measuring gate propagation delays at different in- Ij = IT/16 (2)
jector current levels.

FREQUENCY DIVIDER SECTION

INJECTOR A CLOCK INPUT

r
The frequency divider sections of XA-C409 test circuits
are made up of two Ootype flip-flops internally connect- RESET
ed in the ( + 2) mode. These frequency dividers are op- 4 OUTPUTS
OUTPUT
erated with serial clocking and parallel reset controls. 03 01 (2)

The internal interconnections of these Ootype flip-flop INJECTOR B N.C.

sections are shown in Figure 2. The corresponding
package terminals are also identified in the figure. The OSCILLATOR N.C.
OUTPUT
flip-flops operate on the negative-transitions of the
clock input, and reset with the reset at a "high" logic INJECTOR C N.C.
state. When the circuit is reset, all the outputs go to a
"low" state. The logic polarities and the timing se- OSCILLATOR OSCILLATOR
OUTPUT OUTPUT
quence of the circuit waveforms are given in Figure 3.
GROUND
(SUBSTRATE) INJECTOR 0
Evaluating the Frequency Divider Section
Figure 4 shows the circuit connection for the frequency Figure 1. Package Terminals for XR-C409 Test IC.
divider section of the XA-C409. The recommended
clock input level is OV and + 1V for the "low" and ...---------0 .,. 2 OUTPUT
INJECTOR
"high" levels. For optimizing high frequency perform- 14
ance, a square wave clock input is recommended with
a source impedance :s 100n.
2

Biasing of Injectors } t40UTPUTS

All of the 16 12L gates forming the frequency divider

sections are biased by the total injector current, ITo ap-
RESET 0------------'
15
plied to the injector terminal (Pin 1) as shown in Figure Figure 2. Block Diagram of Frequency Divider Section.
4. The total injector current, ITo applied to the flip-flop

11-84
 CLOCK INPUT The value of the load resistor, RL, is determined by the
(PIN 161
current sinking capability of the output transistor, T1, in-
ternal to the chip. Since T1 is the output of an 12L gate,
RESET - - - - ,
(PIN 151 11....-_ _ _ _ _ _ _ _ _ _ _--11
r- its worst case sinking current is limited to the individual
gate current, Le.:
+ 2 OUTPUT
(PIN 141 IT
(3)
.. 4 OUTPUTS
16
(PINS 2 ANO 31
-----' This current-sinking capability in turn limits the mini-
mum value of load resistance RL to:
Figure 3. Timing Diagram for Frequency Divider Section.
(4)

The peak output swing is limited to approximately 3

V' 5V - - - . . - - - - - - ,
Rl 8RB volts due to the collector-base breakdown of the 12L
tiT RB gate output, Le., transistor T1 of Figure 5.

til Rl High Frequency Capability

'~nn. 300!! 16
The maximum operating frequency of 12L frequency-
ClK INPUT o-.JI,fI.rv--o-.....
XR·C409
OUTPUT
U O
O 7V
' . divider circuits is a function of the total injector current.
(PIN 2. 3.
OR 141
For low-current operation, the maximum toggle-
01 frequency of the flip-flops forming the frequency-divider
section increases linearly with increasing injector cur-
01 ~ lOW CAPACITANCE -=- rent. Typical maximum toggle frequency vs. injector
CLAMP DIODE -=-
10MHz ,...-----,----,-----r---..,......----,
Figure 4. Test Circuit for Frequency Divider Section.
>
u
z
::>
Measuring Output Waveforms ~
... lMHz
500

Each of the output terminals of' XR-C409 frequency- gg 200

divider are open-collector type terminals which require
~ 100kHz f------+----:;,~-t----+---+------l
a pull-up resistor to positive supply voltage. Thus, the :;
output rise-time is limited by the external RC time con- ;(
..:
50
:;
stant due to the load resistance, RL, and the parastic 20
andlor load capacitance, CL.

Figure 5 shows a recommended circuit connection to TOTAL INJECTO'l CU'IRENT. IT. APPLIED TO PIN 1 (16 GATESI

test the output swing at high frequencies, using a low-

capacitance clamp-diode, D1, to clamp the output Figure 6. Typical Maximum Toggle Frequency vs. Injector
swing to == +0.7V above ground. Current Characteristics for XR-C409 Frequency
Divider Section

(NOTE: Clock Input: 1V POp Square Wave)

v+

•
current characteristics are shown in Figure 6. Note that
the maximum toggle-rate obtainable is in the range of 3
to 5 MHz, at a total injector current level of 1 to 2 mA,
which corresponds to individual injector currents of ap-
proximately 60 p.A to 120 p.A per gate.

D 1 ; CLAMP DIODE RING-OSCILLATOR SECTIONS

The ring-oscillator sections of XR-C409 test circuit are
intended for measurement of propagation delays asso-
ciated with 12L gates. Each of these oscillators are
made up of a cascade of 8 four-output 12L gates. Figure
7(a) shows the basic electrical equivalent circuit of a
four-output 12L gate. Its corresponding logic symbol is
Figure 5. Recommended External Connections to Measure shown in Figure 7(b). The basic gate operates as an in-
Output Waveforms. verter with single input and four outputs.

11-85
AN·17
INJECTOR IPIN 41

IPIN 51
OSCILLATOR

'I
n--...-I--O 0 UT PUT

INPUTS
ICOMMON) 0---+--_--£
2

:
OUTPUTS

INPUTS ~ d1

OUTPUTS

PIN 8
lal
LOGIC SYMBOL
EQUIVALENT CIRCUIT

Ring Oscillator Using Single Gate Output per Stage

Figure 7. Four-Output 12L Gate
(Section 3)

The propagation delay through an 12L gate depends on

the following sets of parameters:
IPIN 9)

1. Device design: (i.e., manufacturing methods and

device layout used in fabrication process). IPIN 10)
OSCILLATOR
n-~--o OUTPUT
2. Injector current level: (gate switching speed in-
creases with increasing current, until a maximum
is reached).
PIN 8
Ibl
3. Choice of outputs used: (the output closest to the
injector has minimum propagation delay at high
currents). Ring Oscillator Using Two Gate-Outputs per Stage
(Section 5)
4. Number of outputs used: (if fewer outputs are
used and the unused outputs left open, the gate
delay is Lower at low currents. However, at high
currents, i.e., Ij <:! 100jtA/gate, gates with fewer IPIN 61

outputs left unused show lower delays. This is due o INJECTOR

to excess storage-time effects due to open-

!PIN 71
circuited gate outputs. See Figure 10.)

Figure 8 shows the basic seven-stage ring-oscillator cir-

cuits included on the XR-C409 chip to evaluate the
Li=OO}---- OSCILLATO"
"----'----" OUTPUT

propagation delay characteristics of 12L gates. Since PIN 8

the delay characteristics depend on the choice and the lei

number of gate outputs used, the test IC includes three

separate ring oscillator sections. The ring oscillator of Ring Oscillator Using Four Gate-Outputs per Stage
Figure 8(a) corresponds to section (3) in the package di- (Section 4)
agram of XR-C409 shown in Figure 1. This oscillator us-
es only one gate-output per gate. The output used is the
one closest to the injector, with the remaining outputs Figure 8. Equivalent Circuits of the 7-Stage Ring Oscillator
left open-circuited. Section.
The ring-oscillator of Figure 8(b) uses two gate outputs
per stage. The outputs used are the two closest to the

r
v+
injector. The ring oscillator of Figure 8(c) has all four
outputs shorted together.

All three oscillator sections of XR-C409 have separate

injectors, but share a common ground (pin 8). Each os- OSCILLATOR
cillator also has a separate output buffer stage. OUTPUT

Figure 9 shows a recommended test circuit for evaluat-

ing gate delay vs. gate current characteristics using the
Jill
ring oscillator sections of XR-C409. Since each ring-
D, = LOW CAPACITANCE
oscillator section is comprised of 8 gates, the actual in- CLAMP DIODE
jector current per gate, Ij, is 1/8 of the total injector cur-
rent, IT,:
Figure 9. Recommended Test Circuit for Evaluating Power-
Ij = injector current/gate = ~ (5) Delav Characteristics of 12L Gates Using Ring
Oscillator Sections of XR-C409.
8

11-86
 AN·17
The total injector current, IT, is determined by the exter- where N is the number of stages in the ring oscillator.
nal bias resistor, RBm as given by equation (1).
For the case of the 7-stage oscillator circuits in the XR-
Measuring Output Waveforms C409 test chip, Td can be calculated from equation (8)
by setting N = 7.
The output terminals of XR-C409 ring counter sections
are open-collector type terminals, similar to the outputs Figure 10 shows the typical gate-delay vs. injector cur-
of the frequency divider sections. Thus, the outputs re- rent characteristics measured from the three ring-
quire pull-up resistors to the positive supply voltage. oscillator sections of XR-C409. In the figure, the gate
The output rise-time is strongly affected by the external delay is plotted as a function of the injector current per
RC time constant due to the load resistance, RL, and gate. The gate geometry layout of XR-C409 ring-
the parasitic load capacitance, CL. In the test circuit of oscillator sections is not optimized for high frequency
Figure 9, a low-capacitance clamp diode, D1 is used to operation.
limit the output swing and thus minimize the slow rise-
time effects.
10", , . . . . - - - - - , - - - - - , - - - - - , - - - - - - - ,

The minimum value of load resistance, RL, is deter-

mined by the current sinking capability of the output 12L
gate. For proper operation of the ring-oscillator circuits,
the load current, IL, should be limited to:
1"'I--~~~----_+_----+_---__l

IT 500
IL ::$- (6)
4 SECTION 3
200 (ONE·OUTPUT /GA TEl
which limits the output load resistance, RL, for ring-
loon'I-----+-------f"'I~,___--+_----__t
oscillator sections to:
50
(7)
20 SECTION 4
Calculating Propagation Delays (4 OUTPUTS/GATE I
lOn, L-......L-_...J....---1._..I..-_I.--I....---1._-.l...-:-:~--'--...J....~
.1"A I"A 10"A 100"A lmA
The average propagation delay Td per gate can be cal- INJECTOR CURRENT PER GATE. Ij
culated from the ring oscillator frequency, fo as:
Figure 10. Typical Propagation Delay vs. Injector Current
1 Characteristics as Measured from 7-Stage Ring
Td = --sec (8)
2Nfo Oscillator Section of XR-C409.

•
11-87
 AN-18
Designing Wide-Tracking
Phase-Locked Loop Systems
INTRODUCTION
Phase locked-loops with their excellent frequency The actual driving voltage for the VCO is now a voltage
tracking characteristics have found their way into many proportional to fi which can be varied a fixed percent-
applications where synchronizing or synthesizing of sig- age by the phase detector.
nals is required. Although they do have the ability to
track an incoming signal very well, the actual tracking CIRCUIT DESIGN
range is quite limited by the nature of PLL's to less than
2:1. This range of less than 2:1 must be observed if har- The heart of the circuit is the XR-2212 Precision Phase-
monic locking, a plague to the designer, is to be avoided. Locked Loop. Figure 2 shows the XR-2212's internal
blocks and necessary external components. The VCO
This application note describes the design of tracking in the XR-2212 is actually a current controlled oscillator.
PLL with a tracking range of greater than 100:1, with Pin 12 is fixed at the reference voltage, Vr :: V; ,and
no harmonic locking problems. This design uses the
XR-2212 Precision Phase-Locked Loop in conjunction the current drawn from this terminal controls the fre-
with the XR-320 Monolithic Timer and an XR-084 Quad quency of oscillation of the VCO, fO. With RO grounded,
BiFet Operational Amplifier to form a wide range PLL as shown, the VCO's free running or center frequency
with automatic tuning. is:

PRINCIPLES OF OPERATION fO = _1_

ROCO
Figure 1 shows the block diagram of the tracking PLL.
The circuit is comprised of three blocks: the PLL, the RO and Co are calculated using this relationship at fO
Frequency to Voltage Converter, and Precision Clamp- maximum. With the PLL locked on its center frequency,
ing Circuit. The blocks operate as follows. The PLL the phase detector's dc output, Pin 10, is also at Vr and
locks onto the incoming frequency and produces an the current flowing in RO is proportional to fO. If the bot-
output frequency identical to that of the input, but tom end of RO is now raised above ground, the current
phase shifted. The center of the lock range is controlled in RO will change linearily with the voltage, as will fO
by Vl. Vl is derived from the FN converter, which pro- thus providing the voltage control input for the VCO. If
duces a voltage proportional to the incoming frequency. RO is left at zero volts and fi is moved, the dc voltage at
This voltage, Vl, thus provides an automatic PLL center Pin 10 will inversely follow fi, increasing fi decreases
frequency tuning signal. The swing of the phase detec- the voltage at Pin 10, modulating the current from Pin
tors filtered voltage, V2, controls the amount the VCO 10 and thus fO. The maximum swing of Pin lOis:: ± Vr,
can be moved about its center frequency. The precision giving the following relationship:
clamp fixes the swing on V2 to a fixed percentage of Vl, ±Vr
keeping the tracking range of the PLL constant as its
center frequency is varied.
.:1f R1 RO (V rRO)
±-=--=-±--= ±-
RO
fO Vr R1 R
Vr 1 R1
AD
fin--_-~.I
INCOMING .:1f being the PLL's tracking range.
SIGNAL

0--+-""*--+-----<.
fo
OUTPUT

g
,e_ 1•

. "1- ""
Co _
INV 7

OP AMP

Figure 2. XR-2212 Internal Blocks

Figure 1. Tracking PLL Block Diagram. with External Components.

11-88
In our application a constant ~ is desired, so if the out- WIDE RANGE SYNTHESIZER USING RR-2212 PLL
put of the phase detector, Pin 10, is clamped to - VRO, This same technique of automatic tuning can be used
the voltage across RO, a constant tracking range will be to form a wide range synthesizer as shown in the block
maintained. C1 serves as the loop, low pass filter, and is diagram of Figure 5. Here a programmable frequency
made to equal ~o for a damping of 1/2 •
divider has been put into the loop between the VCO out-
put and the phase detector input. Since the PLL will
drive the VCO until its two inputs are at the same fre-
The voltage driving RO comes from the FN converter quency, the VCO will be at:
which is formed by the XR-320 Monolithic Timer. The in-
ternal blocks and external components of the XR-320 fVCO == Nf r where N in the binary number ap-
are shown in Figure 3. The input to the FN is brought to plied to the programmable divider
the trigger input, Pin 6, which, when driven above the (N ~ 1)
threshold, triggers the F/F and opens the internal
switch transistor, S1. The voltage on CT will linearily The FN converter used in the previous application to
rise, at a rate set by RT until Vr is reached at which time drive RO, or tune the PLL, is now replaced with a digital-
the comparator resets the F/F and closes S1, waiting to-analog converter, DAC. Its digital inputs come from
now for the next rising edge on Pin 6. Once triggered the same lines which control N. The DAC's output volt-
the output, Pin 12, will go low for the timing period de- age, which drives RO, will now vary proportionally with
fined by the relationship: N, or retuning the PLL with each new N. The same
clamping network is used on the phase detectors out·
put as discussed earlier.

Since Pin 12 will now have a constant low time and a

repetition rate equal to that of the incoming signal, fi, it
can be filtered to provide a voltage proportional to fi.

Figure 4 shows the complete tracking PLL circuit. The

precision clamp is formed by A1-A3 which samples the
voltage across RO and clamps the XR-2212's phase de-
tectors output to ± VRO. With the given values, the
tracking range of the circuit is one kHz to 100 kHz, with
INPUT FROM II
the XR-2212's tracking range set at approximately ± ...r
0.33 fa. The input frequency voltage range is 10 mV
RMS to 3 V RMS with the output producing a 10 pop v
square wave. Calibration is done by first applying 100
kHz to the input and adjusting P1 for fa equal to fi in fre-
quency but shifted in phase by approximately 90°, then
with fi :::: 1 kHz P2 is adjusted again for equal frequen- Figure 3. XR-320 Internal Blocks with
cies with 90 0 of phase shift. External Components.

+12v~-------------'----------------~+-~

I°Lr-------------r----------~~~--+_~

5.6K

12K
•
A,'A3 = ~XR-084
P,= >FULL SCALE ADJUST
=
P2 >ZERO ADJUST

Figure 4. Wide Range Tracking PLL.

11-89
AN·18
Figure 6 shows the complete wide range synthesizer put voltage range is 10 mV RMS to 3 V RMS with the
circuit. The two 4-bit binary counters, 74161, and mag- output providing a T2L compatible square wave.
nitude comparator, 8130, form the programmable di-
vider. The output of the divider is a variable duty cycle
pulse so that the flip-flop, 7474, was added so that
phase detector was always presented with a square
wave. Since the flip-flop also divides by two, the mini-
mum value for the divider will be 2 or the actual N of the
overall divider will be the binary input times two, 2N.
The DAC uses the reference voltage of the XR-2212 as
1 0 0 - - + - - - - -.........
its reference with amplifier A4 used to scale the voltage
to AO correctly. C1 provides loop compensation and its
value will determine not only the response of the circuit
but the short term frequency stability of fa. A trade off
must be made here as decreasing C1 will provide for a
faster responding loop but decrease the short term sta-
bility of fa. It is probably most desirable to have a highly
stable output frequency and slower responding loop,
which the values in Figure 6 provide for. FROM VREF
OF XR·2212

With the values shown, fo will be one kHz to 100 kHz

with fref :::: 500 Hz and N :::: 1 to 100. The reference in- Figure 5. Wide Range Synthesizer Block Diagram.

24K

+12v 0-----------------4t-----+---+-'-I

'REF O - - - - - - - - - - - - - - - - - - - i r-r-----i~

'oO------+--~-----~--------.

.sv~_n==EE=~llP.
DIGITAL GND~

0----:L
ANALOG GND

750!1
Al - A4 ; > XR·084
Pl ; > FULL SCALE ADJUST
P2 ; > ZERO ADJUST

10 ; 2 N Irel 1 s Ns 1DO
Ire I ; 500HZ
"'--4~t-iVcc A7 A6
Aa
10K A9
8a
89
Z (OUTPUTl
87 86 8 5 84 8 8 2 B1 BO GND
3

LS8

51K
IIIS8

8 3 8 4 8 5 8 6 B7 Ba i
-12. 0----=----....--1 ~ 0

V
LC
V
REF
- V
REF
+ To
+12.
20K

Figure 6. Wide Range Synthesizer.

11-90
Calibration is done by first adjusting P1 for a 100 kHz
AN·18
Typical input and output waveforms for rref = 500 Hz,
output with N = 100 and then adjusting P2 for a one top trace, and fo, bottom trace, with N switching from
kHz output with N = 1. 40 to 8 are shown in Figure 7.

Figure 7. Typical Input and Output Waveform.

•
11-91
 AN-19
Clock Recovery System
INTRODUCTION
Recovering encoded serial data from floppy disk sys- Figure 2 shows the block diagram of the clock recovery
tems poses a major design problem as the synchro- system. The XR-320 forms a bi-directional one-shot. It
nized clock used to encode data is embedded within will produce a positive output pulse for both rising and
the data stream. The clock cannot be readily extracted falling edges on its input. The period of these output
using common phase-locked loop techniques as the ac- pulses is set equal to one half the total period of clock.
tual clock may appear for only short periods of time in a This is used to provide a frequency component in the
common encoding format such as NRZI. This clock is data stream equal to the clock even under worst case
necessary to decode the serial data and retrieve the data conditions of five ones, zero, five ones, zero. (Seen
original data. in Figure 1.) This can also be seen to double the fre-
quency of the data stream which is desirable as the
This application note describes the design of a PLL PLL will now be able to lock to the original clock. The
(phase-locked loop) system which can be used to re- XR-2212 forms the PLL which, when the actual clock
cover the clock from a serial data stream using NRZI appears in the data stream, locks to and produces a
protocol with very excellent stability. The design utilizes frequency at its veo output equal to and synchronized
the XR-2212 Precision Phase-Locked Loop in conjunc- with the clock. The PLL's phase detector output is con-
tion with the XR-320 Monolithic Timer to form the heart nected to the input of a sample and hold (8tH) as well
of the system. The system also uses a 74123 Dual One- as the 8tH's output through a switch. This switch is held
8hot and 398t13333 for timing and sample and hold open by the 74123 as long as the clock appears in the
purposes. data stream. Whenever a one is present the clock will
not appear in the data stream and the 74123 places the
PRINCIPLES OF OPERATION sample and hold in the hold mode and closes the
switch. This holds the voltage at the phase detector and
Figure 1 shows a data stream and clock using a typical keeps the proper driving voltage to the veo, thus main-
NRZI protocol. In this protocol changes in levels repre- taining the frequency at the output of the veo equal to
sents a binary zero, while no transitions a binary one. and synchronized with the clock.
From the figure it can be seen that the data stream can
have a maximum rate of change corresponding to a fre- DUAL ONE·SHOT
quency equal to one half the clock frequency with the
actual data being a string of zeros. This format guaran-
tees that there will be no more than five ones in a row.
The slowest rate of change will then be a frequency
corresponding to one twelfth the clock.

ACTUAL DATA 0 0 0 0 I I I I I 0 I I I I I 0 0 0 I

NRZI
ENCODED
DATA STREAM

CLOCK

II
Figure 2. Clock Regenerator Block Diagram.

When the clock reappears in the data stream the 74121

drives the switch open and 8tH to the sample mode
T2 1;-, I n~ ___.---L with the PLL once again tracking the clock in the data
H RETRIGGERED BEFORE
I.n IT TIMED OUT stream. The length of T1 is made equal to slightly less
than the period of the clock so that the 8tH is always
ready in the event the clock is not in the data stream
and any sample to hold glitches will not be transmitted
10 to the phase detector's output. The length of T2 is made
REGENORATED slightly longer than the clock period which will cause
CLOCK
the switch to close immediately after one clock pulse is
missed. With a clock period T, these times, T1 and T2,
Figure 1. System Timing Diagram. are set equal to 0.8 T and 1.2 T, respectively.

11-92
 PHASE SHIFT
AN·19
CIRCUIT DESIGN BETWEEN
V,

'0 AND',
The heart of the circuit is the XR-2212 Precision Phase-
V+
Locked Loop. Figure 3 shows the XR-2212's internal
blocks and necessary external components. The phase
detector output is a high impedance current source out-
put so it can be forced or held at a particular voltage r-- V+ 2

I
easily, as by the S/H. The PLL's center frequency is I
equal to: I

fo = _1_
ROCO Figure 4. PLL In/Out Phase Relationships.
The XR-320 Monolithic Timer used for the bi-directional
RO and Co are calculated using the data stream's clock one-shot is shown in block form with its external com-
frequency set equal to fo. The tracking range of PLL is ponents in Figure 5. The control flip-flop can be trigger-
given by the following relationship: ed by either positive or negative edges on its inputs,
which are tied together for this application to provide bi-
~f = fo -R1 ~f => tracking range directional triggering. Once triggered, the output will
R1 provide a low level signal for a period defined by:

TLOW = 2 RTCT

These components are calculated with TLOW set equal

to one half the clock period.

Co
5,/

Figure 3. XR-2212 Internal Blocks with External ----1~

Components. v+~L
I -=
______ - - - - -

10K
The phase relationship between the incoming signal, fi'
and the output signal, fo, will be 90° if fi is equal to fo LOGIC
OUTPUT
10

and will vary up 90° or down 90° from this nominal if fi

is at either end of the tracking range. The voltage at the
output of the phase detector will also vary linearly with
these phase relationships. These relationships are
shown in Figure 4. The tracking range is made very
large since a constant phase relationship between the Figure 5. XR-320 Internal Blocks with External Components.
recovered clock is desirable. Therefore, any errors in Table 1 summarizes the previously described formulas
the S/H or drops through the switch will not significantly as well as those for the 74121 Dual One-Shot.
alter this phase relationship. ~f is made equal to. ap-
proximately 0.8 fo, and R1 is calculated accordingly. C1 Table 1
is used to remove the double frequency component

•
from the phase detectors output and also in conjunc- FOR XR-2212 FOR XR-320 FOR 74123
tion with Co controls the PLL transient response char-
acteristics, according to the following relationship: (1) RoC o = _1_ (4) RTCT = _1- (5) REX1CEX1 =
fCLK 2fCLK
1
~ = 1f4.JCO (2) R1 = 1.2 Ro 0.8 fCLK In 2

C1 = Co (6) REX2CEX2 =
(3)C1
4
_ Co
for a loop damping of V2, C1 - "4
1.2 fCLK In 2

11-93
AN·19 +5YO--------------------~~+_------------~------------~_.~----~~--~

10K REX,
XR·320 74123 15K

I 10~pr
14
f, o-.-------------~~

DATA STREAM
'- Y+

PLUS CLOCK
P,
100pF
5K

6.1 RT
18K
RT
lOGIC 10
TR,
10K OUT
CT 0,
IN914
GND CT
100pF f1 GND
8 1

GNDo---------------------~_+------------~~--_4------~~-~+_--_r------------_+--------~

f-----.-----+-----'
0.1,.F
+12YO------------~--+_--------------------+_------------------~~r_------------r-~

14
fo ~---------------.-~--~
REGENERATED
12
CLOCK

y-

82K RO

Co 820pF 5K

-12Vo-------------------------------------------------------~--------------~

P, = " ADJUST SO POSITIYE PORTION OF Ii IS EOUAl TO ", OF THE CLOCK PERIOD

P2 = ;. ADJUST FOR 90 PHASE SHin BETWEEN f1 and fo WITH" = fClK

Figure 6. Complete Clock Regenerator.

Figure 6 shows the complete clock recovery circuit

with values designed for a clock of 122 kHZ. The input
to the system will accept input low levels from 0 V to
0.5 V levels and high levels from 1.5 V to 5 V. The output
provides a 10 V P-P square-wave. Calibration is accom-
plished by adjusting P1 for the output of the XR-320 to
equal exactly one half of the clock period and P2 for a
90 0 phase shift between fi and fo with a constant string
of zeros applied at fi.

The oscilloscope photograph in Figure 7 shows the sys-

tem waveforms with the input data stream on top and fo
on the bottom.

The same circuit can be used to regenerate or clean up

a clock with occasional missing cycles by applying it to
the point labeled fi and eliminating the XR-320 from the
circuit.

Figure 7. System Waveforms.

11-94
Buildong a Complete IFSK Modem Using
XR·2211 and XR·2206
INTRODUCTION
phone line, while it will decode to "1's" and "a's" 2025
With the number of digital systems and equipment Hz and 2225 Hz received from the line. The originate
growing so rapidly, the need for a method of moving da- modem simply reverses the frequencies for send and
ta has also become a fast growing field. This applica- receive. The sinewave modulator will produce two dis-
tion note describes the construction of a modem sys- crete frequencies at its output corresponding to a "1"
tem using frequency shift keying, FSK, for serial data or a "a" at its data input. The line hybrid will steer these
transmission. The system utilizes the XR-2206 as a frequencies to the phone line while causing received
modulator, the XR-2211 as a demodulator, and an frequencies to go to the bandpass filter and demodulat-
XR-084 op amp as a bandpass filter. These three IC's or. This block will therefore provide isolation between
make up a complete working 300 baud, full duplex, FSK modulator and demodulator at each end. The bandpass
modem. filter is used to remove unwanted signals and noise re-
ceived from the phone line before they reach the
GENERAL DESCRIPTION demodulator.

Figure 1 shows the block diagram of an FSK system. The PLL demodulator will lock onto incoming frequen-
The complete system is comprised of an answer and cies at its input and produce "1's" or "a's" at its output.
originate modem. The answer modem will convert input The carrier detect output will produce a low, "a" signal
data to either 1070 Hz or 1270 Hz and send it to the out when valid data is being received.
ORIGINATE MODEM ANSWER MODEM

PHONE LINE

Figure 1. Block Diagram of FSK Modem System.

OPERATION AND CALIBRATION

number of bits per second which can be sent and re-
The circuit has been designed for + 12 volt operation. ceived. The answer can be used to drive the originate
The data inputs accept TIL compatible signal levels, and vice-versa. R19 is then adjusted for a square-wave
while the outputs provide OV to + 12V signal levels. on the data received output.

Calibration is done by first adjusting the modulator. With

a low signal on its input, R21 is adjusted for 1270 Hz or
2225 Hz for originate and answer respectively. Then
with a high signal in, R22 is adjusted for 1070 Hz or
R20 is used to set the modulator output level. With the
modulator output set at - 6 dBm, the system will oper-
ate with an input signal range of + 10 dBm to - 48
dBm.
II
2025.
CIRCUIT CONSTRUCTION
The demodulator is easiest adjusted by feeding into the
modem input an alternating 1070 Hz/1270 Hz or 2025 Figures 2 and 3 show the circuit schematic and compo-
Hz/2225 Hz signal in a square-wave fashion. The modu- nent layout. One PC board is used for answer or origi-
lating frequency should be 150 Hz, which is one-half nate and should use the appropriate components as
the system baud rate of 300. The baud rate refers to the listed in Table 1.

11-95
AN·20
~--~--,-----~-,--~----------------------------~·-oV+
RI3
CARRIER
RI2 DETECT

DATA
CI2 RECEIVED

IC2

RI

~~~+-~~~------~----------~--~--+---4-~--~-oGHD

R26

~
o R21
PHONE DATA TO
LINE BE SENT
~-------------------o
R24

Figure 2. Complete FSK Modem Using XR-2211 and XR-220S.

SOK 2K
POTENTIOMETER POTENTIOMETER

DATA TO BE SENT

V.

GND

CARRIER DETECT

DATA RECEIVED

PHONE
LINE

Figure 3. XR Modem Foil Side Shown (Not to Scale).

11-96
 AN·20
Table 1. Modem Parts List

IC1A-D XR-084
IC2 XR-2211
IC3 XR-2206

ANSWER ORIGINATE

R1 * 40.2K 47.5K
R2* 499 191
R3* 270K 357K
R4* 60.4K 39.4K
R5* 680 160
R6* 383K 270K
R7* 24.9K 20K
R8* 1.21K 360
R9* 160K 160K
R10 1K 1K
R11 1K 1K
R12 5.1K 5.1K
R13 5.1K 5.1K
R14 510K 510K
R15 510K 510K
R16 100K 100K
R17 47K 100K
R18 7.5K 9.1K
R19 2K 2K
R20 50K 50K
R21 2K 2K
R22 2K 2K
R23 3.9K 8.2K
R24 3.6K 6.8K
R25 200 200
R26 1M 1M
R27 1M 1M
C1- C6* 0.01 0.01
C7 0.1 0.1
C8 22 22
C9 0.01 0.01
C10 0.1 0.1
C11 0.022 0.01
C12 0.1 0.047
C13 1 1 I

C14
C15
C16
C17
0.1
0.1
1
1
0.1
0.1
1
1
II
I

All resistors are 1/4 watt - 5 % tolerance, except as

marked with (*) which are 1 % tolerance. Values given
in (0).

All capacitors are 5 % tolerance, except as marked with

(*) which are 1 % tolerance. Values given in IlF.

11-97
 AN-21

Precision Narrow-Band Tone Detector

INTRODUCTION PRINCIPLES OF OPERATION
The Phase-Locked Loop (PLL) is a very versatile build- Figure 1 shows the block diagram of the narrow-band
ing block with a wide range of applications in signal pro- tone detector using the XR-2208 and XR-2213. The
cessing and communication systems. As a tone detec- XR-2208 is being operated as a balanced modulator or
tor or tone discriminator, the PLL is accurate and stable frequency mixer. It "mixes" the input frequency, fiN,
enough for most applications not requiring very narrow with a stable frequency source, fe, to produce the sum
bandwidths. The smallest, practical detection band is and difference frequencies of fiN and fe. The low pass
limited by the temperature stability of the PLL center filter removes the higher frequency component (fiN +
frequency and accuracies of external components. For fc) and passes the difference frequency to the XR-2213
example, designing a tone detector using a single PLL PLL. The input signal is "mixed-down" in frequency in
to discriminate a 10Hz tone out of 100 kHz can present this manner, allowing the PLL center frequency, fo, to
great difficulty. A PLL with center frequency of 100 kHz be set at a much lower frequency than the input signal.
can drift by 2 Hz/oe given a typical center frequency With a lower fo, the PLL drift (Hz/°C) becomes less,
drift of 20 ppm/ceo A slight change in ambient tempera- making the tone detector less susceptible to ambient
ture can cause the PLL to unlock. On the other hand, temperature changes.
there are various applications involving pressure trans-
ducers and crystal oscillators that require a very stable The input signal to the XR-2208 is a periodic waveform
system capable of detecting a small change in frequen- with frequency of:
cy over a wide frequency spectrum.
fiN ± AflN
This application note describes the use of the XR-2213
PLL in conjunction with the XR-2208 analog multiplier where AflN is the detection range. The range of fre-
as a frequency mixer. It is capable of detecting a 1 Hz quencies for detection is between fiN - AflN and fiN
tone out of a frequency spectrum greater than 1 MHz. It + AfIN. It is necessary to band-limit the input frequen-
can accept almost any periodic waveform including cy for proper operation of the tone detector. Since the
sine, square, and triangular waves. Error due to temper- XR-2208 takes the "absolute" difference in frequency
ature drift is typically 0.2 %/oe. The tone detector out- between fiN and fe, it is possible to obtain the same
put changes to a high state when the input is within the output frequency with different values for fiN, causing
detection band. the tone detector to lock onto the "wrong" frequencies.

IC

I
DETECTOR
j---------...- t:>-t-o
... I
"OUT

I
L- - - - - - - - - - _...J r- H1
--.J LO

Figure 1. Functional Diagram of Narrow Band Tone Decoder.

11-98
 AN·21
In order to band-limit the input frequencies, a low pass Table 1. Tone Decoder Performance vs. ~fIN/fo
filter with very sharp roll-off (6th order or higher) with
the corner frequency around fiN can be used. For high TYPICAL NORMALIZED
frequency applications (fiN > 100 kHz), a bandpass PLL fo RELATIVE
crystal filter can be used. Crystal filters have stable fre- ±~fIN
STABILITY ACQUISITION MAXIMUM fiN
quency characteristics and very high Q's (Q > 1000) fo (Hz/cC) TIME ALLOWED (Hz)
making very sharp bandpass filters. Crystal filters are
0.1 % 0.02 x ~flN 0.1 fiN + ~fIN(1999)
commercially available through various manufacturers. 0.5 % 0.004 x ~flN 0.5 fiN + ~fIN(399)
1.0 % 0.002 x ~flN 1.0 fiN + ~fIN(199)
The control frequency, fC, must come from a very sta- 5.0 % 0.0004 x ~flN 5.0 fiN + ~fIN(39)
ble and accurate source since any error in fC will di- 10.0 % 0.0002 x ~flN 10.0 fiN + ~fIN(19)
rectly affect the tone decoder. A crystal oscillator with a 20.0 % 0.0001 x ~flN 20.0 fiN + ~fIN(9)
"divide-by-N" counter as shown in Figure 2 can gener-
ate a very stable frequency, with temperature stability
fo = PLL center frequency
in the range of 1 ppm/DC.
fiN ± ~flN = input frequency range
The control frequency is given by:
DESIGN EQUATIONS (All R's in ohms; all C's in farads)
fC = fiN + fo
1. The XR-220S control frequency, fC, is given by:
where fo is the PLL center frequency in Hz. the Choice
of fo is arbitrary, however the larger fo is, the more the fC = fiN + fo
PLL becomes susceptible to temperature variations but
2. The maximum input frequency allowed is:
the better the acquisition time or "pull-in" time be-
comes. One the other hand, if fo is small, then tempera-
flN(max) s fiN + 2fo - ~fC
ture variation has less effect but acquisition time be-
comes worse. Table 1 shows the relative performances Where ±~fC is the capture range of the PLL.
of the tone decoder with respect to the ratio of ~fINlfo.
3. The capture range, ±~fC, is set as:
The output of the low pass filter is fed into the pre-amp
of the XR-2213 PLL. When this frequency falls within ±~fC = ±~fIN
the detection band or the PLL (fo ± ~fc), the voltage
comparator goes to a high state and remains there until Where ± ~flN is the input frequency variation.
the input frequency falls outside the detection band;
the output voltage then goes to a low state. when there 4. The lock range, ± ~fL' is set equal to ± ~fC:
is no input signal applied to the XR-220S, the PLL out-
put remains low. .:lfC RO
(Hz)
fo R1

5. The loop damping factor, 0, is set to 0.63:

IC

0=.1 @Q
4~C1
R 6. The PLL center frequency, fo, is given by:

fo = _1_ (Hz)
ROCO

L--_ _ _ _~

5MO-10M!1
20 pF
1 pG - 30 pF
C,
7. Loop detect filter capacitor, Cd, is given by:

RD is set to 470 kO.

Increasing Cd slows down the logic output response
time.

S. The low pass filter time constants, CF and RF:

~fC in Hz

• I

C1 Pulls the crystal down (lower frequency) RF CF = ..!. RF s 20 kO

fo
C2 Pulls the crystal up (higher frequency)
Where fo is the PLL center frequency.
Figure 2. Crystal Oscillator.

11-99
AN·21
DESIGN EXAMPLE 5. ±.::lfC = ±.::lfL = ± 10 Hz
Consider the design of a narrow-band tone detector R1 = Rofo/.::lfC = 100 KO
with frequency detection range of 111.7 kHz ± 10Hz
(fIN ± .::lfIN)· 6. The damping factor is set to 0.63:
1. Choose the PLL center frequency to be 100 Hz.
C1 = Co (~)2 = 0.16",F
fC = 111.8 kHz
7. Loop detect filter constants:
fC can be produced by using a 3.58 MHz crystal (ad-
justed to 3.5776 MHz) and using a divide-by-32 Choose RD = 75 KO to prevent harmonic locking.
counter in a crystal oscillator.
Cd = 16/20 Hz = 0.8 ",F
2. Maximum input frequency allowed is:
8. Low pass filter time constants, CF and RF:
flN(max) = 111,890 Hz
RF = 20 KO
3. Capture range, ± .::lfC is: CF = 1/foRo = 0.5 ",F
±.::lfC = ±10 Hz A circuit schematic for the above tone detector is
shown in Figure 3.
4. PLL center frequency is 100 Hz (fo):
Choose Ro = 10 KO (choice is arbitrarily set be- Typical acquisition time for this circuit is less than 100
tween 10 KO ::5 Ro ::5 100 KO) msec.

Co = 1IfoRo = 1.0 ",F

+10 V +10 V

~O.I~F ~ 0.1 ~F

10 Kll

IC

YOUT

RO 8 Kfl + 5 Kfl pot

Co 1.0 ",F (non-polar)
R1 100 Kfl
C1 = 0.16/-LF
RO 75 Kfl
Co 0.8/-L F

c· 20 pF
RF 20 Kfl
C··3.571I1Hz
CF 0.5/-LF

Figure 3. Circuit Schematic of Narrow Band Tone Decoder.

11-100
 AN-22
XR·210/XR·215/XR·S200
Phase·Locked loops
INTRODUCTION
This Application Note discusses the various parameters produces a periodic signal whose frequency is propor-
and equations used in applying the XR-210, XR-215, tional to the error voltage. The VCO is actually a "cur-
and XR-S200 Phase Lock Loop (PLL) successfully. It de- rent" controlled oscillator (ICO) in the sense that it is
scribes the operation of the phase detector and the the current derived from VOUT that actually controls
voltage controlled oscillator as well as a discussion on the frequency of oscillation.
phase comparator gain, VCO gain, lock range, capture
range and free running frequency. A section on low
pass filters contains most common RC filters and a dis- PHASE
VOUT
lOW PASS
COMPARATOR Fll TER
cussion on damping factor. Finally, a summary of PLL
parameters and a design example are included.

XR-210
The functional diagram of the XR-210 Phase Locked
Loop (PLL) is shown in Figure 1. The phase comparator
produces a dc voltage which is directly proportional to
the phase difference between the two input signals.
This error voltage, VOUT, is then filtered and applied to
the voltage controlled oscillator (VCO), which in turn Figure 1. Phase Locked Loop Functional Diagram.

V+ o-----------~----------_.--------------------------~

3.2 K!l 6 Kl! 6 K!l

t Your

1 mA
BIAS
1 mA •
Figure 2. XR-210/XR-215 Phase Comparator.

11-101
AN·22
PHASE COMPARATOR +V

The circuit diagram of the XR-21 0 phase comparator is

shown in Figure 2. The input pins (4 and 6) and the bias
pin (5) are externally biased to approximately 112 V + to
insure proper operation. The input signals must be ca-
pacitively coupled to Pins 4 and 6.
- - - - +6 V
The output voltage on Pins 2 and 3, VOUr. depends on
the relative phase, ¢, of the iput signals. The change of VOUT
VOUT with respect to the change in ¢ is defined as the
phase comparator conversion gain and is given by: --- ~6V

Figure 3a. 90° Out of Phase.

K¢ = Ll VOUT VOLTS
(1 )
Ll¢ RADIAN +V

To examine how VOUT changes with ¢, consider the fol- -v

lowing three cases. It is assumed that the input voltage
is large enough (> 50 mVRMS) to cause limiting in the Y,N (6)
differential stage. All calculations are done at V + = 12
volts.
- - - +6V

Case 1: Input voltages are equal to the bias voltage.

VOUT

The operating current is shared equally between tran- - - -6V

sistors 022, 028, 039, and 040. This causes approxi-
Figure 3b. 45° Out of Phase.
mately 0.5 mA to flow through the output resistor (6 K!l)
and hence VOUT = 0 volts. The voltage on Pin 2 and
OUTPUT PHASE
Pin 3 is approximately equal to: VOL TAGE DIFFERENCE
(VOUT) (.!,)
V+ - (0.5 mA) (6K!l) = 9 volts.
+6 V 180
Case 2: Input voltages are both greater than the bias.

022 and 040 conduct 1 mA each, causing 038 to con-

duct 1 mA. Therefore V2 == 6 volts, V3 == 12 volts and
hence VOUT == - 6 volts. OV 90

The same output conditions are obtained if the input

voltages were both less than the bias.
-6 V
Case 3. Input voltages are out of phase and VIN (Pin 6)
is greater than the bias. Figure 4a. Phase Detector With No Saturation.

022 and 039 conduct 1 mA each, causing 035 to con- PHASE

OUTPUT
duct 1 mA. Therefore, V3 == 6 volts, V2 == 12 volts and VOLTAGE DIFFERENCE
hence VOUT == + 6 volts. (YOUT) ...
( )

The same output conditions are obtained if VIN (Pin 4) •

t- 180

':
were greater than the bias. I

------~ ~ ~ ~ ~!
+1 7 V
Figure 3 shows the output voltage wave form when the
input signals are 90° and 45° out of phase. OV

Notice that the duty cycle of the output waveform -1.7 V

changes as the phase difference of the input signals
I
change. For illustration purposes, square v.;aves are
shown as input signals, however, other periodic wave-
10 4-
forms would produce similar output waveforms. Figure 4b. Phase Detector With Saturation.

11-102
 AN·22
The output of the phase detector is connected to a low It is possible to obtain a tracking range close to 90° ±
pass filter which converts the square wave output to an 90° by connecting an external resistor network to the
approximate dc voltage. The relationship of this dc volt- phase detector output as shown in Figure 5. This cir-
age, VOUT, with respect to the input phase difference, cuitry limits the output swing to 10 ± 1 volt and pre-
¢, is shown graphically in Figure 4a. Assuming no satu- vents the internal circuitry from saturating at extreme
ration occurs in the internal circuitry, a PLL can lock on- phase conditions.
to an input signal with maximum difference of 180° to
0° with respect to the veo Signal. The phase comparator gain for the XR-210 is approxi-
mately given by:
Due to internal saturation of the output, the maximum
phase difference the XR-21 0 can track is approximately K¢ == 4.0 VOLTS (2)
50° or 90° ± 25°. This is because the output transistors RADIAN
of the phase detector saturate at approximately 8.3
volts and the maximum output voltage, VOUT, obtain- With the external bias network, it is approximately:
able is about ± 1.7 volts. Figure 4b shows the phase
detector characteristic of the XR-21 O. VOLTS
K¢ == (3)
RADIAN

-- --, I
1420
I

:l______ ~.____I
I
I
I
I I
a,
'"
CB :

EXTERNAL 1
J
BjAS

- -

ROUT ~ 2.0 Kn

Figure 5. External Resistor Bias Network.

I---VOUT--~

AO

Co
•
260 n AT

Figure 6. XR-210 Current Controlled Oscillator.

11-103
AN·22
CURRENT CONTROLLED OSCILLATOR (I CO) The change in timing current with RT is given by:

The functional diagram of the ICO is shown in Figure 6. LlIT == 0.17 mA (11)
The output frequency, fo, is directly proportional to the RT
total timing current, IT. seen by the ICO.
The free running frequency can now be given by:
(4)

Any change in output voltage of the phase comparator fo == 200 (1 + Q:..:!.Z HZ) (12)
Co RT
causes a change in fo as follows:
where RT is in KO and Co is in /1-F.
Ll VOUT
Llfoa--- (5)
RO The ICO gain is now:

where RO is the external resistor between Pins 11 and 211" (200 1 + Q:..:!.Z)
12. It will be shown in the following section how RO sets Llw 211"~ Co ~
the lock range of the PLL. K 0=-- =-== (13)
Ll VOUT RO IT RO IT
Combining equations 4 and 5 yields:
However, the timing current is now:

~=~ (6)
IT == (IX + o~~) mA = (1 + o~~) mA (14)
Ll VOUT RO IT

where IT is the total timing current with VOUT ::= 0 volt. Substituting this into the ICO equation yields:
In this case, IT = IX == 1 mA. Substituting this into
equation 6 yields the ICO conversion gain: KO == 200(211") = 1256 RADIANS/SEC (15)
Co RO RO Co VOLT
KO =~ == 211" fo RADIANS/SEC (7)
Ll VOUT RO VOLT and remains unchanged with the addition of RT.

where RO is in KO. Note: The discrepancy between the calculated and

measured KO can be attributed to tolerances of
The minimum value of RO should be approximately internal resistors and errors in approximating IX.
1.7 Krl. This is because the maximum current through
RO must be limited to 1 mA and since VOUT has a maxi-
mum range of approximately ± 1.7 volts, RO must be LOCK RANGE
limited to greater than 1.7 KO.
The lock range of a PLL, ± LlwL, is given by:
The free running frequency of the PLL is given by:
± LlwL = (Kif» (KO) (OE) RADIANS (16)
fo == -200 C0 . . F
IS In /1- . (8) SEC
Co
where OE is the maximum phase difference at the de-
Substituting this into ICO gain equation 7 yields: tector inputs in radians. 0E is approximately equal to
0.43 radians (25°).
KO == 1256 RADIANS/SEC (9)
RO Co VOLT Using measured values for Kif> and KO yields:

where RO is in KO and Co is in /1-F. ± LlwL == 1565 RADIANS (17)

RO Co SEC
Experimental data yields:
where RO is in KO and Co is in /1-F.
KO == ~ RADIANS/SEC (10)
RO Co VOLT
XR-215
The above equations were calculated without the ICO
tuning resistor, RT, connected to Pin 9. Adding RT in- The XR-215 PLL is basically the same as the XR-210.
creases the timing current and hence increases the The major difference is in the ICO section which is de-
free running frequency. fo: scribed below.

11-104
PHASE COMPARATOR
AN·22
With the ICO tuning resistor, RX, connected to Pin 10,
the ~ree running frequency is increased by a factor pro-
The phase comparator conversion gain is given by:
portional to the change in timing current:
Kif> == 3.6 VOLTS (18)
RADIAN .:If ex .:lIT == 0.7 (23)
RX
Saturation of the internal circuitry occurs limiting the
The ICO free running frequency is given by:
tracking range of the phase detector to about 90° ±
25°.
fo == 220 (1 + 0.7) (24)
An external resistor network shown in Figure 5 can in- Co RX
?rease the ~ange ~o about 90° ± 90°. The correspond-
where RX is in KO and Co is in p.F.
Ing conversion gain becomes:
KO == 1140 RADIANS/SEC (25)
Kif> == 1.3 VOLTS (19) RO Co VOLT
RADIAN
ICO and remains unchanged with the addition of RX'

The current controlled oscillator of the XR-215 is shown LOCK RANGE

in Figure 7. The ICO conversion gain is given by:
The lock range of the XR-215, ± .:lwL, is given by:
KO = 211" fo RADIANS/SEC (20)
RO IX VOLT
± .:lwL = (Kif» (KO) (BE) (26)

wh~re BE is approximately equal to 0.43 radians (25°).

Since IX = 1.1 rnA and fo = 220, USing measured values for Kif> and KO yields:
Co
± .:lwL == 1765 RADIANS (27)
KO == 1256 RADIANS/SEC (21) RO Co SEC
RO Co VOLT
where RO is in KO and Co is in p.F.
where RO is in KO and Co is in JLF.
Note: Using the external bias network (Figure 5) does
Experimental data yields: not change KO' To calculate the lock range with
this network, BE should be set to approximately
KO == 1140 RADIANS/SEC (22) 7r/2 radians (90°).
RO Co VOLT

J----VOUT

RO
r---------------------~------~12~--_V'~--~

Co 1 mA 1 mA
• I

.J..
Figura 7. XR·215 ICO.

11-105
AN·22
XR-S200 With Pins 15 and 16 open, fo is given by:

The XR-S200 PLL is basically the same as the XR-210 fo == 200 (Ix + 11 + 12) = 500 Hz (30)
and 215 except that many of the interconnections are Co Co
made external to the chip. These external connections
can aid in the flexibility of the chip. since IX == 1 mA, 11 == 0.5 mA, 12 == 1 mA.

PHASE COMPARATOR With Pins 15 and 16 tied high, fo is given by:

The phase comparator outputs are not tied internally to fo == 200 (IX) = 200 Hz (31)
the ICO as the XR-210 and 215. The measured phase Co Co
comparator gain is approximately:
where Co is in 1lF.
K¢ == 4 VOLTS (28)
RADIAN With Pins 15 and 16 open:

Saturation of the internal circuitry occurs limiting the KO = 211' fo ==~ (32)
tracking range to about 90° ± 25°. This range can be RO IT RO Co IT
increased by using the bias network shown in Figure 5.
where IT = IX + 11 + 12 == 2.5 mA, thus
ICO
KO == 1256 RADIANS/SEC (33)
The current controlled oscillator of the XR-S200 is RO Co VOLT
shown in Figure 8. The ICO gain is given by:
where RO is in KO and Co is in 1lF.
KO = 211' foRADIANS/SEC (29)
RO IT VOLT With Pins 15 and 16 tied high:

where IT is the timing current when VOUT = 0 volts. Ko==~ (34)

RO Co IT
The ICO free running frequency, fo, can be modified by
applying a digital pulse on Pins 15 and 16 through a di- where IT = IX == 1 mA. Thus
ode and a 1 KO resistor. By changing the voltage states
on these Pins, it is possible to obtain four discrete fre- KO == 1256 RADIANS/SEC (35)
quencies for fo. By connecting a resistor from either Pin RO Co VOLT
15 or 16 to ground, it is also possible to modify the cen-
ter frequency. and remains unchanged.

Co , mA , mA

I
Figure 8. XR-S200 ICO.

11-106
 AN·22
LAG FILTER LAG FILTER

I I
r r
1 1
F(8)=~ F(8) =1+ 2 71 S

WYJ =

8 = 1 8 = 1
2~ 2~

LAG-LEAD FILTER LAG-LEAD FILTER

LJ
1 + 72 8 1 + 72 8
F(8) = 1 + 8(271 + 72) F(8) = 1 + 8(T1 + 72)

8 = 1 /
2
-~
+ T2
2T1

FOR 71 > >

(72

T2
+ -..L)
KV
8 = 12 j KV
71 + 72

FOR 71 >.-, T2
(72 + 1)
KV
• I

8= ~ (1 +72KV) 8 = _ _1__ (1 + 72 KV)

2 2KV T1 2~

Figure 9. Low Pass Filters.

11-107
AN·22
Measured value for KO is approximately:

KO == 1262 RADIANS/SEC (36)

RO Co VOLT

LOCK RANGE
Using measured values for Kcp and KO yields: 20

±~"'L == 2170 RADIANS

RO Co SEC

where RO is in KO, and Co is in /!F.

(37)

/
V
LOW PASS FILTER
The low pass filter section for the XR-210/215/S200 is
formed by connecting an external capacitor or RC net-
work across the output of phase comparator section. /
V
Most common passive low pass filters are shown in 10 20 26
Figure 9. R1 is the internal resistor with nominal value
v~ (VOLTS)
of 6 KO. If an external bias network as shown in Figure
5 is used, R1 = 2 KO. Pin numbers shown in Figure 9
apply to the XR-210 and XR-215.
Figure 10. Maximum Input Voltage vs. Supply Voltage.
The term KV shown in the filters is the total forward gain
of the PLL and is equal to the product of Kcp and KO'
however, by adjusting T, the damping factor as well as
CAPTURE RANGE the capture range is changed. These two parameters
can be individually controlled in a lag-lead filter.
The capture or acquisition range of the PLL, ± ~"'C,
can be approximated as: General systems and control theory indicates that for
maximum stability the damping factor, 0, must be
± ~"'C == ± ~"'L IFO ~"'C) I (38) greater than 0.7. In many FSK demodulation circuits
using Exar PLLs, it was found that with 0 as low as 0.2,
where IFO ~"'C) I is the magnitude of the low pass filter the circuit functions properly at high baud rates.
evaluated at '" = ~"'C, Since IF(j ~"'C) I is always less
than unity, the capture range is always smaller than the DESIGN EXAMPLE
lock range.
Design an FSK demodulator using the XR-210 with the
There is no explicit relationship for calculating ~"'C, following specifications:
however for a simple lag filter, it can be expressed as:
Mark frequency: 1070 Hz
± ~"'C == [KV RADIANS (39) Space frequency: 1270 Hz
~-;j' SEC VCc: + 12 volts

For lag-lead filters, capture range can be roughly esti- 1. fa = 1170 Hz

mated by "'7'/' (See Figure 9.) Actual data indicates that
capture range is larger than "'7'/ and approaches the Co = 200 == 0.2 /!F
lock range. fa

DAMPING FACTOR Adjust RT (Pin 9 to GND) for correct fa.

The advantage of using a lag-lead filter is that generally 2. ~"'L = 211" (~fL) = 211" (200 Hz) = 1256 RAD/SEC
speaking, it gives better stability due to the extra zero.
The damping factor can be adjusted without necessar- RO = ~ = 6.23 KO
ily changing the capture range. With a simple lag filter, ~"'L Co

11-108
3. Set capture range, AwC, equal to AWL. Using a lag- 4. The damping factor is given by:
AN·22
lead filter, AwC can be approximated by:
o= 1 1 (1 + 72 KV) = 0.22
2.../2 KV 71

Even with critical damping (0 < 1.0), the XR-210

functions properly as an FSK demodulator with baud
KV = KOK~ =2921 rate of 300 BPS.

5. For V + of 12 volts, the input voltage should be lim-

ited to 5 volts PK-PK to avoid internal saturation (see
Let R2 = 50 n. Thus 71 » 72 Figure 10).

6. Schematic for the above example is shown in

C1 = 0.15 JtF Figure 11.

12 V

I
5K o.1~F

_ R2
10 K
5K

16 12 V

2K

5K
4K

4 K
DATA OUT

01 "F
15

Co = 0.2 JLF
RO = 6.23 KO
J"'"' 3K

FSK IN

C1 = 0.15 JLF 14 11
10 K
R2 = 50 n
RT = 10 KO RT
Co RO

Figure 11. XR-210 FSK Demodulation.

11-109
AN·22
Table 1. Summary of PLL Parameters (1)

PARAMETER XR-210 XR-215 XR-S200

Phase Comparator 4.0 VOLTS 3.6 VOLTS 4.0 VOLTS

Kcp RADIAN RADIAN RADIAN

VCO KO 910 RAD/SEC 1140 RAD/SEC 1262 RAD/SEC

- -
RO Co VOLT RO Co VOLT RO Co VOLT

Lock Range ± .1wL 1565 RADIANS 1765 RADIANS 2170 RADIANS

- -
RO Co SEC RO Co SEC RO Co SEC

F~2c Running 200 (1 + 0.17) Hz 200 (1 + 0.7) Hz 500 Hz (2)

Frequency fo Co RT Co RT Co

Capture Range ± .1wC

(Simple Lag) (3)
~KOK<I> ~KO K<I> ~KOK<I>
T1 T1 T1

Damping Factor 0
(Simple Lag) 1~
2KO Kcp T1
1~
2KO Kcp T1
1~
2KO Kcp T1

(1) RO. RT. RX in KO

Co in JLF
(2) fo shown for Pins 15 and 16 open
(3) For other filter configurations, refer to the filter section. T1 = R1 C1.

11-110
 VA7.4P
LJYA
e v,,;n R
~1 AN-23

High-Performance Frequency-To-Voltage
Converter using the XR-2211

'~
INTRODUCTION
f\j' tiN
'O~'O
A stable highly linear f/v converter can be easily de- o CARRIER
DETECT
signed using the XR-2211 phase locked loop. The flv
can be used for a dynamic range from ± 1 % to ±80%
over a frequency range of .01 Hz to 1 MHz. Figure 1. F/V Block Diagram.

The block diagram of the flv is shown in Figure 1. The Vo

circuit will perform flv conversion according to the rela-
tionship

2 VREF X INTERCEPT = K2
SLOPE = K,

where K1 and K2 are set by the designer.

VREF
The transfer function relating Va to fiN is shown in Fig-
ure 2. The carrier detect output, Q, (Pin 5) which goes
high over the tracking range is shown in Figure 3. K2

The basic circuit diagram is shown in Figure 4. The IL 10 IH liN

slope K1 is determined by the relationship Figure 2. F/V Transfer Function.

K1 = _-_1_ a
VR COR1

where VR = VCC /2 - VBE

The x intercept or upper frequency, K2 is determined by

the relationship

Vee

DESIGN EXAMPLE liN

Figure 3. F/V Carrier Detect Output.

Design a flv converter for the frequency range 100 Hz
to 600 Hz.
18 - 1.3
resolution::::; VCC - VBE - 33.4
- -mV-
The first step is to calculate the center frequency fo, fH - fL 600 - 100 Hz
(Figure 2) in
forVCC=18V
fo = fL + fH = 100 + 600 = 350 Hz We can now calculate VREF
2 2
Supply voltage is directly proportional to the degree of VREF = VCC/2 - VBE = 9 V - .65 V = 8.35 V
resolution obtainable.
The center frequency is given by
In order to obtain a greater resolution a higher supply
voltage is used. For this design an 18 V supply is used fo = _1_
giving us a resolution of approximately ROCO

11-111
AN·23
l' t 1.
Vo

o----j

Figure 4. F/V Circuit Diagram.

choosing RO = 20 K and rearranging and a cut-off frequency

1 1 fC = _ 1 _
Co = ROFO = (20 KO) (350 Hz) 2",RFCF

= .143",F Selecting RF = 100, K, CF is then given by

C ==_3_ F
Since
RO = (fH - fL> F .::If/.::lt '"
R1 2 fo
where ~ = maximum expected rate of
2 (350 Hz) (20K) .::It change of input frequency
(600 - 100) Hz
for ~ = 300 cycles/sec
= 28 K .::It

CF = ~ ",F = .01 ",F

The selection of C1, the loop filter capacitor has a de- 300
gree of flexibility in its value. For a damping coefficient
of .5. giving T = 1 ",secs FC = 160 Hz

A carrier detect output is available at Pins 5 and 6 (Q

C1 == Co = .143 ",F = .035 ",F
and Q). The components CD and RD comprise the lock-
4 4
detect filter. For RD = 470 K, and a capture range ap-
It should be noted that an increased value of C1 will in- proaching the lock range, a minimum value of CD is
crease response time but reduce ripple, while a de- given by
creased value of C1 will reduce response time, in-
crease capture range, but increase ripple. CD(",F) ~ _1_6- = J.§.. = .032 ",F
fH - fL 500
The slope K1 can now be calculated RD = 470 K

K1 = _ _1_ = 1 TEMPERATURE STABILITY

VRCOR1 (8.35) (.143 ",F) (28 K)
The XR-2211 is characterized by excellent temperature
= 29.91 Hz stability, in the order of 50 ppm/oC. The output voltage
V temperature coefficient can be calculated by

and since K2 = fMAX = 600 Hz -V = -1 x ---'-'--

50 oom x ('IH - ,IL)
°C K1 °C
The transfer function is then given by
substituting
fiN = -29.91 Vo + 600
= 33.4 mV x 50 ppm x (600 - 100) Hz
The filter RF CF forms a one-pole post detection filter, Hz
with a time constant
.8 mV
°C

11-112
 AN-24

Digitally Programmable Phase-Locked Loop

INTRODUCTION CIRCUIT DESIGN
Most phase-locked loops require manual potentiometer Figure 2 shows the XR-215 internal blocks and neces-
adjustment if the center frequency of the circuit is criti- sary external components. The VCO center frequency,
cal. Also, once adjusted, if ambient temperature fo, is calculated by the formula:
changes cause the PLL's VCO or center frequency to
shift, the potentiometer would have to be readjusted if f = 200 (1 + 0.6) Co .in JLF (1)
the accurate center frequency was to be maintained. o Co RX RX In KO
Readjustments are, of course, an impractical solution.
In this application it is desirable to have a variable cur-
This application note describes the design of a digitally rent drawn from Pin 10, and RX omitted. Equation 1 is
programmable PLL. Being digitally controlled, a micro- then modified to equation 2 is a current instead of a re-
processor or other digital circuitry could easily tune or sistor is used at Pin 10.
retune the VCO when necessary. The design uses the
XR-215 monolithic PLL together with the XR-9201 D/A f = 200 (1 + I ) Co in JLF (2)
converter, which provides the tuning function. o Co PIN 10 IplN 10 in mA

PRINCIPLES OF OPERATION Equation 2 can now be used to determine IplN 10 for a

given fo adjustment range. Once the center frequency
Figure 1 shows the block diagram of the digitally pro- has been set, RO can be calculated to adjust the track-
grammable PLL. The circuit is comprised of two blocks: ing range using the relationship:
the PLL and the D/A converter. The PLL is used for FM
demodulation, synchronizing signals, or frequency syn- ±t:.WL = 211't:.fL = 1565 rad RO in KO (3)
thesis. It processes these Signals, which are centered ROCO sec Co in JLF
around its free-running frequency, fo . This fo is set by
the internal voltage-controlled oscillator, VCO, in the or RO = 1565 RO in KO, Co in JLF (4)
PLL. The VCO within the XR-215 is really a current- 211't:.fLCO
controlled oscillator, ICO. This is, the frequency of oscil-
lation of the ICO is directly proportional to the timing Now with RO calculated for t:.fL, the capture range, t:.fC
current, IT- IT is made up of two components: an inter- is set using the loop time constant capacitors C1:
nal fixed current and an externally programmable cur-
rent, IplN 10. This IplN 10 control current is provided by
a D/A converter with a current output. Since the D/A ± t:.WC = ~KoKcf>
71
= 211't:.FC (5)
provides an output current that is directly set by an in-
put digital code, this code will actually control the cen- 71 = Loop Time Constant
ter frequency of the PLL's ICO, fo . Ko = VCO Conversion Gain
K<t> = Phase Detector Conversion Gain
XR·215

Substituting the values for KoK<t> and solving for FC:

t:.FC = ....!..- 0.684 (6)

•
211' ROCOC1
'0 cr-j.-.4----< or 0.017 R in KO, C in F (7)
t:.fC2ROCO 0 0 JL

The resistors RI and RF are used to set the gain of the

op amp when used for FM demodulation. Cc is op amp
compensation and is in the range of 300 pF for unity
gain to 50 pF for a gain of 10 and up. The resistors go-
ing to Pins 4, 5, and 6 are used to dc-bias the phase de-
tector inputs at half supply, with their actual value not
DATA INPUT
critical. The capacitors C2 and C1 are used for capaci-
Figure 1. Programmable PLL Block Diagram. tive coupling.

11-113
AN·24
~----------------~--~Vcc

AI
SK

Vcc
PHASE
DETECTOA

2K

SK

,oO----+--------~

Ax

Figure 2. XR-215 with External Components.

DATA INPUT
17-------------10

10

10

Figure 3. XR-9201 D/A with External Components.

Figure 3 shows the D/A converter internal blocks with Also: 10 + TO = IFS = Full-scale Current (9)
external circuitry. Data is fed into the input latches,
which will allow data to flow through to the current
switches when CE is high and hold data when CE is low. IFS = 2 IREF (255) (10)
.256.
The output currents are related to the digital inputs by:
The full-scale current is set using R by the relationship:
B7 B6 B5 B4 B3 B2 B1 BO]
10=21REF [ -+-+-+-+-+-+-+- (8)
2 4 8 16 32 64 128 256
R = VREF VREF =2 V (11 )
where BN = 1 if bit N is high IREF
BN = a if bit N is low
B7 = MSB The 10 KG potentiometer from Pin 3 to ground is used
BO = LSB to fine-adjust the internal reference to exactly 2.00 V.

11-114
 AN·25

Full-Duplex 1200 BPS/300 BPS

Modem System
ceived signal range can vary from about 0 dBm to
INTRODUCTION -45 dBm.
This application note describes the construction of a DEMUX. Demultiplexer to switch transmitted carrier
full-duplex modem system which operates at either (Txc) and received data (Rxd) between 300 BPS and
1200 BPS with phase shift keying encoding (PSK) 1200 BPS.
or 300 BPS with frequency shift keying (FSK). The
1200 BPS is in a synchronous format or 300 BPS asyn- AUTO SPEED SELECT. Automatically senses whether
chronous. 300 BPS or 1200 BPS information is being received
and controls the demux with this information.
This system is not intended to be directly connected to
the telephone network as this requires FCC approval. SLICER. A voltage comparator used to convert ana-
log receive carriers (Rxcar) into digital signals suit-
PRINCIPLES OF OPERATION able for the XR-2123 and XR-14412 Rxcar inputs.
The heart of this system is three LSI integrated circuits. CARRIER DETECT (CD). A level sensor with a digital
The XR-2120 is a switched-capacitor filter (SCF) to output to indicate when a Rxcar is present.
provide precise bandpass filtering at 1200 Hz and
2400 Hz. The XR-2123 performs the 1200 BPS PSK TIMING CIRCUIT. This circuit extracts a 600 Hz re-
modulation/demodulation and the XR-14412 the 300 BPS ceive signal timing from the Rxcar for synchroniza-
FSK modulation/demodulation. These three devices are tion purposes in the XR-2123.
shown with the necessary external functions to perform
a 212A type synchronous modem in Figure 1. These SCRAMBLER/DESCRAMBLER. These sections scram-
other functions are described as follows: ble the data to be transmitted (Txd) while descram-
bling the received data (Rxd).
LINE INTERFACE. Provide DC isolation between mo-
dem and telephone network. This section, known as DELAY CIRCUIT. To provide a delay between the re-
a direct-access arrangement, must be approved by quest to send (RTS) data and clear to send (CTS) da-
the FCC for direct connection to the telephone net- ta commands.
work.
Figure 2 shows the complete circuit implementation of
AGC. Automatic gain control to provide a constant modem, with Table 1 listing the recommended circuit
signal level to other portions of the circuit. Its re- values.

j
r!.'HON<
~
•
Figure 1. 212A Type Modem System.
11-115
 CLOCK GENERATOR

I
......
m

»
CtS
TIMING
CIRCUIT
.' ~ )GNO 21' Isl13

AUTO SPEED SELECT

z
•
I\)
Figure 2. XR-212A Type Modem. en
DESIGN EXAMPLE
AN·25
Design a digitally programmable PLL with a center fre- 4. C1 is determined by equation 7:
quency, fa, equal to 20 kHz. Provide for a 10% digital
tuning range. The circuit shall also have the following
lock and capture ranges:
C = 0.017 = 0.022 F
1 (4 K)2 (5) (0.01) /-L

±AfL = 5 kHz, ±AfC = 4 kHz 5. The D/A components can now by specified, first us-
1. Using equation 2, first with IplN 10 = 0 (digital in- ing equation 10 and the previously calculated IplN
puts all zeros) Co can be determined. 10 maximum current:

fa = 200 IplN 10 max == IFS 2 IREF(255)

Co 256

2. This same equation is used to determine the maxi- IREF = 50 JlA

mum value of IplN 10 for a 10% change in fo. Rear-
ranging equation 2 yields: 6. The reference current setting resistor, R. is now de-
termined using equation 11:
toCo 22 K (0.01) -1 == 0.1 mA
IplN 10 = ---1
(max) 200 200

fa = 20 K + 2 K Adjustment Range
7. Calibration of the system is accomplished by adjust-
3. RO is now calculated from equation 4: ing potentiometer R3 for VREF on the XR-9201 to ex-
actly 2.00 V.
R = 1565 = 5 KO
o (271") (5 K) (0.01) Figure 4 shows the completed design example.

O,022IJ. F1
0.1 ~,F

'i ~I--+----,
2K

PHASE
DETECTOR
2K

O.1IJ F

0.1 ~F 5K XR·215

'Oo--+--+---+---+--<
VCO
OUTPUT

GNO
10K
10

•
j'P'N 10 DATA INPUT CE .5 V -7 V

XR.9201 ,vce 1-"'8'--_--+

-VEE t-:----t----;

'OK

Figure 4. Digitally Programmable PLL.

11-117
AN·25
A. XR-4 7 41 Quad Op Amp R1 2.2K R2 2.2K R3 2.2K
B. XR-4741 Quad Op Amp R4 2.2K R5 1.2K R6 1M
C. XR-1458 Dual Op Amp R7 10K R8 10K R9 1M
D. LM-339 Quad Comparator R10 10K R11 1K R12 62K
E. XR-14412 FSK Mod/Demod 300 BPS R13 100K R14 47K R15 62K
F. XR-2120 Filter-Switched Cap R16 10K R17 100K R18 470K
G. XR-2123 PSK Mod/Demod 1200 BPS R19 100K R20 10K R21 10K
H. CD-4049 Hex Inverter R22 62K R23 47K R24 100K
I. CD-4016 Quad B1-Lateral Switch R25 18K R26 62K R27 1K
J. CD-4030 Quad Exclusive-OR Gate R28 4.7K R29 10K R30 1M
K. CD-4013 Dual 0 Flip-Flop R31 120K R32 10K R33 1K
L. CD-4013 Dual 0 Flip-Flop R34 68K R35 600 R36 300
M. Dual 4 Bit Static Register 4015 R37 600 R38 10K R39 10K
N. Dual 4 Bit Static Register 4015 R40 10K R41 10K R42 10K
O. Dual 4 Bit Static Register 4015 R43 39K* R44 180K* R45 392*
P. Dual 4 Bit Static Register 4015 R46 39K* R47 180K* R48 392*
Q. MM7404 Hex Inverter R49 39K* R50 464* R51 180K*
R. DM74193 Synchronous Up/Down Counter R52 13K R53 71.5K R54 10K
S. XR-1488 Quad Line Driver R55 10K R56 10K R57 10K
T. XR-1489 Quad Line Receiver R58 10K R59 1M R60 10K
U. XR-4194 Dual Tracking Regulator R61 10K

All resistor values are in ohms.

* = > 1 % tolerance.

Crystals
CR1 - 4.032 MHz MTRON
C1 82 pF C14 1 /-tF CR2 - 1,000 MHz FOX
C2 .033/-tF C15 .1/-tF CR3 - 4.608 MHz X-TRON
C3 .022/-tF C16 .001 /-tF
C4 .1 /-tF C17 .001 J.tF Transformer
C5 .033 J.tF C18 4.7 J.tF T1 - T2220 M ICROTRAN
C6 .033 J.tF C19 2.2 J.tF
C7 .033 J.tF C20 4.7 J.tF Transistors
Cs .033 J.tF C21 4.7 J.tF Q1 - A854 ROHM
Cg .033 J.tF C22 .1 J.tF Q3 - C1741 ROHM
ClO .033/-tF C23 .1 /-tF Q4 - C1741 ROHM
C11 .1 J.tF C24 4.7 J.tF
C12 0.22/-tF C25 4.7 J.tF FETs
C13 4.7/-tF C26 4.7/-t F Q2 - 2N4861

Component List for 212A Type Modem System

11-118
 AN·26

High-Speed FSK Modem Design

INTRODUCTION DESIGN EQUATIONS - Refer to Figure 6
As the need for transmitting data increases, some ap- 1. The frequency of oscillation of the XR-2206 when
plications require data to be sent faster than the con- used as a modulator, with the FSK input (Pin 9) is
ventional telephone line modems. This application note high is:
describes the design and construction of a high speed
full-duplex, FSK modem using XR-2206 as a modulator
and XR-210 as the demodulator transmitting data at the R7A + R7B C3
rate of 100 Kilobaud.
When the FSK input (Pin 9) is low the frequency
PRINCIPLES OF OPERATION equals

The block diagram in Figure 1 describes the basic

building block in any FSK modem system. The major R8A + R8B C3
difference is that in high speed applications, data is
transmitted over a twisted pair wire or coaxial cable in- 2. The filter best suited for modem applications is the
stead of the telephone line with its limited bandwidth. butterworth filter due to its linear phase response
The complete system is comprised of an answer and within the passband. Table 1 shows the normalized
originate modem. Simply stated, the modulator con- capacitor values for butterworth filters up to fifth or-
verts the input data to two discrete frequencies corre- der.
sponding to its 1's and O's and is then sent over a line or Table 1
cable. The line hybrid steers these frequencies to the
bandpass filter, where it will remove any unwanted sig- ORDER NO. C1 C2 C3
nals that might have gotten through due to the line or
cable before reaching the demodulator. The demodulat-
2 1.414 .7071
or, which is a phase locked loop, will lock onto the in-
3 3.546 1.392 .2024
coming frequencies and produce 1's and O's on its out- 4 1.082 .9241
put. A detailed description on FSK techniques is given
2.613 .3825
in the EXAR MODEM DESIGN HANDBOOK.
5 1.753 1.354 .4214
3.235 .3090

ORIGINATE ANSWER

DATA Pll BANDPASS BANDPASS PlL DATA

RECEIVED DEMODULATOR FIL TER FIL TER DEMODULATOR RECEIVED

•
560/640KHZ 160/240KHZ

160/240KHZ 560/640KHZ

DATA DATA
SINEWAVE LINE LINE SINEWAVE
TO BE TO BE
MODULATOR HYBRID HYBRID MODULATOR
SENT SENT

TWISTED
PAIR WIRE OR
COAXIAL CABLE

Figure 1. Block Diagram of High Speed FSK Modem System

11-119
AN·26
Figure 3 shows a third order active high pass filter. To The equations for using the XR-21 0 as an FSK demodu-
solve for the actual resistor values we use the formula: lator are as follows:

R=---
Wc CN C ilF = Fmark - Fspace

Where CN is the normalized capacitor and Wc = 271'Fc. ilFL = 2(F mar k - Fspace)
In this equation, make all capacitors equal.
Fmark + Fspace
FO =
2

Co is in ""f
FO = -234 ( 1 .1)
+-
Co RT RT is in KO

234
Co =
FO

Figure 3. ilW
c
=J ilWL
6KC1
After calculating Rx remember for single supply opera-
tion the op amp must be biased at 1/2 VCC; therefore
take twice the calculated value for Rx and configure as
shown in Figure 4. ilWL
C1 =
6KilWc2
+V

2(1565)
RO = RO is in KO
ilWLCO

10- 4
C18 =
271' (Baud Rate)

10- 4
Figure 4. C19 =
371' (Baud Rate)

Figure 5 shows a third order active butterworth low DESIGN EXAMPLE

pass filter. To convert from the normalized capacitor
values to the actual capacitor values, we use the for- Design a FSK Demodulator with the following specifica-
mula: tion:

FO = 200 kHz

ilFL = 160 kHz

Where eN is the normalized capacitor value and Wc = Baud Rate = 100 Kilobaud
271'Fc. In this equation, make all resistors equal.
In this example, we must know the mark and space fre-
c,o = 3.546 quencies. If Fmark = 160 kHz and Fspace = 240 kHz,

"; [~;t> I
the free running frequency is equal to

Fmark + Fspace
2
Rl1

o .. I = 200 kHz
Cg ~ '.394 I c" = .2024 In order to calculate the free running frequency, we use
1 the formula:
FO = 234
Figure 5. Co

11-120
In this example we will use a variable resistor (RT) in or-
AN·26
For the filter, 18 dB of attenuation should be sufficient;
der to fine tune FO to exactly 200 kHz, therefore: therefore:

Design a third order high pass butterworth filter with fc

F0- -234
- (1 +.1)
- = 100 kHz.
Co RT
1) In order to solve for actual resistor values use Table
1 and set all capacitors equal.. The design example
The lock range (.::lFd is equal to twice the difference of
is shown below:
the mark and space frequencies, so

.::lFL = 2(Fspace - Fmark)

RO, which sets the lock range equals:

R _ 2(1565) .::lWL = 211'FL

o - .::lWLCO 6.28 (160x 103)
= 1004800

2(1565)
Where Co is in ",f
1004800.0015 and RO is in KO R== _ _1_
WeCN C
= 2.0 KO

R15 == 1 == 4500
The Capture Range (..:1Fd is equal to: (6.28 x 100x 103)3.546(1000x 10- 12)

r;;NL .::lWc = 211'.::lFc

.::lW
c -vGKW
-
.::lWL = 211'.::lFL
R14 == 1
(6.28 x 100 x 10 3)1.392(1000 x 10- 12)
== 1.1KO

1
In order to solve for C17 we rearrange the equation to Rx = 7.8KO
read. (6.28 x 100 x 10 3).2024(1000 x 10- 12)

After calculating Rx take twice the value and confi-

.::lWL
C17 = gure as shown below:
(6K) Wc 2
+v
1004800 = 300 x 10- 12
(6K) 753600 2
R16 = 15.6K
therefore: Rx

.::lW
c -
-J 1004800
(6 x 103) 300 x 10- 12
{
R'7 - 15.6K

= 118.97 kHz Design a third order lowpass butterworth filter with Fe

= 300 kHz.
It is important to note C17 and 6K set the loop time con-
stant. When used as an FSK Demodulator, the XR-210
has post detection filtering on the output of the phase
detector. In order· to calculate the values for C18 and
C19 we use the relationships:
2) In order to solve the actual capacitances, use Table
1 and set all resistors equal. The design example is
shown below:
II
C18 = _ _1_0_-_ 4 __
271' (Baud Rate)
10- 4
160 x 10 - 12 or 160 pf
6.28 (100x 103)

C19 = 10-
4
106x 10- 12 or 106 pf
Cg = 73apl I
9.42 (100 x 103)

11-121
AN·26
Design an FSK modulator with Fmark = 560 kHz and
Fspace = 640 kHz. The frequency of oscillation with
the FSK input (Pin 9) is high is equal to:

C = 3.546 = 1880 f
21r(300x10 3)1x10 3 P Fmark = -R7A
-- ---
+ R7B C3
C10 = __3_.5_4_6_ 1880 pf
1884000000 - - - - - - = 560 x 103 or 560 kHz
1K + 785!1.0011"f
C9 = __1_.3_9_2_ 738 pf When FSK input (Pin 9) is low the frequency is equal to:
1884000000

.2024 Fspace = R8A + R8B C3

C11 107 pf
1884000000

- - - - - - = 640 x 103 or 640 kHz

1K + 5620.0011"f

""

12
I I I
':' ':" ':"

TO
TWISTED 'AIA WIRE OR
~AL.C::::'.::.:.LE _ _~.......:.
lHOOJ3
INATIONAL.I

Figure 6. Complete Schematic for 100 Kilobaud FSK Modem

11-122
......
...... RX DATA
...... GRND
I\)
(,J
+12V
TX DATA

l>
z•
I\)
Figure 7. P.C. Board layout for 100 Kilobaud FSK Modem-Component Side
0)
AN·26
PART NO. ANSWER ORIGINATE PART NO. ANSWER ORIGINATE

R1-R2 5.1K 5.1K C1 47 ILf 47 ILf

R3 50KO Pot 50KO Pot C2 4.7 ILf 4.7 ILf
R4 2000 2000 C3 .001 ILf .001 ILf
R5 510 510 C4 4.7 ILf 4.7 ILf
R6-R7 1000 1000 C5-C6 .1 ILf .1 ILf
*R8 750 750 C7 4.7 ILf 4.7 ILf
R9-R10 10 KO 10 KO C8 1 ILf 1 ILf
R11-R13 1 KO 1 KO C9 738 pf 317 pf
R14 1.1 KO 2280 C10 1800 pf 807 pf
R15 4500 900 C11 107 pf 46 pf
R16-R17 16 KO 3 KO C12-C14 1000 pf 1000 pf
R18-R19 5 KO 5 KO C15 .22 ILf .22 ILf
R20 2 KO 2 KO C16 1 ILf 1 ILf
R21 4 KO 4 KO C17 300 pf 300 pf
R22 10 KO 10 KO C18 150 pf 150 pf
R23 5 KO 5 KO C19 106 pf 106 pf
R24 249 KO 249 KO C20 10 pf 10 pf
R25 4 KO 4 KO C21 .1 ILf .1 ILf
R26 3 KO 3 KO C22-C25 4.7 ILf 4.7 ILf
R27 10 KO 10 KO Q1 2N2222A 2N2222A
R28 5 KO 5 KO T1 PE-5760** PE-5760**
R29 5620 5620 Z1 1N5232 1N5232
R30 1.3 KO 1.3 KO IC 1 XR-2206 XR-2206
RO 2.4 KO 7.4 KO IC 2 LH0033t LH0033t
RT2 1 KO Pot 1 KO Pot IC 3 XR-5532 XR-5532
R7A 1.4 KO 5620 IC 4 XR-5533 XR-5533
R7B 1 KO Pot 1 KO Pot IC 5 XR-210 XR-210
R8A 7500 3.3 KO *1500
R8S 1 KO Pot 1 KO Pot J1-J2 JUMPER JUMPER
RT1 500 1000 WIRE WIRE

*Twisted Pair Wire

* * Pulse Engineering
tNational

Figure 8. Component List for 100 Kilobaud FSIC Modem

11-124
 AN-27

High-Frequency TTL Compatible Output

from the XR-215 Monolithic PLL Circuit
INTRODUCTION
With digital circuitry as common as it is, it is necessary approximately 3 volts. The veo output is ac coupled in
to be able to interface analog signals to digital systems. order to block this dc level. The input signal causes 01
This can be done by using the XR-215, a monolithic PLL to be overdriven, where the amplitude is 400 mVpp of-
circuit, and an additional buffer circuit. fsetted at approximately 0.769 Vdc. When 01 is in the
offstate, the collector voltage will be forced high and
When an input signal is present within the capture when this voltage exceeds 0.7 Vdc, 02 will turn on and
range of the PLL system, the XR-215 will lock on the in- the collector of 01 will be clamped at 0.7 Vdc. The out-
put signal and the veo section of the PLL will synchro- put of the veo at the TIL buffered output will be in
nize with the input frequency. The veo output can then phase.
be buffered in order to produce a TIL compatible out-
put.
PHASE VCO
COMPARATOR RANGE TIMING
PRINCIPLES OF OPERATION +VCC OUTPUTS SELECT CAPACITOR

Figure 1 shows a functional block diagram of the XR-

215 monolithic PLL system. The circuit contains a
phase comparator, a voltage controlled oscillator (VeO),
and an operational amplifier. A complete phase locked COMPARATOR 6
loop system can be made by simple ac coupling the INPUTS INPUT
veo output to either of the phase comparator inputs, PHASE ,--_+-11-0 ~~~T~~'~
COMPARATOR 0-"-1-----'
and by adding a low pass filter to the phase comparator BIAS
outputs.

The veo output can be buffered in order to produce a

TIL compatible output at high frequencies by the sim- -VEE OP AMP OP AMP
INPlJT OUTPUT
ple common emitter circuit shown in Figure 2. The am- OP AMP
COMPENSATION
plitude of veo degrades as frequency increases and at
21 MHz, the amplitude is reduced from approximately
2.5 Vpp to 400 mVpp. The dc output level is 2 volts be- Figure 1. Functional Block Diagram of XR·215 Monolithic PLL
low Vee so with Vee equal to ± 5 volts, the dc level is Circuit.

TTL BUFFERED
OUTPUT
I

FROM PIN .::-15

OF XR-215
II
I

Q1 - Q2~2 N2369

Figure 2. Common Emitter Buffer Circuit.

11-125
AN·27

VCO OUTPUT (PIN 15)

OF XR-215

TTL BUFFERED OUTPUT

AT 21 MHz MEASURED
WITH X100 PROBE.

PROPAGATION DELAY IS
APPROXIMATELY 5 ns

11-126
HIGH FREQUENCY SYNTHESIS
AN·27
An application where a high frequency TIL compatible system is synchronized to an input signal at frequency
output would be useful is in high frequency synthesis, fs, the veo output (pin 15) is at frequency Nfs, where N
as shown in Figure 3. The output of the buffer, which is the divider modulus. This is useful because a large
can produce a high frequency TIL compatible output, number of discrete frequencies can be synthesized
is divided down the divider modulus N. When the entire from a given reference frequency.

CB
+5V
II I
C1 C1
~

Cc
INPUT
f = fs
0
I
1 KSl 4
8
5

1 KSl XR-215
6

15 VCO OUTPUT
fo = Nfs

CC

-5V

+5V +5 V ~J-----'-'-----.
5 1 KSl

fo =N
11
SN7493 .;- N
BINARY COUNTER
14
II
I

2 12

01 - 02 2N2369

Figure 3. High Frequency Synthesis Circuit.

11-127
 AN·28

XR·212AS Modem System

INTRODUCTION XR-2120 PSK Modem Filter: This is a switched
capacitor type filter for providing precise filtering and
This application note describes a four-chip modem set equalization for both 300 BPS FSK and 1200 BPS PSK
designed to perform the complete Bell 212A type mo- carrier signals.
dem function. Described arelthe functions of each de-
vice, the connection of the four together, and testing XR·2121 • PSK/FSK Modulator: Complete modulation
procedures with performance data. functions are performed by this device for both 300
BPS FSK and 1200 BPS PSK.
PRINCIPLES OF OPERATION
XR·2122· PSK/FSK Demodulator: Demodulation of FSK or
The basic characteristics of the 212A type modem are PSK encoded carriers is performed by the XR-2122.
listed in Figure 1. As seen, this type of system is basi-
cally a dual modem. It can communicate with either XR·2125 • Data Buffer: Performs asynchronous to syn-
low speed FSK modems (Bell 100 Series) or at 1200 chronous and synchronous to asynchronous conver-
BPS to PSK modems. sion.

Figure 2 illustrates the major components of most mo- MAJOR 212A TECHNICAL SPECIFICATIONS
dem systems. The four sections are:
DATA RATES:
1. Modem Signal Processor (MSP): This is the heart of Low Speed Mode:
the modem. It contains the modulator, demodulat- 0-300 BPS Asynchronous Format
or, and filtering functions. High Speed Mode:
1200 BPS Character-Asynchronous Format
2. Data Coupler: This section in the 212A is a direct ac- 1200 BPS Synchronous Format
cess arraignment (DM). This type is directly con-
nected to the switched telephone network. The ENCODING FORMATS:
DM serves to protect the phone network from Low Speed Mode:
modem and vice versa. FSK (Frequency Shift Keying)
High Speed Mode:
3. UART: Performs serial to parallel conversion and PSK (Phase Shift Keying)
timing functions.
OPERATING MODE:
4. Handshaking Controls: Timing functions for signals Full-Duplex at all Speeds
such as clear to send (CTS) and request to send
(RTS). LINE REQUIREMENT:
Two-Wire Switched Network
The XR-212A consists of the following four devices
which perform the complete MSP function. Figure 1. Major 212A Technical Specifications

I
TERMINAL : I UART I
MODEM
SIGNAL I
OR CPU
I I I PROCESSOR I
I DATA
I TELEPHONE
I COUPLER -' OR LEASED
I
I (OAA)
i LINE

I HANDSHAKING
I
I CONTROLS
(RS·232)
I
I I
Figure 2. Modem Architecture

11-128
 AN·28
COMPLETE SYSTEM
Figure 3 is a simplified schematic intended to illustrate formance over other line conditions which may occur in
the complexity of the system. an actual telephone link. The last piece in the test set-up
is the line impairment simulator which can add impair-
Figure 5 illustrates the complete schematic diagram of ments to the carrier signal which may exsist in the
the XR-212AS. telephone channel. These impairments include noise and
frequency offset.
A performance test set-up is illustrated in Figure 4 The
data error analyzers send a known data pattern and The major specification often used to judge a modem's
analyze whether this data was correctly received and quality is its bit error rate (BER) as a function of inter-
demodulated. These analyzers give a quantitative fering noise or signal to noise ratio (SIN).
number for errors received. On the line side of the
modems there is a line simulator to introduce amplitude Figures 6, 7, and 8 illustrate the typical BER vs. SIN
and group delay characteristics to the transmission performance for the XR-212AS operating at 1200 BPS
channel as in an actual phone line. Most testing would for the three different line conditions. The data taken
include performance data for three different lines, C2 - for these figures is under the following conditions:
nominal or normal line, CO (3002) - worst case line, and
back-to-back - no line. The XR-212AS is optimized for RXC = -40 dBM
C2 line conditions (fixed compromise equalization in TXC = -10 dBM
the XR-2120, however, it is important to know per- 511 Random Data Pattern

XR·2121 MODULATOR
CAR

ADJ
COMP 10K
XR·2125 XR·2120 10K
TXD
I 10K
TXD
Txc SYNC CLK TXCAR TXCAR
Txc Txc IN
10M
ASYNC ~~K ~_ _ _ _ _ _ --+-< 1.8432 MHZ
XR-2122 E:EPHONE

RXD~----I CLK II ~TWORK

RXD SYNC IN RXCAR ~_ _ _~ RXCAR~----------~
RXC~----I

FILTER
600Q

DEMODULATOR

•
Figure 3. Complete Modem Signal Processor

TxeAR

r-------~RXD~------~--~~ . . - - - -........ RXDr--------,

HP1645A Rxe MODEM BRADLEY Rxe HP1645A

DATA UNDER 2A/2B 3002 DATA
LINE 212A
ERROR TEST LINE MODEM ERROR
TXD IMPAIRMENT SIMULATOR TXD
ANALYZER XR·212AS ANALYZER
SIMULATOR
Txe Txe

RXC
Figure 4. Performance Test Set-Up

11-129
 AN-28

00:
O~

Figure 5. Complete 212AS Schematic

11-130
 C2 LINE
AN-28 10-3
ANSWER OR
ORIGINATE MODE
1200 BPS OPERATION
L.U 10-4
l-
e:::(
0:
0:
0 10-5
0:
0:
L.U
!:::
C!l 10- 6

10-7
4 6 8 10 12 14
SIGNAL TO NOISE RATIO (dB)
Figure 6. Error for C2 Type Line
10- 3 BACK-TO-BACK
LINE CONDITION
1200 BPS OPE RATION
L.U 10-4
l-
e:::(
0:
0:
0 10-5
0:
0:
L.U
I-
C!l 10-6

10-7
6 8 10 12 14 16
SIGNAL TO NOISE RATIO (dB)
Figure 7. Error Probability for Back·to-Back line
10-3 OR IG CO LINE
J 1200 BPS OPERATION

L.U 10-4
l-
e:::(
0:
0:
0 10-5
0:
0:
L.U
!:::
C!l 10-6

10- 7
6 8 10 12 14 16
SIGNAL TO NOISE RATIO (dB)
Figure 8. Error Probability for CO Type line
11-131
 ~R AN-29

XR-212ACS Performance Testing

INTRODUCTION TEST INFORMATION

The task of testing the performance of a modem is quite The performance or quality of the modem is measured by
often at best a difficult one. To simulate in the laboratory, its' ability to send and receive data accurately. This is usual-
conditions that may exist on actual phone lines is not only ly specified as its bit error rate (BER). The BER is specified
difficult but requires special test equipment. However, to as the number of errors for a given number of data bits
predict actual operating performance, this testing is neces- received. For example, a BER of 1/10-5 states that one
sary. This application note describes the test method and error may be seen for every 100,000 data bits received. The
actual data on a 300 BPS/1200 BPS full duplex modem BER is usually given as a function of various impairments
system. which may occur on the analog (phone) transmission
medium.
The modem acts as the link between the digital, data side,
and analog, line side, mediums as shown in Figure 1.

DIGITAL ANALOG LINES DIGITAL

DATA (PHONE) DATA

Figure 1. Modem Data Link

The testing here will be done for the following conditions:

1. BE R versus signal to noise ratio (S/N). Th is test is the 2. BER vs. Rx car level. The Tx car is set to a fixed
specification which best describes a modem's actual level and the Rx car level is decreased while BER is
performance in operating environments. The mo- measured at various levels.
dem's transmitted carrier, Tx car, and received carrier
Rx car, are set to fixed levels while noise is added 3. BER vs. frequency offset. Frequency offset repre-
to the Rx car. Figure 2 illustrates such a condition. sen"ts a shift in the frequency of the Rx car due to the
analog medium. For example, an Rx car may be re-
The data error analyzers are used to both send a ceived with a frequency of 1203 Hz although it was
predictable data pattern as well as verifying if it is originally transm itted at 1200 Hz.
received properly. It will count errors for a given
number of data bits.

SUMMER

DATA MODEM DATA

ERROR UNDER MODEM ERROR
ANALYZER TEST RXCAR ANALYZER

Figure 2. BER vs. SIN

11-132
 AN-30

Speakerphone Design using XR-T6420-1

and XR-T6421
INTRODUCTION

A general circuit, showing the major stages within the The attack and release time constants for the VCAs are
speakerphone, is shown in Figure 1. It consists of two audio then determined. The release time constant which is de-
channels (TX and RX), a control circuit. and a hybrid inter- fined as the time for the VCAs to switch from ON to IDLE
face circuit. The gain of each audio channel is controlled state (can be 2-3 seconds) is set by the parallel resistance
by the control circuitry with the use of a voltage controlled of the two control voltage amplifier input resistances and a
amplifier (VCA). The inputs to the control circuit are ob- capacitor.
tained from each of the audio channels.
Once the capacitor is selected, the attack time is calulated.
The hybrid interface circuit performs three important func- This is normally fast to prevent missing the first part of the
tions. First. it couples the TX channel signal to the tele- signal. This is determined by the RC product of the pre-
phone line. Second, it couples the signal on the telephone viously selected capacitor and the series resistor from the
line to the RX channels. And, finally, it cancels a majority capacitor to pin 1 of the control circuit. The output
of the TX signal that can couple into the RX channel. The impedance of the control circuit is low for both the TX and
amount of TX signal that appears on the RX channel is RX state, and is high impedance for the idle state.
called sidetone.
The final step in the design procedure is to adjust the four
rectifiers in the control circuitry. The effect of the noise
circuitry can be disabled by connecting pin 6 to VREF, pin
18, or by increasing the RC time constant on pin 6. Since
CIRCUIT OPERATION
both channels must be functional for this adjustment, there
will be interaction between the rectifiers during adjustment.
Adjusting speakerphones for proper operation is a difficult
This is where understanding the system to determine which
task. There really are not any specifications for the system,
rectifier is causing the problem is helpful. This can be a long
except that during operation, the system must sound right-
and ted ious process because the system must work for a
a high Iy su bjective requ i rement.
variety of line conditions as well as for different people
using the system.
The method used in designing the speakerphone was to first
adjust the gain for each audio path separately with the VCA
RESUL TS
set to maximum gain. After the levels have been set. then
the frequency response can be adjusted to the designer's
requ irements. The finalized schematic for the system is shown in Figure 4.
The frequency response and gain for both channels are plot-
ted in Figure 2. Figure 3 is the component stuffing diagram.
The next step is to determ ine the operating point of the
VCAs. For the system described here, it was decided to
have the sum of the attenuations introduced by both VCAs
to be equal to -50 dB, and the idle state for each VCA to be SET-UP PROCEDURES
-25 dB. The idle state is the condition where the control
logic has not determined which channel should be on and Step 1 - Preliminary Set-Up
has placed the system in a wait state with both channels
partially on until a decision has been made. Connect the junction of Cl and R 1 to ground.Adjust R2 to
make the voltage on Pin 9 of the XR-T6420-1 between +80
The "gain" of the control voltage (ICl and IC2 in Figure 3) and +90 mV. Adjust R3 to make the voltage on Pin 19 of
amp can be calculated because both the input and output the XR-T6420-1 between -80 and -90 mV.
voltage swings are known. The input swing is the control
voltage output from the control circuit XR-T6421, pin 1. Step 2 - Transmit Channel Adjustments
The output swing can then be determ ined using the control
voltage versus gain for the VCAs from the data sheet for Connect the junction of Cl and R 1 to VCe. Adjust R4
XR-T6420-1. and R5 to obtain proper levels on the telephone line
according to system requirements. Normal gains for the
The control voltages for the VCAs in the idle state is then microphone amplifier are in the range of +35 to +45 dB.
adjusted by the addition of a resistance to the invertin~ in- The frequency response of the transm it channel can be
put (RVCTX and RVCRX, Figure 3). adjusted at this time.

11-134
 AN-30

TXPATH

~
Z
~
Cl
UJ
>
;:::
~
a: TX AMP
OUTPUT

+40
TX veA
OUTPUT

TELEPHONE
LINE
+30

MICROPHONE AMP
OUTPUT
+20

VIN = 4mVp_p
+10
100 1K 10K

FREQUENCY (Hzl

Figure 2. Frequency Response and Gain

SPKR

MIC

"""","22K
H
0'

Figure 3. Component Stuffing Diagram

11-136
 EX4R AN-31

PCM Line Interface

INTRODUCTION Receiver Circuit Description:

The XR-T5680 is a Monolithic PCM Transceiver. It is de- The receiver is designed to handle a max imum of 10 dB line
signed primarily for short line (<10 dB) PCM transmission attenuation. This condition allows the design to adopt a
applications such as in digital Private Branch Exchange relatively simple approach as compared with long trans-
(PBX) environment, Digital Multiplexed Interface (OMI) and mission line receivers which usually require AlBO circuits
standard PCM data interface circuits. The maximum fre- and equalization networks to function properly.
quency of operation is 10 MBits/s so it covers T1, T1C, T2
and Europe's CEPT 2048K and 8448K Bits/s data rates.
The device is packaged in a hermetic 18 Pin CEROIP and The successfu I operation of th is receiver relies on the peak
is designed such that there is no phase difference between detector which converts the incoming signal amplitude into
the extracted clock and data outputs at the receiver. a DC variable threshold. The variable threshold is arranged
to slice the input signal at half amplitude point at the data
comparator (see Figure 3). so that 0+ and 0- data can be
accurately extracted under the worst expected condition.
It also ensures a nominal ouput pulse width change at
different input signal levels. The 0+ and 0- data both go
through similar level shifting circuits to be converted into
PRINCIPLES OF OPERATION
TTL compatible output signals.
Figure 1 contains a Functional Block Diagram of the
X R-T5680. The circu it consists of two separate sections:
one is the line receiver, and the other is the line transmitter.
The receiver accepts incoming bipolar signals and converts
them into TTL 0+ and 0- data streams. It also produces
a clock output from the input data. I n the transm it direc-
tion, full width, TTL compatible 0+ and 0- signals at the
I inputs and a 50% duty cycle clock are combined to form

the bipolar line signal at the outputs of a transformer.

The power supplies for the two sections of the circuit are Clock Extraction and Timing:
internally isolated to avoid crosstalk problems.
Since the input spectrum does not carry any frequency
components around the transmission rate, input wave-
form is full wave rectified and applied to an external L-C
resonant circu it for clock extraction. The amplitude modu-
lated sine wave at the resonant circuit is coupled through a
capacitor to a zero crossing detector before applied to the
input of a ECL/TTl converter as shown in Figure 2.

To convert the half-width data at the receiver outputs

into full width signals for digital processing, it is common
practice to use positive edge triggered O/F Fs. This requires
the mid-point of the data to be aligned with the rising edge
of the clock so that no error will result should the data be
jittered with a max. amplitude of iO.25 U I relative to the
clock (see Figure 5). The disadvantage of this scheme is
additional hardware is needed to ensure that the two signals
have the correct timing relationship. It is possible by means
of an alternative retiming circuit as shol,lli'l in Figure 6 to
perform the same function while still keeping the data
and the clock in the same phase. This circuit has twice the
Figure 1. Functional Block Diagram jitter tolerance under the same ccmdition as compared with
a single Ootype counterpart and is recommended to be used
with the XR-T5680. It is anticipated that no glitches due to
crosstalk, etc., should exist at the receiver data output ter-
minals under the intended short line applications.

11-138
 AN-31

EXTERNAL
COMPONENT

CLOCK
TTLOIP

- - - -_ _-[)ATACOUP & CLOCK EXT'RACTlOfriII _ __

----ZEROCOOSS~,.GOET&ECLiTTLCONIJ - - -...

Figure 2. Simplified Circuit of XR-T5680 Receiver

-10dB (1-1-1 Pattern) WITH DATA THRESHOLD

-3 dB VERT = 1VtCM
HORZ = 200 nStCM

TANK CIRCUIT WAVEFORM AT PIN 4

-6 dB WITH DATA THRESHOLD

-10 dB WITH DATA THRESHOLD RECEIVER DATA AND CLOCK OUTPUTS

Figure 3. Typical Eye Pattern Obtained at Pin 2
or 3 for Coaxial Cable at Various Line Figure 4. Timing Diagram of Circuit Waveforms
Length. Bit Rate = 2048 KBits/S for a 1-1-1 Input Data Pattern
11-140
 AN-31

56 1:1:1 TO LINE 75[2

+Vcc
5.0V

D+I/P
SAMPLING CLOCK lIP
D-I/P

DATA+O/P

DATA-O/P

CLOCKO/P

+Vcc
5.0V

*430Q FOR TWISTED PAIR L·C TANK

Figure 8. A Recommended Circuit Diagram Connection For 2048K Bits/s Line Interface Application

11-142
AN-32

ELECTRICAL CHARACTERISTICS
o
Test Conditions: +VCC = 5.0 V, operating temperature OoC to +70 C.

PARAMETERS PIN UNITS CONDITIONS

NO. MIN TVP MAX

DC Supply 14 4.75 5.0 5.25 V

Supply Current 9,14 35.0 45.0 mA Transmitter Drivers Open

Tank Drive Current 9 1.7 2.0 2.3 mA Pin 8 & 11 = 0 V, Supply

3.0 V to Pin 6

Clock Output Low 13 0.3 0.8 V IOL =1.0 mA

Clock Output High 13 3.0 4.3 V IOH= -400~A

D+, D- Output Low 12,10 0.4 0.8 V IOL = 1.0 mA

D+, D- Output High 12,10 3.0 4.5 V IOH = 400~A

Driver Low Voltage 17,18 0.6 0.05 V IOL=40mA

Driver Sinking Current 17,18 40 mA VOL = 0.95 V

Driver Output Rise Time 17,18 20 30 nS With 150n Pull·Up

to +5.0 V, CL = 15 pF

Driver Output Fall Time 17,18 20 nS With 150n Pull-up

to +5.0 V, CL = 15 pF

Pulse Width at 2048K 17,18 219 244 269 nS With 150n Pull-iJp
to +5.0 V

Pulse Width Imbalance at 2048K 17,18 5 10 nS At 50%

Clock Duty Cycle at 2048K 13 40 50 60 nS %

Clock Rise Time 13 25 nS 10-90%

11-144
AN-32

PIN 14

'--"1--41~-+--+------, TO ECL/TIL
CONVERTER

PIN 2

"--PEAK DETECTOR--.. ~DATA COMPARATOR AND--. ~ CLOCK AMPLIFIER AND --.

FULL WAVE RECTIFIER CROSS ZERO DETECTOR

Figure 4. Simplified Schematic of XR·T5681 Receiver

TRANSMITTER

The transmitter consists of two identical TTL input open si~nals. a synchronized 50% duty cycle TTL clock is needed
collector NAND gates. The output driver has a nonsatu- at Pin 5 to obtain a bipolar signal at the output of a center
rating stage and can handle a maximum current of 40 mAo tapped transformer (See Figure 5). The output pulse con-
If the inputs are half width signals. Pin 5 should be returned forms to CCITT G.703 recommendation. A circuit connec-
to +VCC via a 1 Kn resistor. If the input data are full width tion diagram for 1.5Mb/s line interface is shown in Figure
6.

SYNCHRONIZED
CLOCK

D+

INPUT DATA

D- --------~~-------~~~---------
OUTPUT ________ ~~ ~~I_____ ~____~Il~, ______
BIPOLAR
SIGNAL
u U
Figure 5. XR·T5681 Transmitter Section Timing Diagram

11-146
 SLrULI
TElECDmm/[]PtTPtCOmm
SPEC~Ptl ~SSLJE

Implement Bell TlC

PCM repeater using
just two IQ
the signals at frequent intervals, a repeater constructs
Because T-carrier lines will be an essential an accurate reproduction of the original digital pulse
train. Typically, you insert repeaters in twisted-pair
part of tomorrows data-communication lines at approximately 6000-ft (1.8 km) intervals.
networks) it)s imperative that you learn The function of a repeater can be summarized as
how to interface your communication reshaping, regenerating, and retiming ("the three Rs").
o Reshaping means to restore a pulse to its original
systems with these lines. Two ICs let you width (but not necessarily to its original shape).
implement a TlC repeater that contains It's essential that a pulse be reshaped so it won't
all the circuitry necessary for pulse- spill over into an adjoining time slot and interfere
with the detection process.
code-modulation (PCM) transmission. o Regenerating means deciding whether each arriv-
ing signal is a zero or a one. To make this logical
decision, the repeater adjusts the decision thresh-
M Kursat Kimyacioglu, Exar Corp old of its comparator circuit to the middle of the
pulse amplitude.
Once the exclusive province of a select community of • Retiming means synchronizing clock signals. To
telephony engineers, the techniques involved in Bell retime, the repeater must extract the clock signal
TIC transmj"sion and repeaters are now required from this incoming pulse train by sampling the
knowiedge for anyone transmitting data along twisted- comparator output. It must sample the output at
pair cables. You can use two lCs to implement-- a rate that ensures it will recover with a minimum
economically-a TIC repeater that includes all the number of errors, so the signals the repeater
active circuit functions necessary to accommodate transmits will have correct spacing, pulse width,
pulse-code-modulation (PCM) transmission. and rise and fall times.
Repeaters are essential for PCM transmission over TIC systems must accommodate the same transmis-
more than 6000 ft of cable. When a pulse travels along a sion distances between repeaters as TI systems do-a
cable, it gets distorted in shape, dispersed in time, and nominal maximum of 6300 ft over 22-gauge pulp- or
subjected to crosstalk and random noise. By repeating plastic-insulated cable. As a result, the repeaters for
11-148
 TABLE 1-LlNE REQUIREMENTS FOR T1 AND T1 C SYSTEMS
PARAMETER REQUIREMENT
T1 T1C
SYSTEM TYPE REGENERATIVE BASEBAND, REGENERATIVE BASEBAND,
DIGITAL DIGITAL
MEDIA TWISTED-PAIR CABLE TWISTED-PAIR CABLE
TRANSMISSION RATE 1.544M BPS 3.152M BPS
(24 DIGITIZED VOICE (48 DIGITIZED VOICE
CIRCUITS) CIRCUITS)
RECOMMENDED RANGE SO REGENERATIVE SECTIONS 50 REGENERATIVE SECTIONS
(90 krn) (90 krn)
PAIR LOSS 7TO 35 dB 9 TO 54 dB
REPEATER/REGENERATOR AMI-BIPOLAR, AUTOMATIC- AMI-BIPOLAR. AUTOMATIC-
lINE.JBUILD-OUT, SELF- LlNE..,BUILD-OUT, SELF-
TIMED CIRCUIT TIMED CIRCUIT
MAXIMUM NUMBER OF
NO-PULSE SYMBOL
INTERVALS 15 132
TIMING CIRCUIT a FACTOR LOW a SOT0100 HIGH 0>1000
REPEATER SPACING 6300 FT MAX WITH 6300 FT MAX WITH
22-GAUGE COPPER PULP- 22-GAUGE COPPER PULP-
INSULATED CABLE INSULATED CABLE
FAULT DETECTION BIPOLAR VIOLATION AND BIPOLAR VIOLATION AND
TRIO-PULSE FAULT-LOCATION TRIO-PULSE FAULT·LOCATION
CONFIGURATION CONFIGURATION
LINE CURRENT 60 rnA 60 rnA

INPUT
TRANSFORMER EYE
PATTERN

LINE J ALBO
NETWORK
[:,
RECOVERED CLOCK

VARIOLOSSER
DIODES

Fig I-To provide automatic gain control, an Alba (automatic line-build-ouO network usually precedes the repeater's preamp.
line-voltage drop within preset limits. are frequency dependent. Theoretically, the equaliza-
The transmission requirements for Tl and TIC re- tion process establishes the exact inverse of the cable
peater designs are approximately the same. However, characteristics to reshape transmitted pUlses. In prac-
the TIC line loss may be as high as 54 dB. In addition, tice, however, equalization almost exactly compensates
T1C'shigher transmission rate makes it more suscepti- cable loss vs frequency characteristics, but it only
ble to performance degradations induced by variations partially corrects phase distortion.
between the cables in an installed system. Thus, TIC is In existing systems, cable lengths are governed by
much harder to implement than Tl is. the distance between repeaterR, ~hi1e c8l)le character-
A TIC system, which consists of two multiplexed Tl istics vary according to temperature and humidity
channels, has a bit rate of 3.152M bps. This figure is conditions. Because of these factors, the repeater must
slightly more than twice the Tl rate since synchroniza- have a variable-slope transfer function that will match
tion and control bits have been added to the stream. any cable length and also respond continually to chang-
Now, the power output's spectral density peaks at 1.576 ing environmental conditions.
MHz. In a TIC system, you can't approximate the
line-loss characteristics with a single pole-you'll need Realizing a repeater
at least two poles and maybe three. As Fig 1 illustrates, an automatic-line-build-out
Remember that transmission-cable characteristics (Alho) network usually precedes the preamp. In addi-
11-150
The repeater must have a variable-slope
transftr function that responds continually
to changing environmental conditions.

line code for PCM transmission. When you use AMI, In practice, when both high-Q and low-Q clock-
you transmit successive ones in opposite (bipolar) direc- extraction techniques are employed, high-Q techniques
tions. AMI also offers a means of detecting single-bit result in more accurate extraction. You can implement
errors. high-Q extraction circuits using passive quartz crystal
The circuit in Fig 1 employs a full-wave rectifier to filters or crystal-controlled phase-locked loops. For
extract the network clock signal; it rectifies the equal- low-Q circuits, you can get by with conventional RLC
ized signal at about 50% of its peak value and drives a tuned circuits.
tank circuit with this signal. The rectifier's clipping An equalized signal is applied to a pair of compara-
level changes the amplitude and phase of the recovered tors to detect positive and negative pulses. Two data-
clock. This scheme is susceptible to variations in pulse latch circuits store the detected pulses on the positive-
amplitude and density, so it results in timing jitter, going edge of the clock. Data-latch outputs and the
most of which is caused by mistiming in the clock clock signal are then gated and amplified to produce
extraction circuit. When there are no marks on the line, regenerated and retimed pulses for transmission over
the recovered clock will drift toward the self-oscillating the next 6000 ft of cable.
frequency of the tuned circuit. A new mark will return The complete TIC repeater design is shown in Fig 3.
the clock to the data-repetition rate. The jitter will be The bipolar PCM signal, attenuated and distorted by
dependent upon the degree of mistuning and the spec- the transmission medium, is applied through a pulse-
tral density of the data signal. Local noise and crosstalk shaping network to a preamp. This network, along with
will also affect the jitter. variolosser diodes, forms the Albo circuit, which pro-

Fig 3-The Albo network automatically adjusts for varying cable characteristics. The network comprises the variolosser diodes ami the
pulse-shaping network/preamp.
11-152
11-154
EXAR'S COMMITMENT TO QUALITY
AND RELIABILITY

First the terms Quality and Reliability must be A Modest Investment

defined.
EXAR's Standard and Exce"" screening methods
Quality is conformance to requirements, i.e., are virtually identical to those used in compliance
meets specification requirements, adheres to pro- with military specifications.
cedure, etc. Quality must be measurable, thus it
must be defined in measurable terms. Quality is Yet, because there is no extensive military
measurable in many ways, a common one being documentation involved, EXAR can pass these
Average Outgoing Quality Level (AOQL) generally savings on to you.
stated in Parts Per Million (PPM).
The result is that you receive almost mil-grade
Reliability is length of time product conforms. parts at lower prices.
This is also a measurable quantity and is gener-
ally expressed as Mean Time Between Failures
(MTBF) or Failures in Time (FIT). The relationship
FAILURE RATE COMPARISON
between MTBF (or failure rate) and time is illus-
trated in the bathtub curve.
INFArH NORMAL WEAROUT
EXAR is committed to achieving high levels of MORTALITY LIFE PERIOD
PERIOD
Quality and Reliability. To achieve this goal, we
design and build quality and reliability into all
our products. Each EXAR employee is committed
to assuring this goal by diligent adherence to the
quality first concept.

EXAR continuously monitors the Quality and

Reliability levels of its products via AOQL sam-
pling plans and periodic reliability testing pro-
grams. Monitoring alone is not sufficient. At EXAR
any reject discovered at the monitoring level is
scrutinized by extensive failure analysis and cor-
rective action taken to prevent recurrence.

Reliability, primarily a function of device design, EXAR's Reliability Program Summary

fabrication, and assembly methods and materials,
cannot be tested into les. However, EXAR pro- EXAR's reliability program is designed for the
poses combinations of specific environmental evaluation of high-density complex integrated cir-
tests designed to accelerate failures of marginal cuits which require greater attention than simple
devices, thereby eliminating early life failures. conventional reliability tests. EXAR believes in
By choosing the desired combination of environ- producing excellent reliability (XR) by building
mental tests, you can choose the reliability level the quality and reliability into the products. Once
that fits your need. raw silicon is transferred to a complex integrated
circuit, through quality conscious people, it needs
to satisfy the increasingly stringent requirement
Benefits Every Step of the Way of the QA Reliability Department to ensure that
Devices that undergo the specifically designed the products demonstrate the acceptable level of
environmental tests begin paying dividends the quality and reliability.
moment you receive them and continue doing
so for the life of the system. Reliability Testing
Your circuit board testing is also reduced along Reliability is defined as "the probability of an
with your test equipment costs. Since more of item to perform a required function under stated
the components on a board are higher quality, conditions for a stated period of time." EXAR
the quality of the entire board is better. performs the reliability testing on a sample of
100 pieces and the flow being used is detailed in
There is less board rework for the same reason. Table 1. There are monitoring programs at EXAR
to assure high product reliability.
Even traditional burn-in can be reduced substan-
tially, improving the flow of work in process. Based on the data available from reliability exper-
iments, MTBF, and failure rate are computed
Finally, performance in the field is improved. using the Arrhenius equation. Results of recently
Fewer field failures result in fewer service prob- completed reliability experiments are summar-
lems and, more important, fewer dissatisfied ized in Table 2.
customers.
12-2
 *QUALIFICATION & QUALITY CONFORMANCE PROCEDURES

Mil-Std, Method 5005, Class B

Screen Test Conditions Requirement

GroupA Final electrical repeated on sam- Each sublot sampling basis.

piing basis (sub group 1 thru 11)

Group B Package construction & function Each sublot sampling basis

related tests (dimensions, resis- except subgroup 6.
tanceto solvent, solderability, Subgroup 8 only for initial
int. visual, bond strength, seal qualification.
&EDS)

Group C Die related tests (life test, temp Performed every 3 month
cycling, canst. acceleration & interval for each micro
seal tests) circuit group.

Group D Package related tests (dimen- Performed every 6 month

sions, lead integrity, seal tests, interval for each package
thermal shock, temp. cycle, type.
moisture test, mechanical shock,
vibration, canst. acceleration &
salt atmosphere)

12-4
 EXAR'S EXCEL'· PROGRAM

PLASTIC(P) CERAMIC(N)
SCREENING COMMENTS
XL1 XL2 XL3 XL4

Pre cap. QCI2006 Method 2010 QCI2004 Method 2010 100%

Internal Visual Condo B

Sta. Bake 6 hrs @ 175°C 6 hrs @ 175°C 6 hrs @ 175°C 6 hrs @ 175°C 100%

Temp. Cycling -65°Cto -65°Cto 10 Cycles 100%

+ 150°C + 150°C
Const.Accel. 30,OOOgm Y1 30,OOOgmY1 .65%AQL
axis axis

Fine Leak .65%AQL .65%AQL .65%

Gross Leak 100% 100%

Pre Burn-in 100% 100% 100% 100% Per Device Spec

Electrical

Burn-in 48 hrs 160 hrs 48hrs 160 hrs

Final Electrical 100% 100% 100% 100% Per Device Spec

AQLSampie .065% .065% .065% 0.65% Mil Std 105 D

External Visual PerXRStd PerXR Std PerXR Std PerXR Std 100%

QAPlant 100% 100% 100% 100%

Clearance

PRICING MARKING
EXAMPLE

CONSULT x = Grade Designation

FACTORY C = Commercial

Y = Package Type
P = Plastic
N = Ceramic

Z = Screening Level
1 through 4

12-6
 Package Information
(Plastic)

8 PIN MOLDED PLASTIC DIP 8 PIN MOLDED PLASTIC DIP (JAPAN)

,-
300' 012

r--I---.l ---L
031 !17
153
031

Ur.---.....,.,.....,.,-
012
668 ...A
-~t6
l+~~-
142-
i26
-J I- -.111-- Q~
1}~
118
ili r
1~~2 _j
mFfMN=1 "" g~~ _.l11~26
I_- ffi -' 100' 012
1_-- 600' 012---1 016 100 . 1_

I- 700' 012----
. 008

14 PIN MOLDED PLASTIC DIP 16 PIN MOLDED PLASTIC DIP

r -- 900 012~ ~0940

300 012
"""-1::::: ~:1]: 300 - 012

------1 ' 031

.6i1 : 008 ~
.
... OJ? "
.
----
~.

008
066

',- 1180
rL
-T--~--~
152
126
I, I 1---
1:+012
1
____ --1

I 370
322 .1

18 PIN MOLDED PLASTIC DIP 20 PIN MOLDED PLASTIC DIP

13-2
 Package Information
(Cerdip)

r---. 766
---j
I-·~~~-I Inn r .754 ., n n I
-+
U
025R
Typ .289
.245
-+
1

'050~~~
.030 . -.

L: :3 Max

TI ~.15O
.005-11_
Min .100
J I _IL .023 .120
L .015
Typ

8 PIN CERAMIC CAVITY DIP 14 PIN CERAMIC CAVITY DIP

898
_ .
8 8 2 -1

""'i: ::::::l~
1

I-;~-I-.·
~-170 L mmm-~~
.030
.. --. ~~-I I ~L ~
m.
050 -:-.170 .030· -.

tl
.200 Max "'i4o .2ooM..

'I~ T
-1-#£_1-0
.008 ---t-~
~.12O
oo8J\_00_150~L
RQ. If
-'I~
~ .ISO

0
-15 0 .005
Min _1- -U-
Typ
_IL .023
oi5 Min
__
.100
Typ
.015
.120

16 PIN CERAMIC CAVITY DIP 18 PIN CERAMIC CAVITY DIP

~ 1.078 .[

I
r-- .
In n n n I
958
--J
942 n n nnl
Inn n I 1.062

·~wwmM ~~=
420
.030
L
, .OSO.
.200 Max
_.
.400
_1 + .OSO

_ gqJf ~RRRR ARAi¥1

1

til - 11=1 ~008 I +

~ ~---t
M

"

J L 0 1 8 ' 003
-.
.looJ
Typ
Lm -U-

-
U

\-00 -15'
.040! .010 u

:lL.018
U u u u

'OO31OO~002-1
U u u u

L .:~

20 PIN CERAMIC CAVITY DIP 22 PIN CERAMIC CAVITY DIP

13-4
 Package Information
(Plastic Small Outline)

.342± .012
.197±.012

r1
""m3'''' I
r--O---.
.173 ± .008..
. L - - "', ---*.
.244 ± .012

.025
---.1 .059 ±.004
--.l ,008 ± ,004 ~
.025
.002 Min --.t±
,059 ,004

.OO8:!:.O04

~~L:!
.002 Min
t-,c::)\~ t=m:r--r
.012Minf .016 ± .004
t-JiT~
I- .050 ± .006 ,012 Min
rL
J
,016±004 JL ~
,O5O±,OO6

8 PIN S.O. T. PACKAGE (M.D.P.) 14 PIN S.O.T. PACKAGE (M.D.P.)

I' ,394 ± .012'1

I
.4040±.012

'I
r-~---'
.173~~~,012
I
,213
r-r.~~~Jlf
j ,006 J 19

I
~,012

' .059 ± ,004

.006 ± ,004 ~5 .002 MIn --.l ,031 .070±.004
,008 ± ,004 -1 ,002 Min ~

t-tE3\~ t-~~ t-~t t-~-r

~ ~
,012 M i n ) -
,016±,OO4JI_J
. .050±.008 012Minr~ 01S±,OO4Jl
.000±,OO6

16 PIN S.O.T. PACKAGE (M.D.P.) 18 PIN S.O.T. PACKAGE (M.D.P.)

,03'
,03'
--L- 1- .070±.D04
T:un+-E3=~l.4070:!:004If=.~OOOO 0 OHtiP~
-11-·012 Min ,OOU.OO4 .002 Min ..jf...j I-,oso:!: ,006 ~+
....J J.- .012 Min OM ± otW
tpv:UuiOuriumuiuIDUuiOurilAiul
,!!,)2 ~!" ..f I. -I J... ,OSC :!:.CIOS
.01S:!: ,004 .0'8 ± ,004

20 PIN S,O.T. PACKAGE (M.D.P.) 22 PIN S.O.T. PACKAGE (M.D.P.)

13-6
44 PIN QUAD PACKAGE

13-8
The Benefits of Surface Attachment
Surface mounting identifies a technique for mounting • Higher Performance-Because boards are smaller
ICs and other devices of like geometries in a low-profile and IC lead inductances are less, distributed react-
package on the surface of a printed-circuit board. ances are reduced and signal paths are shortened.
These devices are today known as SO (Small Outline) This raises performance in high-speed, digital sys-
devices. Unlike plated-through-hole technology in tems, and in r-f systems.
which the leads of devices are inserted in holes
perpendicular to the board surface, the leads of the • Cost-Effective On-Shore Assembly-Because the
SO devices solder to circuit board pads that lie on SO components enhance the appeal of on-shore,
the board surface. automated assembly, they can eliminate the severe
logistic demands and extended cycle times of off-
Both the surface area and the profile (height of the shore assembly.
package above the board) are reduced. As an example,
a 14-pin SO package has an overall height of .067-inch, Typical Surface Mounting Applications ...
whereas a conventional DIP is .177-inch high. The SO In consumer products where compact assemblies are
package leads are spaced on 0.50-inch centers, rather essential-hand-held cameras, toys, audio equipment.
than 0.1 OO-inch centers, as is the case with the tradi- In automotive equipment ... engine and climate
tional DIP package. controls.
Other benefits include: In Telecommunications ... modems, active filter net-
works, speech processors, PBXs and voice-recogni-
• Reduces Assembly Costs-By utilizing the new
tion units.
pick-and-place equipment, board assembly can be
fully automated. Components are available on reels In Computer Peripherals ... Disk Drives, Winchester
which dramatically reduce storage and handling Drives, and thermal and impact printers.
costs.

• Smaller Boards-Because the SO package sizes

are approximately 30% to 50% smaller in size than
their DIP counterparts, printed-circuit boards can be
reduced in size by 50% or more.
Exar's Surface-Mountable
Package Devices Exhibit
• Less Complex Circuit Boards-Since SO-packaged
ICs mount on the surface, rather than in relatively Extraordinary Reliability
large (.035-inch) plated-through holes, both rigid
and flexible circuit boards require fewer and smaller
Exar's so package, using a unique nitride passi-
vation, has shown itself able to survive highly
holes. Where interconnections are required be- stressful environmental conditions. Which is why
tween layers, vias, typically 0.018-inch in diameter, Exar's SO devices are as reliable as any 0.300-
are employed. This enables designs to employ inch spaced, conventional DIP.
fewer circuit board layers and hence less costly cir-
cuit boards per square inch. Here is some typical test data:

Reliability Data
Sample XR2004 XR3403 XR4558
Test Condition Size Rejects Rejects Rejects
External Visual Per MIL STD 883, method 2009. 200 0 0 a
High Temp. Storage 48 Hr. at 150°C 200 a a a
Temperature 10 cycles- - 65°C to 150°C per MIL STD
Cycling 883, method 1010, condition C. 200 a a a
Electrical Tests Per Exar Data Sheet. 200 a a a
Lot Sample 48 Hr. Max. Elect. Tests per MIL STD 883,
Burn-in method 1015 at 125°C for48 hours; end
point electrical tests per Exar Data Sheet. 55 a 0 a
Autoclave 100 Hr. 121°C, 15 p.s.i.g.; electrical tests
(Pressure Cooker) per Exar Data Sheet. 25 1* a a
Steady State 1000 Hr. TA = 125°C per MIL STD 883,
Life method 1015. (See Note) 55 a a a
Biased 1000 Hr. TA = 85°C, R.H. = 85%; electrical
Moisture Life tests per Exar Data Sheet. 55 U a a
* Note: One electrical failure at post burn-in after 500 hOI"rs. 13-10
Surface-Mounting A Glossary of
Manufacturing Techniques ... Surface Attachment Terms
Component Handling Aspect Ratio
Exar can supply ICs in both antistatic tubes and various The ratio of the circuit board thickness to the smallest hole
tape and reel options, including EIA standard RS-4B1 diameter.
specified taping (see bibliography page 7). This taping Barrel
is compatible with automated assembly equipment The cylinder formed by plating through a drilled hole.
such as Panasonic's Panaplace "M", Universallnstru- Fluorinated Carbon
menfs Onserter, and adaptable to many others such A fluid which when vaporized behaves as a highly-effective
as Dynapert, Zevatech, Celmacs, Fuji. and MCT. heat-transfer medium in vapor-phase soldering.
Component Placement Hot-Air Soldering
Typically pick-and-place equipment uses a vacuum A typical hot-air system employs a preheat and a soldering air
mechanism to hold the device on its vacuum place- jet. Preheat usually occurs at 110°C, followed by soldering at
260°C. Travel is typically 10 cm/minute (3.93 inches/minute).
ment probe. Placement equipment can place within
Air pressure must be monitored to make sure a device is not
± 0.0005 inch from a fixed x-y position. Typical equip- blown out of position or that molten solder does not bridge
a
ment places BOO to BOO components per hour with adjoining traces.
some equipment placing surface-mounted devices at
Infrared
even much higher rates.
Basically an oven technique for reflow soldering.
A standard technique is to tack the IC in place with Mil
solder paste, then dried in order to secure position One-thousandth (0.001) of an inch.
prior to wave soldering.
Multilayer Printed-Circuit Board
In practice, alignment can be off slightly due to the A printed circuit board consisting of three or more conduct-
'self-aligning' feature. For when the heat melts the ing circuit planes separated by insulating material and
solder, the leads are pulled laterally as well as down bonded together with internal and external connections to
onto the pads. each level of the circuitry as required.
Plated-Through Hole
Component Soldering A hole with the deposition of metal (usually copper) on its
The SO package is designed primarily for reflow solder- sides to provide electrical connections between conductive
ing-rather than wave soldering. Reflow techniques patterns at the levels of a printed circuit board.
include: Reflow Soldering
• Infrared A technique employed in surface attachment to solder de-
• Hot Air vices to printed circuit boards. It requires that leads and pads
• Vapor Phase of boards already have solder in place.

Best results are obtained when the same solder is SMD

Surface Mount Device-(same as SO)
used on the leads and on the substrate metalization.
Printed-circuit boards can be metalized by dipping in SO Package
a solder bath, or by screening solder paste and then Small Outline Package (See SMD)
reflowing. Paste thickness should be typically 0.006 Solder Paste
to O.OOB inch (150 to 200 micrometers) thick. Finely-powdered solder and flux suspended in a binder.
Solder Resists
Coatings which mask and insulate portions of a circuit pat-
tern where solder is not desired.
Vapor-Phase Soldering
Batch Type A technique employed in surface attachment technology to
VPSSystem reflow solder devices to the foil pads on the printed circuit
board. Heat is conducted through a gas, typically a boiling in-
Secondary ert fluid usually 215°C blanketed with a vapor blanket to pre-
~ s Condensing vent loss of the inert fluid. This technique is significantly
r> Secondary C Coils
Vapor
faster than other methods.
~ Zone S; Primary Via
p C Condensing
A plated-through hole used as a through connection, but in
Primary Coils
Vapor which there is no intention to insert a component lead.

GJ5 . .
Filter
::.
Zone

Pump
~Immersion
Heater
Wave Soldering
The traditional technique for soldering components to circuit
boards. The bottom surface of the boards travels across the
surface of a reservoir of molten solder and the solder is
drawn up into each plated-through hole by capillary action.
Wetting
The formation of a relatively uniform, smooth, unbroken and
adherent film of solder to a base material.

13-12
 ~R

Authorized Sales Representatives

ALABAMA flORIDA MAINE NEW JERSEY (Northern)
REP INCORPORATED DONATO & ASSOC., INC. (SEE NEW HAMPSHIRE) (SEE NEW YORK CITY)
PO BOX 4889 5401 KIRKMAN RD., STE. 785
11535 GILLELAND ROAD ORLANDO, FL 32819
HUNTSVILLE, AL 35815 305/352-0727 MARYLAND NEW JERSEY (Southern)
205/881-9270 TWX 62897593 COMPONENT SALES SUNDAY·O'BRIEN
TWX 810-726-2102 106 OLD COURT ROAD 15 POTTER STREET
FAX 205-882-6692 DONATO & ASSOC., INC. SUITE 204 HADDONFIELD, NJ 08033
535 HOLLOW RIDGE ROAD BALTIMORE, MD 21208 609/429·4013
PO BOX 1560 301/484-3647
ALASKA TWX 710-862-0852
PALM HARBOR, FL 33563
(CALL EXAR DIRECT) 813/785-3327 NEW MEXICO
SYN TECH
DONATO & ASSOCIATES, INC. MASSACHUSETTS
8016 A ZUNI ROAD, S.E.
ARIZONA
ATIN: WOODY WOODRUFF (SEE NEW HAMPSHIRE) ALBUQUERQUE, NM 87108
SUMMIT SALES 2027 L1TILE NECK ROAD 505/266-7951
7802 EAST GRAY ROAD CLEARWATER, FL 33515
SCOTISDALE, AZ 85260 MICHIGAN NEW YORK (Upstate)
602/998-4850
GEORGIA R.P. URBAN & ASSOCIATES QUALITY COMPONENTS
TWX 910-950-1283
2335 BURTON ST., SE 3343 HARLEM ROAD
REP INCORPORATED PO BOX 7386
1944 NORTHLAKE PKWY., BUFFALO, NY 14225
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STE. 1 616/245-0511
HARVEY KING, INC. TUCKER, GA 30084 TWX 910-380-2126
TWX 810-273-6992
6393 NANCY RIDGE DRIVE 404/938-4358
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619/587-9300 FAX 404-938-0194 MINNESOTA 116 E. FAYETIE STREET
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DAN'L ENGINEERING 315/682-8885
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1618 COTNER AVENUE SUITE S145
(CALL EXAR DIRECT)
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612/854-7550 NEW YORK (City)
213/879-0770
TWX 910-342-6343 ILLINOIS (Northern) TLX 291008 DANL ENG BLTN TRIONIC ASSOCIATES, INC.
FAX 213-478-0190 JANUS, INC. 320 NORTHERN BLVD.
650 DEVON, STE. 165 MISSISSIPPI GREAT NECK, NY 11021
LANDA/MINYARD, INC. ITASCA, IL 60143 516/466-2300
1616 EAST 4TH ST., STE. 280 (SEE ALABAMA) TWX 510-223-0834
312/250-9650
SANTA ANA, CA 92701 TWX 510-600-3070
714/543-7805 MISSOURI NORTH CAROLINA
ILLINOIS (Southern) JIM MOORE & ASSOCIATES ZUCKER ASSOCIATES, INC.
CALIFORNIA (Northern) 380 BROOKES DRIVE, STE. 109 PO BOX 19868
(SEE MISSOURI)
TRIPAR ASSOCIATES HAZELWOOD, MO 63042 RALEIGH, NC 27619
SUITE C204 3141731-2240 9191782-8433
1580 OAKLAND ROAD INDIANA TWX 650 277 3960 MCI TWX 510-928-0513
SAN JOSE, CA 95131 (SEE OHIO)
408/280-5744 MONTANA OHIO
IOWA (SEE COLORADO) THOMPSON & ASSOCIATES
COLORADO (SEE MISSOURI) 23715 MERCANTILE ROAD
CANDAL INC. NEBRASKA BEACHWOOD, OH 44122
1536 COLE BLVD., STE. 145 216/831-6277
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303/233-0155 JIM MOORE & ASSOCIATES
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NEVADA
KANSAS CITY, MO 64151 5556 PHEASANT DRIVE
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COi,NECiiCUi 614/877-4304
PHOENIX SALES
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RIDGEFIELD, CT 06877 (SEE OHIO) ACCESS SYSTEMS CORP. 309 REGENCY RIDGE
203/438-9644 7C TAGGART DRIVE DAYTON, OH 45459
TWX 710-467-0662 NASUA, NH 03060 513/435-7733
LOUISIANA 603/888-8160 TWX 810-459-1767
(SEE TEXAS) TWX 710-228-1769
DELAWARE
(SEE MARYLAND)

14-2
 E.X4R

International Sales Representatives

AUSTRALIA GREECE LATIN AMERICA SPAIN
TOTAL ELECTRONICS GENERAL ELECTRONICS LTD. INTECHTRA UNITRONICS, SA
9 HARKER STREET 209 THIVON STREET 2629 TERMINAL BLVD. PRINCESA,l
PMB NO. 250 NIKEA MOUNTAIN VIEW MADRID 8, SPAIN
BURWOOD 3125, AUSTRALIA PIRAEUS 7, GREECE CA 94043 USA SPAIN
PHONE 288-4044 PHONE 49 13595 PHONE 415/967-8818 PHONE 242-52-04
TLX 790-31261 TOTELEC AA TLX 863/212949 GELT GR TLX 345 545 INTECTRA MNTV TLX 831-46786 UTRON E

TRONIC BITS
HONG KONG LIECHTENSTEIN SWEDEN
PO BOX 371
MENTONE ROHM ELECTRONICS LTD. (SEE SWITZERLAND) AB BETOMA
VICTORIA 3194, AUSTRALIA FLT. 13 3/F NEWPORT CTR. DALVAGEN 12, BOX 1138
PHONE 555-6777 116 MATAUKOK RD. S-171 22 SOLNA
TLX 790-151479 TRON AA TOKWAWAN, KOWLOON LUXEMBOURG SWEDEN
HONG KONG (SEE GERMANY) PHONE 08·820280
PHONE 3-343481 TLX 19389 BETOMA(S)
BELGIUM TLX 780/37503 REHCL HYX
(SEE NETHERLANDS) NETHERLANDS
NIJKERK ELEKTRONIKA BV SWITZERLAND
INDIA DRENTESTRAAT 7 1083HK STOLZ AG
BRAZIL FEGU AMERSTERDAM TAEFERNSTR. 15
ROHM ELECTRONICS LTDA. 2584 WYANDOTTE STREET HOLLAND CH-5405
AL. REO NEGRO 1356 MOUNTAIN VIEW PHONE 020 462221 BADEN-DAETTWILL
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BARUERI, SP, BRAZIL PHONE 415/961-2380 PHONE 056 840151
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NEW ZEALAND
DENMARK PROFESSIONAL
ISRAEL TAIWAN
MER-EL AlS ELECTRONICS LTD.
VED KLAEDEBO 18 VECTRONICS LTD. PO BOX 3,.,43 SEA UNION
DK-2970 HORESHOLM 60 MEDINAT HAYEHUDIM ST. 22A MILFORD ROAD PO BOX 45-95 TAl PEl
DENMARK PO BOX 2024 MILFORD, AUCKLAND 9 ROOM 303, HUA-NAN BLDG.
PHONE 02/57 10 00 HERZLlA B 46120, ISRAEL NEW ZEALAND NO. 162, CHANG AN EAST RD.,
TLX 855-37360 MEREL DK PHONE 052-556070 PHONE 46 94 50 2ND SEC.
TLX 342579 VECO TLX 791-21984 PROTON TAIPEI, TAIWAN, REP. OF CHINA
PHONE 751-2063 OR 751-6856
FINLAND TLX 24209 SEAUNION TAIPEI
YLEISELEKTRONIIKKAlOY ITALY NORWAY
LUOMANNOTKO 6 ELEDRA SPA HEFRO TEKSNISK AlS
UNITED KINGDOM
0220 ESPOO 20 VIALE EL VEZIA, 18 POST BOKS 6596
FINLAND 20154 MILANO, ITALY RODEZOKKEN MICROCALL LTD.
PHONE 90-452-1255 PHONE (2) 349751 TRONDHEIMVEIER 80 THAME PARK ROAD
TLX 123212 YLEOY SF TLX 843/332332 ELEDRA I OSLO 5, NORWAY THAME, OXON OX9 3XD
PHONE 30 02 86 ENGLAND
TLX 856-76205 HEFRO N PHONE 084-421-4505
FRANCE JAPAN TLX 83 7457 MEMEC G
VALDIX TOKYO ELECTRON LTD.
SINGAPORE
ZA DES GODETS CE NO: 426 38 FL SHINJUKU NOMURA
ROHM ELECTRONICS PTE. LTD. ALL OTHER COUNTRIES
91374 VERRIERES LE BUISSON BLDG.
FRANCE 1-26-2 NISHI-SHINJUKU 140 BAYA LEBAR RD. (CALL EXAR DIRECT)
PHONE 16/920-2606 SHINJUKU-KU TOKYO 160 #06-01103, A-Z BLDG.
TLX 690312 ALDIX F JAPAN SINGAPORE 1440
PHONE 65-745-9342 REGIONAL SALES OFFICES
PHONE 03-343-4411
GERMANY (WEST) TLX 781/2322240 LABTEL J TLX 786-26648 ROHMS EXAR CORPORATION - Europe
ZILOG HOUSE
ROHM ELECTRONICS GMBH
SOUTH AFRICA MOORBRIDGE ROAD
D-4051 KORSCHENBROICH KOREA MA!DE!'lHE,l''o, BERKS.,
rv1UEHLENSTRASSE 70 SOUTH CONTINENTAL
HANARO CORPORATION DEVICES ENGLAND
WEST GERMANY
RM. 601, HANAM BLDG. RANDOVER HSE, SUITE 516 44-628-783066
PHONE 02161/61010-1
TLX 841/852330 ROHM 0 44-27 YOIDO-DONG, COR HENDRIK VERWOERD,
YOUNGDEUNGPO-KU EXAR CORPORATION -
DOVER RD.
SEOUL 150, KOREA Corporate Headquarters
RANDBURG, TRANSVALL
PHONE 02/784-1144 SO. AFRICA 750 PALOMAR AVENUE
TLX K26878 HANARO PHONE 48 05 15 SUNNYVALE, CA 94086
FAX 02/784-0157 TLX 960 4-24849 SA 408/732-7970
TWX 910-339-9733
FAX 408-737-1635

14-4
IDAHO IOWA MARSHALL ELECTRONICS NEW HAMPSHIRE
(SEE WASHINGTON) BELL INDUSTRIES ONE WILSHIRE ROAD (SEE MASSACHUSETTS)
1221 PARK PLACE, NE BURLINGTON, MA 01803
CEDAR RAPIDS, IA 52402 617/272-8200
ILLINOIS
319/395-0730 NEW JERSEY
DIPLOMAT ELECTRONICS RC COMPONENTS DIPLOMAT ELECTRONICS
1071 JUDSON STREET DEECO, INC. 222 ANDOVER STREET 490 S. RIVER VIEW DR.
BENSENVILLE, IL 60160 2500 16TH AVE., SW WILMINGTON, MA 01887 TOTOWA, NJ 07512
312/595-1000 CEDAR RAPIDS, IA 52406 617/657-4310 2011785-1830
319/365-7551 TWX 710-347-1743
GBL-GOULD TWX 910-525-1331
610 BONNIE LANE GCI/GENERAL COMPONENTS
ELK GROVE VILLAGE, IL 60007 INC.
MICHIGAN
KANSAS 245 D CLiFFTON AVENUE
3121593-3220 MARSHALL ELECTRONICS WEST BERLIN, NJ 08091
MARSHALL ELECTRONICS 31067 SCHOOLCRAFT 6091768-6767
IEC/INTERCOMP 8321 MELROSE DRIVE LIVONIA, MI 48150
2200 STRONGTTON AVE., LENEXA, KS 66214 313/525-5850 MARSHALL ELECTRONICS
STE.210 913/492-3121
101 FAIRFIELD ROAD
HOFFMAN ESTATES, IL 60695 MILGRAY ELE·-:;TLiONIGS RM ELECTRONICS FAIRFIELD, NJ 07006
312/843·2040 4310 R.B. CHAFFEE MEMORIAL 201/882-0320
KENTUCKY
DRIVE
MARSHALL ELECTRONICS (SEE INDIANA) GRAND RAPIDS, MI 49508 MARSHALL ELECTRONICS
1261 WILEY RD., UNIT F 6116/531-9300 158 GAITHER DRIVE
SCHAUMBURG, IL 60195 TWX 810-273-8779 MT. LAUREL, NJ 08054
LOUISIANA
312/490-0155 609/234-9100 (NJ)
(SEE TEXAS) REPTRON ELECTRONICS
REPTRON 34404 GLENDALE ROAD
1000 E. STATE PARK, SUITE K LIVONIA, MI 48150 NEW MEXICO
MAINE
SCHAUMBURG, IL 60195 313/525-2700 BELL INDUSTRIES
312/882-1700 (SEE MASSACHUSETTS) 11728 LINN, NE
MINNESOTA ALBUQUERQUE, NM 87123
RM ELECTRONICS 505/292-2700
MARYLAND DIPLOMAT ELECTRONICS
180 CROSSEN TWX 910-989-0625
ELK GROVE VILLAGE, IL 60007 DIPLOMAT ELECTRONICS 14920 29TH AVENUE, NO.
312/932-5150 9150 RUMSEY RD., STE. A-6 PLYMOUTH, MN 55441
BETATRON
TWX 910·651-3245 COLUMBIA, MD 21045 612/559-2500
2825 B BROADBEND PKWY., NE
301/995-1226 ALBUQUERQUE, NM 87123
MARSHALL ELECTRONICS
INDIANA 505/344-2318
MARSHALL ELECTRONICS 3800 ANNAPOLIS LANE
ALTEX 8445 HELGERMAN COURT PLYMOUTH, MN 55441
12774 N. MERIDIAN GAITHERSBURG, MD 20877 612/559-2211 NEW YORK
CARMEL, IN 46032 301/840-9450 DIPLOMAT ELECTRONICS
317/848-1323 MERIT ELECTRONICS
4610 WETZEL ROAD
TWX 810-341-3481 PIONEER ELECTRONICS 2525 NEVADA AVE., STE. 210
LIVERPOOL, NY 13088
9100 GAITHER ROAD MINNEAPOLIS, MN 55427
315/652-5000
BELL/GRAHAM ELECTRONICS GAITHERSBURG, MD 20877 6121546-5383
133 S. PENNSYLVANIA 301/921-0660 DIPLOMAT ELECTRONICS
INDIANAPOLIS, IN 46204 TWX 710-828-0545 110 MARCUS DRIVE
MISSISSIPPI
317/634·8202 MELVILLE, NY 11747
TWX 810-341-3481 (SEE ALABAMA)
MASSACHUSETTS 516/454-6400

BELL/GRAHAM ELECTRONICS ALMO ELECTRONICS JACO

MISSOURI
3433 E. WASHINGTON BLVD. 60 SHAWMUT ROAD 145 OSER AVENUE
CANTON, MA 02021 OLIVE ELECTRONICS
FT. WAYNE, IN 46801 HAUPPAUGE, NY 11787
617/821-1450 9910 PAGE BOULEVARD
219/~23·3422 516/2734-5500
ST. LOUIS, MO 63132
TWX 810-332·1562 DIPLOMAT ELECTRONICS TWX 510-227-6232
314/426-4500
28 COMMING PARK TWX 910-763-0720
WOBURN, MA 01801 MARSHALL ELECTRONICS
MARSHALL ELECTRONICS 617/935-6611 129 BROWN ST.
6990 CORPORATE DRIVE MONTANA JOHNSON CITY, NY 13790
INDIANAPOL!S, !N "6278 GERBER 6071798-1611
(CALL EXAR DIRECT)
317/297-0483 128 CARNEGIE ROW
NORWOOD, MA 02061
RM ELECTRONICS 617/329-2400 NEBRASKA
7031 CORPORATE CIRCLE DR. TWX 710-336-1987 (SEE MISSOURI)
INDIANAPOLIS, IN 46278
317/291-7110
NEVADA
(SEE CALIFORNIA)

14-6
L.A. VARAH REGIONAL DISTRIBUTION DISTRIBUTION ADDITIONS AS OF 4/1/86 MASSACHUSETTS
504 A IROQUOIS SHORE DRIVE OFFICES BELL INDUSTRIES
OAKVILLE, ONTARIO CALIFORNIA
EXAR CORPORATION 329 WASH'lNGTON ST., 103
CANADA L6H 3K4
1787 VETERANS MEMORIAL BELL INDUSTRIES WOBURN, MA 01801
416/842-8484
TWX 06-982397
HWY. 12322 MONARCH STREET 617/932-0577
CENTRAL ISLIP, NY 11772 GARDEN GROVE, CA 92641
L.A. VARAH 516/582-8983 714/220-0681 MICHIGAN
1-1832 KING EDWARD ST. TWX 910-596·2362 BELL/GRAHAM ELECTRONICS
WINNEPEG, MANITOBA 814 PHOENIX DRIVE
EXAR CORPORATION -
CANADA R2R ON1 Corporate Headquarters BELL INDUSTRIES ANN ARBOR, MI 48104
204/633-6190 750 PALOMAR AVENUE 11812 SAN VINCENTE BLVD., 300 313/971-9093
SUNNYVALE, CA 94086 LOS ANGELES, CA 90049
L.A. VARAH 213/826·6778
4081732-7970 PREHLER ELECTRONICS
6420 6A STREET SE TWX 910-339-9233
CALGARY, ALBERTA 20770 ORCHARD LAKE ROAD
FAX 408-737-1635 BELL INDUSTRIES FARMINGTON HILLS, MI 48024
CANADA T2H 2B7 306 EAST ALONDRA BLVD.
403/255-9550 313/473-7200
GARDENA, CA 90247 800/336-1406TOLL FREE
213/515-1800 800/321-5982 OUTSIDE MI
L.A. VARAH TWX 910-346-6336
2077 ALBERTA ST.
VANCOUVER OHIO
BELL INDUSTRIES
BRITISH COLUMBIA PREHLER ELECTRONICS
1829 A DEHAVILLAND DRIVE
CANADA V5Y 1C4 17991 ENG LEWOOD STREET
THOUSAND OAKS, CA 91320
604/873-3211 MIDDLEBURG HEIGHTS, OH 441:
805/499-6821
TWX 910-321-3799 216/243-5510
R.A.E. INDUSTRIAL 800/824-9319 TOLL FREE
ELECTRONICS 800/321-0178 OUTSI DE OH
3455 GARDNER CT. DIPLOMAT
BURNABY, B.C. 9787 AERO DR IVE
SAN DIEGO, CA 92123 TENNESSEE
CANADA V5G 4J7
604/291-8866 619/292·5693 BELL/GRAHAM ELECTRONICS
TLX 0435653 230 GREAT CIRCLE RD., STE. 12,
GEORGIA NASHVILLE, TN 37228
R.A.E. INDUSTRIAL 615/242-2682
PREHLER ELECTRONICS
ELECTRONICS
4400-C BANKERS CIRCLE
11680 - 170 STREET TEXAS
EDMONTON, ALBERTA ATLANTA, GA 30360
CANADA T5S 1J7 404/447-5540 BELL INDUSTRIES
403/451-4001 800/241-0940 TOLL FREE 9 HIGHLAND
TLX 0372653 RICHARDSON, TX 95081
BELL/GRAHAM ELECTRONICS 214/744-2510
R.A.E. 6690 JONES MILL CT., UNIT C
501-45A STREET EAST NORCROSS, GA 30092 WASHINGTON
SASKATOON, SASKATECHEWAN 404/662-0923 DIPLOMAT
CANADA S7K OW6 541 INDUSTRY
306/933-2888 FLORIDA SEATTLE, WA 98188
TLX 0742825 BELL/GRAHAM ELECTRONICS
10810 72nd ST., N., STE. 201
R.A.E. LARGO, FL 33541
760 CENTURY STREET 813/541·4434
WINNIPEG, MANITOBA,
CANADA R3H OM1 ILLINOIS
2041786-8401
BELL INDUSTRIES
TLX 0757622
515 BUSSE AVENUE
R.A.E. ELK GROVE VILLAGE, IL 60007
500 NOR FINCH DRIVE 312/640-1910
DOWNSVIEW, ONTARIO TWX 910·223·4519
CANADA M3N 1Y4
4161736-1588 PREHLER ELECTRONICS
TLX 06527405 2300 N. KILBOURN AVE.
CHICAGO, IL 50539
R.A.E. 312/384,6100
15 MT. ROYAL BLVD. 800/621-4177 TOLL FREE
MONCTON, NEW BRUNSWICK
CANADA E1E 2T9 INDIANA
506/855-2200 BELL/GRAHAM ELECTRONICS
TLX 0142889 408 NORTH STREET
LAFAYETTE, IN 47902
R.A.E. 317/423-5564
#103 - 11 MORRIS DR.
DARTMOUTH, NOVA SCOTIA
PREHLER ELECTRONICS
CANADA jM2
6060 CASTLEWA Y WEST
9021465-2350
INDIANAPOLIS, IN 46250
TLX 01931563
317/841·0018