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Ece282 Labsheet 3

The document describes a digital electronics lab experiment on synthesizing logic circuits. The objectives are to design logic circuits based on given specifications and implement them in Tinkercad. Two examples are given: 1) Designing a circuit with 3 inputs (x1, x2, s) that selects the output as x1 if s=0 and x2 if s=1. 2) Designing a circuit with 3 inputs (X1, X2, X3) that outputs 1 if the decimal value of inputs is less than 1, and 0 otherwise. The reduced sum-of-products and product-of-sums expressions are derived and implemented for each case.

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51 views14 pages

Ece282 Labsheet 3

The document describes a digital electronics lab experiment on synthesizing logic circuits. The objectives are to design logic circuits based on given specifications and implement them in Tinkercad. Two examples are given: 1) Designing a circuit with 3 inputs (x1, x2, s) that selects the output as x1 if s=0 and x2 if s=1. 2) Designing a circuit with 3 inputs (X1, X2, X3) that outputs 1 if the decimal value of inputs is less than 1, and 0 otherwise. The reduced sum-of-products and product-of-sums expressions are derived and implemented for each case.

Uploaded by

Madhav S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Akella Madhav

AM.EN.U4ECE20006
19ECE282 Digital Electronics and Systems Lab

Lab sheet 3: Synthesis of Logic circuit

Date: 15-09-21
Objectives
1. To synthesize a logic circuit using the given specifications.

Theory
Logic circuits provide a solution to a problem; by implementing functions that are needed to carry
out specific tasks. Logic circuits provide complete capability for execution of programs and
processing of data. Such circuits are complex and difficult to design. But regardless of the
complexity of a given circuit, a designer of logic circuits is always confronted with the same basic
issues. First it is necessary to specify the desired behavior of the circuit. Second, the circuit has to
be synthesized and implemented. Finally, the implemented circuit has to be tested to verify that it
meets the specifications.
The desired behavior is often initially described in words, which then must be turned into a
formal specification.

Lab Experiments:

1) In computer systems it is often necessary to choose data from exactly one of a number of possible
sources. Suppose that there are two sources of data, provided as input signals x1 and x2. The values
of these signals change in time, perhaps at regular intervals. Thus sequences of 0s and 1s are
applied on each of the inputs x1 and x2. Design the simplest sum-of-products circuit that produces
an output that has the same value as either x1 or x2, dependent on the value of a selection control
signal s. Therefore, the circuit should have three inputs: x1, x2, and s. Assume that the output of
the circuit will be the same as the value of input x1 if s = 0, and it will be the same as x2 if s =1.
Implement a circuit for the case in Tinkercad.

f = 𝒔̅ 𝒙𝟏 + 𝒔𝒙𝟐

Truth Table:
s 𝑥1 𝑥2 f
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Case 1:

s = 0; x1 = 0; x2 = 0

s = 0; x1 = 0; x2 = 1
s = 0; x1 = 1; x2 = 0

s = 0; x1 = 1; x2 = 1
Case 2:

s = 1; x1 = 0; x2 = 0

s = 1; x1 = 0; x2 = 1
s = 1; x1 = 1; x2 = 0

s = 1; x1 = 1; x2 = 1
2) Create the truth table for a logic function (a function of 3 variables) which works as:
function takes a value 1 when the decimal equivalent value of the combination of
3 input variables is less and takes a value 0 otherwise. Create the reduced SOP
function for the case and implement it in Tinker cad.

Truth table

X1 X2 X3 Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

Reduced SOP Function = f: (x1)’(x2)’ + (x3)’(x1)’

CASE 1:
CASE 2:

CASE 3:
CASE 4:

CASE 5:
CASE 6:

CASE 7:
CASE 8:

3) Create the reduced POS function for the case given in Problem 2 and implement
that using Tinker cad.

X1 X2 X3 Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

Reduced POS Function = f: (x1)’(x3)’


CASE 1:

CASE 2:
CASE 3:

CASE 4:

Signature of the faculty:


Date:
.
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