Assignment no.

2
QUESTION NO.1:

Design a

i. 4x1 Mux
ii. 1x8 DMUX
iii. 3X8 Decoder
iv. 8x3 Encoder
v. 2x4 decoder

ANSWER:

1. 4x1 Mux (Multiplexer)

A 4x1 Mux has 4 data inputs and 1 output. It uses 2 selection lines (S1 and
S0) to choose between the inputs.

Truth Table:

S S Input Input Input Input Outp

1 0 0 1 2 3 ut
0 0 D0 X X X D0
0 1 X D1 X X D1
1 0 X X D2 X D2
1 1 X X X D3 D3

Logic Equation:

Output=(S1′⋅S0′⋅D0)+(S1′⋅S0⋅D1)+(S1⋅S0′⋅D2)+(S1⋅S0⋅D3)\text{Output}
= (S1' \cdot S0' \cdot D0) + (S1' \cdot S0 \cdot D1) + (S1 \cdot S0' \cdot
D2) + (S1 \cdot S0 \cdot D3)Output=(S1′⋅S0′⋅D0)+(S1′⋅S0⋅D1)+
(S1⋅S0′⋅D2)+(S1⋅S0⋅D3)

Where:

 S1' and S0' are the negations of S1 and S0, respectively.

2. 1x8 DMUX (Demultiplexer)

A 1x8 DMUX takes a single input and routes it to one of the 8 output lines,
based on the 3 selection lines (S2, S1, S0).

Truth Table:
 In
SSS Out Out Out Out Out Out Out Out
pu
210 put0 put1 put2 put3 put4 put5 put6 put7
t
0 0 0 D D X X X X X X X
0 0 1 D X D X X X X X X
0 1 0 D X X D X X X X X
0 1 1 D X X X D X X X X
1 0 0 D X X X X D X X X
1 0 1 D X X X X X D X X
1 1 0 D X X X X X X D X
1 1 1 D X X X X X X X D

3. 3x8 Decoder

A 3x8 Decoder takes 3 binary inputs (A2, A1, A0) and generates 8 outputs,
with only one output active at a time based on the input combination.

Truth Table:

A A A Out Out Out Out Out Out Out Out

2 1 0 put0 put1 put2 put3 put4 put5 put6 put7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

4. 8x3 Encoder

An 8x3 Encoder converts 8 inputs into a 3-bit binary code. The highest
priority input generates the corresponding binary output.

Truth Table:

Inp Inp Inp Inp Inp Inp Inp Inp A A A

ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 2 1 0
1 X X X X X X X 1 1 1
X 1 X X X X X X 1 1 0
X X 1 X X X X X 1 0 1
X X X 1 X X X X 1 0 0
X X X X 1 X X X 0 1 1
 X X X X X 1 X X 0 1 0
X X X X X X 1 X 0 0 1
X X X X X X X 1 0 0 0

Where "X" represents a don't-care condition.

5. 2x4 Decoder

A 2x4 Decoder takes 2 inputs (A1, A0) and generates 4 outputs. Only one
output is active at a time.

Truth Table:

Output Output Output Output

A1 A0
0 1 2 3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

These designs provide the basic truth tables and logic equations for each
of the components requested. The next step would be to implement these
designs using logic gates or programmable devices like FPGAs or
microcontrollers, depending on the target application.

QUESTION NO.2:

Design

i. a Half Adder
ii. a Half Subtractor
iii. a Full Adder
iv. a Full Subtractor
v. a comparator

ANSWER:

1. Half Adder

A Half Adder adds two binary digits and provides two outputs: the sum and the carry.
Truth Table:

Su Carr
A B
m y
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic Equations:

 Sum = A ⊕ B (XOR Gate)

 Carry = A ⋅ B (AND Gate)

2. Half Subtractor

A Half Subtractor subtracts two binary digits and provides two outputs: the difference and
the borrow.

Truth Table:

Differen Borro
A B
ce w
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Equations:

 Difference = A ⊕ B (XOR Gate)

 Borrow = A' ⋅ B (AND Gate, where A' is the negation of A)

3. Full Adder

A Full Adder adds three binary digits (two inputs and a carry-in) and provides two outputs:
the sum and the carry-out.

Truth Table:

Su Cou
A B Cin
m t
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic Equations:

 Sum = A ⊕ B ⊕ Cin
 Carry-out (Cout) = (A ⋅ B) + (B ⋅ Cin) + (A ⋅ Cin)

4. Full Subtractor

A Full Subtractor subtracts three binary digits (two inputs and a borrow-in) and provides
two outputs: the difference and the borrow-out.

Truth Table:

Differen Bou
A B Bin
ce t
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Logic Equations:

 Difference = A ⊕ B ⊕ Bin
 Borrow-out (Bout) = (A' ⋅ B) + (Bin ⋅ (A' ⊕ B))

5. Comparator (2-bit comparator)

A Comparator compares two binary numbers and outputs whether they are equal, greater,
or less. Here, let's design a 2-bit comparator.

Truth Table:

A> A< A=
A1 A0 B1 B0
B B B
 0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1

Logic Equations:

 A > B = (A1 ⋅ B1') + (A1' ⋅ A0 ⋅ B0')

 A < B = (A1' ⋅ B1) + (A0' ⋅ A1 ⋅ B1')
 A = B = (A1 ⋅ B1) ⋅ (A0 ⋅ B0)

These designs provide the truth tables and logic equations for each of the components
requested. You can implement these using basic gates (AND, OR, XOR, NOT) to build the
corresponding circuits.

QUESTION NO.3:

From the truth table write the SOP and POS expressions and draw the logic circuits
I.
A B C OUTPUT=X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
II
B OUTPUT=F
A

0 0 1
0 1 1
1 0 0
1 1 0

ANSWER:

Expression for SOP (Sum of Products) and POS (Product

of Sums) from the Truth Table

Let's break this into two parts based on the given truth tables:

I. First Truth Table: Output = X

Output
A B C
(X)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

1. SOP Expression (Sum of Products):

The SOP expression is formed by identifying the rows where the output is
1. In this case, rows 6 and 8 have an output of 1.

 Row 6 (A = 1, B = 0, C = 1): The product term will be A ⋅ B' ⋅ C.

 Row 8 (A = 1, B = 1, C = 1): The product term will be A ⋅ B ⋅ C.

Therefore, the SOP expression is:

X=A⋅B′⋅C+A⋅B⋅CX = A \cdot B' \cdot C + A \cdot B \cdot C

2. POS Expression (Product of Sums):

The POS expression is formed by identifying the rows where the output is
0. These rows are:

 Row 1 (A = 0, B = 0, C = 0): The sum term will be A + B + C.

 Row 2 (A = 0, B = 0, C = 1): The sum term will be A + B + C'.
 Row 3 (A = 0, B = 1, C = 0): The sum term will be A + B' + C.
 Row 4 (A = 0, B = 1, C = 1): The sum term will be A + B' + C'.
 Row 5 (A = 1, B = 0, C = 0): The sum term will be A' + B + C.
 Row 7 (A = 1, B = 1, C = 0): The sum term will be A' + B' + C.

Therefore, the POS expression is:

X=(A+B+C)⋅(A+B+C′)⋅(A+B′+C)⋅(A+B′+C′)⋅(A′+B+C)⋅(A′+B′+C)X = (A +
B + C) \cdot (A + B + C') \cdot (A + B' + C) \cdot (A + B' + C') \cdot (A'
+ B + C) \cdot (A' + B' + C)

Logic Circuit for SOP Expression:

o A⋅B′⋅CA \cdot B' \cdot C

 Use AND gates to generate the product terms:

o A⋅B⋅CA \cdot B \cdot C

 Use an OR gate to combine these two product terms to generate the
final output.

The SOP logic circuit will look like:

A ──────────────┐
│
AND ──────┐
B ─── NOT ──────┘ │
OR ─── X (Output)
C ──────────────┐ │
AND ──────┘
A ──────────────┘
B ──────────────┐
C ──────────────┘
II. Second Truth Table: Output = F

Output
A B
(F)
0 0 1
0 1 0
1 1 1
0 0 1
1 0 1

1. SOP Expression (Sum of Products):

From the truth table, the output is 1 for rows 1, 3, 4, and 5. We will write
the product terms for these rows.

 Row 1 (A = 0, B = 0): The product term is A' ⋅ B'.

 Row 3 (A = 1, B = 1): The product term is A ⋅ B.
 Row 4 (A = 0, B = 0): This row is repeated, so it doesn’t affect the
expression.
 Row 5 (A = 1, B = 0): The product term is A ⋅ B'.

Therefore, the SOP expression is:

F=A′⋅B′+A⋅B+A⋅B′F = A' \cdot B' + A \cdot B + A \cdot B'

2. POS Expression (Product of Sums):

From the truth table, the output is 0 for row 2. So we form the sum term
for this row.

 Row 2 (A = 0, B = 1): The sum term is A + B'.

Therefore, the POS expression is:

F=(A+B′)F = (A + B')

Logic Circuit for SOP Expression:

o A′⋅B′A' \cdot B'

 Use AND gates to generate the product terms:

o A⋅BA \cdot B
o A⋅B′A \cdot B'
 Use an OR gate to combine these three product terms to generate
the final output.
The SOP logic circuit will look like:

A ─── NOT ──────┐

│
AND ──────┐
B ─── NOT ──────┘ │
OR ─── F (Output)
A ──────────────┐ │
B ──────────────┘ │
AND ──────┘
A ──────────────┐
B ──────────────┘

Summary of Expressions:

a. SOP: X=A⋅B′⋅C+A⋅B⋅CX = A \cdot B' \cdot C + A \cdot B \cdot

1. First Truth Table (X):

C
b. POS: X=(A+B+C)⋅(A+B+C′)⋅(A+B′+C)⋅(A+B′+C′)⋅(A′
+B+C)⋅(A′+B′+C)X = (A + B + C) \cdot (A + B + C') \cdot (A
+ B' + C) \cdot (A + B' + C') \cdot (A' + B + C) \cdot (A' + B'
+ C)

a. SOP: F=A′⋅B′+A⋅B+A⋅B′F = A' \cdot B' + A \cdot B + A \cdot

2. Second Truth Table (F):

B'
b. POS: F=(A+B′)F = (A + B')

These expressions correspond to the respective truth tables and their

corresponding logic circuits.