LABORATORY WORK REPORT

Question 1a

1.0. INTRODUCTION

The combinational Logic circuit is the circuit which its output depends only on the input of the
circuit. Any change of the input means change in the output.
2.0 DESIGN THEORY
Since the circuit is combinational, the truth table can be used to realize its circuit and a K-map is
used to minimize each output of the circuit. From the given information, the J input is the control
signal of which when it is TRUE i.e. equals 1 and the input is converted to its equivalent code II
as indicated on the lab question. When the control signal J is FALSE i.e. equals 0 then inputs are
converted to its equivalent code III.

2.1. TRUTH TABLE

The truth table consists of five inputs J, A, B, C and D with four outputs W, X, Y and Z.

INPUT OUTPUT
J A B C D W X Y Z
MINTERM
0 0 0 0 0 0 d d d d
1 0 0 0 0 1 0 0 1 1
2 0 0 0 1 0 0 1 0 0
3 0 0 0 1 1 d d d d
4 0 0 1 0 0 0 1 0 1
5 0 0 1 0 1 d d d d
6 0 0 1 1 0 d d d d
7 0 0 1 1 1 d d d d
8 0 1 0 0 0 0 1 1 0
9 0 1 0 0 1 0 1 1 1
10 0 1 0 1 0 1 0 0 0
11 0 1 0 1 1 d d d d
12 0 1 1 0 0 1 0 0 1
13 0 1 1 0 1 1 0 1 0
14 0 1 1 1 0 1 0 1 1
15 0 1 1 1 1 1 1 0 0
16 1 0 0 0 0 d d d d
17 1 0 0 0 1 0 0 0 0
18 1 0 0 1 0 0 0 0 1

1
 19 1 0 0 1 1 d d d d
20 1 0 1 0 0 0 0 1 0
21 1 0 1 0 1 d d d d
22 1 0 1 1 0 d d d d
23 1 0 1 1 1 d d d d
24 1 1 0 0 0 0 0 1 1
25 1 1 0 0 1 0 1 0 0
26 1 1 0 1 0 0 1 0 1
27 1 1 0 1 1 d d d d
28 1 1 1 0 0 0 1 1 0
29 1 1 1 0 1 0 1 1 1
30 1 1 1 1 0 1 0 0 0
31 1 1 1 1 1 1 0 0 1

2.2. K-MAP MINIMIZATION

The minimization and simplification is done through the use of five variables K-map, and we
consider the Product of Sum (POS) and the Sum of Product (SOP) format.

i. For the output W

000 001 011 010 100 101 111 110

BCD BCD

JA JA
00 d 0 d 0 00 0 d d d

01 1 1 1 1
0 0 d 1
01 11 0 0 1 1
11 0 0 d 0
10 0 d d d
10 d 0 d 0

2
From the K- Map:

SOP expression can be obtained by considering all 1s and don’t cares, and the following
simplified expression was obtained.
W = J’AB + BC + J’AC
The total number of gates is five.
POS expression can be obtained by considering all Os and the don’t cares, and the following
simplified expression was obtained.
W = A (J’+A’+C) (A’+B+C) (J’+D+B’)

ii. For the output X

000 001 011 010 100 101 111 110

BCD BCD
JA JA
d 0 d 1 1 d d d
00 00
1 1 d 0 0 0 1 0
01 01
0 1 d 1 1 1 0 0
11 11
d 0 d 0 0 d d d
10 10

From the K- Map:

3
SOP gives the following value:
Collecting all 1s and don’t cares the following simplified expression.
X = J’A’D’ +AB’D + J’CD+JAB’C’+JABC’+JAB’CD’
The total number of gates is twelve.

POS
Collecting all the Os and the don’t cares to obtain a simplified expression
X = (A+D’) (J+A’+B’+C) (J+A’+D+C’) (J’+A) (J’+B+D+C) (J’+A’+B’+C’)
The total number of gates is twelve.

iii. For the output Y

000 001 011 010 100 101 111 110

BCD BCD
JA JA
d 1 d 0 0 d d d
00 00
1 1 d 0 0 1 0 1
01 01
1 0 d 0 1 1 0 0
11 11
d 0 d 0 1 d d d
SOP
10 10
Collecting all 1s
and don’t cares the following simplified expression.
Y = J’C’D + JBC’ + J’BCD’+AB’C’D’ (a total of nine gates)
POS
Collecting all the Os and the don’t cares to obtain a simplified expression

4
Y= (C’+D’) (J + B’+C + D) (J’+C’) (J’+B+C+D’) (B+C’)
The total number of gates is ten.

iv. The output Z

000 001 011 010 100 101 111 110

BCD BCD
JA JA
d 1 d 0 1 d d d
00 00
0 1 d 0 1 0 0 1
01 01
1 0 d 1 0 1 1 0
11 11
d 0 d 1 0 d d d
10 10

SOP
Z = JB’CD’ + JBD + JAB’D’+J’B’D + J’BD’
The total number of eight gates are going to be used to implement the
POS
Collecting all the Os and the don’t cares to obtain a simplified expression
Z= (J + B’ + D’) (J+A’ + B+ D) (J+B + C’+ D) (J’ + B + D’) (J’ + B’ + D)
A total number of eleven gates are going to be used.

3.0. CIRCUIT AND SIMULATION

3.1. Circuit
With accordance to the above simplification, designs which favor a small number of gates have
been considered. And therefore, for implementing, SOP format is going to be used, for X a POS
format is considered despite of having the same number of gates but have less number of inputs
compared with the SOP format, for Y a SOP format is going to be used and a SOP is used.

5
 KPD1
A
43 21

V1
0V A B C D

W W

output

X
X
4 321

Y Y

Z Z

6
3.2. Waveform
After simulating the following waveforms were thus obtained as shown below.

1560 1570 1580 1590 1600 1610

W

4.0 CONCLUSION
From the analysis above it can be observed that using different format representation (POS and
SOP) can result into reducing the number of gates used on the chip and input to the chip as well
and therefore minimizing cost and delay due to the large number of gates in the circuit.

Question 1b

7
1.0. INTRODUCTION

Encoder is the digital function that produces a reserve operation from that of a decoder.
An encoder has 2n inputs and n output lines. The output lines generate the binary code for 2n
input variables. The encoder assumes that only a single input is 1 at a time. The encoder is the
combinational circuit since the output depends directly from the input and the truth table is used
to realize the circuit of it.

2.0. DESIGN THEORY

The encoder as explained above in this case is the octal decoder which consist of 8 input lines
(equivalent to 2n and thus n=3) of which only one line is assumed high and consist of 3 output
lines that generates the corresponding input binary number.

2.1 TRUTH TABLE

Note that the circuit has 8 inputs and could have 28=256 possible input combination but only 8
of these 256 inputs has any meaning and the other input are the don’t care condition. That is why
only 8 inputs are considered with 3 output lines generating these eight inputs.
Therefore the below is the truth table of the 8 by 3 encoder (associating only 8 inputs with any
meaning) where A7 (most significant bit) through A0 (list significant bit) are the input and B2
(MSB) through B0 (LSB) are the output lines.

INPUTS OUTPUTS
A7 A6 A5 A4 A3 A2 A1 A0 B2 B1 B0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

2.2. Minimization and simplifications

After the truth table, the following results obtained after simplification using the SOP format
where the output is the function of the inputs.
B2 = A3 + A2 + A1 + A0
B1 = A5 + A4 + A1 + A0
B0 = A6 + A4 + A2 + A0

8
3.0 CIRCUIT AND SIMULATION

3.1 The circuit diagram

The circuit below was thus drawn from the simplified equations above using the circuit maker
software. The data sequence generates the inputs to the circuit. This data sequence is triggered by
the clock as shown on the circuit.

B0
U1A DISP1

DS1
Data 8
Seq 7 4321
6 U1B B1
5
V1 4
3
CP1 Q1 CP1 2
CP2 Q2 CP2 1
U2A B2

3.2. Waveform
After simulating the above circuit, the following were the waveform developed.

1620 1630 1640 1650 1660 1670 1680

B0
B1
B2

4.0 CONCLUSION
As spotted above, there are 8 inputs therefore 256 input combinations were expected.
However the situation is not the case since out of all these 256 only 8 inputs has any meaning
and thus they are only considered while remaining are treated as don’t care condition.
Encoders of this type however are not available in IC packages, since they can be easily
constructed with the OR gates. The encoder available in IC form is called the priority encoder.

9
Question 1c. Design of an 8X1 multiplexer

1.0 INTRODUCTION
A digital multiplexer is the combinational logical circuit that selects binary information from one
of many input lines and directs it to a single output line. The selection of an input line is done by
a set of selection lines also known as control lines. There are normally 2n input lines and n select
lines (of which its combination determines which input to output i.e. selected).

2.0. DESIGN THEORY

An 8x1 multiplexer is the digital circuit with the eight input lines (23) and thus 3 selection lines
to identify which input among the eight has been selected.

10
2.1. Truth table
The following bellow is the truth table realizing the multiplexer with eight inputs lines and a
single output line. A, B, and C are the selector.
INPUT OUTPU
T
A B C F
0 0 0 I1
0 0 1 I2
0 1 0 I3
0 1 1 I4
1 0 0 I5
1 0 1 I6
1 1 0 I7
1 1 1 I8

2.2. Minimization and simplification

From the table above the following simplification were thus obtained
F = A’B’C’ I0+ A’B’CI1 + A’BC’ I2 + A’BC I3 + AB’C’ I4 + AB’CI5 + ABC’I6 + ABCI7
3.0. CIRCUIT AND SIMULATION
3.1. The circuit diagram
The circuit diagram below is a result the logic function obtain above after minimizing the
information from the truth table and the circuit thus drawn using the circuit maker software. The
selector inputs as well as the eight input data to the circuit are generated by the data sequencer of
which is triggered by the clock as shown on the circuit below.

11
 DS2
V1
Data 8
CP1 Q1 Seq 7
CP2 Q2 6
5
4
3
CP1 2
CP2 1
DS1
Data 8 U7C U7B U7A
Seq 7
6
5 U1A
4
3
CP1 2
CP2 1
U1B

U2A U5A DISP1

U2B F 4321
U6A

U3A

U3B
U5B

U4A

U4B

3.2. Simulation and Wave Forms

From the same circuit maker then the wave forms of the developed circuit after simulating was
then obtained as shown on the wave forms that follow.

700 710 720 730 740 750

F

4.0. CONCLUSION

12
From the waveform there are glitches (the point where the wave goes high and back to low
immediately) observed which are resulted from the internal delays of the gates, longer circuit
wire and other related contributed factors. Multiplexer found itself very useful MSI function and
has a multitude of applications. It is used for connecting two or more sources to a single
destination among computer units and useful in constructing a common bus system.

Question 1d.
1. INTRODUCTION

A decoder is a combinational logic device which converts binary information from n input lines
to a maximum of 2n unique output lines. It is a combinational device since the output depends
direct from the input i.e. any change done on the input will also affect the output.If the n-1
decoded information has unused or don’t care combinations, the decoder output will have less
than 2n outputs.

2. DESIGN THEORY

During designing of 5X32 decoder i.e. 5 input lines with 32 output lines, four 3X8 decoders are
therefore used making a total of 32 outputs with three inputs shared among the all four decoders.

13
The remaining two input lines will be used to generate 4 output lines on which each of these four
lines will be used as an enable signal to the four decoders (3X8).

Therefore for designing simplicity, two circuits are developed one for 3X8 decoder and the
remaining one for 3X8 decoder. And the overall 5X32 decoder resulted by integrating the four
3X8 decoder and one 2X4 decoder in a block diagram.

i. For 3x8 decoder

The decoder receives three lines and produces eight lines on which among them is selected as an
output. On this decoder an enable signal is then also associated.

ii. Truth table

The truth table below assumes the following: A is the MSB and C the LSB of the inputs while D7
is the MSB and D0 is the LSB of the outputs

A B C D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Minimization and simplifications

D7 = A’B’C’ D4 = A’BC D1 = ABC’

D6 = A’B’C D3 = AB’C’ D0 = ABC

D5 = A’BC’ D2 = AB’C

iii. 3x8 Decoder circuit

14
 iv. 2X4 decoder

The decoder receives two lines and produces four lines on which among them is selected as an
output. On this decoder signal an enable signal is not associated.

INPUTS OUTPUTS 3. Truth table

A B D3 D2 D1 D0
0 0 1 0 0 0 The truth table below assumes the following: A is the
0 1 0 1 0 0 MSB and C the LSB of the inputs while D7 is the MSB
1 0 0 0 1 0
1 1 0 0 0 1 and D0 is the LSB of the outputs

The outputs are: D3 = A’B’ D2 = AB’ D1 = AB’ D0 = AB

The circuit for 2X4 decoder is as follows

15
 U2B U2A

U1A

U1B

U1C

U1D

4. Circuit diagram

From the given two design a 5 by 32 decoder can be designed using four 3 by 8 decoders and 0ne
2 by 4 decoder as described above. The designed diagram in block diagram is as shown below
showing all the 32 outputs and the 5 inputs.

16
 DataGen
Data 8
Seq 7
6
5
4
3
CP1 2
CP2 1

CLK U5C U5B U5A

CP1 Q1 U1A 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
CP2 Q2 D31

U1B
D30
Decoder
4555
1/2
A1 Q3 U2A
A0 Q2 D29
Q1
E Q0

U2B
D28

U3A
D27

U3B
D26

U4A
D25

U4B
D24

U14A
D23

U14B
D22

U15A
D21

U15B
D20

U16A
D19

U16B
D18

U17A
D17

U17B
D16

U22A 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
D15

U22B
D14

U23A
D13

U23B
D12

U24A
D11

U24B
D10

U25A
D9

U25B
D8

U21B
D7

U21A
D6

U20B
D5

U20A
D4

U19B
D3

U19A
D2

U18B
D1

U18A
D0

17
Waveforms after the simulation of above circuit

320 330 340 350 360 370

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31

Question 2a

18
 1. INTRODUCTION
A memory cell is a storage device with the capability of storing a single bit data at a time. This
memory cell can either be a single core memory or flip flop of different types such as JK, SR, D
and T flip flop.

2. DESIGN THEORY
As the memory cell is concern, it can be active or in active. The decision of whether the cell is
active or not active is done through the use of selector signal. However when the cell is active
then it can either be performing writing or reading. The reading and writing operation is mainly
done by the Read/write signal to the system where 1 for the read and 0 for the write.

The circuit behaves purely combinational when during reading the data and sequential when
during writing.

i. During reading

Truth table
R/W Sel Output data

0 0 inactive

0 1 Don’t care

1 0 inactive

1 1 Dout

Minimization and simple circuit

Output = R/WSelDout

U1A

ii. During writing

19
During writing, the select (S) need to be high making the cell active in order to accept the written
data. Apart from that, the write signal also needs to be active to signify writing.

Assume the cell has two state that is state 0 (the previous written data was zero) and state 1 (the
previous written data is 0ne)

a) State diagram

A B

b) State table

Data previous Data to be written

in cell 0 1

A A B

B A B

c) State assignment table

From the table above, let A=0 and B=1 and therefore the following is the state assignment table.

P.S Input data N.S

0 0 0

0 1 1

1 0 0

1 1 1

20
 d) The excitation state and truth table using SR flip flop

P.S Input data N.S S R

(Din)

0 0 0 0 d

0 1 1 1 0

1 0 0 0 1

1 1 1 d 0

Minimization

From the table above, the following have been obtained

S= Din and R= Din’

However, for the data to be written as explained above, then the select signal need to be high and
the R/W signal need to be zero. Therefore, the data input is going to be ended with these to
signals and thus the S and R are thus going to be as follows

S = SelWDin and R = SelWDin’

3. The circuit diagram

For the memory cell which reads and writes, then the following circuit which is the combination
of the above two is thus obtained.

21
 Sel
5V

Din

CLK
CP1 Q1
CP2 Q2 S Q Dout
S0 _
R Q

RW
5V

Resulting wave forms

280 290 300 310 320 330 340

Din
Dout

Question 2b

1. INTRODUCTION

22
Memory cells can be configured in different configurations containing cells of any number such
as a configuration of 4x3 where four rows of three memory cells. And each memory cell is a one
bit memory cell.

2. DESIGN THEORY

A 4x3 RAM consist of 12 memory cells in total of which each three memory cells are arranged
on a single row. The design is based on a single memory cell. The single cell involves the
following signals; the selector signal for deciding the activeness or inactive of the cell, the
Read/write signal for making decisions whether to write or to read with bit 1 for read and 0 for
write, the data in signal supplying data to the memory and the data out signal to produce the
result during read.

Memory cell

The four rows of three memory cell each are controlled by the enable input of the decoder. The
decoder is disabled when the line is zero and at this time none of the memory words are selected
and when the decoder is enabled i.e. the line is 1 one among the four words is selected depending
on the addressing.

3. Circuit realization
i. Considering a single cell
The bellow circuit is the single memory cell as designed on the above problem 2a.
23
 Sel
5V

Din

CLK
CP1 Q1
CP2 Q2 S Q
Dout
S0 _
R Q

RW
5V

The select signal which is the address to be monitored by the decoder can either be one
indicating the word has been selected or zero signifies no word for that memory has been
selected, while the R/W signal signifies read (1) or write (0) operation respectively. For the 4X3
memory unit then each cell need to have this signal for symmetry purpose. The clock in this case
behaves as the input data signal.

ii. Circuit realization for the 4X3 memory unit

From the theory and analysis from the single cell memory, then a three row four column circuit
is designed and obtained as shown below where the input to the memory unit is generated by the
data sequencer on which at this moment acts as the buffer for input data and is triggered by the
clock as shown on the circuit below. The decoder as explained above is the one which provide a
select signal to each row indicating which row is active i.e. which word has been selected. And
on a single word can be selected at a time however the memory unit is capable of handling four
words of three bits each. Furthermore, the decoder is triggered by the enable signal (as explained
above)

24
 DS1
Data 8
CLK Seq 7
6
5
V1 4
3
CP1 Q1 CP1 2
CP2 Q2 CP2 1

U25A
4555
1/2
V2 A1 Q3 U13A
A0 Q2 U18B
0V Q1 U15C
E Q0 U10
U5 U1
S Q
S Q _ U24D U13B S Q
U16A _ U21A U18C R Q _
U23A
R Q R Q

U16B U19A U13C

U9 U2
U6
S Q S Q
_ S Q
U24C U14A _
U23B U16C U19B _ R Q
R Q U23F R Q

U14B
U17A U19C U3
U7 U11 S Q
U14C _
S Q S Q
U24B R Q
U17B _ U20A _
U23C R Q U22A R Q
U15A
U17C U20B U4
U12 U8 S Q
S Q U24E U15B _
_ S Q R Q
U23D U18A U20C _
R Q U24A R Q

V3
5V U23E

U28C U29B U28B U27A

U27B U26A U26B U26C
U29C U27C U29A U28A

U30A
U31A U30B
DISP1

4321 D2 D1
D0

25
Waveform after the simulation of above circuit

1120 1130 1140 1150 1160 1170 1180

CLK

D0
D1
D2

LAB 3: DESIGN COUNTERS.

26
 (a) The N-bit binary counter is a device that counts up to 2N. It then resets and counts again
from zero. Design a four-bit binary counter with J-K flip-flops.

1. INTRODUCTION
Counters are N bits devices which when pulsed counts from 0 to 2N– 1, and the process then
repeats. Actually they are the modulo N counters where N is the number of bits and 2N is the
number of states to be taken by the counter.

The counter will increase by 1 for each input pulse. When the output reaches 2N – 1 then

the next state of the circuit will go low, that is the process repeats itself again.

2. DESIGN THEORY
The four bits binary counter is the counter which counts from 0 and adds one to obtain

the next state value up to 24 – 1=15 when a pulse is received before reset back to zero and the

process repeats. Since the counter counts from zero, then the counter will have 16 states and four
bits will be involved. The counter will thus have 16 outputs and will be designed using four JK
Flip Flops since four bits will be needed to represent the 16 states effectively.

The following are the design states which are to be followed.

2.1 THE STATE DIAGRAM OF THE COUNTER

27
 1 2 3 4 5
0

15

14
13 12 11 10 9 8

The counter moves from on state to another when a pulse is issued

2.2 THE STATE TABLE OF THE COUNTER FROM THE STATE DIAGRAM ABOVE :

Present State (P.S) Next State (N.S)

S/N S3 S2 S1 S0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 0 0 1

1 0 0 0 1 0 0 1 0

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 1 0 0

4 0 1 0 0 0 1 0 1

5 0 1 0 1 0 1 1 0

6 0 1 1 0 0 1 1 1

7 0 1 1 1 1 0 0 0

8 1 0 0 0 1 0 0 1

9 1 0 0 1 1 0 1 0

10 1 0 1 0 1 0 1 1

11 1 0 1 1 1 1 0 0

12 1 1 0 0 1 1 0 1

13 1 1 0 1 1 1 1 0
28
14 1 1 1 0 1 1 1 1

15 1 1 1 1 0 0 0 0
2.3 THE TRUTH TABLE OF THE COUNTER :

Present State (P.S) Next State (N.S) FF3 FF2 FF1 FF0

S3 S2 S1 S0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 0 1 0 d 0 d 0 d 1 d

0 0 0 1 0 0 1 0 0 d 0 d 1 d d 1

0 0 1 0 0 0 1 1 0 d 0 d d 0 1 d

0 0 1 1 0 1 0 0 0 d 1 d d 1 d 1

0 1 0 0 0 1 0 1 0 d d 0 0 d 1 d

0 1 0 1 0 1 1 0 0 d d 0 1 d d 1

0 1 1 0 0 1 1 1 0 d d 0 d 0 1 d

0 1 1 1 1 0 0 0 1 d d 1 d 1 d 1

1 0 0 0 1 0 0 1 d 0 0 d 0 d 1 d

1 0 0 1 1 0 1 0 d 0 0 d 1 d d 1

1 0 1 0 1 0 1 1 d 0 0 d d 0 1 d

1 0 1 1 1 1 0 0 d 0 1 d d 1 d 1

1 1 0 0 1 1 0 1 d 0 d 0 0 d 1 d

1 1 0 1 1 1 1 0 d 0 d 0 1 d d 1

1 1 1 0 1 1 1 1 d 0 d 0 d 0 1 d

1 1 1 1 0 0 0 0 d 1 d 1 d 1 d 1

2.4 MINIMIZATION USING K-MAPS

Consider FF3

For input J3 For input K3

29
 S1S0 S1S0
00 01 11 10 00 01 11 10
S3S2 S3S2
00 0 0 0 0 00 d d d d
01 0 0 1 0 01 d d d d
10 d d d d 10 0 0 1 0
11 d d d d 11 0 0 0 0

J3
=S2S1S0 K3=S2S1S0

Consider FF2

For input J2 For input K2

S1S0 11 S1S0 11
00 01 10 00 01 10
S3S2 S3S2
00 0 0 1 0 00 d d d d
01 d d d d 01 0 d 1 0
10 d d d d 10 0 0 1 0
11 0 0 1 0 11 d d d d

J2=S1S0 K2=S1S0

Consider FF1

For input J1 For input K1

30
 S1S0 S1S0
00 01 11 10 00 01 11 10
S3S2 S3S2
00 0 1 d d 00 d d 1 0
01 0 1 d d 01 d d 1 0
10 0 1 d d 10 d d 1 0
11 0 1 d d 11 d d 1 0

J1=S0 K1=S0

Consider FF0

For input J0 For input K0

S1S0 S1S0
00 01 11 10 00 01 11 10
S3S2 S3S2
00 1 d d 1 00 d 1 1 d
01 1 d d 1 01 d 1 1 d
10 1 d d 1 10 d 1 1 d
11 1 d d 1 11 d 1 1 d

J0=1 K0=1

3. CIRCUIT DIAGRAM AND WAVEFORMS

31
 output

S3 S2 S1 S0
4321

CLK S S S S
J Q J Q J Q J Q
CP S3 _ CP S2 _ CP S1 _ CP S0 _
K Q K Q K Q K Q
R R R R
CLK
CP1 Q1
CP2 Q2 key
5V

4. CONCLUSSION AND RECOMMENDATION

The circuit performs as intended and depicts a modulo 4 counter.

32
QUESTION 3(b)

Design a divide-by-12 counter that will count (in binary) the number of pulses on the input line.
Use J-K flip-flops.

1. INTRODUCTION
Divide by N counters are the counters which counts up from zero to 2 N - 1 then resets to one
and the process then repeats. Actually they are the modulo N counters where N is the

number of bits and 2N states.

The counter will increase by 1 for each input pulse. When the output reaches 2n – 1 then

the next state of the circuit will go low. Thus next state becomes zero and the process

repeats itself.

2. DESIGN THEORY

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To design a four-bit binary counter, will require 2N states, where N is the maximum number of
bits in the counter. In our case its four bits (specified from the question). Thus we have 2 4 =16
states in total.

The state will be increasing by 1 for each input pulse. When the output reaches 1011=11(in base
10), the next state would expected to be 1100 but for divide by 12 counter reset the counters i.e.
clears all the registers and starts from 0000 rather than 1100.

Since the counter has 12 states then a total of four JK flip flop are going to be used.

2.1 THE STATE DIAGRAM FOR THE COUNTER:

2 3 4 5
1

6
0

7
11 10 9 8

2.2 THE STATE TABLE FOR THE ABOVE STATE DIAGRAM :

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 Present State (P.S) Next State (N.S)

S/N S3 S2 S1 S0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 0 0 1

1 0 0 0 1 0 0 1 0

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 1 0 0

4 0 1 0 0 0 1 0 1

5 0 1 0 1 0 1 1 0

6 0 1 1 0 0 1 1 1

7 0 1 1 1 1 0 0 0

8 1 0 0 0 1 0 0 1

9 1 0 0 1 1 0 1 0 2.3
10 1 0 1 0 1 0 1 1 THE
11 1 0 1 1 0 0 0 0

12 1 1 0 0 d d d d

13 1 1 0 1 d d d d

14 1 1 1 0 d d d d

15 1 1 1 1 d d d d

TRUTH TABLE :

Present State (P.S) Next State (N.S) FF3 FF2 FF1 FF0

S3 S2 S1 S0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 0 1 0 d 0 d 0 d 1 d

0 0 0 1 0 0 1 0 0 d 0 d 1 d d 1

0 0 1 0 0 0 1 1 0 d 0 d d 0 1 d

0 0 1 1 0 1 0 0 0 d 1 d d 1 d 1

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 0 1 0 0 0 1 0 1 0 d d 0 0 d 1 d

0 1 0 1 0 1 1 0 0 d d 0 1 d d 1

0 1 1 0 0 1 1 1 0 d d 0 d 0 1 d

0 1 1 1 1 0 0 0 1 d d 1 d 1 d 1

1 0 0 0 1 0 0 1 d 0 0 d 0 d 1 d

1 0 0 1 1 0 1 0 d 0 0 d 1 d d 1

1 0 1 0 1 0 1 1 d 0 0 d d 0 1 d

1 0 1 1 0 0 0 0 d 1 0 d d 1 d 1

1 1 0 0 d d d d d d d d d d d d

1 1 0 1 d d d d d d d d d d d d

1 1 1 0 d d d d d d d d d d d d

1 1 1 1 d d d d d d d d d d d d

2.4 MINIMIZATION USING K-MAPS

Consider FF3

For input J3 For input K3

S1S0 S1S0 11
00 01 11 10 00 01 10
S3S2 S3S2
00 0 0 0 0 00 d d d d
01 0 0 1 0 01 d d d d
10 d d d d 10 d d d d
11 d d d d 11 0 0 1 0

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J3=S2S1S0 K3=S1S0

Consider FF2

For input J2 For input K2

S1S0 11 S1S0 11
00 01 10 00 01 10
S3S2 S3S2
00 0 0 1 0 00 d d d d
01 d d d d 01 0 0 1 0
10 d d d d 10 d d d d
11 0 0 0 0 11 d d d d

J2=S3’ S1S0 K2=S1S0

Consider FF1

For input J1 For input K1

S1S0 S1S0
00 01 11 10 00 01 11 10
S3S2 S3S2
00 0 1 d d 00 d d 1 0
01 0 1 d d 01 d d 1 0
10 d d d d 10 d d d d
11 0 1 d d 11 d d 1 0

J1=S0 K1=S0

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Consider FF0

For input J0 For input K0

S1S0 S1S0
00 01 11 10 00 01 11 10
S3S2 S3S2
00 1 d d 1 00 d 1 1 d
01 1 d d 1 01 d 1 d d
10 d d d d 10 d d d d
11 1 d d 1 11 d 1 1 d

J0=1 K0=1

3. CIRCUIT DIAGRAM AND WAVEFORMS:

Circuit diagram

The minimization above with the resulted equations end up in producing the following circuit
diagram:

38
 DISP1

4321

S3 S2 S1 S0

V2
5V

S S S S
J Q J Q
CP S3_ CPS2 _ J Q J Q
K Q K Q CP S1_ CP S0_
CLK K Q K Q
R R R R

CLK
CP1 Q1 U2A
CP2 Q2

Simulation and waveforms

Simulation was done using the circuit maker and after simulation the following waveforms were
obtained.

4. CONCLUSION AND RECOMMENDATION

From the waveform, a delay is observed during the raising edge of a clock to each of the output.
The delay is resulted from the internal gates delay and delays due to the JK flip flop used.

39
Furthermore, the change of S3 is very much slow i.e. change slowly as compare with the output
S0 which is the fastest, changes once after every two clock pulse (which is twice as much the
speed of output S2 as can be seen from the wave forms ).

LAB4: DESIGN OF SEQUENTIAL CIRCUITS USING MEMORY CELLS.

Design a synchronous sequential circuit whose inputs are binary levels and that the following
state assignment is used:

Y=0 ≡ A

Y=1 ≡ B

Use Karnaugh maps to find:

(a) The State Table; and

(b) The State Diagram.

Hint: Use D Flip-Flop as your memory device.

1. INTRODUCTION
A sequential circuit is the one in which the decisions are made based on combination of the
current input as well as the past history of the inputs, furthermore a synchronous sequential
circuit is the one which is triggered by using clock.

40
The D flip flop is commonly used in situations where there is feedback from the output back
to the input through some other circuitry and this feedback can sometimes cause the flip-flop
to change states more than once per clock cycle. In order to ensure that the flip-flop changes
state just once per clock pulse, we break the feedback loop by constructing a master-slave
flip-flop.

2. DESIGN THEORY
2.1 STATE DIAGRAM

2.2 THE STATE TABLE

PRESENT
NEXT STATE [Q(t+1)]
STATE
[Q(t)]
In=0 In=1

A: 0 A/0 B/1

B:1 B/1 A/0

2.3 THE TRUTH TABLE

41
 In Q(t) Q(t+1) OUTPUT(Z)

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 0

2.4 THE EXCITATION TABLE

In Q(t) D

0 0 0

0 1 1

1 0 1

1 1 0

3. K-MAP MINIMIZATION

Q(t)
0 1
In

0 0 1

1 1 0

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 D  I nQ(t )  I nQ (t )
1. CIRCUIT DIAGRAM AND WAVEFORMS
U4A
U1 A_ 1 L1

U1A
U1 A_ 3

V1 L1 _ 1
CP1 Q1 U2A
CP2 Q2
U3A
V1 _ 3 S U1 A_ 2
D Q
_ U1 B_ 5
CP Q U1B
R U1 B_ 4
U4 A_ 3

V3
5V
V3 _ 1

The circuit diagram of the synchronous

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