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Topic: Course Name: Embedded System Design With ARM

The document discusses ARM instruction set part 2, including data transfer instructions, single and multiple register transfer instructions, and memory-mapped I/O. It describes various ARM instructions for single register loads and stores that can transfer bytes, half-words, and words. It also covers multiple register load and store instructions and the different addressing modes they support for incrementing/decrementing addresses. Finally, it provides an example of using instructions to copy a block of memory and explains that I/O ports are treated as memory locations accessed using LDR and STR instructions in ARM.

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Sagar Bhokare
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46 views13 pages

Topic: Course Name: Embedded System Design With ARM

The document discusses ARM instruction set part 2, including data transfer instructions, single and multiple register transfer instructions, and memory-mapped I/O. It describes various ARM instructions for single register loads and stores that can transfer bytes, half-words, and words. It also covers multiple register load and store instructions and the different addressing modes they support for incrementing/decrementing addresses. Finally, it provides an example of using instructions to copy a block of memory and explains that I/O ports are treated as memory locations accessed using LDR and STR instructions in ARM.

Uploaded by

Sagar Bhokare
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Course Name: Embedded System Design with ARM

Faculty Name: Prof. Indranil Sen Gupta


Department : Computer Science and Engineering

Topic
Lecture 8: ARM Instruction Set (Part 2)
 Data transfer instructions

 Single register transfer instructions

 Multiple register transfer instructions

 Memory-mapped I/O in ARM


(b) Data Transfer Instructions

• ARM instruction set supports three types of data transfers:


a) Single register loads and stores
• Flexible, supports byte, half-word and word transfers
b) Multiple register loads and stores
• Less flexible, multiple words, higher transfer rate
c) Single register-memory swap
• Mainly for system use (for implementing locks)

3
• All ARM data transfer instructions use register indirect addressing.
• Before any data transfer, some register must be initialized with a memory address.
ADRL r1,Table ; r1 = memory address of Table
• Example:
LDR r0,[r1] ; r0 = mem[r1]
STR r0,[r1] ; mem[r1] = r0

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• Single register loads and stores
• The simplest form uses register indirect without any offset:
LDR r0,[r1] ; r0 = mem[r1]
STR r0,[r1] ; mem[r1] = r0
• An alternate form uses register indirect with offset (limited to 4 Kbytes):
LDR r0,[r1,#4] ; r0 = mem[r1+4]
STR r0,[r1,#12] ; mem[r1+12] = r0
• We can also use auto-indexing in addition:
LDR r0,[r1,#4]! ; r0 = mem[r1+4], r1 = r1 + 4
STR r0,[r1,#12]! ; mem[r1+12] = r0, r1 = r1 + 4

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• We can use post indexing:
LDR r0,[r1],#4 ; r0 = mem[r1], r1 = r1 + 4
STR r0,[r1],#12 ; mem[r1] = r0, r1 = r1 + 12
• We can specify a byte or half-word to be transferred:
LDRB r0,[r1] ; r0 = mem8[r1]
STRB r0,[r1] ; mem8[r1] = r0
LDRSH r0,[r1] ; r0 = mem16[r1]
STRSH r0,[r1] ; mem16[r1] = r0

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• Multiple register loads and stores
• ARM supports instructions that transfer between several registers and memory.
• Example:
LDMIA r1,{r3,r5,r6} ; r3 = mem[r1]
; r5 = mem[r1+4]
; r6 = mem[r1+8]
• For LDMIB, the addresses will be r1+4, r1+8, and r1+12.
• The list of destination registers may contain any or all of r0 to r15.
• Block copy addressing
• Supported with addresses that can increment (I) or decrement (D), before (B)
or after (A) each transfer.

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• Examples of addressing modes in multiple-register transfer:

LDMIA, STMIA
• Increment after
LDMIB and STMIB
• Increment before
LDMDA, STMDA
• Decrement after
LDMDB, STMDB
• Decrement before

8
• Point to note:
• ARM does not support any hardware stack.
• Software stack can be implemented using the LDM and STM family of instructions.

9
An Example

• Copy a block of memory (128 bytes aligned).


• r9: address of the source
• r10: address of the destination
• r11: end address of the source

Loop: LDMIA r9!,{r0-r7}


STMIA r10!,{r0-r7}
CMP r9,r11
BNE Loop

10
Memory Mapped I/O in ARM

Data
Memory

Data
Data Address I/O Port
Memory
Address
Decoder
.. I/O Port
. ..
.
Select I/O Port
Lines

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• No separate instructions for input/output.
• The I/O ports are treated as data memory locations.
• Each with a unique (memory) address.
• Data input is done using the LDR instruction.
• Data output is done with the STR instruction.

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