FETs And MOS Capacitors

1 Introduction
Field effect transistors are the semiconductor devices which operate on principle of control of output
current by input voltage or electric field. The field effect transistors are of two types called Junction
Field Effect Transistor (JFET) and Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
The current in FETs is contributed by one type of carriers only therefore these devices are unipolar
devices. The field effect transistors have following advantages and disadvantages over bipolar
junction transistor.

Advantages of FETs over BJT

1. Current in FET is carried by majority carriers, therefore, it is a unipolar devices but in BJT
current is carried by both electron and holes, therefore, BJT is a Bipolar device.
2. FETs have very high input impedance of order of Mega ohms as compared to BJT
3. BJT is more noisy than FETs.
4. FET exhibits no offset voltage as observed in BJT.
Offset voltage is the drop across the junction in BJT.
5. FETs suffer from no secondary breakdown like BJT. Thermal breakdown is called secondary
breakdown where as Avalanche and zener breakdowns called primary breakdown.
6. FETs have very small switching losses as compare to BJT. But their ON state losses are more as
compared to BJT.
7. Switching frequency of FETs is higher than BJT because their turn OFF time is smaller.
8. FETs have better frequency response than BJT.
9. The breakdown voltage of FETs has positive temperature coefficient that means breakdown
voltage increases with increase in temperature. The positive temperature coefficient of FETs
makes it suitable for parallel operation.
Disadvantages of FETs as compared to BJT
1. FETs have higher ON state losses because their resistance is more than that of BJT in continuous
conduction state.
2. The dynamic resistance of FETs is higher as compared to BJT.
3. The gain bandwidth product of FETs is smaller as compared to BJT.

2 Metal-Oxide-Semiconductor (MOS) Capacitor ( Only for ECE)

A Metal-Oxide-Semiconductor (MOS) capacitor has a a metal gate deposited on a oxide (SiO2) layer.
The oxide layer is fabricated on a semiconductor substrates as shown in Fig.1. The semiconductor
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substrate can be either n-type or p-type. A Metal-Oxide-Semiconductor (MOS) capacitor is heart of
MOSFET operation.
Metal gate

Oxide
tox ox

Semiconductor
Substrate

Fig.1 Structure of basic MOS capacitor structure

A MOS capacitor acts like a parallel plate capacitor with a dielectric inserted between the plates. The
capacitor per unit area of the oxide of the MOS capacitor is given by,
ox
Cox =
ox

where, εox permittivity and tox is thickness of oxide layer.

A MOS capacitor can work in three modes of operations called accumulation mode, depletion mode
and inversion mode of operations.

Accumulation mode
If gate terminal is given a potential such that there is accumulation of majority carriers of substrate
at the interface of oxide and semiconductor then mode of operation is called accumulation mode.

Depletion Mode
If gate terminal of the MOS capacitor is given such a potential that it repels the majority carrier from
the interface of oxide and semiconductor resulting in formation of depletion layer in the substrate
region at the interface then the mode of operation is called depletion mode. In depletion mode there
are induced space charge of impurity atoms of semiconductor substrate in the depletion layer.

Inversion Mode
If gate terminal of the MOS capacitor is given such a potential that it attracts minority carries
from semiconductor substrate at oxide-semiconductor interface forming an inversion layer with
concentration of minority carriers at more than the concentration majority carriers in bulk of substrate
then the mode of operation is called inversion mode. Inversion mode is key to operation of MOSFET.
The critical gate voltage, when there is formation of inversion layer at the surface, is called threshold
voltage.
A MOS capacitor offers maximum capacitance in accumulation and inversion modes of operations if
high frequency effects are neglected. The capacitance offered is minimum in the depletion mode of
operation.

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2.1 Energy Band Diagram of MOS Capacitor
Case - I : MOS Capacitor with p-type substrate
The biasing of a MOS capacitor with p-type semiconductor substrate for accumulation, depletion
and inversion modes of operation is shown in Fig. 2.
Gate Gate Gate
++++++
––– ––– ++++++ electrons + + + + + +
oxide oxide + oxide +
++++++ – – – – – – – –– –– –– –– –– ––
p-type v p-type v p-type v
substrate + substrate – substrate –

holes Acceptor
Acceptor
impurity
impurity
ions
ions
(a) Accumulation mode (b) Depletion mode (c) Inversion mode

Fig.2 Biasing of MOS capacitor with p-type substrate (a) accumulation mode (b) depletion
mode (c) inversion mode

Energy band diagram under equilibrium

The work function of metal is normally defined as energy required to bring an electron on the surface
or vacuum level from the Fermi level of the metal. However, for MOS capacitor and MOSFET
the work function (qφm) for metal-oxide interface will be defined as energy required to move the
electron from Fermi level of metal to conduction band of oxide and work function (qφsem) for oxide-
semiconductor interface will be defined as energy required to move an electron from Fermi level of
semiconductor to conduction band of the oxide. There is another important term qφF which will be
used for difference in energy of actual Fermi level and intrinsic Fermi level for semiconductor. Under
idealized condition it is assumed that work of metal is equal to work function of the semiconductor
(i.e. φm = φsem ) so that there is no difference in work functions. The Fermi level under idealized
conditions at equilibrium when no bias is applied to the MOS capacitor is as shown in Fig.3(a). At
equilibrium with zero bias the Fermi level on both sides of oxide layer is at the same level.

Energy band diagram under accumulation mode

The MOS capacitor with p-type semiconductor substrate operates in accumulation mode when the
metal gate is connected to negative terminal of the supply as shown inf Fig. 2(a). When gate terminal
is connected to the negative potential the electrons are deposited on gate metal. The negative charge
on the gate metal induces an electric field in the oxide layer which in turn attracts holes from the
p-type semiconductor substrate and holes are accumulated on the oxide-semiconductor interface as
shown in the Fig. 3(a). The applied negative potential on gate terminal results in increase in energy of
electrons in metal. As a result Fermi level of metal EFm shifts above the equilibrium position (EFs) by
qV, where V is applied voltage. The work function of metal (qφm) and that of semi conductor (qφsem )
does not change with applied voltage so it results in tilting of conduction band of the oxide layer as
shown in Fig. 3(b). The induced electric field  in oxide causes a gradient in intrinsic Fermi energy
level Ei near the oxide-semiconductor interface. The induced electric field in oxide is related to the
gradient in Ei as under,
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1 dE i
(x) = (1)
q dx

The accumulation of holes at oxide-semiconductor interface increases the concentration of holes

at the interface. The increased concentration of holes at the interface in semiconductor results in
upward bending of upper level of valence band (EV) closer to the Fermi energy level(EFs) at the
interface. Therefore, the upper energy level of valence band of semiconductor is tilted upward
near the interface. Similar tilt is observed in intrinsic energy level as well as lowest energy level of
conduction band of the semiconductor as shown in Fig. 3(b). The concentration of holes in valence
band of a semiconductor in terms of actual Fermi level and intrinsic Fermi level is given by,
(E − E )/ kT
p = n i e i Fs (2)
Conduction band of oxide  Vox

qm qsem

EC EC
EFm
qV Ei
EFm Ei qF
qF EFs
EFs +
++ Ev
Ev
Accumulation of
holes
p-type p-type
Metal Oxide Semiconductor Metal Oxide Semiconductor
(a) At equilibrium ( V = 0) (b) Accumulation mode ( V < 0)
Vox  Vox 
Inversion layer
of electrons

EC __
_
EC

Ei
Ei qF
qF EFs
EFs qV Ev
qV
EFm Ev EFm

p-type p-type
Metal Oxide Semiconductor Metal Oxide Semiconductor
(c) Depletion mode ( V > 0) (d) Inversion mode ( V >> 0)

Fig.3 Energy band diagram of MOS with p-type semiconductorsubstrate (a)At thermal equilibrium
(b) under accumulation mode (c) under depletion mode (d) under inversion mode

It is observed from equation (2) that concentration of holes near the oxide-semiconductor interface

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can increase only if there is increase in difference Ei − EFs near the interface. If there is no current
in the semiconductor then there is no variation in Fermi level, EFs, in the semiconductor. So, the
difference Ei − EFs near the oxide-semiconductor interface is increased only by tilting the intrinsic
level Ei upward at the interface. The Fermi level, EFs, at interface is more closer to the upper energy
level of valence band which means holes concentration at interface is larger than that arising from
the doping of p-type substrate.

Energy band diagram under depletion mode

The MOS capacitor with p-type semiconductor substrate work in depletion mode when the metal
gate terminal of the capacitor is given a small positive potential as shown in Fig. 2(b). When gate
terminal is connected to a small positive potential the gate metal acquires a positive charge. The
applied positive potential on gate terminal results in decrease in energy of electrons in metal. As a
result Fermi level of metal EFm shifts down the equilibrium position (EFs) by qV, where V is applied
voltage. The positive charge on the gate metal induces an electric field in the oxide layer which repels
the holes away from oxide-semiconductor interface and, therefore, a depletion layer is formed below
the gate region close to oxide-semiconductor interface as shown in Fig. 3(c). The depletion region
near the interface consists of uncovered bound negative charges of acceptor impurity just like the
depletion region of pn junction. The depletion of holes near the oxide-semiconductor interface results
in decrease in concentration of holes which in turn results in tilting of upper energy level of valence
band (EV) away from the Fermi level (EFs) near the interface in depletion region as shown in Fig. 3(c).
Similar tilt is observed in intrinsic energy level as well as lowest energy level of conduction band of
the semiconductor.

Energy band diagram under inversion mode

When positive potential, connected to the metal gate, is further increased there is a situation when
intrinsic Fermi level Ei bends below the Fermi level EFs at oxide-semiconductor interface and the
lowest level of conduction band (EC) also bends downward and becomes closer to the Fermi level
(EFs) as compared to highest level of valence band (EV) as shown in Fig. 3(d). Therefore, the region
near oxide-semiconductor interface has properties similar to that of a n-type semiconductor. This
bending of Ei below EEs at oxide-semiconductor result in large electron concentration in conduction
band near oxide-semiconductor interface. For inversion mode bend in intrinsic level at surface, φs
> 2φF . The critical gate voltage, when there is formation of inversion layer at the surface , is called
threshold voltage. Therefore, an n-type surface layer is formed not because of doping but due to
inversion of originally p-type semiconductor due to large applied voltage. The inversion layer of
electrons is separated from underlying p-type layer by depletion region. This formation of inversion
layer is key to MOSFET operation.

Case - II : MOS Capacitor with n-type substrate

The biasing of a MOS capacitor with n-type semiconductor substrate for accumulation, depletion and
inversion modes of operation is shown in Fig. 4.

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Gate Gate Gate

 –– –– –– –– –– ––
+++ +++
holes
oxide oxide – oxide –
 + + + + + + + + ++ ++ ++ ++ +
+ +
n-type v n-type v n-type v
substrate – substrate + substrate +
electrons Donor
Donor
impurity
impurity
ions
ions
(a) Accumulation mode (b) Depletion mode (c) Inversion mode
Fig.4 Biasing of MOS capacitor with n-type substrate (a) accumulatoin mode (b) depletion
mode (c) inversion mode

Energy band diagram under equilibrium

Under idealized condition it is assumed that work function of metal is equal to the work function
of semiconductor (i.e. φm = φsem ) so that there is no difference in work functions. The Fermi level
under idealized conditions at equilibrium when no bias is applied to the MOS capacitor is as shown
in Fig.5(a). At equilibrium with zero bias the Fermi level on both sides of oxide layer is at the same
level.

Energy band diagram under accumulation mode

The MOS capacitor with n-type semiconductor substrate operates in accumulation mode when the
metal gate is connected to positive terminal of the supply as shown inf Fig. 4(a). When gate terminal
is connected to the positive potential gate metal acquires a positive charge. The positive charge on
the gate metal induces an electric field () in the oxide layer which in turn attracts electrons from the
n-type semiconductor substrate and electrons are accumulated on the oxide-semiconductor interface
as shown in the Fig. 5(b). The applied positive potential on gate terminal results in decrease in energy
of electrons in metal. As a result Fermi level of metal, EFm, shifts below the equilibrium position
(EFs) by qV, where V is applied voltage. The work function of metal (qφm) and that of semi conductor
(qφsem) does not change with applied voltage so it results in tilting of conduction band of the oxide
layer.
The accumulation of electrons at oxide-semiconductor interface results in increases in concentration
of electrons at the interface. The increased concentration of electrons at the interface in semiconductor
results in downward shifting of lowest level of conduction band (EC) closer to the Fermi energy level
(EFs) at the interface. Therefore, the lowest energy level of conduction band of semiconductor is tilted
downward near the interface. Similar tilt is observed in intrinsic energy level(Ei) as well as highest
energy level (EV) of valence band of the semiconductor as shown in Fig. 5(b). The concentration of
electrons in conduction of a semiconductor in terms of actual Fermi level and intrinsic Fermi level is
given by,
(E − E )/ kT
n = n i e Fs i (3)

It is observed from above equation that concentration of electrons near the oxide-semiconductor

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interface can increase only if there is increase in difference EFs− Ei near the interface. If there is no
current in the semiconductor then there is no variation in Fermi level, EFs, in the semiconductor. So,
the difference EFs− Ei near the oxide-semiconductor interface is increased only by tilting the intrinsic
level Ei downward at the interface. The Fermi level, EFs, at interface is more closer to the lower
energy level of conduction band which means electrons concentration at interface is larger than that
arising from the doping of n-type substrate.

Conduction band of oxide 

qm qsem Accumulation

of electrons
__ _ EC
EC
qF EFs
EFs qV
qF EFm Ei
EFm Ei
Ev
Ev

n-type
n-type Metal Oxide Semiconductor
Metal Oxide Semiconductor

(a) At equilibrium ( V = 0) (b) Accumulation mode ( V > 0)

 

EFm EC EFm qV EC
qV
qF EFs qF EFs
Ei Ei
+
++
Ev Ev
Inversion layer
of holes

n-type n-type
Metal Oxide Semiconductor Metal Oxide Semiconductor

(c) Depletion mode ( V < 0) (d) Inversion mode ( V << 0)

Fig.5 Energy band diagram of MOS with n-type semiconductor substrate (a) At thermal
equilibrium (b) under accumulation mode (c) under depletion mode (d) under inversion mode
Energy band diagram under depletion mode
The MOS capacitor with n-type semiconductor substrate work in depletion mode when the

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metal gate terminal of the capacitor is given a small negative potential as shown in Fig. 4(b).
When gate terminal is connected to a small negative potential the gate metal acquires a negative
charge. The applied negative potential on gate terminal results in increase in energy of electrons
in gate metal. As a result Fermi level of metal EFm shifts upward from the equilibrium position
(EFs) by qV. The negative charge on the gate metal induces an electric field () in the oxide layer
which repels the electrons away from oxide-semiconductor interface and, therefore, a depletion
layer is formed below the gate region close to oxide-semiconductor interface as shown in
Fig. 5(c). T
he depletion region near the interface consists of uncovered bound positive charges of
donor impurity similar to the depletion region of pn junction. The depletion of electrons near the
oxide-semiconductor interface results in decrease in concentration of electrons which in turn results
in tilting of lowest energy level of conduction band (EC) away from the Fermi level (EFs) near the
interface in depletion region as shown in Fig. 5(c). Similar tilt is observed in intrinsic energy level
as well as highest energy level of valence band of the semiconductor.

Energy band diagram under inversion mode

When negative potential of the metal gate is further increased there is a situation when intrinsic
Fermi level Ei bends above the Fermi level EFs at oxide-semiconductor interface and the highest level
of valence band (EV) also bends upward and becomes closer to the Fermi level (EFs) as compared
to lowest level of conduction band (EC) as shown in Fig. 5(d). Therefore, the region near oxide-
semiconductor interface has properties similar to that of a p-type semiconductor. This bending of
Ei above EEs at oxide-semiconductor result in large hole concentration in valence band near oxide-
semiconductor interface. Therefore, a p-type surface layer is formed not because of doping but due
to inversion of originally n-type semiconductor due to large applied voltage. The inversion layer of
holes is separated from underlying n-type layer by depletion region.
2.2 Surface Potential, Carrier Concentration and Depletion Region Width in
MOS Capacitor in Inversion Mode
Case - I : MOS Capacitor with p-type substrate
When MOS capacitor with a p-type substrate works in the inversion mode the intrinsic Fermi level(Ei)
bends down below the Fermi level (EFs) at the oxide-semiconductor interface as shown in Fig. 6. Let
qφF represents the difference in intrinsic Fermi level (Ei) and actual Fermi level (EFs) at equilibrium
state in bulk of the semiconductor substrate and qφs represents bending of intrinsic Fermi level (Ei)
at oxide-semiconductor interface. Let the energy level difference qφ represents extent of bends in
energy band Ei from its equilibrium value at a distance x from the interface. Here φs is called surface
potential which is a potential drop across the depletion layer of the capacitor. The condition φs = 0 is
known as flat band condition which is an ideal MOS. When φs < 0 the energy band bends upward at
the interface and there is hole accumulation and φs > 0, there is formation of depletion region. When
φs > 0 and qφs > qφF these is formation of inversion layer at the oxide-semiconductor interface. For
strong inversion, the formation of n-type inversion layer should be as strong as p-type substrate. In
other works there is condition called threshold of inversion when concentration of electrons at the
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interface becomes concentration of holes in the bulk of substrate. This condition occurs when,
φs = 2φF (4)
Depletion
layer
W
EC

q
Ei
qFq qF
qs EFs
EV

x
p-type
Oxide Semiconductor
Fig.6 Energy band diagram of MOS with p-type semiconductor substrate under inversion mode

Expression of Surface Potential :
From the semiconductor theory it found that the concentration of holes in p-type substrate under
thermal equilibrium state is given by,
(E Fs E V )

p ≈ NA ≈ N e kT
(5)

where NV represents density of states in valence band and NA is acceptor concentration.

Above equation can be further modified as under,
(E Fs − E V − E i + E i ) (E i − E V ) (E i − E Fs )
− −
NA = N V e kT
= NVe kT
e kT
(6)

(E i − E Fs )

⇒ NA = n i e kT
(7)

(E i − E V )
−
where, ni = N V e kT
= intrinsic carrier concentration (8)

From the energy band diagram of Fig.6, we have,

Ei − EFs = qφF
qφF

⇒ NA = n i e kT (9)

kT N A N
⇒ =φF n
= VT n A (10)
q ni ni

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kT
where, VT = = Thermal voltage
q

The surface potential for at threshold inversion point,

kT N A N
⇒ φ s = 2φ F = 2 n = 2VT n A (11)
q ni ni

Carrier Concentrations on Interface :

The electron concentration in the p-type substrate region in bulk out of depletion region at thermal
equilibrium is given by,
(E − E )
n2 ni2 − i Fs
n0=
= i = (E i − E Fs )
n i e kT
(12)
NA
nie kT

For bulk of p-type substrate away from depletion region, Ei − EFs = qφF
qφF
−
⇒ no = n i e kT
(13)

For depletion region at any distance ‘x’ from oxide-semiconductor interface,

Ei − EFs = qφF− qφ
So, the electron concentration in depletion region at any distance from inerface is given by,
− q( φF −φ ) − qφ F qφ qφ

⇒ n = n i e kT
= nie kT
⋅ e kT= n o e kT (14)

At the oxide-semiconductor interface, φ = φs . Therefore, the concentration of electrons at the interface

(ns),
qφs

n s = n o e kT (15)

For strong inversion, φs = 2φF

2qφF

⇒ ns = noe kT
(16)

Similarly, concentration of holes in the bulk region can be obtained using equation (7) as under,
E i − E Fs qφ F

= N A n=
p0 = ie
kT
n i e kT (17)

For depletion layer region at distance ‘x’ from the interface, Ei − EFs = qφF− qφ
q( φF −φ ) qφF qφ qφ
− −
p = n i e kT
= n i e kT ⋅ e kT
= p0 e kT
(18)

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Therefore, the concentration of holes at the interface (ps), φ = φs
qφs qφs
− −
∴ =ps p=
oe
kT
NAe kT
(19)

For threshold inversion point, φs = 2φF

2qφF
−
⇒ ps = N A e kT
(20)

Depletion Layer Width :

When a MOS capacitor works in inversion mode there is formation of depletion layer at oxide-
semiconductor interface similar to a one side pn junction as shown in Fig.4.6. The space charge
or depletion layer width in p-substrate near oxide-semiconductor interface is given similar to a one
sided pn junction as under,
2εs φs
W = (21)
qN A

Where εs = εrs εo , is permittivity of semiconductor, εrs is relative permitivity of semiconductor and εo

is permititivy of free space. The surface potential φs is potential drop across the space charge region
of the semiconductor substrate.
When surface potential φs = 2φF, the Fermi level at interface is above the intrinsic level where as it is
below the intrinsic level in bulk of semiconductor. The electron concentration at interface is same as
hole concentration in bulk of semiconductor. This condition is known as threshold inversion point and
applied voltage across the MOS capacitor at threshold inversion point is known as threshold voltage,
VT . The sapce charge width at threshold inversion point is maximum. Beyond the threshold inversion
point the electron concentration at the oxide-semiconductor interface increases exponentially with
gate voltage but width of space charge or depletion layer does not change significantly. The maximum
width of space charge is given by,


2ε s φ s 4ε s φ F
Wmax = = (22)
qN A qN A

Putting expression of φF from equation (4.10) in above equation, we have,

4εs VT N
⇒ Wmax =  n A (23)
qN A ni

Case - II : MOS Capacitor with n-type substrate

When MOS capacitor with a n-type substrate works in the inversion mode the intrinsic Fermi level(Ei)
bends above the Fermi level (EFs) at the oxide-semiconductor interface as shown in Fig. 4.7.
Expression of Surface Potential :
From the semiconductor theory it found that the concentration of electrons in p-type substrate under

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thermal equilibrium is given by,
(E C − E Fs )
−
no ≈ ND ≈ N C e kT
(24)

where NC represents density of states in conduction band and ND is donor concentration.

Above equation can be further modified as under,
(E C − E Fs − E i + E i ) (E C − E i ) (E Fs − Ei )
− −
ND = N C e kT
= NCe kT
e kT
(25)

(E Fs − E i )

⇒ ND = n i e kT
(26)

(E C − E i )
−
where, ni = N C e kT
= intrinsic carrier concentration (27)

Depletion
layer

EC
qs qFq EFs
q
qF
Ei

EV
x
n-type
Oxide Semiconductor
Fig.7 Energy band diagram of MOS with p-type semiconductor
Substrate under inversion mode

From the energy band diagram shown above, we have,

EFs − Ei = qφF
qφ F

⇒ ND = n i e kT (28)
kT N D N
⇒ =φF n
= VT n D (29)
q ni ni
The surface potential for strong inversion,
kT N D N
⇒ φ s = 2φ F = 2 n = 2VT n D (30)
q ni ni

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Carrier Concentrations on Interface :
The hole concentration in the n-type substrate at thermal equilibrium in given by,
(E − E )
n2 ni2 − Fs i
po=
= i = (E Fs − E i )
n i e kT (31)
ND
n i e kT

For bulk of p-type substrate away from depletion region, Ei − EFs = qφF
qφF
−
⇒ po = n i e kT
(32)

For depletion region at any distance ‘x’ from oxide-semiconductor interface,

Ei − EFs = qφF− qφ
Then hole concentration at any distance ‘x’ from oxide-semiconductor interface can be written as
under,
− q( φF −φ ) − qφ F qφ qφ

p = n i e kT
= nie kT
⋅ e kT= p o e kT (33)

At the oxide-semiconductor interface, φ = φs . Therefore, the concentration of holes at the interface

(ps),
qφs

ps = p o e kT (34)

For strong inversion, φs = 2φF

2qφF

⇒ ps = p o e kT
(35)

Similarly, concentration of electrons can be obtained using equation (28) as under,

E Fs − E i qφ F

= N D n=
no = ie
kT
n i e kT (36)

The concentration of electrons at distance ‘x’ from the interface,

q( φF −φ ) qφF qφ qφ
− −
and n = n i e kT
= n i e kT ⋅ e kT
= n 0e kT
(37)

Therefore, the concentration of electrons at the interface (ns),

qφs qφs
− −
=n s n=
oe
kT
NDe kT
(38)

For strong inversion, φs = 2φF

2qφF 2qφF
− −
⇒ =
n s n=
oe
kT
NDe kT
(39)

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Depletion Layer Thickness :
The space charge or depletion layer width in n-substrate near oxide-semiconductor interface is given
similar to a one sided pn junction as under,
2εs φs
W = (40)
qN D

The depletion layer width is maximum at threshold inversion point with φs = 2φF. So, the maximum
width of depletion layer in n-type substrate is given by,
2ε s φ s 4ε s φ F
Wmax = = (41)
qN D qN D

Putting expression of φF from equation (4.29) in above equation, we have,

4εs VT N
⇒ Wmax = n D (41a)
qN D ni

2.3 Charge Distribution, Electric Field and Electric Potential in MOS capacitor
The charge density, electric field and electric potential in a MOS capacitor with p-type substrate
working in strong inversion mode of operation with gate voltage more than a limiting value called
threshold voltage is shown in Fig.8.
Charge Distribution
In inversion mode of operation, the depletion region of MOS capacitor with p-substrate consists of
negative charge of inversion layer at the interface and uncovered negative charge of acceptor impurity
o
atoms. The width of inversion is of order of 100 A which is negligible as compared to total width of
depletion layer. The charge density in depletion layer due to uncovered impurity ions at threshold
inversion point,
Qd = − q NA W (42)

Let Qinv is charge density of inversion layer of electrons at oxide-semiconductor interface. The
inversion charge density is taken into account only when gate voltage is more than a limiting voltage
called threshold voltage. Then total charge density (Qs) on substrate side of the capacitor is given by,
Qs = Qd + Qinv = − qNAW + Qinv (43)

The total positive charge on gate metal plate is equal to net negative charge in semiconductor in the
depletion region to maintain charge neutrality.
Qm = – Qs = – (Qd + Qinv) = qNAW − Qinv (44)
Q m qN A W − Qinv
⇒ = (45)

Here, Qm, Qd, Qinv and Qs are charge densities whose value will be negative for negative ions or
electrons and positive for holes or positive ions.
The charge per unit area of depletion region at threshold of inversion is given by

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [15]
QdT = –q NA Wmax (46)
Putting the expression of Wmax from equation (4.23) in above equation, we have,

NA
4εs VT n
ni NA
⇒ QdT = −q N A − 4qN A εs VT n
= (47)
q NA ni

p-type
Metal Oxide Semiconductor

qVox Depletion
region
EC

(a) Energy Bands Ei

qS qF
EFs
qV
EV

M O S

Q
Qm

(b) Charge Density W

Qd x

Qn
E

(c) Electric Field

W x
V

Vox
(d) Electric Potential
VG
s
0 W x

Fig.8 Energy band diagram , charge density, electric field and electric potential of
MOS capacitor with p-type substrate in inversion mode of operation.

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [16]

Electric Potential
Under the ideal conditions with equal value of work function of gate metal and semiconductor, the
applied voltage at the gate of MOS capacitor appears partially across oxide layer and partially across
the depletion layer as under,
VG = Vox + φs (48)
The potential difference across oxide layer is related to the capacitance of oxide layer as under,
Qm Q
Vox = = − s (49)
Cox Cox

where Qm is surface charge density at metal- oxide interface, Qs is surface charge density at oxide-
semiconductor interface and Cox is capacitance per unit area of the oxide layer.
εox
Cox = (50)
t ox

where εox is primitivity of oxide layer and tox is thickness of oxide layer.
Qs
⇒ Vox = − t ox (51)
ε ox

Note: The surface potential is considered to be positive when energy bands bend downward and it is
negative when energy bands bend upward.

Electric Field () :

The electric filed in the depletion region in semiconductor near the oxide-semiconductor interface
varies linearly in manner similar to depletion region of one sided pn junction. The maximum electric
field intensity at oxide-semiconductor interface due to acceptor ions in depletion layer is given by,
Qd qN W
d,max = = − A (53)
εs εs

Putting expression of W from equation (21) in above equation, we have,

qN A 2εs φs
d,max = (54)
εs qN A

2qN A φs
⇒ d,max = (55)
εs

Modifying above equation ,we have,

4φs 2
⇒ d,max = (56)
(2εs φs / qN A )

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [17]
2φs
⇒ d,max = (57)
W

For threshold inversion point, W = Wmax, φs = 2φF

4φF
∴ dT = (58)
Wmax

Electric field at Strong Inversion :

When MOS capacitor works in strong inversion mode there is formation of inversion layers of
charges carriers at oxide-semiconductor interface. Total charge in substrate in inversion mode is
given by equation (43). Electric intensity at oxide-semiconductor interface in substrate can be given
as,
Qs QdT + Qinv
inv = = (59)
εs εs

Total electric field at the oxide-semiconductor interface at threshold inversion point on semiconductor
side,
s = dT + inv (60)
QdT Qinv
⇒ s = + (61)
εs εs
qN A Wmax Qinv 4φF Qinv
⇒ s = − + = + (62)
εs εs W εs

According to boundary conditions at oxide-semiconductor interface, the charge densities must be

same at the interface on both sides of the interface.
So, |Qm| = |Qs| (63)
εox ox =
εs s (64)

Where εs is permittivity of semiconductor and  is electric field intensity in semiconductor at the

interface.
Example 1
An ideal MOS capacitor has boron doping-concentration fo 1015 cm–3 in the substrate. When a gate
voltage is applied, a depletion region of width 0.5 µm is formed with a surface (channel) potential of
0.2 V. Given that ε0 = 8.854 × 10–14 F/cm and the relative permittivities of silicon and silicon dioxide
are 12 and 4, respectively, the peak electric field (in V/µm) in the oxide region is___________
GATE(EC-III/2014/2M)
Solution : Ans : 2.3 to 2.5
The boron is an acceptor or p-type impurity. If doping impurity is Baron then semiconductor is
p-type.
Given, acceptor concentration, NA = 1015 cm–3

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [18]
Depletion region width, W = 0.5 µm
Surface potential, φs = 0.2 V
Relative permittivity of Si, ε rs = 12
Relative permittivity of oxide, εrox = 4
εo = 0.854 × 10–14 F/cm
If there is formation of depletion region, the MOS capacitor must be working on depletion mode with
positive gate voltage. The charge stored in depletion layer per unit area is given by,
Qd = qNA W

⇒ Qd = 1.6×10–19×1015×0.5×10–4
The maximum electric field on oxide semiconductor interface is given by,
Qd qN A W
Es = = ....(i)
ε rs εo εs

Where, εs = εrsεo
Width of depletion layer in MOS capacitor is given by,
2εs 1
W = ⋅ φs
q NA

Putting expression of W in equation (i), we have,

qN A 2εs 1 2q
Es = ⋅ ⋅=
φs ⋅ N A ⋅ φs
εs q NA εs

4.φs2 2φ
⇒ Es = = s
2ε 1 W
⋅ ⋅ φs
q NA

2 × 0.2
⇒ Es = = 0.8 × 106
0.5 × 10−6

According boundary condition of electric field at oxide-semiconductor interface,

εsEs = εoxEox
εs 12
⇒ Eox = ⋅ E s = × 0.8 × 106 = 2.4 × 106 V/m = 2.4 V/µm
εox 4

2.4 Variation of surface charge density as a function of surface potential

The variation of surface charge density in a MOS capacitor with p-type substrate is shown in Fig.9

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [19]
10–4
p-type Si

–5
10

|Qs| (C/cm2)

rons
t
10–6

elec
s
hole
10–7 2F

Flat
band
ps <NA
ps >NA ns > ps ns > NA
ps <NA
10–8 ns <NA Weak
Accumulation inversion Strong inversion
Depletion

EV EC
F
–9
10
–0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

s (V)

Fig.9 Variation of surface charge density in accumulation, depletion

and inversion modes as a function of surface potential
It observed from above figure that
1. Under flat band condition i.e. φs = 0 the net space charge is zero. This is because fixed dopant
charges are canceled by mobile carrier charges at flat band.
2. When surface potential is negative it attracts and forms an accumulation layer of majority carrier
holes at the interface. The concentration of holes at surface (ps) is more than the acceptor impurity
concentration (NA).
3. The device works in depletion mode for a positive surface potential in the range, 0 < φs < φF, In
depletion mode both concentration of holes (ps) and electrons (ns) at interface is less than the
acceptor concentration.
4. For φF < φs < 2φF, the Fermi energy (EF) at surface is in upper half at surface which implies an
n-type material, but have not yet reached at threshold inversion point. This condition is referred
as weak inversion. In weak inversion concentration of electrons is more than concentration of
holes at interface but it is less than the acceptor concentration.
5. When φs > 2φF, the electron density on surface increases rapidly with increase in surface potential
resulting in strong inversion. In strong inversion mode the concentration of electrons at interface
is more than the acceptor concentration in bulk and behaviour becomes like n-type material at
interface.
2.5 Work Function Difference
For MOS devices the work function of metal (qφm) is taken as energy required to move an electron
from the Fermi level of metal (EFm) to the conduction band of oxide (ECox) and work function of
semiconductor (qφs) is defined as the energy required to move an electron from Fermi level of
semiconductor (EFs) to conduction band of oxide. The energy required to move an electron from
conduction band of semiconductor (EC) to conduction band of oxide is called electron affinity (qX)
of the semiconductor. The location of Fermi level in a semiconductor depends on doping level of

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [20]
the semiconductor. Therefore, the work function of semiconductor depends on doping level of the
semiconductor and it may not be same as the work function of the metal. In this case the work function
of semiconductor is assumed to be greater than that of the metal. The energy band diagram of metal,
oxide and semiconductors before making the contact is shown in Fig. 10(a). When metal-oxide-
semiconductor contact is made, the Fermi energy level of metal shifts downward to align with Fermil
level of semiconductor at thermal equilibrium as shown in Fig. 10(b). Since the work functions of
metal and semiconductor remain unaltered during this process, therefore, there is downward bending
of conduction band of the oxide on metal-oxide interface. Bending of conduction band of oxide layer
under thermal equilibrium induces an electric field (o) in the oxide layer with higher potential on
semiconductor side as compared to metal side. The potential difference across the oxide layer is
Vox0 at thermal equilibrium with zero bias voltage applied across the MOS capacitor. The induced
electric field in the oxide layer repels holes away from interface of oxide-semiconductor interface
and thus a depletion layer is formed near the interface. This depletion layer has uncovered negative
bound charges of acceptor impurities. Thus a surface potential (φs0), similar to built in potential of
a depletion layer of pn junction, is developed across the depletion layer formed on semiconductor
side of oxide-semiconductor interface. The reduction of concentration of holes near the interface
results in bending of valence band downward, away from the Fermi level (EF), at the interface to
accommodate reduction in concentration of holes. Similar bend is observed in intrinsic Fermi level
(Ei) and conduction band (EC) of the semiconductor. Bending of conduction band (EC) at the interface
also increases the electron affinity(qX) at the interface. Fig.10 shows the energy band diagram of
MOS capacitor with p-type substrate at thermal equilibrium before making contact and after making
contact with zero bias voltage applied.

Conduction band of oxide Conduction Band of oxide

ECox
qVox0

qX qs
qm qX qs0
qX
Eg = 9 eV
EC
qm 

EC
EFm Ei qs0 Eg/2
EFs Ei
qF
EV EFm EFs
EV
EVox
Metal Oxide Semiconductor
(M) (O) (S) M O S
(a) Before making contact (b) After making contact
Fig.10 Energy band diagram of MOS capacitor with p-type substrate at thermal equilibrium
(a) before making contact (b) after making contact with zero bias voltage

As Fermi levels on both side of the oxide layer is at the same level, therefore, we have,
Eg
qφm + qVox0 = (qX − qφs0 ) + + qφF (65)
2
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [21]
  Eg 
⇒ Vox0 + φs0 = − φm −  X + + φF   (66)
  2q 
⇒ Vox0 + φs0 = – φms
 Eg 
where, φms = φm −  X + + φF  (67)
 2q 
⇒ φms = φm – φs (68)
Eg
where, φs = X + + φF = work function of semiconductor (69)

2q

The potential φms is known as metal semiconductor work function difference.

Similarly metal-semiconductor work function difference for a MOS-capacitor with n-type substrate
can be given by
 Eg 
φms = φm– φs = φm −  X + − φF  (70)
 2q 
Note : i. For MOS capacitor with p-substrate, the work function (φs ) of semiconductor is more than work
function (φm) of metal there work function difference (φms) is negative for MOS capacitor with
p-substrate.
ii. For MOS capacitor with n-substrate , the work function (φs ) of semiconductor is less than work
function (φm) of metal there work function difference (φms) is positive for MOS capacitor with
n-substrate.
2.6 Flat Band Voltage
It is observed from previous section that there exists a work function difference (φms) in a MOS
capacitor at thermal equilibrium due to difference in work functions of semiconductor and gate
metal. It results in shifting of Fermi level in metal as well as bending of energy bands at oxide-
semiconductor interface. An external gate voltage called Flat Band Voltage is required to be applied
at which there is no bending of energy bands at the metal-semiconductor interface and there is zero
net charge is space charge region as shown in Fig.11.
Case-I : When there is no trapped charge in oxide layer
If a gate voltage VG is applied, the potential drop across the oxide and surface potential will change
which can be given as,
VG = ∆Vox + ∆φ
= s ( Vox − Voxo ) + ( φs − φso ) (71)

⇒ VG = Vox + φs + φms (72)

Where, Vox is voltage drop across oxide layer and φs is surface potential.
At flat band there is no bending of energy bands at the metal-semiconductor interface so the surface
potential is zero at flat band condition.
∴ φs = 0 (73)
The space charge in depletion layer is also zero at flat band condition so the voltage drop across the
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [22]
oxide layer is zero at flat band.
∴ Vox = 0 (74)
The flat band voltage is obtained by putting φs = 0 and Vox = 0 in equation (72),
i.e. VFB = φms = φm– φs (75)
Putting this relation in equation (4.72), we have,
VG = Vox + φs +VFB (76)
For the MOS capacitor with p-substrate, the work function (φs ) of semiconductor is more than work
function (φm) of metal, therefore, flat band voltage is negative for MOS capacitor with p-substrate.
Similarly, for the MOS capacitor with n-substrate, the work function (φs ) of semiconductor is less
than work function (φm) of metal, therefore, flat band voltage is negative for MOS capacitor with
p-substrate.

Case-II : Considering work function difference as well as trapped charges of oxide layer
The oxide layer always contains the trapped positive charges due to imperfection in the oxide (SiO2)
layer. If the effect of positive trapped charges in oxide layer is also taken into account then the flat
band voltage is required will be function of work function difference and density of trapped positive
charge in the oxide layer. The trapped positive charge normally appears close to oxide-semiconductor
interface.
Oxide Conduction Band
Oxide Conduction Band

qVox0

qX

qm 

EC EC
qs0 Eg/2 Eg/2
Ei EFm Ei
qF VFB qF
EFm EFs EFs
EV EV

M O S M O S

(a) At thermal equilibrium (b) At flat band

Fig. 11 Energy band diagram of MOS capacitor at (a) At thermal equilibrium (b) At flat band
Let equivalent trapped charge per unit area located in oxide near oxide-semiconductor interface is Qx.
The metal-semiconductor work function difference for a zero bias gate voltage is given by
− φms = Voxo + φso (77)
If no biasing voltage is applied then there is no charge in the semiconductor. The trapped oxide
charges in the oxide layer induces charges on the metal-oxide interface such that,

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [23]
Qm + Qx = 0 (78)
⇒ Qm = − Qx (79)
The charge distribution due to trapped charges on oxide layer with zero bias voltage applied to the
MOS capacitor is shown in Fig. 12.

Metal Oxide Semiconductor

Qm Qx

Fig.12 Charge distribution in MOS capacitor at flat band

The voltage across the oxide layer is given by,
Qm
Vox = (80)
Cox
Qx
⇒ Vox = − (81)
Cox

In flat band condition oxide-semiconductor surface potential is zero as φs = 0. Then gate voltage VG
given by equation (4.49) become a flat band voltage,VFB as under,
Qx
∴ VFB = Vox + φmx = − + φmx (82)
Cox

Example 2
A MOS capacitor is fabricated on p-type Si (silicon) where the metal work function is 4.1 eV and
electron affinity of Si is 4.0 eV. EC–FF = 0.9 eV, where EC and EF are the conduction band minimum
and the Fermi energy levels of Si, respectively. Oxide εr = 3.9, ε0 = 8.85 × 10–14 F/cm, oxide thickness
tox = 0.1µm and electronic charge q = 1.6 × 10–19 C. If the measured flat band voltage of the capacitor
is –1V, then the magnitude of the fixed charge at the oxide-semiconductor interface, in nC/cm2, is
_______.
GATE(EC-II/2017/2M)
Solution : Ans. : 6.85 to 6.95
Given, qfm = 4.1 eV
4.1eV 4.1eV
⇒ = =
fm = 4.1V
q 1.6 × 10−19

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [24]
Oxide Conduction Band

qVox0

qX

qm 

EC
qs0 Eg/2
Ei
EC  EF
EFm EF
EV

M O S
Electron affinity of Si, qX = 4.0 eV
4.0eV 4.0eV
⇒ X ==
= 4.0V
q 1.6 × 10−19

Difference of energy levels,

EC – FF = 0.9 eV
EC − EF = 0.9eV
=
0.9eV
0.9V
= q 1.6 × 10−19
q

Using above figure the work function difference of MOS capacitor is given by,
qfms = qfm – (qX + EC – FF )
 E − EF 
⇒ fms = φm −  X + C 
 q 

⇒ fms = 4.1 – (4.0 + 0.9) = – 0.8 V

The flat band voltage with fixed trapped charge in oxide layer is given by,
Qx
VFB = φms −
Cox

Qx
⇒ VFB = φms − t ox
ε rox εo

From the given data,

εrox = 0.9, ε0 = 8.85 × 1014 F/cm, tox = 0.1 µm = 0.1 × 10–4 c.m., VFB = –1V
Qx
⇒ –1 = −0.8 − .t ox
ε rox εo

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [25]
0.2 × 3.9 × 8.85 × 10−14
⇒ Qx = = 6.903 nC/cm2
0.1 × 10−4

2.7 Threshold Voltage

The threshold voltage is applied gate voltage at which threshold inversion point occurs in
semiconductor near the oxide-semiconductor interface of the MOS capacitor. In MOS capacitor,
the threshold inversion point occurs when surface potential, φs = 2φF. The width of depletion layer in
semiconductor region is maximum at threshold inversion point. Fig.13 shows the charge distribution
in MOS capacitor at threshold inversion point for a p-type semiconductor substrate.
At the threshold inversion point the depletion layer width near oxide-semiconductor interface in
semiconductor is maximum. If Qx is trapped positive charge density in oxide, QmT is positive charge
density per unit area metal gate at threshold inversion point. The sum of all the charges in metal,
oxide and substrate must be zero to maintain electrical neutrality.
Qx + QmT + QsT = 0 (83)
⇒ QmT = − QsT − Qx (84)
The maximum space charge per unit area at oxide-semiconductor interface is given by,
QsT = QdT = − q NA Wmax (85)

Metal Oxide Semiconductor

Qm Qx

Wmax

Fig.13 Charge distribution in MOS capacitor with p-substrate threshold inversion point

The applied gate voltage is given in terms of surface potential as,

VG = Vox + φs + φms (86)
At threshold inversion point, φs = 2φF and gate voltage is equal to the threshold voltage creating
electrons inversion layer of charge at oxide-semiconductor interface.
VT VoxT + 2φF + φms
= (87)

Where VoxT is voltage across the oxide at the threshold inversion point. The energy band diagram of
MOS capacitor with p-substrate and an applied positive gate voltage, VG under threshold inversion
point is as shown in Fig.14.

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [26]
The voltage across oxide layer at threshold inversion point can be given by,
Q mT Q + Qx Q + Qx
VoxT = =
− sT =
− dT (88)
Cox Cox Cox

Vox

EC

Ei
F
s =2F EFs
EV
VG =VT
Wmax

M O S
Fig.14 Energy band diagram of MOS capacitor with p-substrate at threshold inversion point

Then threshold voltage becomes as under,

QdT + Q x
VT = − + φms + 2φF (89)
Cox

QdT Q x
⇒ VT = − − + φms + 2φF (90)
Cox Cox

QdT
⇒ VT = − + 2φF + VFB (91)
Cox

Qx
Where, VFB = − + φmx = flat band voltage.
Cox

The charge density at interface at threshold inversion point is given by,

QsT = QdT = –q NA Wmax (92)
qN A Wmax
⇒ =VT + 2φF + VFB (93)
Cox

2.8 Gate Voltage at Strong Inversion

There is condition of strong inversion in a MOS capacitor when the gate voltage becomes more than
the threshold voltage. The width of depletion layer is fixed at Wmax at strong inversion and charge
density of depletion layer is same as its threshold value. There is additional charge density on oxide-
semiconductor interface due to inversion layer. The surface potential across the depletion is also
fixed at φs= 2φF at strong inversion. Therefore, if gate voltage is increased beyond threshold voltage

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [27]
then additional voltage drops across the oxide layer only.
For strong inversion the charge of substrate,
Qs = QdT + Qinv (94)
If trapped positive charge in oxide layer is also considered then equivalent charge on metal gate,
Qm = − (Qs + Qx )= − QdT − Qinv− Qx (95)
The voltage drop across the oxide layer,
QdT + Qinv + Q x
Vox = = − (96)
Cox Cox

From equation (86), the gate voltage is given by,

VG = Vox + φs + φms
QdT + Qinv + Q x
⇒ VG = − + φms + φs (97)
Cox

Qinv QdT Q
⇒ VG = − − + 2φF − x + φms (98)
Cox Cox Cox

Putting expression of flat band voltage from equation (81) in above equation, we have,
Qinv QdT
⇒ VG = − − + φs + VFB (99)
Cox Cox

For strong inversion region of operation, φs = 2φF

Qinv QdT
⇒ VG = − − + 2φF + VFB (100)
Cox Cox

Putting expression of threshold voltage from equation (91) in above equation, we have,
Q
⇒ VG =
− inv + VT (101)
Cox

QdT
where, VT =− + 2φF + VFB (102)
Cox

The charge density of inversion layer can be obtained from equation (101), as under,
Qinv =
−Cox (VG − VT ) (103)

Example 3
A voltage VG is applied across a MOS capacitor with metal gate and p-type silicon substrate at T = 300 K.
The inversion carrier density (in number of carriers per unit area) for VG = 0.8 V is 2 × 1011 cm–2 For VG =
1.3 V, the inversion carrier density is 4 × 1011 cm–2. What is the value of the inversion carrier density for
VG = 1.8 V?

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [28]
(a) 4.5 × 1011 cm–2 (b) 6.0 × 1011 cm–2
(c) 7.2 × 1011 cm–2 (d) 8.4 × 1011 cm–2
GATE(EC-II/2016/2M)
Solution : Ans. (b)
Given, T = 300 K
The inversion carrier density of MOS capacitor with p-substrate in terms of gate voltage is given by
Qinv = − Cox(VG – VT)
where Cox is capacitance per unit area of oxide and VT is threshold voltage.
Given charge is not mentioned to be negative that means it must be magnitude of the charge. So,
taking only magnitude, we have,
Qinv = Cox(VG – VT) .....(i)
Case-I Qinv = 2 × 1011 cm–2
when VG = 0.8 V
⇒ 2 × 1011 = Cox (0.8 – VT)
2 × 1011
⇒ Cox = ....(ii)
0.8 − VT

Case-II Qinv = 4 × 1011 cm–2

when VG = 1.3V.
⇒ 4 × 1011 = Cox (1.3 – VT)
4 × 1011
⇒ Cox = ....(iii)
1.3 − VT

From (i) and (ii), we have,

2 × 1011 4 × 1011
=
0.8 − VT 1.3 − VT

⇒ 1.3 – VT = 1.6 – 2VT

⇒ VT = 0.3V
Putting value of VT in equation (ii), we have,
2 × 1011
Cox = = 4 × 1011 F/cm2
0.8 − 0.3

When VG = 1.8 V the inversion charge density can be obtained values of Cox and VT in equation (i) as
under,
Qinv = 4 × 1011 (1.8 – 0.3) cm–2
⇒ Qinv = 6.0 × 1011 cm–2

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [29]
2.9 Capacitance-Voltage Characteristics of MOS Capacitor
The capacitance of MOS device is function of applied voltage and it is given by,
dQ
C =
dV

Under ideal condition it is assumed that there is no charge trapped in oxide as will as in oxide-
semiconductor interface. There are three operating conditions in MOS capacitor which are
accumulation, depletion and inversion.
Case-I : Ideal condition
A. Accumulation Mode
In accumulation mode of operation of MOS capacitor the metal gate is given negative potential
which induces accumulation layer of holes in the substrate at the oxide-semiconductor interface. The
capacitance per unit area of MOS capacitor for accumulation mode is oxide capacitance which is
given by,
ε ox
C(acc.)
= C= ox (104)
t ox
The charge distribution in accumulation mode of a MOS capacitor with p-substrate is as shown in
Fig.15.

|dQ|

+Qs

x
–Qm

|dQ|

M O S
Fig.15 Charge distribution in MOS capacitor with p-substrate in accumulation mode

B. Depletion Mode
A MOS capacitor with p-type substrate works in depletion mode when metal gate is connected to
small positive voltage. The applied small positive potential induces a space charge region in substrate
near oxide-semiconductor interface. The metal acquires a positive charge due to applied positive
voltage and depletion region near interface contains the negative bound charges of acceptor impurity.
The charge distribution in depletion mode of a MOS capacitor with p-substrate is as shown in Fig.16.

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|dQ|

+Qm
W
x

+Qs |dQ|

M O S
Fig.16 Charge distribution in MOS capacitor with p-substrate in depletion mode

In depletion mode, the MOS capacitor offers two capacitances appearing in series. One capacitance
is due to oxide layer and second capacitance is due to formation of depletion layer in semiconductor
near oxide-semiconductor interface. The capacitance of oxide layer is fixed where as capacitance of
depletion layer is function of applied bias voltage. The total capacitance per unit area in depletion
mode is given by,
Cox Cd
C(dep) = (105)
Cox + Cd

where Cd is capacitance per unit are of depletion region.

The capacitance per unit are of depletion region is given by,
εs
Cd = (106)
W

Where εs is permittivity of semiconductor and W is width of depletion layer.

C ε /t
∴ C(dep) = ox = ox ox (107)
C ε W
1 + ox 1 + ox ⋅
Cd t ox εs
ε os
⇒ C(dep) = (108)
ε
1 + ox ⋅ W
εs

The capacitance C(dep) decreases with increase in width of depletion layer. The width of depletion is
maximum at Threshold of inversion point threshold gate voltage. Therefore, capacitance offered by
MOS capacitor is minimum at threshold inversion point. The minimum capacitor of MOS capacitor
can be given by,
εox
∴ C′min = (109)
εox
t ox + ⋅ Wmax
εs

4εs 1 4εs 1 N
Where, Wmax = ⋅ ⋅ φFp = ⋅ ⋅ VT n A (110)
q NA q NA ni

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C. Inversion mode
In inversion mode of operation, it is the charge of inversion layer and gate metal which varies with
applied gate voltage. When gate voltage becomes more than the threshold value the width of depletion
layer becomes maximum and thus the charge in depletion region does not change when gate voltage
is increased above threshold value. Fig. 17 shows the charge distribution of MOS capacitor with
p-substrate in inversion mode.
The capacitance offered by MOS capacitor in inversion mode is oxide capacitance which is given by
εox
C(inv)
= C= ox (111)
t ox

|dQ|
Wmax
+Qm
x
–Qs
–Qi
|dQi|

M O S
Fig.17 Charge distribution in MOS capacitor with p-substrate in inversion mode
The variation in capacitance of MOS of a MOS capacitor as a function of gate voltage is shown in
Fig. variate min MOS capacitance w.r.t. gate voltage is shown in Fig.18

Cd C

Accumulation Strong inversion

Cox
ion
De

s
ple

nver
t
ion

ki
Wea

Cmin

VFB 0 VT VG
Fig.18 Variation in MOS capacitance with gate voltage
Case-II : Effect of frequency
In an inversion mode of MOS capacitor with p-type substrate, there is formation of inversion layer of
electrons at oxide-semiconductor interface. The inversion layer of electron is formed due to diffusion
of electrons from p-substrate across the depletion layer and due to thermal generation of electron-
hole pairs within the space charge region. If MOS capacitor is subjected to an a.c. voltage the
concentration of electrons in inversion layer cannot change instantaneously. In such case capacitor-

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voltage (C-V) characteristics of MOS capacitor is function of frequency of the ac signal. At very
high frequency the charge of inversion fails to respond to change in gate voltage. At high frequencies
the differential change in charge occurs with gate voltage due to change of space charge width. The
capacitance of MOS capacitor is at its minimum value at high frequency as shown in Fig.19.

Accumulation Low Frequency

Cox

High Frequency
Cmn
inversion
Va
0
Fig.19 Variation in MOS capacitance with frequency
High frequency in above figure corresponds to 10 MHz and low frequency corresponds to it 10 kHz.
Case-III. Effect of oxide trapped charges
A MOS capacitor can have fixed trapped positive charge in oxide layer. The flat band voltage becomes
more negative and threshold voltage reduces due to positive trapped charge in the oxide layer of a
MOS capacitor with p-type substrate.

Example 4
Common Data for Question A & B :
The figure shows the high-frequency capacitance-voltage (C-V ) characteristics of a Metal/SiO2 /
silicon (MOS) capacitor having an area of 1×10–4 cm2. Assume that the permitivities (ε 0 ε r ) of

silicon and SiO2 are 1×10–12 F/cm and 3.5×10–13 F/cm respectively.

C
7pF
1pF
0 v

A. The gate oxide thickness in the MOS capacitor is

(a) 50nm (b) 143nm
(c) 350 nm (d) 1 µm
GATE(EC/2007/2M)
B. The maximum depletion layer width in silicon is
(a) 0.143 µm (b) 0.857 µm
(c) 1 µm (d) 1.143 µm
GATE(EC/2007/2M)

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Solution:
A. Ans.(a)
The C-V characteristics of MOS capacitor at frequency operation are shown below,

C Depletion
Strong Gate
Accumulation
Inversion
7pF
SiO2 tox

P-substrate
1pF
MOS
VT VG

When gate voltage is negative there is accumulation of holes below oxide layer in MOS capacitor
with p-substrate.
In such case oxide layer only offers a capacitance which is given by,
ε A
Ci = ox ......(i)
t ox

where,
εox → Permitivity of oxide layer
A → Area of gate electrode or area of capacitor
tox → Thickness of oxide
Given, εox = 3.5 × 10–13 F/cm
A = 1 × 10–4 cm–2
From given characteristics, C
Ci7 =
pF7 pF Ci

C 1pF

V
Putting above values in equation (i), we have,
3.5 × 10−13 × 1 × 10−4
7 × 10–12 =
t ox

3.5 × 10−17 1
⇒ tox = = × 10−5 cm
7 × 10−12 2

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⇒ tox = 50 nm
B. Ans.(b)
When voltage is more than threshold voltage the capacitance of MOS capacitor is minimum. When
gate voltage applied is positive a depletion layer is also formed in p-substrate below oxide layer. This
depletion layer also offers a capacitance. Both oxide layer and depletion layer capacitances applies
in series. The equivalent capacitance of combination is given as,

Ci

Cd

Ci C d
C =
Ci + C d

εs
Where, Cd = = Depletion layer capacitor
W

W = Width of depletion layer

εs = Permittvity of Si
Beyond VT , Cd is minimum and W is maximum.
Ci Cd min
∴ C = .....(ii)
Ci + Cd min

∴ Cd min = ....(iii)
max

From given characteristics,

C = 1 pF & Ci = 7 pF
7 × Cd,min
∴ 1 =
7 + Cd,min

⇒ 7 + Cd min = 7 Cd min
7
⇒ Cd min = pF
6

Putting Cd, min in equation (iii), we have,

7 εA
× 10−12 = s
6 Wmax

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Given, εs = 1×10–12 F/cm
A = 1 × 10–4 cm–2
7 1 × 10−12 × 1 × 10−4
⇒ × 10−12 =
6 Wmax

6 −4
⇒ Wmax = × 10 cm
7

⇒ Wmax = 0.857 µm
Example 5
In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness
is 100 nm. The permittivities of the semiconductor and the oxide layer are εs and εOX respectively.
ε
Assuming s = 3, the ratio of the maximum capacitance to the minimum capacitance of this MOS
εOX
capacitor is ..........
GATE(EC-II/2015/2M)
Solution : Ans.( 4.3 to 4.4)
Given thickness of oxide layer,
tox = 10 nm
Maximum thickness of depletion layer,
Wmax = 100 nm
Ratios of permittivity of semiconductor to oxide,
εs
= 3
εox

The maximum capacitance of MOS capacitor is equal to capacitance of oxide layer which is given
by,
εox
Cmax = Cox = .....(i)
t ox

The minimum capacitance of MOS capacitor is observed when depletion layer thickness is maximum.
The minimum capacitance of MOS capacitor is equal to series combination of capacitance of oxide
layer and lowest capacitance of depletion layer.
Cox Cd,min
∴ Cmin = .....(ii)
Cox + Cd min

εs
where, Cdmin =
Wmax

From (i) and (ii), we have,

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Cmax C + Cd min C
= ox = 1 + ox
Cmin Cd min Cd min

Cmax ε W
⇒ = 1 + ox ⋅ max
Cmin t ox εs

Cmax 1 100 × 10−9

⇒ = 1 + × =4.33
Cmin 3 10 × 10−9

3 Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)

MOS Field Effect Transistor (MOSFET) has become most popular device due to it design on
integrated circuits fabricated on single Silicon chip. It is also known as Insulated Gate Field Effect
Transistor (IGFET).

3.1 Physical Structure and Symbols of MOSFET

A MOSFET has four terminals called Source (S), Drain (D), Gate (G) and Body (B). The body
terminal (B) is normally shorted with the source terminal. So, only source, drain and gate terminals
will be discussed in the following section. MOSFET has a conducting channel between source and
drain to provide path for the drain current. The source is the terminal at which majority carriers enter
into the channel and drain is the terminal at which the majority carriers leave the channel. The gate is
control terminal of MOSFET. The potential of gate terminal controls the drain current of MOSFET.
Therefore, MOSFET is a voltage controlled device and it can be used as a voltage controlled current
source. The construction of MOSFET is symmetrical so the functions of source and drain can be
interchanged in a MOSFET. The gate terminal is separated from body of MOSFET by an oxide layer
which acts as an insulating layer. The

Types of MOSFET
i) Enhancement type: (a) n-channel (b) p-channel.
ii) Depletion type: (a) n-channel (b) p-channel.

Enhancement type n-channel MOSFET

An enhancement type n-channel MOSFET consists of p-type substrate on single Si wafer in which
two n+ layers are diffused to act as source and drain. A thin layer of oxide (SiO2 ) is grown on
the surface of substrate between drain and source regions. The layer of oxide act as an insulator
between gate and body of MOSFET. A thin layer of metal is deposited on oxide layer to act as a gate
electrode of the MOSFET. Metallic contacts are also made with source, drain and body for external
connections of the MOSFET. An n-channel MOSFET is alternatively known as NMOS transistor.

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Fig.20 shows the physical structure and symbols of a n-channel enhancement type MOSFET.

Source Gate Drain

(S) (G) (D)

Gate
metal Oxide

n+ n+

D D D
p - substrate
G G G
B
Substrate or
Body (B) S S S
Fig. 20 Physical structure and symbols of enhancement type n-channel MOSFET

Enhancement type p-channel MOSFET

The physical structure of an enhancement type p-channel MOSFET is similar to that of enhancement
type n-channel MOSFET. The only difference is that the substrate is n-type material and p+ layers form
source and drain of the MOSFET. A p-channel MOSFET is alternatively known as PMOS transistor.
Fig. 21 shows the physical structure and symbols of enhancement type p-channel MOSFET.

Source Gate Drain

(S) (G) (D)

Gate
metal Oxide

p+ np +

D D D
n - substrate
G G G

Substrate or
Body (B) S S S
Fig. 21 Physical structure and symbols of enhancement type p-channel MOSFET

Depletion type n-channel MOSFET

The physical structure of a depletion type n-channel MOSFET is similar to n-channel enhancement
type MOSFET except that it has a thin n-type layer below the oxide layer which forms a conducting

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channel between source and drain regions. Fig.22 shows the physical structure and symbols of a
depletion type n-channel MOSFET.
Source Gate Drain
(S) (G) (D)

Gate
metal Oxide

n+ n+

n-channel
D D D
p - substrate
G G G
SS
Substrate or
Body (B) S S S

Fig. 22 Physical structure and symbols of depletion type n-channel MOSFET

Depletion type p-channel MOSFET

The physical structure of a depletion type p-channel MOSFET is similar to p-channel enhancement
type MOSFET except that it has a thin p-type layer below the oxide layer which forms a conducting
channel between source and drain regions. Fig.23 shows the physical structure and symbols of a
depletion type p-channel MOSFET.

Source Gate Drain

(S) (G) (D)

Gate
metal Oxide

p+ np +

p-channel
D D D
n - substrate
G G G
SS
Substrate or
Body (B) S S S
Fig. 23 Physical structure and symbols of depletion type p-channel MOSFET

3.2 Operation of MOSFET

Case-I: Operation of Enhancement type MOSFET
The n-channel enhancement type MOSFET is most commonly used transistor among all the

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MOSFETs. Enhancement type n-channel MOSFET is a MOS capacitor with two n+ regions diffused
in the p-type substrate. When the gate terminal is connected to a positive potential, it forms a depletion
layer below the oxide-semiconductor interface between source and drain regions. Fig.24 shows the
biasing arrangement of an enhancement type n-channel MOSFET. If gate voltage (VG) is increased,
there is accumulation of electrons at the oxide-semiconductor interface.
VDS
_ +
VGS G
_ +
D
S
++ + + ID
D
__ ___ ID
n+ n+
G +
VDS _
+
p - substrate VGS _ S

B

Fig. 24 Operation of enhancement type n-channel MOSFET with positive voltage at gate
and n-channel between drain and source regions.

If gate voltage becomes equal to a value called threshold voltage (VT) then sufficient number of
electrons are accumulated in the region below oxide layer between source and drain regions forming
a conducting channel of inversion layer. This channel provides a path for current flow from drain to
source due to drain to source voltage. In a MOSFET, the source is the terminal at which majority carriers
enter into the channel and drain is the terminal at which majority carriers leave the channel. In n-channel
MOSFET, the electrons are majority carriers so the electrons must enter at source and leave at drain,
therefore, negative terminal of battery is connected at the source and positive terminal is connected
to the drain and drain current flows from drain to source. Reverse is true for a p-channel enhancement
type of MOSFET. Since, the drain current is due to majority carriers only, therefore, MOSFET is an
example of unipolar device.

Note: The operation of enhancement type p-channel MOSFET is similar to that of enhancement type
n-channel MOSFET. In p-channel MOSFET the conducting channel is formed by holes accumulated
below the oxide-semiconductor interface between drain and source regions. The voltages VGS , VDS
and drain current ID are negative in case of a p-channel MOSFET.

Case-II: Operation of depletion type MOSFET

The depletion type n-channel MOSFET , the electrons in n-layer diffused between source and
drain regions form a conducting channel. Fig.24a shows the biasing arrangement of a depletion type
n-channel MOSFET. When the gate terminal is connected to a negative potential, it forms a depletion
layer below the oxide-semiconductor interface between source and drain. If negative bias voltage
(VG) at gate is increased, the width of depletion layer in the channel increases and effective width of
the conducting channel formed by n-layer decreases and hence the channel resistance increases and

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drain current decreases. Since, the drain current decreases with increase in biasing voltage at gate
terminal therefore, this MOSFET is known as depletion type of MOSFET. A depletion type MOSFET
has non-zero current when gate voltage is zero. The bias voltage at gate terminal of depletion type
n-channel MOSFET can be positive or negative. The drain current increases with increase positive
voltage applied at gate and it decreases with increase in negative bias voltage applied at gate.
Therefore, the depletion type MOSFET can work in depletion as well as enhancement modes of
operation. VDS
_ +
VGS G
_ +
D
S
++ + + ID
D
_ ___ ID
n+ n n+
G +
VDS _
Depletion layer
+
p - substrate VGS _ S

Fig. 24a Operation of depletion type n-channel MOSFET with negative voltage at gate and
positive voltage between drain and source regions.

Note: The operation of depletion type p-channel MOSFET is similar to that of depletion type n-channel
MOSFET. In depletion type p-channel MOSFET, the conducting channel is formed by holes in p-layer
diffused between drain and source regions. The voltages VGS, VDS and drain current ID are negative
in case of a p-channel MOSFET.

3.3 Output or Drain characteristics of MOSFET

I. Enhancement type n-channel MOSFET

The drain characteristics of MOSFET gives the variation of drain current (ID) as a function of drain
to source voltage (VDS) and gate to source voltage (VGS). Mathematically, the drain characteristics of
a MOSFET are defined by,
ID = f(VDS,VGS) (112)
It has been seen in previous section the gate to source voltage is used to induce a conducting n-channel
between source and drain regions. The n-channel forms the inversion layer of electrons below oxide
layer between the source and drains regions of the MOSFET. Fig.25 shows the drain characteristics
of an enhancement type n-channel MOSFET. The drain characteristics of MOSFET can be divided
into three regions called ohmic, saturation and cutoff regions depending upon the value of gate to
source and drain to source voltages.

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Saturation region
ID
VDS,sat= VGSVT
VGS4 > VGS3
Ohmic or
Triode
region VGS3 > VGS2

VGS2 > VGS1

VGS1 > VT

VGS=VT

Cut off region VDS

Fig. 25 Drain characteristics of n-channel enhancement type MOSFET

Ohmic or Triode or Linear region
When voltage (VGS) applied between gate and source terminals is more than the threshold voltage, an
inversion layer of electrons is induced in substrate region below gate electrode forming a conducting
channel ash shown in Fig. 24. If drain to source voltage (VDS) is increased from zero, the electrons
in channel start drifting from source to drain. Since current flows in the direction opposite to that of
electrons, therefore, a current called drain current (ID) starts flowing through the channel from drain
to source. The concentration of charge carriers in the channel increases with increase in the gate to
source voltage. Therefore, the drain current increases with increase in VGS as shown in the figure.
When VDS is increased within the range 0 < VDS < (VGS − VT ) there in increase of drift velocity of
electrons in the channel and thus the drain current increase. This limiting value of VDS = (VGS − VT ),
defines a boundary between the ohmic and saturation region and it is denoted by as VDS,sat. It should
be observed from the Fig.25 that value of VDS,sat increases with increase in voltage VGS. The slope of
drain characteristic gives the conductance of the channel of MOSFET and it changes with change
in voltage VGS in the ohmic region. The conductance of the channel of MOSFET in ohmic region
is proportional to the excess voltage (VGS − VT). This excess voltage is known as overdrive voltage.
Thus, in ohmic region of operation a MOSFET behaves like a voltage controlled resistor or voltage
variable resistor(VVR). The resistance of MOSFET varies linearly with voltage VGS in ohmic region
so ohmic region is a also linear region.
In the switching applications such as digital circuits, a MOSFET behaves like a closed switch with a
finite resistance in ohmic region of operation. Thus a MOSFET has a finite ON state resistance unlike
a BJT which has negligible ON state resistance.
The drain current of enhancement type n-channel MOSFET in ohmic region is function of drain to
source voltage as well as gate to source voltage and it is given by
 1 2
I D =
µ n Cox [(VGS − VT ) VDS − VDS ] (113)
L 2

where,  is width of the channel, L is length of the channel, k is process transconductance parameter
and VT is threshold voltage of the MOSFET
It should be noted here that symbol ‘’ used is width of channel in MOSFET.

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Saturation Region or Active Region
When gate to source voltage is more than the threshold voltage and drain to source voltage is increased
above the limiting value of VDS,sat, the MOSFET enters into the saturation region of operation. The
operation of MOSFET in saturation region can be explained by considering effect of voltage VDS on
channel depth as shown in Fig. 26. It can be observed from the Fig. 26 that the voltage VDS appears
across complete length, L, of the channel. If source terminal is taken at ground reference then drain
to source voltage increases from 0 at source end to VDS at drain end. If gate to source voltage is
considered to be fixed at particular value, VGS , then the voltage across complete length of the channel
varies from VGS at source end to (VGS − VDS) at drain end. The depth of channel is proportional to the
voltage across the channel, therefore, the channel depth is maximum at the source end and minimum
on drain end of the channel as shown in Fig. 26.
VDS

_
+
VGS
G
S _ D
+

Oxide
VDS
Source channel Drain
n+ n+
L
_ VDS +
Fig. 26 Effect of VDS in channel depth in n-channel enhancement type MOSFET

Thus channel acquires a tapered or wedge shape when voltage VDS is increased from zero. The depth
of channel on drain end further reduces with increase in the voltage VDS . When the voltage across
the channel VGD or (VGS − VDS) becomes equal to VT or alternatively VDS becomes equal to a limiting
value equal to VGS − VT ( = VDS,sat), the channel is pinched off and its depth becomes negligible at
drain end the drain current reaches at saturation level. It can be seen from drain characteristics in Fig.
25 that the drain current no more varies with voltage VDS for VDS > (VGS − VT ) because the channel
is under pinched off condition for this voltage range. Thus, the drain current in saturation region is
independent of drain to source voltage.
The drain current in saturation region is the function of gate to source voltage and it is given by

I D =
µ n Cox (VGS − VT ) 2 (114)
2L

It is observed from above equation that the drain follows the square law relation with gate to source
voltage and it is independent of drain to source voltage. In saturation region MOSFET can be used as
an ideal current source whose value is controlled by VGS. A MOSFET works like a transconductance
amplifier in saturation region of operation.
Cut off region
The n-channel MOSFET works in cutoff region when gate to source voltage is less than the threshold

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voltage. Therefore cutoff region is defined by,
VGS ≤ VT (115)

In cutoff region the drain current is negligible and MOSFET behaves like an open switch.

Note: Summary of conditions of operation of n-channel MOSFET in different regions of operation,

i. For ohmic region, VDS < VGS − VT

ii. At boundary between ohmic and saturation regions, V=

DS VGS − VT

iii. For saturation region or pinched off region, VDS > VGS − VT

iv. For cutoff region, VGS ≤ VT

II. Enhancement type p-channel MOSFET

The output characteristics of enhancement type p-channel MOSFET are similar to that of enhancement
type n-channel MOSFET as shown in Fig. 27. However, the voltages VGS, VDS and current ID are
negative for a p-channel MOSFET.
The drain current enhancement type p-channel MOSFET in ohmic region is function of drain to
source voltage as well as gate to source voltage and it is given by
 1 2
ID =
µ p Cox [(VSG + VT ) VSD − VSD ] (116)
L 2

The drain current in saturation region is the function of gate to source voltage and it is given by

I D =
µ p Cox (VSG + VT ) 2 (117)
2L

It should be noted here that mobility here is mobility of holes (µp)and sign of threshold voltage is
reversed. The threshold voltage is negative for an enhancement type p-channel MOSFET.
ID

Cut off region

VGS=VT VDS
VGS= 3V

VGS= 4V

VGS= 5V
Ohmic or
Triode
VGS= 6V region

Saturation region

Fig. 27 Drain characteristics of p-channel enhancement type MOSFET

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Note: Conditions for operation of p-channel MOSFET in different regions of operation,

i. For ohmic region PMOSFET, VDS > VGS - VT or VSD < VSG - |VT|
ii. At boundary between ohmic and saturation regions,
VDS = VGS - VT or VSD = VSG - |VT|
iii. For saturation region or pinched off region,
VDS < VGS - VT or VSD > VSG - |VT|
iv. For cutoff region, VGS ≥ VT or VSG ≤ |VT|
v. The voltages VDS, VGS and VT are negative for p-channel MOSFET.
vi. The voltage difference (VGS - VT ) is also known as Gate overdrive voltage. (VOV)

III. Depletion type n-channel MOSFET
The depletion type MOSFETs are used rarely. The output characteristics of depletion type n-channel
MOSFET are similar to that of enhancement type n-channel MOSFET as shown in Fig. 28. In
depletion type of MOSFET the gate to source voltage can be positive or negative. When the gate
voltage is positive the drain current increases with increase in the voltage so it works in enhancement
mode and when gate to source voltage is negative and drain current decreases with gate voltage so
it works in depletion mode. When a negative voltage is applied at gate terminal a depletion layer is
formed in n-channel. The n-channel may be completely occupied by the depletion region at a critical
gate voltage called pinch off voltage and drain current at pinch off becomes zero. This region of
operation is called pinch off or cutoff region. So, the cutoff voltage for depletion type MOSFET is
known as pinch off voltage.
Saturation region
ID
VDS,sat= VGSVT
VGS4 > VGS3
Ohmic or
Triode
region Enhancement
VGS3 > 0
mode

VGS2= 0
IDSS
VGS1 < 0 Depletion
mode
VGS=VT

Pinch off or Cut off region VDS

Fig. 28 Drain characteristics of n-channel depletion type MOSFET

The drain current in saturation region is the function of gate to source voltage and it is given by
2
 V 
=I D I DSS 1 − GS  (118)
 VT 

Where IDSS is drain current when gate is short circuited with the source terminal and VT is threshold

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or pinch off voltage.
The current IDSS for depletion type n-channel MOSFET is given by,
µ C W 2
I DSS = n ox VT (118a)
2 L
Note : i An n-channel depletion type MOSFET works in depletion mode when VGS is negative and in
enhancement mode when VGS is positive.
ii. A depletion type MOSFET can work in depletion as well as enhancement modes whereas the
enhancement type MOSFET can work in enhancement mode only

Example 6
An enhancement-type NMOS transistor with VT = 0.7 V has its source terminal grounded and a 1.5
V dc applied to the gate. In what region does the device operate for (i) VD = + 0.5 V (ii) VD = 3V
Solution : (i) Triode ; (ii) Saturation;
Given, VT = 0.7 V, VGS = 1.5 V
VGS – VT = 1.5 − 0.7 = 0.8V
(i) VDS = 0.5 V
NMOS works in ohmic region when VDS < (VGS – VT).
So when VDS = 0.5 V given NMOS operates in Triode or ohmic region.
(ii) VDS = 3V
NMOS works in saturation region when VDS > (VGS – VT). So, for VDS = 3V, the given NMOS works
in saturation of operation.

3.4 Transfer characteristic of MOSFETs

Case-I: Transfer Characteristics of enhancement type n-channel MOSFET
Transfer characteristic of MOSFET gives the variation of output drain current with respect to the
input gate to source voltage for a fixed drain to source voltage. The drain current varies differently
with respect to gate to source voltage for ohmic and saturation regions therefore, a MOSFET has
different transfer characteristics for ohmic and saturation regions.

Transfer characteristics for ohmic or linear region

The drain current for ohmic region of operation is given by,

 1 
ID = µ n Cox  (VGS − VT ) VDS − VDS2  (119)
L  2 

For small value of VDS, the drain current can be approximated as,

ID = µ n Cox (VGS − VT ) VDS (120)
L

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [46]
 
⇒ ID = µ n Cox VDS VGS − µ n Cox VT VDS (121)
L L
⇒ ID = mVGS + c
The above equation represents of straight line in ID Vs VGS plane with a slope,


m = µ n Cox VDS (122)
L

It is observed here that ID varies linearly with VGS for fixed value of VDS in ohmic region of
operation. Practically curve varies nonlinearly due to source-drain resistance and mobility reduction
at higher field across the oxide layer. The transfer characteristics for ohmic region is as shown in Fig.
29

ID

Deviation from linearity

due to field-dependent
m o b i l i t y a n d
s o u rc e -d rai n s eri es
resistance

VT
VG
Fig. 29 Transfer characteristics of MOSFET in ohmic region

Transfer characteristics for saturation region

When the gate to source voltage is less then threshold voltage there exists depletion layer below oxide
layer between source and drain which has no free charge carriers. An inversion layer of electron
forms a conducting channel only when the gate to source voltage becomes more than the threshold
voltage. The drain current of enhancement type MOSFET is negligible when gate voltage is less than
threshold voltage.
ID

VT VGS
Fig. 30 Transfer characteristics of n-channel enhancement type MOSFET

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [47]
The drain current starts increasing when the gate to source voltage VGS is increased beyond the
threshold voltage (VT). The concentration of electrons in the channel increases with increase in gate
to source voltage resulting into increase in the current. This mode of operation, where concentration
of carriers increases in the channel with increase in gate to source voltage is called enhancement
mode.
The drain current for saturation region of operation is given by,

ID = µ n Cox (VGS − VT ) 2 (123)
2L

⇒ I D = µ n Cox (VGS − VT )
2L

 
⇒ I D = µ n Cox VGS − µ n Cox VT
2L 2L

⇒ I D = mVGS + c (124)

It is observed from above equation that ID does not varies linear with VGS in saturation region rather
it follows the square law. However, I D varies linearly with VGS with a slope of


m = µ n Cox (125)
2L

The variation of I D with respect to the voltage VGS is shown in Fig. 31.

ID

VT
VG
Fig. 31 Variation of I D with respect to gate voltage of MOSFET in saturation region

Case-II Transfer characteristic of Depletion Type n-channel MOSFET

An depletion type n-channel MOSFET works in depletion mode when the gate to source voltage

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [48]
is negative. The negative bias voltage induces a depletion layer in the n-type channel. The width
of depletion layer increases and hence effective width of the channel reduces with increase in gate
to source voltage. Therefore, the drain current reduces with increase in the gate to source voltage
in depletion type n-channel MOSFET. At a critical voltage called pinch off voltage the conducting
channel is completely covered by the depletion region and hence th drain current becomes also most
zero. Such condition is known as pinch off condition. When the gate to source voltage is positive the
electrons concentration in the channel increases and hence the drain current increases with increase
in positive gate to source voltage. Such mode where drain current increases with increase in the
positive gate to source voltage is called enhancement mode. The transfer characteristics of n-channel
depletion type MOSFET are shown in Fig.32

ID
Depletions Enhancement
mode mode

Vt VGS
Fig. 32 Transfer characteristics of n-channel depletion type MOSFET
3.5 Control of Threshold Voltage of MOSFET
Since the threshold voltage determines the input voltage level required to turn on or turn off of a
MOSFET, therefore, it should be adjustable. The threshold voltage of a MOSFET should be as kept
low as possible because of the following reasons,
• Small power supply can be used.
• The device will have compatibility of operation with bipolar devices.
• It will require smaller switching time due to smaller voltage swing.
• Device will have higher packing density.

The threshold voltage of a n-channel MOSFET is given by

( Qd + Q x ) + 2φ + φms
VT = F (126)
Cox

where, Qd= qN A =
Wmax 4qN A ∈s φF = bound charge density in depletion layer

Qx= Positive charge trapped in oxide layer.

ε
Cox= ox = capacitance of oxide layer per unit area
t ox

From above equation it is observed that the threshold voltage can be reduced by using the following
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methods.
i. By reducing work function difference ( φms) which can be reduced by using a poly-silicon gate
doped with Boron instead of metal gate.
ii. The threshold voltage can be reduced by increasing the capacitance of oxide layer. The capacitance
of oxide layer can be increased by reducing the dielectric thickness (tox) and by using oxide layer
of (Si3 N4 + Si O2) which has higher value of dielectric constant (εox).
iii. The threshold voltage can also be reduced by ion implantation where ions of opposite polarity
to that of substrate dopant are implanted near source and drain region in the channel. If dose of
ion implantation is made heavy the behaviour of device can be changed from enhancement to
depletion type which gives flexibility of fabricating both types of MOSFETs on same ICs. The
threshold voltage can be reduced to zero with this technique. The ion implantation is basically
used to neutralize the effect of unconverted impurities ions in depletion region below inversion
layer of the MOSFET. the ion implantation also reduces Cgd and Cgs. The threshold voltage of
n-channel enhancement type MOSFET with ion implantation with Boron ions can be given by,
qF
VT2 = VT1 + B (127)
Cox
where, FB is dose of Boron ions in the form of sheet of charge.
iv. By using silicon with <100> structure rather than <111> structure.
v. By reducing charge stored in the depletion layer which can be reduced by reducing the doping
concentration of dopant in substrate.
vi. By connecting source at lower potential than the bulk.

Note • Threshold voltage of MOSFET is not kept at zero, practically, it is of order of 0.7 V.
• VT for isolating regions should be kept high for proper isolation of devices.
• The threshold voltage reduces with reduction in channel length and it increases with reduction
in channel width.

Example 7
A silicon n MOSFET has a threshold voltage of 1 V and oxide thickness of 400A0.
[εr(SiO2) = 3.9, εo = 8.854 ×10−14 F/c.m. q = 1.6 ×10−19 C]
The region under the gate is ion implanted for threshold voltage tailoring. The dose and type of the
implant (assumed to be a sheet charge at the interface) required to shift the threshold voltage to –1V
are
(a) 1.08 × 1012/cm2, p-type (b) 1.08 × 1012/cm2, n-type
(c) 5.4 ×1011/cm2, p-type (d) 5.4 × 1011/cm2, n-type
GATE(EC/1996/2M)

Solution : Ans.(a)
Given,
Threshold voltage, VT2 = – 1V, VT1 = 1V,
εr(SiO2) = 3.9,
εo = 8.854 × 10–14 F/cm,

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [50]
o
Oxide thickness, tox = 400 A = 400 × 10–8 cm
Capacitance of oxide layer,
ε r,ox εo
Ci =
t ox

Where Ci = Dielectric constant of oxide

FB = Dose of ion-implanted
3.9 × 8.85 × 10 –12
∴ Ci =
40 × 10 –10

The threshold voltage with ion-implantation in n-MOSFET is given by,

qFB
VT2 = VT1 + .......(i)
Ci

Putting there values in equation (i), we have,

1.6 × 10−19 × FB
⇒ –1 = 1 +
(8.854 × 10−14 × 3.9) / 400 × 10−8

⇒ FB = 1.08 × 1012 cm–2

In n-channel MOSFET depletion layer consists of positive bound charges. These positive bound
charges give positive threshold voltage. This threshold voltage can be made negative by ion-
implantation with negative bound charge impurity of p-type material such as Boron.
Note :- In n-channel MOSFET threshold voltage may be changed from positive to negative by changing
stored charge in depletion layer from positive to negative.

3.6 Derivation of ID-VDS Relationship of Enhancement type n-channel MOSFET

Consider an n-channel MOSFET connected with biasing voltages as shown in Fig.4.28. Let the
voltage VGS is more than the threshold voltage. The voltage VDS appears across the channel with 0
V at the source end and VDS at the drain end. Then effective voltage across the channel is VGS − VDS
at drain end and VGS at source end. This difference in voltage across the conducting channel from
source to drain end results in tapering of conducting channel with small depth on drain side as shown
in Fig.33. Let the voltage drop from source to drain is Vx at distance x from the source end. Then
the effective voltage across the channel is VGS − Vx at distance x from the source end of the channel.
Consider a differential portion dx of channel at distance x from the source end. If Cox is capacitance
per unit area of gate electrode then the capacitance of portion of dx is Coxdx. The differential
charge stored in inversion layer in differential portion dx of channel can be obtained by replacing
voltage VG by VGS – Vx in equation (103) as under,

dq = Qinvdx = −Cox .dx[VGS – Vx – VT] (128)

Where the negative sign indicates negative charge in inversion layer.

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VDS

VGS
Source Gate Drain
dx

Oxide tox
Channel dx
Velocity 
dt
ID e
Source Drain
dx
E
_ dVx +
VDS
Vx Voltage
Vx+dVx
0 x x + dx L
_ VDS
+
Fig. 33 n-channel MOSFET with zoomed channel region.

The electric field in channel is directed from drain to source in −x-direction due to voltage applied
between drain and source. The voltage drop across the differential portion dx can be given by,
dVx
Ex = − (129)
dx
The drift velocity of electrons from source to drain in the channel is related to the electric field as
under,
dx dV
= −µn E x =
µn x (130)
dt dx

Negative sign in above equation indicates that the electrons move in the direction opposite to the
direction of electric field.
Where µn is the mobility of electrons in the channel also known as surface mobility. It is a physical
parameter whose value depends on the fabrication process technology. The surface mobility is
normally less than the bulk mobility due to more scattering of electrons at surface region because of
structural imperfections at the surface. The resulting drift current i in the channel can be given in the
channel as follows :
dq dq dx
I = = × (131)
dt dx dt

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [52]
Putting charge dq and drift velocity dx/dt in above equation from equations (127) and (129) in above
equation, we have,
dVx
I = −µn Cox  [ VGS − Vx − VT ]
dx
The current i is measured at point ‘x’ in the channel but it is constant through out the channel of the
MOSFET. So, the current ‘I’ must be equal to drain current of the MOSFET. Therefore, the drain
current of MOSFET can be obtained as under,
dVx
ID = − I µn Cox  [ VGS − Vx − VT ]
=
dx

⇒ IDdx = µn Cox  [ VGS − Vx − VT ] dVx

Integrating both sides of over the range from x = 0 to x = L and corresponding values of Vx from 0
to VDS, we have,
L VDS
∫ I D dx = ∫ µn Cox  [ VGS − Vx − VT ] dVx
0 0

   1 2
ID = (µn Cox )   ( VGS − VT ) VDS − VDS  (132)
L
  2 

The above expression of current ID is applicable for linear region of drain characteristics. The drain
to source voltage at the boundary of ohmic and saturation region, VDS = VGS − VT , gives the drain
current for saturation region as under,
1
( µ n Cox )   ( VGS − VT )
 2
I D = (133)
2  L 

It is observed from above expression of current that the drain current for saturation region is
independent of voltage VDS.
Transconductance parameter
The factor µnCoxis known as transconductance parameter of the MOSFET. It is determined by the
process of fabrication of MOSFET. It is denoted by k for NMOS and has dimension of A/V2.
∴ k = µn Cox (134)
The expressions of drain current for ohmic regions in terms of transconductance parameter can be
written as follows :
 1
Triode region: ID = k  ( VGS − VT ) VDS − VDS2  (135)
L  2 

1 
k ( VGS − VT )
2
Saturation region: = ID (136)
2 L

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [53]
The ratio of the channel width  to the channel length L in the expressions of drain current is
known as the aspect ratio of the MOSFET. The voltage Vov = VGS - VT is called overdrive voltage of
MOSFET.

Example 8
Consider an n-MOSFET for which εox = 4.5×10−11 F/m, tox = 8 nm, µn = 450 cm2/V-s and VT =
0.7 V. If W/L = 8 µm/0.8 µm then calculate the values of VGS and VDS min needed to operate the
transistor in the saturation region with a DC current ID = 100 µA.
Solution :
Drain current in saturation region is given by,
µn Cox  µn εox 
( VGS −=
VT ) ( VGS − VT )
2 2
ID =
2L 2t ox L

Given, ID = 100 µA = 100 × 10–6 A

εox = 3.45 × 10–11 F/m
tox = 8 nm = 8 × 10–9 m

= 8 µm/0.8 µm = 10
L

VT = 0.7V
µn = 450 cm2 /V-s = 450 × 10–4 m2/V-s
450 × 10−4 × 3.45 × 10−11 × 10
( VGS − 0.7 )
2
∴ 100 × 10–6 = −9
2 × 8 × 10

⇒ VGS = 1.021V
Minimum drain to source voltage required to operate MOSFET is saturation region is given by,
VDS, min = VGS – VT = 1.021 – 0.7 = 0.321V

Example 9
When the gate-to-source voltage (VGS) of a MOSFET with threshold voltage of 400 mV, working
in saturation is 900 mV, the drain current is observed to be 1 mA. Neglecting the channel width
modulation effect and assuming that the MOSFET is operating at saturation, the drain current for an
applied VGS of 1400 mV is
(a) 0.5 mA (b) 2.0 mA
(c) 3.5 mA (d) 4.0 mA
GATE(EC/2003/2M)
Solution : Ans.(d)
Drain current of MOSFET is given by
ID = K (VGS – VT)2
Given, ID = 1 mA at VGS = 900 mV
& VT = 400 mV

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [54]
⇒ 1 × 10–3 = K(900 × 10–3 – 400×10–3)2
1
⇒ K =
250

When, VGS = 1400 mV

1
⇒ ID = (1400 × 10−3 − 400 × 10−3 ) 2
250

⇒ ID = 4 mA

Example 10
Consider a long-channel MOSFET with a channel length 1 µm and width 10 µm. The device
parameters are acceptor concentration NA= 5 × 1016 cm–3, electron mobility µn = 800 cm2 /V-s, oxide
capacitance/area Cox = 3.45 × 10–7 F/cm2, threshold voltage VT=0.7 V. The drain saturation current
(IDsat) for a gate voltage of 5 V is_______mA (rounded off to two decimal places). [ε0 = 8.854 ×
10–14F/cm, εsi = 11.9].
GATE(EC/2019/2M)
Solution : Ans.(25.40 to 25.60)
The drain current in saturation region of operation is given by,
µn Cox W
⋅ ( VGS − VT )
2
ID,sat =
2 L
Given, VGS = 5V, VT = 0.7V
W = 10 µm, L = 1µm
µn = 800 cm2/V-s = 800×10–4 m2/V-s
Cox = 3.45 × 10–7 F/cm2 = 3.45 × 10–3 F/m2

∴ µnCox = 800×10–4×3.45 ×10–3 = 2.76×10–4
2.76 × 10−4 10 × 10−6
× ( 5 − 0.7 ) = 25.51 mA3.7
2
∴ ID,sat = × −6
2 1 × 10

Transconductance of Enhancement type n-channel MOSFET

The transconductance of MOSFET is defined as change in drain current with respect to change in
gate to source voltage. Mathematically, the transconductance region is given by,
∂I D
gm =
∂VGS VDS

Case-I : For ohmic region

The drain current in ohmic region of operation is given by,
  1
ID = µ n Cox  ( VGS − VT ) VDS − VDS2  (137)
L  2 

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [55]
∂ ID W
Transconductance, gm = = µ n Cox VDS (138)
∂ VGS L

Case-I : For saturation region

The drain current for saturation region is given by,
µ p Cox 
ID = (VSG − | VT |) 2 (139)
2L

∂  W 
The transconductance, gm = µ p Cox [(VSG − | VT |) 2 ]
∂ VSG  2L 

⇒ gm =
µ p Cox (VSG − | VT |) (140)

It is observed from the above equation that gm is linear function of gate voltage with zero value at VGS
= VT. But practically the variation of transconductance is as shown in Fig. 34. The transconductance
reaches a maximum value and then decreases due to effect of source-drain resistance and reduction
in mobility at higher field across the oxide layer.

gm

gm(max.)

0 VT VG
Fig. 34 Variation of gm to gate voltage of MOSFET in saturation region

It is observed from above equation that the transconductance in saturation region is linear function of
voltage VGS and it is independent of voltage VDS.

It is observed from equation (140) that the transconductance of MOSFET,

• Increases with increase in width of channel
• Increases with increase in electron mobility
• Increases with increase in capacitance per unit area of oxide
• Increases with increase in dielectric constant of oxide
• Decreases with increase in oxide thickness
• Decreases with increase in channel length.
Transconductance of Enhancement Type p-channel MOSFET
The drain current for saturation region of PMOS is given by,

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µ p Cox 
ID = (VSG − | VT |) 2 (141)
2L

∂  W 
The transconductance, gm = µ p Cox [(VSG − | VT |) 2 ]
∂ VSG  2L 


⇒ gm =
µ p Cox (VSG − | VT |) (142)
L

Transconductance of Depletion Type n-channel MOSFET

The drain current of n-channel depletion MOSFET is given by,
2
 V 
ID = I DSS 1 − GS  (143)
 Vt 
Where, IDSS is drain current when gate terminal is shorted with source terminal. The current IDSS is
given by,

µ n Cox W 2

IDSS = Vt (144)
2 L
∂   VGS  
2
∂I D
Transconductance, g= =  I DSS 1 −  
m
∂VGS ∂VGS   Vt  
 
2I DSS  VGS   VGS 
⇒ gm = − 1 −  = g mo 1 −  (145)
Vt  Vt   VT 

2I DSS 2I DSS
Where, gmo = − = (146)
VT | VT |

Example 10
An n-channel depletion MOSFET has following two points on its ID-VGS curve :
(i) VGS= 0 at ID = 12 mA and
(ii) VGS = – 6 Volts at ID=0
Which of the following Q-points will give the highest trans-conductance gain for small signals ?
(a) VGS = – 6Volts (b) VGS = –3Volts
(c) VGS = 0 Volts (d) VGS = 3 Volts
GATE(EC/2006/1M)
Solution : Ans.(d)
The drain current of n-channel depletion MOSFET is given by,
2
 V 
ID = I DSS 1 − GS  ......(i)
 Vt 

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Given, ID = 12 mA at VGS = 0
Putting above values in equation (i), we have,
2
 0 
⇒ 12 = I DSS 1 − 
 Vt 
⇒ IDSS = 12 mA ......(ii)
Also, VGS = – 6V when ID = 0
Putting above values in equation (i), a gain, we have,
2
 (−6) 
0 = 12 1 − 
 Vt 

⇒ Vt = –6V .....(iii)
Transconductance of depletion type MOSFET is given by

∂   VGS  
2
∂I D
=
gm =  I DSS 1 −  
∂VGS ∂VGS   Vt  
 

2I DSS  VGS 
⇒ gm = − 1 − 
Vt  Vt 

2 × 12  VGS 
⇒ gm = − 1−
(−6)  (−6) 

 V 
⇒ gm = 4 1 + GS 
 6 

i. when VGS = –6V

 6
gm = 4 1 −  =
0
 6

ii. when VGS = –3V

 3
gm = 4 1 −  =
2mS
 6

 0
iii. when VGS = 0, gm = 4 1 +  = 4mS
 6

 3
iv. when VGS = 3 V, gm = 4 1 +  = 6mS
 6

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [58]
Example 11
The slope of the ID vs. VGS curve of an n-channel MOSFET in linear regime is 10–3 Ω–1 at VDS = 0.1
V. For the same device, neglecting channel length modulation, the slope of the I D vs. VGS curve

(in A / V) under saturation regime is

approximately_____
GATE(EC-III/2014/2M)
Solution: Ans . (0.06 to 0.08)
The drain current in linear region of operation of n-channel MOSFET is given by
µn Cox   1
ID =  ( VGS − VT ) VDS − VDS2 
L  2 

µn Cox  µ C  1 
⇒ ID = VGS VDS − n ox  VT VDS + VGS 
L L  2 

Slope of ID Vs VGS curve represented by above equation is given by,

µn Cox 
m = VDS
L

Given, m = 10–3 Ω–1 at VGS = 0.1V

µn Cox 
⇒ 10–3 = × 0.1
L

µn Cox W
⇒ = 10–2
L

Drain current in saturation region is given by,

µn Cox 
( VGS − VT )
2
ID =
2L

µn Cox  µC 
⇒ ID = VGS − n ox VT
2L 2L

∴ Slope of I D Vs VGS curve represented by above equation,

µn Cox W 10−2 10−1

m = = = = 0.0707
2L 2 2

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [59]
3.7 Channel Resistance in ohmic region or ON resistance of n-channel MOSFET
The channel resistance of MOSFET in ohmic region is also known as drain or output resistance. It
can be obtained from expression of drain current of n-channel MOSFET (NMOS) for ohmic region
as follows,
 1 2
ID = µ n Cox [(VGS − VT ) VDS − VDS ] (147)
L 2

∂ ID 
Drain conductance, gD = µ n Cox
= [(VGS − VT ) − VDS ] (148)
∂ VD S L

When VDS << (VGS − VT), the drain current can be approximated by neglecting the term containing
VDS in above as under,
∂I D 
g D = µ n Cox
= (VGS − VT ) (149)
∂ VD S L

Drain or channel resistance,

∂VDS 1
=rD =
∂I D 
µ n Cox (VGS − VT ) (150)
L
It is observed from above equation that the drain or channel resistance decreases linearly with
increase in the gate to source voltage in ohmic region of operation. Therefore, MOSFET can be used
as a voltage variable resister (VVR) in ohmic region of operation.
Note : The channel resistance in saturation region is infinite because the channel is in pinched off condition
in saturation region of operation.
Example 12
Consider a long-channel NMOS transistor with source and body connected together. Assume that the
electron mobility is independent of VGS and VDS. Given,
gm = 0.5 µA/V for VDS = 50 mV and VGS = 2 V,
gd = 8 µA/V for VGS = 2 V and VDS = 0 V
∂ ID ∂ ID
Where g m = and g d =
∂ VGS ∂ VDS

The threshold voltage (in volts) of the transistor is ............

GATE(EC-II/2016/2M)
Solution : Ans. (1.18 to 1.22)
The NMOS operates in ohmic region when VDS = 0.
The drain current in ohmic region of operation is given by,
  1
ID = µ n Cox  ( VGS − VT ) VDS − VDS2 
L  2 

Transconductance of transistor,

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [60]
∂ ID W

gm = = µ n Cox VDS
∂ VGS L

Given, gm = 0.5 µA/V for VDS = 50 mV and VGS = 2 V


⇒ 0.5×10−6 = µ n Cox × 50 × 10−3
L

⇒ µ n Cox = 0.01×10−3
L

Drain conductance of in ohmic region,
∂ ID 
gd = = µ n Cox ( VGS − VT ) − VDS 
∂ VDS L 
Given, gd = 8 µA/V for VGS = 2 V and VDS = 0 V

( 2 − VT ) − 0 
−3
⇒ 8×10−6 = 0.01 × 10

⇒ VT = 1.2 V

Example 13
Consider an n-MOSFET for which εox = 4.5×10−11 F/m, tox = 8 nm, µn = 450 cm2/V-s and VT = 0.7 V.
If W/L = 8 µm/0.8 µm then find the value of VGS required to cause the device to operate as a 1000 Ω
resistor for very small VDS.
Solution:
An n-MOSFET can be operated as a resistor in ohmic region of operation. The resistance of MOSFET
in ohmic region is given by,
1 1
rD = =
µn Cox  µn εox 
( VGS − VT ) ( VGS − VT )
L t ox L

Given, µn = 410 cm2/V-s = 450 × 10–4 m2/V-s , εox = 3.45 × 10–11 F/m , tox = 8 nm = 8 × 10–9 m
VT = 0.7V

 8µm
= = 10
L 0.8µm

rD = 1000 Ω
1
⇒ 1000 =
450 × 10 × 3.45 × 10−11 × 10
−4
( VGS − 0.7 )
8 × 10−9

⇒ VGS = 1.22 V

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [61]
Example 14
The small-signal resistance (i.e., dVB/dID) in kΩ offered by the n-channel MOSFET M shown in the figure
below, at a bias point of VB = 2 V is (device data for M: device transconductance parameter kN = µnCox′
(W/L) = 40 µA/V2, threshold voltage VT = 1V, and neglect body effect and channel length modulation
effects)
VB
ID

(a) 12.5 (b) 25

(c) 50 (d) 100
GATE(EC/2013/2M)

Solution : Ans.(b)
VB

ID

G M
+
VGS –
S

When gate terminal of MOSFET is shorted with the drain,

VDS = VGS

∴ VDS > VGS − VT

The MOSFET operates in saturation region when VDS > VGS − VT . The drain current of MOSFET in
ohmic region is given by,
µ n Cox W
( VGS − VT )
2
ID =
2 L

Here, VGS = VDS = VB

µ n Cox W
( VB − VT )
2
⇒ ID =
2 L

Differentiating w.r.t. VB, we have,

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [62]
dI D W
= µ n Cox ( VB − VT )
dVB L

W
Given, µ n Cox ⋅ = 40 µA/V2 ; VB = 2V ;
L

VT = 1V

dI D
⇒ = 40 × 10–6 (2 – 1) = 40 × 10–6 mho
dVB

Small signal resistance of MOSFET,

dVB 1 1000
= =
−6
kΩ
= 25kΩ
dI D 40 × 10 40

3.8 Non-ideal Effects in MOSFETs

I. Channel Length Modulation Effect

It has been assumed till now that the voltage VDS does not affect the drain current in saturation region
once the conducting channel is pinched off for VDS > VGS – VT. However, practically the effective
channel length reduces with in VDS as shown in Fig.35.
VDS

_
+
VGS
G
S _ D
+

Oxide

Source channel Drain

n+ n+
L L L
_ VDSsat= VGSVT +_ +
VDSVDSsat

Fig. 35 Channel length modulation in n-channel MOSFET

When VDS is increased above VGS – VT the pinched off region of channel expands towards source
region and effective length of channel reduces from L to L−∆L. This phenomenons is known as
channel length modulation. As drain current is inversely proportional to L so it increases with
decrease in L. The drain current when effective channel length is L−∆L can be given by,
1 
( VGS − VT )
2
ID = k (151)
2 L − ∆L
1  1
( VGS − VT )
2
⇒ ID = k
2 L 1− ∆L
L

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [63]
−1
1   ∆L 
( VGS − VT )
2
⇒ ID = k ⋅ 1 −  (152)
2 L  L 
−1
 ∆L   ∆L 
If ∆L << L then 1 −  ≈ 1 +  as probational expansion.
 L   L 

1   ∆L 
 ( VGS − VT )
2
⇒ ID = k 1 + (153)
2 L L 

The fractional change in channel length ∆L/L is proportional to the voltage VDS and it can be given as

∆L/L = λ VDS (154)

Where λ is called channel length modulation parameter or channel length modulation coefficient.

1 
k (1 + λVDS )( VGS − VT )
2
⇒ =ID (155)
2 L

It is observed from the above equation that the drain current increases with increase in VDS in
saturation region also due to channel length modulation effect. The drain characteristics with
channel modulation effect can be drain as shown in Fig.36. When output characteristics are extended
backward, these meet at point –VA on VDS - axis.
From above equation, ID = 0 when 1 + λVDS = 0
1
⇒ VDS = − (156)
λ

Let the value of VDS at ID = 0 is equal to – VA then,

1
– VA = −
λ

1
⇒ VA = (157)
λ

The voltage VA is usually referred as early voltage.

The drain or channel or output conductance for saturation region with channel length modulation
effect can be given as,
∂I
go = D (158)
∂ VDS
1  2 ∂ (1 + λVDS )
⇒ go = k ( VGS − VT ) ⋅
2 L ∂ VDS

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [64]
1 
go = k ( VGS − VT ) ⋅ λ = ID′λ
2
⇒ (159)
2 L

µ n Cox 
( VGS − VT )
2
where, ID′ = (160)
2 L
ID
ohmic Saturation
> VG
S3

V GS4 1
slop 
ro
V GS1
V GS3 >
V GS1
V GS2 >

VGS1 >VT

VGS < VT

–VA VDS
Fig. 36 Output characteristics of enhancement type n-channel MOSFET
with channel length modulation

The current ID′ is drain current without channel length modulation effect taken into account.
Output or drain or channel resistance in saturation region,
1 1 VA
ro = = = (161)
g o I D′λ I D′

Note : i. The drain current and output resistance for PMOS with channel length modulation effect is given
by,
µp Cox W
ID = (1 + λ VDS )(VGS − VT ) 2
2 L
Here, VDS, VGS and VT are negative for PMOS
ii. The output resistance of PMOS with channel modulation effect is given by,
1 1 | VA |

ro = = =
go I D′λ I D′

The current ID′ is drain current without channel length modulation effect taken into account.

II. Substrate Body Effect

In many applications, the body terminal of the MOSFET is shorted with source terminal which
results in pn junction between substrate and channel having zero bias. In such cases substrate does
not play any role in circuit operation and its existence can be neglected. However, in integrated
circuits (ICs) the substrate is normally common to many MOS transistors. In such circuits, the
substrate is normally connected to highest negative potential in order to maintain cutoff condition for
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [65]
all substrate-to-channel pn junctions. The resulting reverse bias voltage VSB between source and body
results in widening of depletion region and reduction of the effective depth of conducting channel as
shown in Fig.37.

Channel

Depletion region Drain

Source

Fig. 37 Channel depth reduction due to substrate body effect.

The value of VGS required to maintain the depth of the channel is more and the threshold voltage is
also increased due to the body effect. The increase in threshold voltage results in decrease in drain
current. Therefore, it is observed the negative potential given to the substrate of MOSFET controls
the drain current also. Thus body acts like another gate for MOSFET and this phenomenon is known
as body effect.
The change in threshold voltage due to substrate body effect for both n-channel and p-channel
MOSFETs is given by,
2εs qN A 
( 2φ + VB ) − ( 2φF ) 
1/ 2 1/ 2
∆VT =
Ci  F 

Where, VB is substrate bias voltage. It is negative for n-channel MOSFET and positive for p-channel
MOSFET.
The variation in threshold voltage w.r.t. to variation in substrate bias voltage can be given by,
∂VT 1 2εs qN A 1
( 2φF + VB )
−
∴ = 2
∂VB 2 Ci

Here 2fF << |VB| and can be neglected.

III. Temperature Effect

The channel resistance in ohmic region is given by,

∂ VDS L
rD = = (162)
∂ ID k ( VGS − VT )

The threshold VT voltage has negative temperature coefficient of approximately −2 mV/oC. The
transconductance parameter k also decreases with increase in temperature. Here the decrease in k
w.r.t. temperature is more dominant over decrease in VT with temperature, therefore, the channel
resistance increases with increase in temperature. Hence, the channel resistance of MOSFET has
positive temperature co-efficient unlike BJT which has negative temperature co-efficient. Therefore,
the drain current of MOSFET decreases with increase in temperature which makes it suitable for
parallel operation.
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [66]
The drain current in FET deceases with increase in temperature due to decrease in mobility of carriers
in the channel with increase in temperature of the device. The transconductance decreases with
increase in temperature. The variations in drain resistance and transconductance with temperature
are shown in Fig. 37b.

gm
rd

T
Fig. 37 (b) Variations of rd and gm of FET with temperature

Note : i. Since MOSFET has positive temperature coefficient, therefore, its resistance increases with
increase in temperature and drain current reduces, because of this characteristic FET never
undergoes a thermal breakdown or secondary breakdown. This characteristic of FET makes it
suitable for parallel operation.
ii. BJT has negative temperature coefficient, therefore, it suffers from secondary or thermal
breakdown. This characteristic of BJT makes it unsuitable for parallel operation.
IV. Sub-threshold current
When the gate voltage is less than the threshold voltage the drain current even exists due to existence
of inversion layer for potential surface in the range, φF < φs < 2φF. It has been seen in MOS capacitor
the inversion layers starts forming when the surface potential, φs, becomes more than φF. This sub-
threshold drain current is leakage current of MOSFET in OFF state. It results in power dissipation in
MOSFET in OFF state.
The sub-threshold current is observed during weak invention when . It is kept as minimum as possible
to reduce OFF state power lass in MOSFET.
V. Mobility variation
The mobility of electrons in inversion layer is smaller than bulk of semiconductor due to surface
scattering. The carriers in the channel are very close to the semiconductor-oxide interface, they are
scattered by surface roughness and by coulombic interaction with fixed charges in the gate oxide.
VI. Hot Electron Effect
The electrons traveling from source to drain in n-channel MOSFET acquires high kinetic energy
in pinch-off region near drain on expense of energy stored in electrostatic potential in pinch off
region. These electrons are called hot electrons. Hot electrons can jump from conduction band of
semiconductor to the conduction band of oxide thus penetrate in the oxide layer. The hot electrons
may result in increase in flat band and threshold voltages and give rise to a current in gate terminal
resulting in reduction in input impedance of the MOSFET. This effect is known a hot electron effect.
This effect is less prominent in p-channel MOSFET because the mobility of holes is less than that of
electrons.

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [67]
Example 15
A MOSFET in saturation has a drain current of 1 mA for VDS = 0.5 V. If the channel length modulation
coefficient is 0.05 V–1, the output resistance (in kΩ) of the MOSFET is ........
GATE(EC-I/2015/2M)
Soluiton : Ans.(19 to 21)
The channel resistance in terms channel length modulation coefficient is given by,
1
ro =
λI D

where, ID drain current without channel modulation effect and λ is channel length modulation
coefficient.
Given, λ = 0.05 V–1 and ID = 1 mA
1
⇒ ro = kΩ = 20 kΩ
0.05 × 1

Example 16
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to
be 1 mA at a drain-source voltage of 5V. When the drain-source voltage was increased to 6V while
keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to
source saturation voltage is much smaller than the applied drain-source voltage. The channel length
modulation parameter λ(in V–1) is .............
GATE(EC-III/2015/2M)
Soluiton: Ans.(0.018 to 0.026)
The drain current in terms channel length modulation parameter is given by,
µ C 
( VGS − Vth ) (1 + λVDS )
2
ID = n ox ⋅
2 L
Case-I: When VDS = 5V, ID = 1 mA
µ C 
( VGS − Vth ) (1 + 5λ )
2
⇒ 10−3 = n ox ⋅ .....(i)
2 L
Case-II: When VDS = 6V, ID = 1.02 mA
µ n Cox 
( VGS − Vth ) (1 + 6λ )
2
⇒ 1.02×10−3 = ⋅ .....(ii)
2 L
From the equations (i) and (ii), we have,
1.02 1 + 6λ
=
1 + 5λ

λ = 0.0222 V–1
Example 17
Consider an n-channel metal oxide semiconductor field effect transistor (MOSFET) with a gate-to
source voltage of 1.8 V. Assume that W = 4, µNCox = 70 × 10–6 AV–2, the threshold voltage is 0.3 V,
L

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [68]
and the channel length modulation parameter is 0.09 V–1. In the saturation region, the drain
conductance (in micro seimens) is .............
GATE(EC-I/2016/2M)
Soluiton : Ans. (28 to 29)
The drain current in saturation region when the channel length modulation is taken into consideration
is given by,
µC 
ID = n ox ( VGS − VT ) (1 + λVDS )
2

2L
∂ µn Cox
Drain conductance, gD = =
( VGS − VT ) λ
∂ VDS 2L

W
Given, = 4, VGS = 1.8V, µN Cox = 70 × 10–6 AV–2 , VT = 0.3 V, λ = 0.09 V–1
L
70 × 10−6 × 4
(1.8 − 0.3) × 0.09 = 28.35 µS
2
⇒ gD =
2

3.9 MOSFET Scaling

The frequency response of a MOSFET increases as the channel length decreases. However, the while
scaling of MOSFET the device dimension and voltages should be scaled such that both horizontal
and vertical fields essentially remain constant. For example if channel length is changed from L to kL
then the drain voltage should be changed from VD to kVD. Similarly the gate voltage is also changed
from VG to kVG so that drain and gate voltages remain compatible to maintain vertical field constant,
The oxide thickness should be changed from tox to ktox. The device scaling and its effects on various
parameters of the device are shown in Table.1
Table 1: MOSFET Scaling and its effects on parameters
Device and circuit parameters Scaling factor(k < 1)
Scaled parameters Device dimensions (L, t ox, W, x i ) k
Doping concentration (N a , N d ) 1/ k
Voltages k
Effect on device Electric field 1
parameters Carrier velocity 1
Depletion widths k
Capacitance (C = εA/t) k
Drift current k
Effect on circuit Device density 1 / k2
parameters Power density 1
Power dissipation per device (P = VI) k2
Circuit delay time ( ≈ CV/I) k
Power-delay product (Pτ) k3

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3.10 Breakdown and Gate protection of MOSFET
Breakdown at Drain
The drain to substrate pn junction of MOSFET is reverse biased. If voltage at drain is increased
beyond some critical value the pn junction between drain and substrate may breakdown due to
avalanche multiplication. The avalanche multiplication results in sudden increase of drain current.
Another breakdown which occurs at low drain voltage before avalanche multiplication is punch
through condition. The punch through occurs in devices with relatively smaller channel length
where the depletion region of drain substrate pn junction extends towards the source region
and completely covers the conducting channel between drain and source. The drain current
increases suddenly. However, the breakdown due to punch through does not damage the device
permanently.
Breakdown of Gate oxide
If gate to source voltage reaches critical value of approx 20V then there is dielectric breakdown of
oxide layer which results in permanent damage to the device. The gate of MOSFET is protected by
fabricating a Zener diode between gate and source. This diode protects the gate against excessively
high voltage.

3.11 Comparison of Enhancement and Depletion type MOSFETs

i. An enhancement type MOSFET has no conducting channel when the gate voltage is zero whereas
depletion type MOSFET has drain current even when gate voltage is zero. Therefore, depletion
type of MOSFET is less preferred because it has less use in appliances.
ii. The logic level voltages of enhancement and depletion type of MOSFETs is opposite to each
other.
iii. The depletion MOSFET is free from sub-threshold leakage current and gate oxide leakage
current.
iv. As a enhancement MOSFET shrinking in size, there is no way to stop the sub threshold leakage
current diffused across from source to drain because the drain and source terminals are closer
physically. This is not the problem with depletion type MOSFET because a pinched channel
stops the diffusion current completely.

3.12 Comparison between p-channel and n-channel MOSFET

i. p-channel has more ON state resistance as compared to n-channel.
ii. The physical size of p-channel MOSFET is more.
iii. Packing density of n-channel MOSFET is high.
v. n-channel MOSFET has better switching response.
vi. Cost of n-channel is higher.
vii. n-channel MOSFET has the problem of premature turning ON due to contamination of positive
ion in SiO2 layer.

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Example 18
Common Data for Questions A and B:
In the three dimensional view of a silicon n-channel MOS transistor shown below, δ =20 nm. The
transistor is of width 1µm. The depletion width formed at every p-n junction is 10 nm. The relative
permittivities of Si and SiO2, respectively, are 11.7 and 3.9, and ε0 = 8.9 × 10–12 F/m.
1µm

D 1nm
1µm

0.2 µm 0.2 µm
D   S
0.2 µm p substrate 0.2 µm

B
A. The source-body junction capacitance is approximately
(a) 2 fF (b) 7 fF
(c) 2 pF (d) 7 pF

B. The gate-source overlap capacitance is approximately

(a) 0.7 fF (b) 0.7 pF
(c) 0.35 fF (d) 0.24 pF
GATE(EC/2012/2M)
Solution:
A. Ans.(b)
1µm

D 1nm
1µm

0.2 µm 0.2 µm
D   S
0.2 µm p substrate 0.2 µm

B
Total area of cross-section of source w.r.t. substrate ,

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [71]
Ass = (0.2 × 10 –6 + 0.2 × 10–6 + 0.2 × 10 –6) × 1 × 10–6 m2 = 0.6 × 10–12
m2
Width of depletion layer at junction between source & substrate, Ws = 10 × 10–9 m
Capacitance due to depletion layer is given as,
ε r,si εo A ss 11.7 × 8.9 × 10−12 × 0.6 × 10−12
Css = =
Wss 10 × 10−9

⇒ Css = 6.24 × 10–15 F ≈ 7 fF

B. Ans.(a)
Area of overlap between gate & source,
AGS = 1 × 10–6 ×δ = 1 × 10–6 × 20 × 10–9
⇒ AGS = 20 × 10–15 m2
Thickness of oxide layer, tox = 1 × 10–9 m
Capacitance of overlap area between gate and source,
ε r,sio2 εo A GS 3.9 × 8.9 × 10−12 × 20 × 10−15
Cas = =
t ox 1 × 10−9

⇒ Cas = 0.69 × 10–15 F ≈ 0.7 fF

4 Junction Field Effect Transistor (JFET) ( No more in GATE

syllabus)
The basic structure of a n-channel JFET is shown in Fig. 38. It consists of a n-type semiconductor
bar where p+ type is diffused on both sides of the bar. The JFET has three terminals called Gate (G),
Source (S) and Drain(D). The region between to gate regions is called channel of JFET.

VGG
Gate (G)

IG

IS ID
Source (n) Drain
(S) (D)
n-channel
w

x RL
+
p type gate
depletion region

VDD

Fig. 38 Basic structure of n-channel JFET

Terminals of JFET :
1. Source: It is the terminal through which majority carriers enter into the channel of device. Source
of FET is analogous to emitter of BJT.

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [72]
2. Drain: Drain is the terminal through which majority carriers leave the channel of the device. It
is analogous to collector of BJT.
3. Gate: It is the control terminal of the device. It is analogous to base of the BJT. In n-channel
JFET a heavily doped p+ region is defused on both sides of the n-channel to form the gate layer
as shown in the figure.

Symbol of JFET :

D D

G G
S S
n-channel p-channel

Fig. 39 Symbols of JFET

4.1 Operation of JFET

When pn junction formed on both sides of channel of JFET is reverse biased there is formation of
depletion layer at the junction. As p+ region of the gate is heavily doped as compared to the channel
region so most of the depletion layer lies in the channel. The depletion layer has only immobile
bound charges so it does not provide conduction path for the current. The width of depletion layer
increases with increase in reverse biasing voltage applied at the gate terminal. The increase in
depletion layer width results in decrease in effective width of the conducting channel which in turn
results in decrease in channel conductance. Thus drain current of JFET decreases with increase in
the reverse biasing voltage applied at the gate terminal of the device. Thus the modulation of channel
conductance by gate voltage controls the channel current of the JFET. Therefore, JFET is a voltage
controlled device. It can be used as a voltage controlled current source. The gate voltage induces a
field in the depletion layer due to which name of devices is field effect transistor.

4.2 Static Drain Characteristics of JFET

The circuit of JFET with common source for static drain characteristics is shown in Fig.40.

D ID R
+ + L
G
VDS VDD
_ _
+ _
IG
VGG
+ VGS S IS
_

Fig. 40 Circuit of n-channel JFET for static drain characteristics

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The drain characteristics of the n-channel JFET are drawn in the Fig. 41. The static drain characteristics
of a JFET is defined by,
ID = f (VDS, VGS)
When the drain to source voltage,VDS, is increased for a fixed value of gate to source voltage,VGS,
the drain current,ID, initially increases linearly with voltage VDS due to finite resistance offered by the
channel. The width of depletion layer increases due to reverse bias of pn junction between gate and
channel caused by voltage drop in the channel from drain to source. The potential drop is highest
on drain end in n-channel JFET so the level of reverse bias is maximum on drain end of the channel
and hence width of depletion layer is maximum and width of channel is smallest of drain end of the
channel as shown in Fig. 38. When the drain to source voltage reaches at pinch off level the width
of the channel reaches at minimum and drain current becomes constant and almost independent of
VDS. If voltage is further increased beyond some critical value an avalanche multiplication occurs
at pn junction resulting in the breakdown and drain current increases suddenly. The drain to source
voltage required for avalanche multiplication decreases with increase in gate to source reverse biasing
voltage.
The drain to source voltage required for pinch off of the channel decreases with increase in gate to
source reverse biasing voltage. When the gate to source reverse biasing voltage is increased the with
of depletion layer decreases and channel width decreases. At a critical value of gate to source voltage
called pinch off voltage, VP, the channel width is reduced to zero and drain current becomes almost
zero.
Breakdown region
ID
Saturation region
VGS= + 1
Ohmic region
VGS= 0
IDSS
VGS= –2V

VGS= –5V
VGS=VP

VP VDS
ID, OFF
Cut off region
Fig. 41 Common source drain characteristics of n-channel JFET

Regions of operation
1. Active/Saturation/Pentode region: In saturation region the drain current, ID, is almost constant
and independent of drain to source voltage,VDS. In this region the drain current varies with variation
in gate to source voltage,VGS. Therefore, JFET can be use as a transconductance amplifier in
saturation region of operation. When gate to source reverse biasing voltage is increased the drain
current reduces. At certain critical value of VGS called pinch off voltage,VP , the width of the
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channel becomes negligible and drain current becomes almost zero. This condition corresponds
to the pinch off condition and the device behaves like open switch. When drain current increases
with increase in reverse biasing gate voltage the device operates depletion mode and when drain
current increases with forward biasing gate voltage the device operates in enhancement mode.
However, JFET is always used in depletion mode of operation.
2. Ohmic/Triode region: In ohmic region of operation, the device offers some finite resistance for
particular value of gate to source voltage. As reverse biasing voltage at gate terminal is increase
the width of depletion layer is increased and effective channel width is decreased and hence
conductivity of channel is reduced. Thus, the resistance offered by the channel increases with
increase in reverse biasing voltage VGS. So, the device behaves like voltage variable resistor in
ohmic region. In this region, JFET behaves like a closed switch having finite resistance. Because
of the finite resistance offered by the device in ohmic region the ON state losses of FET are more
than BJT. When the drain to source voltage is increased in ohmic region the drain current also
increases proportionally. The drain current becomes almost constant when VDS reaches a critical
value called VDS pinch off. The drain to source pinch off voltage reduces with increase in reverse
biasing voltage VGS.
3. Cut-off region: In this region the drain current is almost zero and the device behaves like an open
switch. The gate to source voltage is equal to the pinch off voltage in cut off region. However,
there is some leakage drain current, ID,OFF , even under pinch off condition. The drain leakage
current is of order of nanoamperes for a Si device.
4. Breakdown region: When drain to source voltage is increased beyond certain critical value, the
drain current increases suddenly due to avalanche multiplication at reverse biased pn junction.
This breakdown voltage reduces with increase in gate to source voltage.

Note : i. FET can be used as a transconductance amplifier when it is operated in saturation.

ii· FET can be used as a closed resistive switch in ohmic region and as an open switch in cut off
region.
iii. FET can be used as a active load when drain is shorted with gate terminal.
iv. The maximum voltage that can be applied between any two teminals of FET is the lowest voltage
that will cause avalanche multiplication.

G
S

Fig. 42 FET used as load with gate shorted with the drain

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [75]
4.3 Expression for pinch off voltage
The expression of pinch off voltage of a n-channel JFET can be obtained by consider a JFET operating
in saturation mode as shown in Fig. 43. Let w is breadth of the channel, L is length of the channel,
2a is maximum width of the channel, 2b(x) is width of the channel at distance x from the edge of the
channel and W(x) is width of depletion on one side of the channel corresponding to 2b(x).

VGG
IG G

+
VGS
w
L
IS _ ID D
S (n)
W(x)
2a 2b(x)
w
W(x)

x RL
p+ type gate

VDD

Fig. 43 Circuit for pinch off voltage of n-channel JFET

As p+ layer of gate is heavily doped so most of the depletion layer lies in n-channel. The width of the
depletion layer in the channel can be is given by,
2ε
W(x) = [Vo +VGS (x)] (163)
q ND

where, ND is donor concentration in the channel, ε is permittivity of semiconductor, is Vo barrier

potential and VGS(x) is reverse biasing voltage at distance x from the left edge of the channel.
The total width of depletion layer at any distance ‘x’ from left edge of channel can be represented in
terms of a & b as under,
2W(x) = 2a – 2b(x)
⇒ W(x) = a – b(x)
⇒ W = a – b(x) (164)
From equations (163) and (164), we have,
2ε
a – b(x) = [Vo +VGS (x)] (165)
q ND

At pinch off, b(x) = 0 and Vo + VGS(x) ≈ VP

2ε
∴ a = VP (166)
q ND

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [76]

q ND 2
⇒ VP = . a (167)
2ε

Relation between VGS and VP

The relation between VGS and VP can be obtained by putting Vo + VGS ≈ VGS in equation (165) as
under,
2ε 1
a – b = . .VGS (168)
q ND

From equations (166) and (168), we have,

V
⇒ a – b = a GS (169)
VP

2
 b
⇒ VGS= 1 −  . VP (170)
 a

 1

 V  2
⇒ b = a 1 −  GS  (171)
  VP  

4.4 Volt-ampare characteristic of JFET for ohmic region

The drain current for small voltage between drain and source can be given by
ID = q(nµn + pµp)EA
Where, E is electric field in the channel and A is effective area of cross section of the channel.
For, n channel, n ≈ ND and n >> p
∴ ID ≈ q ND µn EA (172)
VDS
Here, E = (173)
L

where, L is length of the channel.

The effective area of cross-section of the channel,
A = 2bw (174)
VDS
⇒ ID = q N D µ n × 2bw (175)
L

Putting expression of b from equation (171) in above equation, we have,

 1

2aq N D µ n w  V  2
1 − GS  V
=
⇒ ID (176)
L   VP   DS

It is observed from above equation that drain current, ID ∝ VDS in ohmic region, therefore, JFET

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [77]
behaves like a resistance in ohmic region. This resistance is function of gate to source voltage VGS.
Therefore, device behaves like voltage controlled resistance. Because of this characteristic JFET can
be used as a Voltage Variable Resistor (VVR) when it is operated in ohmic region.
Channel Resistance in ohmic region,
VDS
rd = (177)
ID
rd,ON
⇒ rd = 1 (178)
 VGS  2
1−  
 VP 

where, rd,ON = (179)

2aq N w
The channel resistance rd,ON is ON state resistance of JFET. It is drain resistance at VGS = 0. It is given
by,
V
rd,ON = DS (180)
ID V = 0
GS

The V-I characteristics of JFET for ohmic region are drawn in Fig.44. It is observed from equation
(178) that the channel resistance of JFET increases with increase in gate to source voltage. Therefore,
slope of the V-I character decreases with increase in gate to source voltage as shown in Fig. 44.

ID |VGS1| > |VGS2| > |VGS3|

VGS3

VGS2

VGS1

VDS
Fig. 44 Volt-ampare characteristic of JFET for ohmic region

Drain current in saturation region :
VDS
The electric field in channel, E = (181)
L

The drain current in active region is almost independent of VDS and it is given by:
 1

  VGS  2 
ID = 2aq N D µ n WE 1 −  (182)
  VP  

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [78]
The mobility of electrons is related to the electric field as under,
µn ∝ E −1 ;
E > 104 V/cm
−1

∝ E 2 ; 103 < E < 104

= constant ; E < 103
For saturation VDS is large so the electric field is large. Therefore,
µn ∝ E−1
or
µn = kE−1 ; where k is constant of proportionality. (183)
 1

  VGS  2 
⇒ ID = 2kaq N D W 1 −  (184)
  VP  

It observed from this equation that the drain current becomes independent of voltage VDS in saturation
region.

Note : i. JFET behaves like ohmic device for small VDS and like constant current source for large VDS in
saturation region.
ii. FET has higher ON state resistance than BJT because it behaves like a resistor when it is
operated as a closed switch in ohmic region. Therefore, continuous conduction losses are more
in FET than a BJT. But switching losses in FET are less because it is a unipolar device and their
is no reverse biased junction in the path of load current. So, the reverse recovery time of FET is
negligible as compare to BJT. Due to which the losses during turning off are negligible. Since,
the turn off time of FET is negligible due to negligible reverse recovery time, therefore, the
switching frequency of FET is very high as compare to BJT.

Example 19
Common Data for Questions A and B:
The channel resistance of an N-channel JFET shown in the figure below is 600 Ω when the full
channel thickness (tch) of 10 µm is available for conduction. The built-in voltage of the gate P+N
junction (Vbi) is – 1V. When the gate to source voltage (VGS) is 0V, the channel is depleted by 1 µm
on each side due to the built-in voltage and hence the thickness available for conduction is only 8 µm.

+
Gate
VGS +
P
– Source tch N Drain
+
P

A. The channel resistance when VGS = 0 V is

(a) 480 Ω (b) 600 Ω
(c) 750 Ω (d) 1000 Ω

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [79]
B. The channel resistance when VGS = –3 V is
(a) 360 Ω (b) 917 Ω
(c) 1000 Ω (d) 3000 Ω
GATE(EC/2011/2M)
Solution:
A. Ans.(c)
+
VGS p +

W n
– Drain
2a = tch 2b
Source ID
W
p +

Width of depletion layer,

W = a – b
where,
2a → Full channel thickness.
2b → Effective width of channel.
The drain current of JFET can be given by,
VDS
JD = σE ≈ N D qµ n ·
L
Let effective area of cross-section of channel,
A = 2bw
where, w → breadth of channel
VDS
∴ ID = 2bWJD= 2bWNDqµn
L
Channel resistance for small values of VDS in ohmic region,
V′ L
⇒ rd = DS =
ID 2bWN D qµ n

1
⇒ rd ∝
2b

2b1
⇒ rd2 = ·rd1
2b 2

Given, rd1 = 600Ω, 2b1 = 10µm, 2b2 = 8µm

10
∴ rd2 = × 600 = 750Ω
8

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [80]
B. Ans.(c)
Width of depletion layer in n-channel JFET is given by,
2ε 1
W = · ·(Vo + VGS )
q ND
Where, Vo is built in potential at pn-junction
∴ W ∝ Vo + VGS

Given, W = 1µm when VGS = 0, Vo = –1V

When, VGS = –3V
1/ 2
 −1 − 3 
W2 =   × 1 µm = 2µm
 −1 − 0 
∴ Effective width of channel,
2b = 2a – 2W2 = 10 – 4 = 6 µm
10
Drain resistance, rd3 = × 600 = 1000 Ω
6

4.5 Transfer characteristics of JFET

JFET behaves like a constant current device in saturation region . In this region, the drain current
is at saturation level and is independent of drain to source voltage but it varies as a function of gate
to source voltage. The variation of drain current as a function of gate to source voltage in saturation
region is called transfer characteristic. In saturation region, the drain current as a function of gate to
source voltage is given by,
2
 V 
I DS I DSS 1 − GS 
= (185)
 VP 

where, IDSS is drain current when VGS = 0 i.e. gate is shorted to source. The transfer characteristics of
JFET are as shown in Fig.45.
IDS

IDSS

VP VGS
Fig. 45 Transfer characteristic of JFET
When VGS = VP , the drain current becomes ‘0’ and device behaves like open switch. When drain to
source voltage is increased with fixed VGS applied, the drain current also increases and channel width
reduces. The channel width never reduces to zero with increase in drain to source voltage because the

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [81]
current density will become infinite. So, when VDS is increased the channel width reaches a minimum
level at a threshold value of VDS and current becomes constant and the device enters into saturation
region. This current in saturation region can be reduced to zero only by applying negative VGS i.e.
gate to source voltage equal to pinch off voltage. When VGS is greater than VP, a small leakage current
flows through the device from drain to source. These current is called ID,OFF. The current ID,OFF is order
of nano-amperes.
Note : Since the output drain current of FET is function of gate to source input voltage, therefore, FET is an
example of voltage controlled current source.

Gate reverse current (IGSS):

This is the current which flows from gate to source when VGS > VP with drain short circuited with
source. The IGSS is of order of nano-amperes for silicon.

D
IGSS

VGS >VP
S

Fig. 46 Gate reverse current of JFET

Note : FETs/MOSFETs are fabricated with silicon because:

i) Wafer preparation is easy.
ii) Silicon is available in abundance.
iii) IC fabrication is easy with silicon.
iv) Many devices can be fabricated with single crystal layer.
v) Silicon can be used as a semiconductor when it is single crystal and it can be used as a insulator
with SiO2.
vi) It is stable at higher temperature.
4.6 Transconductance of JFET
The transconductance of JFET is defined as rate of change of drain current with respect to gate to
source voltage for fixed value of drain to source voltage.
∂ ID
gm = (186)
∂VGS

Drain current of JFET for saturation region in terms of pinch off voltage is given by,
2
 V 
ID = I DSS 1 − GS  (187)
 VP 

∂   V  
2
 V   −1 
⇒ gm =  I DSS 1 − GS  = 2 I DSS 1 − GS  ×  
∂VGS   VP    VP   VP 

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [82]
−2 I DSS  VGS 
⇒ gm =
VP 1 − V  (188)
 P 

 V 
g m g mo 1 − GS 
⇒ = (189)
 VP 

2 I DSS
where, gmo = − = Maximum Transconductance (190)
VP

From equation (187), we have,

 VGS  I DS
1 − V  = I (191)
 P  DSS

Putting above relation in equation (188), we have,

−2 I DS I DSS I I
=
gm = 2 DS DSS (192)
VP | VP |

Example 20
An n-channel JEFT has IDSS = 2mA and VP = −4 V. Its transconductance gm (in millimho) for an
applied gate to-source voltage VGS of −2 V is
(a) 0.25 (b) 0.5
(c) 0.75 (d) 1.0
GATE(EC/1999/2M)
Solution : Ans.(b)
Transconductance of n-channel JFET is given by,
 V 
gm = g mo 1 − GS 
 VP 

2 I DSS  VGS 
⇒ gm = − 1 − 
VP  VP 

Given, IDSS = 2 mA, VP = –4 V

and VG S = – 2V
2 × 2  (−2) 
⇒ gm = − 1− millimho
−4  (−4) 

⇒ gm = 0. 5 millimho

4.7 Small Signal Model of FET

The small signal model of a FET is represented in manner similar to a BJT. The drain current for
small signal is formally represent as function of drain to source voltage and gate to source voltage as
under,

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [83]
iD = f(vGS, vDS) (193)
If both gate and drain voltages are variable then the drain current can be obtained by consider only
first two terms of Taylor’s series expansion, the drain current of FET can be given by
∂ iD ∂ id
∆ iD = ⋅ ∆vGS + ⋅ ∆ vDS (194)
∂ vGS VDS
∂vDS VGS

For small signals, ∆iD = id , ∆vDS = vds , ∆vGS = vgs

1
⇒ =id g m vgs + . vds (195)
ro

δ id δ vDS
where, gm = and rd = (196)
δvGS VDS = constant
δ iD VGS = constant

The parameter gm is called mutual conductance or transconductance of FET. It is also designated

as common source forwarded transconductance. The second parameter rd is drain resistance of the
FET.
The small signal model of FET can be drawn by using equation (195) as as shown in Fig. 47.

D G id D
id + + +
G gm vgs vds
vds vgs rd
+
vgs – – –
–
S S S
(a) JFET (b) Small signal model
Fig. 47 Small signal model of FET

Small Signal Voltage Gain or Amplification Factor of FET

∂vDS
µ = = gmrd (197)
∂vGS
Temperature Dependence of rd and gm
The drain current in FET deceases with increase in temperature due to decrease in mobility of carriers
in the channel with increase in temperature of the device. The the drain resistance of FET increases
with increase in temperature and transconductance decreases with increase in temperature. Thus,
drain resistance of FET has positive temperature coefficient. The variations in drain resistance and
transconductance with temperature are shown in Fig. 48.

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [84]

gm
rd

T
Fig. 48 Variations of rd and gm of FET with temperature

Note : i. Since MOSFET has positive temperature coefficient, therefore, its resistance increases with
increase in temperature and drain current reduces, because of this characteristic FET never
undergoes a thermal breakdown or secondary breakdown. This characteristic of FET makes it
suitable for parallel operation.
ii. BJT has negative temperature coefficient, therefore, it suffers from secondary or thermal
breakdown. This characteristic of BJT makes it unsuitable for parallel operation.
4.8 Comparison between JFET and MOSFET parameters
i. Transconductance gain (gm) of MOSFET is more than JFET.
ii. Drain resistance (rd)of JFET is of order of MΩ and that of MOSFET is of order of kΩ. JFETs
have characteristic curves more flat than those of MOSFETs indicating a higher drain resistance
due to low resistance offered by channel compared in JFET.
iii. Drain to source capacitance (Cds) is of same order for both JFET and MOSFET
iv. Gate to source capacitance (Cgs)an gate to drain capacitances (Cgd) are of same order.
v. Gate to source or input resistance (rgs) of MOSFET is higher than that of JFET. This is due to
negligibly small leakage current in MOSFET as compared to JFET.
vi. Gate to drain resistance (rgd) of MOSFET is higher than that of JFET.
vii. JFETs can only be operated in the depletion mode whereas MOSFETs can be operated in either depletion
or in enhancement mode.
viii. When JFET is operated with a reverse bias on the junction, the gate current IG is larger than it
would be in a comparable MOSFET. The current caused by minority carrier extraction across a
reverse-biased junction is greater, per unit area, than the leakage current that is supported by the
oxide layer in a MOSFET. Thus MOSFET devices are more useful in electro-meter applications
than are the JFETs.
ix. MOSFETs are somewhat easier to manufacture, they are more widely used than are the JFETs.
x. MOSFET has higher speed of operation compared to JFET’s.
xi. Because the oxide layer is so thin, the MOSFET is susceptible to permanent damage by
electrostatic charges. Even a small electrostatic build up can destroy a MOSFET permanently.
But this can be avoided mostly by careful and intelligent design of the device.

rrr

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GATE QUESTIONS

Q.1 A MOS capacitor made using p type substrate is in the accumulation mode. The dominant charge in
the channel is due to the presence of
(a) holes (b) electrons
(c) positively charged ions (d) negatively charged ions
GATE(EC/2005/2M)
Q.2 The figure shows the high-frequency capacitance-voltage (C-V ) characteristics of a Metal/SiO2 /
silicon (MOS) capacitor having an area of 1×10–4 cm2. Assume that the permitivities (ε 0 ε r ) of silicon
and SiO2 are 1×10–12 F/cm and 3.5×10–13 F/cm respectively.

C
7pF
1pF
0 v

Consider the following statements about the C - V characteristics plot :

S1: The MOS capacitor has an n-type substrate.
S2: If positive charges are introduced in the oxide, the C-V plot will shift to the left.
Then which of the following is true ?
(a) Both S1 and S2 are true (b) S1 is true and S2 is false
(c) S1 is false and S2 is true (d) Both S1 and S2 are false.
GATE(EC/2007/2M)
Q.3 The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of
this MOS is in

SiO2
EFm
B EC
B EFs
Ei
Ev

(a) inversion (b) accumulation

(c) depletion (d) flat band
GATE(EC-III/2016/1M)

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Q.4 Figures I and II show two MOS capacitors of unit area. The capacitor in Figure I has insulator
materials X (of thickness t1 = 1 nm and dielectric constant ε1 = 4) and Y (of thickness t2= 3 nm and
dielectric constant ε2 = 20). The capacitor in Figure II has only insulator material X of thickness tEq.
If the capacitors are of equal capacitance, then the value of tEq (in nm) is ..............

Metal Metal
t 
tq 
t 
Si Si

Figure I Figure II
GATE(EC-III/2016/2M)
Q.5 The figure shows the high-frequency C-V curve of a MOS capacitor (at T = 300 K) with Φms =
0 V and no oxide charges. The flat-band, inversion, and accumulation conditions are represented,
respectively, by the points
C
P

VG
0

(a) P, Q, R (b) Q, R, P
(c) R, P, Q (d) Q, P, R
GATE(EC/2019/1M)
Q.6 Which of the following effects can be caused by a rise in the temperature ?
(a) Increase in MOSFET current (IDS) (b) Increase in BJT current (Ic)
(c) Decrease in MOSFET current (IDS) (d) Decrease in BJT current (Ic)
GATE(EC/1990/2M)
Q.7 The threshold voltage of an n channel MOSFET can be increased by
(a) Increasing the channel dopant concentration
(b) Reducing the channel dopant concentration
(c) Reducing the gat-oxide thickenss
(d) Reducing the channel length
GATE(EC/1994/1M)
Q.8 The MOSFET switch in its on-state may be considered equivalent to
(a) Resistor (b) Inductor
(c) Capacitor (d) Battery
GATE(EE/1998|1-M)

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Q.9 An enhancement type n-channel MOSFET is represented by the symbol

(a) (b)

(c) (d)

GATE(EE/1999|1 M)
Q.10 The effective channel length of a MOSFET in saturation decreases with increase in
(a) gate voltage (b) drain voltage
(c) source voltage (d) body voltage
GATE(EC/2001/1M)
Q.11 MOSFET can be used as a
(a) current controlled capacitor (b) voltage controlled capacitor
(c) current controlled inductor (d) voltage controlled inductor
GATE(EC/2001/1M)
Q.12 The variation of drain current with gate-to-source voltage (ID-VGS characteristic) of a MOSFET is
shown in Figure The MOSFET is
ID

0 VGS
(a) an n-channel depletion mode device (b) a p-channel depletion mode device
(c) an n-channel enhancement mode device (d) a p-channel enhancement mode device
GATE(EE/2003|1 M)
Q.13 For an n-channel enhancement type MOSFET, if the source is connected at a higher potential than
that of the bulk (i.e.VSB > 0), the threshold voltage VT of the MOSFET will
(a) remain unchanged (b) decrease
(c) change polarity (d) increase
GATE(EC/2003/1M)
Q.14 For an n-channel MOSFET and its transfer curve shown in figure the threshold voltage is

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [88]
ID
VD = 5V

characteristics
D

Transfer
VG = 3V

S
1V VGS VS = 1V
(a) 1 V and the device is in active
(b) –1 V and the device is in saturation region
(c) 1 V and the device is in saturation region
(d) –1 V and the device is in active region
GATE(EC/2005/2M)
Q.15 Group I lists four different semiconductor devices. Match each device in Group I with its characteristic
property in Group II
Group I Group II
P. BJT inversion 1. Population
Q MOS capacitor 2. Pinch-off voltage
R LASER diode 3. Early-effect
S. JFET 4. Flat-band voltage
(a) P-3, Q-1, R-4, S-2 (b) P-1, Q-4, R-3, S-2
(c) P-3,Q-4, R-1, S-2 (d) P-3,Q-2, R-1, S-4
GATE(EC/2007/2M)
Q.16 The measured transconductance gm of an NMOS transistor operating in the linear region is plotted
aginst the gate voltage VG at a constant drain voltage VP . Which of the following figures represents
the expected dependence of gm on VG ?

gm gm

(a) (b)

VG VG
gm gm

(c) (d)

VG VG

GATE(EC/2008/2M)

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Q.17 The drain current of a MOSFET in saturation is given by ID = K (VGS – VT )2 where K is a constant.
The magnitude of the transconductance gm is
K (VGS − VT ) 2
(a) (b) 2 K (VGS − VT )
VDS
ID K (VGS − VT ) 2
(c) (d)
VGSVDS VGS

GATE(EC/2008/1M)
Q.18 Consider the following two statements about the internal conditions in an n-channel MOSFET
operating in the active region.
S1: The inversion charge decreases from source to drain
S2: The channel potential increases from source to drain
Which of the following is correct ?
(a) Only S2 is true
(b) Both S1 and S2 are false.
(c) Both S1 and S2 are ture, but S2 is not a reason for S1
(d) Both S1 and S2 are true, and S2 is a reason for S1
GATE(EC/2009/2M)
Q.19 At room temperature, a possible value for the mobility of electrons in the inversion layer of a silicon
n-channel MOSFET is
(a) 450 cm2/V-s (b) 1350 cm2/V-s
(c) 1800 cm2/V-s (d) 3600 cm2/V-s
GATE(EC/2010/1M)
Q.20 The source of a silicon (ni= 10 per cm ) n-channel MOS transistor has an area of 1 sq µm and a depth
10 3

of 1µm.If the dopant density in the source is 1019/cm3,the number of holes in the source region with
the above volume is approximately
(a) 107 (b) 100
(c) 10 (d) 0
GATE(EC/2012/2M)
Q.21 In a MOSFET operating in the saturation region, the channel length modulation effect causes
(a) an increase in the gate-source capacitance
(b) a decrease in the transconductance
(c) a decrease in the unity - gain cutoff frequency
(d) a decrease in the output resistance
GATE(EC/2013/1M)
Q.22 If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET, it
will lead to
(a) a decrease in the threshold voltage (b) channel length modulation
(c) an increase in substrate leakage current (d) an increase in accumulation capacitance
GATE(EC-I/2014/1M)
Q.23 A depletion type N-channel MOSFET is biased in its linear region for use as a voltage controlled

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [90]
resistor. Assume threshold voltage VTH = –0.5 V, VGS = 2.0 V, VDS = 5 V, W/L = 100, COX =
10–8 F/cm2 and µn = 800 cm2/V-s. The value of the resistance of the voltage controlled resistor
(in Ω) is _______
GATE(EC-I/2014/2M)
Q.24 In MOSFET fabrication, the channel length is defined during the process of
(a) isolation oxide growth (b) channel stop implantation
(c) poly-silicon gate patterning (d) lithography step leading to the contact pads
GATE(EC-III/2014/1M)
Q.25 For the N MOSFET in the circuit shown, the threshold voltage is Vth, where Vth > 0. The source
voltage VSS is varied from 0 to VDD. Neglecting the channel length modulation, the drain current ID as
a function of VSS is represented by
VDD

VSS

(a)

ID ID

(a) (b)

VSS VSS

VDD – Vth Vth

ID ID

(c) (d)
VSS VSS

VDD – Vth VDD – Vth

GATE(EC-I/2015/2M)
Q.26 Which one of the following processes is preferred to form the gate dielectric (SiO2) of MOSFETs?
(a) Sputtering (b) Molecular beam epitaxy
(c) Wet oxidation (d) Dry oxidation
GATE(EC-III/2015/1M)
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [91]
Q.27 A long-channel NMOS transistor is biased in the linear region with VDS = 50 mV and is used as a
resistance. Which one of the following statements is NOT correct?
(a) If the device width W is increased, the resistance decreases.
(b) If the threshold voltage is reduced, the resistance decreases.
(c) If the device length L is increased, the resistance increases.
(d) If VGS is increased, the resistance increases.
GATE(EC-II/2016/1M)
Q.28 Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET):
P: As channel length reduces, OFF-state current increases.
Q: As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.
Which of the above statements are INCORRECT?
(a) P and Q (b) P and S
(c) Q and R (d) R and S
GATE(EC-I/2016/1M)
Q.29 Consider an n-channel MOSFET having width W, length L, electron mobility in the channel µn and
oxide capacitance per unit area Cox. If gate-to-source voltage VGS= 0.7V, drain-to-source voltage VDS =
0. 1V, (µn Cox) = 100 µA/V2, threshold voltage VTH = 0.3 V and (W/L) = 50, then the transconductance
gm (in mA/V) is _______.
GATE(EC-II/2017/1M)
Q.30 An n-channel enhancement mode MOSFET is biased at VGS > VTH and VDS > (VGS – VTH) where VGS is the
gate-to-source voltage, VDS is the drain-to-source voltage and VTH is the threshold voltage. Considering
channel length modulation effect to be significant, the MOSFET behaves as a
(a) voltage source with zero output impedance
(b) voltage source with non-zero output impedance
(c) current source with finite output impedance
(d) current source with infinite output impedance
GATE(EC-II/2017/1M)
Q.31 Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double
that of T1. Both the transistors are biased in the saturation region of operation, but the gate overdrive
voltage (VGS – VTH) of T2 is double that of T1, where VGS and VTH are the gate – to – source voltage
and threshold voltage of the transistors, respectively. If the drain current and transconductance of T1
are ID1 and gm1 respectively, the corresponding values of these two parameters for T2 are
(a) 8ID1 and 2gm1 (b) 8ID1 and 4gm1
(c) 4ID1 and 4gm1 (d) 4ID1 and 2gm1
GATE(EC-II/2017/2M)
Q.32 Given, Vgs is the gate-source voltage, Vds is the drain source voltage, and Vth is the threshold voltage
of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are
(a) Vgs < Vth ; Vds ≥ Vgs – Vth (b) Vgs > Vth ; Vds ≥ Vgs – Vth

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [92]
(c) Vgs > Vth ; Vds ≤ Vgs – Vth (d) Vgs < Vth ; Vds ≤ Vgs – Vth
GATE(EE/2019/1M)
Q.33 An n-channel JFET has a pinch-off voltage of Vp = – 5 V, VDS (max) = 20 V, and gm = 2mA/V. The
minimum ‘ON’ resistance is achieved in the JEFT for
(a) VGS = – 7V and VDS = 0V (b) VGS = 7V and VDS = 0V
(c) VGS = 0V and VDS = 20V (d) VGS = – 7V and VDS = 20V
GATE(EC/1992/2M)
Q.34 The action of JFET in its equivalent circuit can best be represented as a
(a) Current Controlled Voltage Source (b) Current Controlled Voltage Source
(c) Voltage Controlled Voltage Source (d) Voltage Controlled Current Source
GATE(EC/2003/2M)
Q.35 The cross section of a JFET is shown in the following figure. Let VG be − 2V and let VP be the initial
pinch-off voltage. If the width w is doubled (with other geometrical parameters and doping levels
remaining the same), then the ratio between the mutual transconductances of the initial and the modified
JFET is
Gate VG
+
p

Source n w Drain
+
p
Gate VG

1  1 − 2 / VP 
(a) 4 (b)  
2  1 − 1 / (2VP 


1  1 − 2 / VP  1 − (2 / VP )
(c)   (d)
2  1 − 1 / (2VP 
 1 − (1 / 2 VP )
GATE(EC/2008/2M)
Q.36 Which of the following can be considered to be the advantage of FET amplifiers as compared to BJT
amplifiers?
1. Higher input impedance
2. Good bias stability
3. Higher gain-bandwidth product
4. Lower noise figure
Select the correct answer using the codes given below:
Codes:
(a) 1,2 and 3 (b) 1,2 and 4
(c) 2,3 and 4 (d) 1,3 and 4
Q.37 Which of the following can be considered to be the advantage of FET amplifiers as compared to BJT
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [93]
amplifiers?
1. Higher input impedance
2. Good bias stability
3. Higher gain-bandwidth product
4. Lower noise figure
Select the correct answer using the codes given below:
Codes:
(a) 1,2 and 3 (b) 1,2 and 4
(c) 2,3 and 4 (d) 1,3 and 4
GATE(EC/1990/2M)
Q.38 The “Pinch off” voltage of a JFET is 5.0 volts. Its “Cut off” voltage is
(a) (5.0)1/2V (b) 2.5 V
(c) 5.0 V (d) (5.0)3/2V
GATE(EC/1990/2M)
Q.39 The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an
uncharged condition, a bias of +3 V is applied to the gate contact with respect to the body contact.
The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained
within the dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value
in Coulombs, rounded off to the nearest integer) is _______.

GATE
Silicon Dioxide
Si
BODY

DASHED BOX
GATE(EE/2020/1M)
Q.40 For an n-channel silicon MOSFET with 10 nm gate oxide thickness, the substrate sensitivity
( ∂VT / ∂VBS ) is found to be 50 mV/V at a substrate voltage |VBS| = 2 V, where VT is the threshold
voltage of the MOSFET. Assume that, |VBS| » 2ΦB, where qΦB is the separation between the Fermi
energy level EF and the intrinsic level Ei in the bulk. Parameters given are
Electron charge (q) = 1.6 × 10–19 C
Vacuum permittivity (ε0) = 8.85 × 10–12 F/m
Relative permittivity of silicon (εSi) = 12
Relative permittivity of oxide (εox) = 4
The doping concentration of the substrate is
(a) 7.37 × 1015 cm–3 (b) 4.37 × 1015 cm–3
(c) 2.37 × 1015 cm–3 (d) 9.37 × 1015 cm–3
GATE(EC/2021/2M)

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [94]
Q.41 The band diagram of a p-type semiconductor with a band-gap of 1 eV is shown. Using this
semiconductor, a MOS capacitor having VTh of –0.16 V, C′ox of 100 nF/cm2 and a metal work function

of 3.87 eV is fabricated. There is no charge within the oxide. If the voltage across the capacitor is VTh.
the magnitude of depletion charge per unit area (in C/cm2) is
Vacuum level

4 eV

EC
0.5 eV
Ei
EFs
0.2 eV
EV
(a) 1.70 × 10–8 (b) 0.52 × 10–8
(c) 1.41 × 10–8 (d) 0.93 × 10–8
GATE(EC/2020/2M)

rrr

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [95]

ANSWERS & EXPLANATIONS

Q.1 Ans.(a)
In accumulation mode of MOS capacitor, with p-substrate, the dominant charge is due to presence
of holes and in inversion mode of same capacitor the dominant charge is due to electrons. The
capacitor is in accumulation mode when metal plate is applied negative potential with respect to
semi conductor and inversion mode is observed when metal plate is given positive potential w.r.t.
semiconductor layer.

Q.2 Ans.(c)
C
7pF

V
VT
Statement, S1 : From given characteristics it is observed that capacitance minimum beyond positive
value of voltage V. This voltage is called threshold voltage. The threshold voltage is positive only for
a p-substrate. Hence given MOS capacitor has p-substrate. So, given statement S1 is false.
Statement, S2 : If positive charges are introduced in oxide layer the threshold voltage required for
inversion of charges below oxide layer is reduced because positive charges exert additional attractive
force on electrons of p-substrate. Therefore, C-V plot will shift to the left when positive charges are
introduced in oxide. So, given statement S2 is true.

Q.3 Ans. (a)

SiO2
EFm
B EC
B EFs
Ei
Ev

It is observed from above diagram that the intrinsic Fermi level is in bulk of substrate is below the
actual Fermi level and it is above the actual Fermi level at the oxide-semiconductor interface which

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [96]
is possible only in inverse mode of operation of the MOS capacitor.
Q.4 Ans. 1.55:1.65

Metal Metal
t 
tq 
t 
Si Si

Figure I Figure II
The equivalent capacitance of combination in Figure I is two capacitors connected in seires as under,

CX

CY

The equivalent capacitance of series combination of capacitors is given by,
CX CY
Ceq1 = .....(i)
CX + CY

If capacitor has unit are then capacitances of material X & Y per unit area are given by,
ε1εo
CX = = Capacitance per unit area of X
t1

ε 2 εo
CY = = Capacitance per unit area of Y
t2

The capacitance per unit area of capacitor of Figure II is given by,

ε1εo
Ceq2 = .....(ii)
t Eq

If both Figure I and Figure II are having equal capacitances the from equations (i) and (ii), we have,

ε1εo CX CY

=
t Eq CX + CY

ε1εo ε 2 εo
×
ε1εo t1 t2
⇒ =
t Eq ε1εo ε 2 εo
+
t1 t2

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [97]
ε1t 2 + ε 2 t1
⇒ tEq =
ε2

Given, t1 = 1 nm, ε1 = 4, t2= 3 nm and ε2 = 20

4 × 3 + 20 × 1
⇒ tEq = nm
20

⇒ tEq = 1.6 nm

Q.5 Ans.(b)
Given C-V curve of MOS capacitor,
C
P

VG
0

(i) When V is negative the MOS capacitor works in Accumulation mode at ‘P’.
(ii) When V = 0, the MOS capacitor offers flat band at ‘Q’.
(iii) Finally MOS capacitor works in inversion mode with V > 0 at ‘R’.
Q.6 Ans.(b,c)

Reverse saturation current in BJT double for every 10°C rise in temperature. β of BJT also increases
with increase in temperature. Since IC = βIB + (1 + β) ICO, therefore IC, increases with increase in
temperature. A MOSFET has positive temperature coefficient so its drain resistance increases with
increase in temperature hence drain current decreases with increase in temperature.

Q.7 Ans.(a)

The threshold voltage of n-channel MOSFET can be increased by increasing the channel dopant
concentration or by increasing the oxide thickness.
Note :- Methods of reducing VTH :
i) By using Si with <100> structure instead of <111> structure.
ii) By using layer of (Si3 N4 + Si O2) instead of Si O2 alone
iii) Poly crystalline Si doped with boron is used as gate electrode instead of Al.
iv) By reducing thickness of oxide layer which in turn increases oxide capacitance.
v) By decreasing doping concentration in substrate.

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [98]
vi) By ion implantation near drain and source terminals
vii) By connecting the source at lower potential than Bulk.
Q.8 Ans.(a)
MOSFET behaves like a closed switch when it is operated in ohmic region of its drain characteristics.
In ohmic region it offers a finite resistance. So, the MOSFET switch in its on-state may be considered
equivalent to a resistor.

Q.9 Ans.(a)

i) Symbols of MOSFETs :
Type of MOSFET
n-channel p-channel

D D
D
E G SS G SS
P S S
L
E D D
T
I G G
O
N S S
D D
T
Y
G G
P
E
S S

E
N D D
H
A G SS G SS
N
C S S
E
M
E
N D D
T
G G
T
Y S S
P
E

ii) Symbols of JFETs :–

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [99]
D D

G G

S S
n-channel p-channel

Q.10 Ans.(b)
Effective channel length of a MOSFET in saturation decreases with increase in drain voltage.
Q.11 Ans.(b)
MOSFET can be used as voltage controlled capacitor.
Q.12 Ans.(b)
Transfer characteristics of MOSFETS :
Case-I: n-channel depletion mode
IDS

– VGS + VGS
Case-II: p-channel depletion mode
IDS

+ VGS
Case-III: n-channel enhancement mode
IDS

VT + VGS

Case-IV p-channel enhancement mode

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [100]
IDS

–VGS –VT + VGS

Q.13 Ans.(d)
The threshold voltage of n-channel enhancement type MOSFET increases if source is connected at
higher potential than Bulk.
Q.14 Ans.(c)
ID
VD = 5V
characteristics

D
Transfer

VG = 3V

S
1V VGS VS = 1V
From transfer characteristic threshold voltage of MOSFET,
VT = 1V
From MOSFET voltages,
VGS = VG – VS = 3 – 1 = 2V
VGS – VT = 2 – 1 = 1 V
Also, VDS = VD – VS = 5 – 1 = 4V
MOSFET operates in saturation region when VDS > (VGS – VT)
Since given VDS is more than (VGS – VT), therefore, MOSFET must be operating in saturation region
of output characteristic.
Q.15 Ans.(c)
I) BJT exhibits early effect
II) MOS capacitor has flat band voltage.
III) LASER diode exhibit population inversion
IV) JFET has a pinch voltage
Q.16 Ans.(a)
Variation of transconductance of NMOS as a function of gate voltage is as shown below

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [101]
gm

gm1 max

VT VG

Q.17 Ans.(b)
Given, ID = K (VGS – VT)2
The transconductance of MOSFET is defined by
∂I D
gm =
∂VGS VDS = constant

∂
⇒ gm = [K(VGS − VT ) 2 ]
∂VGS

⇒ gm = 2K[VGS – VT]
Q.18 Ans.(d)
The inversion charge decreases in n-channel MOSFET from source to drain because the channel
potential increases from source to drain.
G
SiO2 d
source Inversion
side Drain
Depletion side
n-channel MOSFET
Vx L VD

o L
Q.19 Ans.(a)
The mobility of electron in n-type Si semiconductor is 1350 cm2/V-s but mobility of carriers decreases
with increase in electric field. The electric field in inversion layer of n-channel MOSFET is high. So
mobility of electrons falls below 1350 cm2/V-s. So, option (a) is correct.

Q.20 Ans.(d)
In n-channel MOS transistor the source region is also n-type and in n-type material the number holes are
equal to the number of intrinsic electrons.
Volume of the source = 1 × 10–12 × 1 × 10–6 = 10–18 m3
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [102]
Density of intrinsic electrons,
ni = 1010 × 106 / m3 = 1016 per m3
Number of intrinsic electrons = 1016 × 10–18
= 10–2 = 0.01
Number of holes = Number of intrinsic electrons
= 0.01 ≈ 0
Q.21 Ans.(d)
When gate to source voltage of n – MOSFET is increased the effective channel length is reduced
which is called channel length modulation . The channel length modulation has following effects,
i. Output resistance (drain resistance) of MOSFET reduces.
ii. High frequency response of MOSFET is improved. So, unity given cut off frequency is increased.
iii. Trans conductance of MOSFET is increased.
iv. Switching speed is increased.
Q.22 Ans.(a)
If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET,
it will lead to a decrease in the threshold voltage and increase in Flat band voltage. The flat band
voltage becomes more negative in n-channel MOSFET.
Q.23 Ans.: 499 to 501
The n-channel MOSFET can be used as a voltage controlled resistor when it is operated in Ohmic
region. The drain current in ohmic region of operation is given by,
µn Cox   1
ID =  ( VGS − VT ) VDS − VDS2 
L  2 

The channel conductance in ohmic region is defined as,

∂ ID
gD =
∂ VDS

µn Cox 
⇒ gD = ⋅ ( VGS − VT ) − VDS 
L

⇒ gD = 800 × 10–8 × 100 [(2 – (0.5) –5]

gD = 2000 × 10 × 100 =
−
500

1
Channel resistance, |rD| = = 500 Ω
gD

Q.24 Ans (c)

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [103]
In MOSFET fabrication, the channel length is defined during the process of poly-silicon gate
patterning.
Q.25 Ans. (a)
VDD

VSS

Since drain is shorted with gate terminal, therefore,

If VDS = VGS then VDS < VGS − Vth .
When VDS < VGS − Vth , the MOSFET operates in ohmic region of operation with drain current given
by,
µ n Cox W  1
ID = ⋅  ( VGS − Vth ) VDS + VDS2 
2 L  2 

Putting, VGS = VDS in above equation, we have,

µ n Cox W  1
ID = ⋅  ( VDS − Vth ) VDS + VDS2 
2 L  2 

From the circuit diagram given above,

VDS = VDD − VSS
Case-I: When VSS = 0, VDS = VDD − 0 = VDD
µ n Cox W  1
⇒ ID = ⋅  ( VDD − Vth ) VDD + VDD 2  .....(i)
2 L  2 

Case-II: When VSS = VDD

VDS = VDD − VDD = 0
⇒ ID = 0
It is observed from above two cases that when voltage VSS is changed from 0 to VDD the drain current
varies non-linearly from value given by equation (i) to zero.
So, option (a) is correct choice.
Q.26 Ans. (d)
Dry oxidation is preferred to form the gate dielectric (SiO2) of MOSFETs.
Q.27 Ans. (d)

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [104]
The drain current in ohmic region of drain characteristics of MOSFET is given by
µn Cox   1
ID =  ( VGS − VT ) VDS − VDS2 
L  2 

Conductance of channel,
∂ I D µn Cox 
gD = = ( VGS − VT ) − VDS 
∂ VDS L

1 1
rD = =
g D µn Cox   V − V − V 
L ( GS T) DS 

Observation :
(i) Channel resistance increases when L is increased
(ii) Channel resistance decreases when channel width W is increased.
(iii) Channel resistance decreases when voltage VGS is increased
So, option (d) is not correct
Q.28 Ans. (c)
When channel length of MOSFET is reduced,
Q: output resistance decreases.
R: threshold voltage remains unchanged
Q.29 Ans. : 0.45 to 0.55
When VDS < VGS – VTH , the MOSFET works in ohmic region.
Given, VGS = 0.7V, VDS = 0.1V ,VTH = 0.3
∴ VGS – VTH = 0.7 – 0.3 = 0.4
Here, VDS < VGS – VTH , so given MOSFET works in ohmic region for given VDS and VGS. Two drain
current in ohmic region is given by,
µn Cox   1 2 
ID =
L ( VGS − VT ) VDS − 2 VGS 
 

Trans conductance in given as,

∂ I D µn Cox 
gm = = ⋅ VDS
∂ VGS L

Given, µnCox = 100µA/V2

W
and = 50, VDS = 0.1V
L

∴ gm = 100 × 10–6 × 50 × 0.1

⇒ gm = 0.5 mA/V
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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [105]
Q.30 Ans. (c)
An n-channel enhancement mode MOSFET operates in saturation region when it is biased at VGS >
VTH and VDS > (VGS – VTH). If channel length modulation effect is significant it behaves current
source with finite output impedance.
Q.31 Ans. (b)
The drain current of n-channel MOSFET in saturation region is given by,
µn Cox 
( VGS − VT )
2
ID = ....(i)
2L

Given 2 = 21 .....(ii)

VGS2 – VT2 = 2 (VGS1 – VT1) ....(iii)
From equation (i)

 ( VGS2 − VT 2 )
2
I D2
= 2 ×
I D1 l ( VGS1 − VT1 )2

2
I D2 2  2 ( VGS1 − VT1 ) 
⇒ = 1 ×
I D1 l VGS1 − VT1

⇒ ID2 = 8 ID1
Transconductance in saturation region of MOSFET,
∂I µm Cox 
=
gm = D ( VGS − VT )
∂ VGS L

g m2 2 ( VGS2 − VT 2 )
⇒ =
g m1 1 ( VGS1 − VT1 )

g m2 21 × 2 ( VGS1 − VT1 )

⇒ =
g m1 1 ( VGS1 − VT1 )

⇒ gm2 = 4 gm1
Q.32 Ans.(b)
NMOS works in saturation region when following two conditions are satisfied.
(i) VGS > VTH
(ii) VDS ≥ VGS – VTH
Note : I. For saturation region,VGS > VTH

VDS ≥ VGS – VTH

II. For ohmic region, V GS
> VTH

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [106]

VDS ≤ VGS – VTH
III. For cutoff region, VGS < VTH
Q.33 Ans.(b)
A JFET behaves like ohmic device in ohmic region of operation. From drain characteristics of JFET
it is clear that the device operates in ohmic region when voltage VDS is very small, ideally, VDS =
0. The slope of characteristics increases with change in VGS from negative to positive. So the given
JFET offers minimum ‘ON’ resistance when VGS is positive and large. i.e. at Vas = +7 v and VDS = 0V
ID

ohmic V=
GS +7 V
region V=
GS 0 V
V=
GS –7 V

V=
GS –V P

VDS

Q.34 Ans.(d)
The action of JEFT in its equivalent circuit can be represented as voltage controlled current source.
Q.35 Ans.(b)
Transconductance of JFET in saturation region is given by,
  V 1/ 2 
gm(sat) = G o 1 −  G  
  VP  

2aZ
Where, Go = = conductance with no gate voltage
ρL

L → Length of channel
a
→ Half width of channel
Z
→ Depth of channel
ρ → Resistivity of material of channel
w → Width of channel
1/ 2
 –V 
1−  G 
g m2 a  VP2 
⇒ = 2 · 1/ 2
g m1 a1  –V 
1−  G 
 VP1 
Given, w2 = 2w1
or a2 = 2a1

and VG = – 2 V

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [107]
VG
+
p
n a
Source W=2a Drain
+
p
VG
⇒ Also pinch off voltage
q a 2 ND
VP =
2∈

⇒ VP ∝ a2
VP2 a2
= 22 = 4
VP1 a1

⇒ VP2 = 4 VP1 = 4 VP

 2 
1/ 2
 2 
1/ 2
  2  
1/ 2

1−   1−    1−   
g m1 a1  VP1  1  VP  1  VP  
⇒ = · 1/ 2 =
· 1/ 2 =  1/ 2 
g m2 a2  2  2  2  2  1 
1−  1−  1 − 
     
V
 P2  4V
 P 2V
  P 

Q.36 Ans.(b)
Advantage of FET amplifiers over BJT amplifiers:
i) Higher input impedance
ii) Good bias stability
iii) Lower noise figure or less noisy.
iv) No secondary breakdown
v) Suitable for parallel operation
vi) Better switching speed
vii) Lower offset voltage, so it is better signal chopper
Disadvantages of FET over BJT amplifiers:
i) Lower gain bandwidth product
ii) Higher on-state resistance so higher on state losses.
iii) Lower power rating
Q.37 Ans.(b)
Advantage of FET amplifiers over BJT amplifiers:
i) Higher input impedance
ii) Good bias stability

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [108]
iii) Lower noise figure or less noisy.
iv) No secondary breakdown
v) Suitable for parallel operation
vi) Better switching speed
vii) Lower offset voltage, so it is better signal chopper
Disadvantages of FET over BJT amplifiers:
i) Lower gain bandwidth product
ii) Higher on-state resistance so higher on state losses.
iii) Lower power rating

Q.38 Ans.(c)
Pinch off voltage,
VP = 5.0 V
At cutoff the gate to source voltage of JFET is equal to pinch off voltage.
∴ VGS(OFF) = VP
⇒ VGS(OFF) = 5.0 V
Q.39 Ans(0 to 0)
Application of positive potential at Gate terminal of metal-oxide-semiconductor structure shown in
figure induces both negative and positive charges. Therefore, net charge on structure as a whole is
always zero.

Q.40 Ans.(a)
The change in threshold voltage due to substrate body effect is given by,
2εs qN A 
( 2φ + VB ) − ( 2φF ) 
1/ 2 1/ 2
∆VT =
Ci  F 

Where, VB is substrate bias voltage.

εox 4 × 8.85 × 10−14
Ci = =
t ox 10 × 10−7

∂VT 1 2 ∈s qN A 1
( 2φF + VB )
−
∴ = 2
∂VB 2 Ci

If 2φF < < | V B|,

∂VT 1 2εs qN A 1
∴ = ×
∂VB 2 Ci | VB |

2 × 12 × 8.85 × 10−14 × 1.6 × 10−19 N A 1

⇒ 50 × 10–3 = −14 −7
×
2 × 4 × 8.85 × 10 / 10 × 10 2

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [109]
⇒ NA ≈ 7.37 × 1015 cm–3
Q.41 Ans(a)
Vacuum level

4 eV

EC
0.5 eV
Ei
EFs
0.2 eV
EV
From given energy level diagram work function of semiconductor,
Eg
φs = Χ + + ( E i − E Fs )
2

φs = 4 + 0.5 + (0.5 – 0.2) = 4.8 eV

Work function of metal, φm = 3.87 eV
Metal to semiconductor work function difference,
qφm − qφs =3.87 − 4.8 =−0.93 eV
qφms =

0.93
⇒ φms = − eV =
−0.93V
q

Threshold voltage of MOS capacitor is given by,

( QdT + Q x ) + 2φ
VTh = − F + φms
Cox

Where, QdT is depletion layer charge, Cox oxide layer capacitance and Qx is charge trapped in oxide
layer.
Here, Qx = 0 (given)
QdT
∴ VTh = − + φms + 2φF
Cox

From given energy diagram

qφF = Ei – EFs = 0.5 – 0.2 = 0.3 eV
φF = 0.3 V
Also given, VTh = –0.16 V

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FETs & MOS Capacitors EDC & ANALOG ELECTRONICS [110]
and Cox = 100 nF/cm2
QdT
⇒ –0.16 = − − 0.93 + 2 × 0.3
100 × 10−9

−1.7 × 10−8 C / cm −2
⇒ QdT =

rrr

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