Op-Amp And Its Applications

1 Introduction
An operational amplifier is a direct coupled high gain amplifier which consists of stages with
differential amplifiers, level shifter and an output stage. An operational amplifier is available in a
single IC package. An operational amplifier can be used to amplify both AC and DC signals. It has
got a number of applications such AC and DC amplifications, active filters, oscillators, comparators,
regulators, waveform generators etc. Fig. 1 shows the block digram of an operational amplifier.

V1 Dual i/P Dual input Level

balanced Compliment-
unbalanced Shifter ary
output o/p Diff. “Emitter
Differential Push-Pull Vo
Amplifier Followers” Amplifier
V2 Amplifier

Fig. 1 Block diagram of operational amplifier

Stages of Op-Amp:
i. First Stage
The input stage of op-amp consists of dual input balanced output differential amplifier. This stage
provides most of the voltage gain of Op-amp. It consist of BJTs/FETs with matched characteristic in
order to have high input impedance.
ii. Second Stage
The output of first is connected at input of second stage. Second stage of op-amp is a dual input
unbalanced output differential amplifier. This stage is used to further increase the voltage gain and to
get single output from dual input. There is direct coupling between input stage and second stage due
to which the DC level of signal at output of second stage is well above the ground level.
iii. Third stage
Third stage of operational amplifier consists of an emitter follower or level shifter. This stage is used
to bring DC level of signal to ground level.
iv. Fourth stage
Last or output stage of an operational amplifier is a push-pull complementary amplifier. This stage
increases the output voltage swing and raises current supplying capability of the op-amp. Therefore,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [2]
output stage is used to enhance the power level at the output of op-amp. The output stage also
provides the low output resistance.

Note : i. Differential amplifier is used at input stage of op-amp to achieve high common mode rejection
ratio. (CMRR).
ii. The differential amplifiers used in op-amp can be BJT or MOSFET based. The matched
characteristics of FETs at input stage help in achieving high Common Mode Rejection Ratio
(CMRR).
iii. The transconductance of BJT is more than MOSFET so the gain of BJT based differential
amplifier is more than a MOSFET based differential amplifier.
iv. An active load can be used in collector circuit of differential amplifier of an op-amp to increase
overall voltage gain.
v. Since, both input and output signals of op-amp are the voltages, therefore, it behaves as a voltage
controlled voltage source.
vi. An operational amplifier has direct coupling among the internal stages, therefore, the op-amp
can amplify signal of very low frequencies including DC signals.

2 Pin Diagram, Symbol and Equivalent circuit of Op-Amp

Symbol:
The schematic symbol of an op-amp is shown in Fig. 2(a). Op-amp has two input terminals with
plus (+) and minus (-) labels and one output terminal. Two additional terminals shown in Fig. 2(a)
are used for power supplies of the op-amp. The input terminal with (+) label is called non-inverting
terminal and input terminal with (-) notation is called inverting terminal. When input is connected
at non-inverting terminal with inverting terminal grounded, the output of op-amp is in phase with the
input signal and when input is applied at inverting terminal with non-inverting terminal connected to
ground, the output signal is 180o out of phase with respect to input signal.

7 +VCC OFFSET
3 1 8 NC
V1 + 6
NULL

Vo
IN 2 8-pin 7 +VCC
2
V2 – IN 3 IC 6 OUT
OFFSET
4 –VEE VEE 4 5 NULL

(a) Symbol (b) Op-amp IC

Fig. 2 Symbol and IC of Op-amp

where, V1 → Voltage at non-inverting input

V2 → Voltage at inverting input
Vo → Voltage at output
+VCC & -VEE → Voltage at output
Pin Diagram:
The pin diagram of an 8 pin IC of operational amplifier is shown in Fig. 2(b). The labellings along

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [3]
with number of each pin indicates the function of pin. The pin number 3 is non-inverting input , pin
2 is inverting input , pin 6 is output terminal of the op-amp. Pin 7 and 4 are power supply terminal
labeled as +VCC and -VEE, respectively. Pin 1 and 5 are used for DC offset null. Pin 8 is labeled as
NC which indicates ‘No Connection’.
Equivalent Circuit of Op-Amp:

+VCC

+
V1
3
Ro
Vd Ri Vo
+ AoLVd
V2
2
–
~ AOLVd
–

VEE
Fig. 3 Equivalent circuit of op-amp
Fig. 3 shows the equivalent circuit of op-amp. The equivalent circuit input resistance (Ri), output
resistance (Ro), open loop voltage gain (AOL).

The input ‘3’ is non inverting terminal and input ‘2’ is inverting terminal.
The output resistance, Ro , is Thevenin’s equivalent resistance seen across output terminal of op-amp.
Vd is differential input voltage of op-amp. The output voltage of op-amp is ,
Vo = AOLVd = AOL(V1-V2) (1)

Note : i. For an ideal Op-amplifier Ri is infinite, Ro is zero and AOL is infinite.

ii. An op-amp is an example of a Voltage Controlled Voltage Source (VCVS)

Example 1
In a circuit, if the open loop gain is 106 and output voltage is 10 volts, the differential voltage should
be
(a) 10 µV (b) 0.1 V
(c) 100 µV (d) 1 µV
IES(E&T,02)
Solution : Ans. (a)
+ +
Vid A Vo
– –

Output voltage of op-amp,

Vo = A Vid
Vo
⇒ Vid =
A
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [4]
Given, A = 106, Vo = 10V
10
⇒ Vid = 6 = 10 µV
10
3 Characteristics of Operational Amplifier
3.1 Input bias current
An op-amp consists of BJT/FET based differential amplifier at input stage. The input terminals of
differential amplifier draw biasing currents which are input bias current of op-amp. The input bias
current is taken to be the average of two current entering at the input terminals of the op-amp. If IB+
is bias current at non-inverting terminal and IB- is bias current at inverting terminal as shown in Fig.
4, then the bias current of op-amp is,

I +B + I -B
IB = (2)
2
+
IB
+ V

IB
–
Fig. 4 Input bias currents of op-amp
Note : Ideally input bias current of an op-amp is zero.
So, ideally, IB = 0
3.2 Input offset current
Input offset current is algebraic difference of biasing currents entering at the inverting and non-
inverting terminals of an op-amp.
I=
io | I B+ - I -B | (3)

Note : Ideally input offset current of an op-amp is zero.

So, ideally, Iio = 0
3.3 Input Offset Voltage
Due to mismatch of characteristics of BJTs/MOSFETs of input stages of an op-amp, there is small
DC voltage at output terminal even if there is no input applied. A small differential input voltage
needs to be applied to reduce this offset voltage at output terminal. This differential input voltage
required to reduce output offset voltage is called input offset voltage as shown in Fig. 5.
Vd = Vio ; when Vo = 0

+ + Vo= 0
Vd = Vio
– –
Fig. 5 Input offset voltage of op-amp

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [5]
Note : i. Offset voltage can be positive or negative.
ii. Ideally input offset voltage of an op-amp is zero.
So, ideally, Vio = 0

3.4 Input Offset Drift Voltage

It is the change in input offset voltage per unit change in temperature.
∆ Vio
Input offset voltage drift = (4)
∆T

∆ Vio
Note : Ideally, = 0
∆T

3.5 Output Offset Voltage

As discussed above, a DC voltage appears at output terminals of an op-amp due to mismatch of
characteristics of BJTs/FETs of input stages of an op-amp even if no input is applied. This output
voltage is called output offset voltage. The output offset voltage is caused by input offset voltage as
well as input bias current. The output offset voltage is represented by Voo.

+
Voo
–

Fig. 6 Output offset voltage of op-amp

Note : Ideally, Voo = 0
Output offset voltage of op-amp with feedback:
An operational amplifier can have two feedback configurations called inverting and non-inverting
configurations. Fig. 7(a) shows the inverting configurations and Fig. 7(b) shows the non-inverting
configuration of op-amp based feedback amplifier.
RF
RF
R1 IB


– R1 IB

Vi –
Vo
+ Vo
IB
+ +
+
IB
Vi

(a) Inverting configuration (b) Non-inverting configuration

Fig. 7 Output offset voltage due to Vio and IB
The output offset voltage in both inverting and non-inverting configurations of operational amplifier
can be either voltage or current generated. The output offset voltage of the both inverting as well as
non-inverting amplifiers due to input offset voltage is given by,
 RF 

Voo = 1 + Vio (5)
 R1 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [6]
Where , Vio is input offset voltage of op-amp.
The output offset voltage due to input bias current for both inverting as well as non-inverting
amplifiers is given by,
VoIB = RfIB (6)

IB+ + IB-

Where , IB = 2 = Input bias current (7)

The offset voltage due to Vio and IB can be either positive or negative individually. So, the output
offset voltage is maximum when polarity of both offset voltage are same. The total maximum output
offset voltage of amplifier due to input offset voltage and bias current would be,
VooT = Voo + VoIB (8)

 RF 
⇒ VooT = 1 +  Vio + RFIB (9)
 R1 

The output offset voltage due to input bias current (IB) can be minimized by connecting a resistance
ROM in non-inverting terminal both inverting as well as non-inverting amplifiers as shown in Fig.
8. The resistance ROM is called offset minimizing resistor or compensating resistor. The offset
minimizing resistor is equal to the parallel combination of R1 and RF.
R 1R F
So, ROM = R1 || R F = (10)
R1 + R F

RF RF
R1 R1
–
Vi –
Vo Vo
+ +

ROM ROM

Vi

(a) Inverting configuration (b) Non-inverting configuration

Fig. 8 Bias current compensation or offset minimization
The output offset voltage with compensating resistance is given by,

 R 
VooT = 1 + F  Vio + (IB1- IB2)RF (11)
 R1 

 RF 
⇒ VooT = 1 +  Vio + IioRF (12)
 R1 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [7]

Where, Iio = IB1- IB2 = input offset current.

The input bias current IB is much larger than the input offset current Iio. So, the output offset
voltage for the circuit with compensating resistance given by equation (12) is smaller than the
voltage given by the equation (9) without compensating resistance. It also observed from
equation (11) that output offset voltage ( VoIB ) of the circuit with compensating resistance,ROM ,
due to input bias current (or input offset current) is eliminated completely if input offset current
is Iio is zero or IB1= IB2.
Note : Total output offset voltage of an op-amp is always equal to its saturation voltage of op-amp
VooT = + Vsat
Example 2
The opamp used in the inverting amplifier shown in figure has an equivalent input offset voltage Vios
of 5 mV. The output offset voltage is

560k
10k
–
Vi +
Vios
+ Vo

10k

(a) 5 mV (b) 280 mV

(c) 285 mV (d) 560 mV
GATE(IN/2003/2M)
Solution : Ans.(c)
560 k

RF
10 k
Vin –
+
R1 V Vo
ios
– +

10 k

Given, Vios = 5 mV
The output offset voltage of inverting configuration shown above is given by,
 R 
Vo o = 1 + F  Vios
 R1 

 560 
⇒ Vo o = 1 +  × 5mV = 285 mV
 10 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [8]
Example 3
In figure input offset voltage of the operational amplifier is 2 mV. The output dc-error voltage is
10 R

C R
V1
–
V
+
V2 C R
10 R

(a) 0 (b) 2 mV
(c) 11 mV (d) 22 mV
GATE(IN/2001/1M)
Solution : Ans.(d)
RF = 10 R
C R1 = R
V1
+ –
Vios V
– +
V2
C R
10 R

The output off set voltage of circuit shown above in terms of input offset voltage can be given by,
 R 
Vo o = 1 + F  Vio
 R1 

Given, RF = 10 R, R1 = R and Vio = 2 mV

 10R 
⇒ Vo o = 1 +  × 2 mV
 R1 

⇒ Voo = 22 mV

Example 4
In op-amp based inverting amplifier with a gain of 100 and feedback resistance of 47kΩ, the op-amp
input offset voltage is 6 mV and input bias current is 500 nA. The output offset voltage due to an
input offset voltage and an input bias current, are
(a) 300 mV and 23.5 mV (b) 606 mV and 47.0 mV
(c) 300 mV and 47.0 mV (d) 606 mV and 23.5 mV
IES(E&T,2018)
Solution : Ans.(d)
The magnitude of gain of inverting amplifier is given by,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [9]

RF
A =
R1
47k
⇒ 100 =
R1

⇒ R1 = 470 W
Output offset voltage in terms of input offset voltage,
 R   47k 
Voo = 1 + F  Vio = 1 +  ×6 mV = 606 mV
 R1   470 

The offset voltage in terms of input bias current,

VoIB = IBRF= 500 nA × 47 k = 23.5 mV

Example 5
Let V1 =V2 =0 and R1=20 kΩ. Assume that the Op-amp is ideal except for a non-zero input bias
current. What is the value of R2 for the output voltage of the Op-amp to be zero ?
(a) 2.2 kΩ (b) 9.1 kΩ
(c) 20 kΩ (d) 100 kΩ
GATE(IN/2007/2M)
Solution : Ans.(b)
With V1 = V2 = 0 & R1 = 20 k the given circuit becomes
RF

20 k 100 k

–
20 k Vout
}

Req +

R2

The equivalent resistance at inverting terminal with V1 = V2 = 0,

20 × 20
Req = = 10 k
20 + 20

When both inputs are zero the voltage at output is output offset voltage. Output offset voltage due to
input bias currents reduces to zero.
when, R2 = RF | | Req
R F × R eq 100 × 10 1000
⇒ R 2 = = k= k = 9.1 kW
R F + R eq 100 + 10 110

3.6 Power Supply Rejection Ratio (PSRR)

Power supply rejection ratio is the change in input offset voltage per unit change in one of the supply

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [10]
voltages with another held constant.
Note : Ideally, PSRR = 0

3.7 Common Mode Rejection Ratio (CMRR)

Common mode rejection ratio is the ratio of differential mode gain to the common mode gain of
operational amplifier.
| Ad |
CMRR = | A | (13)
cm

where, Ad are differential mode gain and Ac are common mode gain.
| Ad |
In decibels (dB), CMRR dB = 20 log10 (14)
| A cm |

Consider an op-amp having open loop gain A1 is w.r.t. non-inverting terminal. and gain A2 w.r.t
inverting terminal. Let V1 is voltage applied at non-inverting terminal and V2 is voltage applied at
inverting terminal as shown in Fig. 9.
V1
+
VO
–
V2
Fig. 9 Output voltage of op-amp in terms of V1 and V2
Then, output voltage of op-amp will be,

Vo = A1V1 + A2V2 (15)

The input voltage for differential mode is given by,
V=
in V=
d V1 - V2 (16)

Input voltage for common mode is given by,

V1 + V2
V
=in V=
cm (17)
2

From equation (16) and (17), we have,

2 Vcm + Vd
V1 = (18)
2

2 Vcm - Vd
V2 = (19)
2

Putting expression of V1 and V2 in equation (15), we have,

 2 V + Vd   2 Vcm - Vd 
Vo = A1  cm  + A 2  
 2 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [11]

[A1 - A 2 ]
⇒ Vo =+
[A1 A 2 ] Vcm + Vd (20)
2

⇒ =Vo A cm Vcm + A d Vd (21)

where, Acm = A1 + A2 = Common mode gain (22)

A1 - A 2
⇒ Ad = = Differential mode gain (23)
2

From equations (13), (22) and (23), we have,

| A d | 1 A1 - A 2
⇒ CMRR
= = (24)
| A cm | 2 A1 + A 2

Output voltage of op-amp in terms of CMRR,

Vo = Vd Ad + Vcm Acm
 A V 
⇒ Vo = Vd A d 1 + cm . cm  (25)
 A d Vd 

 1 V 
⇒ Vo Vd A d 1 +
= . cm  (26)
 CMRR Vd 
Note : Ideally, Acm= 0 and CMRR = ∞

So, ideally, Vo = Vd A d (27)

Example 6
An Op-amplifier has differential gain of 1 × 103 and CMRR is 100. The output voltage of op-amp
with inputs of 120 mV and 80 mV will be
Solution :
Output voltage of op-amp,
 1 V 
Vo = Vd A d 1 + . cm 
 CMRR Vd 
Differential input, Vd = V1 – V2
Given, V1 = 120 mV, V2 = 80 mV
Vd = 120 – 80 = 40 mV
120 + 80
Common mode input, Vcm = = 100 mV
2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [12]

 1 100 
⇒ Vo = 1000 × 40 1 + × mV = 41V
 100 40 
Example 7
If V1 and V2 are the input voltage of an instrumentation amplifier and output voltage is,
Vo = 100 (V1 – V2) + 10–4 (V1 + V2)
then find out CMRR and gain of amplifier.
Solution :
Output voltage in terms of differential and common mode gains ,
 V + V2 
Vo = A d (V1 - V2 ) + A cm  1 
 2 

Given, Vo = 100 (V1 – V2) + 10–4 (V1 + V2)

Comparing above two equations, we have,
Thus, Ad = 100
Acm = 2 × 10–4
| Ad | 100
Now, CMRR|dB = 20 log10 = 20 log 10 = 113.9 dB
| A cm | 2 × 10-4

3.8 Slew Rate

It is the maximum rate of change of output voltage with respect to time, obtainable without any
distortion in output. Slew rate is normally specified in V/ms.
d Vo
Slew rate, SR = (28)
dt max

Slew rate determines the maximum frequency obtainable for distortion free output for desired output
voltage swing. Alternatively, slew rate determines maximum undistorted output voltage swing for a
given low frequency of the input signal.

Note : Ideally, Slew Rate = ∞

Slew Rate Equation :
Consider op-amp based amplifier as shown in Fig. 10. The amplifier shown in the figure can be any
configuration of operational amplifier. Let input signal to the amplifier is Vi = Vm sin ωt . The slew
rate can be used to determine the maximum frequency of the output signal as follows,

+ op-amp based +
Vi amplifier with Vo
_ gain ‘A’ _

Fig. 10 Slew rate for inverting amplifier

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [13]
Input signal, Vi =
Vm sin ωt (29)
Output of the amplifier is given by,
Vo = A Vi (30)

Putting the expression of input voltage from equation (29) in equation (30), we have,
⇒ Vo = A Vm sin ωt (31)

d Vo
⇒ = A Vm ω cos ωt (32)
dt

From equation (32), the maximum rate of change of output voltage is given by,
d Vo
= A Vm ω (33)
dt max

For a distortion free output of the amplifier, the slew rate should be greater maximum value of rate
of change of output signal of the amplifier.
The slew rate in terms of output is define by,
d Vo
SR ≥ (34)
dt max

⇒ SR ≥ A Vm ω (35)

(SR)
⇒ f ≤ (36)
2πA Vm
For given amplitude of input voltage the maximum frequency of the input voltage for distortion free
output signal is,
(SR)
⇒ f max = (37)
2πA Vm

Equation (36) also gives maximum amplitude of input voltage for given frequency to get distortion
free output as under,
(SR)
Vm,max = (38)
2πfA

Note : Characteristics of ideal Op-amplifier

i) Infinite input impedance
ii) Zero output impedance
iii) Infinite open loop gain
iv) Infinite slew rate
v) Infinite band width
vi) Band width and gain production is high

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [14]
Example 8
An amplifier using an op-amp with a slew rate of 1 V per µ sec has a gain of 40 dB only. If this
amplifier can amplify signals up to 20 kHz without introducing any distortion then find out the
amplitude of input signal which should not be exceeded to avoid the distortion.
Solution :
Output of amplifier, Vo = A Vin = A . Vm sin ωt.
Gain of amplifier, AdB = 20 log A = 40 dB
A = 102 = 100
Rate of change of output ,
d Vo
⇒ = A Vmw cos ωt
dt

SR
For distortion free output, f ≤
A Vm 2π

1 × 106
⇒ f ≤
100 × Vm × 2π

1 × 106
⇒ Vm ≤
100 × 20 × 103 × 2π

⇒ Vm ≤ 79.57 mV
So, maximum value of amplitude of input signal for distortion free output is 79.57 mV.
Example 9
The op-amp having a slew rate of 62.8 V/µsec is connected in a voltage follower configuration. If the
maximum amplitude of input signal is 10V then find out the minimum frequency at which the slew
rate limited distortion would set in at the output.
Solution :
Maximum frequency of input signal for distortion free output,
SR
fmax =
2π AVm

Gain of voltage follower A = 1

62.8 × 106
⇒ fmax = = 1MHz
2π × 10

The maximum frequency for distortion free output is minimum frequency at which the slew rate
limited distortion would set in at the output.
Example 10
An opamp that is powered from a ± 5V supply is used to build a non-inverting amplifier having a gain

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [15]
of 15. The slew rate of the op-amp is 0.5 × 106 V/s. For a sinusoidal input with amplitude of 0.3 V,
the maximum frequency (in kHz) up to which it can be operated without any distortion is (up to one
decimal place) _________.
GATE(IN/2018/2M)
Solution : Ans. (17.5 to 17.9 )
Output non-inverting amplifier,
Vo = AVin
The slew rate of a op-amp is defined as,
dVo dVin
=A
dt max
dt

For sinusoidal input, Vin = Vp sin ωt

To avoid slew-rate induced distortion maximum rate of change of output voltage should be less than
or equal to the slew rate.
dVp sin ωt
A ≤ SR
dt max

2πf |A|Vp ≤ SR
Given, A = 15 , Vp = 0.3 V, S
R = 0.5 × 106 V/s
⇒ 2π × f × 15 × 0.3 ≤ 0.5 ×106
0.5 × 106
⇒ f ≤
15 × 0.3 × 2π

⇒ f ≤ 17.68 kHz
Thus maximum frequency with no distortion in output is 16.68 kHz.
3.9 Ideal Voltage Transfer Characteristics of Op-amp
The output voltage of an op-amp varies linearly with input difference voltage until it reaches at a
saturation value. The magnitude of positive value of saturation voltage is always less than or equal
to +VCC and magnitude of negative value of saturation voltage in magnitude is always less than VEE.
Fig. 11 shows the ideal voltage transfer characteristics of an op-amp with zero offset voltage.
Vo

+Vsat

Vd
– Vsat

Fig. 11 Ideal voltage transfer characteristics of op-amp

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [16]

4 Frequency Response of Op-amp

The gain of an operational amplifier can vary with frequency due to capacitances between stages
of operational amplifier and internal capacitances of BJT/FET used in internal stages of op-amp.
The variation of gain of operational amplifier with respect to frequency of input signal is called
frequency response of the amplifier. The open loop gain of an op-amp with single pole as a function
of frequency is given by,
A OL
AOL(f) = 2
(39)
f 
1+  
 fo 
where, AOL is 0 Hz or DC open loop gain and fo is called break or corner frequency of op-amp.
The frequency response of amplifier comprises of two plots called magnitude versus frequency plot
and phase versus frequency plot. The frequency in magnitude plot as well as phase plot is taken in
logarithmic scale in order to cover wide range of frequency. The magnitude in magnitude plot is also
taken in decibels (dB) to cover higher values of gain on linear scale. Fig. 12 shows the frequency
response of an operational amplifier.
Gain
Gain
(in dB)

A AdB
Roll off rate 3 dB Roll off rate
0.707A (A3)dB

BW BW
1
UGB UGB
0
fo f1 f fo f1 f

(a) Gain not in dB (b) Gain in dB

Fig. 12 Frequency response of operational amplifier
Cut-off frequency
The cutoff frequency of an operational amplifier is frequency at which gain (in dB) of the amplifier
falls by 3 dB or gain becomes 1/ 2 or 0.707 times its constant value. An operational amplifier has
direct coupling among the internal stages, therefore, the op-amp can amplify signals of very low
frequencies including DC signals. So, an operational amplifier behaves like a low pass filter and has
only upper cut-off frequency which is same as bandwidth of the op-amp. Cut off frequency is also
known as 3 dB cut-off frequency or corner frequency. The magnitude of gain reduces at a rate called
roll off rate for frequencies more than the 3 dB cut-off frequency. Normally the roll of rate is -20 dB
per decade or -6 dB per octave.
Bandwidth
Bandwidth of an amplifier is defined as range of frequencies for which gain of the amplifier constant.
The gain bandwidth product of op-amp with single crossover frequency remains constant. The
frequency at which gain of op-amp is unity is called unity gain bandwidth (UGB).

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [17]
If fo is 3 dB cut-off frequency and AOL is open loop DC gain then the unity gain bandwidth of the op-
amp can be given by,
UGB = f1 = foAOL (40)
where, f1 is corner frequency at which gain is unity or gain in dB is zero.
The unity gain bandwidth for closed loop negative feedback configurations with single corner
frequency is given by,
UGB = fFAF (41)
where, AF is closed loop DC voltage gain and fF is cut-off frequency or bandwidth with feedback.
From equations (39) and (40), we have,
foAOL = fFAF (42)
Compensation in Op-amp :
Compensation is used to improve frequency response and stability of operational amplifier.
a. Internal compensation
Internal compensation using phase lead or phase lag compensating networks using R & C components
can be used to improve frequency response of an op-amp. The internally compensated operational
amplifiers have very small open loop bandwidths. So, gain of amplifier falls off relatively at low
frequency. For 741 op-amp the first break frequency or open loop bandwidth is 5 Hz.
b. External compensation
An op-amp can have two types of external compensations,
i. Dominant pole compensation: Dominant pole compensation reduces the peak overshoot,
reduces the frequency of oscillation and compensate for phase shift introduced by feedback.
ii. Miller effect compensation: Miller compensation is provide by connecting a feedback capacitors
in intermediate stages.
Note : The transfer function of Op-amp is similar to a low pass filter so an op-amp behaves like a low pass
filter.
Example 11
A unity gain buffer amplifier has a bandwidth of 1 MHz. The output voltage of the amplifier for an
input of 2 V sinusoid of frequency 1 MHz will be
(a) 2 V (b) 2 2V
2 4
(c) V (d) V
2 2
GATE(IN/2002/2M)
Solution : Ans.(c)
A

1
1
2

1MHz f

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [18]

1
Gain of an amplifier becomes times of the midband gain at cut-off frequency.
2

Given, fc = BW = 1MHz
1
So, gain of given amplifier becomes when frequency applied is equal to cut-off frequency of 1
2
MHz.
1
⇒ Vo = V
2 i

1 2
⇒ Vo = ×2 = V
2 2
Example 12
An Op-amp has an open-loop gain of 105 and an open-loop upper cutoff frequency of 10 Hz. If
this Op-amp is connected as an amplifier with a closed-loop gain of 100, then the new upper cutoff
frequency is
(a) 10 Hz (b) 100 Hz
(c) 10 kHz (d) 100 kHz.
GATE(EE/2001/1 M)
Solution : Ans.(c)
Gain bandwidth product of op-amp remains constant.
∴ fOLAOL = fCLACL
f OL A OL 10 × 105
⇒ fCL = = = 10 kHz
A CL 100

5 Open Loop Configurations of Op-amp

There is no connection between output and input terminals of op-amp in open loop configuration.
There are three open loop configurations of an op-amp which as discussed as follows,

1. Differential Configuration
Both inverting and non-inverting input terminals are connected to input supply in a differential
configuration as shown in Fig. 13.
R1
+
V1 ~ R2 Vo
–
~ V2

Fig. 13 Open loop differential configuration

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [19]
Differential configuration is used to amplify the difference of two input supply voltages therefore,
the differential configuration is used as differential amplifier. If V1 is input voltage at non-inverting
terminal and V2 is input voltage at inverting terminal then the output of differential amplifier is given
by,
Vo = AOL (V1 - V2) (43)
Here, AOL is open loop gain of op-amp and the resistances R1 and R2 shown in Fig. 13 are the source
resistances.
2. Non-inverting Configuration
The non-inverting terminal is connected to input supply voltage and inverting terminal is connected
to ground in a non-inverting configuration as shown in Fig. 14. Non-inverting configuration is used
as a non-inverting amplifier. If V1 is input voltage at non-inverting terminal then the output of non-
inverting amplifier is given by,
Vo = AOL V1 (44)

R1
+
V1 ~ Vo
–

Fig. 14 Open loop non-inverting amplifier

3. Inverting Configuration
The inverting terminal is connected to input supply voltage and non-inverting terminal is connected
to ground in a inverting configuration as shown in Fig. 15. Inverting configuration is used as a
inverting amplifier. If V2 is input voltage at inverting terminal then the output of inverting amplifier
is given by,

Vo = AOL V2 (45)

+
R2 Vo
–
~ V2

Fig. 15 Open loop inverting amplifier

Normally open loop gain of an op-amp is very high and input signals applied in all the open loop
configurations drive the op-amp to saturation and output of op-amp is saturated at positive or negative
saturation level. The open loop configurations are not used in linear applications because of this issue
of saturation of op-amp.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [20]

6 Closed Loop Negative Feedback Configurations of Op-Amp

If output of op-amp is fed back to input circuit through a network called feedback network then
configuration of op-amp is called closed loop or feedback configuration. Depending on types input
and output signals there can be four types of feedback configurations called,
i. Voltage - series feedback
ii. Voltage-shunt feedback
iii. Current - series feedback
iv. Current-shunt feedback
All the feedback configurations have been discussed in detail in chapter of feedback amplifiers.
The output signal of an operational amplifier is a voltage signal, therefore, most commonly used
configurations of op-amp are voltage-series feedback or voltage -shunt feedback configurations
which are discussed in the following sections.

6.1 Voltage - Series Feedback Configuration

Fig. 16 shows the voltage-series feedback configuration of operational amplifier. The voltage-series
feedback configuration is a non-inverting closed loop configuration of operational amplifier.

RF
R1
– –
– Vf + Vd AOL Vo
+ +

Vin
Fig. 16 Voltage-series feedback amplifier
The resistances R1 and RF constitute the feedback circuit. As the output signal of the op-amp is a
voltage signal so the type of sampling is shunt or voltage sampling. The voltage across resistance R1
is feedback voltage. The feedback voltage appears in series with the input voltage of the amplifier.
Applying KVL in input loop the differential input voltage can be given by,
Vd = Vin– Vf (46)
The feedback voltage can be given by,
R1
Vf = . Vo (47)
R1 + R F

The feedback factor of the amplifier can be given by,

Vf R1
b = = (48)
Vo R1 + R F

Voltage Gain :
Voltage gain of a feedback amplifier in terms of open loop gain is given by,
A OL
AF = (49)
1 + A OLb

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [21]
Putting expression b from equation (48) in above equation, we have,

A OL (R1 + R F ) A OL
AF = = (50)
R1
1+ A OL R1 + R F + A OL R1
R1 + R F

1
⇒ AF = (51)
1 R1
+
A OL R1 + R F
For an ideal op-amp, AOL = ∞

The gain of the amplifier with ideal op-amp can be obtained by putting, AOL = ∞, in equation (50),
as under,
R1 + R F
AF = (52)
R1

RF
⇒ AF = 1 + (53)
R1

The output voltage of the amplifier,

⇒ Vo = AFVin (54)
 R 
For ideal op-amp, Vo =  1 + F  Vin (55)
 R1 

(R1 + R F ) A OL
For non-ideal op-amp, Vo = Vin (56)
R1 + R F + A OL R1

Input Resistance:
The input resistance of a voltage -series feedback amplifier is given by,
Rif = Ri(1 + AOLβ) (57)
Putting expression of b from equation (48) in above equation, we have,

 R1 
⇒ Rif = R i  1 + A OL (58)
 R 1 + R F 
Output Resistance:
The output resistance a voltage-series feedback amplifier is given by,
Ro
Rof = (59)
1 + A OL b

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [22]
Putting expression of b from equation (48) in above equation, we have,
Ro
⇒ Rof = (60)
R1
1 + A OL
R1 + R F

Closed Loop Frequency Response :

The gain of closed loop non-inverting configuration as a function of frequency can by given
by,
AF
AF(f) = 2
(61)
f 
1+  
 fF 

Where AF is closed loop DC gain of amplifier and fF is cut-off frequency of closed loop
configuration.
The frequency response of voltage series feedback amplifier can be drawn by using equation (66a) as
is shown in Fig.17.

Gain
open loop
AOL
closed loop
AF

fo fF f
Fig. 17 Frequency response of voltage-series feedback amplifier
Cut-off frequency and Bandwidth :
The gain bandwidth product of an op-amp based amplifier ,with signal cutoff frequency, remains
constant and is equal to unity gain bandwidth. As op-amp based amplifier has only upper cutoff
frequency so the bandwidth of amplifier is same as upper cutoff frequency. The unity gain bandwidth
of amplifier with feedback can be given by,

UGB = AOLfo (61a)

Where AOL is open loop DC gain and fo is cutoff frequency of op-amp.

Alternatively, the unity gain bandwidth is same for closed loop configuration also, so,

UGB = AFfF (62)

Where, AF is closed loop DC gain and fF is cutoff frequency of closed loop configuration of op-
amp. From equations (61a) and (62), we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [23]
AFfF = AOLfo (63)
A OL f o
⇒ fF = (64)
AF

As gain bandwidth of op-amp remains constant so if gain of the amplifier reduces by factor (1 + AOL
β) due to negative feedback then the bandwidth of the amplifier increases by the same factor i.e. (1 +
AOL β). Thus, upper cutoff frequency of voltage series feedback amplifier can also be given by,
fF = (1 + AOL β)fo (65)
where fo is cut off frequency of op-amp with open loop.
Putting expression of b from equation (48) in above equation, we have,
 R1 
fF = 1 + A OL .  fo (66)
 R1 + R F 
Output Offset Voltage :
As the gain of op-amp with non-inverting negative feedback configuration reduces by a factor (1 +
AOL β) so the total output offset voltage of the amplifier also reduces by the same factor. Thus, the
total offset voltage non-inverting negative feedback amplifier can be given by,
± VooT
VooT,F = (67)
1 + A OLb
where, VooT is output offset voltage without feedback.
The output offset voltage op-amp without feedback is equal to positive or negative of saturation
voltage of op-amp. So, the output offset voltage of non-inverting negative feedback or voltage-series
configuration of op-amp can be given by,
± Vsat
VooT,F = (68)
1 + A OLb

Note : Voltage-series feedback configuration of op-amp is used as a non-inverting amplifier.

Example 13
The op-amp of the circuit shown in the figure has a unity gain frequency of 1 MHz. The cut-off
frequency of the feedback amplifier is
Vin + V0
–
10 k
90 k
10 k

(a) 100 kHz (b) 1 MHz
(c) 10 MHz (d) 90 MHz
IES(E&T,95)
Solution : Ans. (a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [24]
Vin +
Vo
–
RL = 10 k
R1 = 10 k RF = 90 k

Closed loop gain,
RF 9
AF = 1 + = 1 + = 10
R1 1

Given unity gain frequency, fo = 1 MHz

Unity gain band of Op-amp
For Op-Amp gain bandwidth remains constant
∴ AOLfo = AF × fF
at unity gain, AOL = 1, fo = UGF
UGF
fF =
AF

1 × 106
⇒ fF = = 100 kHz
10

Example 14
The Op-amp of figure has a very poor open loop voltage gain of 45 but is otherwise ideal. The gain
of the amplifier equals
8k
2k
–
Vo
Vi +

(a) 5 (b) 20
(c) 4 (d) 4.5
GATE(EC/1990/2M)
Solution : Ans.(d)
8k
2k
–
Vo
Vi +

Feedback factor of above cirucuit,

2
β = = 0.2
2+8

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [25]
Gain of amplifier with feedback,
A
AF =
1 + Ab

Given, A = 45
45
⇒ AF = = 4.5
1 + 45 × 0.2

Example 15
An Op-amp with an open-loop gain of 10,000, Rin = 2 k and Ro = 500 Ω is used in the non-inverting
configuration as shown in the figure. The output resistance Rof is

20 k
–
+
1 k RL = 1.0 k
Vs Rof

(a) 250.5Ω (b) 21Ω
(c) 2Ω (d) 0.998Ω
IES(EE,99)
Solution : And (d)
20 k
1 k RF
–
R1 +
+~ Ref RL= 1k
Vs
–

Feedback factor of non inventing amplifier given above,

R1 1 1
β = = =
R1 + R F 1 + 20 21

Given, Ro = 500Ω, Rin = 2kΩ, Open loop gain, AoL = 10000

Given amplifier has a voltage shunt feedback amplifier whose output resistance with feedback is
given by
R
Rof = o
1 + Ab

500
⇒ Rof = = 0.998 Ω
1
1 + 1000 ×
21

Example 16
An opamp has ideal characteristics except that its open loop gain is given by the expression

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [26]

104
A V (s) = . This op-amp is used in the circuit shown in the figure. The 3-dB bandwidth of
(1 + 10-3 s )
the circuit, in rad/s, is
+
+ Av Vo
–
Vi ~
–
9 k

1 k

(a) 102 (b) 103

(c) 104 (d) 106
GATE(IN/2015/2M)
Solution : Ans. (d)
+
+ Av Vo
–
Vi ~
–
9 k

1 k

Given, open loop gain of op-amp of circuit,
104 A
Av(s) = -3
=
(1 + 10 s)  s 
1 + 
 ωo 

Where, A = 104 = open DC gain of op-amp and wo = 103 rad/s = cutoff frequency of op-amp.
Feedback factor of the given amplifier,
1k
b = = 0.1
1k + 9k

The 3-dB bandwidth of the circuit, in rad/s, for closed loop configuration is given by,
wF = ( 1 + Ab)wo = ( 1 + 104 × 0.1) × 103 rad/s ≈ 106 rad/s
Example 17
An op-amp has a finite open loop voltage gain of 100. Its input offset voltage V (= +5mV) is ios

modeled as shown in the circuit below. The amplifier is ideal in all other respects. Vinput is 25 mV.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [27]
1 k 15k

–
A0=100
+
+
– Vios = 5mV

+
– Vinput

The output voltage (in millivolts) is ...........

GATE(EC-II/2016/2M)
Solution : Ans. (400:425)
1 k 15k

R1 RF
–
A0=100 Vo
+
+
– Vios = 5mV

+
– Vinput

Given open loop gain of op-amp, Ao = 100

R1 1 1
Feedback of the circuit, b = = =
R1 + R F 1 + 15 16

Ao 100 400
Closed loop gain , AF = = =
1 + A ob 1 29
1 + 100 ×
16
400
Output voltage, Vo = AF(Vinput + Vio) = (25 + 5) mV = 413.79 mV
29
Example 18
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier
(op-amp), and has an open-loop voltage gain, A0 = 105V/V and an open-loop cut-off frequency fc =
8Hz. The voltage gain of the amplifier at 15 kHz, in V/V is ________.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [28]
R2 = 79 k

R1 = 1 k
–
Vo
+
Vi
~
GATE(EC-I/2017/2M)
Solution : Ans. : 43.3 to 45.3
R2 = 79 k

R1 = 1 k
–
Vo
+
Vi
~

R1 1 1
Feedback factor, b = = =
R1 + R 2 1 + 79 80
Cutoff frequency with feedback,
 5 1 
fF = ( 1 + Aob) fc = ( 1 + 105 × 1 + 10 ×  × 8 = 10.008 kHz
 80 
5
Ao 10
DC gain with feedback, AF = = 5
= 79.9
1 + A ob 1 + 10 × (1/ 80)
The closed loop gain of op-amp based amplifier as a function of frequency is given by,
AF
AF(f) = 2
f 
1+  
 fF 

79.9
At f = 15 kHz, AF(f) = 2
= 44.34
 15 × 103 
1+  
 10008 

6.2 Voltage Follower

A voltage follower circuit is obtained by replacing resistance R1 by open circuit and resistance RF
by short circuit in voltage-series feedback non-inverting amplifier as shown in Fig. 19. The voltage
follower circuit is essentially a unity gain non-inverting amplifier because of which it is also known

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [29]
as Unity Follower circuit. Thus, output voltage of unity follower circuit is same as its input voltage
and hence its name is voltage follower. A voltage follower circuit is also called a voltage buffer.

+ Vo
–

Vin
Fig. 18 Voltage or unity follower circuit
Output voltage, Vo = Vin (69)
Facts About Voltage Follower
i) Gain of voltage follower is unity.
ii) Output signal is same as input signal.
iii) Input impedance is infinity and output impedance is zero.
iv) It can be used for marching of high impedance source to low impedance load.
v) It provides isolation between source and load.
Note : A current buffer is an amplifier with unity current gain. A good current buffer has low input impedance
and high output impedance current buffer is an electronic circuit that is used to transfer electric
current from input source having very less impedance (effective resistance) to output loads with high
impedance.
6.3 Voltage-Shunt Feedback Configuration
Fig. 19 shows the voltage-shunt feedback configuration of operational amplifier. The voltage-
shunt feedback configuration is an inverting closed loop configuration of operational amplifier. The
resistances R1 and RF constitute the feedback circuit. Normally, gain of voltage-shunt amplifier is a
transresistance gain and input as well as feedback signals are current signals. But, it is voltage gain
which is topic of significance here, so instead of transresistance gain, the voltage gain is discussed
for voltage-shunt configuration of op-amp based amplifier here. For voltage gain of voltage-shunt
feedback amplifier, the input as well as feedback signals are assumed to be voltage signals.

RF
Vin R1 If
– Vo
Iin
+

Fig. 19 Voltage-shunt feedback amplifier

The voltage feedback in the input circuit can be obtained by using the principle of superposition by

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [30]
considering the input voltage and output voltage one by one as follows,
The feedback voltage can be given by,
R1
Vf = . Vo (70)
R1 + R F

The feedback factor of the amplifier can be given by,

Vf R1
b = = (71)
Vo R1 + R F

The input voltage reaches at output terminal through feedback resistance as well as op-amp. The part
of input voltage reaching at output terminal through feedback resistance attenuates the output voltage
by a factor K called attenuation factor. The attenuation factor K is given by,
RF
K = (72)
R1 + R F
Then, the closed loop gain of voltage-shunt amplifier can be given by,
Vo - K A OL
AF = = (73)
Vin 1 + b A OL

Putting the expression of b and K from equations (71) and (72) in above equation, we have,
RF
. A OL
R1 + R F
AF = - R1
(74)
1+ . A OL
R1 + R F

For an ideal op-amp, AOL = ∞

RF
AF = - (75)
R1

Input Resistance :
Input resistance of voltage-shunt feedback configuration can be obtained by using the Miller‘s
Theorem. According to the Miller’s Theorem the resistance of feedback path can be transferred to
the input and output terminals as shown in Fig. 20.
RF

Vin R1 R1
Vin
– Vo – Vo
AOL Ri AOL
+ Rif RF Rof
+ Ro AOLRF
1AOL
AOL –1

(a) Voltage-shunt feedback (b) Miller’s equivalent

Fig. 20 Voltage shunt feedback and its Miller’s equivalent circuit.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [31]
The resistance seen from input terminal in Miller’s equivalent circuit is input resistance of the
voltage-shunt feedback amplifier. The resistance seen from input
terminals of Miller’s equivalent circuit,
 RF 
Rif = R1 +   || R i (76)
 1 - A OL 

For an ideal op-amp, AOL = ∞ , then input resistance for amplifier with ideal op-amp becomes,
Rif = R1 (77)
Note : Miller Theorem : According Miller’s theorem an impedance in feedback path can be transfered
to input and output terminals of the op-amp as shown below,

Z1 Z2

Av ⇒ Av

Fig. 21 Miller’s Theorem Equivalent

The impedances transferred to input and output terminals of amplifier,
Z Z
Z1 = and Z2 =
1 - Av 1
1-
Av

where Av is voltage gain of the amplifier.
Output Resistance :
The output resistance of voltage-shunt feedback configuration is obtained similar to that of voltage-
series feedback configuration. Thus, the output resistance a voltage-series feedback amplifier is
given by,
Ro
Rof = (78)
1 + A OL b

Frequency Response :
The frequency response of inverting configuration is similar to a non-inverting configuration. The
closed gain for inverting configuration is given by,
AF
AF(f) = 2
(79)
f 
1+  
 fF 

where AF is closed loop DC gain of amplifier and fF is closed loop cutoff frequency

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [32]
Cut-off Frequency and Bandwidth :
The gain bandwidth product of an op-amp based amplifier ,with signal cutoff frequency, remains
constant and is equal to unity gain bandwidth. As gain bandwidth of op-amp remains constant so if
gain of the amplifier reduces by factor (1 + AOL β) due to negative feedback then the bandwidth of the
amplifier increases by the same factor i.e. (1 + AOL β). Thus, upper cutoff frequency of voltage series
feedback amplifier can also be given by,
fF = (1 + AOL β)fo (79a)
As op-amp based amplifier has only upper cutoff frequency so the bandwidth of amplifier is same as
upper cutoff frequency. The unity gain bandwidth of amplifier with feedback can be given by,

UGB = AOLfo (80)

where AOL is open loop DC gain and fo is cutoff frequency of op-amp.
From equations (79) and (80), we have,
UGB
fF = (1 + A OLb) (81)
A OL

From equation (73) and (81), we have,

UGB
fF = ×K (81a)
AF

Output Offset Voltage :

As the gain of op-amp with inverting negative feedback configuration is reduced by a factor (1 + AOL
β) so the total output offset voltage of the amplifier also reduces by the same factor. Thus, the total
offset voltage inverting negative feedback amplifier can be given by,
± VooT
VooT,F = (82)
1 + A OLb
where, VooT is output offset voltage without feedback.
The output offset voltage op-amp without feedback is equal to positive or negative of saturation
voltage of op-amp. So, the output offset voltage of inverting negative feedback or voltage-shunt
configuration of op-amp can be given by,
± Vsat
VooT,F = (83)
1 + A OLb

Note : Voltage-shunt feedback configuration of op-amp is used as a inverting amplifier.

6.4 Concept of Virtual Ground

Consider the operational amplifier of shown in Fig. 22, which forms a part of an amplifier with
negative feedback. Although the op-amp shown in Fig. 22 is having open loop but it is assumed that
it forms a part of a closed loop network consisting of negative feedback.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [33]
V1
+ – Vo
Vd =V1–V2 AOL
_ +
V2

Fig. 22 Ideal op-amp with same potential at inverting and non-inverting amplifier
For op-amp, Vo = AOL Vd (84)
⇒ Vd = Vo/AOL (85)
For an ideal op-amp, AOL = ∞
⇒ Vd = Vo/ ∞ = 0 (86)
⇒ V1 –V2 = 0 (87)
⇒ V1 = V2 (88)
In the amplifier circuits consisting of ideal op-amps with negative feedback, the potential at inverting
as well as non-inverting terminals is same.
If non-inverting terminal is grounded then,
V1 = V2 = 0 (89)
When non-inverting terminal of an inverting amplifier with negative feedback is physically connected
to ground, the inverting terminal is also at ground potential due to infinite gain of the op-amp. Such
condition when inverting terminal is not connected physically to ground but it is at ground potential,
is known as virtual ground at inverting terminal.
Note : In case of open loop ideal op-amp a small differential input voltage or voltage at one of the input
terminals drives the op-amp to saturation. So, the concept of virtual ground does not apply to op-amp
with open loop.

Example 19
V0
The inverting Op-amp shown in figure has an open-loop gain of 100. The closed loop gain is
Vs

R2 = 10 K
R1 = 1 K
Vs –
Vi +
– + V0

(a) –8 (b) –9
(c) –10 (d) –11
GATE(EC/2001/2M)
Solution : Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [34]
R2 = 10 K
R1 = 1 K
Vs –
Vi +
– + V0

1 1
β = =
1 + 10 11
Closed loop gain of above circuit is given by
- A OL k
AF = ;
1 + A OLb

R2 10 10
k = = =
R1 + R 2 1 + 10 11

Given, open loop gain of op-amp. AOL = 100

10
100 ×
∴ AF = – 11 = -100 × 10 ≈ -9
1 111
1 + 100 ×
11

7 General Linear Applications of Op-Amp

An operational amplifier is used as linear amplifier in general linear applications. The output of op-
amp is linear function of input signal in linear applications. There a numerous linear applications of
op-amp some of which are discussed in the following sections.
Steps of solving op-amplifier circuit for linear applications:
1. Step-I: Find the voltage at non inverting terminal.
2. Step-II: Applying KCL at node of inverting terminal to find the relation between input and
output signals.
7.1 Inverting Amplifier
An operational amplifier connected in inverting configuration can be used as an inverting amplifier.
Fig. 23 shows the circuit diagram of an inverting amplifier.
RF
Vin Iin R1
a
– Vo
Rin
+

Fig. 23 Inverting amplifier
Applying KCL at node a, we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [35]

Va - Vin Va - Vo
+ = 0 (90)
R1 RF

As non-inverting terminal is grounded so the inverting terminal is at virtual ground.

∴ Va = 0

Putting above value of Va in equation (90), we have,

- RF
⇒ Vo = Vin (91)
R1

Vo - R F
Gain of amplifier, AF = = (92)
Vin R1

Input Resistance of Inverting Amplifier :

The input resistance of inverting configuration is the resistance seen by the input source.
Mathematically, it can be obtained as under,
The input current of the amplifier can be given by,
V - Va Vin - 0 Vin
Iin = in= = (93)
R1 R1 R1

Vin
Input resistance, Rin = = R1 (94)
Iin

Applications of Inverting Amplifier :
i. Inverting Amplifier as Negative Scale Changer :
The inverting amplifier can also be used as a negative scale changer. The output voltage of inverting
amplifier given by equation (91) can be written as ,

⇒ Vo = - KVin (95)
RF
where, K = = scale factor (96)
R1
It is observed from equation (95), the inverting amplifier changes the scale of input signal by
factor K. Since, output voltage is negative so the amplifier is a negative scale changer.
Note : The gain of inverting amplifier is negative so it can be used as sign changer or phase changer or
analog inverter.

ii. Inverting Amplifier as a Phase Shifter :

Fig. 24 shows the circuit diagram of an inverting amplifier as phase shifter.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [36]
ZF

Vin Z1
–
a
Vo
+

Fig. 24 Inverting amplifier as a phase shifter

Let ZF = ZF ∠θF and Z1 = Z1 ∠θ1 . The the output voltage of the amplifier is given by,

ZF ∠θF
Vo = - . Vin (97)
Z1 ∠θ1

The magnitude of output voltage,

ZF
|Vo| = . | Vin | (98)
Z1

The phase angle of output voltage,

∠ Vo = 180o + qF - q1 + ∠ Vin (99)
It is observed from equation (99) that the phase of output of inverting amplifier is not same as phase
of input of the amplifier. The level of phase shift can be decided by selecting suitable value of ZF

and Z1 .

Example 20
The wiper of the 20 kΩ potentiometer in figure is positioned half way. Then the voltage Vo of the
circuit is
15k

20k
2V +
–
–
10k + Vo

(a) – 1.7 V (b) – 1.0 V

(c) – 0.75 V (d) + 2.5 V
GATE(IN/2004/2M)
Solution : Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [37]
15k

a 10k
2V +
–
–
+ Vo
+
VTH
–
b

When potentiometer is position half way the Thevenin’s equivalent seen across terminal ab can be
given by
10
VTH = ×2 =
1V
10 + 10

RTH = 10 × 10 = 5 kΩ
10 + 10

The circuit can be redrawn as under,

15k

RFH =5k a 10k

–
Vo
+
VTH = 1V

The output voltage of circuit can be given by,

15 15
Vo = - × VTH =
- × 1V =
-1V
10 + 5 15

Example 21
The input resistance of the op-amp circuit shown in figure is
100 k

1 k
–
V1 V0
+

(a) 100 kΩ (b) 99 kΩ

(c) 1 kΩ (d) 101 kΩ
GATE(IN/1994/1M)
Solution : Ans.(c)
Iin 100k
Vin –
1k Vo
+

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [38]
For ideal opam, V– = V+
∴ V– = 0
∴ Current supplied by source,
Vin - V- Vin - 0 Vin
Iin = 3
= 3 =
1 × 10 1 × 10 1 × 103
Vin
Input resistance, R in= = 1kΩ
Iin

Example 22
The transfer gain for the circuit shown in the figure is given by
R2 R3

R4
R1
Vi –
Vo
+

 R 3R 3   R 3R 4 
 R2 + R3 + R   R + R + R2 
(a) –  4
 (b) –  3 4

 R 1   R 1 
   

 R 2R 4 
 R + R + R3   R + R3 
(c) –  
2 4
(d) –  2 
 R1   R1 
 

IES(EE,97)
Solution : Ans (a)
R2 R3 c
a R4
b
R1
Vi –
Vo
+

Converting star connection abc of feedback path to delta connection we have,

R 2R3
Rac = R2 + R3 +
R4

R 2R 4
Rab = R2 + R4 +
R3

R 4R3
Rbc = R4 + R3 +
R2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [39]

Rac
a c

Rab
Rbc
b

–
Vi R1
+ Vo

Shifting resistances Rab * Rbc on input & output side we have
Rac

10k
Vi – c
a Vo
R1 Rab
+
Rbc
10k

Rab can be removed as terminal ‘a’ is a vertical ground

R ac
So, Vo = – Vi
R1

 R 2R3 
Vo  R2 + R3 + R 
Gain of amplifier, A = = – 4

Vi  R 1 
 

Example 23
The input resistance of the circuit shown in the figure, assuming an ideal op-amp, is
2R

R 3R

Vi
–

+ Vo

(a) R/3 (b) 2R/3

(c) R (d) 4R/3
GATE(IN/2009/1M)
Solution : Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [40]
2R
Iin
‘a’
Vin ‘b’ R R
–
Vout
+

For ideal opamp,

V– = V+
∴ Va = V– = 0V
KCL at node ‘a’,
0 V 0 Vout
= 0
R 3R

⇒ Vout = – 3Vin ...(i)

KCL at node ‘b’,
Vin - Vout Vin - 0
–Iin + + = 0 ...(ii)
2R R

From equation (i) & (ii),we have,

4Vin Vin
–Iin + + = R
2R R

3Vin
⇒ = Iin
R
Vin R
∴ Input resistance, R=
in =
Iin 3

Example 24
What is the output voltage Vo of the circuit given below ?
100 k
470 k
10 k 22 k
_ 47 k
_ 2.2 k
+ _
+ Vo
+
1 mV

(a) –1.1 V (b) + 1.1 V
(c) 1.0 V (d) 10 V
IES(E&T,07)
Solution : Ans. (b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [41]
100 k
470 k
10 k 22 k
–
1 – 2.2 k
+ V01 47 k 2 –
+
1mV
–
~ + V02
+
3 Vo

Output voltage of Op-amp (1),
 100 
V01 = 1 + 1mV = 11 mV
 10 

Output of Op-amp (2),

470
V02 = - V01 = – 10 × 11 mV
47

Output of Op-amp (3),

22
Vo = - × V02 = –10 × (–10 × 11) mV = 1.1 V
2.2

Example 25
vin
The op-amp shown in the figure is ideal. The input impedance is given by
iin

Z
iin
+
vo
vin + –
–

R2 R1

R1 R2
(a) Z (b) -Z
R2 R1

R1
(c) Z (d) -Z
R1 + R 2

GATE(EE/2018/1M)
Solution : Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [42]

Z
iin
a +
vo
vin + b –
–

R2 R1

Voltage at node ‘a’, va = vin

R2
The voltage at node ‘b’, vb = × vo (i)
R1 + R 2

For an ideal op-amp, vb = va

∴ vb = vin (ii)

From equations (i) and (ii), we have,

R2
vin = × vo
R1 + R 2

R1 + R 2
⇒ vo = × vin
R1

For ideal op-amp biasing current is zero. So, the current through impedance Z is iin only. The curring
through Z can also be given by,
vin - v o v 1 R + R2
iin = = in - × 1 × vin
Z Z Z R2

 1 1 R + R2  R
iin =  - × 1  vin =- 1 vin
Z Z R2  ZR 2

vin ZR1
Input impedance, Rin = =-
iin R2

7.2 Non-inverting Amplifier

An operational amplifier connected in non-inverting configuration can be used as an non-inverting
amplifier. Fig. 25 shows the circuit diagram of a non-inverting amplifier.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [43]
RF
R1
–
a
Vo
+

Vin
Fig. 25 Inverting amplifier
Applying KCL at node ‘a’, we have,
Va - 0 Va - Vo
+ = 0 (100)
R1 RF

For an ideal op-amp with negative feedback the voltage at inverting terminal is same as voltage at
non-inverting terminal.
∴ Va = Vin (101)
Putting above expression of Va in equation (100), we have,
Vin Vin - Vo
+ = 0 (102)
R1 RF

 R 
⇒ Vo = 1 + F  Vin (103)
 R1 

Vo R
Gain AF = =1 + F (104)
Vin R1

Applications of Non-inverting Amplifier :

i. Non-Inverting Amplifier as Positive Scale Changer
The non-inverting amplifier can also be used as a positive scale changer. The output voltage of non-
inverting amplifier given by equation (103) can be written as ,
Vo = KVin (104a)
 R 
where, K = 1 + F  = scale factor (104b)
 R1 

Example 26
A non-inverting Op-Amp summer is shown in the figure. The output voltage V0is

R 2R
–
R
Sin 100 t + V0

R

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [44]

3
(a) sin 100 t (b) sin100 t
2
(c) 2 sin 100 t (d) 3 sin 100 t
IES(EE,97)
Solution : Ans (b)
R 2R

a –
R b
Sin 100 t + V0

Applying KCL at node ‘b’,

V - sin100t Vb - 0
b + = 0
R R

1
⇒ Vb = sin100t
2

For ideal Op-amp, Va = Vb

1
∴ Va = sin100t
2

Applying KCL at node ‘a’,

V1 - 0 Va - Vo
+ = 0
R 2R

1 1 V
⇒ sin100t + sin100t - o = 0
2R 4R 2R

3
⇒ Vo = sin100t
2

Example 27
Vout
The circuit diagram of an Op-amp based amplifier is shown in the given figure. The ratio is
Vin
75 k
equal to –
75 k
15 k = R1
+ +

Vout
Vin
–

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [45]
(a) 9 (b) 11
(c) 10 (d) 21
IES(E&T,96)
Solution : Ans. (b)
75 k
75 k
–
15 k = R1
+ +

Vout
Vin
–

The circuit shown above is non-inverting configuration of Op-amp with gain,

RF
AF = 1 +
R1

where, RF = 75 + 75 = 150 k and R1 = 15 k

150
∴ AF = 1 + = 11
15

7.3 Difference Amplifier

An operational amplifier can be used for implementation of difference amplifier. Fig. 26 shows the
circuit diagram of a difference amplifier using an operational amplifier.
RF

R1
V1 –
a
R2 VO
b
V2 +

R3

Fig. 26 Differential amplifier using op-amp

R3
Voltage at node ‘b’, Vb = . V2 (105)
R2 + R3

Applying KCL at node ‘a’, we have,

Va - V1 Va - Vo
+ = 0 (106)
R1 RF

For ideal op-amp, Va = Vb

Vb - V1 Vb - Vo
∴ + = 0
R1 RF

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [46]

Vo  1 1  V
=  +  Vb - 1
RF  R F R1  R1
RF  R 
⇒ Vo = - . V1 + 1 + F  Vb (107)
R1  R1 

RF  R  R3
⇒ Vo = - V1 + 1 + F  . V2 (108)
R1  R1  R 2 + R 3

Taking R3= RF and R2 = R1, we have,

RF  R  RF
Vo = - .V1 + 1 + F  . V2 (109)
R1  R1  R1 + R F

RF R
⇒ Vo = - .V1 + F . V2 (110)
R1 R1

RF
⇒ Vo = [V2 - V1 ] = A dV d (111)
R1

RF
Where, Vd = Differential input voltage and Ad = = Differential gain of amplifier.
R1

Modes of operation of Difference Amplifier:

I. Common Code
The input voltages for common mode are,
V1 = V2 = V (112)
Putting above values in equation (111), the output of amplifier becomes,
RF
Vo = [V – V] = 0 (113)
R1

II. Single Ended Mode

Input voltages for single ended mode are,
V1 = 0 or V2 = 0
III. Differential Mode
The input voltages for differential mode are given by,
V1 = –V, V2 = V (114)
Putting above values in equation (111), the output of amplifier becomes,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [47]

RF R
Vo = [V - (- V)] = F (2 V) (115)
R1 R1

Application of Difference Amplifier as Subtracter :

RF= R
R1 = R
V1 –
R2= R
V2 + Vo

R3= R

Fig. 27 Difference amplifier as subtracter

A difference amplifier can be used to perform function of a subtracter by selecting,
RF = R1 = R2 = R3 = R (116)
By putting above values of resistances in equation (108), the output voltage becomes,
Vo = V2 - V1 (117)
The the circuit works like a subtracter.
Example 28
If the Op-amp in figure is ideal, the output voltage Vout will be equal to
5 k

1 k
2V –

3V + Vo
1 k
8 k

(a) 1 V (b) 6 V
(c) 14 V (d) 17 V
GATE(EC/2003/2M)
Solution : Ans.(b)
5 k

1 k
2V –
a
b
3V + Vo
1 k
8 k

Voltage at node ‘b’,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [48]

8 8
Vb = × 3V = V
8 +1 3

KCL at node ‘a’,

Va - 2 Va - Vo
+ = 0
1 5

8
For ideal op-amp, Va = Vb = V
3
 5 5
⇒ Vo = 1 +  Va - × 2
 1 1
8
⇒ Vo = 6 × - 10V = 6 V
3

Example 29
The differential input resistance of the circuit shown in figure is
RF

R1
V1 –
R1 Vout
V2 +

RF

(a) R1 (b) R1/2

(c) 2R1 (d) RF
GATE(IN/1996/1M)
Solution : Ans.(c)
RF

R1
I V1
– –
Vd + ‘a’
– Vo
+ ‘b’ +
I V2 R1
RF

RF
Voltage at node ‘b’, Vb = ·V2
R1 + R F

For ideal Op-amp, V– = V+

RF
∴ Va = Vb = ·V2
R1 + R F

Current supplied by source,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [49]
RF
·V2 - V1
Va - V1 R1 + R F

I = =
R1 R1

For differential input, V1 = –Vd/2 and V2 =+Vd/2

1 RF 1 
 2 + R + R · 2  Vd
 1 F 
I =
R1

Vd 2R (R + R F )
⇒ = 1 1  2R1
I R1 + 2R F

Vd
Differential input resistance, Rd = ≈ 2R1
I
Example 30
In the circuit shown in figure, the op-amps used are ideal. The output Vo is
10k
Vi=1V 10k +
–
+ – Vo
+
Vi=2V 10k
1k
10k 2k

(a) 3.0 V (b) 1.5 V

(c) 1.0 V (d) 0.5 V
GATE(IN/2003/2M)
Solution : Ans.(b)
10k

10k

V1 = 1V –
1
+ Vo
+ V01
2
V2 = 2V 10k –
10k

1k
2k

Voltage at output of Op-amp 1,

 10  1 10
V01 = 1 +  × × V2 - × V1 = V2 – V1 = 2 – 1 = 1V
 10  2 10

Voltage at output of Op-amp 2,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [50]

 1 3
Vo = 1 +  × V01 = × 1 =1.5V
 2 2

Example 31
The output of the op-amp in the circuit of figure is

10k
+3V 10k
–

+ Vo
10k
10k

(a) 0V (b) –3 V
(c) + 1.5 V (d) + 3V
GATE(IN/2004/1M)
Solution : Ans.(a)
10k
10k
Vi = 3V a –
Vo
b
+
10k
10k

KCL at node ‘b’ gives,

10
Vb = ×3 =
1.5V
10 + 10

For ideal Op-amp, V+ = V–

∴ Va = Vb = 1.5 V
KCL at node ‘a’gives,
1.5 – 3 1.5 - Vo
+ = 0
10 10

⇒ Vo = 0

Example 32
The figure shows a single op-amp differential amplifier circuit.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [51]
100k

500 10k
–
Vo
10mV + 50 10k
– +

+ 20mV
– 100k

Which one of the following statements about the output is correct ?

(a) Vo ≤ 95 mV (b) 95 mV< Vo ≤ 98 mV
(c) 98 mV < Vo ≤ 101 mV (d) Vo > 101 V
GATE(IN/2007/2M)
Solution : Ans.(b)
100k

500 10k

‘a’ –
Vout
10mV + 50 10k
– ‘b’ +

+ 20mV
– 100k

Applying KCL at node ‘b’,

100 × 103
Vb = × 20mV = 18.17 mV
100 × 103 + 50 + 10 × 103

For ideal opamp, V– = V+

∴ Va = Vb = 18.17 mV
Applying KCL at node ‘a’,
Va - 10 Va - Vo
+ = 0
10.50 100

 100  100  100  100

⇒ Vo = 1 +  Va - × 10 = 1 +  × 18.17 - × 10
 10.5  10.5  10.5  10.5

⇒ Vo = 95.975 mV
So, 95 mV < Vo < 98 mV is correct answer.

Example 33
For the op-amp circuit shown below, v0 is approximately equal to

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [52]
10V

95  1M
105 
100 k

Vo

100 k
95  1M
105 

(a) −10 V (b) − 5 V

(c) + 5 V (d) + 10 V
GATE(IN/2008/2M)
Solution : Ans.(b)
10V

95 1M
105
100k a
V1 
V2 b
 Vo
100k
95 105 1M

From input circuit,

105 105
V1 = × 10 V =V .....(i)
200 20

95 95
& V2 = × 10V = V
200 20

Voltage at node ‘b’,

1 1 95
Vb = × V2 = × × 10V
1.1 1.1 200

For ideal opamp, V– = V+

1 95
∴ Va = Vb = × × 10V ...(ii)
1.1 200

KCL at node ‘a’, gives,

V - V1 Va - Vo
a + =0
0.100 1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [53]

1  1 
⇒ Vo = – V1 + 1 +  Va
0.1  0.1 

Putting the values of V1 and Va from (i) and (ii) , we have,

1 105 1.1 1 95 105 - 95 
⇒ Vo = – × + × × V =–   V = − 5V
0.1 20 0.1 1.1 20  2 
Common Data for Examples 34 and 35 :
A differential amplifier is constructed using an ideal op-amp as shown in the adjoining figure. The
values of R1 and R2 are 47 kW and 470 kW respectively.
R2

R1
V1 –

V2 + Vo
R1
R2

Example 34
The input impedances seen looking into the terminals V1 and V2, with respect to ground, respectively,
are
(a) 47 kΩ and 43 kΩ (b) 47 kΩ and 47 kΩ
(c) 47 kΩ and 517 kΩ (d) 517 kΩ and 517 kΩ
GATE(IN/2010/2M)
Solution : Ans.(c)
R2

R1
V1 –

V2 + Vo
R1
R2

Given, R1 = 47 kΩ, R2 = 470 kΩ

Case -I: Input impedance w.r.t. V1
Setting V2 = 0, the circuit becomes as under,
R2

R1
V1 –
‘a’
‘b’ Vo
+
R1
R2

For ideal opamp V– = V+

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [54]
∴ Va = Vb = 0
Then current suppled by V1,
V1 - Va V1 - 0
I1 = =
R1 R1

V1
Input impedance w.r.t. V1, = R=
1 47kΩ
I1

Case-II : Input impedance w.r.t. V2

Setting V1 = 0, the circuit becomes as under,
R2

R1
–

I2 Vo
V2 +
R1
R2

Current drawn from V2,

V2
I2 =
R1 + R 2

Resistance seen by V2,

V2
= R1 + R2
I2

∴ Input impedance w.r.t. V2,

V2
= 47 + 470 = 517 kW
I2
Example 35
V1 and V2 are connected to voltage sources having an open circuit output of +1 each and internal
resistances of 13 kΩ and 3 kΩ respectively. The output voltage V0 is
(a) 0V (b) 0.15 V
(c) 1.5V (d) 10 V
GATE(IN/2010/2M)
Solution : Ans.(b)
By replacing voltage sources by their equivalent circuit. We have circuit as shown below,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [55]
470 k

Rs1=13k 47k 1
V1
–
P
1V Vo
1
V2
+
1V Rs2=3k 47k
470k

Output voltage Vo of the circuit becomes as under,

R2  R2  -470  470 
Vo = – × V1 + 1 +  V´ = × 1 + 1 +  × V´
R1 + R s1  R1 + R s1  60  60 

470 47
where, V′ = 1 × =
470 + 50 52

-470  470  47
⇒ V0 = + 1 + × = 0.15V
60  60  52
Example 36
In the ideal opamp circuit given in the adjoining figure, the value of RF is varied from 1 kΩ to 100
kΩ. The gain (G = v0 / vi) will
RF

R = 10 k
–

+ + +
Vi V0
R = 10 k

(a) remain constant at + 1 (b) remain constant at –1

(c) vary as –(RF / 10,000) (d) vary as (1 + RF / 10,000)
GATE(IN/2010/1M)

Solution : Ans.(a)

RF

R = 10 k
–
+ +
Vi + V0
R = 10 k
RF  R 
Output voltage of circuit, Vo = – Vi + 1 + F  Vi
R  R 

From circuit, R = 10kΩ

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [56]

 RF   RF 
Vo = -Vi  10  + Vi 1 + 10 
   

When RF = 1kΩ
Vo 1 1
= – +1+ = 1
Vi 10 10

 100   100 
When RF = 100 kΩ, Vo = - Vi   + Vi 1 +
 10   10 

Vo 100 100
⇒ = - +1+ =1
Vi 10 10

So, the gain remain constant at +1.

Example 37
In the circuit below, the operational amplifier is ideal. If V1 = 10 mV and V2 = 50 mV, the output
voltage (Vout) is
100 k

10 k
V1 –

V2 + Vout
10 k
100 k

(a) 100 mV (b) 400 mV

(c) 500 mV (d) 600 mV
GATE(EE/2019/2M)
Solution : Ans.(b)
100 k

10 k a
V1 –
b V0
V2 +
10 k
100 k

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [57]

100
Voltage at node ‘b’, Vb = × V2
100 + 10

10
⇒ Vb = V2
11

For an ideal opam, Va = Vb

10
∴ Va = V2
11

Applying KCL at node ‘a’,

Va - V1 Va - V0
+ =0
10k 100k

100k  100k 
⇒ V0 = V1 + 1 +  Va
10k  10k 

⇒ V0 = –10V1 + 11 Va
10
⇒ V0 = -10V1 + × 11V2
11

⇒ V0 = 10(V2 – V1)
⇒ V0 = 10(50 – 10) mV
⇒ V0 = 400 mV
Short cut : Given circuit is a differential amplifier with output voltage given by,
R2 100
V0 = (V2 - V=
1) (50 - 10) mV
= 400 mV
R1 10

Example 38
The common mode voltage is completely attenuated at the output of the differential amplifier shown
in the given figure if

R1 R2
–
+ e0
R3
e2
e1 R4

(a) R1 + R2 = R3 + R4 (b) R1 – R2 = R3 – R4
(c) R1/R2 = R3/R4 (d) R2/R1 = R3/R4
IES(EE,96)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [58]
Solution : Ans (c)
R2

R1
a –
eo
+
b
R3
+ e2
–
+ e1 R4
–

Voltage at node,
R4
Vo = × e1
R3 + R4

output voltage of Op-amp,

R1  R 
eo = - e2 + 1 + 2  V a
R1  R1 

For ideal Op-amp, V+ = V–

R2  R  R4
⇒ eo = - e2 + 1 + 2  × e1
R1  R1  R 4 + R 3

For common mode, e1 = e2 = e

R2  R  R4
eo = - e2 + 1 + 2  e1
R1  R1  R 3 + R 4

when eo = 0
R2 R + R2 R4
= 1 ·
R1 R1 R 3 + R 4

⇒ R2(R3 + R4) = (R1 + R2)R4

⇒ R2 R3 = R1R4
R1 R
⇒ = 3
R2 R4

Example 39
The expression for the output voltage Vo in terms of the input voltage V1 and V2 in the circuit shown
in the figure, assuming the operational amplifier to be ideal is :
V0 = A1 V1+ A2 V2
The values of A1 and A2 would be respec tively

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [59]

10 k 100 k
V2 –
V1 + V0
11 k
99 k

(a) 9 and –10 (b) 9.9 and –10

(c) –9 and 10 (d) –9.9 and 10
IES(EE,97)
Solution : Ans (b)
100k

10k
V2 –
a
11k b
V1 + Vo

99k

Voltage at node ‘b’

99 9
Vb = Vo = V1
99 + 11 10

For ideal Op-amp, Va = Vb

9
∴ Va = V1
10

Applying KCL at node ‘a’,

Va - V2 Va - Vo
+ = 0
10 100

 1 + 100  100  9
Vo =   × Va - × V2 = 1 -  V1 - 10V2
 10  10  10 

⇒ Vo = 9.9V1 – 10V2 = A1 V1 + A2 V2
Where, A1 = 9.9, A2 = – 10
7.4 Summing Amplifier
A summing amplifier is used to amplify the sum of input voltages. It can either amplify each voltage
with different amplification factors and them perform summing operation or it performs the summing
operation and then amplify the sum of voltages. Different possible operations of summing amplifier
as discussed in following sections,
Case-I: Inverting Mode
In this mode of operation the input voltages are connected to inverting terminal through different
resistances and non-inverting terminal is connected to ground as shown in Fig. 28.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [60]
RF

R1 a
V1 –
R2
V2 Vo
V3 +
R3

Fig. 28 Summing amplifier in inverting mode

Applying KCL at node ‘a’, we have,

0 - V1 0 - V2 0 - V3 0 - Vo
+ + + =0
R1 R2 R3 RF

R R R 
⇒ Vo = -  F V1 + F V2 + F V3  (118)
R
 1 R 2 R 3 

Special cases:
Case-A : When, R1 =R2 = R3 = R
R
Vo = - F [V1 + V2 + V3 ] (119)
R

Thus the circuit works like a summing amplifier when R1 =R2 = R3 = R

Case-B : When, R1 =R2 = R3 = R = 3RF
 V + V2 + V3 
Vo = -  1  (120)
 3

Then the amplifier works like an averaging circuit.

Case-C : When, R1 =R2 = R3 = RF= R
V =
- [V1 + V2 + V3 ] (121)

Then the amplifier works like a circuit which performs summing operation.

Case-II: Non-inverting Mode

In this mode of operation the input voltages are connected to non-inverting terminal through different
resistances and inverting terminal is connected to feedback network as shown in Fig. 29.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [61]
RF
R1

a –
Vo
R b
V1 +
R
V2
V3
R R

Fig. 29 Summing amplifier in non-inverting mode

The output voltage of non-inverting configuration can be obtained by finding the voltage at node ‘b’.
The voltage at node b can be obtained by either applying KCL at node b or by using superposition
theorem. Applying KCL at node b, we have,
Vb Vb - V1 Vb - V2 Vb - V3
+ + + =0
R R R R

1
⇒ Vb = (V1 + V2 + V3 ) (122)
4

The output voltage of non-inverting configuration is given by,

 R 
Vo = 1 + F  Vb (123)
 R1 

Putting expression of Vb from equation (122), in above equation, we have,

 R   V + V2 + V3 
Vo = 1 + F   1  (124)
 R1   4 

Special Case:
Case- A: When, RF = 3R1
Vo = V1 + V2 + V3 (125)
The amplifier works like a summing circuit.
Case- B: When R1 = 3RF
1
Vo = (V1 + V2 + V3 ) (125a)
3

The amplifier works like an an averaging circuit.

Case-III: Differential Mode

In this mode of operation the input voltages are connected to inverting as well as non-inverting

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [62]
terminals as shown in Fig. 30.
RF
R1 a
V1
–
R1 Vo
V2
R b
V3 +
V4
R R

Fig. 30 Summing amplifier in differential mode

The output voltage of differential configuration can be obtained by finding the voltage at node ‘b’.
The voltage at node b can be obtained by either applying KCL at node b or by using superposition
theorem. Applying KCL at node b, we have,

Vb Vb - V3 Vb - V4
+ + = 0
R R R

1

⇒ Vb = ( V3 + V4 ) (126)
3

Applying KCL at node ‘a’, we have,

Va - V1 Va - V2 Va - Vo
+ + = 0
R1 R1 RF

RF R  RF 
⇒ Vo = - V1 - F V2 + 1 +  Va (127)
R1 R1  R1 / 2 

1
For ideal op-amp, Va = Vb = ( V3 + V4 ) (128)
3
Putting above expression of Vb in equation (127), we have,

RF R  RF  1

Vo = - V1 - F V2 + 1 +  × (V3 + V4 ) (129)
R1 R1  R1 / 2  3

⇒ Vo = - R F V1 - R F V2 + 1 + R F  V3 + 1 + R F  V4 (130)
R1 R1  R1 / 2  3  R1 / 2  3

Above expression of output voltage can also be written directly by considering each of input voltages
one by one and finding output due to each input and finally adding all output voltages.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [63]
Special Case:
When, RF = R1, the output voltage of the circuit becomes as under,

Vo = (V3 + V4) - (V1 + V2) (131)
Example 40
The given figure shows a computational circuit using Op-amps. The value of Vout in this circuit is
10k 20k
V1

V2 – 10k 10k
20k
+
V3 –
5k
+ Vout

(a) 2 V1+ V2 – 2 V3 (b) 2 (V1 + V2) – V3
(c) V1 + V2 + V3 (d) V1 + 2 V2 - V3
IES(E&T,93)
Solution : Ans. (a)
10k A 20k
V1
VA
20k
V2
– 10k B 10k

+ V01

–
V3 5k
+ Vout

Applying KCL at node 1,
VA - V1 VA - V2 VA - V01
+ + =0
10 20 20

Since node (A) is at virtual ground,

So, VA = 0
20 20
⇒ V01 = - V1 - V2 = –2V1 – V2 .......(i)
10 20

Applying KCL at node ‘B’,

VB - V01 VB - V3 VB - Vout
+ + =0
10 5 10

As node B is also at virtual ground

So, VB = 0

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [64]

10 10
⇒ Vout = - V01 - V3 = –V01 – 2V3
10 5

Putting expression of V01 from equation (i), in above equation, we have,

⇒ Vout = –(–2V1 – V2) – 2V3 = 2V1 + V2 – 2V3

Example 41
The output voltage of the circuit show in the given figure is

R 2 k
–
+2V R + V0
–1V
R
R

(a) 1.0 V (b) 1.5 V

(c) 2.0 V (d) 2.5 V
IES(EE,98)
Solution : Ans (a)
2R
R
b –
R a
+ 2V + V0
R
– 1V
R

Applyhing KCL at node (a),

Va - 2 Va + 1 Va
+ + =0
R R R

⇒ 3Va = 1
1
⇒ Va = V
3

For ideal Op-amp, V– = V+

∴ Vb = Va = 1/3 V
Applying KCL at node (b),
Vb - 0 Vb - Vo
+ = 0
R 2R

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [65]
1
3
1
3 - Vo
⇒ + =0
R 2R

1 1
⇒ Vo = 2  +  = 1 V
3 6

Example 42
A non-inverting Op-amp amplifier is shown in figure. The output voltage Vo is
R

2R
–
R
–2V + Vo
R
(2+sin100t)V

(a) (3/2) sin (100 t) (b) 3 sin (100 t)

(c) 2 sin (100 t) (d) None of the above
GATE(EE/1996/1 M)
Solution : Ans.(a)
2R

R
–
a
R b Vo
–2V +
(2+sin100t)V
R
KCL at node ‘b’,
Vb + 2 Vb - (2 + sin100t)
+ =0
R R

2Vb = sin 100t

1
Vb = sin 100t
2

For ideal Op-amp, V– = V+

∴ Va = Vb = 1/2 sin 100t
KCL at node ‘a’,
V - 0 Va - Vo
a + =0
R 2R
3
⇒ Vo = 3Va = sin 100t
2
Example 43
For the circuit shown below, taking the opamp as ideal, the output voltage Vout in terms of the input

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [66]
voltages V1 , V2 and V3 is
9

1 VCC
V3 –
1
V1 + Vout
4 VSS
V2
(a) 1.8V1 + 7.2V2 – V3 (b) 2V1 + 8V2 – 9V3
(c) 7.2V1 + 1.8V2 – V3 (d) 8V1 + 2V2 – 9V3
GATE(EE-II/2016/2M)
Solution : Ans. (d)
9

1 VCC
V3 a
–
1 b
V1 + Vout
4 VSS
V2

The biasing current entering at inverting and non-inverting terminals is zero for ideal opamp. So,
voltage at node b can be obtained by applying KCL at node b as under,
Vb - V2 Vb - V1
+ = 0
4 1

⇒ Vb = (4V1 + V2) / 5
Applying KCL at node a, we have,
Va - V3 Va - Vout
+ = 0
1 9

⇒ Vout = -9V3 + ( 1+9) Va

Putting the expression of Va from equation (i), in above equation, we have,
⇒ Vout = -9V3 + ( 1+9)(4V1 + V2) / 5 = 8V1 + 2V2 – 9V3

Example 44
An ideal opamp has voltage sources V1, V3, V5, ........., VN – 1 connected to the non-inverting input and
V2, V4, V6, .........., VN connected to the inverting input as shown in the figure below (+VCC = 15 volt,
1 1 1 1 1
–VCC = –15 volt). The voltages V1, V2, V3, V4, V5, V6, ......... are 1, - , , - , , - , ........ volt,
2 3 4 5 6
respectively. As N approaches infinity, the output voltage (in volt) is ............

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [67]
10 k
V2
10 k 10 k
V4

VN – +VCC
10 k V0
+
1 k –VCC
V1
V3
1 k 1 k
VN–1
1 k
GATE(EC-I/2016/2M)
Solution : Ans. 14.9:15.5
The output voltage of above circuit can be given by

1  
10 10 10 N / 2  10 
Vo = - V2 - V4 ..... - VN + × 1 + ( V + V2 + ....VN -1 )
10  1
10 10 10 1+ N / 2 
 N/2

 
 1   N
⇒ Vo = -V2 - V4 ...... - VN +   × 1 +  ( V1 + V3 + .... + VN -1 )
1+ N   2
 2

⇒ Vo = V1 – V2 + V3 – V4 +......+ VN–1 – VN

1 1 1 1
Given, V1 = 1, V2 =
- , V3 =, Vn =
- , V5 =......
2 3 4 6
 1 1  1 1  1 1
∴ Vo = 1 -  -  + -  -  + -  -  + .......
 2 3  4 5  6 7

1 1 1 1 1
⇒ Vo = 1 + + + + + + ..... + up to infinity
2 3 4 5 6

The expression of Vo represents a Harmonic series. The sum of Harmonic series with infinite number
of terms is infinite. So, output voltage becomes infinity mathematically. However, the output voltage
of op-amp cannot be more the saturation voltage which is less than or equal to the supply voltage.

∴ Vo = +VCC = + 15V

8 Voltage to Current and Current to Voltage Converters

A voltage to current converter is a voltage controlled current source (VCCS) and current to voltage

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [68]
converter is a current controlled voltage source (CCVS).
8.1 Voltage to Current Converter
A voltage to current converter can be realized either by connected a floating load in feedback path
or by connecting a grounded load at non-inverting terminal. Each of these circuits is realized in the
following sections.
Case-I: With Grounded Load
The voltage to current converter with grounded load can be either in inverting mode or in non-
inverting mode. The load is connected at non-inverting terminal in both inverting and non-inverting
modes of converter.
Non-Inverting Mode :
The input voltage source is connected at inverting terminal in inverting mode voltage to source
converter with grounded load as shown in Fig. 31.

Vin R
a –
Vo
+
R b
R
IL RL

Fig. 31 Voltage to current converter with grounded load in inverting mode

Applying KCL at node ‘a, we have,

Va - Vin Va - Vout
= 0
R R

1
⇒ Va = [Vin + Vout ] (132)
2

For ideal Op-amp, V– = V+

1
∴ Vb = Va = [Vin + Vout ] (133)
2

Applying KCL at node ‘b’, we have,

Vb V - Vout
+ IL + b = 0 (134)
R R

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [69]
Putting the expression of Vb from equation (133) in above equation, we have,
2 1  V
⇒ I L +  (Vin + Vout )  - out = 0 (135)
R 2  R

Vin
⇒ IL + = 0
R

Vin
⇒ IL = - (136)
R

As load current is independent of load resistance so the circuit behaves like a voltage to current
converter.

Non-Inverting Mode :
The input voltage source is connected at non-inverting terminal in non-inverting mode voltage to
source converter with grounded load as shown in Fig. 32.

R
a –
Vo
+
R b
Vin
R
IL RL

Fig. 32 Voltage to current converter with grounded load in non-inverting mode

Applying KCL at node (a), we have,
Va - 0 Va - Vo

+ = 0 (137)
R R

Vo
⇒ Va = (138)
2

Vo
For ideal op-amp, Vb = Va = (139)
2

Applying KCL at node (b), we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [70]

Vb - Vin Vb - Vo
+ + I L = 0 (140)
R R

Putting the expression of Vb from equation (139) in above equation, we have,

V V V V
⇒ o - in + o - o + I L = 0 (141)
2R R 2R R

Vin
⇒ IL = (142)
R

As load current is independent of load resistance so the circuit behaves like a voltage to current
converter.

Case-II: With Floating Load

The load is connected in feedback path and voltage source is connected at non-inverting terminal in
a floating load type voltage to current converter as shown in Fig. 32. A floating load type voltage to
current converter is an example of a current-series feedback amplifier with load current as output
signal and supply voltage as input signal. The voltage drop across resistance R1 acts like a series
feedback signal.

(Load) IL

R1 RL
a –

Vin +
–

Fig. 33 Voltage to current converter with floating load
Applying KCL at node ‘a’, we have,
Va
- I L = 0 (143)
R1

Va
⇒ IL = (144)
R1

For an ideal op-amp, Va = V+ = Vin

Vin
⇒ IL = (145)
R1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [71]
It is observed here that load current is independent of load resistance. So, the circuit behaves like a
voltage to current converter.

8.2 Current to Voltage Converter

Fig. 34 shows the circuit diagram of a current to voltage source converter. A current to voltage
converter used to converter the output current from a solar cell or photo-diode to voltage signal.
RF

a – Vo
IS +

Fig. 34 Current to voltage converter

As bias current entering at inverting terminal of ideal op-amp is zero so whole of the source current
flows through the feedback resistance.

Applying KCL at node ‘a’, we have,

Va - Vo
- IS = 0 (146)
RF
If op-amp is ideal then , Va = V+ = 0

⇒ Vo = - RFIS (147)
The feedback resistance of current to voltage source converter is sometimes shunted with capacitor
to reduce the effect of high frequency noise and possibility of oscillations.
Example 45
In the circuit shown in figure the input voltage Vin (t) is given by 2 sin (100π t). For RL in the range
0.5 kΩ to 1.5 kΩ, the current through RL is
Vin(t) = 2sin (100 t)
+ V0
–
+ RL
–
~
1k IR
L

0.5k <RL<1.5k

(a) +2 sin (100 πt) mA (b) –2 sin (100 πt) mA

(c) +0.5 sin (100πt) mA (d) 1.5 sin (100 pt) mA

GATE(IN/2005/1M)
Solution : Ans.(a)
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [72]

+
+

~
Vo
Vin _
– RL
‘a’
IR
L
R1 1k

For ideal op-amp, V– = V+

∴ Va = Vin = 2 sin 100 πt
Va
KCL at node ‘a’, - I R L = 0
R1
Vin 1
⇒ I R L = = × 2sin100πt = 2 sin 100pt mA
R1 103

Note :- As load current is independent of load resistance so the given circuit is a floating load type V to I
converter in non-inverting mode.

Example 46
In the circuit given below, the opamp is ideal. The value of current IL in microampere is .............
100k

100k
–
10k
1V +
10k
IL
RL

GATE(IN/2016/2M)
Solution : Ans. (100)
R1 = 100 k

R1 = 100 k
–
'a'
R2 'b' Vo
Vi = 1V +
10 k R2

10 k
RL
IL

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [73]

R1 1
Voltage at node ‘a’, Va = × Vo =Vo
R1 + R1 2

1
For ideal op-amp voltage at node ‘b’, Vb = Va = Vo
2

Applying KCL at node ‘a’,

Vb - Vo Vb - Vi
+ + I L = 0
R2 R2
Vo Vo
- Vo - Vi
⇒ 2 + 2 + I L = 0
R2 R2
Vi 1
⇒ =
IL = = 104 A = 100 µA
R 2 10 × 103

Example 47
Consider the following circuit:

1 k 1 k
10 V
+ 15 V
–
V0
+
Vb – 15 V

1 k IL 1 k
200 

What is the load current IL in the above circuit?

(a) –5 mA (b) –10 mA
(c) + 25 mA (d) + 50 mA
IES(E&T,04)
Solution : Ans. (b)
1k A 1k
Vin = 10 V
+15V

–
Vo
+

1k –15
Vb B

1k
RL 200 

KCL at node (A),

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [74]

VA - 10 VA - Vo
+ = 0
1 × 103 1 × 103

⇒ 2 VA = Vo + 10
For ideal op-amp, VA = VB
⇒ 2 VB = Vo + 10 ......(i)
KCL at node (B),
V V V - Vo
B + B + B = 0
1000 200 1000

⇒ Vo = 7 VB ......(ii)
From (i), (ii);
2VB = 7 VB + 10
VB = – 2V
VB -2
Load current, IL = = = -10 mA
R 200

Short Cuts :- Given circuit is V to I converter with,

Vin 10
IL = = = – 10 mA
R 1k

Example 48
The value of V0 in the circuit, shown in figure is

0.3 mA 10 k
–
V0
+

20 k 30 k

(a) – 5V (b) –3 V
(c) + 3 V (d) + 5 V
GATE(IN/2004/2M)
Solution : Ans.(a)
‘b’ 10k

0.3mA

–
Vo
+

20k ‘a’ 30k

KCL at node ‘a’,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [75]

Va - Vo Va
+ = 0
30 20

 30  2
⇒ Vo = 1 +  Va = Vo
 20  5

For ideal Op-amp, V+ = V–

2
∴ Vb = Va = Vo
5

V - Vo
KCL at node ‘b’, b = 0.3 × 10–3
10 × 103

2 
⇒  5 - 1 Vo = 3 × 10 × 10
–3 3

 

⇒ Vo = - 5V

Example 49
In the circuit shown in the given figure, the output voltage will be

100 k
–
+ e0
100 A 1 k

(a) 9 V (b) 10 V
(c) 11 V (d) 12 V
IES(EE,98)
Solution : Ans (b)
100 k

(a) –
+ e0
100 A 1 k

For ideal op-amp, V+ = V–

So, Va = V– = 0V
Applying KCL at node ‘a’
0-e 0-0
o 3 + 3
- 100 × 10-6 =
0
100 × 10 100 × 10

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [76]
⇒ eo = – 100 × 10–6 × 100 × 103 V

⇒ eo = -10V

Example 50
In the circuit shown in the figure, the expression for Io/Ii is

Rf
– RL
V0
Ii +
 Io R

(a) RI /(RI + R) (b) Rf /RL
(c) (I + Rf /R) (d) (1 – Rf /R)
IES(EE,93)
Solution : Ans (b)
Rf

+2 – RL
vid Vo
Ii  +
– Io R
I

Output voltage of op-amp, V

o = - Ii Rf
Vo R
Current in resistance ‘R’, I = = – Ii f
R R

Applying KCL at output node ,

Io + I = Ii
Rf
⇒ Io - Ii = Ii
R
Io R
⇒ = 1 + f
Ii R

Example 51
The input resistance Rin (= vx/ix) of the circuit in figure is
R1 = 10 k R2 = 100 k

–
vo
+
vx
ix R3 = 1 M

(a) + 100 kΩ (b) – 100 kΩ

(c) + 1 MΩ (d) – 1 MΩ
GATE(EE/2004/2 M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [77]
Solution : Ans.(b)
R2 = 100k

R1
a –
10k b
vs + Vo
is

R3 = 1M

Applying KCL at node ‘b’,

vs - v o
= is
R3

vs –is R3 = vo ....(i)
For ideal Opamp, va = vb
∴ va = vs
Applying KCL at node ‘a’,
vs - 0 vs - v o
+ = 0
R1 R2

 R2 
⇒ vo = 1 +  vs ....(ii)
 R1 

From (i) & (ii), we have

 R 
vs – is R3 = 1 + 2  vs
 R1 

  R 
⇒ is R3 = vs 1 - 1 + 2  
  R1  

vs R R
⇒ = - 3 1
is R2

vs RR 10 × 103 × 1 × 106
Input resistance, Rin = = - 1 3 =– = –100 kΩ
is R2 100 × 103
Example 52
Find out output voltage of circuit given below:

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [78]
1K
1mA
–
–
+ Vo1 Vo
+
90 K RL
10 K

Solution :
Output of first stage op-amp,
Vo1 = –1 mA × 1K

Output of second stage op-amp

 90 
Vo = 1 +  Vo1
 10 

⇒ Vo = –10 V

9 Instrumentation Amplifier
In many industrial applications we need to measure the physical quantities such as temperature,
pressure, humidity etc. Such quantities are measured with the help of transducers whose output
signal is normally a voltage signal. The output signal of transducers is required to be amplified with
the help of an instrumentation amplifier. Fig. 35 shows the circuit diagram of an instrumentation
amplifier used to amplify the output of a bridge circuit used to measure temperature of a process with
the help of a thermistor.
V1
Thermistor
+ Vo1 R2
1
(RT) R –
R1
+ R
a –
eo Vo
RP R1 3
_ b +
R R – R
V2 2 R2
+ Vo2
+–
E
Bridge circuit Buffers Difference Amplifier
Fig. 35 Instrumentation amplifier Current to voltage converter
The buffer amplifiers are connected between bridge circuit and difference amplifier to avoid loading
bridge circuit and to control the gain of the amplifier. The output of buffer amplifiers of op-amp 1
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [79]
and op-amp 2 can be obtained by considering the circuit of op-amp 1 and op-amp 2 separately. If op-
amps are ideal then the voltage at node ‘a’ is V1 and voltage at node ‘b’ is V2. The isolation circuits
of op-amp 1 and op-amp 2 can be drawn as shown in Fig. 36.

V1 V1
+
RP
1 Vo1
–
R R
–
2 Vo2
RP +
V2 V2

(a)
(b)
Fig. 36 Buffer amplifier of op-amp 1 and op-amp 2

The output of op-amp 1 can be given by,

R  R 
Vo1 = - V2 + 1 + V1 (148)
RP  R P 

The output of op-amp 2 can be given by,

R  R 
Vo2 = - V1 + 1 +  V2 (149)
RP  R P 

The output of difference amplifier at output stage of the instrumentation amplifier can be given by,

R2
Vo = (Vo2 - Vo1 ) (150)
R1

Putting expressions of Vo1 and Vo2 in above equation, we have,

R2  R  R  R  R  
⇒ Vo = - V1 + 1 +  V2 + V2 - 1 +  V1  (151)
R1  R P  R P  R P  R P  

R 2  2R 
⇒ Vo = 1+ (V2 - V1 ) (152)
R1  R P 

⇒ Vo = Av(V2 – V1) (153)

R2  2R 
Where, Av = 1 +  = Gain or scaling factor (154)
R1  RP 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [80]
Thus, the gain of amplifier can be adjusted by varying the value of single register, RP.

Salient Features of instrumentation Amplifier

i) High accuracy
ii) High CMRR
iii) High gain stability
iv) Low DC offset
v) Low output impedance
vi) Adjustable scale factor.

Example 53
In the instrumentation amplifier shown in figure, if the switch SW is changed from position A to B,
the values of the amplifier gain G before and after changing the switch respectively are
+
– 50 k 500 k
SW
100 k
A
V1 +
22.2 k 10.53 k –
G(V1–V2)
50 k
V2 100 k

– 500 k
+

(a) 45, 95 (b) 50, 100

(c) 100, 200 (d) 90, 180
GATE(IN/2005/2M)
Solution : Ans.(c)
+ R1 R2
V1
–
–
R´ +
A B
Vo = G (V1– V2)
R1
RP
R´
R2
–
V2
+

Output voltage of instrumentation amplifier shown above is given by,

R 2  2R ′ 
Vo = 1 +  [V1 - V2 ]
R1  R P 

Vo = G [V1 – V2]
R 2  2R ′ 
Where, G = 1 + 
R1  R P 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [81]
Given, R1= 50 k, R2 = 500 k, R´ = 100 k, RPB = 10.53 k and RPA = 22.2 k
When switch is at position A,
500  2 × 100 
GA = 1+ = 100
50  22.2 

When switch is at position B,

500  2 × 100 
GB = 1+ = 200
50  10.53 

10 Integrator and Differentiator Circuits

Integrator is a circuit whose output signal is integral of the input signal and differentiator is a circuit
whose output signal is differentiation of input signal. Both of these circuits are discussed in the
following sections.

10.1 Integrator
An integrator circuit is realized using an inverting amplifier by replacing resistance in feedback path
by a capacitor as shown in Fig. 37.
ZF

1/sCF

Vi(s) R
– Vo(s)
+

Fig. 37 Integrator circuit

The gain or transfer function of the integrator in s-domain can be given by,

Vo (s) Z (s)

=- F (155)
Vi (s) R

Vo (s) 1 / sCF 1
⇒ =- =
- (156)
Vi (s) R sCF R

Output voltage of the circuit,

1
Vo(s) = - Vi (s) (157)
s CF R

The output voltage in time domain can be obtained by taking inverse Laplace transform of above
equation as under,
t
1
vo(t) = - ∫ vi (t) dt
CF R -∞
(158)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [82]
The gain of integrator as function of frequency can be obtained by replacing s by jω in equation
(156), as under,
Vo ( jω) 1
= - (159)
Vi ( jω) jω C F R

Problems Associated with Integrator Circuit:

It is observed from above relation that the magnitude of gain becomes infinite at ω = 0 and the op-
amp is driven to saturation and operation becomes unstable. So, it remains no more a linear amplifier
and the circuit ceases its operation as integrator. The gain at low frequency can be reduced by
connecting a resistance in shunt with the feedback capacitor as shown in Fig. 38.
RF

Vi(s) R
CF
Vo(s)
–

Fig. 38 Integrator circuit with stabilizing resistance

The value of resistance in feedback path is selected such that

T ≥ RFCF (160)

where T is time period of input signal.

Note : The resistance RF reduces the error in output voltage by limiting the gain at low frequency. Thus RF
improves the stability of integrator.

Example 54
A unit positive step is applied at the input of the circuit shown in the figure. After 20 seconds, the
output Vo will be
1 F

1 M + 10 V
–
Vin + V0
– 10 V

(a) + 20 V (b) + 10 V
(c) – 10 V (d) – 20 V
IES(EE,98)
Solution : Ans (d)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [83]
C= 1µF

R = 1M +10V
–
Vin(t) ios
+ Vo(t)

–10V

Above circuit is an inverting mode integrating circuit, whose output is given by

t
1
Vo(t) =
RC ∝ ∫
vin (b)dt

Given Vin (t) = u (t) = 1; t > 0

= t ; < 0
t
1
⇒ Vo(t) = –
RC 0 ∫
1dt

1 1
⇒ Vo(t) = – t= – t = -t
RC 1 × 10 × 1 × 10-6
6

At t = 20 sec
Vo (t) = -20V

Example 55
For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0, the
switch S is closed. The voltage Vc across capacitor at t = 1 millisecond is
1F

Vc
–
1k Vo
+
10V

In the figure shown above, the Op-amp is supplied with ±15 V.

(a) 0 Volt (b) 6.3 Volts
(c) 9.45 Volts (d) 10 Volts
GATE(EC/2006/2M)
Solution : Ans.(c)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [84]
1F

Vc
–
1k Vo
+

10V

When switch is open there is no feedback in the circuit and the output of op-amp is given as,
Vo = Vsat = + 15V
when switch is closed the capacitor starts charging with time constant RC.
The voltage across capacitor for t > 0 is given by,
Vc(t) = Vf – (Vf – Vi) e–t/RC
Here, Vi = 0,
Vf = +15 V
R = 1 k, C = 10–6 F
⇒ Vc(t) = +15(1 – e–t/RC)
At t = 1 m sec.
-10-3 10-3
Vc = +15(1 - e ) = 15(1 – e–1) = 9.45 V

Example 56
An integrator circuit is shown in figure. The opamp is of type 741 and has an input offset current
iOS of 1µA. C is 1 µF and R is 1 MΩ. If the input Vi is a 1 kHz square wave of 1 V peak to peak, the
output V0, under steady state condition, will be
C
R
–
Vi ios
+ Vo

(a) a square wave of 1 V peak to peak (b) a triangular wave of 1 V peak to peak
(c) positive supply voltage + Vcc (d) negative supply voltage – Vcc
GATE(IN/2003/1M)
Solution : Ans.(c)
C
R
–
Vi ios
+ Vo

Above circuit is an integrator. When input signal to an integrator is square wave the output signal is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [85]
a triangular wave.
Vi

+1V
T/2
t

–1 V
Vo

Example 57
The op-amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-
voltage Vi = 1 mV is applied at the input at time t = 0 as shown. Assuming that the operational
amplifier is not saturated, the time constant (in millisecond) of the output voltage Vo is
C

R 1F
–

Vi 1k A=1000
+ +
1mV +
–
Vo
t =0 s
–

(a) 1001 (b) 101

(c) 11 (d) 1
GATE(EE-I/2015/2M)
Solution : Ans. (a)
1/sC

1 µF
R
–
1k A
+ + +
Vi – Vo
–

The given circuit is an inverting amplifier connected in voltage shunt configuration with non-ideal
op-amp having open loop gain of A = 100. The closed loop gain of voltage-shunt configuration is
given by,
AK
AF =
1 + Ab

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [86]

R sCR
For the given cirucit, β = =
R + 1 / sC 1 + sCR

1 / sC 1
and K = =
R + 1 / sC 1 + sCR

1
A×
1 + sCR = A
⇒ AF =
sCR 1 + sCR + AsCR
1+ A ×
1 + sCR

A A
⇒ AF = =
1 + s (1 + A ) RC 1 + st
Where, t = (1 + A) RC = time constant of the circuit
For the given circuit, A = 1000, R = 1kΩ, C = 1 µF
∴ t = (1 + 1000) × 103 × 10–6 = 1001 ms

10.2 Differentiator
A differentiator circuit is realized using an inverting amplifier by connecting a capacitor in series
with the input supply as shown in Fig. 39.

RF
Vi(s) C
– Vo(s)
1/sC
+

Fig. 39 Differentiator circuit

The gain or transfer function of the differentiator in s-domain can be given by,
Vo ( s ) RF
= - (161)
Vi ( s ) 1 / sC

Vo ( s )
⇒ = - sCRF (162)
Vi ( s )

⇒ Vo(s) = - sCRFVi(s) (163)

The output voltage in time domain can be obtained by taking inverse Laplace transform of above
equation as under,
dvi (t)
vo(t) = -CR F (164)
dt
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [87]
The gain of integrator as function of frequency can be obtained by replacing s by jω in equation
(156), as under,
Vo ( jω)
= - jwCRF (165)
Vi ( jω)

Problems Associated with differentiator Circuit:

i) At high frequencies gain of the circuit becomes large driving the op-amp to saturation, which
results into unstable operation of the circuit.
ii) At high frequencies the impedance of capacitor also becomes small and hence the input impedance
of circuit. This makes the circuit sensitive to the noise signals.

Both of these problems can be overcome by connecting a resistance in series with capacitor and a
capacitor across feedback resistance as shown in Fig. 40.

CF

Vi(s)
– RF Vo(s)
R1 C1
+

Fig. 40 Practical differentiator circuit

The values of R1C1 and RFCF should be selected such that,

R1C1 = RFCF (166)

The input signal is differentiated properly if

T ≥ RFC1 (167)

where T is time period of input signal.
Note : The differentiator is most commonly used in waveshaping circuits to detect high frequency components
in an input signal and also as a rate of change detector in FM modulators.

Example 58
The input vi to a differentiator consists of a signal voltage vs = 10 sin (50 t) and a noise voltage vn =
0.1 sin (250 t). The signal-to-noise voltage ratio at the output of the differentiator
(a) decreases by a factor of 5 (b) decreases by a factor of 20
(c) increases by a factor of 5 (d) increases by a factor of 20
GATE(IN/1997/1M)
Solution: Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [88]

d
Vi dt Vo

Differentiator

Given, Vi = Vs + Vn
where Vs = 10 sin 50 t
Vn = 0.1 sin 250 t
dVi d
Output voltage, Vo = = [10 sin 50 t + 0.1sin 250 t]
dt dt

⇒ Vo = 500 cos 50 t + 25 cos 250 t

Vo = Vos + Von
where, Vos = 500 cos 50 t = output due to signal
Von = 25 cos 250 t = output due to noise
Signal to noise ratio at input,
| Vs | 10
SNRi = = = 100 ...... (i)
| Vn | 0.1

Signal to noise voltage ratio at output,

| Vos | 500
SNRo = = = 20 ..... (ii)
| Von | 25

From (i) and (ii), we have,

SNR o 20 1
= =
SNR i 100 5
1
⇒ SNRo = × SNR i
5

Thus, signal to noise ratio at output decreases by factor of 5.

11 Active Filters
The passive filters are comprised of only passive components like resistance, capacitance and
inductances. The active filters are comprised of passive components as well as op-amp based
amplifier. These filters provide the amplification in addition to the filtering action so these filters are
easy to tune. The active filters do not have problem of loading like passive filters due to high input
impedance and low output impedance of op-amp. These filters are cheaper due to low cost of op-
amp and absence of costly inductors.. Therefore, active filters are preferred over passive filters. The
passive filters can be categorized in five types,
i. Low pass filter

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [89]
ii. High pass filter
iii. Band pass filter
iv. Band reject
v. All pass filter
Ideally filters should have zero attenuation in passband and infinite attenuation in stop band which
is not practically possible. However, practical filters can be made to have ideal like characteristics
by using special designs techniques, precision components and high speed op-amps. Butterworth,
Chebyshev and Cauer filters are some of the commonly used practical filters. The Butterworth filter
has flat stop band and flat passband due to which it is also known as flat-flat filter. The Chebyshev
filter has a ripple passband and flat stop band. A Cauer filter gives ripple passband and ripple stop
band. Cauer gives best stop band among all these three filters.
11.1 Low Pass Filters
The low pass filer allow to pass the signals of frequency up to certain frequency called cutoff
frequency of the filter. These filters attenuates the frequencies more than the cutoff frequency of the
filter. The op-amp based low pass filter can be realized in inverting as well as non-inverting modes
as follows,
Case-I: Non-inverting mode
Fig. 41 shows a first order low pass filter in non-inverting mode. The input signal is connected at
non-inverting terminal through R and C components and feedback network is connected at inverting
terminal to provide the negative feedback as usual.
RF
R1
–
Vo
R b
Vin +
1/sC

Fig. 41 Low pass filter in non-inverting mode

Voltage at node ‘b’ can be given by,

1 / sC
Vb = × Vin (s) (168)
R + 1 / sC

The output voltage of the op-amp can be given by,

 R 
Vo(s) =  1 + F  × Vb (169)
 R1 

Putting expression of voltage Vb from equation (168) in above equation, we have,

 RF  1 / sC
Vo(s) = 1 +  × . Vin (s) (170)
 R1  R + 1 / sC

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [90]
Transfer function of the filter,
Vo (s) Ao
⇒ = (171)
Vi (s) 1 + s CR

RF
Where, Ao = 1 + = DC gain of amplifier (172)
R1

The transfer function of the filter can be obtained in frequency domain by replacing s by jω in
equation (171) as under,
Vo ( jω) Ao Ao Ao
= = = (173)
Vin ( jω) jω jω f
1+ 1+ 1+ j
1 / CR ωH fH

1
Where, ωH = 2pfH = = Higher cut off frequency of the filter (174)
RC
1
or fH = (175)
üπ

Frequency Response of Low Pass Filter :

The frequency response of a filter comprises of magnitude versus frequency as well as phase versus
frequency plots. The magnitude plot gives variation of magnitude of transfer function of the filter as
function of the frequency.
The magnitude and phase angle of transfer function of low pass filter can be obtained from equation
(173) as under,
Vo Ao
= (176)
Vin  f 
2

1+  
 fH 

 V ( jω)  -1 f
∠ o  = - tan (177)
 Vin ( jω)  fH

The variation of magnitude of transfer function or frequency response can be drawn using equation
(177), as shown in Fig. 42. The gain of filter becomes 1/ 2 or 0.707 times of the DC gain at cutoff
frequency. If gain is taken in dB then gain falls by 3dB from DC gain at cutoff frequency due to
which cutoff frequency is also known as 3dB cutoff frequency.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [91]
Vo
Vin
Ao
Ao
2 Roll off rate
(–20dB/dec)
Passband Stopband

fH f
Fig. 42 Frequency response of low pass filter
Case-II: Inverting Mode
A. Capacitor Based :
Fig. 43a shows a capacitor based first order low pass filter in inverting mode. The feedback path
consists of a parallel combination of R and C. The input signal is connected at inverting terminal
through resistance R1.
R

Vin(s) R1
– 1/sC Vo(s)

Fig. 43a Capacitor based low pass filter in inverting mode

The impedance of feedback path,

R × (1 / sC) R
ZF(s) = = (178)
R + 1 / sC 1 + sCR

Transfer function of filter of the filter,

Vo (s) Z (s) R / (1 + sCR) R / R1
= - F = - =
- (179)
Vin (s) R1 R1 (1 + sCR)

Vo (s) Ao
⇒ = (180)
Vin (s) 1 + s CR

R
Where, Ao = - = DC gain of amplifier (180a)
R1

For frequency domain, s = jw,

Vo ( jω) Ao Ao Ao
= = = (181)
Vin ( jω) jω jω f
1+ 1+ 1+ j
1 / CR ωH fH
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [92]
B. Inductor Based :
Fig. 43b shows a inductor based first order low pass filter in inverting mode. The feedback path consists
of a resistance and the input signal is connected at inverting terminal through series combination of
a resistance R1 and inductor L.
Z1(s) RF

R1 sL
–
Vin(s) Vo(s)
+

Fig. 43b Inductor based low pass filter in inverting mode

Transfer function of above circuit can be given by
Vo (s) R RF
T(s) = =
- F = - (182)
Vin (s) Z1 (s) R1 + sL
In frequency domain, s = jω
Vo ( jω) RF R / R1 Ao
= - =
- F =
- (182a)
Vin ( jω) R 1 + j ωL jωL jω
1+ 1+
R1 ωH
RF
Where, Ao = = DC gain of the filter (183)
R1

R1

ωH = = cut off frequency (183a)
L

Note : A first order low pass filter has one pole on negative real axis and no zeros.
Case-III : Second Order Low Pass Filter
A second order low pass filter can be realized by connecting to low pass RC circuits in non-inverting
terminals as shown in Fig. 44.
RF

R1
–
Vin R2 R3 Vo
+
1 1
sC2 sC3

Fig. 44 Second order low pass filter

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [93]
The magnitude of of transfer function of second order low pass filter is given by,
Vo ( jω) Ao
= (184)
Vin ( jω) 4
 f 
1+  
 fH 

RF
Where, Ao = 1 + (184a)
R1

1
And fH = = cutoff frequency (184b)
2 π R 2 R 3 C 2 C3

Case-IV : nth Order Low Pass Filter

Higher order low pass filters can be realized by connecting first order and second order low pass
filters in cascade. The magnitude of transfer function for nth order filter is given by,
Vo ( jω) Ao

= (184c)
Vin ( jω)  f 
2n

1+  
 fH 

Where, n → order of filter.

Note : A second order low pass filter has two poles located on negative real axis and no zeros.

Example 59
In the circuit shown in Figure if e1 = sin t, the voltage eo is

10k 10k
–
100k eo
+
ei
~ 10F

 π 1  π
(a) 2 sin  t -  (b) sin  t + 
 4 2  4

1  π  π
(c) sin  t -  (d) 2 sin  t - 
2  4  4

GATE(IN/1996/1M)
Solution : Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [94]
RF

R1 10 k
–
10 k
R eo
ei +
100 k
C 10 F

The circuit shown above is a low pass filter with transfer function,
RF
1+
e R1
H(jω) = o =
ei 1 + jωRC

Given, ei = sin t = sin(ωt + φ)

where, ω = 1 rad/sec, φ = 0°
10
1+
10 2
H(jω) = 3 -6 =
1 + j1 × 100 × 10 × 10 × 10 1 + j1

|H(jω)| = 2
∠H(jω) = – 45º
Magnitude of output voltage,
|eo| = |H(jω)| × |ei| = 2 ×1 = 2
Phase of output voltage, ∠eo = ∠H(jω) + ∠ei = – 45º + 0º = – 45º

Instantaneous output voltage, eo = |eo| sin (ωt + ∠eo)

∴ eo = 2 sin(t - 45°)

Example 60
Consider the circuit shown below
330pF

22k 22k
+
Vin Vo
330pF –
10k

17k

The correct frequency response of the circuit is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [95]
|Vo/Vi|
|Vo/Vi|
4dB 0dB
1dB –3dB
(a) (b) 40dB/decade
20dB/decade

21.9 kHz f
21.9 kHz f

|Vo/Vi|
4dB
1dB
(c) 40dB/decade (d) |Vo/Vi|
4dB
21.9 kHz f 1dB
20dB/decade
GATE(IN/2007/2M)
f
21.9 kHz
Solution : Ans.(c)
C=330pF

R=22k R=22k C
Vin +
Vout
C=330pF –
RF 10k

R1 17k

The circuit given above is a second order low pass filter having transfer function,

Ao

Av =
4
 f 
1+  
 fH 

RF 1
Where, Ao = 1 + = d.c. gain and fH = = cutoff frequency of filter
R1 2πRC

Given, RF = 10k, R1 = 17k, R = 22kΩ, C = 330pF

10
∴ Ao = 1 +
17

 10 
In dB, AodB = 20 log 1 +  =
4dB
 17 

1 1
Cutoff frequency, fH = = = 21.9 kHz
2πRC 2π × 22 × 10 × 330 × 10-12
3

www.digcademy.com digcademy@gmail.com
 Op-amp & Its Applications EDC & ANALOG ELECTRONICS [96]
The characteristic of above filter are as under,
Av,dB

4dB
3dB
1dB

fH = 21.9kZ f

Example 61
A first order, low pass filter is given with R = 50 Ω and C = 5 µF. What is the frequency at which the
gain of the voltage transfer function of the filter is 0.25?
(a) 4.92 kHz (b) 0.49 kHz
(c) 2.46 kHz (d) 24.6 kHz
GATE(EE/2001/1M)
Solution : Ans.(c)
Transfer function of the low pass filter,
1
T(jω) =
1 + jωRC

1 1
Gain, |T(jω)| = =
12 + ( ωRC )
2
1 + (ω× 50 × 5 × 10-6 ) 2

Let at ω = ω1 ; T(jω) = 0.25,

1
⇒ 0.25 =
1 + ( ω× 50 × 5 × 10-6 )
2

⇒ ω = 15491.93 rad/s
⇒ 2pf = 15491.93 rad/s
⇒ f = 2.46 kHz

Example 62
In the circuit shown using an ideal opamp, the 3-dB cut-off frequency (in Hz) is ...........
10 k 10 k
Vi
+
0.1F – Vo
10 k 10 k

GATE(EC-III/2015/1M)
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [97]
Solution : Ans. (159 to 160)
The given circuit can be redrawn as show below
10 k C 10 k
Vi +
R b
a Vo
0.1 µF C –
R
10 k 10 k

The biasing current drawn by ideal op-amp is zero. So, current in 10 kΩ resistance connected at non-
inverting terminal of Op-amp is zero.
1 / j ωC 1
Then, Vb = Vc = × Vi
= × Vi
1 1 + jωCR
+R
j ωC
Output voltage of non-inverting configuration can be given by,
 R 1
Vo = 1 +  × Vb =2Vb =2 × × Vi
 R 1 + jω CR
Vo 2
⇒ =
Vi jω
1+
ωc
1
When, wc = 2π f c = = cutoff frequency.
RC
1 1
⇒ =
fc = = 159.1Hz
2π RC 2π × 10 × 103 × 0.1 × 10-6

Example 63
The operational amplifier shown in the figure is ideal. The input voltage (in volt) is Vi = 2 sin(2π ×
2000 t). The amplitude of the output voltage Vo (in volt) is .............
0.1F

1 k 1 k
–
Vi +
Vo

GATE(EE-II/2015/1M)
Solution : Ans. (1.1 to 1.4)
The given circuit can be redrawn as show below

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [98]
C = 0.1 µF

R= 1k
1 k
Vi –
R Vo
+

The transfer function of given circuit can be given by,

 1 
 R × j ωC 
 
R+ 1 
 jω C  1
Vo - =
-
= R 1 + jω RC
Vi
1
⇒ Vo = - × Vi
1 + j2π fRC
Amplitude of output voltage,
1
|Vo| = × | Vi |
1 + ( 2π f RC )
2

Given, Vi = 2 sin (2π × 2000 t) = |Vi| sin 2π ft

where, |Vi| = 2 and f = 2000
1
⇒ |Vo| = ×2
1 + ( 2π × 2000 × 1 × 103 × 0.1 × 10-6 )
⇒ |Vo| = 1.245 V

Example 64
Assuming the op-amp shown in the figure to be ideal, the frequency at which the magnitude of Vo will
be 95% of the magnitude of Vin is...............kHz.
+
10 k Vo
–

Vin ~ 10 nF
1 k
1 k

GATE(IN/2017/2M)
Solution : Ans. (2.9 to 3.0)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [99]
10 k 'b'
Vi +
R1
Vo
C 10 µF
–
1 k
'a'
R2
1 k R2

1
j ωC 1
Voltage at node ‘b’, Vb = Vin
×= × Vin
1 1 + jωRC
R1 +
j ωC

 R 
Output voltage, Vo = 1 + 2  Vb =
2Vb
 R2 

1 2
⇒ Vo = 2 × =× Vin × Vi
1 + jω R1C 1 + jω R1C
For given circuit R1 = 10 kΩ, C = 10 nF
2
⇒ Vo = × Vi
1 + j2π f × 10 × 103 × 10 × 10-9

2
Magnitude of output |Vo| = × | Vi |
1 + ( 2π × 10 f )
-4 2

Let |Vo| = 0.95 |Vi| at f = f1

2
⇒ 0.95 =
1 + ( 2π × 10-4 f1 )
2

⇒ f1 = 2.948 kHz

Example 65 C

R1 L R2
–
Vi
+ Vo

The op-amp circuit shown above represents a

(a) High pass filter (b) Low pass filter
(c) Band pass filter (d) Band reject filter
GATE(EC/2008/2M)
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [100]
Solution : Ans.(b)
ZF

Z1 C

R2
–
Vi R1 L
+ Vo

The transfer function of amplifier

Vo Z
= - F
Vi Z1

1
× R2
j ωC R2
where, ZF = =
1
+ R 2 1 + j ωR 2 C
j ωC

Z1 = R1 + jωL
Vo R2
∴ = -
V1 (1 + jωR 2 C)(R1 + jωL)

Above expression is the transfer function of second order low pass filter.
11.2 High Pass Filters
The high pass filer allow to pass the signals of frequency above certain frequency called cutoff
frequency of the filter. These filters attenuates the frequencies less than the cutoff frequency. The op-
amp based high pass filter can be realized in inverting as well as non-inverting modes as follows,
Case-I: Non-inverting Mode
Fig. 45 shows a first order high pass filter in non-inverting mode. The input signal is connected at
non-inverting terminal through R and C components and feedback network is connected at inverting
terminal to provide the negative feedback as usual.

RF
R1
–
1
sC b Vo
Vin +
R

Fig. 45 High pass filter in non-inverting mode

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [101]
Voltage at node ‘b’ can be given by,
R
Vb = × Vin (s) (185)
R + 1 / sC

The output voltage of the op-amp can be given by,

 R 
Vo(s) =  1 + F  × Vb (186)
 R1 
Putting expression of voltage Vb from equation (185) in above equation, we have,
 R  R
Vo(s) = 1 + F  × . Vin (s) (187)
 R1  R + 1 / sC

Transfer function of the filter,

 R 
 1+ F 
Vo (s)
= 1 + R F   R  
=
R1
 (188)
Vin (s)    
R1   R + 1 / sC   1 + 1 / sCR 



Vo (s) Ao
⇒ = (189)
Vin (s) 1 + 1
s CR

RF
where, Ao = 1 + = Gain of the filter at high frequencies (190)
R1

The transfer function of the filter can be obtained in frequency domain by replacing s by jω in
equation (189) as under,

Vo ( jω) Ao
= (191)
Vin ( jω) 1 / CR
1+
jω

Vo ( jω) Ao Ao
⇒ = = (192)
Vin ( jω) ω f
1+ L 1+ L
jω jf

1
where, ωL = 2pfL = = cutoff frequency of the filter (193)
RC
Frequency Response of High Pass Filter :

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [102]
The frequency response of a high pass filter is obtained similar to a low pass filter. The magnitude
and phase angle of transfer function of pass filter can be obtained from equation (192) as under,

Vo ( jω) Ao Ao
= = (194)
Vin ( jω) ω 
2
f 
2

1+  L  1+  L 
 ω f 

Vo f
And ∠ tan -1 L
= (195)
Vin f
The variation of magnitude of transfer function or frequency response of high pass filter can be
drawn using equation (194), as shown in Fig. 46. The gain of filter becomes 1/ 2 or 0.707 times of

the flat band gain at cutoff frequency. If gain is taken in dB then gain falls by 3dB from flat band gain
at cutoff frequency due to which cutoff frequency is also known as 3dB cutoff frequency.

Vo
Vin
Ao
Ao
2

stop Passband
band

fL f
Fig. 46 Frequency Response of high pass filter

Case-II: Inverting Mode

A. Capacitor Based :
Fig. 47a shows a capacitor based first order high pass filter in inverting mode. The feedback path
consists of a resistance RF and the source of signal is connected at inverting terminal through series
combination of a resistance R and capacitor C.

RF

Vin(s) R 1/sC
–
Vo(s)
+

Fig. 47a Capacitor based high pass filter in inverting mode

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [103]

RF R /R
The output voltage, Vo(s) = - . Vin (s) =
- F . Vin (s) (196)
1 1
R+ 1+
sC sC R

Transfer function of filter of the filter,

Vo (s) RF / R Ao
⇒ = - =
- (196a)
Vin (s) 1 1
1+ 1+
s CR s CR

RF
Where, Ao = - (196b)
R
For frequency domain, s = jw,
Vo ( jω) Ao Ao Ao
= = = (197)
Vin ( jω) 1 / CR ω f
1+ 1+ L 1+ L
jω jω jf

B. Inductor Based :
Fig. 47b shows an inductor based first order high pass filter in inverting mode. The feedback path
consists of parallel combination of a resistance RF and inductor L. The input signal is connected at
inverting terminal through a R1.
sL
ZF(s)
RF
Vin(s) –
R1 Vo(s)
+

Fig. 47b High pass indcutor based filter in inverting mode
Transfer function of the filter,
Vo (s) Z (s) sL R F / (sL + R F ) R /R
= - F = - =
- F 1 (198)
Vin (s) R1 R1 RF
1+
sL

In frequency domain, s = jω
Vo ( jω) R / R1 Ao
⇒ = - F =
- (199)
Vin ( jω) R /L ω
1+ F 1+ L
jω jω

RF
Where Ao = = gain at large frequencies (199a)
R1
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [104]

RF
wL = = Cutoff frequency of the filter. (199b)
L

Case-III : Second Order High Pass Filter

A second order high pass filter can be realized by connecting to low pass RC circuits in non-inverting
terminals as shown in Fig. 48.

The magnitude of of transfer function of second order high pass filter is given by,
Vo ( jω) Ao
= (200)
Vin ( jω) f 
4

1+  L 
f 

RF
R1
–
1 1
sC2 sC3 Vo
+
Vin R2 R3

Fig. 48 Second order high pass filter

RF
Where, Ao = 1 + (200a)
R1

1
And fL = = Lower cutoff frequency (200b)
2 π R 2 R 3 C 2 C3

Case-IV : nth Order High Pass Filter

Higher order high pass filters can be realized by connecting first order and second order high pass
filters in cascade. The magnitude of transfer function for nth order high pass filter is given by,
Vo ( jω) Ao

= (201)
Vin ( jω) f 
2n

1+  L 
f 
Where, n → order of filter.
Note : The role off rate of frequency response of nth order filter is - 20n dB/dec, where n is order of the filter.

Example 66
The 3-dB cut-off frequency of a first order analog high pass filter is ωc. For a signal 0.5sinωc(t), the
output will have a phase shift of
(a) – π/2 (b) – π/4

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [105]
(c) π/4 (d) π/2
GATE(IN/2001/2M)
Solution : Ans.(b)
Transfer function of 1st order high pass filter is given by,
Ao Ao
Af = =
fc ω
1+ j 1+ j c
f ω

where, fc = cutoff frequency of filter

when, ω = ωc,
A A
Af = o = o ∠ – 45°
1 + j1 2

Vo A
⇒ = o ∠ – 45°
Vi 2

⇒ ∠Vo = ∠Vi + ∠ - 45°

So, the phase shift in output is – 45° or – π/4

Example 67
The circuit below implements a filter between the input current ii and the output voltage vo. Assume that
the op-amp is ideal. The filter implemented is a
L1
R1
ii
–

+ +
vo
–

(a) low pass filter (b) band pass filter

(c) band stop filter (d) high pass filter
GATE(EC/2011/1M)
Solution : Ans.(d)
Equivalent circuit,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [106]
L1

R1

ii
–
1
+
+
vo
–

For ideal op-amp v+ = v–

As v+ = 0, So v– = 0
Applying KCL at node 1,
0 - vo 0 - vo
+ + ii = 0
jωL1 R1

 1 1 
⇒ vo  +  = ii
 j ω L1 R 1

Transfer function of circuit,

vo R1
H(jω) = =
ii R /L
1+ 1 1
jω

|H(jω)| =
 R1 / L1 
 
 
The gain |H(jω)| of circuit increases with increase in frequency. So, the given circuit represent a high
R1
pass filter with cut-off frequency ωL = .
L1

11.3 Band Pass Filter

A band pass filter passes a band of frequencies. It attenuates all the frequencies below lower
cutoff frequency and above upper cutoff frequency. Band pass filter can be classified in two
categories called wide band pass with Q-factor more than 10 and narrow band pass with
Q-factor less than 10.
Case-I : Wide Band Pass Filter
Wide band pass filter is realized by connecting first order low pass and high pass filters, in cascade as
shown in Fig. 49. The combination works like a band pass filter only if cutoff frequency of high pass
stage is lower than high pass stage.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [107]
RF
RF R
R –
– Vo
C1 +
Vin + R2 C2
R1

High pass Low pass

Fig. 49 Wide band pass filter.
The transfer function of wide band pass filter is production of transfer function of low pass stage and
high pass stages as under,
Vo ( jω) A oL A oH
= × (202)
Vin ( jω) f f
1+ j 1- j L
fH f

RF
Where, AoL = AoH = 1 + 1 + , (203)
R

1
fH = = Upper cutoff frequency of low pass stage (204)
2πR 2 C2

1
and fL = = Lower cutoff frequency of high pass stage (205)
2πR1C1

The cutoff frequency of low pass stage is higher cutoff frequency and the cutoff frequency of high
pass stage is lower cutoff frequency of bandpass filter.
Vo ( jω) Ao
⇒ = (206)
Vin ( jω)  f  fH 
1 + j f  1 - j f 
 L 

Where, Ao = AoLAoH = Mid band gain of the bandpass filter (207)

The magnitude of tranfer function of the band pass filter can be given by,
Vo ( jω) Ao
Vin ( jω) = (208)
  f 2    f H 2 
1 +    1 +   
  f L     f  

Condition:
The cascaded combination of low pass and high pass stages work like a wide band pass filter only if

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [108]
the cutoff frequency of low pass stage is more than the cutoff frequency of high pass stage.
i.e. fH > fL (209)
1 1
or > (210)
R 2 C2 R1C1

⇒ R1C1 > R2C2 (211)

Frequency Response of Wide Band Pass Filter :

The frequency response of a wide band pass filter can be drawn by using the equation (208) as shown
in Fig. 50.
Gain

Ao
Ao
2 Passband

fL fH f

Fig. 50 Frequency Response of band pass filter

Bandwidth :
BW = fH - fL (212)

Case-II : Narrow Band Pass Filter

A narrow bandpass filter consists of op-amp in inverting mode with two feedback paths as shown in
Fig. 51.
C2

Vin R1 b C1 R3
a – Vo
R2
+

Fig. 51 Narrow band pass filter

Frequency response of narrow band pass filter is shown in Fig. 52. The frequency fo is called center
frequency of the filter.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [109]
Gain
Ao
0.707Ao

fL fo fH f
Fig. 52 Frequency response of narrow band pass filter
Case-III : Wide Band Pass Filter in Inverting Mode
A wide band pass filter can also be realized using signal op-amp in inverting mode by connecting
parallel RC branch in feedback path and series RC branch in series with the source as shown in Fig.
53.
1/sC2

R2

Vin R1 1/sC1
– Vo
+

Fig. 53 Wide band pass filter using signal op-amp

Transfer function of filter of the filter can be given by,

1
R2×
s C2
1
R2 +
s C2
Vo(s) = - . Vin (s) (213)
1
R1 +
s C1

C1 / C2
⇒ Vo(s) = - . Vin (s) (214)
 1 
1 +  (1 + s C1R1 )
 s C2 R 2 

Vo (s) C1 / C2
⇒ = - (215)
Vin (s)  1 
1 +  (1 + s C1R1 )
 s C2 R 2 
Above equation can also be modified as under,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [110]

Vo (s) R 2 / R1
⇒ = - (216)
Vin (s)  1 
(1 + s C2 R 2 ) 1 + 
 s C1R1 

Statement for Linked Answer Example 68 and 69:

A general filter circuit is shown in the figure:
R2

R1 C
Vi –
Vo
+
R3
R4

Example 68
If R1 = R2 = RA and R3 =R4 =RB , the circuit acts as a
(a) All pass filter (b) Band pass filter
(c) High pass filter (d) Low pass filter.
GATE (EE/2008/2 M)
Solution : Ans.(c)
R2
zF
R1 C
Vi –
‘a’
‘b’ Vo
+
R3
R4

Voltage at node ‘b’, Vb = ×

R3 R4

For ideal opamp, V– = V+

R4
∴ Va = Vb = × Vi
R 3 + R4

KCL at node ‘a’,

Va - Vi Va - Vo
+ = 0
R1 ZF

ZF  Z  Z  Z  R4
Vo = – Vi + 1 + F  Va = – F Vi + 1 + F  × × Vi
R1  R1  R1  R1  R 3 + R 4
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [111]

1
R2 ×
jω C R2
where, ZF = =
1 1 + j ωC R 2
R2 +
j ωC

R2  R2  R4
Vo = - Vi + 1 +  × × Vi
R1 [1 + jωC R 2 ]  R1 (1 + jωCR 2  R 3 + R 4
Given, R1 = R2 = RA & R3 = R4 = RB
1 1 1 
Vo = - × Vi + 1 +  Vi

1 + jωCR A 2  1 + jωCR A 

 -2 + 2 + jωCR A  j ωC R A
Vo =   Vi = × Vi
 2(1 + jωCR A )  2(1 + jωC R A )

Vo 0.5
Gain of circuit, A = =
Vi 1 + ωL
jω

0.5
⇒ |A| = 2
ω 
1+  L 
 ω

1
where, ωL = = lower cut-off frequency.
CR A

|A|

L 

Gain of circuit reduces with decrease in frequency and becomes constant at ω = ∞. So, given circuit
is a high pass filter.

Example 69
The output of the filter is given to the circuit shown in figure:
RA/2

vin C v0

The gain vs frequency characteristic of the output (vo ) will be

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [112]

Gain Gain
(a)
(b)
0 
0 

Gain Gain
(c) (d)
0 
0 

GATE (EE/2008/2 M)
Solution : Ans.(d)
RA/2
+
Vin 1/jC Vo
–

The transfer function of circuit

Vo 1 / jωC 1 1
= = =
Vin RA jωCR A jω
+ 1 / jω C 1+ 1+
2 2 ωH

2
where, ωH = = upper cutoff frequency of low pass filter
CR A

⇒ ωH = 2 ωL
The transfer function of circuit is that of a low pass filter, with cutoff frequency which is twice the
cutoff frequency of high pass filter. The overall characteristics with RC circuit connected at output of
high pass filter, will be as shown below,
|A|

L= 1 L= 2

CRA CRA

11.4 Band Reject Filter

A band reject filter attenuates or rejects a band of frequencies. The frequencies outside
the stop band are passed through the filter. The band reject filter can be classified in two

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [113]
categories called wide band reject filter and narrow band reject filter (Q > 10). The narrow
band reject filter is uncommonly known as notch filter.
Case-I : Wide Band Reject Filter
Wide band reject filter can be realized by connecting outputs of high pass and low pass filters at
inputs of summing amplifier and giving same input to both low pass and high filters as shown in the
Fig. 54. The combination works like a band reject filter only if upper cutoff frequency of low pass
filter is less than lower cutoff frequency of high pass filter.
High pass filter

RF

R
–

R
+
R
C2 R2 – Vo
Vin RF
R
+
R
–
R1
+
C1

Low pass filter Summing Amplifier

Fig. 54 Wide band reject filter

Conditions:
i. The gain of pass band of both filters should be kept same.
ii. The combination of works like a wide band reject filter only if the cutoff frequency of low pass
stage is less than the cutoff frequency of high pass stage.

fH < fL (217)
1 1
⇒ < (218)
R1C1 R 2 C2
⇒ R2C2 < R1C1 (219)

Frequency Response of Wide Band Reject Filter :
The frequency response of a wide band reject filter is as shown in Fig. 55. It is observed from the
characteristics that the band of frequencies between two cutoff frequencies is rejected by the filter.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [114]

Gain Pass Pass

band stop band band

Ao
0.707Ao

fL fH f
Fig. 55 Frequency Response of band pass filter
Case-II : Narrow Band Reject Filter
A narrow band reject filter is also known as notch filter as shown in Fig.55. It can be realized by
using a twin-T RC network. The output of twin-T network is connected at input of a voltage follower
to improve the Q-factor. Notch filters are mostly used in communication systems and biomedical
instruments to eliminate the undesired frequency. The notch out frequency of notch filter is given by,
1
fN = (220)
2πRC

R R
Vin
C C
+
R 2C – Vo
2

Twin-T network
Fig. 56 Narrow band reject or notch filter

Frequency Response of Notch Filter :

Frequency response of narrow band pass filter is shown in Fig. 57. The frequency fN is notch frequency
of the filter.
Gain
Ao
0.707Ao

fL f N fH f

Fig. 57 Frequency Response of notch filter

Q-factor of Notch Filter:

Q-factor of notch filter is given by,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [115]

fN f
Q = = N (221)
f H - f L BW

where BW is bandwidth of the filter.

11.5 All Pass Filter
All pass filter passes all the frequency components of input signal without attenuation. However,
it provides different phase shift to different frequency components of input signal. The all pass
filter is used to compensate the phase shift introduced in signals by communication channels during
transmission over a transmission channel. All pass filters are also known as delay equalizers or phase
correctors. Fig. 58 shows an all pass filter.
RF= R1
R1
Vo
–
a
+ R b
Vin +
–
~
1
sC

Fig. 58 All pass filter

1
Voltage at node b, Vb = sC Vin
1
R+
sC
1
⇒ Vb = Vin (222)
1 + s CR

1
For ideal op-amp, Va = Vb= . Vin (223)
1 + s CR
Applying KCL at node a, we have,
Va - Vin Va - Vo
+ = 0 (224)
R1 R1

⇒ Vo = 2Va – Vin (225)

Putting expression of Va from equation (223) in above equation, we have,

⇒ Vo = 2 × Vin - Vin (226)

1 CR

1 - s CR
⇒ Vo = . Vin (227)
1 + s CR

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [116]
Transfer function of the filter,
Vo 1 - s CR
⇒ = (228)
Vin 1 + s CR
The transfer function in frequency domain can be obtained by replacing s by jw in above
equation as under,
Vo 1 - jω CR
= (229)
Vin 1 + jω CR

Magnitude of transfer function or gain,

1 + ( ω CR )
2
Vo
= =1 (230)
Vin 1 + ( ω CR )
2

Phase shift provided by the filter is phase angle

Vo
∠ = –2 tan–1 ωCR (231)
Vin

It is observed from equation (230) and (231) that an all filter has unity gain and it proves a phase shift
in the signal. So, an all pass filter can be used for shifting the phase of input signal. The maximum
phase shift provided by an all pass filter is –180o.

Note : General Transfer function of second order filters

a
I. Second order low pass filter: H(s) = 2
s + bs + c
A second order low pass filter has no zeros and two poles located on negative real axis.
as 2
II. Second order high pass filter: H(s) = 2
s + bs + c
A second order high pass filter has two zeros at origin and two poles located on negative real
axis.
as
III. Second order band pass filter: H(s) = 2
s + bs + c
A second order band pass filter has one zero at origin and two poles located on negative real
axis.
as + b
IV. Second order band reject filter: H(s) = 2
s + cs + d

A second order band reject filter has one zero on negative real axis and two poles located on
negative real axis.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [117]
Example 70
For the circuit of figure with an ideal operational amplifier, the maximum phase shift of the output
Vout with reference to the input Vin is

R1 R1
–
Vin VOut
+
R
C

(a) 0o (b) – 90o

(c) + 90 (d) + 180o
GATE(EE/2003/1M)
Solution : Ans.(d)
R1

R1
–
a
Vin b + Vout
R

1
Voltage at node ‘b’, Vb = ·Vin
1 + jωRC

For ideal Op-amp, V– = V+

1
∴ Va = ·Vin
1 + jωRC

Applying KCL at node ‘a’, we have

Va - Vin Va - Vout
+ =0
R1 R1

⇒ Vout = 2Va – Vin

 2 
⇒ Vout =  - 1 Vin
1 + jωRC 

Vout 1 - jωRC
=
Vin 1 + jωRC

∠(Vo/Vin) = – 2tan–1 ωRC

Max value of tan–1 ωRC = ± 90°
So maximum phase shift provide by given circuit is ± 180°

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [118]
Example 71
For the circuit shown in the figure, R1 = R2 = R3 = 1 Ω, L = 1 µH and C = 1 µF. If the input Vin =
V 
cos(106 t), then the overall voltage gain  out  of the circuit is .........
 Vin 

L R1
R3
–
– Vout
+ R2 C
+
Vin ~

GATE(EC-III/2016/2M)
Solution : Ans. (–1.0)
R1
R3
jL
– R2 1/jC
(1) –
+ Vo1 C (2) Vout
+
Vin ~

Output voltage of Op-amp 1,
 R 
Vo1 = 1 + 1  Vin .....(i)
 j ωL 

R3
Output voltage Op-amp 2, Vout = × Vo1
1
R2 +
j ωC
Putting expression of Vo1 from (i) in above equation, we have,

R3  R 
Vout = - × 1 + 1  × Vin .....(ii)
1  j ωL 
R2 +
jωC
Given, Vin = cos 106 t = cos wt
where, w = 106 rad/s
For the given circuit, R1 = R2 = R3 = 1Ω, C = 1µF, L = 1µH.
Putting above values in equation (ii), we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [119]

1  1 
Vout = - × 1 + -6 
× Vin
1 
6
j10 × 1 × 10 
1+
j106 × 1 × 10-6

⇒ Vout = –Vin
Vout
⇒ = –1
Vin

12 Non-linear Applications of Op-Amp

These are the applications in which output of the operational amplifier is not a linear function of input
signal. The applications include rectifier and comparator circuits. These are small signal applications
in which peak value of input signal is few millivolts.
12.1 Half Wave Rectifier
The rectifier operation can be performed by using op-amp when the signals are having amplitude
up to few millivolts. The half wave rectifier operation can be performed in inverting as well as non-
inverting modes. The rectification operation can be also be performed on positive as well as negative
half of input signal.
Case-I : Non-inverting mode:
In this mode the input signal is applied at non-inverting input terminal of op-amp. A diode is connected
at output terminal of the diode. The non-inverting mode can be used to perform positive as well as
negative half rectifier which as discussed as follows,
I. Positive Half Wave Rectifier

Fig. 59a shows the circuit diagram of a positive half wave rectifier. During positive half cycle of input
signal, the voltage at output terminal ‘o’ of op-amp is positive and the diode D is forward biased.
When diode D is forward biased, it acts like a closed switch and the circuit behaves like a voltage
follower with output voltage same as input voltage. During negative half cycle of input voltage, the
voltage at terminal ‘o’ of op-amp is negative and the diode D is reverse biased and output voltage is
zero. Fig. 59b shows the waveforms of input and output signals of positive half wave rectifier.
Vin

– o Vo
Vin Vo
+ D
RL D is ON D is OFF D is ON

t
(a) Positive half wave rectifier (b) Input and output signal waveforms
Fig. 59 Positive half wave rectifier in non-inverting mode and input & output signals

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [120]
Voltage Transfer Characteristic:
It is observed from waveforms of input and output signals of positive half wave rectifier in non-
inverting mode that output is same as input signal for positive half and it is zero for negative half
cycle. So, the voltage transfer characteristics can be drawn as shown in Fig. 59c.
Vo

Vm

 Vm Vm Vi

Vm

Fig. 59c Voltage transfer characteristics of positive half wave rectifier in non-inverting mode

II. Negative Half Wave Rectifier

Fig. 60a shows the circuit diagram of a negative half wave rectifier. During negative half cycle of
input signal, the voltage at output terminal ‘o’ of op-amp is negative and the diode D is forward
biased. When diode D is forward biased, it acts like a closed switch and the circuit behaves like
a voltage follower with output voltage same as input voltage. During positive half cycle of input
voltage, the voltage at terminal ‘o’ of op-amp is positive and the diode D is reverse biased and output
voltage is zero. Fig. 60b shows the waveforms of input and output signals of negative half wave
rectifier.

Vin

Vo
– o Vo
D is OFF D is ON D is OFF D is ON
Vin
+ D t
RL

(a) Negative half wave rectifier (b) Input and output signal waveforms

Fig. 60 Negative half wave rectifier in non-inverting mode and input & output signals

Voltage Transfer Characteristic:

It is observed from waveforms of input and output signals of negative half wave rectifier in non-
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [121]
inverting mode that output is same as input signal for negative half and it is zero for positive half
cycle. So, the voltage transfer characteristics can be drawn as shown in Fig. 60c.
Vo

Vm

 Vm

Vm Vi

Vm

Fig. 60c Voltage transfer characteristics of negative half wave rectifier in non-inverting mode

Case-II : Inverting Mode

Fig. 61a shows the circuit diagram of a inverting mode half wave rectifier using op-amp. During
negative half cycle of input signal, the voltage at output terminal ‘o’ of op-amp is positive and the
diode D1 is reverse and diode D2 is forward biased and circuit works like an inverting amplifier.
During positive half cycle of input voltage, the voltage at terminal ‘o’ of op-amp is negative and
the diode D1 is forward and diode D2 is reverse biased. As there is no current through RF under this
condition so output terminal is also at virtual ground and the output voltage is zero. Fig. 61b shows
the waveforms of input and output signals of the inverting mode half wave rectifier. The diode D1 is
used to avoid saturation of op-amp.

Vin

t
RF

D1 Vo
Vin R1 D1 ON D1 OFF D1 ON D1 OFF
– D2 Vo D2 OFF D2 ON D2 OFF D2 ON

+ o t

(a) Inverting mode half wave rectifier (b) Input and output signal waveforms
Fig. 61 Inverting mode half wave rectifier and input & output signal waveforms

Voltage Transfer Characteristic:
It is observed from waveforms of input and output signals of negative half wave rectifier in inverting
mode that output is inverted version of input signal for negative half and it is zero for positive half
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [122]
cycle. So, the voltage transfer characteristics for inverting mode half wave rectifier can be drawn as
shown in Fig. 61c.
Vo

Vm

 Vm Vm Vi

Vm

Fig. 61c Voltage transfer characteristics of negative half wave rectifier in inverting mode

Example 72
The cut-in voltage of the diodes in the rectifier of figure is 0.6 V
10 k

Vo

10k 20 k
Vi –

Identify the correct output characteristic (Vo vs Vi)

V0
V0
(a) Slop-2 (b)

Vi

Vi Slop = – 1

V0
(c) V0 Slop = 1
(d)

0.6 V
Vi
0.6 V Vi
Slop = – 1

GATE(IN/1993/1M)
Solution : Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [123]
Vin

t
10 k

Vo

10k 20 k
Vi – D1 D2

+
t

Given circuit is a precision half wave rectifier in inverting mode.
Case-I : When input is positive the output is negative. The diode D1 is OFF and diode D2 is ON. So,
equivalent circuit becomes as under.
10 k

Vo

10k 20 k D2
D1
Vi –

10
Vo = - Vi = – Vi
10

Case-II : When input is negative the output is positive. The diode D1 is ON and D2 is OFF. The circuit
becomes as under.
10 k

Vo

10k 20 k D2
D1
Vi –
‘a’
+

As D2 is open so, Vout = Va =0V

The transfer characteristics of circuit can be drawn as under,
Vo

Vi

slope = –1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [124]
Example 73
The transfer characteristic for the precision rectifier circuit shown below is (assume ideal op-amp and
practical diodes)
+20V
R

4R
D2
Vi –
R Vo
+ D1

Vo
Vo

10
(a) (b) 5

Vi
Vi –10 –5 0
–10 –5 0

Vo Vo

10
(c) (d)
5

Vi Vi
0 +5 +5
0

GATE(EC/2010/2 M)
Solution : Ans.(b)
+20V
R

4R
D2
Vi –
R Vo
+ D1

The given circuit is a half wave rectifier. The circuit gives zero output during positive half cycle
because input is given to inverting input. The equivalent circuit during negative half cycle will be as
shown,
+20V R
4R

Vi –
R (a) Vo
+

Applying KCL at node a, we applying

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [125]

0 - 20 0 - Vi 0 - Vo
+ + =0
4R R R

Vo =-5 - Vi

The transfer characteristics of the circuit can drawn by using above equation as under,
Vo

+5V

–10V –5V Vi

–5V

Example 74
In the circuit given below, the diodes D1 and D2 have a forward voltage drop of 0.6 V. The op-amp
used is ideal. The magnitude of the negative peak value of the output Vo in volt is ..........
16k

D2
10k
– D1
1 sin
(3000t)V
~ + V0

GATE (IN/2016/1M)
Solution : Ans.(1.55 to 1.65)
16k

D2
10k
– D1
1 sin
(3000t)V
~ + V0

The given circuit is a rectifier which rectifies the positive half cycles. The circuit is an inverter so
the positive half cycle of input becomes negative at output. The output of the circuit remains zero
for negative half cycle. The output of op-amp becomes -vsat as soon as input becomes positive and
it turns on the diode D1 and turns off the diode D2. Thus, the circuit behaves like an inverter circuit
during positive half cycle of input with gain of -(16/10).
The magnitude of negative peak of output signal can be given by,
Vomax = (16/10) ×1 = 1.6 V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [126]
12.2 Full Wave Rectifier
Fig. 62 shows the circuit diagram of a full wave rectifier using an op-amp. The full wave rectifier
consists of two op-amps both connected in inverting mode.

R R R
Vin R
– D1 – Vo
+
+
D2

R
Fig. 62 Full wave rectifier using op-amp
The operation of the circuit as full wave rectifier can be explained by considering positive and
negative half cycles of input signal separately as follows,

Case-I : Positive half cycle

During positive half cycle of input signal the diode D1 is ON and diode D2 is OFF. Thus the diode
D1 behaves like a closed switch and diode D2 behaves like an open switch during positive half cycle.
The equivalent circuit of the rectifier during positive half cycle can be drawn as shown in Fig. 63.
R R R
V
Vin R
– – Vo
+ 1 + 2

V= 0
R
Fig. 63 Equivalent circuit of full wave rectifier during positive half cycle.
Voltage at inverting terminal of op-amp 1,
V- = V+ = 0 (232)
Since, bias current entering in inverting and non-inverting terminals of ideal op-amp is zero so the
voltage at non-inverting terminal of op-amp 2 is same as voltage at inverting terminal of op-amp 1.
∴ V′′ = 0 (233)
The op-amp 1 is connecting in inverting configuration with output voltage,

R
V′ = - Vin =
- Vin (234)
R

The op-amp 2 is connected in differential configuration with output voltage,

R  R
Vo = - V ′ + 1 +  V ′′ = - V′ + 2 V′′ (235)
R  R

Putting expressions of V′′ and V′ from equations (233) and (234) in above equation, we have,
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [127]
Vo = – (–Vin) + 2 × 0 = Vin (236)

Case-II : Negative half cycle

During negative half cycle of input signal the diode D1 is OFF and diode D2 is ON. Thus the diode
D1 behaves like an open switch and diode D2 behaves like a closed switch during negative half cycle.
The equivalent circuit of the rectifier during negative half cycle can be drawn as shown in Fig. 64.

R R b R
V
Vin R
– – Vo
a + 1 + 2

V
R
Fig. 64 Equivalent circuit of full wave rectifier during negative half cycle
Both opamps are assumed to be ideal and for an ideal opamp , V- = V+
∴ Voltage at node ‘b’, Vb = V′′
∴ Voltage at node ‘a’, Va = 0
Applying KCL at node ‘a’, we have,

0 - Vin 0 - V ′′ 0 - V ′′
+ + = 0
R 2R R
3
⇒ V ′′ = –Vin (237)
2

2
⇒ V′′ = - Vin (238)
3

The output voltage of op-amp 2,

 R  3
⇒ Vo =  1 + V=′′ V ′′ (239)
 2R  2

Putting expression of V’’ from equation (238) in above equation, we have,

Vo = – Vin (240)

It is observed from equations (240) the the output signal is inverted version of input signal during
negative half cycle of input voltage and it is same is input voltage during positive half cycle. Thus,
the circuit works like a full wave rectifier with waveforms of input and output signals as shown in
Fig. 65.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [128]
Vin

Vo

D1 ON D1 OFF D1 ON D1 OFF
D2 OFF D2 ON D2 OFF D2 ON
t

Fig. 65 Waveforms of input and output signals of full wave rectifier
Voltage Transfer Characteristic:
It is observed from waveforms of input and output signals of full wave rectifier that output is same
as input signal during positive half cycle and it is inverted version of input signal for negative half
cycle. So, the voltage transfer characteristics of full wave rectifier can be drawn as shown in Fig. 65b.
Vo
Vm

 Vm Vm Vi

Vm

Fig. 65b Voltage transfer characteristics of full wave rectifier

Example 75
The block diagrams of two types of half wave rectifiers are shown in the figure. The transfer
characteristics of the rectifiers are also shown within the block.

P
Q
V0 V0
Vin V0 Vin V0
0 Vin
Vin
t 0

It is desired to make full wave rectifier using above two half-wave rectifiers. The resultant circuit will
be

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [129]
R
R
R
R Vin P –
Vin P – +
Vo
Vo Q
Q + R
R
R
(a) (b)

R R R
R
Vin Q 
 Vo –
P R Vo
R P +
R
Vin
Q
(c) (d) R
GATE (EE/2008/2 M)
Solution : Ans.(b)

P
Q
V0 V0
Vin V0 Vin V0
0 Vin
Vin
t 0

Transfer characteristics of full wave rectifier can be drawn as under, :

Vo

Vin

Characteristics of rectifier Q are same as second quadrant of characteristic of full wave rectifier. So,
second quadrant of full wave rectifier can be realized by connecting Q at non inverting terminal of
op-amp. The first quadrant of full wave rectifier is inverted version of characteristics of half rectifier
P. So, first quadrant of full wave rectifier can be realized by connecting P at inverting terminal of op-
amp. Thus full wave rectifier can be realized with half wave rectifier P & Q by using the circuit given
below,
R

R
Vin P –
+
Vo
Q
R
R

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [130]
12.3 Peak Detectors
The peak detector circuits are used to find positive as well as negative peak value of a voltage signal.
There are two types of peak detector circuits called positive and negative peak detectors.
Case-I : Positive Peak Detector
Fig. 66a shows the circuit diagram of a positive peak detector. When input voltage is positive the
diode D is forward biased and behaves like a closed switch and circuit works like a voltage follower.
The output voltage of the circuit is same a input voltage. The capacitor gets charged to peak value of
input voltage if voltage falls below the peak value the diode gets reverse biased and capacitor holds
the last peak value of input signal. The waveforms of input and output signals are shown in Fig. 66b.
Vin

Vo
– D
Vin Vo
+

t
(a) Positive peak detector (b) Waveforms of input and output signals

Fig. 66 Positive peak detector and its input and output signals

Case-II : Negative Peak Detector

Fig. 67a shows the circuit diagram of a negative peak detector. When input voltage is negative, the
diode D is forward biased and behaves like a closed switch and circuit works like a voltage follower.
Vin

Vo

– D Vo
Vin t
+

(a) Negative peak detector (b) Waveforms of input and output signals
Fig. 67 Negative peak detector and its input and output signals

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [131]
The output voltage of the circuit is same a input voltage. The capacitor gets charged to peak value of
input voltage if voltage falls below the peak value the diode gets reverse biased and capacitor holds
the last peak value of input signal. The waveforms of input and output signals are shown in Fig. 67b.
12.4 Clippers using op-amp
The clipping circuits are used to clip a voltage waveform at a reference level. These circuits can be
used to clip positive as well as negative peaks of a signal at positive as well as negative reference
level.
I. Negative peak clipper with negative reference
Fig. 68a shows the circuit diagram of negative peak clipper with negative reference voltage. The
negative reference voltage is obtained from negative power supply (-VEE) of op-amp by connecting
a potentiometer as shown in the Fig. 68a. The waveforms of input and output voltages of negative
peak clipper with negative reference are shown in Fig. 68b.
Vin
Vm

t
+VCC –Vref
D
– Vo
Vo
+ RL
–VEE
Vin

+ –Vref t
–Vref
Potentiometer – –Vm

(a) Negative peak clipper with negative reference (b) Input and output voltage waveforms

Fig. 68 Negative peak clipper with negative reference and input & output signal waveforms

Case-I : When Vin > – Vref
When input voltage is positive or less negative than -Vref , the diode is forward biased and diode
behaves like a closed switch and circuit behaves like a voltage follower. Thus, output voltage is same
as input voltage for Vin > – Vref as shown in Fig. 68b.
∴ Vo = Vin

Case-II : When Vin < – Vref

When input voltage is more negative than -Vref , the diode is reverse biased and diode behaves like
an open switch. In such case voltage at output terminal of the circuit is same as reference voltage.
∴ Vo = Vref

II. Negative peak clipper with positive reference
Fig. 69a shows the circuit diagram of negative peak clipper with positive reference voltage. The
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [132]
positive reference voltage is obtained from positive power supply (+VCC) of op-amp by connecting a
potentiometer as shown in the Fig. 69a. The waveforms of input and output voltages of negative peak
clipper with positive reference are shown in Fig. 69b.
Vin
Vref

0 t
–VEE
D
– Vo
Vo
+ RL
+VCC Vref
Vin
0 t
+
Vref
Potentiometer –

(a) Negative peak clipper with positive reference (b) Input and output voltage waveforms

Fig. 69 Negative peak clipper with positive reference and input & output signal waveforms

Case-I : When Vin > Vref

When input voltage is more than Vref , the diode is forward biased and diode behaves like a closed
switch and circuit behaves like a voltage follower. Thus, output voltage is same as input voltage for
Vin > Vref as shown in Fig. 69b.

∴ Vo = Vin

Case-II : When Vin < Vref

When input voltage is less than Vref , the diode is reverse biased and diode behaves like an open
switch. In such case voltage at output terminal of the circuit is same as reference voltage.

∴ Vo = Vref

III. Positive peak clipper with negative reference
Fig. 70a shows the circuit diagram of positive peak clipper with negative reference voltage. The
negative reference voltage is obtained from negative power supply (-VEE) of op-amp by connecting
a potentiometer as shown in the Fig. 70a. The waveforms of input and output voltages of positive
peak clipper with negative reference are shown in Fig. 70b.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [133]
Vin
Vm

0
+VCC t
D –Vref
– Vo
Vo
+ RL
–VEE
Vin

+ 0
–Vref
t
Potentiometer
– –Vref
–Vm
(a) Positive peak clipper with negative reference (b) Input and output voltage waveforms

Fig. 70 Positive peak clipper with negative reference and input & output signal waveforms

Case-I : When Vin > – Vref

When input voltage is positive or less negative than -Vref , the diode is reverse biased and diode
behaves like an open switch. In such case voltage at output terminal of the circuit is same as reference
voltage.

∴ Vo = -Vref

Case-II : When Vin < – Vref

When input voltage is more negative than -Vref , the diode is forward biased and diode behaves like
a closed switch and circuit behaves like a voltage follower. Thus, output voltage is same as input
voltage for Vin < – Vref as shown in Fig. 70b.

∴ Vo = Vin

IV. Positive peak clipper with positive reference

Fig. 71a shows the circuit diagram of positive peak clipper with positive reference voltage. The
positive reference voltage is obtained from positive power supply (+VCC) of op-amp by connecting a
potentiometer as shown in the Fig. 71a. The waveforms of input and output voltages of positive peak
clipper with positive reference are shown in Fig. 71b.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [134]
Vin
Vm
Vref
0 t
–VEE
D
– Vo
Vo
+ RL
Vin +VCC
Vref
+ 0 t
Vref
Potentiometer –
–Vm
(a) Positive peak clipper with positive reference (b) Input and output voltage waveforms

Fig. 71 Positive peak clipper with positive reference and input & output signal waveforms

Case-I : When Vin > Vref
When input voltage is more than Vref , the diode is reverse biased and diode behaves like an open
switch. In such case voltage at output terminal of the circuit is same as reference voltage.
∴ Vo = Vref

Case-II : When Vin < Vref

When input voltage is less than Vref , the diode is forward biased and diode behaves like a closed
switch and circuit behaves like a voltage follower. Thus, output voltage is same as input voltage for
Vin < Vref as shown in Fig. 71b.
∴ Vo = Vin

V. Two Level Clipper Using Zener Diode

A two level clipper circuit can be implemented using an op-amp and Zener diode by connecting series
combination of Zener diodes across load at output terminals of a unity follower circuit as shown in
Fig. 72. When magnitude of input voltage is between - (Vz + VD) and (Vz + VD), none of the diodes
work in breakdown region and combination of diodes work like open circuit because either of the
diodes is reverse biased, so the output voltage is same as input voltage. When input voltage is more
negative than - (Vz + VD), the diode D1 is reverse biased and works in breakdown region and D2 is
forward biased and output voltage is clipped at - (Vz + VD). When input voltage is more than +(Vz +
VD), the diode D1 is forward biased and Diode D2 is reverse biased and works in breakdown region
and output voltage is clipped at +(Vz + VD).

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [135]
Vin

(Vz+ VD)

–(Vz+ VD) t

– Vo
 Vo
+
+ V+z D1 VD +VZ + VD
+ 
~V
– in

VD
+
+
D2 Vz t
 –(Vz+ VD)

(a) Two level clipper (b) Waveforms of input and output signals
Fig. 72 Two level clipper and its input and output signals.

13 Logarithmic amplifier
A log amplifier is used to perform logarithmic operation on input signal. These are used in digital
voltmeters and spectrum analyzers. The log amplifiers can be implemented by using diode as well
as BJT.
Case-I : Lag amplifier using diode
A log amplifier is implemented by using inverting configuration of op-amp with the diode connected
in the feedback path as shown in Fig. 73. Let ID is current and VD is voltage drop across the diode.
ID
Vin R + VD –
a – Vo
+

Fig. 73 Log amplifier using a diode

Applying KCL at node a, we have,
Va - Vin
+ I D = 0 (241)
R

For ideal op-amp, Va = V+ = 0

Vin
⇒ ID = (242)
R

The diode current is given by,

VD
η VT
ID = Is (e - 1) (243)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [136]
where, Is is reverse saturation current of the diode, VT is thermal voltage and η is ideality factor of
diode.
Voltage across diode, VD = –Vo (244)
where, Vo is output voltage of the circuit.
- Vo
Vin
⇒ Is (e η VT - 1) = (245)
R

- Vo
Vin
⇒ e η VT = 1 + (246)
Is R

 V 
⇒ –Vo = η VT ln 1 + in 
 Is R 

 V 
⇒ Vo = -η VT ln 1 + in  (247)
 Is R 
As the reverse saturation current of diode is very small in the range of nano-amperes.
Vin Vin
So, 1+ ≈ (248)
Is R Is R

 Vin 
⇒ Vo ≈ -η VT ln   (249)
 Is R 

It is observed from above equation that the output voltage is log operation of input voltage. Thus
given circuit performs the log operation.

Case-II : Log amplifier using BJT

A log amplifier can be implemented by using a BJT by using inverting configuration of op-amp with
the BJT connected in feedback path. The base terminal of BJT is grounded as shown in Fig. 74. Let
IC is collect and VBE is base to emitter junction voltage of BJT.
IC IE  IC
_
Vin R +
VBE
– Vo
+

Fig. 74 Log amplifier using a BJT
The collector current of BJT is given by,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [137]
VBE
V
IC = Is e T (250)

Where Is is saturation current of BJT.

It is observed from the circuit of Fig. 73 that the output voltage of log amplifier is same as negative
of base to emitter of BJT.
∴ VBE = -Vo (251)
Putting above expression of VBE in equation (250), we have,
- Vo
VT
IC = Is e (252)

For ideal op-amp, V- = V+ = 0

The bias current of ideal opamp is zero so the collector current of BJT is same as current
supplied by the source.
V -V Vin - 0 Vin
So, IC = in=-
= (253)
R R R

Putting above relation of IC in equation (258), we have,

- Vo
Vin V
= Is e (254)
T

R
V 
⇒ Vo = - VT ln  in  (255)
 Is R 

Example 76
Consider the following circuit using an ideal op-amp. The I-V characteristics of the diode is described
=
by the relation I Io ( e V/ VT - 1) where VT = 25 m V, Io = 1 µ A and V is the voltage across the diode

(taken as positive for forward bias).

D 4K

Vi = –1V – +
–
100K Vo
+

For input voltage V1 = – 1 V, the output voltage Vo is

(a) 0 V (b) 0.1 V
(c) 0.7 V (d) 1.1 V
GATE(EC/2008/2M)
Solution : Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [138]
– VD +
I

D 4k Vo
100k
–
Vi= –1V a
+

For ideal op-amp,

V– = V+
Va = 0
KCL at node ‘a’,
0 - (-1)
– I = 0
100

1
⇒ I = mA
100

(
I = Io eVD /VT - 1 )
Given, Io = 1µA, VT = 25 mV

-6
∴ 1 × 10 e D(
V /25×10 -3
-1 = ) 1
100
× 10-3

-3
⇒ e VD /25×10 = 11

VD
⇒ = n 11
25 × 10-3

⇒ VD = 0.0599 V
voltage across diode,
VD = Vo – 4I

103
⇒ Vo = VD + 4I = 0.0599 + 4 × × 10-3 = 0.1 V
100

14 Sample and Hold circuit

The sample and hold circuit samples the input signal and holds its last sampled value of input signal
is sampled again. Fig. 75a shows the circuit of a sample and hold circuit. The n-channel MOSFET
is used as a controlled switch which is controlled by control voltage Vc. The capacitor C is used to
hold the last sampled value of the input signal. When control signal is high, the MOSFET is ON and
the output signal is same as input signal. When control signal is low, the MOSFET is OFF and the

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [139]
capacitor holds last sampled value of the input signal. Fig. 75b shows the waveforms of input, output
and control signals of sample and hold circuit.
Vin

Vc

Vo
–
Switch
t
–
V + sample hold sample hold
period period period period
Vin + Vo
C

Vc
t

(a) Sample and hold circuit (b) Input and output voltage signals
Fig. 75 Sample and hold circuit and its input and output signals

15 Comparators
A compare circuit is used to compare an unknown signal with a known signal called reference
signal. Op-amp can be used as a comparator by applying unknown signal at one input terminal and
reference signal at another input terminal. The comparator circuits can be used in inverting as well
as non-inverting modes with either positive or negative reference voltage. The comparator circuits
are mostly used a voltage level detectors or Schmitt triggers.

Case-I : Inverting Mode

The unknown signal source is connected at inverting terminal and reference voltage source is
connected at non-inverting terminal in inverting mode operation of comparator. The reference
voltage can be either positive or negative depending on application.

A. Positive Reference
Inverting mode comparator with positive reference voltage is shown in Fig. 76a. The input and
output signals of inverting mode comparator with positive reference are shown in Fig. 76b. The
output of op-amp is +Vsat when input voltage is less than the reference voltage and it becomes -Vsat
as soon as input voltage becomes more than the reference voltage.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [140]
Vin

Vref

0
t

Vo
R1
+Vsat
– Vo
Vin ~
+ 0
R2 t
Vref
–Vsat

(a) Inverting mode comparator with positive reference (b) Input and output voltage signals
Fig. 76 Inverting mode comparator with positive reference and its input and output signals

B. Negative Reference
Inverting mode comparator with negative reference voltage is shown in Fig. 77a. The input and
output signals of inverting mode comparator with negative reference are shown in Fig. 77b. The
output of op-amp is +Vsat when input voltage is more negative than the reference voltage and it
becomes -Vsat as soon as input voltage becomes positive or less negative than the reference voltage.

Vin

Vref t

R1 Vo
– +Vsat
Vo
Vin ~
+
R2 t
Vref
–Vsat

(a) Inverting mode comparator with negative reference (b) Input and output voltage signals

Fig. 77 Inverting mode comparator with negative reference and its input and output signals

Case-II : Non-inverting Mode

The unknown signal source is connected at non-inverting terminal and reference voltage source
is connected at inverting terminal in non-inverting mode operation of comparator. The reference
voltage can be either positive or negative depending on application.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [141]
A. Positive Reference
Non-inverting mode comparator with positive reference voltage is shown in Fig. 78a. The input and
output signals of non-inverting mode comparator with positive reference are shown in Fig. 78b. The
output of op-amp is +Vsat when input voltage is more than the reference voltage and it becomes -Vsat
as soon as input voltage becomes less than the reference voltage.
Vin

Vref

0
t
R1 Vo
– Vo +Vsat
Vref
+
R2 0
+ t
Vin ~ –
–Vsat

(a) Non-inverting comparator with positive reference (b) Input and output signals
Fig. 78 Non-inverting mode comparator with positive reference and its input and output
signals
B. Negative Reference
Non-inverting mode comparator with negative reference voltage is shown in Fig. 79a. The input and
output signals of non-inverting mode comparator with negative reference are shown in Fig. 79b. The
output of op-amp is +Vsat when input voltage is positive or less negative than the reference voltage
and it becomes -Vsat as soon as input voltage becomes more negative than the reference voltage.
Vin

Vref t
R1
Vo
– Vo +Vsat
Vref
+
R2
+ t
Vin ~ –
–Vsat

(a) Non-inverting comparator with negative reference (b) Input and output voltage signals
Fig. 79 Non-inverting mode comparator with negative reference and its input and output
signals
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [142]
15.1 Zero Crossing Detector
A zero crossing detector is a comparator circuit with zero reference voltage. A zero crossing detector
can work in inverting as well as non-inverting mode like a comparator.
Case-I : Inverting Mode
The unknown signal source is connected at inverting terminal with non-inverting terminal connected
to ground through a resistance in inverting mode. Fig. 80 shows the circuit diagram and waveforms
of input and output voltages of zero crossing detector in inverting mode.
Vin
Vm

t
Vm
Vo
Vsat

R1
+ – Vo t
Vin ~
– +
Vsat
R2

(a) Inverting mode comparator with positive reference (b) Input and output voltage signals
Fig. 80 Inverting mode zero crossing detector and its input and output signals
Case-II : Non-inverting Mode
The unknown signal source is connected at non-inverting terminal with inverting terminal connected
to ground through a resistance in non-inverting mode. Fig. 81 shows the circuit diagram and
waveforms of input and output voltages of zero crossing detector in non-inverting mode.
Vin
Vm

R1 Vm
Vo
– Vsat
Vo
+
R2
+ t
~ V
– in
Vsat
(a) Non-inverting comparator with positive reference (b) Input and output voltage signals
Fig. 81 Non-inverting mode zero crossing detector and its input and output signals
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [143]
Example 77
If the input to the ideal comparator shown in figure is a sinusoidal signal of 8V (peak to peak) without
any DC component, then the output of the comparator has a duty cycle of

Input +
Output
Vref = 2 V –
(a) 1/2 (b) 1/3
(c) 1/6 (d) 1/12
GATE(EC/2003/1M)
Solution : Ans.(b)
Given circuit is non-inverting comparator.
Input
(Vin) +
Output
– (Vo)
Vref = 2V

Given, peak-to-peak input voltage = 8V

Waveforms,
Vin
+4V

+2V

2 t
1 2
–2V

–4V
Vo
2
+Vsat
ON FF

t
–Vsat

When ; Vin < 2V, Vo = – Vsat

Vin > 2V, Vo = + Vsat
At ωt = θ1, Vin = 2V
⇒ 4 Sin θ1 = 2V
π
θ1 = 30° =
6

π 5π
θ2 = π - θ1 = π - =
6 6

5π π 2 π
θON = θ2 – θ1 = – =
6 6 3
θON 2π / 3 1
Duty cycle of output = = =
2π 2π 3
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [144]

16 Schmitt Trigger
Schmitt trigger is a comparator circuit with positive feedback. So, it is also known as
regenerative comparator. The feedback voltage of the circuit acts like a reference voltage
of a comparator circuit. The input signal is applied at inverting terminal of the op-amp. A
Schmitt trigger can be used as a sine to square wave converter. Fig. 82 shows the circuit
diagram of a regenerative comparator. The resistance ROM = R1|| R2 is offset minimizing
resistance and it is used to minimize the offset voltage of the circuit.
Vin ROM
–
Vo
+
R2

+
Vref R1
–

Fig. 82 Schmitt trigger or regenerative comparator

R1
Feedback voltage, Vref = × Vo =
bVo (256)
R1 + R 2

R1
Where, β = (257)
R1 + R 2

The gain of the op-amp increases due to positive feedback. The open loop gain of op-amp is already
very high so further increase in gain due to positive feedback results in saturation of output of op-
amp. So, the output voltage of op-amp is either +Vsat or -Vsat depending upon the input voltage.
Case-I : Vo = +Vsat
Let initially, Vo = +Vsat

The reference feedback voltage,
Vref = + βVsat = VUT (258)

Where, VUT is called upper threshold.
It observed that if output of op-amp is initially saturated at +Vsat and the reference voltage of the
circuit becomes +bVsat. The output remains saturated at +Vsat till input voltage is less than +bVsat.
The output changes from +Vsat to -Vsat as soon as input becomes more than +bVsat or VUT .
Case-II : Vo = –Vsat
The moment output voltage becomes –Vsat , the reference feedback voltage becomes,
Vref = –β Vsatt = VLT (259)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [145]

Where, VLT is called lower threshold voltage.
The output remains saturated at –Vsat till input voltage is positive or less negative than –bVsat. The
output changes from -Vsat to +Vsat as soon as input becomes more negative than -bVsat or VLT . The
moment output voltage becomes +Vsat , the reference feedback voltage becomes +β Vsatt or VUT .

Above two cases keeps on repeating cyclically for a sinusoidal input signal. The waveforms of input
and output voltage of Schmitt trigger can be drawn as shown in Fig. 83.

Vin
+Vm
VUT

t
VLT
–Vm
Vo
+Vsat

T
T t
2
–Vsat

Fig. 83 Input and output signals of Schmitt trigger

Transfer Characteristic of Schmitt Trigger :
The variation of output voltage of Schmitt trigger with respect to input voltage is called transfer
characteristics. The transfer characteristics of Schmitt trigger is a hysteresis curve as shown in Fig.
84.

Vo
+Vsat

VLT VUT
Vin
–Vm +Vm

–Vsat

Fig. 84 Hysteresis characteristics of Schmitt trigger

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [146]
Hysteresis Voltage:
The difference between upper threshold and lower threshold voltages of Schmitt trigger is called
hysteresis voltage.
∴ Vhy = VUT − VLT (260)

Noise Margin:
It maximum noise which can be superimposed on input signal without affecting the output of Schmitt
trigger. The noise margin for a Schmitt trigger is given by,
Noise Margin = VUT − VLT (261)

Example 78
Given the ideal operational amplifier circuit shown in figure indicate the correct transfer characteristics
assuming ideal diodes with zero cut-in voltage.
+ 10V
–
vi v0
+
– 10V
2 k

0.5 k
2 k

+10V v0 +10V v0

–8V +5V –5V +8V

(a) –10V (b) –10V

+5V v0 +10 V v0

–5V +5V
v1 –5V +5V
v1

(c) –10 V (d) –5 V

GATE(EC/2005/2M)

Solution : Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [147]
+ 10V
Vin –
Vo
+
– 10V D1
2k
+
0.5 k D2
Vref 2 k
–
The circuit shown above is schmitt trigger
If Vo = + Vsat = + 10 V then D1 is ON & D2 is OFF
2
So, Vref = + × 10 = + 5V = VUT = Upper threshold voltage
4

If Vo = – Vsat = – 10V then D1 is OFF and D2 is ON

2
So, Vref = - × 10 = – 8 V = VLT = Lower threshold voltage
2.5

Waveforms :- Transfer characteristics :-

Vin
+10V v0
5V
t
–8V
–8V +5V
Vout
+10V
–10V t
–10V

Example 79
Figure (a) shows a Schmitt trigger circuit and figure (b) the corresponding hysteresis characteristics.
The values of VTL and VTH are
+15V +15V
–
+ vo
5 k –15V

vi + 10 k –15V V
– TL VTH

Fig. (a) Fig. (b)

(a) VTL = – 3.75, VTH + 3.75 V (b) VTL = – 1V, VTH = + 5V

(c) VTL = – 5V, VTH = + 15V (d) VTL = – 5V, VTH = + 5V
GATE(IN/2004/2M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [148]
Solution : Ans.(d)
+ 15V

–
Vo
+

– 15V
Vin
5k ‘a’ 10 k

For ideal Op-amp, V+ = V–

∴ Va = V+ = 0
KCL at node ‘a’,
0 - Vin 0 - Vo
+ = 0
5 10

Since opamp is having positive feedback,

Vo = ± Vsat = ± 15V
when, Vo = + 15
Vin 15
- =
5 10

Vin = VTL = – 7.5 V

when, V– = – 15
Vin 15
- = -
5 10

Vin = VTh = + 7.5V

Hysteresis characteristic,
+ 15V

– 15V VTH = + 7.5V

VTL = – 7.5V

Statement for Linked Answer Example 80 & 81

In the Schmitt circuit shown below, the Zener diodes have Vz (reverse saturation voltage) of 6 V and
VD (forward voltage drop) of 0.7 V.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [149]
+12V

+ – R
Vi
– +
+ Vo
R1 –
–12V

Vref
R2

+1.5V
Example 80
If the circuit has the input lower trip point (LTP) = 0 V, the value of R1 / R2 is given as
(a) 0.223 (b) 2.67
(c) 4.67 (d) ∞
GATE(IN/2006/2M)
Solution : Ans.(c)
+12V

+ – R
Vi
– +
+ Vo
R1 –
–12V

Vref
R2

+1.5V
The zener diodes at output of given limit the output voltage level at ±(Vz + VD) or ± 6.7 V.
The hysteresis of the Schmitt trigger are drawn as under,
Vout
+ (VZ + VD)

VUT
VLT Vin

 (VZ + VD)

Here, VUT is upper trip point voltage and VLT is lower trip point voltage. In the given circuit the output
voltage changes from +(VZ + VD) to −(VZ + VD) at upper trip point and from −(VZ + VD) to +(VZ +
VD) at lower trip point.
Vo - 1.5
Reference voltage, Vref = × R 2 + 1.5V
R1 + R 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [150]
At lower trip point,
Vo = −6.7 V
Given , voltage at lower trip point, VLT =Vref = 0V
-6.7 - 1.5
⇒ 0 = × R 2 + 1.5V
R1 + R 2

R1 82 67
= - 1= = 4.47
R2 15 15

Example 81
The input upper trip point (UTP) of the Schmitt trigger is
(a) 1.5 V (b) 2.1V
(c) 2.42 V (d) 6.7 V
GATE(IN/2006/2M)
Solution : Ans.(c)
Output voltage at upper trip point,
Vo = 6.7 V
The input voltage at upper trip point can be given as,
Vo - 1.5
VUT = Vref = × R 2 + 1.5V
R1 + R 2

6.7 - 1.5
⇒ VUT = + 1.5V
(R1 / R 2 ) + 1

6.7 - 1.5
⇒ VUT = + 1.5 = 2.45 V
67 / 15 + 1

Example 82
The input signal shown in the figure below is fed to a Schmitt trigger. The signal has a square wave
amplitude of 6 V p-p. It is corrupted by an additive high frequency noise of amplitude 8 V p-p.

+7V

+ 3V 8V
+1V
6V
–1V
– 3V

–7V

Which one of the following is an appropriate choice for the upper and lower trip points of the Schmitt

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [151]
trigger to recover a square wave of the same frequency from the corrupted input signal Vi?
(a) ± 8.0 V (b) ± 2.0 V
(c) ± 0.5 V (d) 0 V
GATE(IN/2007/2M)

Solution : Ans.(a)
Transfer characteristics of Schmitt trigger :
Vout

VHT

VLT Vin

VH

+7V

VTH + 3V 8V
+1V
6V
–1V
VTL – 3V

–7V

The effect of noise in the Schmitt trigger can be eliminated when the width of hysteresis band
(ie VH = VTH – VTL) is more the peak to peak value of noise voltage.
So, value upper and lower trip points should be at least equal to peak to peak noise voltage
The best choice meeting this criteria among given option is ± 8V.

Example 83
The output voltage (Vo) of the Schmitt trigger shown in figure swings between +15 V and –15V.
Assume that the operational amplifier is ideal. The output will change from + 15V to –15 when the
instantaneous value of the input sine wave is
10 sin (t) –
10 k V0
+
10 k

3 k
+2V
(a) 5 V in the positive slope only (b) 5 V in the negative slope only
(c) 5 V in the positive and negative slopes (d) 3 V in the positive and negative slopes
GATE(EE/2002/2 M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [152]
Solution : Ans.(a)
10 k
–
Vin=10 sin t V0
+
10 k
a
VR
3 k

+2V
Vo - 2
Voltage at node ‘a’, VR = × 3 + 2V
13

when, Vo = +15V
15 - 2
⇒ VR = × 3 + 2V = 5V
13

when, Vo = −15V
-15 - 2
⇒ VR = × 3 + 2V = −1.923V
13

wavefroms :
Vin

VR
t
–VR

Vo
+15V

t
–15V

Conclusion :
Output voltage changes its level from +15V to –15V when input voltage becomes more than +5V at
its positive slope only.

Example 84
In the circuit shown in figure the input voltage Vi is a symmetrical saw-tooth wave of average value
zero, positive slope and peak-to-peak value 20 V. The average value of the output, assuming an ideal
operational amplifier with peak to-peak symmetrical swing of 30 V, is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [153]
Vin –
Vo
+

10k
5k

(a) 5 V (b) 10 V
(c) –5 V (d) 7.5 V
GATE(IN/2005/2M)

Solution : Ans.(d)
Vin –
Vo
+

+ 10k
Vref 5k
–

5
Vref = × Vo
15

when, Vo = + 15, Vref = + 5V

when, Vo = – 15, Vref = – 5V
Vin
+10V
+5V
t
–5V T1 T1
–10V

Vout

+15V
T1 T
t
–15V

From input waveform for 0 < t < T

20
Vin(t) = × t – 10
T

At t = T1, Vin = + 5V
20
⇒ 5 = × T1 - 10
T
T1 3
⇒ =
T 4

Average output voltage,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [154]

T1 (T - T1 )
Voav = × 15 - × 15
T T

3  3
⇒ Voav = × 15 - 1 -  × 15 = 7.5 V
4  4

Example 85
The input-output characteristic of a Schmitt trigger has a hysteresis band of + 0.1 V. If the input
voltage is 5 sin (1000 πt), the delay between the corresponding zero cross-over points of the output
and input signals is
(a) 6.37 µs (b) 0.02 µs
(c) 63.7 µs (d) 2.0 µs
GATE(IN/2005/2M)
Solution : Ans.(a)
Vin –
Vo
+
R1

+
Vf R2
–

Vin
+5V
+0.1V
t
–0.1V
–5V
Vout
+Vgap
t
–Vsat
td

Given, Vin = 5 sin 1000 πt

The output of circuit changes it level when input becomes 0.1V in positive slope.
∴ Vin = 0.1 V at t = td
where td is delay time between zero crossover points of input and output signals.
⇒ 0.1 = 5 sin 1000 π td
1  0.1 
td = sin -1   = 6.37 µs
1000π  5 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [155]
Example 86
In the circuit shown in the figure, the switch S has been in Position 1 for a long time. It is then moved
to Position 2. Assume the Zener diodes to be ideal. The time delay between the switch moving to
Position 2 and the transition in the output voltage V0 is

+15 V +15 V
Position 1
– 1k Vo
Position 2 10 k
S 1 µF +
4.7 k 5V Zener diode
–15 V
-15 V
4.7 k 5V Zener diode

(a) 5.00 ms (b) 8.75 ms

(c) 10.00 ms (d) 13.75 ms
GATE(IN/2009/2M)
Solution : Ans.(b)

+15 V +15 V
Position 1 10 k a
– 1k Vo
Position 2 +
S vc(t) 1 µF
+
– 4.7 k 5V Zener diode
–15 V
15 V +
Vf 4.7 k 5V Zener diode
–

Above circuit has positive feedback from output terminal. When switch ‘S’ is connected at position
‘1’ the capacitor ‘C’ gets charged to +30V. The voltage at inverting terminal becomes +15 V and
output of opamp becomes − 15 V and the output voltage of circuit is limited to −5 V by Zener diode.
Then feedback voltage at non-inverting terminal,
4.7
Vf = × (-5) =-2.5V
4.7 + 4.7

When switch ‘S’ is moved to position ‘2’ the capacitor discharges with time constant, with time
constant,
RC = 104 × 10–6 = 10 msec.
The variation of voltage across capacitor after moving at positive ‘2’ is given by,
- t /RC
vc(t) = Vf – (Vf – Vi) e
Vf = final voltage across ‘C’ = 0V
Vi = initial voltage across ‘C’ = + 30V
t
-
10×10-3
∴ vc(t) = 30e
Voltage at node, va(t) = vc(t) − 15 V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [156]
t
-
10×10-3
⇒ va(t) = 30e − 15 V
The output changes from –15V to +15V when voltage at inverting terminal becomes more negative
than –2.5V. Let output voltage changes from –15V to +15V at t = t1.
Then, va(t1) = – 2.5 V
t1
-
10×10-3
⇒ –2.5 = – 15 + 30e
t1
-
10×10-3
12.5
⇒ e =
30

30
⇒ t1 = 10×10–3 n sec = 8.75 msec
12.5
17 Waveform Generators using Operational Amplifier
An operational amplifier can be used to generate waveforms by operating the op-amp circuit in
oscillating mode. The generation of sinusoidal signals using an op-amp will be dealt with separately
in chapters on oscillators. The square wave, triangular wave and pulse generator circuits are discussed
in the following sections.
17.1 Square Wave Generator or Astable Multivibrator
A square wave can be generated by using an op-amp with negative as well as positive feedback as
shown in Fig. 85. Square wave generator circuit is also known as free running oscillator or astable
multivibrator. It has two unstable states. The op-amp is operated in saturated region in a square wave
generator. The operation of astable multivitrator can be explained with the assumption that the op-
amp is initially saturated due to output offset voltage and positive feedback.

R
C
a – Vo
b + R2

+
Vref R1
–

Fig. 85 Astable multibirator or square wave generator

R1
Feedback voltage, Vref = × Vo =
bVo (262)
R1 + R 2

R1
where, β = (263)
R1 + R 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [157]
The output of op-amp is either +Vsat or –Vsat because of positive feedback. Assuming the steady state
operation.
+ R1
When Vo = +Vsat ; Vref = . Vsat = + βVsat (264)
R1 + R 2

As soon as the output voltage becomes +Vsat, the capacitor starts charging and when the capacitor
voltage becomes more than + βVsat , the output of op-amp changes to -Vsat .
- R1
When, Vo = –Vsat ; Vref = . Vsat = – β Vsat (265)
R1 + R 2

As soon as the output voltage becomes -Vsat, the capacitor first discharges and then starts charging in
opposite direction and when the capacitor voltage becomes more negative than – βVsat , the output
of op-amp changes to +Vsat .
Above cycle of charging and discharging of capacitor keeps on repeating, resulting in square wave
at output of op-amp. T
he waveforms of output voltage and voltage across capacitor are as shown in
Fig. 86.
Vo
capacitor voltage (vc)

Vsat
Vsat
T
T/2
t
Vsat
Vsat

Fig. 86 Waveforms of output signal of astable multivibirator
Expression of voltage across a capacitor, for the period 0 < t < T/2 , is given by,
-t

vc(t) = V∞ – (V∞ – Vo+) e RC (266)

Where, V∞ is steady state value at t = ∞ , Vo + is voltage at t = 0+.
Here, V∞ = + Vsat
Vo + = – βVsat
-t

⇒ vc(t) = Vsat – (Vsat + β Vsat) e RC (267)

At t = T/2, vc(T/2) = βVsat
-T

⇒ βVsat = Vsat – (Vsat + β Vsat) e 2 RC

(268)
-T
1- b
⇒ e 2 RC
=
1+ b
1+ b
⇒ T = 2 RC ln (269)
1- b

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [158]
Example 87
The circuit shown in figure is that of waveform generator. Assuming ideal devices, and +12 V supply,
the output V0 is a

10k
+ 12V
–
Vo
1µF + 500
– 12V
6V

10k 6V
10k

(a) triangular wave of period 120 ms and amplitude + 6V

(b) square wave of period 60 ms and amplitude + 6 V
(c) square wave of period 120 ms and amplitude + 6 V
(d) square wave of period 60 ms and amplitude + 12 V
GATE(IN/2003/2M)
Solution : Ans.(b)
R=10k

1F +12V
– 500
C Vo
+ 6V
–12V R2
6V

10k
R1 10k

The figure shown above is a square wave generator. The level of output voltage is clipped off at ± 6
V by Zener diodes. The time period of wave is given by,
1 + b 
T = 2RC n  
1 - b 

R1 10
where, β = = = 0.5
R1 + R 2 10 + 10

⇒ T = 2 × 10 × 103 × 1 × 10–6 n3 = 21.97 msec

17.2 Pulse Stretcher or Monostable Multivibrator

A monostable multivibrator has one stable state and the other quasi stable state. It can be used to
generate a pulse of adjustable width by using a triggering signal. The monostable multivibrator is
also known as a pulse stretcher. Fig. 87 shows the circuit of monostable multivibrator.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [159]
D1 R

a
–
C
D2 b Vo
+ R2
VT

+
Vref R1
–

Fig. 87 Monostable multivibirator
Let initially the output of the circuit is , Vo = +Vsat
The reference feedback signal for Vo = +Vsat becomes,
R1
Vref = Vsat (270)
R1 + R 2

⇒ Vref = β Vsat (271)

R1
Where, β = (272)
R1 + R 2

The diode is forward biased when output voltage is +Vsat . When diode is forward biased the voltage
at node a is same as voltage drop across diode.
∴ Va = VD (273)
Where VD is voltage drop across forward biased diode.
Voltage at node ‘b’, Vb = Vref = β Vsat (274)
The value of resistances R1 and R2 is selected such that Vb > VD . The output of op-amp remains +Vsat
as long as Vb > VD .

If triggering pulse of suitable amplitude is applied at triggering terminal then the voltage at node
‘b’ falls below VD and output of op-amp becomes –Vsat . Then the Vb becomes –β Vsat and diode is
reversed biased and the capacitor first discharges from VD and then charges to –β Vsat . The moment
voltage across capacitor becomes more negative than –β Vsat, the output of op-amp becomes +Vsat and
Vb becomes +β Vsat. At the same instant, the diode gets forward biased and capacitor gets discharged
suddenly through diode D1. The waveforms of output voltage, triggering pulse and capacitor voltage
of monostable multivibrator are shown in Fig. 88.
Voltage across capacitor for t > 0 is given by,
-t

vc(t) = V∞ – (V∞ – V0+) e RC (275)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [160]

VT

t
Vo
+Vsat
t=0 t=T

t
–Vsat

vc
T
VD
t
Discharging
–Vsat through diode
–Vsat

Charging through R.

Fig. 88 Output voltage waveform of monostable multivibirator

Where V∞ is voltage at t = ∞ and V0+ is voltage at t = 0+.
Here, V∞ = –Vsat and V0+ = VD
-t

⇒ vc(t) = –Vsat – (–Vsat – VD) e RC

(276)
At t = T; vc(T) = – β Vsat
-T

⇒ –β Vsat = –Vsat – (–Vsat – VD) e RC

-T
(1 - b) Vsat
⇒ e RC =
Vsat + VD

Vsat VD
⇒ T = RC ln
(1 - b) Vsat

But, Vsat >> VD , so, Vsat + VD ≈ Vsat

Vsat
⇒ T = RC ln
(1 - b) Vsat

1
⇒ T = RC ln (277)
(1 - b)

R1 1
When, R1 = R2 = R ; β = =
R1 + R 2 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [161]
Then the duration of pulse becomes,
1
T = RC ln = RC ln 2 (278)
1
1-
2

T = 0.69 RC (279)
Applications :
A monostable multi-vibrator can be used for pulse width modulation. It is also used as a pulse
stretcher.
17.3 Triangular Wave Generator
A triangular wave generator consists of square wave generator followed by an integrator circuit. Fig.
89 shows the circuit diagram of a triangular waveform generator.
R R4

C1
a – R3 C2
c – Vo
b + R2
d +
+
Vref R1 Rcom
–

Fig. 89 Triangular wave generator
Example 88
Consider the triangular wave generator shown below.
C F
R k

Input  
10k + Output
1k 

Assume that the op-amps are ideal and have ±12V power supply. If the input is a ± 5Vsquare wave
of duty cycle 50%, the condition that results in a triangular wave of peak to peak amplitude 5 V and
frequency 50 Hz at the output is
R
(a) RC = 1 (b) =1
C

R C
(c) =5 (d) =5
C R

GATE(IN/2007/2M)
Solution : Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [162]
C F
R k
input R1
Vi – R2
10 k (1) –
+ V01 1 k (2) Vo
+

Above circuit consists of an integrator followed by an inverting mode amplifier. Output of the Op-
amp 1 can be given as,
 1 t 
V01 = –  ∫
 R1C 0
Vi dt + Vco-  ......(i)

Output of Op-amp 2 can be given as,
R
Vo = – × V01 .....(ii)
R2

From equation (i) & (ii), we have,

R  1 
t

Vo = + × ∫
R 2  R1C 0
Vi dt + Vco- 


Vi

+5 V
T/2
t
10 m sec.
–5 V
Vo

25 V
t
–2.5 V

t
R R
⇒ Vo = ∫
R 2 R1C 0
Vi dt + ·Vco
R2

t
R
R 2 R1C ∫0
⇒ Vo = Vi dt + Vo (0) ;

R
where Vo(0) = Vco = Initial output voltage
R2

Given, f = 50 H
1
∴ T = = 20 ms
f

At t = 0, Vi = + 5

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [163]
and Vo(0) = –25 V
t
R 1 R
Vo = + × × ∫ 5dt - 2.5 = × 5t - 2.5
R 2 R1C 0 R 2 R1C

At t = T/2 = 10 m sec.
Vo = 2.5 V
R 1
⇒ 2.5 = × × 5 × 10 × 10-3 - 2.5
R 2 R1C

From circuit, R1 = 10 kΩ and R2 = 1 kΩ

R × 103
⇒ 2.5 = 3 3 -6
× 5 × 10 × 10-3 - 2.5
1 × 10 × 10 × 10 × C × 10

R
⇒ = 1
C

Example 89
A waveform generator circuit using op-amps is shown in the figure. It produces a triangular wave at
point ‘P’ with a peak to peak voltage of 5 V for vi = 0 V.
C
R
  ‘P’
 
R1 v1

+12V V
R1

If the voltage v1 is made +2.5 V, the voltage waveform at points ‘P’ will become.

t(sec.)
5V
0
(a) (b)
2.5 V
V

t(sec.) V

V
(c) V
(d)
0 0
t(sec.) t(sec.)
V V

GATE(EE/2008/2M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [164]
Solution : Ans.(d)
Comparator Integrator
C

– V01 R
(1) – P
+ (2)
+ Vo

R1
R1

In the circuit shown above output of comparator is a square wave with amplitude of Vz and that of
integrator is a triangular wave as shown below,
v01
VZ

t
 VZ

v0
VZ

t
 VZ
tfall trise

Case -I : Shifting of dc level of triangular wave

The dc level of triangular wave at output can be shifted by connecting a dc voltage source at inverting
terminal of comparator.
Case - II : Adjusting rise time and fall time of triangular wave
The rise time and fall time of triangular waveform can be adjusted by connecting a dc potentiometer
at non-inverting terminal of integrator as shown below.
Comparator Integrator
C

– V01 R
(1) – P
‘a’ (2)
+
‘b’ + Vo
Vi
R1
R1
+VCC –VEE
potentiometer

The rise time of triagular wave becomes more than fall time when the wiper of potentiometer is
shifted towards −VEE . In such case waveform at output of integrator becomes as under,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [165]
v0
VZ

t
 VZ
trise
tfall

The fall time of triagular wave becomes more than rise time when the wiper of potentiometer is
shifted towards +VCC . In such case waveform at output of integrator becomes as under,
v0
VZ

t
 VZ
tfall
trise

In the given circuit the potentiometer is adjusted to +2.5 V, therefore, the fall time of triagular
waveform at output is more than the rise time. The wave form of output becomes as under,

V

0
t(sec.)
V

17.4 Sawtooth Wave or Spike Generator

Sawtooth wave or spikes can be generated by connecting a differentiating circuit at the output of a
zero crossing detector with sinusoidal input. Either positive or negative spikes can be rectified by
connecting a diode at the output of differentiating circuit. Fig. 90 shows the circuit diagram of a
positive spike generator.

– Vo Vo Vo
+
Vi

Fig. 90 Spike generator

The sinusoidal input applied at non-inverting terminal is converted to square wave. The square wave
is converted to sawtooth wave by differentiating circuit connected at output terminal of op-amp. The
sawtooth wave the converted to postive spikes by diode connected at output of differentiating circuit
as shown in Fig. 91.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [166]
Vi

t
V
+Vsat

t
–Vsat
V

Vo

t
Fig. 91 Output voltage waveform of spike generator

18 555 Timer
The 555 timer is a highly stable device which can be used as a pulse generator, square generator,
mono-shot multivibrator etc. Fig. 92 shows the functional diagram of a 555 times. It is 8 pin integrated
circuit.
VCC
8

6 R Comparator 1
Threshold Vref
+
a – Flip-Flop
Control
Voltage 5 R 4
R FF Q2
Comparator 2 S
b Q Reset
2 +
Trigger –
R
Output
Discharge stage Ouput
Q1 (inverter)
7
3
1 Ground

Fig. 92 Function block diagram of 555 Timer

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [167]
The functions of pins of 555 times is discussed as under,
Pin 1 (Ground) : All voltages are measured with respect to ground terminal.

Pin 2 (Trigger) : Output of timer circuit depends amplitude of external trigger applied at pin 2. When
a negative going triggering pulse is applied at pin 2 , the voltage a inverting terminal of comparator
2 falls below VCC/3 and output of op-amp goes high which sets the flip-flop and output Q of flip-flop

becomes low and output of 555 times goes high.

Pin 3 (Output) : This output terminal of 555 timer. The load resistance can be connected between
pin 3 and ground which is refereed as normally off load. The load resistance can also be connected
between pin 3 and +VCC which is refereed as normally on load.

Pin 4 (Reset) : The timer can be reset by applying a negative pulse at pin 4. It should be connected
to +VCC when not in use.

Pin 5 (Control Voltage) : This pin can be used to vary width of output pulse. It changes threshold as
well as trigger voltage. It should be connected to ground when not in use.

Pin 6 (Threshold) : When voltage at pin 6 becomes more than +2VCC/3, the output of comparator
becomes high and output of FF is reset and thus output Q of flip-flop becomes high and output of

555 times goes low.

Pin 7 (Discharge) : When output of timer is low the transistor Q1 is saturated and pin 7 is connected
to ground through Q1. The transistor Q1 is off when output of timer is high.

Pin 8 (+VCC) : The pin 8 is used to connect external supply to the timer.
18.1 Astable Multivibrator Using 555 Timer
Astable multivibrator is a free running multivibrator used to generate a square wave. A 555 timer
can be used as a astable multivibrator by connecting two resistors (RA & RB) and one capacitor (C)
as shown in Fig. 93.
VCC

8
RA
7 4
RB 555
6 3
Output
2
C 1 5

C1

Fig. 93 Astable multivibrator using 555 Timer

Initially, when output of timer is high, the capacitor C starts charging through combination of resistances

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [168]
RA and RB. When voltage across capacitor reaches 2/3 VCC, the output of internal comparator 1
becomes +Vsat , which resets the flip-flop and output of the timer becomes low. As soon as output
of timer becomes low, the internal transistor Q1 is turned on and capacitor starts discharging through
resistance RB and transistor Q1. When voltage across the capacitor falls to 1/3 VCC, the output of
internal comparator 2 becomes +Vsat which sets the flip-flop and output of timer becomes high. This
cycle of charging and discharging keeps on repeating cyclically and output of timer is a square wave.
The waveforms of capacitor voltage and output voltage of astable multivibrator are shown in Fig. 94.
Vo Output Capacitor
voltage voltage

VCC
2V
3 CC
1 VCC
3

tc td t
T

Fig. 94 Waveforms of capacitor voltage and output voltage

of astable multivibrator

The capacitor C charges through combination (RA + RB) and discharges through RB so the time constant
during charging period is C(RA + RB) and the time constant during discharging period is CRB
The duration of charging time of capacitor can be given by,
tc = (RA + RB)C ln 2 = 0.693(RA + RB)C (280)
The duration of discharging time of capacitor,
td = RBC ln 2 = 0.693 RBC (281)
Total period of square wave at output of multivibrator,
T = tc + td = 0.693(RA + 2RB)C (282)

1 1 1.44
=
Frequency of Oscillation, f = = (283)
T 0.693(R A + 2 R B ) C (R A + 2 R B ) C
Applications of Astable Multivibrator
(a) FSK Generation
(b) PPM (Pulse Position Modulation)

Example 90
An astable multivibrator circuit using IC 555 timer is shown below. Assume that the circuit is
oscillating steadily.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [169]

9V

30 K
4 8
(Reset) (Supply)
6 (Threshold)
(output) 3
10 K
(Gnd)
2 (Trigger) 1
(Discharge)
12 K 7

VC .01 µF

The voltage Vc across the capacitor varies between.
(a) 3V to 5 V (b) 3V to 6 V
(c) 3.6 V to 6 V (d) 3.6 V to 5 V
GATE(EC/2008/2M)
Solution : Ans.(b)
9V

30 K
4 8
(Reset) (Supply)
6 (Threshold)
(output) 3
10 K
(Gnd)
2 (Trigger) 1
(Discharge)
12 K 7

VC .01 µF

Output of astable multivibrator shown above changes level when voltage at trigger pin becomes
V 2Vcc
either greater than 2VCC/3 or less than VCC/3. So, voltage across capacitor varies from cc to
3 3
. From given circuit, VCC = 9V so voltage VC varies from 3V to 6V.

Example 91
An astable multivibrator circuit using a 555 IC is given in the following figure. The frequency of
oscillations is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [170]
VCC – 5V

8 4

I – 5 mA 3
6 output
Vth
555
2
Vtring 7
discharge

C – 0.1 µF
1

(a) 20 kHz (b) 30 kHz

(c) 40 kHz (d) 45 kHz
GATE(IN/2006/2M)
Solution : Ans.(b)
VCC – 5V

8 4

I – 5 mA 3
6 output
Vth
555
2
Vtring 7
discharge

C – 0.1 µF
1

Replacing 555 times by its equivalent circuit we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [171]
+VCC = + 5V
8
Vref
I=5mA
V6 Q2 4
+
R 1
B –
1
VA = VCC R
3 Control + 3
FFQ
2 R S –
VB = 3VCC Power
Amplifier
V2 A +
2
C = 0.1 F R
– Q1

In the circuit shown above the capacitor charges linearly untill V6 > VB. When V6 > VB the output of
Op-amp 1 becomes +Vsat and flip-flop FF is reset which in turn drives the BJTQ1 to saturation. When
BJT Q1 is saturated it discharges the capacitor directly to ground through pin ‘7’. When level of
discharge of capacitor reaches to +VCC/3 the output of Op-amp 2 becomes + Vsat which in turn sets
the FF and makes Q = 0 . So, BJT Q1 is driven to cutoff. The cycle of charging and discharging

repeats periodically with voltage of capacitor varying between +VCC/3 and +2VCC/3. The waveform
of Vc(t) is are shown below,
During charging,
1 t
C ∫o
Vc(t) = idt + Vco

Here, i = 5 mA, C = 0.1µF,

Vcc
and Vco =
3

t
1 V
-6 ∫
⇒ Vc(t) = 5 × 10-3 dt + cc
0.1 × 10 o 3

3 Vcc
⇒ Vc = 50 × 10 t +
3
Vc (t)
2Vcc
+
3
Vcc
+
3
t
T

2Vcc
At t = T, Vc(t) =
3

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [172]

2Vcc 3 V
⇒ = 50 × 10 T + cc
3 3

Vcc
⇒ 50 × 103 T =
3

Given, Vcc = +5V

5
∴ 50 × 103 T =
3
1
⇒ f= = 30 kHz
T

Example 92
A 555 astable multivibrator circuit is shown in the figure below :
5V

RA reset
10k

Discharge
10k RB Out
Trigger
Vc thereshold

C Ground
1F

If RB is shorted, the waveform at VC is

Vcc
Vc
2/3Vcc
2/3Vcc
1/3Vcc 1/3Vcc
t
(a) 0 t (b) 0
Vc Vc
2/3Vcc
2/3Vcc
1/3Vcc 1/3Vcc
(c) 0
t
(d) 0 t

GATE(IN/2007/1M)

Solution : Ans.(a)
5V

10k RA reset
7
Discharge
10k RB Out
6 Trigger
thereshold
Vc
Ground
1F C

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [173]
In 555 astable multivibrator circuit shown above the voltage across capacitor oscillates between
V 2V
+ cc to + cc .
3 3

The capacitor charges through RA & RB from Vcc and discharges through RB to ground through pin 7.
Vcc 2V
Time required to charge from + to + cc ,
3 3

tH = 0.69 (RA + RB) C

Vcc 2V
Time required to discharge from + to + cc ,
3 3
tL = 0.69 RBC
when, RB = 0, tH = 0.69 RAC
and tL = 0
So, capacitor charges through RA but discharges suddenly. So the waveform of voltage across
capacitor, with RB = 0, will be as shown below,
Vc
2Vcc
+
3
Vcc
+
3
t
tH 2tH

Example 93
The circuit of figure shows a 555 Timer IC connected as an astable multivibrator. The value of the
capacitor C is 10 nF. The values of the resistors RA and RB for a frequency of 10 kHz and a duty cycle
of 0.75 for the output voltage waveform are
VCC

RA

Th
RB
Vout
Tr
R1
C 555
Timer
IC
Discharge

(a) RA = 3.51 kΩ, RB = 3.62 kΩ (b) RA = 3.62 kΩ, RB = 7.25 kΩ

(c) RA = 7.25 kΩ, RB = 3.62 kΩ (d) RA = 7.25 kΩ, RB = 7.25 kΩ
GATE(EE/2003/2 M)
Solution ; Ans.(c)
Frequency of as 555 timer astable multivibrator is given by,
1
f = ......(i)
0.69(R A + 2R B )C

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [174]
VCC
RA

Th
RB
Tr Vout
R1
C 555
Timer
IC
Discharge

And duty cycle is given by,

RA + RB
Duty Cycle = ......(ii)
R A + 2R B

Given, f = 10 kHz, C = 10 nF, Duty Cycle = 0.75

1
From equation (i), 10×103 =
0.69(R A + 2R B ) × 10 × 10 –9

RA + 2RB = 1.45×104 .....(iii)

RA + RB
From equation (ii), 0.75 =
R A + 2R B

⇒ RA – 2RB = 0
RA = 2RB .....(iv)
From equations (iii) and (iv),
14.5
RB = kΩ = 3.62 kΩ
4

And RA = 7.25 kΩ

18.2 Monostable Multivibrator Using 555 Timer

A monostable multivibrator is a pulse generating circuit. It is also known as mono-shot multivibrator.
The duration of pulse depends on external resistance (R) and capacitor (C) connected to the timer
as shown in Fig. 95. Initially, the output of multivibrator is low which is a stable state , the internal
transistor Q 1 is on and capacitor C is shorted to ground through Q1. When a negative going triggering
signal is applied at trigger terminal (pin2), the signal at inverting terminal of internal comparator 2
falls below 1/3 VCC which sets the flip-flop and output of 555 timer becomes high and transistor Q1 is
turned off. The moment transistor Q1 is turned off, the capacitor C starts charging towards value VCC.
When capacitor voltage reaches 2/3 VCC, the output of internal comparator 1 becomes +Vsat which
resets the flip-flop and output of timers again becomes low.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [175]
VCC

8
R

7 4
Trigger
555
2 3

6 Output
C
1 5

C1

Fig. 93 Monostable multivibrator using 555 Timer

The transistor Q1 is turned on, which shorts the capacitor C to ground. The output of timer remains
low till another negative going triggering signal is given at trigger input of the circuit. The waveforms
of triggering signal, capacitor voltage and output voltage of the monostable multivibrator are shown
in Fig. 96.
Trigger

VCC

0
t=0 t
Output
VCC

0
T t
Capacitor
Votlage

2/3 VCC
0
t
T
Fig. 96 Waveforms of trigger, capacitor voltage and output voltage
of monostable multivibrator

The duration for which output of timer remains high can be determined by values of resistance R and
capacitor C as under,

Voltage across capacitor during charging period can be given by,

vc(t) = VCC ( 1- e-t/RC) (284)
At t = T, vc(t) = 2/3 VCC
⇒ 2/3 VCC = VCC ( 1- e-T/RC)
⇒ T = RC ln 3 = 1.1 RC (285)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [176]
Applications of Monostable Multivibrator:
(a) Linear RAMP generator
(b) Pulse width modulator or Pulse stretcher
(c) Frequency divider
(d) Missing pulse detector

18.3 Schmitt Trigger Using 555 Timer

A 555 timer can be used as a Schmitt Trigger by biasing both comparators of timer at VCC/2. Fig. 97
shows the circuit diagram of Schmitt trigger. When a sinusoidal input is applied at input terminal the
output of the circuit is a square wave.
VCC

8
R
4
Sinusoidal 6
input 555
3
2
Output
R
1 5
C1

Fig. 93 Monostable multivibrator using 555 Timer

When the input voltage becomes more than +2VCC/3 , the internal flip-flop of the timer is reset and
output of the timer becomes low. When the input voltage falls below +VCC/3, the internal flip-flop is
set and output of the timer becomes high. The output of the timer is a square wave.



www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [177]

GATE QUESTIONS
Q.1 The operational amplifiers use a differential input stage with a constant current source, mainly to
obtain
(a) very low common mode gain (b) very high differential gain
(c) very low input noise (d) very high input resistance
GATE(IN/1997/1M)
Q.2 An amplifier using an op-amp with a slew-rate SR=1 V/µsec has a gain of 40 dB. If this amplifier has
to faithfully amplify sinusoidal signals from dc to 20 KHz without introducing any slew-rate induced
distortion, then the input signal level must not exceed.
(a) 795 mV (b) 395 mV
(c) 79.5 mV (d) 39.5 mV
GATE(EC/2002/2M)
Q.3 A differential output high impedance signal source is connected to an instrumentation amplifier
through two shielded cables. The best way to obtain a high CMRR is to connect the cable shields to
(a) output of the instrumentation amplifier
(b) mean of the two first stage outputs in the instrumentation amplifier
(c) common signal ground
(d) power supply ground
GATE(IN/1995/1M)
Q.4 The signal to noise (S/N) ratio of an amplifier developing an output voltage of 10 V and a noise
voltage of 1 mV is
(a) –40 dB (b) 40 dB
(c) 80 dB (d) 100 dB
GATE(IN/1996/1M)
Q.5 An Op-amp with a slew rate of 1 V/µsec has been used to build an amplifier of gain + 10. If the input
to the amplifier is a sinusoidal voltage with peak amplitude of 1V, the maximum allowable frequency
of the input signal for undistored output is
(a) 830 Hz (b) 15.92 kHz
(c) 31.84 kHz (d) 1.0 MHz
GATE(IN/2000/2M)
Q.6 If the op-amp in figure has an input offset voltage of 5 m V and an open-loop voltage gain of 10, 000,
then vo will be

+ 15 V
–
+ V0
– 15 V

(a) 0 V (b) 5 mV
(c) + 15 V or −15 V (d) + 50 V or −50 V
GATE(EC/2000/1M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [178]
Q.7 The output of an Op-amp whose input is a 2.5 MHz square wave is shown in figure The slew rate of
the Op-amp is

 4V

 4V
0.4 s

(a) 0.8 V/µ sec. (b) 8.0 V/µ sec.

(c) 20.0 V/µ sec. (d) 40.0 V/µ sec.
GATE(IN/2003/1M)
Q.8 For an ECG amplifier the input signal is 100 µV corrupted by a common mode noise of 5 mV. The
output of the amplifier contains 50 mV of signal and 0.001 mV of noise. The CMRR of the amplifier
is
(a) 40 dB (b) 60 dB
(c) 80 dB (d) 100 dB
GATE(IN/2003/2M)
Q.9 The potential difference between the input terminals of an Op-amp may be treated to be nearly zero
if
(a) the two supply voltages are balanced
(b) the output voltage is not saturated
(c) the Op-amp is used in circuit having negative feedback
(d) there is a dc bias path between each of the input terminals and the circuit ground
GATE(IN/2006/2M)
Q.10 In the circuit shown in the following figure, the op-amp has input bias current Ib < 10 nA, and input
offset voltage V io < 1 mV . The maximum dc error in the output voltage is
RF

R1 IB 100k
+ –
Vs
~ 100k Vio
– +
Vo

(a) 1.0 mV (b) 2.0 mV

(c) 2.5 mV (d) 3.0 mV
GATE(IN/2006/2M)
Q.11 If the value of the resistance R in the following figure is increased by 50%, the voltage gain of the
amplifier shown in the figure will change by
10k

1k
Vin –
Vout
+

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [179]
(a) 50 % (b) 5%
(c) – 50 % (d) negligible amount
GATE(IN/2006/1M)
Common Data for Question 12, 13, 14 :
Consider the op-amp circuit shown in the figure below:
20k 100k
V1

V2 –
R1 Vo
+

R2

Q.12 If V1 = 0.2 V, V2 = 0.6 V and V0 = – 7 V, and the op-amp is ideal, the value of R1 is
(a) 5 kΩ (b) 10 kΩ
(c) 15 kΩ (d) 20 kΩ
GATE(IN/2007/2M)
Q.13 Let V1 = V2 = Vc sin 2πft and R1 = 20 kΩ. The op-amp has a slew rate of 0.5 V/µs with its other
parameters being ideal. The values of Vc and f for which the amplifier output will have no distortion
are, respectively
(a) 0.1 V and 300 kHz (b) 0.5 V and 300 kHz
(c) 0.1 V and 30 kHz (d) 0.5V and 30 kHz
GATE(IN/2007/2M)
Q.14 A differential amplifier shown below has a differential mode gain of 100 and a CMRR of 40 dB.If
V1=0.55 V and V2=0.45 V, the output V0 is

V1 +

V2 Vo
–

(a) 10 V (b) 10.5 V

(c) 11 V (d) 15 V
GATE(IN/2008/2M)
Q.15 An ideal op-amp has the characteristics of an ideal
(a) voltage controlled voltage source (b) voltage controlled current sourece
(c) current controlled voltage source (d) current controlled voltage source
GATE(IN/2008/1M)
Q.16 The operational amplifier shown in the circuit below has a slew rate of 0.8 Volts /µs. The input signal
is 0.25 sin(ωt). The maximum frequency of input in kHz for which there is no distribution in the
output is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [180]
470 k

22 k
–

+
0.25 sin t ~ V0

(a) 23.84 (b) 25.0

(c) 50.0 (d) 46.60
GATE(IN/2013/1M)
Q.17 An ideal Op-amp is used to make an inverting amplifier. The two input terminals of the Op-amp are
at the same potential because
(a) The two input terminals are directly shorted internally
(b) The input impedance of the Op-amp is infinity
(c) The open loop gain of the Op-amp is infinity
(d) CMRR is infinity
GATE(EE/1992/2 M)
Q.18 An Op-amp, having a slew rate of 62.8 V/µsec, is connected in a voltage follower configuration. If
the maximum amplitude of the input sinusoid is 10 V, then the minimum frequency at which the slew
rate limited distortion would set in at the output is
(a) 1.0 MHz (b) 6.28MHz
(c) 10.0 MHz (d) 62.8 MHz
GATE(EE/2001/2 M)
Q.19 For the op-amp shown in the figure, the bias currents are Ib1 = 450 nA and Ib2 = 350 nA. The values
of the input bias current (IB) and the input offset current (If) are:
Ib1
–

Ib2
+

(a) IB = 800 nA, If = 50 nA (b) IB = 800 nA, If = 100 nA

(c) IB = 400 nA, If = 50 nA (d) IB = 400 nA, If = 100 nA
GATE(IN/2014/1 M)
Q.20 In the circuit given below, each input terminal of the opamp draws a bias current of 10 nA. The effect
due to these input bias currents on the output voltage Vo will be zero, if the value of R chosen in kilo-
ohm is ..........

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [181]
60k

30k
–
+ V0

GATE(IN/2016/1 M)
Q.21 The differential amplifier, shown in the figure, has a differential gain of Ad =100 and common mode
gain of Ac = 0.1. If V1 = 5.01 V and V2 = 5.00 V, and then Vo, in volt (up to one decimal place) is
________.

V2 –
Differential
V0
Amplifier
V1 +

GATE(IN/2017/1 M)
Q.22 The voltage eo indicated in figure has been measured by an ideal voltmeter. Which of the following
can be calculated?

1M
–
e0
+

1M

(a) Bias current of the inverting input only

(b) Bias current of the inverting and non-inverting inputs only
(c) Input offset current only
(d) Both the bias currents and the input offset current
GATE(EC/2005/2M)
Q.23 An Op-amp. has an offset voltage of 1m V and is ideal in all other respects. If this op-amp is used in
the circuit shown in figure the output voltage will be (select the nearest value)

1 k 1 M
–
+ VOut

(a) 1 mV (b) 1 V
(c) ±1 V (d) 0 V
GATE(EC/1992/2M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [182]
Q.24 In the circuit shown, the op-amp has finite input impedance, infinite voltage gain and zero input offset
voltage. The output voltage Vout is
R2

R1 I1
–
Vout
+
I2

(a) – I2 (R1 + R2) (b) I2 R2

(c) I1 R2 (d) – I1 (R1 + R2)
GATE(EC-I/2014/2M)
Q.25 The Op-amp in the amplifier circuit shown in figure has an offset voltage of 10 mV and it is ideal
otherwise. If Vi is zero, the output voltage Vo is
10 k
1k
Vi –
Vo
+

1k

(a) 0 (b) 10 mV
(c) 100 mV (d) 110 mV
GATE(IN/1999/2M)
Q.26 An amplifier with resistive negative feedback has two left half plane poles in its open-loop transfer
function. The amplifier
(a) will always be unstable at high frequencies
(b) will be stable for all frequencies
(c) may be unstable, depending on the feedback factor
(d) will oscillate at low frequencies
GATE(EC/2000/1M)
Q.27 A 741-type op-amp has a gain-bandwidth product of 1 MHz. A non-inverting amplifier using this op-
amp and having a voltage gain of 20 dB will exhibit a-3-dB bandwidth of
(a) 50 KHz (b) 100 KHz
1000 1000
(c) KHz (d) KHz
17 7.07

GATE(EC/2002/1M)
Q.28 The first dominant pole encountered in the frequency response of a compensated op-amp is
approximately at
(a) 5 Hz (b) 10 kHz
(c) 1 MHz (d) 100 MHz

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [183]
GATE(EC/1999/1M)
Q.29 The ideal Op-amp has the following characteristics.
(a) Ri = ∞, A = ∞, R0 = 0 (b) Ri = 0, A = ∞, R0 = 0
(c) Ri = ∞ A = ∞, R0 = ∞ (d) Ri = 0 A = ∞, R0 = ∞
GATE(EC/2001/2M)
Q.30 An ideal Op-amp is an ideal
(a) voltage controlled current source (b) voltage controlled voltage source
(c) current controlled current source (d) current controlled voltage source
GATE(EC/2004/1M)
Q.31 The feedback factor for the circuit shown in figure is
100 
–
+
+
Vs – 90  1K
10 

(a) 9/100 (b) 9/10

(c) 1/9 (d) 1/10
GATE(EE/2000/1 M)
Q.32 The nature of feedback in the opamp circuit shown is
2 k

1k +6V
–
Vout
+
+ 6V
~ –
Vin

(a) Current – Current feedback (b) Voltage – Voltage feedback

(c) Current – Voltage feedback (d) Voltage – Current feedback
GATE(EE/2009/1M)
Q.33 A good current buffer has
(a) low input impedance and low output impedance
(b) low input impedance and high output impedance
(c) high input impedance and low output impedance
(d) high input impedance and high output impedance
GATE(EC-1/2014/1M)
Q.34 The input resistance Ri of the amplifier shown in figure is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [184]
30 k
10 k
–
~ +
Ri ideal op-amp
(a) 30/4 kΩ (b) 10 kΩ
(c) 40 kΩ (d) infinite
GATE(EC/2005/1M)
Q.35 The amplifier in the figure has gain of –10 and input resistance of 50 kΩ. The values of Ri and Rf are:
Rf

Ri
–

V0
+
= Vin – +

(a) Ri = 500 kΩ, Rf = 50 kΩ (b) Ri = 50 kΩ, Rf = 500 kΩ

(c) Ri = 5 kΩ, Rf = 10 kΩ (d) Ri = 50 kΩ, Rf = 200 kΩ
GATE(IN/2014/1M)
Q.36 Assuming the op-amp to be ideal, the voltage gain of the amplifier shown below is
R1
–
Vo
R2 +
Vi +
–

R3

R R
− 2 (b) − 3
(a)
R1 R1

 R || R 3   R + R3 
(c) −  2  (d) −  2 
 R1   R1 
GATE(EC/2010/1M)
Q.37 When the switch S2 is closed the gain of the programmable gain amplifier shown in the following
figure is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [185]
Vin +
Vo
–
S1 2k
S2

1k
S3

500
S4

500

(a) 0.5 (b) 2

(c) 4 (d) 8
GATE(IN/2006/1M)
Q.38 Let the magnitude of the gain in the inverting Op-amp amplifier circuit shown in figure be x with
switch S1 open. When the switch S1 is closed, the magnitude of gain becomes
S

R
R
–
Vin
Vo
+

(a) x/2 (b) –x

(c) 2x (d) – 2x
GATE(EE/1997/1 M)
Q.39 Consider the inverting amplifier, using an ideal operational amplifier shown in figure. The designer
wishes to realize the input resistance seen by the small-signal source to be as large as possible, while
keeping the voltage gain between –10 and –25. The upper limit on RF is 1 MΩ. The value of R1
should be
RF

R1
–
Vin
+ Vout

(a) Infinity (b) 1 MΩ

(c) 100 kΩ (d) 40 kΩ
GATE(EE/2005/2 M)
Q.40 An op-amp based circuit is implemented as shown below.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [186]

31 k

+15V
1 k
+ –
A +
1V + v0
– –
–15V

In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place)
at node A, connected to the negative input of the op-amp as indicated in the figure is _________.
GATE(EC/2018/2M)
Q.41 The output Vo shown in the figure, in volt, is close to
2 k

+15 V
1 k
– V0
+
+
10 V
–
–15 V

(a) –20 (b) –15

(c) –5 (d) 0
GATE(IN/2017/1M)
Q.42 Given that the op-amp is ideal, the output voltage Vo is
2R

+ 10 V
R
–
V0
+
2V – 10 V

(a) 4 V (b) 6 V
(c) 7.5 V (d) 12.12 V
GATE(EE/2010/1 M)
Q.43 A linear phase low pass filter with a cut-off frequency 1500 Hz shifts a 50 Hz signal by 3 m-sec. It
will shift a signal of 150 Hz by
(a) 3 m-sec (b) 9 m-sec
(c) 1 m-sec (d) 30 m-sec
GATE(IN/1996/1M)
Q.44 In the circuit shown below the op-amps are ideal. Then Vout in Volts is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [187]
1 k 1 k
–2 V
+15 V
+15 V
–
+ Vout
+
–
–15 V
–15 V
1 k
1 k
1 k
+1V

(a) 4 (b) 6
(c) 8 (d) 10
GATE(EC/2013/2M)
Q.45 In the circuit shown below the op-amps are ideal. Then Vout in Volts is
1 k 1 k
–2 V
+15 V
+15 V
–
+ + Vout
–
–15 V –15 V
1 k
1 k
1 k
+1V

(a) 4 (b) 6
(c) 8 (d) 10
GATE(IN/2013/2M)
QQ.46 Assuming the operational amplifier to be ideal, the gain Vout/Vin for the circuit shown in figure is

10 k 10 k

1 k
1 k
–
Vin + Vout

(a) – 1 (b) – 20
(c) – 100 (d) – 120
GATE(EE/2003/2 M)
Q.47 In the circuit shown below the op – amp are ideal. Then Vout in Volts is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [188]
1 k 1 k
–2 V
+15 V
+15 V
–
+ Vout
+
–
–15 V –15 V
1 k
1 k 1 k
+1V

(a) 4 (b) 6
(c) 8 (d) 10
GATE(EE/2013/2 M)
v 
Q.48 In the circuit shown, assume that the opamp is ideal. If the gain  o  is –12, the value of R(in kΩ)
 vin 

is ..............
10k 10k

R
10k
–
Vin +
Vo

GATE(EC-III/2015/2 M)

v0
Q.49 Assuming an ideal op-amp in linear range of operation, of the transfer impedance in MΩ of the
i
current to voltage converter shown in the figure is__________.
R1 = 45 k R2 = 5 k

R3 = 55.5 k
–
vo
+

GATE(IN/2014/2 M)
Q.50 In the figure shown, RT represents a resistance temperature device (RTD), whose characteristic is
given by RT = Ro(1 + αT), where Ro = 100 Ω, α = 0.0039 ºC–1 and T denotes the temperature in ºC.
Assuming the opamp to be ideal, the value of Vo in volts when T = 100º C, is .......... V.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [189]
+
Vr= +1V +
–
RT Vo
–
100 

GATE(IN/2015/2 M)
Q.51 If the Op-amp in figure is ideal, the output voltage Vout will be equal to
5 k

1 k
2V –

3V + Vo
1 k
8 k

(a) 1 V (b) 6 V
(c) 14 V (d) 17 V
GATE(EC/2003/2M)
Q.52 For the Op-Amp circuit shown in the figure, Vo is
2k

1k
–
4V 1k Vo
+
1k

(a) – 2 V (b) – 1 V
(c) – 0.5 V (d) 0.5 V
GATE(EC/2007/2M)
Q.53 The output voltage (Vo) of the circuit shown in figure is
100k

10k
2V –
Vo
5V +
10k
100k

(a) –20 V (b) 20 V

(c) – 30 V (d) 30 V
GATE(IN/1995/1M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [190]
Q.54 In the Op-amp circuit shown in figure the output voltage Vo, is equal to

10k 100 k
a –
Vo
+ +
1V –

(a) 11 V (b) –10 V

(c) 9 V (d) 1 V
GATE(IN/1997/1M)
Q.55 Assuming its differential gain to be 10 and the op-amp to be otherwise ideal, the CMRR is
(a) 102 (b) 103
(c) 104 (d) 105
GATE(IN/2013/2M)
Q.56 The differential amplifier is connected as shown Fig. (b) above to a single strain gauge bridge. Let the
strain gauge resistance vary around its no–load resistance R by ± 1%. Assume the input impedance of
the amplifier to be high compared to the equivalent source resistance of the bridge, and the common
mode characteristic to be as obtained above. The output voltage in mV varies approximately from
(a) +128 to –128 (b) +128 to –122
(c) +122 to –122 (d) +90 to –121
GATE(IN/2013/2M)
Q.57 Assuming that the Op -amp in the circuit shown is ideal, Vo is given by
3R

R
V1 –
V0
+
2R V2 R

5 5
(a) V1 − 3V2 (b) 2V1 − V2
2 2

3 7 11
(c) − V1 + V2 (d) −3V1 + V2
2 2 2

GATE(EC-III/2014/2M)
Q.58 An operational-amplifier circuit is shown in the figure.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [191]
R
+Vsat
+Vsat R
–
vi –
vo
+
+
–Vsat –Vsat

R2
R1

The output of the circuit for a given input vi is

R   R 
(a) −  2  vi (b) − 1 + 2  vi
 R1   R1 

 R 
(c) 1 + 2  vi (d) + Vsat or – Vsat
 R1 

GATE(EE-III/2014/1M)
Q.59 Consider the circuit shown in the figure. In this circuit R = 1 kΩ, and C = 1 µF. The input voltage
is sinusoidal with a frequency of 50 Hz, represented as a phasor with magnitude Vi and phase angle
0 radian as shown in the figure. The output voltage is represented as a phasor with with magnitude
Vo and phase angle δ radian. What is the value of the output phase angle δ (in radian) relative to the
phase angle of the input voltage ?

C
–
Vi = Vi 0 +
Vo = Vo 
C
R

(a) 0 (b) π
π π
(c) (d) −
2 2

GATE(EE-I/2015/1M)
Q.60 In the circuit shown, Vo = VoA for switch SW in position A and Vo = VoB for SW in position B. Assume
V
that the opamp is ideal. The value of o B is ..............
Vo A

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [192]
1k

5V 1k
–
A 1k V0
B
+
SW 1k
1k
1V

GATE(EC-II/2015/1M)
Q.61 Assuming that the opamp in the circuit shown below is ideal, the output voltage Vo (in volts) is
............
2k

1k 12V
–
+ Vo
–12V
1V
GATE(EC-II/2015/2M)

Q.62 In the circuit given below, the opamp is ideal. The output voltage Vo in volt is ..........
20k
20k
10k
2V –
V1
20k + V0

10k

GATE(IN/2016/1M)
Q.63 An ideal opamp is used to realize a difference amplifier circuit given below having a gain of 10. If
x = 0.025, the CMRR of the circuit in dB is ..........

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [193]
100(1+ x)k

10(1– x)k
V1 –
10(1+ x)k
V2 + V0

100(1– x)k

GATE(IN/2016/1M)
Q.64 In the circuit below, the operational amplifier is ideal. If V1 = 10 mV and V2 = 50 mV, the output
voltage (Vout) is
100 k

10 k
V1 –

V2 + Vout
10 k
100 k

(a) 100 mV (b) 400 mV

(c) 500 mV (d) 600 mV
GATE(EE/2019/2M)

Common Data for Question 65, 66, 67 :

Consider the op-amp circuit shown in the figure below:

20k 100k
V1

V2 –
R1 Vo
+

R2

Q.65 If V1 = 0.2 V, V2 = 0.6 V and V0 = – 7 V, and the op-amp is ideal, the value of R1 is
(a) 5kΩ (b) 10kΩ
(c) 15kΩ (d) 20kΩ
GATE(IN/2007/2M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [194]
Q.66 Let V1 = V2 = Vc sin 2πft and R1 = 20 k Ω. The op-amp has a slew rate of 0.5 V/µs with its other pa-
rameters being ideal. The values of Vc and f for which the amplifier output will have no distortion are,
respectively
(a) 0.1 V and 300 kHz (b) 0.5 V and 300 kHz
(c) 0.1 V and 30 kHz (d) 0.5V and 30 kHz
GATE(IN/2007/2M)
Q.67 Let V1 =V2 =0 and R1=20 kΩ. Assume that the Op-amp is ideal except for a non-zero input bias current.
What is the value of R2 for the output voltage ofthe Op-amp to be zero ?
(a) 2.2 kΩ (b) 9.1 kΩ
(c) 20 kΩ (d) 100 kΩ
GATE(IN/2007/2M)
Q.68 If the Op-amp in figure is ideal, then v0 is
C
C
V1 sin t –
V0
V2 sin t
C +

(a) zero (b) (V1 – V2) sin ωt

(c) – (V1 + V2) sin ωt (d) (V1 + V2) sin ωt
GATE(EC/2000/1M)
Q.69 In the op-amp circuit given in figure, the load current iL is
R1 R1
Vs

–
R2
+

R2
R4
iL

V Vs
(a)
− s (b)
R2 R2

Vs
(c) (d)
R1

GATE(EC/2004/2M)
Q.70 The circuit shown in the figure is

R1

+
–
V Load
R2
r

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [195]

rV r || R2
(a) A voltage source with voltage (b) A voltage source with voltage V
R1 || R2 R1

r || R2 V R2 V
(c) A current source with current ⋅ (d) A current source with current ⋅
R1 + R2 r R1 + R2 r

GATE(EE/2007/1 M)
Q.71 In the circuit given below, the opamp is ideal. The value of current IL in microampere is .............
100k

100k
–
10k
1V +
10k
IL
RL

GATE(IN/2016/2M)
Q.72 The value of V0 in the circuit, shown in figure is

0.3 mA 10 k
–
V0
+

20 k 30 k

(a) – 5V (b) –3 V
(c) + 3 V (d) + 5 V
GATE(IN/2004/2M)
Q.73 The circuit shown in figure uses an ideal Op-amp working with +5V and –5V power supplies. The
output voltage Vo is equal to
1K
5V
–
 1 mA + V0
–5V

(a) + 5V (b) – 5V
(c) + 1V (d) – 1V
GATE(EE/2000/1 M)
Q.74 The input resistance Rin (= vx/ix) of the circuit in figure is
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [196]
R1 = 10 k R2 = 100 k

–
vo
+
vx
ix R3 = 1 M

(a) + 100 kΩ (b) – 100 kΩ

(c) + 1 MΩ (d) – 1 MΩ
GATE(EE/2004/2 M)
Q.75 The Op-amp and the 1 mA current source in the circuit of figure are ideal. The output of the
Op-amp is
1.5k

1.0k
–
Vo
1mA Output
+

+5V
(a) – 1.5 mA (b) – 1.5 V
(c) – 7.5 V (d) + 1.5 V
GATE(IN/2003/1M)
Q.76 V1 and V2 are the input voltages of an instrumentation amplifier. The output of the instrumentation
amplifier is found to be 100 (V1–V2) + 10–4 (V1 + V2). The gain and the common mode rejection ratio
(CMRR) of the instrumentation amplifier respectively are
(a) (50, 60 dB) (b) (50, 120 dB)
(c) (100, 60 dB) (d) (100, 120 dB)
GATE(IN/2004/2M)
Q.77 Given that the op-amps in the figure are ideal, the output voltage V0 is
V2 + R
–
R R
–
2R V0
+
R R
– R
V1 +

(a) (V1 – V2) (b) 2 (V1 – V2)

(c) (V1 – V2)/2 (d) (V1 + V2)
GATE(EE-II/2014/2M)
Q.78 In the instrumentation amplifier shown in figure, if the switch SW is changed from position A to B,
the values of the amplifier gain G before and after changing the switch respectively are

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [197]
+
– 50 k 500 k
SW
100 k
A
V1 +
22.2 k 10.53 k –
G(V1–V2)
50 k
V2 100 k

– 500 k
+

(a) 45, 95 (b) 50, 100

(c) 100, 200 (d) 90, 180
GATE(IN/2005/2M)
Q.79 Of the four characteristics given below, which are the major requirements for an instrumentation
amplifier?
P. High common mode rejection ratio
Q. High input impedance
R. High linearity
S. High output impedance
(a) P, Q and R only (b) P and R only
(c) P, Q and S only (d) Q, R and S only
GATE(EE-I/2015/1M)

Q.80 For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0, the
switch S is closed. The voltage Vc across capacitor at t = 1 millisecond is
1F

Vc
–
1k Vo
+
10V

In the figure shown above, the Op-amp is supplied with ±15 V.

(a) 0 Volt (b) 6.3 Volts
(c) 9.45 Volts (d) 10 Volts
GATE(EC/2006/2M)
Q.81 The input vi to a differentiator consists of a signal voltage vs = 10 sin (50 t) and a noise voltage vn =
0.1 sin (250 t). The signal-to-noise voltage ratio at the output of the differentiator
(a) decreases by a factor of 5 (b) decreases by a factor of 20
(c) increases by a factor of 5 (d) increases by a factor of 20
GATE(IN/1997/1M)
Q.82 An integrator circuit is shown in figure. The opamp is of type 741 and has an input offset current
iOS of 1µA. C is 1 µF and R is 1 MΩ. If the input Vi is a 1 kHz square wave of 1 V peak to peak, the

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [198]
output V0, under steady state condition, will be
C
R
–
Vi ios
+ Vo

(a) a square wave of 1 V peak to peak (b) a triangular wave of 1 V peak to peak
(c) positive supply voltage + Vcc (d) negative supply voltage – Vcc
GATE(IN/2003/1M)
Q.83 The op-amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-
voltage Vi = 1 mV is applied at the input at time t = 0 as shown. Assuming that the operational
amplifier is not saturated, the time constant (in millisecond) of the output voltage Vo is
C

R 1F
–

Vi 1k A=1000
+ +
1mV +
–
Vo
t =0 s
–

(a) 1001 (b) 101

(c) 11 (d) 1
GATE(EE-I/2015/2M)
Q.84 The circuit in figure is a

–
R R V0
+
Vin
C C

(a) low-pass filter (b) high-pass filter

(c) band-pass filter (d) band-reject filter
GATE(EC/2004/1M)
Q.85 The Op-amp circuit shown in figure is a filter. The type of filter and its cut-off frequency are
respectively

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [199]

10 K
10 K
–
v1 +
1 µF 1K

(a) high pass, 1000 rad/sec (b) low pass, 1000 rad/sec
(c) high pass, 10000 rad/sec (d) low pass, 10000 rad/sec
GATE(EC/2005/2M)

Statement for Linked Answer Questions 86 & 87:

Consider the Op-Amp circuit shown in the figure.
R

R
–
Vi Vo
+
R
C

Q.86 The transfer function V0 (s) /V1 (s) is

1 − sRC 1 + sRC
(a) (b)
1 + sRC 1 − sRC

1 1
(c) (d)
1 − sRC 1 + sRC

GATE(EC/2007/2M)
Q.87 If Vi =V1 sin (ωt) and V0 = V1 sin (ωt + φ), then the minimum and maximum values of φ (in radians)
are respectively.
(a) – π / 2 and π / 2 (b) 0 and π / 2
(c) – π and 0 (d) – π / 2and 0
GATE(EC/200/M)
Q.88 The circuit shown is a

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [200]
R2

R1 +5V
C
+ –
input
+
– (output)
+
–
–5V

1
(a) low pass filter with ω3dB = rad / s
( R1 + R 2 ) C
1
(b) high pass filter with ω3dB = rad / s
R1C

1
(c) low pass filter with ω3dB = rad / s
R1C

1
(d) high pass filter with ω3dB = rad / s
( R1 + R 2 ) C

GATE(EC/2012/2M)
Q.89 The circuit in figure is a
R2
C1 R1 C2
–
+ + Vo
~

1 1
(a) band-pass filter with lower cut-off ωL = and higher cut off ωH =
R1C1 R2C2

1 1
(b) band-reject filter with lower cut-off ωL = and higher cut off ωH =
R1C1 R2C2

1 1
(c) band-pass filter with lower cut-off ωL = and higher cut off ωL =
R2C2 R2C2

1 1
(d) band-reject filter with lower cut-off ωL = and higher cut off ωL =
R2C2 R1C1
GATE(IN/2004/2M)
Q.90 The op-amp circuit shown below is that of a

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [201]

+
Vin 1µF – Vo
1k
1k
1k

(a) low-pass filter with a maximum gain of 1 (b) low-pass filter with a maximum gain of 2
(c) high-pass filter with a maximum gain of 1 (d) high-pass filter with a maximum gain of 2
GATE(IN/2008/2M)
Q.91 The circuit shown in the figure is

R R
–
vi vo
+
C
R

(a) an all-pass filter (b) a bandpass filter

(c) a highpass filter (d) a lowpass filter
GATE(IN/2009/1M)
Q.92 An active filter is shown in the adjoining figure. The dc gain and the 3 dB cut-off frequency of the
filter respectively, are, nearly
C2

R2
R1
Vi –
Vo
+

R1 = 15.9 kΩ, R2 = 159 kΩ and C2 = 1.0 nF

(a) 40 dB, 3.14 kHz (b) 40 dB, 1.00 kHz
(c) 20 dB, 6.28 kHz (d) 20 dB, 1.00 kHz
GATE(IN/2010/2M)
Q.93 The ideal op-amp based circuit shown below acts as a

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [202]

1 M 1 M 0.5 F 0.5 F

500 k

VI 1 F
–
+
VO

(a) low-pass filter (b) high-pass filter

(c) band-pass filter (d) band-reject filter
GATE(IN/2011/2M)
Q.94 The circuit shown is a
R2

C R1 +5V
+ –
input
+
– (output)
+
–
–5V
1 1
(a) low pass filter with f3dB = rad / s (b) high pass filter with f3dB = rad / s
( R1 + R 2 ) C R1C

1 1
(c) low pass filter with f3dB = rad / s (d) high pass filter with f3dB = rad / s
R1C ( R1 + R 2 ) C
GATE(IN/2012/2M)
Q.95 A major advantage of active filters is that they can be realized without using
(a) op-amps (b) inductors
(c) resistors (d) capacitors
GATE(EE/1997/1 M)
Q.96 Match the circuits and their operation.
Circuit Function

VCC

–
Vo
~ Vin +

A. 1. High-pass filte

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [203]

–
Vo
Vin ~ +

B. 2. Amplifier

–
Vo
~ Vin +

C. 3. Comparator

4. Low-pass filter
Codes :
A B C A B C
(a) 3 4 1 (b) 4 3 2
(c) 3 4 2 (d) 4 3 1
GATE(EE/1998/2M)
Q.97 In the active filter circuit shown in figure, a pair of poles will be realized with ω0 equal to
R1 = 200 k

1 nF 1 nF
R2
–
+

(a) 1000 rad/s (b) 100 rad/s

(c) 10 rad/s (d) 1 rad/s
GATE(EE/2004/2 M)
Q.98 A low-pass filter with a cut-off frequency of 30 Hz is cascaded with a high-pass filter with a cut-off
frequency of 20 Hz. The resultant system of filters will function as
(a) an all-pass filter (b) an all-stop filter
(c) a band stop (band-reject) filter (d) a band-pass filter
GATE(EE/2012/2 M)
Q.99 The circuit shown is a

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [204]
R2

R1 +5V
C
+ –
input
+
– (output)
+
–
–5V

1
(a) low pass filter with f 3dB = rad / s
( R1 + R 2 ) C
1
(b) high pass filter with f 3dB = rad / s
R1C

1
(c) low pass filter with f 3dB = rad / szs
R1C

1
(d) high pass filter with f 3dB = rad / s
( R1 + R 2 ) C
GATE(EE/2012/2 M)
Q.100
0.47µF

22k 22k
–
vo
vin ~ 0.47µF +

91k
82k

For the given low-pass circuit shown in the figure, the cutoff frequency in Hz will be_________.
GATE(IN/2014/2M)
Q.101 In the low-pass filter shown in the figure, for a cut-off frequency of 5kHz, the value of R2(in kΩ) is
–––––––
R2

C
1k 10nF
Vi –
R1 VO
+

GATE(EC-I/2014/1M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [205]
Q.102 The filters F1 and F2 having characteristics as shown in Figures (a) and (b) are connected as shown
in Figure (c).

Vo/Vi Vo/Vi F2
F1
Vi Vo Vi Vo
f1 f2
f f

(a) (b)
R/2

+Vsat
R –
F1
+
Vo
Vi F2 –Vsat
R

(c)
The cut-off frequencies of F1 and F2 are f1 and f2 respectively. If f1 < f 2,. the resultant circuit exhibits
the characteristic of a
(a) Band-pass filter (b) Band-stop filter
(c) All pass filter (d) High -Q filter
GATE(EE-II/2015/1M)
Q.103 The circuit shown below is an example of a
R2

Vin R1 +15V
– Vout
+
–15V

(a) low pass filter. (b) band pass filter.

(c) high pass filter. (d) notch filter.
GATE(EE-II/2016/1M)
Q.104 The operational amplifier is used in the non-linear mode in
(a) Integrators (b) Active filters
(c) Schmitt triggers (d) Instrumentation amplifiers
GATE(IN/1992/1M)
Q.105 If the input to the circuit of figure is sine wave, the output will be

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [206]

I/P –
+ O/P

(a) A half-wave rectified sine wave (b) A full wave rectified sine wave
(c) A triangular wave (d) A square wave.
GATE(EC/1990/2M)
Q.106 One input terminal of high gain comparator circuit is connected to ground and a sinusoidal voltage is
applied to the other input. The output of comparator will be.
(a) a sinusoid (b) a full rectified sinusoid
(c) a half rectified sinusoid (d) a square wave
GATE(EC/1998/1M)

Q.107 In the circuit shown below the switch (S) is closed whenever the input voltage (Vin) is positive and
open otherwise
R R
R
R
 0.5R
+ 
S Vout
Vin +

The circuit is a
(a) Low pass filter (b) Level shifter
(c) Modulator (d) Precision rectifier
GATE(IN/2007/2M)
Q.108 For a given sinusoidal input voltage, the voltage waveform at point ‘P’ of the clamper circuit shown
in figure will be

C +12V
–
RL

~ Vin
+
–12V
P

Vin
Vin

t
t
(a) (b)

Vin

t
12V

(c) (d) –0.7V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [207]
GATE(EE/2006/1 M)
Q.109 The transfer characteristic of the Op-amp circuit shown in figure is
R

R
+Vsat
R +Vsat
vi –
R
–
+ vo
R +
–Vsat
R
–Vsat

Vo
–1 Vo 1

Vi Vi
(a) (b)

Vo Vo

Vi Vi
1
–1

(c) (d)
GATE (EE-III/2014/2 M)
Q.110 The approximate transfer characteristic for the circuit shown below with an ideal operational amplifier
and diode will be
Vss
Vin +

–
D
–Vss
V0
R

Vo Vo

(a) Vin (b) Vin

Vo Vo

(c) Vin (d) Vin

GATE(EE-I/2017/2M)
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [208]
Q.111 The circuit of figure uses an ideal op-amp. For small positive values of Vin, the circuit works as

R
–
Vin + VOut

(a) A half wave rectifier (b) A differentiator

(c) A logarithmic amplifier (d) An exponential amplifier
GATE(EC/1992/2M)

Q.112 In the Op-Amp circuit shown, assume that the diode current follows the equation I = Is exp (V/VT).
For Vi = 2V, Vo = Vo1 and for Vi =4 V, Vo = Vo2 . The relationship between Vo1 and Vo2 is

Vi –
2k Vo
+

(a) Vo2 = 2 Vo1 (b) Vo2 = e2 Vo1

(c) Vo2 = Vo1 ln 2 (d) Vo 1 – Vo2 = VT ln 2
GATE(EC/2007/2M)
Q.113 In the circuit shown below what is the output voltage (Vout) if a silicon transistor Q and an ideal
op-amp are used?

+
1 k VBE –
–
Vout
+
5V +
–

(a) –15 V (b) –0.7 V

(c) + 0.7 V (d) +15 V
GATE(EC/2013/1M)
Q.114 In the circuit shown below what is the output voltage (Vout) in Volts if a silicon transistor Q and an
ideal op – amp are used ?

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [209]

+15 V
Q
1 k
–

+ Vout
5V +
–
–15 V

(a) – 15 (b) – 0.7
(c) +0.7 (d) +15
GATE(IN/2013/1M)
Q.115 In the circuit shown below what is the output voltage (Vout) in Volts if a silicon transistor Q and an
ideal op- amp are used ?

+15 V
Q
1 k
–

+
5V +
–
–15 V

(a) –15 (b) –0.7

(c) +0.7 (d) +15
GATE(EE/2013/1 M)
Q.116 The most commonly used amplifier in sample and hold circuits is
(a) a unity gain inverting amplifier (b) a unity gain non-inverting amplifier
(c) an inverting amplifier with gain of 10 (d) an inverting amplifier with gain of 100
GATE(EC/2000/1M)
Q.117 A sample-and hold circuit has two buffers, one at the input and the other at the output. The primary
requirements for the buffers are
(a) the input buffer should have high slew rate and the output buffer should have low bias current
(b) the input buffer should have low bias current and the output buffer should have high slew rate
(c) both the buffers should have low bias currents
(d) both the buffers should have high slew rate
GATE(IN/2001/1M)
Common Data for Questions 118 and 119 :
The figure shows a sample-and-hold circuit using a MOSFET as a switch. The threshold voltage of
the MOSFET is +2 V. It has zero leakage current in the off state. Assume that the capacitor is ideal.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [210]
Vg
+12 V
–

+ vo
vi C –12 V
Vsub 1 nF

Q.118 The input voltage vi ranges from –5 V to +5 V. Appropriate values of Vsub , of Vg during sampling,
and of Vg during hold are, respectively,
(a) +12 V, ≥ +7 V, and ≤ –3 V (b) –12 V, ≥ +3 V, and ≤ –7 V
(c) +12 V, ≥ +3 V, and ≤ –7 V (d) –12 V, ≥ +7 V, and ≤ –3 V
GATE(IN/2009/2M)
Q.119 The circuit is used at a sampling rate of 1 kHz, with an A/D converter having a conversion time of
200 µs. The op amp has an input bias current of 10 nA. The maximum hold error is
(a) 1 mV (b) 2 mV
(c) 5 mV (d) 10 mV
GATE(IN/2009/2M)
Q.120 For a given sample-and- hold circuit, if the value of the hold capacitor is increased, then
(a) droop rate decreases and acquisition time decreases
(b) droop rate decreases and acquisition time increases
(c) droop rate increases and acquisition time decreases
(d) droop rate increases and acquisition time increases
GATE (EC-IV/2014/1M)
Q.121 In the circuit of figure Vo is
+ 15 V
–
R
+ V0
+1V – 15 V

(a) –1 V (b) 2 V
(c) +1 V (d) +15 V
GATE(EC/2000/1M)
Q.122 The voltage comparator shown in figure can be used in the analog-to-digital conversion as
V1 +
V0
V2 –

(a) a 1-bit quantizer (b) a 2-bit quantizer

(c) a 4-bit quantizer (d) a 8-bit quantizer
GATE(EE/2004/1 M)
Q.123 In figure if the input is a sinusoidal signal, the output will appear as shown in

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [211]

Vout
Vout

t
(a) t (b)

Vout Vout

t t
(c) (d)
GATE(EE/2005|2 M)
Q.124 The circuit shown in figure is that of
–
Vin + V0
R1

R2

(a) A non-inverting amplifier (b) An inverting amplifier

(c) An oscillator (d) A schmitt trigger
GATE(EC/1996/1M)
Q.125 Consider the Schmitt trigger circuit shown below.
+15V
10k

–
Vi
+ Vo

10k
10k

–15V
A triangular wave which goes from –12 V to 12 V is applied to the inverting input of the op-amp.
Assume that the output of the op-amp swings from + 15V to 15 V. The voltage at the non-inverting
input switches between .
(a) – 12V and + 12 V (b) – 7.5V and + 7.5V
(c) – 5V and + 5 V (d) 0 V and 5 V
GATE(EC/2008/2M)
Q.126 The input output characteristics of a Schmitt trigger is given in figure. The noise margin of the Schmitt
trigger is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [212]
5V

1V 3V Vi
(a) 1 (b) 2 V
(c) 3 V (d) 4 V
GATE(IN/2003/1M)
Q.127 In the op-amp circuit shown below, the input voltage vin is gradually increased from −10 V to +10V.
Assuming that the output voltage vout saturates at −10 V and +10 V, vout will change from

Vin –
Vo
+

9k
1k

(a)
−10 V to + 10 V when vin= −1V (b) −10 V to + 10 V when vin= +1V
(c) +10 V to − 10 V when vin= −1V (d) +10 V to − 10 V when vin= +1V
GATE(IN/2008/2M)
Q.128 An ideal opamp circuit and its input waveform are shown in the figures. The output waveform of this
circuit will be
1k 6V
3 Vin –
2 Vout
1 +
t4 t5 t6 2k
v 0 t – 3V
t t t3
–1 1 2
–2 1k

–3

6
6
v
v
t3 t6
t3 t6 0
0 t
t
(a)
–3 (b)
–3
6 6

v v
t6
0 0
t2 t4 t t2 t4 t6
t
–3
(b) (d) –3
GATE(EE/2009/2M)
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [213]
Q.129 The figures show an oscillator circuit having an ideal Schmitt trigger and its input-output characteristics.
The time period (in ms) of vo (t) is__________.

v(t)
o
5V

output
10k 2V 3V
1µF input

/
GATE(IN/2014/2M)
Q.130 In the bistable circuit shown, the ideal op-amp has saturation levels of ± 5 V. the value of R1 (in kΩ)
that gives a hysteresis width of 500 mV is .............

R2 = 20k

R1
+
Vout
–
Vin +
–

GATE(EC-II/2015/1M)
Q.131 For the operational amplifier circuit shown, the output saturation voltages are ±15V. The upper and
lower threshold voltages for the circuit are, respectively.
+ – Vout
Vin
– + 10 k

5 k
+ 3V
–

(a) +5V and – 5V (b) +7V and –3V

(c) +3V and –7V (d) +3V and –3V
GATE(EC-I/2017/1M)
Q.132 The circuit of a Schmitt trigger is shown in the figure. The zener-diode combination maintains the
output between ±7V. The width of the hysteresis band is _________V.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [214]
+15V

vi
– 1 k vo

+
Vz
10 k
–15V
Vz

0.5 k

+2V
GATE(IN/2017/2M)
Q.133 For the circuit shown below,
R

R +12V
– +12V
vi –
+ vo
R –12V +
R –12V

R R

the CORRECT transfer characteristic is

Vo +12V +12V Vo

+6V +6V
–6V –6V
Vi Vi

–12V –12V
(a) (b)
Vo
Vo
+12V +12V

–6V +6V –6V +6V

Vi Vi

–12V –12V
(c) (d)
GATE(EE/2011/1 M)
Q.134 In the following astable multivibrator circuit, which properties of vo(t) depend on R2 ?

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [215]
R1

–
v0 (t)
+
R3
C
R2 R4

(a) Only frequency (b) Only amplitude

(c) Both amplitude and frequency (d) Neither amplitude nor frequency
GATE(EC/2009/2M)
Q.135 In the circuit shown in figure the input voltage Vi is a symmetrical saw-tooth wave of average value
zero, positive slope and peak-to-peak value 20 V. The average value of the output, assuming an ideal
operational amplifier with peak to-peak symmetrical swing of 30 V, is
Vin –
Vo
+

10k
5k

(a) 5 V (b) 10 V
(c) –5 V (d) 7.5 V
GATE(IN/2005/2M)

Q.136 The input-output characteristic of a Schmitt trigger has a hysteresis band of + 0.1 V. If the input
voltage is 5 sin (1000 πt), the delay between the corresponding zero cross-over points of the output
and input signals is
(a) 6.37 µs (b) 0.02 µs
(c) 63.7 µs (d) 2.0 µs
GATE(IN/2005/2M)
Q.137 For the oscillator circuit shown in figure the expression for the time period of oscillations can be
given by (where τ = RC)

C R
–
+ V0
R

(a)
τ n 3 (b) 2τ n 3
(c) τ n 2 (d) 2τ n 2
GATE(EE/2001/2 M)
Q.138 A relaxation oscillator is made using op-amp as shown in figure. The supply voltages of the op-amp

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [216]
are +12V. The voltage waveform at piont ‘P’ will be
R1

C R2
–
Vp Vo
+
P D1
2k
10k

10k D2

6 10

6
10
(a) (b)

6 10

6
10

(c) (d)

GATE(EE/2006/2 M)
Q.139 The switch S in the circuit of the figure is initially closed. It is opened at time t = 0. You may neglect
the Zener diode forward voltage drops. What is the behavior of Vout for t > 0 ?
+10V

1k +10V
–
Vout
0.01µF
10k 5.0V
–10V
S
5.0V
100k

–10V
(a) It makes a transition from –5 V to + 5V at t = 12.98 µs
(b) It makes a transition from – 5 V to + 5 V at t = 2.57 µs
(c) It makes a transition from +5 V to –5 V at t = 12.98 µs
(d) It makes a transition from + 5 V to – 5 V at t = 2.57 µs
GATE(EE/2007/2 M)
Q.140 The circuit shown represents

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [217]

vi C2 +12 V
–
R2 vo
+
–12 V
– 2V R1
C1
(a) A bandpass filter (b) A voltage controlled oscillator
(c) An amplitude modulator (d) A monostable multivibrator
GATE (EC-IV/2014/1M)
Q.141 An oscillator circuit using ideal op-amp and diodes is shown in the figure
R
+5V
–
C Vo
+ –5V

3k D1

1k D2
1k

∆t1 −∆t 2

The time duration for +ve part of the cycle is ∆t1 and for –ve part is ∆t2. The value of e RC
will

be________.
GATE (EE-II/2014/2M)
Q.142 The saturation voltage of the ideal op-amp shown below is ± 10 V. The output voltage Vo of the
following circuit in the steady-state is
1 k

– +10 V
0.25F
+ Vo

–10 V 2 k

2 k

(a) square wave of period 0.55 ms (b) triangular wave of period 0.55 ms
(c) square wave of period 0.25 ms (d) triangular wave of period 0.25 ms
GATE (EE-II/2015/2M)
Q.143 In the op-amp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage Vo to +5V or –5V.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [218]
The switch S is initially closed and is opened at time t = 0.
+10V

S
100 F +10V
t=0
– 470 
VO
10 k +
–10V Z1

–10V
4k Z2
1k

0V 0V
The time t = t1(in seconds) at which Vo changes state is ..........
GATE (EC-II/2016/2M)
Q.144 Assume that the op-amp of figure is ideal. If vi is a triangular wave, then v0 will be

C R
–
Vin + Vo

(a) square wave (b) triangular wave

(c) parabolic wave (d) sine wave
GATE(EC/2000/1M)
Q.145 An ideal sawtooth voltage waveform of frequency 500 Hz and amplitude 3V is generated by charging
a capacitor of 2 µF in every cycle. The charging requires
(a) constant voltage source of 3 V vor 1 ms (b) constant voltage source of 3 V for 2 ms
(c) constant current source of 3 mA for 1 ms (d) constant current source of 3 mA for 2 ms
GATE(EC/2003/2M)
Q.146 An amplifier of gain 10, with a gain-bandwidth product of 1 MHz and slew rate of 0.1 V/µs is fed
with a 10 kHz symmetrical square wave of ±1V amplitude. Its output will be
(a)
+ 10 V amplitude square wave (b) + 2.5 V amplitude square wave
(c) + 10 V triangular square wave (d) + 2.5 V triangular square wave
GATE(IN/2002/2M)
Q.147 IC 555 in the adjacent figure is configured as an astable multivibrator. It is enabled to oscillate at
t = 0 by applying a high input to pin 4. The pin description is : 1 and 8 - supply; 2-trigger; 4-reset;
6-threshold; 7-discharage. The waveform appearing across the capacitor starting from t = 0, as
observed on a storage CRO is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [219]
+VCC

RA 10k

7 8
RB 10k
IC555

2,6
C 4 1

(a) (b)

(c) (d)

GATE(EE/2007/2 M)
Q.148 An astable multivibrator circuit using IC 555 timer is shown below. Assume that the circuit is oscillating
steadily.

9V

30 K
4 8
(Reset) (Supply)
6 (Threshold)
(output) 3
10 K
(Gnd)
2 (Trigger) 1
(Discharge)
12 K 7

VC .01 µF

The voltage Vc across the capacitor varies between.
(a) 3V to 5 V (b) 3V to 6 V
(c) 3.6 V to 6 V (d) 3.6 V to 5 V
GATE(EC/2008/2M)
Q.149 An astable multivibrator circuit using a 555 IC is given in the following figure. The frequency of
oscillations is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [220]
VCC – 5V

8 4

I – 5 mA 3
6 output
Vth
555
2
Vtring 7
discharge

C – 0.1 µF
1

(a) 20 kHz (b) 30 kHz

(c) 40 kHz (d) 45 kHz
GATE(IN/2006/2M)

Q.150 A 555 astable multivibrator circuit is shown in the figure below :

5V

RA reset
10k

Discharge
10k RB Out
Trigger
Vc thereshold

C Ground
1F

If RB is shorted, the waveform at VC is

Vcc
Vc
2/3Vcc
2/3Vcc
1/3Vcc 1/3Vcc
t
(a) 0 t (b) 0
Vc Vc
2/3Vcc
2/3Vcc
1/3Vcc 1/3Vcc
(c) 0
t
(d) 0 t

GATE(IN/2007/1M)

Q.151 The circuit of figure shows a 555 Timer IC connected as an astable multivibrator. The value of the
capacitor C is 10 nF. The values of the resistors RA and RB for a frequency of 10 kHz and a duty cycle

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [221]
of 0.75 for the output voltage waveform are
VCC

RA

Th
RB
Vout
Tr
R1
C 555
Timer
IC
Discharge

(a) RA = 3.51 kΩ, RB = 3.62 kΩ (b) RA = 3.62 kΩ, RB = 7.25 kΩ

(c) RA = 7.25 kΩ, RB = 3.62 kΩ (d) RA = 7.25 kΩ, RB = 7.25 kΩ
GATE(EE/2003/2 M)
Q.152 In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the
output pin 3 is ............
VCC

RA = 2.2 k 8 4
VCC Res
7
Disch
RB = 4.7 k 555Timer
6 3
Thresh Out

2
Trig
Grid
C =0.022F 1

GATE(EC-III/2016/1M)
Q.153 The output voltage Vo of the circuit shown in figure is
10 K
5K
– +
+ + V
– 2V – 0
10 K 100 K

(a – 4 V (b) 6 V
(c) 5 V (d) –5.5 V
GATE(EC/1997/2M)
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [222]
.154 Consider the constant current source shown in the figure below. Let β represents the current gain of
the transistor.
+VCC

Vref
–
+ R2

RL
R1

The load current Io through RL is

 β + 1  Vref  β  Vref
(a) Io =   (b) Io =  
 β  R  β + 1 R

 β + 1  Vref  β  Vref
(c) Io =   (d) Io =  
 β  2R  β + 1 2R
GATE(EC-I/2016/1M)
Q.155 Assume that the operational amplifier in figure is ideal. The current, I, through the 1 K ohm resistor
is .....
2 k

– 1 k
+
2 mA  I 2 K

(a) – 4 mA (b) – 2 mA
(c) 0 mA (d) 4 mA
GATE(EC/1992/2M)
Q.155 Ans.(a)Q.156 In figure, assume the Op-amps to be ideal. The output Vo of the circuit is:

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [223]
10 mH
10 F
10 
Vs –
–
+  + Vo
Vs=10 cos(100 t)

(a) 10 cos(100t) (b) 10∫ cos (100t )

0

t
d
(c) 10−4 ∫ cos (100τ ) dt (d) 10−4 cos (100t )
0
dt

GATE(EC/2001/2M)
Q.157 Group I gives two possible choices for the impedance Z in the diagram. The circuit elements in Z
Vo
satisfy the condition R2 C2 > R1 C1 . The transfer function represents a kind of controller. Match
V1

the impedances in Group I with the types of controllers in Group II.

C1
Z

Vin –
R1 Vo
+

Group I Group II

Q. 1. PID Controller
R2 C2
C2

R. 2.Lead compensator

R2

3. Lag compensator

(a) Q - 1, R - 2 (b) Q - 1, R - 3
(c) Q - 2, R - 3 (d) Q - 3, R - 2
GATE(EC/2008/2M)
Q.158 In the circuit shown below, the op-amp is ideal, the transistor has VBE = 0.6 V and β = 150. Decide

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [224]
whether the feedback in the circuit is positive or negative and determine the voltage V at the output
of the op-amp.
10 V

5 k

V
+
–
1.4 k
5V

(a) Positive feedback, V = 10 V (b) Positive feedback, V = 0 V

(c) Negative feedback, V = 5 V (d) Negative feedback, V = 2 V
GATE(EC/2009/2M)
Q.159 Pick up the correct relationship for the circuit shown in fig.

–
e0
+ I R1
ei
+ –
R2

R2
(a) eo = ei (b) eo = ei
R1

ei ei
(c) I = (d) I =
R2 R1

GATE(IN/1998/1M)
Q.160 The output voltage vo in the circuit in figure is
+V
R2

R1 R1
_ –
+ + Vo

R(1+) R

R2 R
(a) V δ (b) 2 V δ
R R1

R2 R2
(c) Vδ (d) V
R1δ R (1+ δ )

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [225]
GATE(IN/2004/2M)
v 
Q.161 The gain  o  of the amplifier circuit shown in figure is
 vi 
R 3R
–
+ +
4R
RL Vo
R –
Vi +– –
+

(a) 8 (b) 4
3RL
(c) – 4 (d)
R

GATE(IN/2004/2M)
Q.162 In the circuit shown in figure assuming ideal diode characteristics with zero forward resistance and
0.7 V forward drop, the average value of V0 when the input waveform is as shown, is

Vin D2
2 k
+1
0 1 k D1
T T –
2 t Vin
–1
+ V0

(a) –0.7 V (b) –1.0 V

(c) –2.0 V (d) – 2.7 V
GATE(IN/2005/2M)
Q.163 A dual op-amp instrumentation amplifier is shown below. The expression for the output of the
amplifier is given by
V1 +
Vout
–
R2
R1
c
R1
–
R2
+ V2

   2 R2 
(a)  +  ( v2 − v1 ) (b)
v0 = v0 =
1 +  ( v2 − v1 )
   R1 

2 R2  2 R1 
(c) v0
= ( v2 − v1 ) (d) v0 =
1 +  (v2 − v1 )
R1  R2 

GATE(IN/2006/2M)
Q.164 When light falls on the photodiode shown in the following circuit, the reverse saturation current of
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [226]
the photodiode changes from 100 µA to 200 µA
 k

+
 Vout

Assuming the Op-amp to be ideal, the output voltage, Vout , of the circuit
(a) Does not change (b) Change from 1 V to 2 V
(c) Change from 2 V to 1 V (d) Change from –1 V to – 2 V
GATE(IN/2007/1M)
Q.165 Consider the linear circuit with an ideal op-amp shown in the figure below.
1 2

1´ 2´
1K
vi –
vo
+

The Z-parameters of the two port feedback network are Z11= Z22= 11 kΩ and Z12= Z21 = 1kΩ . The
gain of the amplifier is
(a) +110 (b) + 11
(c) – 1 (b) – 120
GATE(IN/2007/1M)
Q.166 In the circuit shown, the Zener diode has ideal characteristics and a breakdown voltage of 3.2 V. The
output voltage V0 for an input voltage Vi = + 1 V is closest to
10k

10k
–
Vi
1 k
Vo
+

(a) –10 V (b) – 6.6 V

(c) –5 V (d) – 3.2 V
GATE(IN/2009/2M)
Q.167 The transfer characteristics of the circuit drawn below is oserved on an oscilloscope used in XY
mode. The display on the oscilloscope is shown on the right hand side. Vi is connected to the X input
with a setting of 0.5 V/div, and Vo is connected to the Y input with a setting of 2 V/div. The beam is
positioned at the origin when Vi is zero.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [227]

Z1 Z2

1k
Vo
Vi = sin 100t V ~

Assuming that the opamp is ideal and the zener diodes have forward biased voltage drop of 0.7 V, the
values of reverse break-down voltage of Z1 and Z2 are, respecitvely,
(a) 3.3 V and 5.3 V (b) 4.7 V and 6.7 V
(c) 6.7 V and 4.7 V (d) 5.3 V and 3.3 V
GATE(IN/2011/2M)
Q.168 Assuming base-emitter voltage of 0.7 V and β = 99 of transistor Q1, the output voltage Vo in the ideal
opamp circuit shown below is
5V
33 k
Q1 100
– 5V
+
VO
1V +–

(a) –1 V (b) – 1/3.3 V

(c) 0 V (d) 2 V
GATE(IN/2011/2M)
Statement for Linked Answer Questions 169 and 170 :
M1, M2 and M3 in the circuit shown below are matched N-channel enhancement mode
MOSFETs operating in saturation mode, forward voltage drop of each diode is 0.7 V, reverse
leakage current of each diode is negligible and the opamp is ideal.

+5V 1k
D1 D2
1mA
IS
Vo

M1 M2 M3
–5V
Q.169 The current IS in the circuit is
(a) – 1mA (b) 0.5 mA
(c) 1 mA (d) 2 mA
GATE(IN/2011/2M)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [228]
Q.170 For the computed value of current IS, the output voltage VO is
(a) 1.2 V (b) 0.7 V
(c) 0.2 V (d) –0.7 V
GATE(IN/2011/2M)
Q.171 A signal vi(t) =10 + 10 sin 100πt + 10 sin 4000πt +10sin 100000πt is supplied to a filter circuit
(shown below) made up of ideal op-amps. The least attenuated frequency component in the output
will be
0.1F
2k 1F

1 k 0.1F
– 750 0.1F
–
+
+ Vo
Vi(t)
~

(a) 0 Hz (b) 50 Hz
(c) 2 kHz (d) 50 kHz
GATE(IN/2013/2M)
Q.172 The circuit below incorporates a permanent magnet moving coil milli-ammeter of range 1 mA
having a series resistance of 10 kΩ. Assuming constant diode forward resistance of 50Ω, a forward
diode drop of 0.7 V and infinite reverse diode resistance for each diode, the reading of the meter in
mA is
–
mA
+
10k

1 k
–
+
5V
50Hz
~ V0

(a) 0.45 (b) 0.5
(c) 0.7 (d) 0.9
GATE(IN/2013/2M)
Q.173 The following circuit has R = 10kΩ, C = 10µF. The input voltage is a sinusoidal at 50 Hz with an rms
value of 10V. Under ideal conditions, the current is from the source is

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [229]
R

is 10 k

VS = 10V rms,
+
OPAMP

50 Hz
–

10 k

R
10 µF C

(a) 10π mA leading by 90° (b) 20π mA leading by 90°

(c) 10 mA leading by 90° (d) 10π mA lagging by 90°
GATE(EE/2009/2 M)
Q.174 In the circuit shown, assume that the opamp is ideal. The bridge output voltage Vo (in mV) for
δ = 0.05 is ...........

100 +
1V
250(1+) 250(1–) –
–V +
o

250 (1–) 250(1+)

100 50

GATE(EC-I/2015/2M)

Q.175 The following signal Vi of peak voltage 8 V is applied to the non-inverting terminal of an ideal
opamp. The transistor has VBE = 0.7 V, β = 100; VLED = 1.5 V, VCC = 10 V and –VCC= –10 V

10V 10V

100k
8 k Vi

+VCC 6V
LED 4V
–
2V
t
+ 15 k
2 k Vi –2V
–VCC –4V
. –6V

The number of times the LED glows is ..........

GATE(EC-I/2016/1M)
Q.176 The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [230]
by-N counter (comprising ÷2 , ÷4, ÷8, ÷16 outputs) is sketched below. The synthesizer is excited
with a 5 kHz signal (Input 1). The free-running frequency of the PLL is set to 20 kHz. Assume that
the commutator switch makes contacts repeatedly in the order 1-2-3-4.
+VCC

Input 1 Phase Low Pass

Detector Filter
Amplifier

VCO
1 2
2 4
3 8 C –VCC
R
4 16

Synthesizer
output

The corresponding frequencies synthesized are:

(a) 10 kHz, 20 kHz, 40 kHz, 80 kHz (b) 20 kHz, 40 kHz, 80 kHz, 160 kHz
(c) 80 kHz, 40 kHz, 20 kHz, 10 kHz (d) 160 kHz, 80 kHz, 40 kHz, 20 kHz
GATE(EC-I/2016/1M)
Q.177 A p-i-n photodiode of responsivity 0.8 A/W is connected to the inverting input of an ideal opamp
as shown in the figure, +VCC = 15 V, –VCC = –15V, Load resistor RL = 10 kΩ. If 10 µW of power is
incident on the photodiode, then the value of the photocurrent (in µA) through the load is ..............
8 k 1 M

+VCC
–
V0
+
1 M
–VCC
10 k

+VCC
GATE(EC-I/2016/2M)
Q.178 The comparators (output = ‘1’, when input ≥ 0 and output =‘0’, when input < 0), exclusive-OR
gate and the unity gain low-pass filter given in the circuit are ideal. The logic output voltages of
the exclusive-OR gate are 0 V and 5 V. The cutoff frequency of the low-pass filter is 0.1 Hz. For
V1 = 1 sin (3000t + 36º) V and V2 = 1 sin (3000t) V, the value of Vo in volt is ............

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [231]
V1 +
–

Low-pass
filter V0
V2 +
–

GATE(IN/2016/2M)
Q.179 In the circuit given below, the opamp is ideal. The input Vx is a sinusoid. To ensure Vy = Vx, the value
of CN in picofarad is ...........
10 k

1 k
–
Vy +
Vx
1 k
1 nF
CN
GATE(IN/2016/2M)
Q.180 The photo diode in the figure below has an active sensing area of 10 mm2, a sensitivity of 0.5 A/W
and a dark current of 1 µA. The i-to-v converter has a sensitivity of 100 mV/µA. For an input light
intensity of 4 W/m2, the output Vo in volt is ..............
Light

i-to-v
converter V0

Photo
diode 176
GATE(IN/2016/2M)
Q.181 In the circuit below, the opamp is ideal and the sensor is an RTD whose resistance Rθ = 1000 (1 +
0.004 θ) Ω, where θ is temperature in °C. The output sensitivity in mV/°C is ..........

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [232]

R =)

1k
–
+ V0
– 10k
5V +
10k

GATE(IN/2016/2M)
Q.182 In the given circuit, assume that the op-amp is ideal and the transistor has a β of 20. The current I0 (in
µA) flowing through the load ZL is ________.
5V

10.5 k

–
 = 20
2V +

ZL

Io

GATE(IN/2018/1M)
Q.183 For the circuit shown below, assume that the OPAMP is ideal

R R

R
–
+ vo
2R
vs
2R
Which one of the following is TRUE?
(a) v0 = vs (b) v0 = 1.5vs

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [233]
(c) v0 = 2.5vs (d) v0 = 5vs
GATE(EE-II/2017/2M)
Q.184 The two-input voltage multiplier, shown in the figure, has a scaling factor of 1 and produces voltage
output. If V1 = + 15 V and V2 = + 3 V, the value of Vo in volt is _________.
V2

R Multiplier

V1 R
– V0
+

GATE (IN/2017/2M)
Q.185 The circuit given uses ideal opamps. The current I (in µA) drawn from the source vs is (up to two
decimal places) _______.
10.1 k

20.0 k 20.0 k
I
–
vs = 1V 10.0 k –
+ 20.0 k +

GATE(IN/2018/2M)
Q.186 In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors Q1 Q2…..,
Q32 are identical in all respects and have infinitely large values of common – emitter current gain (β).
The collector current (Ic) of the transistors is related to their base-emitter voltage (VBE) by the relation
IC = IS exp (VBE/VT), where Is is the saturation current. Assume that the voltage VP shown in the figure
is 0.7 V and the thermal voltage VT = 26mV.

20 k
+15V
+
20 k Vout
–
5 k –15V

VP

Q1 Q2 Q3 Q4

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [234]
The output voltage Vout (in volts) is
GATE(EC-II/2017/2M)
Q.187 In the circuit shown below, the input voltage Vin is positive. The current (I) - voltage (V) characteristics
v/ V
of the diode can be assumed to be I = Io e T under the forward bias condition, where VT is the

thermal voltage and I0 is the reverse saturation current. Assuming an ideal op-amp, the output voltage
Vout of the circuit is proportional to
1k
I

Vin –
Vout
+

(a) loge (Vin/VT) (b) 2Vin

Vin / VT 2
(c) e (d) Vin

GATE(IN/2019/1M)
Q.188 In the circuit shown below, all OPAMPS are ideal. The current 1 = 0 A when the resistance
R = ________ kΩ.
R

3k 12k
3k 3k
– –
I=0 + +
3k

+1V +
–

GATE(IN/2019/2M)
Q.189 The temperature of the coolant oil bath for a transformer is monitored using the circuit shown. It
contains a thermistor with a temperature-dependent resistance, Rthermistor = 2(1 + αT) kΩ. Where T is
the temperature in °C. The temperature coefficient α, is –(4 ± 0.25) %/°C. Circuit parameters: R1 = 1
kΩ, R2 = 1.3 kΩ, R3 = 2.6 kΩ. The error in the output signal (in V. rounded off to 2 decimal places)
at 150° C is ________.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [235]

+ Vout
Rthermistor
+ 3V
– –
R3
R1

R2

+ 0.1V
–

GATE(EE/2020/2M)
Q.190 Assuming that the opamp used in the circuit shown is ideal, the reading of the 1 Hz bandwidth,
permanent magnet moving coil (PMMC) type voltmeter (in volts) is _______.
10 k

20 k
–
+ V/M
Volt
meter
2sin(500t)
volts
~
GATE(IN/2020/2M)
Q.191 If the opamps in the circuit shown are ideal and Vx = 0.5 mV, the steady state value of V0 (in volts,
rounded off to two decimal places) is _______.
100 nF

– 20 
+ –
+– +
Vo
Vx

100  100  99.9 k

GATE(IN/2020/2M)
Q.192 Assuming ideal opamps, the output voltage at V1 in the figure shown (in volts) is ________.
1 k

1 k 5 k 3 k

1 k
– –
V1
+ +

3V +
– 2V +
–

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [236]
GATE(IN/2020/1M)
Q.193 Assume that the opamp in the circuit shown is ideal.
V
The value of s ( in kΩ ) is _______.
Ix

8 k

Ix
+

+ –
Vx
–

1 k 2 k

GATE(IN/2020/1M)
Q.194 A differentiator has a transfer function whose
(a) phase increase linearly with frequency (b) magnitude remains constant
(c) magnitude increases linearly with frequency (d) magnitude decreases linearly with frequency
GATE(IN/2020/1M)
Q.195 A circuit consisting of capacitors, DC voltage source and an amplifier having a voltage gain G = – 5
is shown in the figure. The effective capacitance across the nodes A and B (in μF, rounded off to one
decimal place) is ________.
2 µF

7 µF 4 µF
Gain,G
A
VS + 3 µF
–
B

GATE(IN/2020/2M)
Q.196 The components in the circuit shown below are ideal. If the op-amp is in positive feedback and the
input voltage Vi is a sine wave of amplitude 1 V, the output voltage Vo is
1 k

1V +5V
0 +
Vi Vo
–1V
–
–5V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [237]

(a) a non-inverted sine wave of 2 V amplitude (b) an inverted sine wave of 1 V amplitude
(c) a square wave of 5 V amplitude (d) a constant of either +5 or –5 V
GATE(EC/2020/1M)
Q.197 The components in the circuit given below are ideal. If R = 2 kΩ and C = 1 μF, the –3 dB cut-off
frequency of the circuit in Hz is
R

Vi(j) R
–

2C 2R + Vo(j)

(a) 14.92 (b) 34.46

(c) 59.68 (d) 79.58
GATE(EC/2020/2M)
Q.198 In the circuit shown below, all the components are ideal. If Vi is +2 V, the current Io sourced by the
op-amp is __________ mA.
1 k

+5V
1k
– lo

Vi +
1 k
–5V

GATE(EC/2020/1M)

Answers & Explanations of GATE Questions

Q.1 Ans.(d)
The operational amplifier use a differential input stage with a constant current source, mainly to have
very high input resistance.
Q.2 Ans.(c)
Gain of Op-amp,
AdB = 40 = 20 log A
⇒ A = 100
Output Op-amp,
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [238]
Vo = AVin
The slew rate of Op-amp,
dVo dVin
= A
dt max
dt

For sinusoidal input,

Vin = Vp sin ωt
To avoid slew-rate induced distortion,
dVp sin ωt
A ≤ SR
dt max

2π AVp f ≤ SR
Given, SR = 1V/µsec = 106 V/sec
⇒ 100 × Vp × 2π × 20 × 103 ≤ 106
1
⇒ Vp ≤
4π

⇒ Vp ≤ 79.5 mV
So, input signal should not exceed 79.5 mV
Q.3 Ans.(d)
A differential output high impedance signal source is connected to an instrumentation amplifier
through two shielded cables. The best way to obtain a high CMRR is to connect the cable shields to
power supply ground.
.4 Ans.(c)
Signal to noise ratio of amplifier is defined as
S S
= 10log10
N dB N

S V2 V
= 10log10 S 2 = 20log10 S
N dB VN VN

S 10
⇒ = 20log10 −3 = 20 log10 104 = 80dB
N dB 10

Q.5 Ans.(b)
Given, Vin = 1 sin ωt
Gain, A = 10
Slew rate, SR = 1 /µ sec

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [239]
Output voltage of Op-amp, Vo = A Vin
⇒ Vo = 10 sin ωt
Slew Rate of Op-amp, is defined as
dVo d
⇒ = (10sin ωt) = |10ω cos ωt|max = 10ω
dt max dt max

To avoid slew-rated induced distortion in output,

dVo
≤ S.R
dt max

⇒ 10ω ≤ S.R
⇒ 20πf ≤ S.R
1 × 106
⇒ f ≤
10 × 2π

⇒ f ≤ 15.92 kHz
∴ Maximum allowable frequency of input for undistored output is 15.92 kHz.
Q.6 Ans.(c)
+ 15 V
–
A oL V0
+
– 15 V

Given input offset voltage, Vi

Vo = AOLVio

Given , AOL = 104
Vio = 5 × 10–3 V
Vo = 104 × 5 × 10–3 = 50V
Output of Op-amp can not be more than supply voltage.
So, Vo = + 15V or – 15V
Q.7 Ans.(d)

 4V

 4V
0.4 s

The slew rate of Op-amp is defined as the maximum rate of change of output voltage.
From waveform of output voltage,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [240]

dVo 4 − (−4)
SR = = = 40V/µsec
dt max
0.2 µ sec.

Q.8 Ans.(b)
Common mode gain of Amplifier,
Vo,cm 0.001 × 10−3
Acm = = = 0.0002
Vi,cm 5 × 10−3

Differential mode gain of amplifier,

Vo,d 50 × 10−3
Ad = = = 0.5×103
Vi,d 100 × 10−6

CMRR of amplifier, is given by

Ad
CMRR =
A cm

0.5 × 103
⇒ CMRR = = 2.5 × 106
0.0002

In dB, CMRRdB = 20 log 2.5 × 106 = 127.95 dB

None of the options is correct. Nearest answer is in option (D).
Q.9 Ans.(c)
The potential difference between input terminals of an Op-amp may be treated to be nearly zero if the
Op-amp is used in circuit having negative feedback.
Q.10 Ans.(d)
RF

R1 IB 100k
+ –
Vs
~ 100k Vio
– +
Vo

The output offset voltage op-amp with negative feedback as shown above is given by,
 R 
Voo = 1 + F  Vio + IB RF
 R 

where Vio is input offset voltage and IB is input bias current.

 100 
⇒ Voo = 1 +  × 1 × 10 + 10 × 10 × 100 × 10
–3 –9 3

 100 

⇒ Voo = 2 + 1 = 3 mV

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [241]
Maximum dc error is output voltage is maximum offset voltage at output.
Q.11 Ans.(d)
10k

1k
Vin –
Vout
+

The resistance R is connected to reduce the output offset voltage due to input bias current. When
resistance R is changed, the output offset voltage changes by small amount so gain of circuit changes
by small amount.
Q.12 Ans.(b)
20k 100k
V1

V2 –
R1 Vo
+

R2

For ideal op-amp, V– = V+
∴ V– = Va = 0
KCL at node ‘a’,
0 − V1 0 − V2 0 − Vo
+ + = 0
20 R1 100

100 100
⇒ Vo = − V1 − V2
20 R1

Given, Vo = – 7 V, V1 = 0.2 V ,and V2 = 0.6

100
⇒ –7 = – 5 × 0.2 – × 0.6
R1

60
⇒ = 6
R1

⇒ R1 = 10 k

Q.13 Ans.(c)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [242]
100 k
20 k
V1

a –
V2 Vout
R1=20k +

R2

Given,
V1 = V2 = Vc sin 2πft, R1 = 20 k
Output of amplifier,
100 100
Vo = − × V1 − × V2
20 20

⇒ Vo = – 10 Vc sin 2πfct
No slew-rate induced distortion is introduced if
dVo
≤ S.R.
dt max

dVo
= |20πfVc cos 2πft|max = 20πfVc
dt max

⇒ 20πfVc ≤ S.R.
Given, S.R. = 0.5 V/µs = 0.5 × 106 V/sec
⇒ 20πfVc ≤ 0.5 × 106
0.5 × 106
⇒ f ≤
20π × Vc

Case -I : when, Vc = 0.1 V

0.5 × 106
f ≤
20π × 0.1

⇒ f ≤ 79 kHz
Case-II :- when, Vc = 0.5 V
0.5 × 106
f ≤
20π × 0.5

⇒ f ≤ 15.9 kHz
At 0.5 V, fc max is 15.9 kHz No option gives frequency less than 15.9 kHz
At 0.1 V max frequency is 79 kHz and 30 kHz lies within this maximum frequency so 0.1 V & 30
kHz signal does not have any distortion.
So, option ‘c’ is correct.
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [243]
Q.14 Ans.(b)

V1 +

V2 Vo
–

Output voltage of opamp is given by

Vo = Ad Vd + AcmVcm
Where, Ad is differential mode gain, Acm is common mode gain Vd is differential mode input and Vcm
is common mode input.
For an opamp,Vd and Vcm are given as,
Vd = V1 – V2 = 0.55–0.45 = 0.10
V1 + V2 0.55 + 0.45
Vcm = = = 0.5
2 2

CMRR of opamp is defined as,

Ad
CMRR =
A cm

Given, Ad = 100 and C

MRRdB = 40dB = 20 log CMRR
⇒ CMRR = 102 = 100
Ad 100
∴ Acm = = = 1
CMRR 100

So, Vo = 100 × 0.1 + 1 × 0.5 = 10.5 V

Q.15 Ans.(a)
V1 –
+
Aid AoL
– Vo
V2 +

Vo = A oL Vid

As output voltage of op-amp is function of differential input voltage so the an ideal op-amp has
characteristics of an ideal voltage controlled voltage source.
Q.16 Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [244]
470 k

22 k
–

+
0.25 sin t ~ V0

470
Gain of op-amp, A = −
22

Output op-amp, Vo = AVin

The slew rate of Op-amp is defined as,
dVo dVin
=A
dt max
dt

For sinusoidal input, Vin = Vp sin ωt

To avoid slew-rate induced distortion maximum rate of change of output voltage should be less than
or equal to the slew rate.
dVp sin ωt
A ≤ SR
dt max

2πf |A|Vp ≤ SR
Given, Vin = 0.25 sin ωt,
SR = 0.8 V/µsec = 0.8 ×106 V/sec
470
⇒ 2π × f × × 0.25 × ≤ 0.8 ×106
22

0.8 × 106 × 22
⇒ f ≤
470 × 0.25 × 2π

⇒ f ≤ 23.84 kHz
Thus maximum frequency with no distortion in output is 23.84 kHz.
Q.17 Ans.(c)
Two input terminals of an op-amp are at same potential because the open loop gain of op-amp is
infinity.
Proof :-

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [245]
V1
Vid=V2–V1
–A
oL

+ V0
V2

For Opamp, Vo = AoL Vid

Vo
⇒ Vid =
A oL

For ideal Op-amp,

AoL = ∞
Vo
⇒ Vid = =0
∞

⇒ V1 –V2 = 0
⇒ V1 = V2
Q.18 Ans.(a)
When input is sinusoidal,
vin = Vm sin ωt
Output voltage, vo = A vin = A Vm sin ωt
For voltage follower,
A = 1,
∴ vo = Vm sin ωt
dvo d(vo sin ωt)
= = Vm ω cos ωt max = Vm ω = Vm × 2π f
dt max
dt max

To avoid slew rate induced distortion,

dvo
S R ≥
dt max

⇒ S R ≥ 2πfVm
SR
⇒ f ≤
2πVm

Given, S R = 62.8V/µsec = 62.8×106 V/sec

∴ Vm = 10 V
62.8 × 106
⇒ f ≤
2 × 3.14 × 10

⇒ f ≤ 1 MHz

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [246]
∴ So, slew-rate induced distortion would set in at 1 MHz.
Q.19 Ans. (d)
The input bias current of an op-amp is given by,
I b1 + I b2 450 + 350
IB = = = 400 nA
2 2

Input offset current,

If = Ib1 - Ib2 = 450 - 350 = 100 nA
Q.20 Ans. (20:20)
60k

30k
–
+ V0

The output offset voltage due to input bias current in given circuit becomes zero when,
R = (30k)||(60k) = 20 k
Q.21 Ans. ( 1.4 to 1.6)

V2 –
Differential
V0
Amplifier
V1 +

The output voltage due to inputs V1 and V2 is given by,

 V + V2 
Vo = Ad (V1 - V2) + Ac  1 
 2 

 5.01 + 5 
⇒ Vo = 100 × (5.01 - 5) + 0.1 ×   = 1.5 V
 2 

Q.22 Ans.(c)

IB V2 RF = 1M
2
–
eo
V1
+

IB Rcom = 1M
1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [247]
When resistance Rcom is connected in non-inverting terminal the offset voltage eo at output is due to
input offset current only. The output voltage due to input bias current becomes zero. So, by measuring
eo only input offset current can be calculated.
Q.23 Ans.(b)

1 k 1 M
–
+ VOut

Output voltage interms of offset voltage is given by

 R 
Vout = 1 + F  Vio
 R1 

 106 
⇒ Vout = 1 +  × 1 mV = 1001 × 10–3 ≈ 1V
 103 

Q.24 Ans.(c)

R2

R1 I1
–
Vout
+
I2

If op-amp in the circuit shown above has finite input impedance, infinite voltage gain and zero input
offset voltage then the output voltage Vout is voltage drop across R2 due to input bias current I1.
Vout = I1R2
Q.25 Ans.(d)
10 k
R1 RF
Vi
+–
1k Vio – + Vo

1k

The output offset voltage of amplifier shown above in terms of input offset voltage is given by,
 R 
Voo = 1 + F  Vio
 R1 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [248]

 10 
⇒ Voo = 1 +  × 10 mV
 1

⇒ Voo = 110 mV

Q.26 Ans.(b)
When an amplifier with two left half plane poles in its open-loop transfer function is provided with
resistive negative feedback it will be stable for all frequencies.
Q.27 Ans.(b)
Gain bandwidth product of Op-amp, remain constant,
UGB = foA
where, A → gain and fo → 3 dB cutoff frequency
UGB
⇒ fF = ....(i)
AF

fF AF = foAo
where, fFAF → Gain BW product after feedback.
foA → Gain BW product before feedback
Given, fo = 1 MHz = 1 × 106 Hz
Gain in dB, AFdB = 20 = 20 log AF
⇒ AF = 10
Putting above values in eqaution (i), we have,
106
⇒ fF = = 100kHz
10

3-dB cut-off frequency of op-amp gives 3-dB bandwidth op-amp.

Q.28 Ans.(a)
The first dominant pole encountered frequency response of a compensated op-amp is approximately
at 5Hz.
Q.29 Ans.(a)
Characteristics of ideal Op-amp,
i) Ri = ∞
ii) A = ∞
iii) Ro = 0
iv) CMRR = ∞
v) Bandwidth = ∞

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [249]
Q.30 Ans.(b)
Output voltage of op-amp,
v = Aov vid
where, AoL = open loop gain
vid → differential input voltage
So, ideal op-amp behaves like a voltage controlled voltage source.
Q.31 Ans.(d)
100 
– Vo
+
Vs –+ +
90 
1k
Vf 10 
–

Feedback voltage,
10
Vf = × Vo
10 + 90
Vf 1
Feedback factor, β = =
Vo 10

Q.32 Ans.(b)
2 k

1k +6V
–
Vout
+
+ 6V
~ –
Vin

The non-inverting configuration of op-amp shown above has voltage-voltage feedback which is also
known as voltage-series or series-shunt feedback.
Q.33 Ans.(b)
A current buffer is an amplifier with unity current gain. A good current buffer has low input impedance
and high output impedance current buffer is an electronic circuit that is used to transfer electric
current from input source having very less impedance (effective resistance) to output loads with high
impedance.
Q.34 Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [250]
30k

iin 10k
–
A
B vo
vin ~
+

For ideal op-amp, V– = V+

∴ Va = V+ = 0
So, current supplied by source,
vin − v A vin
iin = =
10k 10k
Input resistance,
vin
R=
in = 10kΩ
iin

Q.35 Ans. (b)

Rf

Ri
–

V0
+
= Vin –
+

The given amplifier is an inverting amplifier. The input resistance of inverting amplifier is given by,
Rin = R1

Given, Rin = 50 kΩ, Gain, AF = -10

∴ R1 = Rin = 50 kΩ
The gain of inverting amplifier is given by,
RF
AF = −
R1

RF
⇒ -10 = -
50k

⇒ RF = 500 kΩ
Q.36 Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [251]
R1
–
Vo
R2 +
Vi +
–

R3

Given circuit can be redrawn as under,

R2

R1
–
(a) Vo
+
Vi +
–
R3

Applying KCL at node (a)

Va − Vi Va − Vo
+ =0
R1 R2

For ideal op-amp,

V– = V+
∴ Va = V+ = 0
Vo R
⇒ = − 2
Vi R1

Vo R
∴ Voltage gain, = − 2
Vi R1
Q.37 Ans.(b)
Vin +
Vo
–
S1 2k
S2

1k
S3

500
S4

500

When switch S2 is closed gain of amplifier is,

 R   2   2
A = 1 + F  =
1 +  = 1 +  = 2
 R   1 + 0.5 + 0.5   2 
Q.38 Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [252]
S

R
R
–
Vin
Vo
+

when switch ‘S’ is open,

Vo 2R
x = =
− –2
= ......(i)
Vi R

when switch ‘S’ is closed,

Vo R
A = =− =–1 ......(ii)
Vi R

From equations (i) and (ii),

∴ A/x = 1/2
x
⇒ A=
2

Q.39 Ans.(c)
RF

R1
–
Vin
+ Vout

Voltage gain of above amplifier,

Vout R
Av = = − F
Vin R1

Given, RF = 1 MΩ
Avmin = – 10
Avmax = – 25
For minimum value R1,
RF
⇒ R1min = −
A vmax

1 × 106
⇒ R1min = −
−25

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [253]

⇒ R1min
= 40 kΩ

For maximum value of R1

RF 1 × 106
⇒ R1max = − = −
A v min −10

⇒ R=
1max 100 kΩ

Q.40 Ans.(0.4 to 0.6)

31 k

RF
1 k +15V
+ –
R1 A +
1V + v0
– –15V
–

Output voltage of amplifier
RF 31
Vo = - × Vin =− × 1 =–31V
R 1
The output voltage cannot be more than the power supply voltage.
So, Vo = –15V
Applying KCL at node ‘A’ we have,
V − 1 VA − Vo
A + = 0
1 31

V − 1 VA − ( −15 )
⇒ A + = 0
1 31
⇒ 3 1 VA – 31 + VA + 15 = 0
⇒ 32 VA = 16
16
⇒ VA = = 0.5V
32

Q.41 Ans. (b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [254]
2 k

+15 V
1 k
– V0
+
+
10 V
–
–15 V

The given circuit is a inverting amplifier whose output can be given by,
2k
Vo = − × 10 V =−
20 V
1k

The output voltage of opamp cannot be more than the power supply voltage in magnitude. So, output
voltage is close to -15 V.
Q.42 Ans.(b)
RF= 2 R

+ 10 V
R1= R
–
V0
+
2V – 10 V

For non-inverting amplifier shown above,

 R 

Vo = Vi 1 + F 
 R1 

 2R 
⇒ Vo = 2 1 + =6V
 1R 

Q.43 Ans.(b)
The phase shift provided by a linear phase shifter is given by,
⇒ φ = ωtd = 2πftd ; td = time shift
φ
⇒ td =
2πf

1
⇒ td ∝
f

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [255]

f1
⇒ td2 = × t d1
f2

Given, td1 = 3ms, f1 = 50Hz, f2 = 150 Hz

50
⇒ td2 = × 3 = 1msec
150

Q.44 Ans.(c)
R1=1 k R2=1 k
V1 = –2V
+15 V
+15 V
–
1 + Vout
+ 2
–
–15 V
–15 V
1 k
R4=1 k
R3=1 k
V2 = +1V

Output voltage of op-amp 1,

R2  R 
V01 = – V1 + 1 + 2  V2
R1  R1 

1  1
Therefore, V01 = − × (−2) + 1 +  × 1 =4V
1  1

Output of op-amp 2,
 R   1
Vout = 1 + 4  V01 = 1 +  × 4
 R3   1

⇒ Vout = 8 V

Q.45 Ans.(c)
R1=1 k R2=1 k
V1 = –2V +15 V
+15 V
–
1 + Vout
+ 2
–
–15 V
–15 V
1 k
R4=1 k
R3=1 k
V2 = +1V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [256]
Output voltage of op-amp 1,
R2  R 
V01 = – V1 + 1 + 2  V2
R1  R1 

1  1
Therefore, V01 = − × (−2) + 1 +  × 1 =4V
1  1

Output of op-amp 2,
 R   1
Vout = 1 + 4  V01 = 1 +  × 4
 R3   1

⇒ Vout = 8 V
Q.46 Ans.(d)
10 d 10k

a c
1k
b
1k
Vin –
R1
Vout
+

For ideal op-amp V– = V+

∴ As V+ = 0 so V– = 0
Applying KCL at node ‘a’,
0 − Vin 0 − Vd
+ =0
1k 10k

⇒ Vd = –10Vin ......(i)
Applying KCL at node ‘d’
Vd − 0 Vd Vd − Vout
+ + =0
10k 1k 10k

⇒ Vout = 12Vd .....(ii)

From (i) and (ii), we have,
Vout = –120 Vin
Vout
⇒ = –120
Vin

Alternate Method
Converting star cannection abc to delta connection, we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [257]
Rac

Rab Rbc
1k
Vin –
R1
Vout
+

Rab and Rbc can be neglected

Vout R
∴ = – ac
Vin R1

From star-delta convertion, Rac is given by,

10 × 10
Rac = 10 + 10 + kΩ
1

= 120 kΩ
Vout −120
∴ =
Vin 1

Vout
⇒ = −120
Vin

Q.47 Ans.(c)
R1=1 k R2=1 k
V1 = –2V
+15 V
+15 V
–
1 + Vout
+ 2
–
–15 V
–15 V
1 k
R4=1 k
R3=1 k
V2 = +1V

Output voltage of op-amp 1,

R2  R 
V01 = – V1 + 1 + 2  V2
R1  R1 

1  1
Therefore, V01 = − × (−2) + 1 +  × 1 =4V
1  1

Output of op-amp 2,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [258]

 R   1
Vout = 1 + 4  V01 = 1 +  × 4
 R3   1

⇒ Vout = 8 V
Q.48 Ans. ( 1 )

10 k d 10 k

a c
R
b
10 k
Vin –
R1
Vout
+

Converting star connection abc to delta connection, we have,
Rac
a c
Rab Rbc
10 k
Vin –
R1
Vout
+

Rab and Rbc can be neglected

Vout R
∴ = – ac
Vin R1

From star-delta convertion, Rac is given by,

10 × 10 100
Rac = 10 + 10 + kΩ = 20 +
R R

100
20 +
Vout R
∴ =-
Vin 10

100
20 +
⇒ -12 = - R
10

⇒ R = 1 kW
Q.49 Ans. (0.6 to 0.6)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [259]
10 k d 10 k

a c
R
b
10 k
Vin –
R1
Vout
+

Converting star connection abc to delta connection, we have,
Rac
a c
Rab Rbc
10 k
Vin –
R1
Vout
+

Rab and Rbc can be neglected

Vout R
∴ = – ac
Vin R1

From star-delta convertion, Rac is given by,

10 × 10 100
Rac = 10 + 10 + kΩ = 20 +
R R

100
20 +
Vout R
∴ =-
Vin 10

100
20 +
⇒ -12 = - R
10

⇒ R = 1 kW

Q.50 Ans. (1.3 to 1.4)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [260]
Vr= +1V
+ V 

a +
–
RT Vo
b
–
R 100 

The resistance of RTD at 100oC,

RT = Ro(1 + αT) = 100 ( 1 + 0.0039 ×100) = 139 Ω
Output voltage of the circuit,
 R   139 
V′ = 1 + T  × Vr =  1 +  ×1 = 2.39 V
 R   100 
For ideal opamp, Vb = Va = 1 V
Voltage across RT , Vo = V′ - Vb = 2.39 - 1 = 1.39 V
Q.51 Ans.(b)
5 k

1 k
2V –
a
b
3V + Vo
1 k
8 k

Voltage at node ‘b’,

8 8
Vb = × 3V = V
8 +1 3

KCL at node ‘a’,

Va − 2 Va − Vo
+ = 0
1 5

For ideal op-amp,

V− = V+
8
∴ Va = Vb = V
3

 5 5
⇒ Vo =1 +  Va − × 2
 1 1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [261]

8
⇒ Vo = 6 × − 10V = 6 V
3

Q.52 Ans.(a)
2k

1k
4V –
‘a’
1k
‘b’ Vo
+

1k

Voltage at node ‘b’,

1
Vb = × 4 = 2V
2

For ideal op-amp,

V– = V+
∴ Va = Vb = 2V
Applying KCL at node ‘a’, we have,
2 − 4 2 − Vo
+ = 0
1 2

⇒ Vo = – 4 + 2 V = – 2V
Q.53 Ans.(d)
100k

10k
2V
‘a’ – Vo
5V ‘b’ +
10k
100k

100
Voltage at node ‘b’ Vb = ×5
110

50
Vb =
11

For ideal opamp, V – = V+

50
∴ Va = Vb =
11

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [262]
KCL at node ‘a’,
V − 2 Va − Vo
a + =0
10 100

 100  100
1 +
 Va − × 2 = Vo
 10  10

50
⇒ Vo = −20 + (11) × = 30V
11

Q.54 Ans.(d)

10k 100 k
a –
Vo
+ +
1V –

For ideal Op-amp,

V– = V+
∴ V– = V+ = 1V
Applying KCL of node a,
V − 1 Va − Vo
a
+ =0
10 100

1 − 1 1 − Vo
⇒ + = 0
10 100

⇒ Vo = 1V

Q.55 Ans.(c)
R2

X R1
– –
Vd Z
Y+ Vo
+
R3
Vi +–
R4

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [263]
The output voltage of a differential amplifier is given by
V0 = Ad Vd + AC VC .....(i)

Where Ad is differential mode gain, Vd is differential mode input voltage, Ac is common mode gain
and Vc common mode input voltage
Given circuit, Vc = Vi
Given,V0 = 3×10–3 V for Vc = 2 V and V0 = 4 × 10–3 V for Vi = 3 V and Ad = 10
Putting above values in equation (i), we have,
3 × 10–3 = 10 Vd + Ac × 2
4 × 10–3 = 10 Vd + Ac × 3
⇒ Ac = 10–3
Common mode rejection ratio (CMRR) of differential amplifier is given by.
Ad
CMRR =
Ac

10
⇒ CMRR = = 104
10−3

Q.56 Ans.(b)
+5V

R R X
– Differentiol Z
Vd Y Amplifier
strain +
Ry gange R

Resistance of strain gauge,

Rg = R± (1% or R = R± 0.01R
From bridge circuit at input of the amplifier,
Rg
VY = × 5V
Rg + R

R 1
and VX = × 5V = V
R+R 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [264]
When Rg = R+0.01R = 1.01R
Differential input voltage,
 Rg 1
Vd = VY –VX =  − ×5

Rg +R 2

 0.01R 1
⇒ Vd1 =  − 5
 1.01R + R 2 

 1.01 1 
=  −  5= 12.437 × 10−3 V
 2.01 2 

Common mode input voltage,

V Y + VX
Vc1 =
2

1  1·01 1 
⇒ Vc1 =  +  × 5V
2  201 2 

= 2.5062 V
Output voltage,
V01 = Ad Vd1 + AC VC1
⇒ V01 = 10 × 12.437 ×10–3 + 10–3 × 2.5062 = + 126.87 mV
When Rg = R–0.01R = 0.99R
Differential input voltage,
 0.99R 1
Vd2 =  − 5=− 12.562 × 10−3 V
 0.99R + R 2 

Common mode input voltage,

VY + VX 1  0.90 1 
Vc2 = =  + = × 5 2.4937 V
2 2  1.99 2 

Output voltage, V02 = –10 × 12.562×10–3 + 10–3 × 2.4937

⇒ V02 = – 123.12 V
So output voltage varies from + 127 V to – 123 V, which is approximately same as range given in
option (b).
Q.57 Ans (d)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [265]
3R

R 'a'
V1 –
Vo
2R + R
V2

Applying KCL at node ‘a’, we have,

Va − V1 Va Va − Vo
+ + = 0
R 2R 3R

For an ideal op-amp, V_ = V+

∴ Va = V2
V − V1 V2 V2 − V0
⇒ 2 + + = 0
R 2R 3R
 3  11
⇒ V0 = −3V1 +  3 + + 1 V2 =
−3V1 + V2
 2  2

Q.58 Ans (d)

R

+Vsat
R
+Vsat –
vi – 2 vo
1 +
vo1
+
–Vsat –Vsat

R2
R1

Op-amp 1 has positive feedback so its output is either +Vsat or –Vsat depending on values of R1 and
R2.
∴ vo1 = ±Vsat
 R
Output of Op-amp 2, vo = 1 +  v o1 =
2v o1
 R

vo = 2(± Vsat) = ± 2Vsat
Output of op-amp can not be more that saturation voltage.
So, v0 = ± Vsat

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [266]
Q.59 Ans. (d)
Z2

Z1
V1 –
– a
Vd Vo
+ b
V2 +
Z1

Z2

Z2
Voltage at node ‘b’, Vb = × V2
Z1 + Z2
Z2
Voltage at node ‘a’, Va = V2 − × V2
Z1 + Z2
Applying KCL at node ‘a’, we have,
V − V1 Va − Vo
a + = 0
Z1 Z2
 Z2  Z2
⇒ Vo = 1 +  ⋅ Va − V1
 Z1  Z1
Z1 + Z2 Z2 Z
⇒ Vo = × V2 − 2 V1
Z1 Z1 + Z2 Z1
Z2
⇒ V2 =
Z1
( V2 − V1 )
Z
⇒ V2 = 2 × Vd
Z1
For given circuit, Z2 = R = 1kΩ
1 1 1 1
Z1 = = = = −6
jωC j2π fC j2π × 50 × 1 × 10 j100π × 10−6

Vd = Vi ∠0°

1 × 103
∴ Vo = × Vd ∠0°
1
j100 ××10−6

⇒ Vo = j0.1 π Vd ∠0°

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [267]

π
⇒ Vo = 0.1 πVd ∠
2
π
∴ ∠V0 =
2

Q.60 Ans. (1.5)

Case-I : Switch at position ‘A’.
When switch is at position ‘A’, the equivalent circuit becomes as shown below,
1k
V1 = 5V 1k
R2
R1 1k
'a'
–
R3
VoA
B A 1k 'b'
+ R
R1
R2 1k
V2 = +1V

R2 1
Output voltage, VoA = ( V2 − V1 ) =(1 − 5) =
−4 .....(i)
R1 1
Case-II : Switch at position ‘B’.
When switch is at ‘B’, the circuit becomes as under,
1k

R2
V1 = 5V R1 = 1k
–

VoB
R3= 1k
+
R1=1k
1k R2
V2 = +1V

1 1
Output voltage, VoB = - × 5 − × 1 =−6V .....(ii)
1 1
From (i) and (ii), we have,
VoB −6
= = 1.5
VoA −4

Q.61 Ans. ( 11 to 12 )

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [268]
2k

1k 12V
–
Vo
+
–12V
R2
1V
For the circuit shown above voltage at inverting terminal,
V = 0V
Voltage at non-inverting terminal, V+ = 1V
Differential input voltage, Vd = V+ – V– = 1 – 0 = 1V
Because of grounding of inverting terminal the circuit behaves like open loop. For ideal op-amp the
output voltage is +Vsat for non-zero positive value of differential input voltage.
∴ Vo = +Vsat = 12V
Q.62 Ans. (–1)
20k

20k
+ Vi a
2V b –
– 10k Vo
20k
+

10k

Applying KCL at node ‘a’,we have,

V − Vb Va − Vo
a + = 0
10 20
 20  20
Vo = 1 +  Va − Vb
 10  10
For ideal opamp, V– = V+
∴ Va = V– = 0
20
⇒ Vo = - Vb = −2Vb .....(i)
10
Applying KCL at node ‘b’, we have,

Vb − Va Vb Vb − 2
+ + = 0
10 20 20

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [269]
Putting Va = 0, we have,
V − 0 Vb Vb 2
⇒ b + + =
10 20 20 20
⇒ 4 Vb = 2
Vb = 0.5 V
Putting above value of Vb in (i), we have,
V0 = – 2 × 0.5 V = –1V
Q.63 Ans. (40:41)
100(1 + x) k

10(1 – x) k
V1 –
'a'
10(1 + x) k 'b' Vo
V2 +

100(1 – x) k

100 (1 − x )
Voltage at node ‘b’, Vb = × V2
10 (1 + x ) + 100 (1 − x )
For ideal voltage at node ‘a’,
100 (1 − x )
Va = Vb = × V2
10 (1 + x ) + 100 (1 − x )

Apply KCL at node ‘a’ , we have,

Va − V1 V − Vo
+ a = 0
10 (1 − x ) 100 (1 + x )

 100 (1 + x )  100 (1 + x )
Vo = 1 +  Va − V1
 10 (1 − x )  10 (1 − x )
10 (1 − x ) + 100 (1 + x ) 100 (1 − x ) 100 (1 + x )
⇒ Vo = × × V2 − × V1
10 (1 − x ) 10 (1 + x ) + 100 (1 − x ) 10 (1 − x )
Let for common mode operation V1 = V2 = VCM
1 − x + 10 (1 + x ) 10 (1 − x ) 10 (1 + x ) 
⇒ Vo =  × −  VCM
 1− x 1 + x + 10 (1 − x ) 1 − x 
V0 10 (11 + 9x ) 10 (1 + x )
⇒ =
ACM = −
VCM 11 − 9x 1− x
Putting, x = 0.05, we have,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [270]

10 (11 + 9 × 0.025 ) 10 (1 + 0.025 )

ACM = − −0.095
=
11 − 9 × 0.025 1 − 0.025
|ACM| = 0.095
Given, differential gain, Ad = 10
Common Mode Rejection Ration in dB is given by
Ad 10
CMRRdB = 20log = 20log = 40.4 dB
A CM 0.095

Q.64 Ans.(b)
100 k

10 k a
V1 –
b V0
V2 +
10 k
100 k

Voltage at node ‘b’,
100
Vb = × V2
100 + 10

10
⇒ Vb = V2
11

For an ideal opam, Va = Vb

10
∴ Va = V2
11

Applying KCL at node ‘a’,

Va − V1 Va − V0
+ =0
10k 100k

100k  100k 
⇒ V0 = V1 + 1 +  Va
10k  10k 

⇒ V0 = –10V1 + 11 Va
10
⇒ V0 = −10V1 + × 11V2
11

⇒ V0 = 10(V2 – V1)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [271]
⇒ V0 = 10(50 – 10) mV
⇒ V0 = 400 mV
Q.65 Ans.(b)
20k 100k
V1

V2 –
R1 a Vo
+

R2

For ideal opamp, V

– = V+
∴ V– = Va = 0
KCL at node ‘a’,
0 − V 0 − V2 0 − Vo
1 + + =0
20 R1 100

100 100
⇒ Vo = − × V1 − × V2
20 R1

Given, Vo = – 7 V, V1 = 0.2 V V2 = 0.6

100
⇒ –7 = – 5 × 0.2 – × 0.6
R1

60
⇒ = 6
R1

⇒ R1 = 10 kW

Q.66 Ans.(c)
100 k
20 k
V1

a –
V2 Vout
R1=20k +

R2

Given, V1 = V2 = Vc sin 2πft, R1 = 20 k

100 100
Output of amplifier, Vo = − × V1 − × V2
20 20
⇒ Vo = – 10 Vc sin 2πfct
No slew-rate induced distortion is introduced if
dVo
≤ S.R.
dt max

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [272]

dVo
= |20πfVc cos 2πft|max
dt max

= 20πfVc
⇒ 20πfVc ≤ S.R.
Given, S.R. = 0.5 V/µs = 0.5 × 106 V/sec
⇒ 20πfVc ≤ 0.5 × 106
0.5 × 106
⇒ f ≤
20π × Vc

Case -I : when, Vc = 0.1 V

0.5 × 106
f ≤
20π × 0.1
⇒ f ≤ 79 kHz
Case-II :- when, Vc = 0.5 V
0.5 × 106
f ≤
20π × 0.5
⇒ f ≤ 15.9 kHz
At 0.5 V, fc max is 15.9 kHz No option gives frequency less than 15.9 kHz
At 0.1 V max frequency is 79 kHz and 30 kHz lies within this maximum frequency so 0.1 V & 30 kHz
signal does not have any distortion.
So, option ‘c’ is correct.

Q.67 Ans.(b)
With V1 = V2 = 0 & R1 = 20 k the given circuit becomes
RF

20 k 100 k

–
20 k Vout
}

Req +

R2

The equivalent resistance at inverting terminal with V1 = V2 = 0,

20 × 20
Req = = 10 k
20 + 20
When both inputs are zero the voltage at output is output offset voltage. Output offset voltage due to
input bias currents reduces to zero.
when, R2 = RF | | Req
R F × R eq
⇒ R2 =
R F + R eq

100 × 10 1000
= k = k = 9.1 kW
100 + 10 110
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [273]
Q.68 Ans.(c)
C

V1 sin t C
a –
V0
V2 sin t C b +

For ideal Op-amp,

Va = Vb
Here Vb = 0
∴ Va = 0
KCL at node ‘a’.
0 − V1 sin ωt 0 − V2 sin ωt 0 − vo
+ + =0
1 / j ωC 1 / j ωC 1 / jωC

⇒ Vo =
−(V1 + V2 )sin ωt

Q.69 Ans.(a)
R1 a R1
Vs

–
R2 Vout
b
+

R2
R4
iL

Applying KCL at node a,

Va − Vs Va − Vout
+ =0
R1 R1

1
Va = [Vs + Vout ]
2

For ideal op-amp,

V– = V+
∴ Vb = Va
1
⇒ Vb = [Vs + Vout ]
2

Applying KCL at node b,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [274]

V V − Vout
b + i L + b =0
R2 R2

2 1 V
iL = − × [Vs + Vout ] + out
R2 2 R2

Vs
⇒ iL = −
R2

Note: Given circuit is V to I converter in inverting mode.

Q.70 Ans.(d)

R1
a b +
V –
IL Load
R2
Ir r

R2
Voltage at node ‘a’, V
+= ×V
R1 + R 2

For ideal op-amp, V – = V+

R2
∴ Vb = Va = ·V
R1 + R 2

Applying KCL at node ‘b’, we have,

Vb − 0
− I L = 0
r

Vb 1 R2
⇒ IL = = × ×V
r r R 2 + R1

R2 V
⇒ I L = ·
R 2 + R1 r

The load current here is independent of load resistance so, given circuit behaves like a current souce
R2 V
of value ·
R1 + R 2 r
Q.71 Ans. (100:100)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [275]
R1 = 100 k

R1 = 100 k
–
'a'
R2 'b' Vo
Vi = 1V +
10 k R2

10 k
RL
IL

R1 1
Voltage at node ‘a’, Va = × Vo =Vo
R1 + R1 2
1
For ideal op-amp voltage at node ‘b’, Vb = Va = Vo
2

Applying KCL at node ‘a’,

Vb − Vo Vb − Vi
+ + I L = 0
R2 R2
Vo Vo
− Vo − Vi
⇒ 2 + 2 + I L = 0
R2 R2
V 1
⇒ IL =
= i = 3
104 A
R 2 10 × 10
⇒ IL = 100 µA
Q.72 Ans.(a)
‘b’ 10k

0.3mA

–
Vo
+

20k ‘a’ 30k

KCL at node ‘a’,

Va − Vo Va
+ = 0
30 20

 30 
⇒ Vo = 1 +  Va
 20 

2
⇒ Va = Vo
5

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [276]
For ideal Op-amp,
V+ = V–
2
∴ Vb = Va = Vo
5

V − Vo
KCL at node ‘b’, b = 0.3 × 10–3
10 × 103

2 
⇒  5 − 1 Vo = 3 × 10 × 10
–3 3

 

⇒ Vo = −5V

Q.73 Ans.(d)
1K

a –
1 mA  + V0

For ideal Op-amp, V– = V+

∴ Va = V– = 0V
Applying KCL at node ‘a’, we have,
0 − Vo
3
− 1 × 10−3 = 0
10

Vo = – 1V
Note: The given circuit is a current to voltage source converter.
Q.74 Ans.(b)
R2 = 100k

R1
a –
10k b
vs + Vo
is

R3 = 1M

KCL at node ‘b’

vs − v o
= is
R3
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [277]
vs –is R3 = vo ....(i)
For ideal Opamp,
va = vb
∴ va = vs
KCL at node ‘a’,
vs − 0 vs − v o
+ =0
R1 R2

 R 
⇒ vo = 1 + 2  vs ....(ii)
 R1 

From (i) & (ii), we have

 R 
vs – is R3 = 1 + 2  vs
 R1 

  R 
⇒ is R3 = vs 1 − 1 + 2  
  R1  

vs R R
⇒ = − 3 1
is R2

vs RR
⇒ Rin = = − 1 3,
is R2

10 × 103 × 1 × 106
Rin = –
100 × 103

⇒ Rin = –100 kΩ

Q.75 Ans.(b)
1.5k

1.0k
–
‘a’ Vo
1mA Output
+

+5V

For ideal Op-amp,

V– = V+
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [278]
∴ Va = 0 V
0 − Vo
KCL at node ‘a’, = 1 × 10–3
1.5 × 10−3

⇒ Vo =−1.5 V
Q.76 Ans.(d)
Output voltage of Instrumentation amplifier is given by
Vo = AdVd + Ac Vc
where, Ad = Differential mode gain
Vd = Differential input voltage
Ac = Common mode gain
Vc = Common mode input
voltage
If V1 and V2 are input voltages to amplifier,
then, Vd = V1– V2 and
V1 + V2
Vc =
2

 V + V2 
∴ Vo = A d [V1 − V2 ] + A c  1  ...(i)
 2 

Given, Vo = 100 [V1 – V2] + 10–4 [V1 + V2] ...(ii)

−4  V + V2 
⇒ Vo = 100[V1 − V2 ] + 2 × 10  1 
 2 

Comparing equations (i) and (ii), we have,

Ad = 100, Ac = 2 × 10–4
∴ Common mode rejection radio is given by,
Ad
CMRR =
Ac

100
⇒ CMRR = = 50 × 104
2 × 10−4

In dB, CMRRdB = 20log10 50 × 104

⇒ CMRRdB = 113.97 dB

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [279]
Q.77 Ans. (b)
V2 +2 R
–
R V02 R
–
2R 3 V0
+
R V01 R
– R
V1 +1

For ideal opamp the voltage at inverting terminal is same as votlage at noninverting terminal. Then,
the output voltage of opamp ‘1’ can be given as,
V2

2R
R V01
–
V1 +1

R  R  V2 V1
V01= − × V2 + 1 +  × V1 = − +
2R  2R  2 2
Similarly, the the output voltage of opamp ‘2’ can be given as,
V2 +2
–
R V02
2R

V1

R  R  V1 3V2
V02 = − × V1 + 1 +  × V2 = − +
2R  2R  2 2
The output voltage of opamp ‘3’ can be given as,
R
V02 R
–
3 V0
+
V01 R
R

 R R R
V0 =  1 +  × V01 − × V02
 R  2R R
⇒ V0 = V01 - V02

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [280]

V2 3V1 V1 3V2
⇒ V0 = − + + −
2 2 2 2
⇒ V0 = 2 ( V1 - V2)
Q.78 Ans.(c)
+ R1 R2
V1
–
–
R´ +
A B
Vo = G (V1– V2)
R1
RP
R´
R2
–
V2
+

Output voltage of instrumentation amplifier shown above is given by,

R2  2R ′ 
Vo = 1 +  [V1 − V2 ]
R1  RP 
Vo = G [V1 – V2]
R 2  2R ′ 
where, G = 1 + 
R1  R P 

Given, R1 = 50 k, R2 = 500 k
R´ = 100 k
RPB = 10.53 k
RPA = 22.2 k
when switch is at position A,
500  2 × 100 
GA = 1+ = 100
50  22.2 

when switch is at position B,

500  2 × 100 
GB = 1+ = 200
50  10.53 
Q.79 Ans. (a)
Of the four characteristics given below, which are the major requirements for an instrumentation
amplifier?
P. High common mode rejection ratio
Q. High input impedance
R. High linearity

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [281]
Q.80 Ans.(c)
1F

Vc
–
1k Vo
+

10V

When switch is open there is no feedback in the circuit and the output of op-amp is given as,
Vo = Vsat = + 15V
when switch is closed the capacitor starts charging with time constant RC.
The voltage across capacitor for t > 0 is given by,
Vc(t) = Vf – (Vf – Vi) e–t/RC
Here, Vi = 0,
Vf = +15 V
R = 1 k, C = 10–6 F
⇒ Vc(t) = +15(1 – e–t/RC)
At t = 1 m sec
−10−3 10−3
Vc = +15(1 − e ) = +15(1 – e–1) = +9.45 V

Q.81 Ans.(a)

d
Vi dt Vo

Differentiator

Given, Vi = Vs + Vn
where Vs = 10 sin 50 t
Vn = 0.1 sin 250 t
dVi d
Output voltage, Vo = = [10 sin 50 t + 0.1sin 250 t]
dt dt

⇒ Vo = 500 cos 50 t + 25 cos 250 t

Vo = Vos + Von
where, Vos = 500 cos 50 t = output due to signal
Von = 25 cos 250 t = output due to noise
Signal to noise ratio at input,
| Vs | 10
SNRi = = = 100 ...... (i)
| Vn | 0.1
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [282]
Signal to noise voltage ratio at output,
| Vos | 500
SNRo = = = 20 ..... (ii)
| Von | 25

From (i) and (ii), we have,

SNR o 20 1
= =
SNR i 100 5
1
⇒ SNRo = × SNR i
5

Thus, signal to noise ratio at output decreases by factor of 5.

Q.82 Ans.(c)
C
R
–
Vi ios
+ Vo

Above circuit is an integrator. When input signal to an integrator is square wave the output signal is
a triangular wave.
Vi

+1V
T/2
t

–1 V
Vo

Q.83 Ans. (a)

1/sC

1 µF
R
–
1k A
+ + +
Vi – Vo
–

The given circuit is an inverting amplifier connected in voltage shunt configuration with non-ideal
op-amp having open loop gain of A = 100. The closed loop gain of voltage-shunt configuration is
given by,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [283]

AK
AF =
1 + Aβ

R sCR
For the given cirucit, β = =
R + 1 / sC 1 + sCR

1 / sC 1
and K = =
R + 1 / sC 1 + sCR

1
A×
1 + sCR A
⇒ AF = =
sCR 1 + sCR + AsCR
1+ A ×
1 + sCR

A A
⇒ AF = =
1 + s (1 + A ) RC 1 + sτ
Where, t = (1 + A) RC = time constant of the circuit
For the given circuit, A = 1000, R = 1kΩ, C = 1 µF
∴ t = (1 + 1000) × 103 × 10–6 = 1001 ms
Q.84 Ans.(a)

–
R R V0
+
Vin
C C

Circuit shown above is a second order low pass filter in non-inverting mode.
Q.85 Ans.(a)
RF

10 k 10 k
–
R1
C Vo
Vin +
1F
1k
R

The transfer function of above circuit,

Vo  R  R
= 1 + F  ×
Vin  R 1  R + 1 / j ωC

Vo 2 2
⇒ Av = = =
Vi 1 − j 1 / RC ω
1− j H
ω ω

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [284]
As gain of circuit increase with increase in ω so circuit is high pass filter with cut off frequency
where, ωH = = cutoff frequency
RC

1
ωH = = 1000 rad/sec.
10 × 10−6
3

Q.86 Ans.(a)
R

R
–
Vi ‘a’ Vo
R ‘b’ +

1/sC

Voltage at node b,
1 / sC
Vb = × Vi
R + 1 / sC

1
⇒ Vb = × Vi
1 + sCR

For ideal op-amp,

V– = V+
1
∴ Va = Vb = ·Vi
1 + sCR

Applying KCL at node ‘a’, we have,

Va − Vi Va − Vo
+ =0
R R

Vo = 2Va – Vi
 1 
⇒ Vo =  2 × − 1 Vi
 1 + s CR 
Vo 1 − sCR
⇒ =
Vi 1 + sCR

Note :- The circuit is an all pass filter.

Q.87 Ans.(c)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [285]
R

R
Vi –

+ Vo
R
C

Vo 1 − sCR
=
Vi 1 + sCR

Given, Vi = V1 Sin ωt
Vo = V1 sin (ωt + φ)
For sinusoidal signal,
s = jω
Vo 1 − jωCR
=
Vi 1 + jωCR

Phase shift provided by filter,

φ = –2tan–1 ωCR
When, ω = 0, φ = 0
and when, ω = ∞, φ = – π
∴ Minimum phase shift = – π
Maximum phase shift = 0
Q.88 Ans.(b)
Z2
{

R2
Z1
{

R1 +5V
C
+ –
input v+i
– +
– vo (output)
+
–
–5V

Transfer function of circuit,

Vo (s) Z R2
= – 2 = –
Vin (s) Z1 1
R1 +
sC

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [286]

Vo (s) R / R1
⇒ = − 2
Vin (s) 1
1+
sC R1

For frequency domain, s = jω

Vo ( jω) R 2 / R1 Ao
= – = −
Vin ( jω) 1 / CR1 ω
1− j 1− j c
ω ω
1
where, ωc = rad/sec
R1C

and Ao = R2 / R1
Magnitude of gain,
Vo ( jω) Ao
=
Vin ( jω) ω 
2

1+  c 
 ω

Gain of circuit increases with increase in frequency so given circuit is a high pass filter with 3dB
cutoff frequency,
1
ωc = rad/sec.
R1C

Q.89 Ans.(a)
Zf
}

Z1 R2
}

C1 R1 C2
–
+ + Vo
Vi
–
~

Transfer function of above circuit is given by

Vo Z
= − f
Vi Z1

1
R2 ×
j ωC 2 R2
where, Zf = =
1 1 + j ωC 2 R 2
R2 +
j ωC 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [287]

1  1 
Z1 = R1 + = R1 1 + 
jωC1  jωC1R1 

Vo R 2 / R1
∴ =
Vi  1 
1 +  (1 + jωC2 R 2 )
 jωC1R1 

Vo Ao
⇒ =
Vi  ωL   ω 
1 − j  1 + j 
 ω  ωH 

R2
Above expression is transfer function of band pass filter,with dc gain, Ao = −
R1

1 1
Lower cutoff frequency ωL = and upper cutoff frequency, ωH =
C1R1 C2 R 2

Q.90 Ans.(d)
1µF ‘a’
Vin +
1/C – Vo
R 1k RF

R1 1k 1k

Voltage gain of circuit,

Vo  R F  R
Av = =1 + ×
V1  R 1  R + 1 / j ωC

RF
1+
R1
Av =
ωL
1− j
ω

Ao
∴ |Av| =
2
ω 
1+  L 
 ω 

1
where, ωL = = cutoff frequency
RC

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [288]

RF
and Ao = 1 +
R1

Gain of circuit increases with increase in frequency so the circuit is a high pass filter.
Gain is maximum when ω = ∞
RF 1
∴ Av, max = Ao = 1+ = 1+ = 2
R1 1

Q.91 Ans.(a)
R
R
Vi a –
C b + Vo
R

Voltage at node ‘b’,

R jωCR
Vo = =
R + 1 / jωC 1 + jωCR

For ideal op-amp,

V– = V+
jωCR
∴ Va = Vb =
1 + jωCR

KCL at node ‘a’,

Va − Vi Va − Vo
+ =0
R R

⇒ Vo = 2 Va – Vi
 jωCR 
= 2 × − 1 Vi
 1 + jωCR 

Gain of circuit,
Vo 1 − jωCR
=
Vi 1 + jωCR

Vo
Magnitude of gain, =1
Vi

Phase angle of gain, ∠ VVo

= – 2 tan–1 ωCR
i

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [289]
Magnitude of transfer function is independent of frequency, so given circuit is all pass filter.
Q.92 Ans.(d)
ZF
C2

Vi R2
a –
R1 Vo
b +

The transfer function of given filter,

Vo Z
H(jω) = = − F
Vi R1

1
R2 ×
jω C 2 R2
where, ZF = =
1 1 + j ωC 2 R 2
R2 +
jω C 2

R2 1 R 2 / R1
⇒ H(jω) = − · = −
R 1 1 + j ωC 2 R 2 jω
1+
ωH

Magnitude of gain,
R 2 / R1
|H(jω)| =
2
 ω 
1+  
 ωH 

1
where, ωH =
C2 R 2

1
fH = = 3dB upper cutoff frequency of filter
2π C 2 R 2

Given, C2 = 1 nF, R2 = 159 kΩ,

1
∴ fH =
2π × 1 × 10−9 × 159 × 103

= 1 kHz
For D.C. gain, ω = 0
R2 159 × 103
∴ H(0) = = = 10
R1 15.9 × 103
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [290]
2nd dB, HdB = 20 log10 10 = 20 dB
Q.93 Ans.(a)
R Va R Vb C/2 Vc C/2
+ a b c
R/2
VI C –
+ +
VO
 
R = 1 M
C = 0.5 F
The type of filter can be determined from the transfer function of circuit in s-domain. So transfer
function of circuit will be obtained first. From which conclusion will be drawn about type of filter.
KCL at node (a),
Va − Vi Va − Vb Va − 0
+ + =0
R R 1 / sC

As node ‘b’ is at virtual ground, So, Vb = 0

2  V
⇒ Va  + sC  = i
R  R

Vi
⇒ Va = ......(i)
2 + sCR

KCL at node (b),

0 − Va 0 − Vc
+ = 0
R 2 / sC

sCR
Va = − Vc .....(ii)
2

From (i) and (ii), we have,

sCR 1
− Vc = Vi
2 2 + sCR

2
⇒ Vc = − × Vi ...(iii)
sCR(2 + sCR)

KCL at node (c),

Vc − 0 V V − Vo
+ c + c =0
2 / sC R / 2 2 / sC

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [291]

 2 sCVo
⇒ Vc sC +  =

 R 2

sCR
⇒ Vc = Vo ....(iv)
2(2 + sCR)

From (iii) and (iv), we have,

sCR 2
⇒ Vo = − × Vi
2(2 + sCR) sCR(2 + sCR)

Vo 4
⇒ = −
Vi (sCR) 2

In frequency doman, s = jω
Vo 4
∴ = 2
Vi ω CR

Gain of circuit reduces as ω increases so given filter like low pass filter.
Q.94 Ans.(b)
Z2
{

R2
Z1
{

R1 +5V
C
+ –
input v+i
– +
– vo (output)
+
–
–5V
Transfer function of circuit,
Vo (s) Z R2
= – − 2 =
−
Vin (s) Z1 1
R1 +
sC
Vo (s) R / R1
⇒ = − 2
Vin (s) 1
1+
sC R1

For frequency domain, s = jω

Vo ( jω) R 2 / R1 Ao
= – = −
Vin ( jω) 1 / CR1 ω
1− j 1− j c
ω ω

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [292]

1
where, ωc = rad/sec
R1C

and Ao = R2 / R1
Vo ( jω) Ao
Magnitude of gain, =
Vin ( jω) ω 
2

1+  c 
 ω

Gain of circuit increases with increase in frequency so given circuit is a high pass filter with 3dB
cutoff frequency,
1
ωc = = rad/sec.
R1C

Q.95 Ans.(b)
A major advantage of active filters is that they can be realized without inductors.
Q.96 Ans.(a)
A. Comparator

VCC

–
Vo
~ Vin +

B. Low pas filter

–
Vo
Vin ~ +

C. High pass filter

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [293]

–
Vo
~ Vin +

Q.97 Ans.(a)
R1 = 200 k

C2 C1

1 nF 1 nF
R2
–
+

Vo s / R1C1
=
Vi C + C2 1
s2 + 1 s+
R1C1C2 R1R 2 C1C2

(ωo / Q)A o s
and AV(s) =
s + (ωo / Q)s + ωo2
2

ωo C + C2
By comparing = 1
Q R1C1C2

10−9 × 2
⇒ ωo =
200 × 103 × 10−18

⇒ ωo = 104 = 1000 rad/s

Q.98 Ans.(d)
When a low pass filter (LPF) is cascaded with high pass filter (HPF) the combination behaves like
bandpass filter provided cut-off frequency of low pass section is more than high pass section. Here,
cut-off frequency of LPF is 30 Hz and that of HPF is 20 Hz. So, the cascaded connection behaves
like band pass filter.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [294]
Gain Gain

30Hz f 20Hz 30Hz f

xi
LPF HPF
x0

Q.99 Ans.(b)
Z2

{
R2
Z1

{
R1 +5V
C
+ –
input v+i
– +
– vo (output)
+
–
–5V

Transfer function of circuit,

Vo (s) Z R2
= − 2 =
−
Vin (s) Z1 1
R1 +
sC

Vo (s) R / R1
⇒ = − 2
Vin (s) 1
1+
sC R1

For frequency domain, s = jω

Vo ( jω) R 2 / R1 Ao
= – = −
Vin ( jω) 1 / CR1 ω
1− j 1− j c
ω ω
1
where, ωc = rad/sec
R1C

and Ao = R2 / R1
Vo ( jω) Ao
Magnitude of gain, =
Vin ( jω) ω 
2

1+  c 
 ω

Gain of circuit increases with increase in frequency so given circuit is a high pass filter with 3dB
cutoff frequency,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [295]

1
ωc = = rad/sec.
R1C

Q.100 Ans. (15 to 16)

0.47µF

C
22k 22k
–
R R vo
vin ~ 0.47µF C +
RF
91k
R1 82k

The circuit given above is a second order low pass filter having cutoff frequency,

1
fH =
2πRC

Given, R = 22kΩ, C = 0.47 mF

1
fH = = 15.39 Hz
2π × 22 × 10 × 0.47 × 10−6
3

Q.101 Ans. : (3.1 to 3.26)

R2

R1 C
Vi –
Vo
+

Transfer function of the circuit can be given by,
 1 
 × R2 
jωC
 
 1
 + R 2 
Vo j ωC R 2 / R1 Ao
− =−

Vi
= R1 1 + jω CR 2 = − ω
1+ j
ωc
R2
Where, Ao = = DC gain of circuit
R1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [296]

1
wc = = cutoff frequency of the circuit
CR 2
1
⇒ fc =
2π CR 2
For given circuit, C = 10 nF, f = 5 kHz
1 1
⇒ R2 = = = 3.18 kHz
2π f c C 2π × 5 × 103 × 10 × 10−9

Q.102 Ans. (b)

R/2

+Vsat
R –
F1
+
Vo
Vi F2 –Vsat
R

The given circuit is a summing amplifier. The frequency
(c) response of the circuit will be overlap of
frequency response of Filter F1 and F2 as shown below.

F1 F2
Vo/Vi
Vi Vo
f1 f2
f

The frequency response of the circuit shown above represents a band reject filter. Thus circuit exhibits
the characteristics of a band reject filter.
Q.103 Ans. (a)
R2

Vin R1 +15V
– Vout
+
–15V

Circuit shown above represents a low pass filter.
Q.104 Ans.(c)
The operational amplifier is used in non linear mode in schmitt trigger.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [297]
Q.105 Ans.(d)
I/P –
+ O/P

Output of above circuit is a square wave because it is a comparator circuit with zero voltage reference.
Q.106 Ans.(d)
vin= Vmsin t
–

+ Vo

When one input of comparator is grounded and another is given sine wave the output of comparator
is a square wave.
Q.107 Ans.(d)
R R

R
– 0.5 R
R –
+ S Vo
Vin +

Case-I : When input voltage is positive, with Vin = +V, switch ‘S’ is closed
The circuit becomes,
R R

R
+V – 0.5 R
R (1) –
+ (2) Vo
+

Output of opamp 1,
R
V01 = – ×V =−V
R

Output of op-amp 2,
R R
Vo = − × V01 − × V
0.5R R

⇒ Vo = – 2 × (–V) – V = V
Case -II : When input voltage is negative with Vin = – V,
switch ‘S’ is open
The circuit becomes,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [298]
R R

R
–V – 0.5 R
R (1) –
+ (2) Vo
+

Output second opamp (2),

R
Vo = – × (− V) = V
R

In both cases Vo is positive so the circuit behaves like a precision rectifier.

Q.108 Ans.(b)

C +12V
–
RL

~ Vin
+
–12V
P

Vin

The circuit shown above is peak clamper with, Vref = 0V

The waveform of output voltage is as shown below,
Vin

t
–Vm
–2Vm
Q.109. Ans (c)
R

R
+Vsat
R +Vsat
vi –
R
–
+ vo1
vo
R +
–Vsat
R
–Vsat

The given circuit consists of a negative have wave rectifier followed by inverter circuit. The rectified
negative half cycles are simultaneously inverted by the rectifier. The output of rectifier stage is again

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [299]
inverted by the inverter circuit connected at the output of the rectifier. For the positive half cycle the
output of the circuit is zero. For negative half cycle of input voltage , the output of input rectifier
stage is positive and output of inverter stage is negative. The output of circuit is zero for positive half
cycle of input and same as input for negative half cycle. The transfer characteristics of the circuit can
be drawn as under,
Vo

1 Vi

Q.110 Ans. (a)
Vss
Vin +

–
D
–Vss
V0
R

The output of the op-amp is positive for positive value of input and diode is forward biased. The
circuit works like a voltage follower for positive value of input and the output voltage is same as
input voltage. The output of op-amp is negative for negative value of input voltage and diode is
reverse biased and output of the circuit is zero for negative value of input voltage. The transfer
characteristics of the circuit can be drawn as under,
Vo

Vin

Q.111 Ans.(c)

R
–
Vin + VOut

The circuit shown above is a logarithmic amplifier.

Q.112 Ans.(d)
I

Vi +V–
–
‘a’
2k
+ Vo

For ideal op-amp,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [300]
V– = V+
Here V+= 0, So V– = 0V = Va
0 − Vi
KCL at node ‘a’, +I =0
2

Vi
⇒ = I
2

V/V
Given, I = Io e T

Here, V = Va – Vo = 0 – Vo = –Vo
Vi − V /V
⇒ + = Io e o T
2

when Vi = 2V,
⇒ +1 = Io e –V01 /VT

−V01 1
= n
VT Io

V01 = VT n Io ......(i)
when Vi = 4V,
4 − V /V
= Io e 02 T
2

Io
⇒ V02 = VT n ......(ii)
2

From equation (i) and (ii) we have,

 I 
V01 – V02 = VT nIo − n o 
 2

⇒ V01 − V02 =
VT n2

Q.113 Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [301]

+
1 k VBE –
–
Vout
+
5V +
–

When Op-amp is connected in inverting mode the output voltage is negative. The negative output
voltage makes base-emitter junction of BJT as forward biased
So, Vout = – VBE = – 0.7 V
Q.114 Ans.(b)

+
1 k VBE –
–
Vout
+
5V +
–

When Op-amp is connected in inverting mode the output voltage is negative. The negative output
voltage makes base-emitter junction of BJT as forward biased
So, Vout = – VBE = – 0.7 V
Q.115 Ans.(b)

+
1 k VBE –
–
Vout
+
5V +
–

When Op-amp is connected in inverting mode the output voltage is negative. The negative output
voltage makes base-emitter junction of BJT as forward biased
So, Vout = – VBE = – 0.7 V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [302]
Q.116 Ans.(b)
The most commonly used amplifier in sample & hold circuit is a unity gain non-inverting amplifier.
Q.117 Ans.(a)
Input buffer of a sample and hold circuit should have high slew rate so that high sampling frequency
can be used and output buffer should have low bias current so that capacitor holds the last sample.
Q.118 Ans.(d)
Vg
+12 V
G –
D S
+ vo
vi C –12 V
Vsub 1 nF

In order to maintain cutoff condition for all the sustrate-to-channel junctions, the substrate of
n-MOSFET in the circuit should be connected to most negative potential and the substrate of
p-MOSFET in the circuit should be connected to most positive potential. So, the substrate voltage of
n-MOSFET of given sample and hold circuit should be kept at −12 V.
The nMOSFET of sample and hold circuit should be turned on during sampling period and should be
turned off during hold period.

Condition of turning ON of n-MOSFET:

VG − VD > VT

or VG > VT + VD
Where VG is gate voltage, VD is drain voltage and VT is threshold voltage of MOSFET. Here the input
voltage of sampler and hold circuit is connected at the drain terminal of MOSFET. The range of input
votlage is from −5 V to + 5 V. So, the drain voltage of the MOSFET is varying from −5 V to + 5 V
and threshold voltage of MOSFET is +2 V.
When VD = −5 VG > 2 − 5
⇒ VG > − 3
When VD = +5 VG > 2 + 5
⇒ VG > + 7
MOSFET will be ON for whole range of input voltage during sampling period if VG > + 7
Condition of turning OFF of n-MOSFET:
VG − VD < VT

or VG < VT + VD
When VD = −5 VG < 2 − 5
⇒ VG < −3
When VD = +5 VG < 2 + 5
⇒ VG < + 7

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [303]
MOSFET will be OFF for whole range of input voltage during hold period if VG < −3.
Q.119 Ans.(b)

Vg
+12 V
–

+ vo
vi C –12 V
Vsub 1 nF

Given, sampling rate, fs = 1kHz

Input bias current of opamp = 1 nA
Convertion time of A/D converter, Tcon = 200 µs
So, hold period of circuit, Thold = 1/fs = 1 ms

The capacitor discharges through input terminals of opamp due to input bias current of opamp during
the hold period. If conversion period of A/D converter connected at output of S&H is finite, the
capacitor gets discharged due to input bias current of opamp during the convertion of sampled signal
from analog to digital. During hold period the sampled voltage across the capacitor should remains
constant. So, the change in voltage across the capacitor of the circuit duing conversion time of
A/D converter gives the hold error of the circuit. The change in voltage across the capacitor during
convertion period can be given as under,
Tcon
1 I bias
ÄVc =
C ∫I
0
dt
=
bias
C
× Tcon

I bias
⇒ ÄVc = × Tcon
C

10 × 10-9
= × 200 × 10-6
1 × 10-9

= 2 mV
Thus the hold error of the given S & H circuit is 2 mV.
Q.120 Ans (b)
For a given sample-and- hold circuit, if the value of the hold capacitor is increased, then droop rate
decreases and acquisition time increases.
Q.121 Ans.(d)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [304]
+ 15 V
–
R
+ V0
+1V – 15 V

The circuit shown above has positive feedback with input given at non-inverting terminals so, output
of circuit is +Vsat = +15V.
Q.122 Ans.(a)
V1 +
V0
V2 –

When V1 > V2 the output is +Vsat (say binary ‘1’) and when V1 < V2 the output becomes –Vsat (say
binary ‘0’). So, the circuit works like 2 level or one bit quantizer.
Q.123 Ans.(d)

The circuit shown above is comparator operated in inverting mode. So its out is a square with
waveform as under,
Vin

Vout

Q.124 Ans.(d)
–
Vin + V0
R1

R2

The circuit shown above is a Schmitt trigger.

Q.125 Ans.(c)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [305]

+15V
10k

–
Vi
+ Vo
a
10k
10k

–15V

Applying KCL at node ‘a’, we have,

Va − 15 Va + 15 Va − Vo
+ + =0
10 10 10

⇒ Va = Vo / 3
15
when Vo = + 15, Va = VUT = = 5V
3

15
when Vo = – 15V, Va= VLT = – = −5V
3

So, the voltage at non inverting terminal switches between –5V and +5V.
Q.126 Ans.(b)
5V

1V 3V Vi
(VL) (VH)
Noise margin of schmitt trigger is equal to hysteresis band of hysteristic characteristic.
∴ Noise margin = VH – VL = 3 – 1 = 2 V
Q.127 Ans.(d)
Vin –
Vo
+

+
9k
Vref 1k
–

The circuit shown above is a Schmitt Trigger with feedback voltage,

1 Vo
Vref = × Vo =
1+ 9 10

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [306]
when, Vo = – 10 ; Vref = – 1V
and when Vo= + 10, Vref = +1V
When input voltage increases gradually from –10V to +10V the output changes from +10 to –10V at
the instant when input cross +1V level.
Vin
+10V

+1V

–1V t

–10V

Vout
+10V

–10V

Q.128 Ans.(d)
1 k 6V
Vin –
Vout
+
–3V 2 k

+
VF 1 k
–

The given circuit is a regenerative comparator or schmitt trigger. The output of regenerative
comparator is a square with output voltage having +Vsat on positive side and –Vsat on negative side.
Here, +Vsat = +6V and –Vsat = –3V
So, output will be a square wave with output oscillating between –3V and +6V.
1 1
Feedback voltage, VF = × Vout = Vout
1+ 2 3

1
when, Vout= + 6V, VF = × 6 = +2V = VUT = Upper threshold voltage
3

when Vout = –3V,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [307]

1
VF = × (−3) = –1 V = VLT
3

= Lower threshold voltage

Waveforms :
Vin

+2V
+1V
t2 tu t
–1V

Vo
+6V
tq
t
t2
–3

Q.129 Ans. (8.0 to 8.5)

v(t)
o
5V
output

10k 2V 3V
1µF input

From the characteristics of Schmitt trigger it is observed that the output voltage varies between
0 V and 5 V and lower and upper threshold value of input feedback voltages are 2 V and 3 V ,
respectively. When input feedback voltage decreases to 2 V the output becomes 5 V and when input
feedback voltage increases to 3 V the output voltage becomes 0 V. The waveforms of input and
output voltages can be drawn as under

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [308]
vc

3V
2V
t

vo

5V

t
tc td

,
The voltage across capacitor is feedback voltage of the Schmitt trigger. During charging period when
vo(t) is +5V, the voltage across capacitor is given by,
t
−
vc(t) = v c∞ − ( v c∞ − v co + ) e
RC

Here, vc∞ = +5V, vco+ = 2V, RC = 10 × 103 × 10 –6 = 10–2

t
−
⇒ vc(t) = 5 - ( 5 − 2) e 10−2
5 − 3e −100t
=

At t = tc, vc(t) = 3V
−100t
⇒ 3 = 5 − 3e c
⇒ tc = 4.05 ms
During discharging period, vo(t) = 0V,
∴ vc∞ = 0, vco+ = 3V
Taking t = tc as reference time
⇒ vc(t) = 0–(0 –3) e –100t
At t = td, vc(t) = 2V
−100t
⇒ 2 = 3e d
⇒ td = 4.05 ms
Time period of output voltage,
T = tc + td = 4.05 + 4.05 = 8.1 ms

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [309]
Q.130 Ans. ( 1 )
R2 = 20k

R1
a +
Vout
–
Vin +
–

The given circuit has positive feedback so its output is saturated at +5V.
Applying KCL at node ‘a’, we have,
Va − Vin Va − Vo
+ =0
R1 R2

R1 R2
Va = × Vo + × Vin .....(i)
R + R2 R1 + R 2

The output voltage becomes +5V when voltage at node becomes positive. Let Vin = Vin1 when Va = 0+
R1 R2
⇒ 0 = ×5+ × Vin1
R1 + R 2 R1 + R 2
R1
⇒ Vin1 = − ×5
R2

The output voltage becomes –5V when voltage at node ‘a’ becomes negative. Let Vin = Vin2 when va
= 0–.
R1 R2
0 = ( −5) + × Vin 2
R1 + R 2 R1 + R 2
R1
⇒ Vin2 = + ×5
R2

The hysteresis band of the circuit can be given as,

R1  R  2R1
VH = Vin 2 − Vin1= × 5 −  − 1 × 5 = ×5
R2  R2  R2

Given, VH = 500 mV, R2 = 20 kΩ

2 × R1
⇒ 500 × 10−3 = ×5
20 × 103
⇒ R1 = 1 × 103 = 1kΩ

Q.131 Ans. (b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [310]

+ – Vout
Vin
– + 10 k
a
5 k
+ 3V
–

Vo − 3
Voltage at node ‘a’, Va = × 5 + 3V
15

The voltage at node gives the threshold voltage at which output changes its state.
when, Vo = +15V, the threshold voltage
15 − 3
Va = × 5 + 3V =7V
15

when, Vo = −15V, the threshold voltage

−15 − 3
Va = × 5 + 3V =−3V
15

The upper and lower threshold voltages for the circuit are +7V and –3V, respectively.
Q.132 Ans. : 0.6 to 0.7
+15V

vi
– 1 k vo

+
Vz
10 k
–15V
Vz

0.5 k

+2V

vo − 2
Voltage at node ‘a’, va = × 0.5 + 2V
10.5

The voltage at node gives the threshold voltage at which output changes its state. For an ideal op-amp

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [311]
the voltage at inverting terminal is same as voltage at non-inverting terminal.
So, va = vi
vo − 2
⇒ vi = × 0.5 + 2V
10.5

The zener-diode combination maintains the output between ±7V.

when, vo = +7V, the threshold value of input voltage,
7−2
vi1 = × 0.5 + 2V =
2.23V
10.5

when, vo = −7V, the threshold value of input voltage,

−7 − 2
vi2 = × 0.5 + 2V =
1.57V
10.5

The width of hysteresis band is given by,

vH = vi2 - vi1 = 2.23 - 1.57 = 0.66 V
Q.133 Ans.(d)
R

v1 R +12V
+ – +12V
vi 1 –
+ v01 2
–
v2 R –12V + +
R –12V
vo
R R –
– vf +
Outputof op-amp 1,
v01 = –v1 + v2 = v2 – v1 = –vin
Let, vin = vm sin ωt
Op-amp 2 has positive feedback so its output is either + 12 V or – 12V. The circuit of op-amp 2 is
Schmitt trigger with,
R
vf = × Vo
R+R
When, vo = 12 V
R
vf = VUT = × 12 = + 6V = Upper threshold voltage
R+R

When, vo = – 12

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [312]

R
vf = VLT = × (−12V) = – 6V = Lower threshold
R+R

Waveforms :
vm
+6V

–6V
–vm
v01
+vm
+6V

–6V

vo
+12V

–12V

Transfer characteristic of overall circuit,

vo

–vm –6V +6V vm vin

Q.134 Ans.(a)
R1

–
Vo
+
R3
C

R2
R4

The astable multivibrator is non-linear application of op-amp in which the output voltage is a square
wave with ± Vsat amplitude. So the amplitude of output voltage of the circuit is independent of
resistance R2.
The time period of output square wave of the circuit is given as,
 2R + R 3 
T = 2(R1 + R 2 )Cln  4 
 R3 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [313]
The frequency of the output wave depends on time constant (R1+R2)C. So only frequency of the
output is function of R2.
Q.135 Ans.(d)
Vin –
Vo
+

+ 10k
Vref 5k
–

5
Vref = × Vo
15

when, Vo = + 15, Vref = + 5V

when, Vo = – 15, Vref = – 5V
Vin
+10V
+5V
t
–5V T1 T1
–10V

Vout

+15V
T1 T
t
–15V

From input waveform for 0 < t < T

20
Vin(t) = × t – 10
T

At t = T1, Vin = + 5V
20
⇒ 5 = × T1 − 10
T
T1 3
⇒ =
T 4

Average output voltage,

T1 (T − T1 )
Voav = × 15 − × 15
T T

3  3
⇒ Voav = × 15 − 1 −  × 15 = 7.5 V
4  4

Q.136 Ans.(a)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [314]

Vin –
Vo
+
R1

+
Vf R2
–

Vin
+5V
+0.1V
t
–0.1V
–5V
Vout
+Vgap
t
–Vsat
td

Given, Vin = 5 sin 1000 πt

The output of circuit changes it level when input becomes 0.1V in positive slope.
∴ Vin = 0.1 V at t = td
where td is delay time between zero crossover points of input and output signals.
⇒ 0.1 = 5 sin 1000 π td
1  0.1 
td = sin −1   = 6.37 µs
1000π  5 

Q.137 Ans.(b)
R
C
–
+ V0
R2=R

R1=R

Given circuit is square wave generator with output wave having time period,
 2R + R 2 
T = 2 RC n  1  Given, R1
 R2 
=
R2 = R
⇒ T = 2 RC n3
⇒ T = 2τ n 3
where, τ = RC
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [315]
Q.138 Ans.(c)
R1

C R2
Vp + Vo
–
2k D1
10k

10k D2

The output voltage of above circuit oscillates between –12V and +12V.
when, Vo = + 12,
D1 → OFF & D2 → ON
10
∴ Vp = × 12 =
+ 6V
10 + 10

when Vo = – 12,
D1 → ON & D2 → OFF
10
∴ Vp = × (−12) =−10 V
10 + 2

The voltage at point ‘p’ oscillates between – 10V and + 6V.

Waveforms,
Vo
12 V
t
–12 V
Vp

+ 6V
t1 t2 t
–10 V

Vc
+ 6V
t
–10 V

Note : Given circuit is a astable multivibrator.

Q.139 Ans.(c)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [316]
+10V

1k +10V
a – V0
Vout
0.01µF 10k
–10V 5.0V
S
5.0V
100k

–10V
The circuit has positive feedback so output of op-amp is ± Vsat. The output voltage Vout is clipped at
±Vz.
When switch is closed, V– = –10V and output voltage of op-amp V0′ becomes +10V.
100 10
Also, V+ = × Vz =Vz
110 11

When V0′ is +10V the Vout is clipped at Vz = +5 because of zener diode.

10 50
So, V+ = + × 5 =+ V
11 11

When switch is open circuited the capacitor starts charging with,

vc(t) = Vc max(1–e–t/RC)
Vc max → Maximum voltage to which capacitor can be charged.
From given circuit,RC

= 1×103×0.01×10–6 = 10–5 and Vc max = 10 –(–10) = 20V
Voltage at node a,
 t
− −5 
Va = vc – 10 = 20 1 − e 10  − 10
 

50
Let Va = at t = t1,
11

50  t
− 1−5 
⇒ = 20 1 − e 10  − 10
11  
⇒ t1 = 12.99 µsec
50
When voltage at node ‘a’ reaches V the voltage of inverting terminal becomes more positive than
11
non-inverting terminal and output of 10V op-amp changes from –10V and Vout change from +5V to
–5V.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [317]
Q.140 Ans.(d)

vi C2 +12 V
–
R2 vo
+
–12 V
– 2V R1

C1
The given circuit is a monostable multivibrator whose operation can be explained as follows,
When input signal is vi is zero the input to inverting terminal is -2 V and output of op-amp is +12
V. When an input triggering pulse is applied such that input to inverting terminal becomes positive,
the output of op-amp becomes -12 V and capacitor first discharges and then charges in opposite
direction. During this process of discharging and charging the voltage across R1 becomes positive
and more than 2 V the output of op-amp changes from -12 V to +12 V and remains same until input
triggering pulse is again applied to the circuit.
Q.141 Ans. (1.2 to 1.3)
R

+5V
–
C Vo
+ –5V

a 3k D1
+
Vref 1k D2
1k
_

The given circuit is astable multivibrator whose output is a square wave with amplitudes of -5 V and
+5 V.

Case-I : When output is +5V

The diode D1 is forward biased land diode D2 is reverse biased. So diode D1 acts like short circuit and
D2 acts like open circuit.
Reference voltage becomes,
1 1
Vref = × 5 = × 5 = 1.25V
1+3 4

Case-II : When output is –5V

The diode D1 is reverse biased and D2 is forward biased.
The reference voltage becomes,
1
Vref = × ( −5) =−2.5V
1+1
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [318]
The wave forms of capacitor voltage and output voltage can be drawn as under
Vo
5V

+ 1.25V
t

–2.5V
–5V
t1 t2

Voltage across capacitor during positive value of output voltage can be given by,
t

vc(t) = v c∞ − ( v c∞ − v co + ) e
−
RC

Here, vc∞ = +5V, vco+ = –2.5V

At t = ∆t1, vc(t) = 1.25 V
∆t 1
−
⇒ 1.25 = 5 − 5 − ( −2.5)  e RC

∆t 1
−
⇒ 7.5e RC
= 3.75
∆t 1
7.5
e RC
= =2
3.75

Taking ∆t1 as reference time, the voltage across capacitor can be given by
t
−
vc(t) = v c∞ − ( v c∞ − v co + ) e RC

Here, vc∞ = –5V, vco+ = 1.25 V

At t = ∆t2, vc(t) = – 2.5 V
∆t 2
−
⇒ –2.5 = −5 − ( −5 − 125) e RC

∆t 2
6.25
⇒ e RC
= = 2.5 .....(i)
2.5
From (i) and (ii), we have,
e ∆t1 / RC 2
= = 0.8
e ∆t 2 / RC 2.5
∆t1 −∆t 2

⇒ e RC
= 0.8

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [319]
Q.142 Ans. (a)
The given circuit is a astable multivibrator whose output is a square wave. The period of square is
given by,

T = 2 RC n 3
⇒ T = = 2×1×103×0.25×10–6 n 3 = 0.55 ms
Q.143 Ans. (0.7:0.9)
The equivalent circuit with switch S open circuited can be drawn as under,

+10V

+
vc C=100 F
_ +10V
a
– 470
VO
10 k R +
–10V Z1
b
–10V
4k Z2
1 k

0V 0V
The voltage at node ‘b’,
1 1
Vb = × Vo = × Vo
1+ 4 5

When Vo = 5V
1
Vb = − × 5 =−1V
5

Voltage across capacitor for t > 0 is given by

t
−
vc(t) = vc∞ – (vc∞ – vco+) e RC

Here, vc∞ = 20V, vco+ = 0, R = 10 kΩ = 104 Ω, C = 100 mF= 10–4 F

∴ RC = 104 × 10–4 = 1
−
t
 − 
t

⇒ vc(t) = 20 − 20e RC
=20 1 − e 1 
 

Voltage at node ‘a’,

Va = –vc + 10
⇒ Va = –20(1 – e–t) + 10
⇒ Va = – 10 + 20e–t

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [320]
Output voltage changes from –5V to + 5V when Va becomes more than or equal to Vo.
So, output changes its state when Va = Vb = –1V at t = t1
⇒ –1 = 10 + 20e–t1

⇒ 20e − t1 = 9
20
t = n = 0.798s
9

Q.144 Ans.(a)

C R
–
Vin + Vo

The circuit shown above is a differentiator. So, output of circuit,

dVin
Vo = – RC
dt

when input of circuit is a triangular wave output will be a square wave.

Q.145 Ans.(d)
v(t)

3V

t
2 msec

Time period of wave,

1
T = = 2m sec
500

Amplitude = 3V
Capacitor = 2 × 10–6 F
Voltage across a capacitor
1
v =
C ∫
idt

Voltage is linear ramp only when i is constant. So, sawtooth wave can be generated by charging
capacitor with a constant current source.
I
∴ v = t
C

At t = 2 msec, Vc = 3V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [321]

I
⇒ 3 = −6
× 2 × 10−3
2 × 10

⇒ I = 3mA

So, changing of capacitor requires at constant current source of 3 mA for 2msec

Q.146 Ans.(a)
Cutoff frequency of Amplifier,
UGB
fo =
A

when, A → gain of amplifier

UGB → unity gain bandwidth
1 × 106
⇒ fo = = 100 kHz
10

Given, frequency of input signals 11 kHz Amplitude of input, Vi = ± 1V, gain, A = 10

∴ Vo = A Vin
⇒ Vo = ± 10 V
Since frequency of signal is less than cutoff frequency of amplifier output of circuit is also a square
wave

Q.147 Ans.(a)
+VCC

RA 10k
7 8
RB 10k

2,6
C 4 1

The voltage across capacitor in astable multivibrator using 555 timer oscillates between
V 2V
+ CC and + CC at steady state but the capacitor starts charging from zero volt in very first cycle.
3 3
The capacitor charges through RA and discharges through RB. So, charging is period is Tc = 0.69 RA
C and discharging period is Td = 0.69 RBC Since, RA = RB = 10k, so charging &
discharging periods are equal. The waveform voltage across capcitor is as shown below,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [322]
VC (t)

2VCC
+
3
VCC
+
3

T T T T t
Time period of output wave,
T = Td + Tc = 0.69 (RAC + RBC) 0.69 × 2 RC = 1.38 RC
Q.148 Ans.(b)

9V

30 K
4 8
(Reset) (Supply)
6 (Threshold)
(output) 3
10 K
(Gnd)
2 (Trigger) 1
(Discharge)
12 K 7

VC .01 µF

Output of astable multivibrator shown above changes level when voltage at trigger pin becomes
V 2Vcc
either greater than 2VCC/3 or less than VCC/3. So, voltage across capacitor varies from cc to
3 3
. From given circuit, VCC = 9V so voltage VC varies from 3V to 6V.
Q.149 Ans.(b)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [323]
VCC – 5V

8 4

I – 5 mA 3
6 output
Vth
555
2
Vtring 7
discharge

C – 0.1 µF
1

Replacing 555 times by its equivalent circuit we have,

+VCC = + 5V
8
Vref
I=5mA
V6 Q2 4
+
R 1
B –
1
VA = VCC R
3 Control + 3
FFQ
2 R S –
VB = 3VCC Power
Amplifier
V2 A +
2
C = 0.1 F R
– Q1

In the circuit shown above the capacitor charges linearly untill V6 > VB. When V6 > VB the output of
Op-amp 1 becomes +Vsat and flip-flop FF is reset which in turn drives the BJTQ1 to saturation. When
BJT Q1 is saturated it discharges the capacitor directly to ground through pin ‘7’. When level of
discharge of capacitor reaches to +VCC/3 the output of Op-amp 2 becomes + Vsat which in turn sets
the FF and makes Q = 0 . So, BJT Q1 is driven to cutoff. The cycle of charging and discharging

repeats periodically with voltage of capacitor varying between +VCC/3 and +2VCC/3. The waveform
of Vc(t) is are shown below,
During charging,
1 t
C ∫o
Vc(t) = idt + Vco

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [324]
Here, i = 5 mA, C = 0.1µF,
Vcc
and Vco =
3

t
1 V
0.1 × 10−6 ∫o
⇒ Vc(t) = 5 × 10−3 dt + cc
3

3 Vcc
⇒ Vc = 50 × 10 t +
3
Vc (t)
2Vcc
+
3
Vcc
+
3
t
T

2Vcc
At t = T, Vc(t) =
3

2Vcc 3 V
⇒ = 50 × 10 T + cc
3 3

Vcc
⇒ 50 × 103 T =
3

Given, Vcc = +5V

5
∴ 50 × 103 T =
3

1
⇒ f= = 30 kHz
T

Q.150 Ans.(a)
5V

10k RA reset
7
Discharge
10k RB Out
6 Trigger
thereshold
Vc
Ground
1F C

In 555 astable multivibrator circuit shown above the voltage across capacitor oscillates between
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [325]

Vcc 2V
+ to + cc .
3 3

The capacitor charges through RA & RB from Vcc and discharges through RB to ground through pin 7.
Vcc 2V
Time required to charge from + to + cc ,
3 3

tH = 0.69 (RA + RB) C

Vcc 2V
Time required to discharge from + to + cc ,
3 3
tL = 0.69 RBC
when, RB = 0, tH = 0.69 RAC
and tL = 0
So, capacitor charges through RA but discharges suddenly. So the waveform of voltage across
capacitor, with RB = 0, will be as shown below,
Vc
2Vcc
+
3
Vcc
+
3
t
tH 2tH

Q.151 Ans.(c)
VCC
RA

Th
RB
Tr Vout
R1
C 555
Timer
IC
Discharge

Frequency of as 555 timer astable multivibrator is given by,

1
f = ......(i)
0.69(R A + 2R B )C

And duty cycle is given by,

RA + RB
Duty Cycle = ......(ii)
R A + 2R B

Given, f = 10 kHz
C = 10 nF
Duty Cycle = 0.75

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [326]
From equation (i),
1
10×103 =
0.69(R A + 2R B ) × 10 × 10 –9

RA + 2RB = 1.45×104 .....(iii)

From equation (ii),
RA + RB
0.75 =
R A + 2R B

⇒ RA – 2RB = 0
RA = 2RB .....(iv)
From equations (iii) and (iv),
14.5
RB = kΩ
4

⇒ RB = 3.62 kΩ
And RA = 7.25 kΩ
Q.152 Ans. (5.55 to 5.75)
Frequency of as 555 timer astable multivibrator is given by,
1
f =
0.69(R A + 2R B )C

1
⇒ f = kHz = 5.68 kHz
0.69(2.2 + 2 × 4.7) × 0.022

Q.153 Ans.(d)
10 K
5K
a – +
2 V –+ + V0
b
10 K 100 K

Applying KCL at node ‘b’, we have,

Vb − 0 Vb − Vo
+ =0
10 100

1
Vb = Vo
11
For ideal op-amp,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [327]
Va = Vb
Applying KCL at node ‘a’, we have,
Va − 2 Va − Vo
+ =0
5 10

3Va Vo
⇒ − = 2
2 2

⇒ 3Va – Vo = 4
 1 
⇒ 3 × − 1 Vo = 4
 11 

8
⇒ − Vo = 4
11

⇒ Vo = −5.5V

Q.154 Ans.(b)

+VCC

I R

E
Vref
R1
b –
a +

IL RL
R1

Voltage at non inverting terminal of op-amp,
V+ = Vcc – Vref
For ideal op-amp, V- = V+ = Vcc – Vref
∴ Voltage at emitter terminal of BJT,
VE = V– = Vcc – Vref

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [328]
Current through resistance, R
V − VE Vcc − ( Vcc − Vref ) Vref
=
IF = cc = .....(ii)
R R R

Collector current of BJT,

β
Ic = × IE
1+ β
β V
⇒ Ic = × ref
1+ β R

∴ Load current,
β V
=
Io = Ic × ref
1+ β R

Q.155 Ans.(a)
2 k

I1

a
– 1k
Vo
+ I
2 mA 2 k

I2

For ideal Op-amp V– = V+

∴ V– = 0V
KCL at node ‘a’,
0 − Vo
= 2
2

⇒ Vo = – 4V
current, I2 = Vo/2k = – 4/2k = – 2mA
Apply KCL at output terminal
I – I2 + I1 = 0
⇒ I – (– 2) + 2 = 0
⇒ I = – 4mA
Q.156 Ans.(a)
10 mH
10 F
10 
Vs – 
a –
R1 + Vo1 R b
2 + Vo

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [329]
For ideal op-amp,
V– = V+
∴ Va = 0 and Vb = 0
KCL at node, ‘a’.
0 − Vs 1

R1
−
L ∫
V01dt =
0

1 V
⇒
L∫V01dt = − s
R1

L dVs
⇒ V01 = −
R1 dt

KCL at node ‘b’,

0 − V01 dV
= C o
R2 dt

dVo V
⇒ C = 01
dt R2

1 1 L dvs L
⇒ Vo = −
R 2C ∫
V01dt = ∫· ·dt =
R 2 C R1 dt R 1R 2 C
× Vs

Given, Vs = 10 cos 100t ;

R1 = 10Ω, R2 = 100Ω ;
L = 10mH, C = 10 µF
10 × 10−3
⇒ Vo = × 10cos100t
10 × 100 × 10 × 10−6

⇒ Vo = 10cos100t

Q.157 Ans.(b)
Z1
Z

C –
Vi
R + Vo

Transfer function of circuits,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [330]

Vo Z
= −
Vi Z1

1
× R1
sC1 R1
where, Z1 = =
1 1 + sC1R1
R1 +
sC1

Vo Z
∴ = −
Vi R1 / (1 + sC1R1 )

Vo Z
= − (1 + sC1R1 )
Vi R1

Case-I when Z is series RC network

R2 C2

1 1+ sC R
From circuit, Z = R 2 + = 2 2
s C2 s C2

Vo (1 + s C2 R 2 )(1 + s C1R1 )
∴ = −
Vi s C 2 R1

Vo 1
∴ =− 1 + s(C2 R 2 + C1R1 ) + s 2 C1C2 R1R 2 
Vi sC2 R1  

Above equation represents the transfer function of a PID controller.

Case-II when Z is parallel RC network
R2

C2

1
R2 ×
sC2 R2
From circuit, Z = =
1 1 + sC 2 R 2
R2 +
sC 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [331]

Vo R 1 + s C1R1
∴ = − 2 ·
Vi R1 1 + s C 2 R 2

 1 
s+
Vo C1  C1R1  C1  s + z1 
= −  = −  
Vi C2  s + 1  C2  s + p1 
 C2 R 2 

1 1
where, z1 = , p1 =
C1R1 C2 R 2

since, R2 C2 > R1 C1 ∴ P1 < Z1

For Lag compensator pole lies nearer to origin than zero. So, transfer function represents a lag
compensator
Q.158 Ans.(d)
Vcc=+10V

Ic Rc=5 k
C +Vcc
V +
 –
B+
 – VBE –V
cc Vs=5V
RE=1.4k IE

Given, β = 150, VBE = 0.6V

Case 1: Let Op-amp has positive feedback
When op-amp has positive feedback its output voltage V is a ± Vsat = ± Vcc
Case a: Let V = +Vsat = +10V
When input voltage at base of BJT V = +10V the BJT is ON. Then,
V – VBE 10 – 0.6
IE = =
RE 1.4k

= 6.71 mA
IE 1
IC ≈ = × 6.714 mA = 6.67 mA
1 1
1+ 1+
β 150

Then voltage at collector of BJT,

VC = VCC – ICRC

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [332]
= 10 – 6.67 × 5
= – 23.35V
Vc must be less than +10V so voltage V can not be +10V.
Case b: Let V = – Vsat = – 10V
When input voltage at base of BJT, V = –10V, the BJT is off with IC = 0 A, then
VC = VCC – ICRC
= 10 – 0×5 = 10 V
When VC = +10V, the voltage at non-inverting terminal of op-amp become V+ = 10V and output
of op-amp cannot be +10V. As seen observed in above case. So, op-amp does not have positive
feedback.
Case 2: Let Op-amp has negative feedback
When op-amp has negative feedback,
V+ = V–
Here V– = +5V
∴ V+ = +5V
Then voltage at collector of BJT,
VC = V+ = +5V
Collector current,
VCC − VC 10 − 5
IC ≈ = = 1 mA
RC 5k

Voltage at emitter terminal,

 1  1 
VE = IERE = 1 +  ICRE = 1 +  1 × 1.4 V =1.409 V
 β  150 

Then voltage at base of BJT or at output of terminal,

V = VBE + VE = 0.6 + 1.409 = 2.009 V
Thus circuit has negative feedback with V = 2.009 V
Q.159. Ans.(a)
Ia

a –
eo
I
b +
R1
Ib I
+ ei –
x

R2

For ideal op-amp,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [333]
ea = eb and Ib = Ia = 0
Here, ea = eo
So, eb = eo
Then ei = eb – ex = eo – IR2
but, eo = I (R1 + R2)
⇒ ei = I(R1 + R2) – IR2 = IR1
ei
⇒ I =
R1

The circuit shown above is a unity follower with eo = ei

Q. 160 Ans.(b)
+V

R2

R1 R1

– –
V1 1 Vo
2
+ (1+)R +
R

Voltage v, at output of Op-amp 1,

(1 + δ)R
V1 = − ×V
R1

R
V1 = −(1 + δ) V
R1

Voltage at output of Op-amp 2,

R2 R
Vo = − V − 2 V1
R1 R

R2 R  R 
⇒ Vo = − V – 2  −(1 + δ) V 
R1 R  R1 

 R R 
⇒ Vo =  − 2 + 2 (1 + δ)  V
 R1 R1 

R2
⇒ V
=o δV
R1

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [334]
Q.161 Ans.(a)
3R

–
R +
1
V01 +
4R
RL Vo
+ R
– Vi – –
2
+ V02

Output voltage of Op-amp (1),

 3R 
V01 = 1 + Vi = 4 Vi
 R 

Output voltage of Op-amp (2),

4R
V02 = − Vi = – 4Vi
R

Output voltage across RL,

Vo = V01 – V02 = 4 Vi – (– 4Vi) = 8 Vi
Vo
⇒ =8
Vi

Q.162 Ans.(b)

Vin D2
2 k
+1
0 1 k D1
T T –
2 t Vin
–1
+ V0

Case-I :– Positive half cycle : During positive half cycle D1 is ON and D2 is OFF. The circuit
becomes as shown below
2k 0.7 v

1k
+
A Vo
Vin = – 1V
–

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [335]
Applying KVL at node (A),
V − (+1) VA − 0.7 − Vo
A
+ =0
1 2

2VA – 2 + VA – 0.7 – Vo = 0
Due to virtual ground, VA = 0
⇒ – 2 – 0.7 = Vo
⇒ Vo = –2.7 V
Case -II : Negative half cycle : During negative half cycle, D1 is OFF and D2 is ON, the equivalent
circuit is,
– +
–
+ Vo

The wave form of output is a shown below

Vin

0.7
T
t
T/2

–2.7

So, Average output-voltage of above waveform

T / 2 T

vo=  ∫ (−2.7)dt + ∫ (0.7)dt 
 0 T/2

1 T T
=  −2.7 × + 0.7 ×  =−1V
T 2 2

Q.163 Ans.(a)
V1
+
Vout
–
R2
b R1
a c
R1
–
R2
+ V2

For ideal opamp, V

+ = V–
∴ Va = V1 and Vc = V2
KCL at node ‘a’,
V V − Vb
a + a = 0
R2 R1

V V − Vb
⇒ 1 + 1 = 0
R2 R1
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [336]

 R 
⇒ Vb = 1 + 1  V1 ......(i)
 R2 

KCL at node ‘b’,

V − Va Vb − Vout
b + =0
R1 R1

Va + Vc
⇒ Vb =
2

2
⇒ Vb = × V0 .....(ii)
2+8

KCL at node ‘c’,

V − Vb Vc − Va
c + =0
R1 R2

 R  R
⇒ Vo = 1 + 2  Vc − 2 Vb ....(iii)
 R1  R1

 R  R
⇒ Vo = 1 + 2  V2 − 2 Vb
 R1  R1

From (i) & (iii), we have,

 R  R  R1   R2   R2 
Vo = 1 + 2  V2 − 2 1 +  V1 = 1 +  V2 − 1 +  V1
 R 1  R1  R2   R1   R1 

 R 
⇒ Vo = 1 + 2  (V2 − V1 )
 R1 
Q.164 Ans.(b)
10 k

–
Io ‘a’ Vout
+

For ideal Op-amp,

V– = V+
∴ V– = 0
KCL at node ‘a’,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [337]

0−V
o3 + Io = 0
10 × 10

Vo = 104 × Io
When, Io=100 µA ;
Vo = 1 V
When, Io = 200 µA ;
Vo = 2 V
So, when Io changes from 100 µA to 200 µA the output voltage changes from 1 V to 2 V.
Q.165 Ans.(d)
1 2
+ +
V1 1´ 2´ V2
I1 – –
1k
Vi –
R 2 Vout
+

Z parameters of 2-part network are defined by,

V1 = Z11 I1 + Z12 I2 ......(i)
V2 = Z21 I1 + Z22 I2 ......(ii)
For ideal opamp, V– = V+
Here V+ = 0
∴ V– = V1 = 0
Putting V1 = 0, in equation (i),
Z11
we have, I2 = − I1 .....(iii)
Z12

From (ii) & (iii), we have,

 Z Z 
V2 =  Z21 − 11 22  I1
 Z12 

but, V2 = Vo
Z12 Z21 − Z11Z22
⇒ Vo = × I1
Z12

Z12
⇒ I1 = × Vo ...(iv) Applying KCL at node ‘a’, we
Z12 Z21 − Z11Z22
have,
0 − Vi
+ I1 = 0
R
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [338]

Vi
⇒ I1 =
R

Putting expression of I1 in equation (iv), we have,

Vo Z Z − Z11Z22
⇒ = 12 21
Vi Z12 × R

Given, R = 1 kΩ, Z11 = Z22 = 11k

and Z12 = Z21 = 1 k
Vo 1 × 1 − 11 × 11
⇒ = −
Vi 1×1

Vo
⇒ = –120
Vi

Q.166 Ans.(b)

10k + Vz –

4k 10k
Vi –
‘a’ Vo
+

For ideal opamp,

V– = V+
∴ Va = V– = 0V
Here opamp is inverting amplifier so output is negative for positive value of input. So zener diode
operates in breakdown region.
KCL at node ‘a’,
0 − Vi 0 − Vo 0 − (Vz + Vo )
+ + =0
1 10 10

Given, Vi = 1V & Vz = 3.2 V

1 Vo 3.2
⇒ − − = 0
1 5 10

Vo 3.2 3.2
⇒ = – 1– =–5– ×5
5 10 10

= – 6.6 V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [339]
Q.167 Ans.(d)
VD VZ2
Z1 Z2

1k VZ1 VD
a Vo
Vi = sin 100t V ~

Vo

Vi

Let VZ1 is breakdown voltage of Z1 and VZ2 is breakdown voltage of Z2 and VD is voltage across
foward biased zener diode.
For ideal opamp V_ = V+ .
Here V+ = 0 , therefore, V_ = 0
Given Setting of x-axis = 0.5 V/div
Setting of y-axis = 2.0 V/div
From given transfer characteristics,
Range of input voltage = −2 divisions to +2 divisions
⇒ Range of input voltage = −2 ×0.5 V to +2 ×0.5 V or −1V to +1 V
Range of input voltage = −2 divisions to +3 divisions
⇒ Range of input voltage = −2 ×2 V to +3 ×2 V
or −4V to +6 V
Case-I: Positive Half Cycle
During positive half cycle of input voltage diode Z1 if forward biased and diode Z2 is reverse biased
and output voltage of the circuit is −4V . So diode Z2 shall work in breakdown mode during positive
half cycle. From the circuit,
0 − VD − VZ2 − Vo = 0
⇒ 0 − 0.7 − VZ2 − (−4) = 0
⇒ VZ2 = 3.3 V
Case-II: Negative Half Cycle
During negative half cycle of input voltage diode Z1 if reverse biased and diode Z2 is foward biased
and output voltage of the circuit is 6V . So diode Z1 shall work in breakdown mode during negative
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [340]
half cycle. From the circuit,
0 + VZ1 + VD − Vo = 0
⇒ 0 + VZ1 + 0.7 − 6 = 0
⇒ VZ1 = 5.3 V
Conclusion: Breakdown voltage of Z1 is 5.3 V and breakdown voltage of Z2 is 3.3 V.
Q.168 Ans.(c)
5V
IC
IB 33 k
Q1 100
– 5V
+ IE
VBE Vo
VE
1V +–

For an ideal op-amp,

V– = V+
Here, V+ = 1V
∴ VE = V– = 1V
Applying KVL in base circuit of BJT, we have,
5 – 33IB – 0.7 – 1 = 0
3.3
⇒ IB = mA
33

⇒ IB = 0.1 mA
Collector current of BJT,
IC = βIB = 99 × 0.1 mA
⇒ IC = 9.9 mA
Emitter current of BJT,
IE = IC + IB = 9.9 + 0.1 = 10mA
Applying KCL at inverting terminal of op-amp, we have,
V− − Vo
− I E = 0
100

1 − Vo
⇒ − 10 × 10−3 = 0
100

⇒ 1 – Vo – 100 × 10 × 10–3 = 0
⇒ Vo = 0V

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [341]
Q.169 Ans.(b)
1k
+5V
D1 D2
1mA
IS
a Vo
ID1 ID2 ID3

M1 M2 M3
–5V
Drain current of enhancement mode MOSFET is given by
µ n Cox W
ID = · (VGS − VT ) 2 = k(VGS – VT)2
2 L

µ n Cox W
where, k = ·
2 L

Gate terminals of all MOSFETs M1, M2, M3 are at same potential in given circuit. all MOSFETs are
matched so k is also same for all MOSFETs. Therefore, drain current of all MOSFETs in given figure
is same.
Applying KCL at node (a), we have,
ID1 + ID2 = 1mA [Gate current of MOSFET is zero]
As ID1 = ID2 = ID
∴ 2ID = 1.0 mA
⇒ ID = 0.5 mA
∴ ID3 = Is = 0.5 mA
Q.170 Ans.(a)
+5V 1k
D1 D2
1mA
IS
a Vo
ID1 ID2 ID3

M1 M2 M3
–5V
The Drain current in n-channel MOSFET always enters in the drain terminal so current IS enters into
the drain terminal of M3. The current IS behaves like a source current and reverse biases the diode D1
and forward biases the diode D2. The equivalent circuit of Op-amp can be drawn as under,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [342]
1k
D2 VD2 = 0.7V
b D1
Vo
IS = 0.5mA
–5V
KCL at node b gives,
V + 0.7 − Vo
b + 0.5mA = 0
1k

Node b is as virtual ground. So, Vb = 0

0 + 0.7 − Vo
⇒ + 0.5mA = 0
1k

⇒ Vo = 1.2 V
Q.171 Ans.(c)
0·1F 2 k 1F

1 k
– 0·1F
0·1F 1 –
+ V01 750 
Vi(t) ~ +
2
+
Vo

Given, Vi(t) = 10 + 10sin 100πt + 10sin 4000 t + 10sin10000 t

Gain of op-amp (1),

V01 1 / ( jω× 0.1 × 10−6 ) 1

= − =
− −4 ......(i)
Vi 3 1 1 + j ω× 10
10 +
jω× 0.1 × 10−6

Gain of op-amp (2),

1
2 × 103 +
V0 jω× 1·0 × 10−6 1 + jω× 2 × 10−3
= − 1
=
− .....(ii)
V01 750 + 10 + jω× 0·75 × 10−3
−6
jω× 0·1 × 10

Overall gain of filter,

V0 1 + jω× 20 × 10−4
=
Vi (1 + jω× 10−4 )(10 + jω× 0.75 × 10−3 )

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [343]

Vo 1 + ω2 × 400 × 10−8
=
Vi (1 + ω2 × 10−8 ) 100 + ω2 × (0·75) 2 × 10−6

At ω = 0
Vo 1
=
Vi 10

At if = 50Hz

Vo 1 + (50) 2 × 400 × 10−8 × 4π2

= = 0·118
Vi 1 + 4π2 × (50) 2 λ10−8 100 + 4π2 × (50) 2 × (0·75) 2 × 10−6

At
ω = 2kHz

Vo 1 + (2 × 103 ) 2 × 400 × 10−8 × 4π2

=
Vi 1 + 4π2 (2 × 103 ) 2 × 10−8 100 + 4π2 (2 × 10) 2 × (0·75) 2 × 10−6

Vo
⇒ = 1·139
Vi

At
ω = 50 kHz,

Vo 1 + (50 × 103 ) 2 × 400 × 10−8 × 4π2

=
Vi 1 + 4π2 × (50 × 103 ) 2 × 10−8 100 + 4π2 × (50 × 102 ) 2 × (0·75) 2 × 10−6

Vo
⇒ = 0·0847
Vi

It is observed that the filter has maximum gain for f = 2 kHz. Therefore, the least attenuated fre-
quency component in the output is 2 kHz.
Q.172 Ans.(a)
D1 D2

mA

Rs 10 k

1 k D3 D4
–
+ R
5V
50Hz
–
~V i +
Vo

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [344]

Input voltage, Vi = 5 2 sin100πt

Case-I Positive half cycle of input voltage

During positive half cycle of input voltage diodes D2 and D3 are forward biased. and D1 & D4 are
reverse baised. T
hen the equivalent circuit become is as under.
 D2

mA V
i
 D3 Rs

R i V
+ –
1k V
+ Vo
Vi
–
~ +

Current through milli ammeter

Vi − V +
i =
R

For ideal opamp, V+ = V- .

Here, V- = 0, therefore, V+ = 0
Vi − 0 1
⇒ i = = × 5 2 sin100π t
R 103

Case-II Negative half cycle of input voltage

During negative halfcycle diodes D1 & D4 are forward biased and D2 and D3 are reverse biased. The
equevalent circuit becomes as under
D1

 V mA

 k
i 
R
V D4
–
1k i
– Vo
Vi
+
~ +

Current through meter remains in the same direction , so the diode circuit is a full wave rectifier. The

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [345]
peak value of current through the meter,
5 2
Im =
103

Average value of current through the meter,

2I 2×5 2
=
Iav = m = 0.45 mA
π π × 103

The permanent magnet moving ammeter is an average reading instrument. So reading of given milli-
ammeter is,
Iav = 0.45 mA
Q.173 Ans.(d)
R

10k

‘b’ –
Vin
~ ‘a’ +
10k
Vout

10F R
C

For ideal opamp, V– = V+

∴ V+ = Vin
Given, Vs = 10∠0º , f = 50 Hz
Applying KCL at node ‘a’, we have,
Vin V − Vout
+ in = 0
1 / j ωC R

Vout = [1 + jωC]Vin
= [1 + j × 100π × 10 × 10 × 10–6 × 103] Vin
= [1 + j 10π]Vin
Applying KCL at node ‘b’, we have,
Vs − Vout
− Is = 0
10 × 103

1 1  1 (1 × j10π) 
⇒ Is = × Vs − Vout =  − Vs
10 × 10 3
10 × 10 3
10 × 10
3
10 × 103 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [346]

− j10π
⇒ Is = × 10∠0º mA = 10π∠–90°mA
10
Q.174 Ans. (249 to 251)
Vin
a 100 Ve +
1V
250(1+) 250(1–) e –
b –V + c
o

250 (1–) 250(1+)

f
d 100 50
R

The overall circuit works like a non-inverting amplifier with overall feedback resistance of,

250 (1 + δ ) + 250 (1 − δ )

Rf = 100 + + 100 = 450Ω
2

Voltage at output of opamp can be given by

 R   450 
Ve = 1 + f  × Vin = 1 +  × 1 = 10V
 R  50 

For ideal opamp, V– = V+ = 1V

∴ Voltage at node f, Vf = V– = 1V
The circuit of feedback path of amplifier can be redrawn as under,

If
I2 a 100 Ve =10V
250(1+) I1 e
250(1–)
b –V + c
o

250(1+) Vf =1V
250 (1–)
f
d 100
Current in feedback path,
Ve − Vf 10 − 1 9 1
IF = = = = A
Rf 450 450 50

Both branches acd and abd have equal resistances. So, the current If is divided equally between these
branches.
If 1 1 1
So, I1 = I 2 = = × = A
2 50 2 100
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [347]
Voltage drop across resistance in branch cd,
1
Vcd = I1 × 250 (1 + δ ) = × 250 (1 + 0.05 ) =2.625V
100

Voltage drop across resistance in brach bd,

1
Vbd = I 2 × 250 (1 − δ ) = × 250 (1 − 0.05 ) =2.375V
100

Voltage between node ‘c’ and ‘b’,

Vo = Vcb = Vcd – Vbd = 2.625 – 2.375 = 0.25 V
or Vo = 250 mV
Q.175 Ans. (2.9:3.1)
10V 10V

100k
8 k Vi

+VCC 6V
LED4V
– 1 2 3 4 5 6
2V
t
+ 15 k
2 k Vi –2V
–VCC –4V
–6V

In the given circuit, the LED is turned on when BJT is driven to saturation and it is turned OFF when
BJT is driven to cutoff region.
Voltage at inverting terminal of opamp,
2
V = × 10 =
2V
2+8

The BJT is driven to saturation when output voltage of opamp is +Vcc and it is driven to cutoff when
output voltage of opamp is –Vcc.
The output voltage of opamp is +Vcc when input voltage becomes more than 2V and it becomes –Vcc
when input voltage is less than 2V.
From the waveforms of input signal it can be seen that input voltage becomes more than 2V at
instants marked as 1, 3, 5 where LED is turned ON. The input voltage becomes less than 2V at
instants marked as 2, 4 and 6 where LED is turned OFF. So, in total the LED is turned ON three times
and turned OFF three times. Therefore, LED of given circuit glows three times for given input signal.

Q.176 Ans. (a)

The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [348]
by-N counter (comprising ÷2 , ÷4, ÷8, ÷16 outputs) is sketched below. The synthesizer is excited
with a 5 kHz signal (Input 1). The free-running frequency of the PLL is set to 20 kHz. Assume that
the commutator switch makes contacts repeatedly in the order 1-2-3-4.
+VCC

Input 1 Phase Low Pass

Detector Filter
Amplifier

VCO
1 2
2 4
3 8 C –VCC
R
4 16

Synthesizer
output
The frequency fed to the phase detector should be set at same level as input signal frequency for
phase comparison for which the output frequencies of synthesizer should be 2×5 kHz, 4×5 kHz, 8×5
kHz and16×5 kHz.
Q.177 Ans. (790:810; –810:–790)
RF= 1 M

+VCC
–
I Vo
+
1 M
–VCC
RL=10 k

+VCC

Given, responsivity of photo diode P = 0.8A/W

Power of incident light,
P = 10 µW
∴ Current through photodiode,
I = R × P = 0.8 × 10 µA = 8 µA
Output voltage, Vo = IRF = 8 × 10–6 × 1 × 106 = 8V
V 8
Load current, =
IL = o = mA 0.8mA
R L 10

or IL = 800 µA

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [349]
Q.178 Ans. (1:1)

V1 + V01
1
–
V03 Low Pass
Vo
Filter
V2 +
2
– V02

Given, V1 = 1 sin (300 t + 36°)

V2 = 1 sin 300 t
The waveforms of output of comparators and Ex – OR gate can be drawn as under,
V1
1V
/5 2

–1
V2
1V
2 11/5
t
/5 6/5
–1V
V01
5V
2
t
/5  5/6

V02
5V

6/5 2 t
/5 

V03
5V
t
/5  6/5 2 1/5

The output opamp 42 is 1 for positive half cycle and zero for negative half cycle as shown in figure.
Corresponding output of Ex – OR gate over one time period of input signal becomes as under
π
V03 = +5 V ; 0 ≤ w t <
5
π
= 0 V; ≤ wt < π
5
π
= +5V; πwt <
5
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [350]

6π
= 0V; < t ≤ 2π
5

The output low pass filter with cutoff voltage of 0.1 Hz is practically a DC value of signal at output
of Ex OR gate. The DC value of V03 can be given by,
 π /5 6
π
5

1  
Vo =  ∫ 5d ( ωt ) + ∫ 5d ( ωt ) 
2π 0
 π 

1  π  6π 
Vo = × 5 × + ×  − π 
2π  5  5 
1
Vo = [1 + 1] =
1V
2

Q.179 Ans. (100:100)

10 k

1 k a
–
Vo
Vy +
Vx
1 k
1 nF
CN
For ideal opamp,
V = V+
∴ Voltage at node ‘a’,
Va = Vy
Applying KCL at node ‘a’, we have,
V − 0 Va − Vo
a + =0
1kΩ 10 kΩ

 10 
Vo = 1 +  Va =11Va =11Vy
 1

Applying KCL at node ‘b’, we have,

Vy − Vx Vy Vy − Vo
+ + =0
1 1 / j ωC j ωC N

∴ Putting Vy = Vx in above equation, we have

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [351]
jωC Vy + jωCN (Vy – 11 Vy) = 0
⇒ C-10 CN = 0
1 1
⇒ CN = ×C = × 10−9 F = 100 pF
10 10

Q.180 Ans. (–2:–2; 2:2)

Light
i-to-v
converter V0

Photo
diode
Power of indent light,
P = 4 × 10 ×10–6 = 40 × 10–6 W
Current of photodiode,
I = 0.5 × 40 × 10–6 = 20 µA
Output voltage of i-to-v converter, Vo = 100 × 20 mV
⇒ Vo = 2000 mV = 2V
Q.181 Ans.(10:10)
R =)

1k a
–
Vo
b +
– 10k
5V +
10k

10
Voltage at node ‘b’, Vb = × ( −5 ) =−2.5V
10 + 10

Va + 5 Va − Vo
+ = 0
R Rθ

Rθ R
⇒ Vo = − ( −5) + 1 + θ  × Va
R  R 

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [352]
For ideal opamp, Va = Vb = – 2.5V
1000 (1 + 0.004θ )  1000 (1 + 0.004θ ) 
⇒ Vo = + × 5 − 1 +  × 2.5
1000  1000 

⇒ V0 = (1 + 0.004 θ) × 5 – (2 + 0.004 θ) × 2.5 = 0.01 θ

Sensitivity of output voltage w.r.t. temperature,
dVo
S = +0.01V / C =
= +10mV / °C
dθ

Q.182 Ans.(0 to 0)

5V
I
10.5 k

VC

– IC
2V +

ZL
Io

For ideal opamp, V– = V+
∴ V– = V+ = 2V
So, voltage at collector terminal of BJT,
Vc = V– = 2V
Current through resistance, R,
Vcc − Vc 5 − 2 30
I = = = mA mA
R 10.5 105

2
⇒ I = mA = 0.286mA
7

Biasing current of ideal opamp is zero.

∴ Ic = I = 0.286 mA
Emitter current of BJT,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [353]

1+ β
=
IE = Io × Ic
β

1 + 20
⇒ Io = × 0.286 =
0.3mA
20

⇒ Io = 300 µA
Note : As per answer key of GATE the given answer is zero mA
Q.183 Ans. (c)

R R

R
–
+ vo
2R
vs
2R
Given circuit can be redrawn as under,
c R R e

R
d
R
a –
Vo
b +
2R
2R

Vs

The star connection in feedback path of opamp can be converted to delta connection. The equivalent
resistance of each branch of delta connection becomes,
R×R
Req = R + R + 3R
=
R

The circuit can be redrawn by replacing star connection by delta connection as under,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [354]
3R

R a
–
3R e
Vo
b + 3R
2R
2R

Vs

Voltage at node ‘b’,

2R 1
Vb = × Vs =Vs
2R + 2R 2
KCL at node ‘a’ gives,
V V V − Vo
a + a + a =0
R 3R 3R
1
For ideal opamp, Va = Vb = Vs
2
1
Vs − Vo
1 Vs Vs
⇒ × + +2 = 0
2 R 2 × 3R 3R

1 1 1 Vo
⇒  + +  Vs =
2 6 6 3

 3 + 1 + 1
⇒ Vo = 3 ×   × Vs =
2.5Vs
 6 

Q.184 Ans. ( − 5)
Vm V2

R Multiplier

V1 R
– V0
a
+

Output voltage of multiplier,

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [355]
Vm = V2 Vo .....(i)
Applying KCL at node ‘a’, we have,
V − V1 Vo − Vm
a + =0
R R

For ideal opamp, V = V+

Hence, Va = V+ = 0
0 − V1 0 − Vm
⇒ + =0
R R
Vm = –V1 .....(ii)
From (i) and (ii), we have,
–V1 = V2 Vo

⇒ Vo =

Given, V1 = 15V, V2 = 3V
15
⇒ Vo = − −5
=
3

Q.185 Ans.(0.98 to 1.00)

10.1 k

20.0 k 20.0 k
I
a 20.0 k
–
Vs = 1V 10.0 k 1 –
+ Vo1 2
+
Vo2

Output voltage of Op-amp (1),
20
V01 = - × Vs =
−2Vs
10

Output voltage of op-amp 2,

20
V02 = − × V01 =− V01 =− ( −2VS )
20

⇒ V02 = 2Vs .....(i)

Applying KCL at node ‘b’, we have,
Vs − Va Vs − V02
+ −I=0
10 10.1
www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [356]
For ideal opamp, V – = V+
∴ Va = V+ = 0
V − 0 Vs − V02
⇒ s + −I=0
10 10.1
Vs Vs − V02
⇒ I = +
10 10.1

Putting Vs = Vs from equation (i), we have,

Vs Vs − 2Vs  1 1 
I = + =−
  Vs mA
10 10.1  10 10.1 

Given, Vs = 1V
1 1  −3
⇒ I =  −  × 1mA = 0.99 × 10 mA
 10 10.1 

⇒ I = 0.99 µA
Q.186 Ans. : (1.1 to 1.2)
The given circuit can be redrawn as under
31 Ic
20 k

31 Ic Vp 5 k
–
I a
b Vout
+
Q2 Q3 Q32 Ic
+ + +
VBE VBE VBE
– – 20 k
–
Q1 Ic
+
VBE1
–

Vout = –4 × 0.7 + 5Va = – 2.8 + 5Va

For an ideal opamp, V– = V+
∴ Va = Vb = VB01
⇒ Vout = –2.8 + 5Vb = – 2.8 + 5Vin
Current through transistor Q1,
Vout − VBE1
Ic1 = = Is e VBE1 / VT mA
20

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [357]
Where VT = 0.026 V = thermal voltage
VBE1
Vout − VBE1
⇒ = Is e 0.026
20

Current through 5 kΩ resistance

VP
Va − Vp VT Vout − Va
= 31Is C = .....(ii)
5 20

Given, VP = 0.7 V
0.7
Vout − Va
∴ = 31I s e 0.026
20

For ideal opamp, V – = V+

∴ Va = Vb = VBE1
0.7
Vout − VBE1
⇒ = 31Is e 0.026 .....(iii)
20

From (ii) and (iii), we have,

V − 0.7
Vout − VBE1 1 BE1
= e 0.026
Vout − VBE1 31

⇒ VBE1 = 0.7 + 0.026 ln 31 = 0.789V

From equation (ii),
Va − Vp Vout − Va
=
5 20

Here Va = VBE1 & Vp = 0.7 V

VBE1 − 0.7 V − VBE1
⇒ = out
5 20

4 VBE1 – 2.8 = Vout – VBE1

⇒ Vout = 5 VBE1 – 2.8 = 5 ×0.789 – 2.8
⇒ Vout = 1.146 V
Q.187 Ans.(c)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [358]
1k
I
R

Vin 'a' –
+ VD – Vout
'b' +

Due to virtual at node a, Va = 0
∴ Voltage across diode,
VD = Vin – Va = Vin – 0 = Vin
Current through diode,
V /V V /V
I = Io e D T = Io e in T

Applying KCL at node ‘a’,

0−V
out − I =0
R

V /V
⇒ Vout = – IR = − Io Re in T

V /V
∴ Vout ∝ e in T
Q.188 Ans.(9 to 9)
R

3k 12k
3k 3k
c a b
– –
I=0 + V01 + V02
3k

1V +
–

Voltage at node ‘c’,
VC = 1 – 3k × I
Given, I = 0
∴ VC = 1V
Node ‘a’ and ‘b’ are at virtual grounds.
∴ Va = Vb = 0

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [359]
Applying KCL at node ‘a’, we have,
Va − Vc Va − V01
+ 0
=
3k 3k

⇒ 0 – 1 + 0 – V01 = 0
⇒ V01 = –1V
Applying KCL at node ‘b’,
Vb − V01 Vb − V02
+ 0
=
3k 12k

12
⇒ V02 = − × V01 =−4(−1) =4V
3

Applying KCL at node ‘c’, we have,

Vc − Va Vc − V02
+ −I = 0
3k R

Here, I = 0
1− 0 1− 4
⇒ + =0
3k R

⇒ R = 3 × 3 k = 9kΩ
Q.189 Ans(0.01 to 0.05)
Rth ‘a’
+
Vout
+ 3V R1 –
–
‘b’
R2 R3

+
–

Voltage node ‘a’
R1
Va = × 3V
R1 + R th

Where Rth = Rthermistor = resistance of thermistor

For an opamp, with negative feedback the voltage at non-inverting terminal is same as voltage at
inverting terminal.
R1
∴ Vb = Va = × 3V
R1 + R th

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [360]
Applying KCL at node ‘b’, we have,
Vb − 0.1 Vb − Vout
+ 0
=
R2 R3

R3  R 
⇒ Vout = − × 0.1 + 1 + 3  Vb
R2  R2 

R3  R  R1
⇒ Vout = × 0.1 + 1 + 3  × ×3
R2  R 2  R1 + R th
Given, Rth = 2(1 + aT) kΩ
R3  R  R1
⇒ Vout = × 0.1 + 1 + 3  × ×3
R2  R 2  R1 + 2 (1 + αT )

Given, R3 = 2.6 kΩ, R2 = 1.3 kΩ

R1 = 1kΩ, T = 150°
2.6  2.6  1
⇒ Vout = − × 0.1 + 1 + × × 3
1.3  1.3  (1 + 2 + 300α )

∂V 1
out =
3× 3× × 300
( 3 + 300α )
2
∂α

∂Vout 2700
⇒ =
( 3 + 300α )
2
∂α

For small variation in ‘α’

∂Vout ∆Vout
=
∂α ∆α

2700
⇒ ∆Vout = × ∆α
( 3 + 300α )
2

Given, α = –(4 ± 0.25) % /°C

or α = –(0.04 ± 0.0025) /°C
Here, Dα = 0.0025
2700
∴ ∆Vout = × 0.0025 =
0.03
( 3 + 300 × 0.04 )
Q.190 Ans.(1 to 1)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [361]
R2 Vo
10 k
D2
20 k D1
–
R1 + V/M Volt
2 sin 500 t
volts ~v in
meter

The given circuit is a half wave rectifier. The diode D1 is forward biased and D2 is reverse biased
during positive half cycle of input supply and the output voltage is zero. The diode D1 is reverse
biased and D2 is forward biased during negative half cycle. The output voltage during negative half
cycle is,
R2
vo = − × vin
R1

Peak output voltage during negative half cycle of input voltage,

10
vom = − × ( −2π ) =π
20
vin
2

–2
vo


A PMMC instrument reads average value of the output signal. The average value of half rectified
wave at output circuit is,
Vom π
Vo, av = = = 1V
π π

∴ Reading of PMMC voltmeter is 1V.

Q.191 Ans.(0.45 to 0.55)

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [362]
100 nF
a
– 20 k C
b 1 –
100  R1 +– + V01 R4 2 Vo
+
Vx
R3

99.9 k
R2 100 

Given circuit has a comparator at input stage and an integrator at output stage.
Initially, voltage at node ‘b’, Vb = Vx = – 0.5
Here, Va = 0
When voltage of non-inverting terminal is negative and more negative than voltage of inverting
terming, the output Vo1 of comparator is –Vsat. Where Vsat is saturation voltage of opamp 1.
∴ Vo1 = Vsat
The voltage Vo1 is input to integrator at output stage whose output can be given by
t t t
1 1 1
Vo = − ⋅ ∫ Vo1dt =
− ∫ (−Vsat )dt = ∫ Vsat dt
R 4C 0 R 4C 0 R 4C 0

1
Vo = Vsat t
R 4C

Thus, output voltage of output stage is a ramp signal.

Voltage at node ‘C’,
R2 100  1 
VC = = × Vo 3
× × Vsat × t 
R2 + R3 100 + 99.9 × 10  R 4 C 

The wave form of VC can be drawn as under,

Vc

0.5 mV

t
t

At certain point of time t′ voltage at node ‘C’ becomes + 0.5 mV. Then voltage at non-inverting
terminal of opamp 1 becomes,
Vb = VX – VC = 0.5 – 0.5 = 0 mV

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [363]
At time t′ the output voltage of integration circuit becomes
R2 + R3 100 + 99.5 × 103
Vo = = × VC × 0.5mV = 0.5V
R2 100

The moment Vb tries to become more than zero the output opamp 1 changes to +Vsat and output
voltage of opamp 2 tries to fall below 0.5 V and voltage at node ‘b’ of opamp 1 tries to becomes
negative which change voltage Vo1 to – Vsat and thus output of circuit Vo is maintained continuously
of 0.5 V.
Q.192 Ans.(7)
1 k

1 k ‘e’ 1 k 3 k
1 k
–
a 1 c –
+ V1 2
b d +

3V +
– 2V +
–

For opamp with negative feedback V+ = V–

∴ Va = Vb = + 3V
and Vc = Vd = 2V
Apply KCL at node ‘a’, we have,
Va Va − V1 Va − Vc
+ + =0
1k 1kΩ 1kΩ

3 3 − V1 3 − 2
⇒ + + =0
1kΩ 1kΩ 1kΩ

⇒ V1 = 7V

Q.193 Ans.(–4 to –4)

8 k

Ix a
+
+ Vo
b –
Vx
–

1 k 2 k

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [364]
For an ideal opamp, V+ = V–
∴ Vb = Va = Vx
Applying KCL at node ‘b’, we have,
Vb − 0 Vb − V0
+ = 0
1kΩ 2k

 2
V=
o 1 +  Vb = 3Vb = 3Vx
 1

Current through 8 kΩ resistance,

Va − Vo Vx − 3Vx
Ix = =
8kΩ 8kΩ

Vx
⇒ = – 4 kΩ
Ix

Q.194 Ans(c)
The output of a differentiator circuit in time domain is given by,
dvin
vo =
dt
d
For frequency domain, = jω
dt

∴ vo = jω vin
Transfer function in frequency domain,
vo
G(jω) = = jω
vin

∴ |G jω| ∝ ω
Q.195 Ans.(14.5 to 15.0)
2µF

1/2s
7µF ‘X’ 4µF
Gain Vo
‘G’
1/7s 1/4s A
Vs + 1/3s 3µF Ceq
–
B

The capacitance seen across terminals AB can be obtained by connecting a source Vx across AB and
replacing source Vs by ground as under. The equivalent circuit is drawn in s-domain for simplicity.

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [365]
1/2s

1/7s 1/4s
G
A Ix Vo = GVx
1/3s + V
– x

Current supplied by source ‘Vx’,

Vx V − GVx
Ix = + x
1 1 1 1
 ||  + 2s
 7s 3s  4s

Given, G = – 5
Vx 6V
∴ Ix = + x
1 1 1
×
7s 3s + 1 2s
1 1 4s
+
7s 3s

Ix 1 40s 20
⇒ = + 12s = + 12s = s + 12s
Vx 1 1 14 7
+
10s 4s
Ix 104
⇒ = s = s Ceq
Vx 7

104
Where Ceq = µF = 14.857µF
7

Q.196 Ans(d)
1k
vi
+1V +5V
1 k
a +
vi
–1V b – vo

–5V

Case-I : If initial input is positive half cycle of input voltage then Vo = + Vsat = + 5. In such case DC
voltage at node a becomes
1 1
Va = × Vsat =× (5) =
+2.5V
2 2

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [366]
The amplitude of input is –1V during negative peak but voltage at node ‘a’ remains positive as its DC
value is +2.5V which is more than input peak value of -1 V. So, the output remains constant at +5V.

Case-II : If initial input is negative half cycle of input signal then output of opamp becomes –5V.
In such case DC voltage at node ‘a’, Va becomes –2.5 V. The voltage at node ‘a’ remain negative for
complete cycle of input signal because maximum value of input goes to +1 V and output of opamp
remain constant at –5V.
So, the output voltage of given circuit is constant either +5V or –5V.
Q.197 Ans(d)
R
1/jC

R C
– Vo(j)
Vi(j) ‘a’
2R b +
1/j2C 2C

For ideal opamp, V– = V+

∴ Va = Vb = 0 V
Applying KCL at node ‘a’ we have,
Va Va V − Vi ( jω) Va − Vo ( jω) Va − Vo ( jω)
+ + a + + 0
=
2R 1 R 1 R
j2ωC j ωC

Putting Va = 0 in above equation, we have,
Vi ( jω)  1
− =  jωC +  Vo ( jω)
R  R

Vo ( jω) 1 1
⇒ = − =
−
Vi ( jω) 1 + jωCR 1+
jω
ωc

1
⇒ Where, ωc = = cutoff frequency of circuit
RC

1 1
⇒ fc = =
2π RC 2π × 2kΩ × 1µF

www.digcademy.com digcademy@gmail.com
Op-amp & Its Applications EDC & ANALOG ELECTRONICS [367]

1
⇒ fc = = 79.58Hz
2π × 2 × 103 × 10−6

Q.198 Ans(6 to 6)
1 k

+5V
1 k
– Io
‘a’ Vo
+
Vi = 2V
–5V 1k

For ideal opamp, V – = V+
∴ Va = Vi = 2V
Output voltage of opamp,
 1  1
Vo = 1 +  Vi = 1 +  × 2 = 4V
 1   1

Applying KCL at output node of opamp,

Vo Vo − Va
+ − Io = 0
1k 1k

4 4−2
Io = + 6 mA
=
1k 1k



www.digcademy.com digcademy@gmail.com