Communication between 8086 and 8087

Purpose of each chip in the above block diagram is explained below.

8284:
This is clock generator IC, ‘3x’ stands for 3 times the frequency provided than the
required one to 8086. 8086 is powered with a 18Mhz crystal oscillator, even
though it is powered with 6MHz clock frequency, because 8086 has a requirement
of 6MHz clock frequency with 33% of duty cycle. There are two other pins, reset
and ready.

• Reset pin is to reset the device.

• When the Ready pin is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state. It is available at
pin 22 and is used to restart the execution. It causes the processor to
immediately terminate its present activity
8282 and 8286:
Address and data lines are multiplexed but, in real both the quantities should be
separated from each other. So there are two other chips that should be integrated
with 8086 to separate address and data.

8282:
If ALE = 1 , multiplexed pins act as address lines, which means the address is
coming through those 20 lines ( ALE signal is also fed to 8282 IC ). If ALE = 1,
then 8282 IC allows the value through multiplexed lines and then stores the value
in it ( 8282 is a latch, it can capture the value ) Similarly BHE bar pin is also
accessed in the same way. Few pins in 8282

STB : This stands for stobe and this pin is equivalent to ALE, whenever STB = 1,
then only address is allowed inside the 8282 from 8086 or else it blocks the line.
OE bar : This is active low signal and stands for output enable.
Whenever ALE = 1, those lines carry address, which is carried to both the ICs
8282 as well as 8286. But 8286 is purely designed to accept data only.

8286:
8286 is a 8 bit data transceiver , as seen in the previous paragraph, whenever ALE
= 1, address is also entering the 8286 , to solve this issue, 8286 should be logically
disconnected when buses are carrying address to it( however physical
disconnection is not possible ) . This is done by an OE bar signal. This OE bar pin
of 8286 is connected to the DEN bar ( data enable which is an active low signal ).
DEN low signal decides whether signal from multiplexed bus should enter the
8286 transceiver or not. Once ALE = 0 , DEN bar = 0 , OE bar = 0, which means
8286 will allow the data from multiplexed bus. As 8286 is a bidirectional device ,
it should be specified whether data is Transmitted or received, which is done by T
pin of 8286.

DT/R ( R is active low ) = 1 ( transmit the data T = 1 )

DT/R = 0 ( receive the data T = 0 )

8288 bus controller:

Let’s assume there are 2 processors that are interfaced with each other to work. By
default bus master is 8086 and later according to requirements other processor can
be bus masters. So there should be bus lines between each processor and each
element in memory, IO ports, by which complexity would become very high. But
this is wrong.
In maximum mode of 8086, no processor produces control signals.
There is a device 8288 which takes a signal from the bus master and generates a
control signal.
Whichever processor is the bus master sends a signal to 8288 bus controller using
the S0’ , S1’ and S2’ pins. These 3 signals are known as status signals.
S2’ S1’ S0’ Signal generated

0 0 0 INTA

0 0 1 IO Read

0 1 0 IO Write and advanced IO write

0 1 1 Halt ( no signal )

1 0 0 Instruction fetch

1 0 1 Mem Read

1 1 0 Mem write and advanced mem write

1 1 1 Idle

8259 PIC( programmable interrupt controller ) :

8259 is an IC to increase the number of interrupts. 8087 also produces interrupts (
here interrupt is not bus master request ). Any device which wants to interrupt
8086 will send a signal to 8259.
8087 interfacing with 8086
1. 8087 sends interrupt to 8259, that goes all the way from INT of 8259
to INTR of 8086.
2. Now 8086 produces status signal of INTA’ ( shown in red color ).
3. Now INTA’ from 8288 bus controller is given to 8259.
4. 8259 produces the vector number and send it through data lines to
8086 ( shown is yellow line )
In this process, when 8259 sends the vector number through buses, that number
can also enter 8286 data transreciver , so there is an EN’/SP’ pin connected to
NAND gate of 8286.

8288 ( DEN ) 8259 ( EN’ ) 8286 will allow or not

If DEN = 0, no matter there will

DEN = 0 be nothing out from 8259 It will allow data from bus

DEN = 1 ( bus EN’ = 0 ( 8259 is sending vector 8286 will not allow
carries address ) number ) anything in it from buses
If DEN = 1 and EN’ = 1 , then only 8286 is going to accept the value from the bus
which tends to be data instead of address.

Important pins in interface:

RQ’/GT0’ :
Here RQ’ refers to the RQ bar ( active low signal ). As known that in maximum
mode, there are multiple processors who work together. In this case all the
processors cannot be BUS MASTERs , By default 8086 is the bus master. If 8087
wants to become bus master then it sends a request( RQ’ ), then 8086 grants( GT’ )
the request. Once the 8087 is done with the job of bus master it sends
to release signal , by which 8086 becomes bus master again.
TEST’ :
This pin of 8086 is connected with the BUSY pin of 8087. Whenever 8087 is
executing an instruction it makes BUSY = 1, so that while execution in 8087, 8086
can check 8087 before giving it another instruction.
But 8086 does not always check for TEST’ . It only checks when user required.
Instructions for 8086 and 8087 are written in a single program. Such a program (
code ) is known as homogeneous code.

Complete Procedure:
 1. 8087 cannot fetch an instruction.
2. All the instructions are fetched by 8086 and whatever is fetched by
8086 is also received by 8087. It means all instructions entered in
8086 and 8087.
3. Once instruction is entered in the BIU ( refer architecture of 8086 ) of
both the processors, both the processors decode them.
4. Consider the above diagram.
First instruction is for 8086. Both of them fetch the opcode and
operand of the instruction. 8087 discards the instruction as the
instruction is not for it.
How does the instruction is decided whether it is for 8086 or 8087:
Every instruction for 8087 has a code in it 11011
It’s syntax is : ESC INSTRUCTION:

5. All the red lines in the figure show that they should be executed by
8087.
6. So before every instruction of 8087, a command should be written
WAIT;
ESC INSTRUCTION;
7. Whenever the WAIT command comes, 8086 will check the TEST’
and if 8087 is free then only the next instruction will be executed by
8087.
These all instructions are fetched by 8086 and received by 8087 also, so there
should be some way so that 8087 can know that whatever is coming in it are
instructions.
8087 interfacing with 8086
Thus the S2’ , S1’, S0’ generated by 8086 are also given to 8087.

QS1, QS0:
These pins are known as Q synchronizing or Q status. These two pins synchronize
the activities of both the processors.

• 8086 is fetching all the instructions and also received by 8087.

 • 8086 now fetched a 8087 instruction and decoded it and then
discarded it, and then 8086 will fetch the next instruction, this next
instruction would overwrite the 8087 instruction in 8087 queue, so
they should be synchronized all the time.
QS1 QS0

0 0 NOP

0 1 Remove opcode

1 0 Clear queue

1 1 Remove operand
In the above situation, when 8086 discarded the 8087 instruction, then the QS1 and
QS0 ( 01 ) is sent to 8087, then 8087 will take that instruction and move it into it’s
EU.

Clear queue is the instruction when 8086 clears its queue and ask 8087 to clear its
queue too, this happens while branching.

NOP is the instruction when 8086 freezes the queue of 8087, at this moment 8087
cannot execute or decode further.

By seeing all these points it can be said that 8086 has control over 8087. Thus 8086
is master and 8087 is the slave.