ECE2002 – FAT LAB (Slot: L1)

Marks: 50
Aim & Design: 20 Marks
Implementation: 20 Marks
Results: 10 Marks

Reg. no Name Question no.

1 20BEC0156 KESHAV KUMAR Q1
2 20BEC0186 MOHAMED ISA M Q2
3 20BEC0270 RAGHAV D SARDA Q3
4 20BEC0291 KAPIL SOOD Q4
5 20BEC0420 SAMAY RAJESH Q5
6 20BEC0431 RESHMA RAMAKRISHNAN Q6
7 20BEC0433 AYUSH KAR MOHAPATRA Q7
8 20BEC0528 SRI SAMRAJ S Q8
9 20BEC0562 HARIKESH V Q9
10 20BEC0637 RAHUL Q10
11 20BEC0638 MALLIDI VAMSI LIKITH REDDY Q11
12 20BEC0640 HARIVARMAN P Q12
13 20BEC0641 DHANUSHIYA D Q13
14 20BEC0642 SATHYA P Q14
15 20BEC0643 KAVIYA K Q15
16 20BEC0646 AADHAVAN M Q16
17 20BEC0664 MALAY RAJPOOT Q17
18 20BEC0670 SANJEEV D Q18
19 20BEC0683 SUDDAPALLI SAI SANDEEP Q19
20 20BEC0689 BHASWANTH REDDY ISANI Q20
21 20BEC0693 G HARRISH Q21
22 20BEC0774 DEVANANDHITHA S Q22
23 20BEC0775 AANCHAL VERMA Q23
24 20BEC0780 VINYAS A SHETTY Q24
25 20BEC0781 AJINKYA SANTOSH BAGMAR Q25
26 20BEC0787 RASHTRA YADAV Q26
1) Design a CE amplifier using voltage divider biasing for the given specifications: VCC = 12 V, IC = 0.7 mA,
Rsig = 15 kΩ; Midband gain AM = 20, fL = 150 Hz. Assume that the nearest break frequencies to fL are 15
Hz, and 1.5 Hz. Use NPN Q2N3904 transistor.

2) Design a CE amplifier using voltage divider biasing for the given specifications: VCC = 12 V, IC = 0.8 mA,
Rsig = 12 kΩ; Midband gain AM = 25, fL = 250 Hz. Assume that the nearest break frequencies to fL are 25
Hz, and 2.5 Hz.

3) Design a CE amplifier using voltage divider biasing for the given specifications: VCC = 12 V, IC = 1.2 mA,
Rsig = 12 kΩ; Midband gain AM = 30, fL = 300 Hz. Assume that the nearest break frequencies to fL are 30
Hz, and 3 Hz.

4) Design a CS amplifier using voltage divider biasing for the given specifications: VDD = 12 V, ID = 0.7 mA,
Rsig = 15 kΩ; Midband gain AM = 20, fL = 150 Hz. Assume that the nearest break frequencies to fL are 15
Hz, and 1.5 Hz.

5) Design a CS amplifier using voltage divider biasing for the given specifications: VDD = 12 V, ID = 0.8 mA,
Rsig = 12 kΩ; Midband gain AM = 25, fL = 250 Hz. Assume that the nearest break frequencies to fL are 25
Hz, and 2.5 Hz.

6) Design a CS amplifier using voltage divider biasing for the given specifications: VDD = 12 V, ID = 1.2 mA,
Rsig = 12 kΩ; Midband gain AM = 30, fL = 300 Hz. Assume that the nearest break frequencies to fL are 30
Hz, and 3 Hz.

7) Design a class B output stage to deliver an average power of 15 W to an 10-Ω load. The power supply is
to be selected such that VCC is about 4 V greater than the peak output voltage. What are the values for the
supply voltage required, the total supply power, and the power-conversion efficiency? Simulate the circuit
and tabulate the observed values found from simulation with the theoretically calculated values.

8) Design a class B output stage to deliver an average power of 12 W to an 15-Ω load. The power supply is
to be selected such that VCC is about 5 V greater than the peak output voltage. What are the values for the
supply voltage required, the total supply power, and the power-conversion efficiency? Simulate the circuit
and tabulate the observed values found from simulation with the theoretically calculated values.

9) Design a class B output stage to deliver an average power of 18 W to an 12-Ω load. The power supply is
to be selected such that VCC is about 4 V greater than the peak output voltage. What are the values for the
supply voltage required, the total supply power, and the power-conversion efficiency? Simulate the circuit
and tabulate the observed values found from simulation with the theoretically calculated values.

10) Design a class AB output stage to deliver an average power of 20 W to an 15-Ω load. The power supply is
to be selected such that VCC is about 5 V greater than the peak output voltage. What are the values for the
supply voltage required, the total supply power, and the power-conversion efficiency? Simulate the circuit
and tabulate the observed values found from simulation with the theoretically calculated values.

11) Design a class AB output stage to deliver an average power of 22 W to an 15-Ω load. The power supply is
to be selected such that VCC is about 5 V greater than the peak output voltage. What are the values for the
supply voltage required, the total supply power, and the power-conversion efficiency? Simulate the circuit
and tabulate the observed values found from simulation with the theoretically calculated values.
12) Design a class AB output stage to deliver an average power of 24 W to an 20-Ω load. The power supply is
to be selected such that VCC is about 4 V greater than the peak output voltage. What are the values for the
supply voltage required, the total supply power, and the power-conversion efficiency? Simulate the circuit
and tabulate the observed values found from simulation with the theoretically calculated values.

13) Design a MOS differential amplifier the given specifications: VCC = 5 V, ICS = 1.2 mA, Rsig = 15 kΩ, RCS
= 150 kΩ, Differential gain Ad = 25. Find the bandwidth. Use MOSFET 1 µm technology library.

14) Design a MOS differential amplifier the given specifications: VCC = 5 V, ICS = 0.8 mA, Rsig = 12 kΩ, RCS
= 120 kΩ, Differential gain Ad = 15. Find the bandwidth. Use MOSFET 1 µm technology library.

15) Design a MOS differential amplifier the given specifications: VCC = 5 V, ICS = 0.9 mA, Rsig = 14 kΩ, RCS
= 130 kΩ, Differential gain Ad = 10. Find the bandwidth. Use MOSFET 1 µm technology library.

16) Design a MOS differential amplifier for the given specifications: VCC = 5 V, ICS = 1 mA, Rsig = 15 kΩ, RCS
= 150 kΩ, CCS = 400 fF, overdrive voltage of transistor is 100 mV. Find the gain and zero of common-
mode response when the drain resistances have a 1.5% mismatch. Use MOSFET 1 µm technology library.

17) Design a MOS differential amplifier for the given specifications: VCC = 5 V, ICS = 1.5 mA, Rsig = 10 kΩ,
RCS = 200 kΩ, CCS = 600 fF, overdrive voltage of transistor is 150 mV. Find the gain and zero of common-
mode response when the drain resistances have a 1% mismatch. Use MOSFET 1 µm technology library.

18) Design a MOS differential amplifier for the given specifications: VCC = 5 V, ICS = 0.8 mA, Rsig = 12 kΩ,
RCS = 250 kΩ, CCS = 500 fF, overdrive voltage of transistor is 120 mV. Find the gain and zero of common-
mode response when the drain resistances have a 2% mismatch. Use MOSFET 1 µm technology library.

19) Design a feedback transconductance amplifier using MOSFET for the given specifications: VCC = 5 V, ICS
= 0.6 mA, Rsig = 12 kΩ, RS = 6 kΩ, VOV = 100 mV. Find the voltage gain and the bandwidth of the amplifier
with and without feedback. Use MOSFET 1 µm technology library.

20) Design a feedback transconductance amplifier using MOSFET for the given specifications: VCC = 5 V, ICS
= 0.7 mA, Rsig = 15 kΩ, RS = 7 kΩ, VOV = 150 mV. Find the voltage gain and the bandwidth of the amplifier
with and without feedback. Use MOSFET 1 µm technology library.

21) Design a feedback transconductance amplifier using MOSFET for the given specifications: VCC = 5 V, ICS
= 0.4 mA, Rsig = 10 kΩ, RS = 10 kΩ, VOV = 120 mV. Find the voltage gain and the bandwidth of the
amplifier with and without feedback. Use MOSFET 1 µm technology library.

22) Design a RC phase shift oscillator for the given specifications: Frequency of Oscillation = 5 kHz VCC = 12
V, IC = 1.2 mA.

23) Design a RC phase shift oscillator for the given specifications: Frequency of Oscillation = 6 kHz VCC = 12
V, IC = 0.8 mA.

24) Design a RC phase shift oscillator for the given specifications: Frequency of Oscillation = 7 kHz VCC = 12
V, IC = 0.9 mA.

25) Design a CS amplifier for the given specifications: VDD = 5 V, ID = 0.8 mA, Rsig = 12 kΩ; Vov = 100 mV.
Find the gain and bandwidth of the circuit. Use MOSFET 1 µm technology library.
26) Design a CS amplifier for the given specifications: VDD = 5 V, ID = 0.6 mA, Rsig = 15 kΩ; Vov = 150 mV.
Find the gain and bandwidth of the circuit. Use MOSFET 1 µm technology library.