16CS402 – Embedded Systems- UNIT 3 COMPANY

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ARM Embedded Processor

UNIT – 3 & 4

Mr. M. Krishna Chennakesava Rao, M.E., (Ph.D.)

Assistant Professor - ECE, VFSTR, Guntur,Company
AP. LOGO

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 UNIT - III
COMPANY
LOGO

ARM Embedded Processor

History, Introduction, Architecture

Interrupt Vector

Programming the ARM, ARM Assembly Language

Instruction Set, Conditional Execution

Arithmetic and Logical Compare

Mr. M. Krishna Chennakesava Rao, Assistant Professor-ECE, VFSTR, Guntur

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  ARM Applications:
• ARM is a widely used 32 bit RISC processor used in many ES.
• Used in PDA, cell phones, multimedia players, handheld game
console, digital TV and cameras
• ARM7: GBA, iPod
• ARM9: NDS, PSP, Sony Ericsson, BenQ
• ARM11: Apple iPhone, Nokia N93, N800
• 75% of 32-bit embedded processors

• Used especially in portable devices due to its low

power consumption and reasonable performance

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 ARM – Advanced RISC Machine
Introduction …

 When used in relation to the ARM:

• Byte means 8 bits
• Half word means 16 bits (two bytes)
• Word means 32 bits (four bytes)

 Most of the ARMs implement two instruction sets:

• 32-bit ARM Instruction Set
• 16-bit Thumb Instruction Set

Advanced ARM processors:

ARM7, ARM9, ARM11 and
Cortex -A, -R, -M
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ARM History …

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 RISC - The Reduced Instruction Set Computers

RISC Architecture

 A fixed (32-bit) instruction size with few formats.

 A load-store architecture.
 A large register bank of thirty-two 32-bit registers.

RISC Organization
 Hard-wired instruction decode logic.
 Pipelined execution.
 Single-cycle execution.

RISC Advantages
 A smaller die size
 A shorter development time
 A higher performance

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 RISC vs CISC

RISC CISC
Fixed size instructions (32 bit) Variable size instructions
with few formats with many formats

Single clock reduced instructions. Multi clock complex instructions.

Register to register load and store Memory to memory load and

store instructions

Large code size, Small code size,

Low cycles per second. high cycles per second.

Emphasis on software Emphasis on hardware

Reduced hardware cost. Increased hardware cost.

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 ARM Basics…

ARM is a 32 bit RISC processor supports TDMI

T Thumb
D On-Chip Debug support
M Enhanced Multiplier
I Embedded ICE (In Circuit Emulator)

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 ARM Basics… Naming rule of ARM
ARM {x} {y} {z} {T} {D} {M} {I} {E} {J} {F} {-S}

–x: family or series (ARM 6,7,9, 10, etc.,)

–y: memory management / memory protection Unit
–z: cache (ARM 3 has on-chip cache of 4kB and ARM 7 has on-chip cache of 8kB )
–T: Thumb decoder ( 16 bit instruction set: compressed form of ARM inst.set)
–D: JTAG debugger (JTAG is an on chip testing unit) JTAG: Joint Test Action Group

–M: fast multiplier

–I: In Circuit Emulator (supports hardware debug)
–E: DSP enhanced instructions (based on TDMI)
–J: Jazelle (Java supported)
–F: floating point unit
–S: Synthesizable, suitable for EDA tools

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 ARM - Advanced Features:

 Thumb (Code density)

 MMU and MPU
 Cache
 Debug Interface
 Embedded ICE
 Fast Multiplier
 Enhanced Instructions (DSP)
 Jazzele DBX (Direct Bytecode eXecution)
 Vector Floating point Unit
 Synthesizable (RTL code is available)

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 ARM Architecture
• 3 stage pipeline organization & its features
• Instruction Set Architecture (ISA)
• Operating Modes
• Register Set
• Mode Switching
• CPSR and SPSR

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 ARM-7 Architecture

3‐stage pipeline ARM organization:

The principal components are:

The register bank
The barrel shifter
The ALU
The address register & incrementer
The data registers
Instruction decoder & control logic.

3-stage pipeline stages:

 Fetch
 Decode
 Execute

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 ARM Features
1. ARM : 32-bit Embedded RISC processor with Instruction Set Architecture (ISA)
• ISA means it constitute the instruction set, addressing modes,
registers, etc.

2. It has Load Store architecture.

a. Supports Register-Register access only
b. ARM doesn’t support Register –Memory Access
ADD A,R0
ADD A,20H

3. More no. of registers are present to support load and store process of execution.

4. ARM 7 supports 3-stage pipe lining process.

Fetch  Decode  Execute
appears to be single cycle execution

5. It is with hard wired architecture.

So, there is no much internal switching operations.
hence power consumption is LOW.

6. It has barrel shifter. 13

 Pipeline Organization
• Increases speed
• Most instructions will be executed in single cycle

• Versions:
– 3-stage (ARM7TDMI and earlier)
– 5-stage (ARM8, ARM9)
– 6-stage (ARM10)
i Fetch Decode Execute
– 8-stage (ARM11-V6)
– 9-stage (ARM11-V6T2) i+1 Fetch Decode Execute

i+2 Fetch Decode Execute

cycle

t t+1 t+2 t+3 t+4

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 ARM ‐ Operating Modes

The ARM7TDMI processor has seven modes of operations:

1. User mode(usr)
o Normal program execution mode
2. Fast Interrupt mode(fiq)
o Supports a high-speed data transfer or channel process.
3. Interrupt mode(irq)
o Used for general-purpose interrupt handling.
4. Supervisor mode(svc)
o Protected mode for the operating system.
5. Abort mode(abt)
o implements virtual memory and/or memory protection
6. Undefined mode(und)
o supports a software emulation of hardware coprocessors
7. System mode(sys)
o A privileged user mode for the operating system. (runs OS tasks)

• Except user mode, all are known as privileged mode.

• User mode is low privileged mode and system mode is the high privileged mode.
• Each mode has access to its own stack space and a different subset of registers. 15
 ARM ‐ Operating Modes

CPSR[4 :0 ] Mo de Us e Reg i s ters

10 10000 User Normal user code user
11 10001 FIQ Processing fast interrupts _fiq
12 10010 IRQ Processing standard interrupts _irq
13 10011 SVC Processing software interrupts (SWIs) _svc
17 10111 Abort Processing memory faults _abt
1B 11011 Undef Handling undefined instruction traps _und
1F 11111 System Running privileged operating system tasks user

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ARM Register Set

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• Current Visible Registers : 17

• Banked out Registers

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 ARM Registers/Programmer Model
 ARM has 37 registers all of which are 32-bits long.

 1 dedicated program counter (PC)

 1 dedicated current program status register (CPSR)
 5 dedicated saved program status registers (SPSR)
 30 general purpose registers

 The current processor mode governs which of several banks is accessible. Each mode
can access
 a particular set of r0-r12 registers
 a particular r13 (stack pointer, sp) and r14 (link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr

• Privileged modes (except System) can also access

 a particular spsr (saved program status register)

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 CPSR Format: (Current Program Status Register)

Conditional I – irq mode Mode bits

Modes
I=1, Disable irq
N ‐ Negative 10000 User Mode (usr)
Z ‐ Zero F‐ fiq mode 10001 Fast Int Mode (fiq)

C ‐ Carry F=1, Disable fiq 10010 Normal Int Mode (irq)

V ‐ Overflow 10011 Software Int Mode (svc)

T‐Thumb
Q- Sticky overflow 10111 Abort Mode (abt)
T=1, Thumb Inst. State
T=0, ARM Inst. State 11011 Undefined Inst Mode (und)
11111 System Mode (sys)

J=1, Jazelle state

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 Saved Program Status Register (SPSR)

• Each privileged mode (except system mode) has associated with it a SPSR
• This SPSR is used to save the state of CPSR when the privileged mode is
entered
• User state can be fully restored when the user process is resumed
• Often the SPSR may be untouched from the time the privileged mode is
entered to the time it is used to restore the CPSR
• If the privileged supervisor calls to itself the SPSR must be copied into a
general register and saved

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 The ARM Register Set & Mode switching

Current Visible
Registers
User
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 Abort FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13 (sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r13(sp) r14 (lr) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
FIQ
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 User Abort FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13(sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r14(lr) r13(sp) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
User
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 Abort FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13 (sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r13(sp) r14 (lr) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
IRQ
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 User Abort FIQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13(sp) r13 (sp) r13(sp) r13(sp)
r14 (lr) r14(lr) r13(sp) r14 (lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
User
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 Abort FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13 (sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r13(sp) r14 (lr) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
SVC
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 User Abort FIQ IRQ Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13(sp) r13(sp) r13 (sp) r13(sp) r13(sp)
r14 (lr) r14(lr) r13(sp) r14 (lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
User
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 Abort FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13 (sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r13(sp) r14 (lr) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
Abort
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 User FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13 (sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r14(lr) r14 (lr) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
User
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 Abort FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13 (sp) r13(sp) r13(sp) r13(sp)
r14 (lr) r13(sp) r14 (lr) r14(lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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 The ARM Register Set
Current Visible
Registers
Undef
Mode r0.
r1
Banked out
r2
r3 Registers
r4
r5
r6 User Abort FIQ IRQ SVC
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12 r13(SP)
r13 (sp) r13(sp) r13(sp) r13 (sp) r13(sp) r13(sp)
r14 (lr) r14(lr) r13(sp) r14 (lr) r14(lr) r14(lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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ARM - Interrupts

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 Interrupts and Interrupt Vector:
• ARM supports 3 types of Interrupts.
1. Exceptions :
2. Software Interrupts (SWI):
3. Hardware Interrupts : will be activated by FIQ & IRQ

Exceptions :
• ARM has a no. of exception modes.

• These are the internally generated interrupts due to errors in program

or due to the occurrence of some specific conditions.
e.g., (divided by zero error)

• When an undefined instruction is detected, the processor can’t process it.

• The solution for such an undesired situation is to make the processor switch to
another mode and generate an interrupt.

• The interrupts take the control, to an interrupt service routine (ISR) residing in a
specific location in memory.

• ‘Interrupt Vector : It is the starting addresses of the ISR

 Interrupt Vector Table…

Since multiple exceptions can arise at the same time it is necessary to define a
priority order to determine the order in which the exceptions are handled.
1. Reset (highest priority),
2. Data abort,
3. FIQ,
4. IRQ,
5. Prefetch abort,
6. SWI, Undefined inst. (lowest priority).
 Interrupt handling Mechanism in ARM

Exception Entry:
When an exception arises, ARM completes the current instruction and
then to handle the exception.

The processor performs the following sequence of actions:

 It changes the operating mode to the corresponding exception.
 It saves the address of the PC (r15) into LR (r14) of the new mode.
 It saves the old value of the CPSR into the SPSR of the new mode.
 It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fast
interrupt, disables by setting bit 6 of the CPSR.

Exception Return:
Once the exception has been handled the user task is normally resumed.
 Any modified user registers must be restored from the handler's stack.
 The CPSR must be restored from the appropriate SPSR.
 The PC must be changed back to the relevant instruction address. (R14 R15)
Programming the ARM

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 Programming the ARM Processor (ALP vs C)
Writing, running and testing programs is the key to understand any processor.

• ARM can be programmed by either ALP or High Level Language (C)

ALP : Faster execution

C : Simpler Programming

• Instruction Set Architecture (ISA) of ARM, can be understood better by

programming using ALP.

• In ALP, we can understand about how registers, memory and flags act on data.
We get a total feel about the processing activity done inside the processor.

• There are many IDEs available for ARM.

IDE (Integrated Development Environment):
The software development tool that has Editor, Linker, Locator, Loader and
debugger on a single platform.
e.g. Keil IDE : RVDK (Real View Development Kit) & Arduino IDE

• In the embedded design world, high level languages are used in product design,
and C is a very popular language. 37
ARM Assembly Language

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ARM Assembly Language

• ARM Instruction set Features (4)

• Data Types (3)
• Data Alignment
• Assembly Language Rules

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ARM Instruction set Features: (4)

In ARM, more than one operation to be done in a single instruction.

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 ARM Instruction set Features: (4)
i) ARM is a RISC processor, in which every instruction has a maximum size of 32 bits.
Instructions are expected to be executed in one cycle.
This is true for most instructions, but not for all.
∴ ARM is a RISC processor with a few CISC type instructions as well.

ii) ARM is with load– store architecture.

i.e., all computations are register based,
i.e., the operands are to be brought to registers from memory, using a load instruction.
After computation, the result is to be stored in memory.
i.e., there is no data processing instructions in which one of the operands is in memory.
All operands are to be available in registers before computation can be done.

iii) ARM ALU has a barrel shifter associated with one of its operands.
A barrel shifter can perform more than one bit of shift/rotation, on an operand.
The barrel shifter allows shifting and an arithmetic operation to be combined in the
same instruction.

iv) ‘Conditions’ can be appended to instructions: to ‘do or not do’ a particular operation
based on a status of a condition flag.
For most other processors, only branching operations depend on flag status.
Here we will see that data movement and data processing instructions can be made
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‘conditional’.
 Data Types
ARM can operate on three different types of operands.
Word : 32-bit data
Half word : 16-bit data
Byte : 8-bit data

ARM stores the data either as ‘little endian’, or ‘big endian’.

Little Endian format: The lowest byte of the word is stored in the lowest address.
Big Endian format: The highest byte of the word is stored in the lowest address.

Consider the 32-bit data word : 0E 47 90 A3

Little Endian Big Endian

Address Data Address Data
0x00001200 0E Intel prefers little endian format,
0x00001200 A3
Motorola uses big endian format.
0x00001201 90 0x00001201 47 ARM allows both formats
0x00001202 47 0x00001202 90 (can be fixed up by software, in the
initialization stage)
0x00001203 0E 0x00001203 A3
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 Data Alignment
• Here memory is organized, as four banks.

• If the data is Aligned, Storing (and loading also) of 4 bytes in memory can be done
in one cycle, bcz the processor has a 32-bit data bus.

• When 32-bit data is stored in memory, four addresses are needed.

But we need to specify only one address in our instruction.
When this address is used to store 32-bit data, this address and the next three
addresses are automatically accessed.

• For 32-bit data, ‘alignment ’ implies that the last two bits of this address are zero.
• For example, the address 0x00001200 is an aligned address.
• For 16-bit data, ‘alignment ’ implies that the last bit of this address is zero.
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 Assembly Language Rules
 An assembly language line has four fields, namely,
label, op-code, operand and comment.

 A label is positioned at the left of a line

It is the symbol for the memory address which stores that line of information.

 The opcode or instruction field.

 The third is the operand field, and

 The comment field which starts with a semicolon.

• The use of comments is advised for making programs more readable.

e.g.,

CRBhargav ADD R1, R2, R3

Label : Bhargav
Opcode : ADD
Operands : R1, R2 and R3
Comment : the line after the semicolon is the comment.
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 Conditional Execution

 ARM Instructions are executed iff a specified condition is true.

 Not only the branch instructions alone but also any data processing
instruction can be used in this way.

 In general, all arithmetic and logic instructions are expected to affect

conditional flags. But for ARM, we must suffix the instruction by S for
this to happen. Otherwise the flags are unaffected.

 Suffix the mnemonic with “ S” on a data processing instruction that

causes the flags in the CPSR to be updated.

 General Instruction Format

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 Conditional Execution
All ARM7TDMI instructions can be executed conditionally, based
on a 4-bit condition field in the instruction.
 Prior to execution, processor tests the state of the condition flags
in the CPSR (N, Z, V, C), and
o If the condition flag state matches the condition, the instruction executes
normally.
o If the condition flag state does not match the condition, the instruction is
executed as a NOP (no operation).
 List of Conditions, Codes and Corresponding Flag Status
Cond Mnemonic Meaning Condition Flag State

0000 EQ Equal Z=1

0001 NE Not Equal Z=0
0010 CS/HS Carry set/unsigned > = C=1
0011 CC/LO Carry clear/unsigned < C=0
0100 MI Minus/Negative N=1
0101 PL Plus/Positive or Zero N=0
0110 VS Overflow O= 1
0111 VC No overflow O= 0
1000 HI Unsigned higher C=1&Z =0
1001 LS Unsigned lower or same C=0|Z=1
1010 GE Signed > = N==V
1011 LT Signed < N! = V
1100 GT Signed > Z = = 0, N = = V
1101 LE Signed < = Z = = 1 or N! = V
1110 AL Always
1111 (NV ) Unpredictable

Conditions used for signed numbers and unsigned numbers are different.
The mnemonic ‘higher’ or ‘lower’ : for unsigned numbers
‘greater than’ or ‘lower than’ : for signed numbers.
47
 ARM Instruction Set
S.No. Data Shift & Athemati Logical Compare
Transfer Rotate c
1 MOV LSL ADD AND CMP
2 MVN LSR ADC ORR CMN
3 ASR SUB EOR TST
4 ROR SBC BIC TEQ
5 RRX RSB
6 RSC

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 ARM Instruction Set
The instruction set can be broadly classified as follows:

i) Data processing instructions

ii) Load store instructions—single register, multiple register
iii) Branch instructions
iv) Status register access instructions

 Note: ARM is a load / store architecture

o These instructions only work on registers, NOT on memory.

Syntax : opcode {s} {cond} Rd, Rn, operand2

 They each perform a specific operation on one or two operands.
o First operand is always a register - Rn
o Second operand is sent to the ALU via barrel shifter. 57
 i) Data processing instructions

MOV and MVN MOV destination, source

MVN destination, source

The ‘MOV ’ instruction is a ‘register to register’ data movement instruction .

MVN stands for move negated
• It moves the complemented value of the source to the destination.

• The ARM data processing instructions are used to move the data b/w
registers. i.e., to modify data values in registers.
• The general purpose registers R1 to R12 can be used.
• The MOV instruction is also used for copying immediate data into registers.

58
Examples
MOV R11, R2 ; copy the contents of R2 to R11
MOV R12, R10 ; copy the contents of R10 to R12
MVN R1, R9 ; move the complemented value of R9 to R0
; if R9 = 0xFFF00000, R1 = 0x000FFFFFF

; each 1-bit in R1 clears the corresponding bit in R9

• MOV r0 , r1 ; r0 = r1
• MVN r0 , r1 ; r0 = not r1
• Each 1-bit in r1 clears the corresponding bit in r0.

o MOVS R2,#10
o MVNEQ R1,#0 59
 Barrel Shifter
Shift and Rotate instructions

60
Examples
LSL R2, #4 ; shift left logically, the content of R2 by 4 bit positions
ASR R5, #8 ; shift right arithmetically, the content of R2 by 4 bit positions
ROR R1, R2 ; rotate the content of R1, by the number specified in R2

PRE R5 = 5, R7 = 8

MOV R7, R5, LSL #2

HERE R7 = R5*4 = (R5 << 2)

POST R5 = 5, R7 = 20

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 Example: The content of some of the registers are given as:
R1 = 0xEF00DE12, R2 = 0x0456123F, R5 = 4, R6 = 28.
Find the result (in the destination register), when the following instructions are executed.
i) LSL R1, #8 ii) ASR R1, R5 iii) ROR R2, R6 iv) LSR R2, #5

i. LSL R1, #8 Pre: R1 = 0xEF00DE12

Post: R1 = 0x00DE1200

ii. ASR R1, R5 Pre: R1= 0xEF00DE12

Post: R1= 0xFEF00DE1

iii. ROR R2, R6 Pre: R2= 0x0456123F

Post: R2= 0x456123F0

iv. LSR R2, #5 Pre: R2= 0x0456123F

Post: R2= 0x0022B091

ii) R5 contains 4. Arithmetically right shifting R1 4 times, causes the MSB (1, for the given number) to
be replicated 4 times on the left, thus causing a sign extension of the shifted number. R1 now contains
0xFEF00DE1.

iii) R6 contains 28. Rotating R2 28 times to the right is equivalent to rotating it 32–28 = 4 times, to the
left. After rotation, R6 contains 0x456123F0.

iii) R2 is logically shifted right 5 times, and so 5 zeros enter through the left. R2 now has the value
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0x0022B091.
 Combining the Operations of Move and Shift

• This allows shifting and data processing to be done in the same instruction cycle.

1. MOV R1, R2, LSL #2 ; R1 = R2 << 2

2. MOV R1, R2, LSR R3 ; R1 = R2 >> R3

The Destination register : R1

The source operand : R2

1. The content of source operand (R2) is logically shifted twice and then moved to the
destination register R1.

2. The amount of ‘shifting’ is specified in register R3. After the shifting is done, the
result is moved to R1.

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Example :
Find the content of the destination registers after the execution of each of the given
instructions, given that the content of R5 = 0x72340200 and R2 = 4
i) MOV R3, R5, LSL #3 ii) MOV R6, R5, ASR R2

Solution

i) MOV R3, R5, LSL #3

0 1 1 1 0 0 1 0 0 0 11 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 10 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
9 1A0 1 0 0 0

The content of R5 is shifted left 3 times, and moved to R3. Now, R3 = 0x91A01000

ii) MOV R6, R5, ASR R2

R2 = 4, and so R5 is arithmetically shifted right 4 times. Since the MSB of the

number in R5 is 0, when right shifting, this bit is replicated 4 times at the left of the
number. After execution, R6 = 0x07234020
64
 Arithmetic Instructions
 The arithmetic instructions implement addition and subtraction of
32-bit signed and unsigned values.
 N is the result of the shifter operation.

65
Examples:

Instruction Operation Calculation

ADD R3, R4, R5 Add R3 = R4 + R5
ADC R3, R4, R5 Add with carry R3 = R4 + R5 + C
SUB R3, R4, R5 Subtract R3 = R4 – R5
SBC R3, R4, R5 Subtract with carry R3 = R4 – R5 – C
RSB R3, R4, R5 Reverse subtract R3 = R5 – R4
RSC R3, R4, R5 Reverse subtract with carry R3 = R5 – R4 – C

SUBS R1, R2, R3 ; the suffix ‘S’ has been used

MOVEQ R2, R1 ; the EQ notation tests the Z = 1 condition

Here the move instruction is executed only if the result of the subtraction produces a
zero and sets the zero flag.

66
Find the result of the following instructions. What do these instructions accomplish?

i) ADD R1, R2, R2, LSL #3 ii) RSB R3, R3, R3, LSL #3 iii) RSB R3, R2, R2, LSL #4
iv) SUB R0, R0, R0, LSL #2 v) RSB R2, R1, #0

Solution

i) ADD R1, R2, R2, LSL #3

One source operand is R2, LSL #3. Left shifting 3 times accomplishes multiplication by 23 = 8
Th e result of the whole operation is R1 = R2 + 8R2 = 9R2

ii) RSB R3, R3, R3, LSL #3

R3 = 8R3 – R3 = 7 R3

iii) RSB R3, R2, R2, LSL #4

R3 = 16R2 – R2 = 15R2
iv) SUB R0, R0, R0 LSL #2
R0 = R0 – 4R0 = -3R0
v) RSB R2, R1, #0
We get R2 = 0 – R1 = -R1. i.e., we get the negative value of R1
67
Example 1: SUB R0,R1,R2
 Given instruction subtracts a value stored in register R2 from a
value stored in register R1. The result is stored in register R0. R0
= R1-R2
 PRE: R0 = 0x00000000, R1 = 0x22223333, R2 = 0x11111111
POST: R0 = 0x11112222, R1 = 0x22223333, R2 = 0x11111111

Example 2: RSB R0, R1, #0

 This reverse subtract instruction (RSB) subtracts R1 from the
constant value #0, writing the result to R0. You can use this
instruction to negate numbers. R0 = 0x0 - R1
 PRE: R0 = 0x00000000, R1 = 0x00000077,
 POST: R0 = -R1 = 0xFFFFFF89
68
 Logical Instructions
Instruction Operation Logical Result

AND R3, R4, R5 Logical AND of 32 bit values R3 = R4 AND R5

ORR R3, R4, R5 Logical OR of 32 bit values R3 = R4 OR R5

EOR R3, R4, R5 Logical XOR of 32 bit values R3 = R4 XOR R5

BIC R3, R4, R5 Logical bit clear R3 = R4 (AND) NOT R5

Example: Given the contents of R3 and R4 as, R3 = 0x0FF00FF0, R4 = 0x0FF00FF0. and R0 = 0.

Find the values in R1, R2 and R5 at the end of the sequence of instructions shown.
i) EORS R1, R3, R4 ii) ANDS R5, R3,
Solution
The content of the destination register and the affected flag is shown alongside the
executed instruction
i) EORS R1, R3, R4 ; R1 = 0x00000000, Z=1
ii) ANDS R5, R3, R0 ; R5 = 0x00000000 Z=1

69
Example 1: ORR R0,R1,R2
 This example shows a logical OR operation between registers R1
and R2. R0 holds the result.
PRE: R0 = 0x00000000, R1 = 0x02040608, R2 = 0x10305070
POST: R0 = 0x12345678

Example 2: EORS R0, R1, R2

 This example shows a logical Ex-OR operation between registers
R1 and R2. R0 holds the result.
PRE: R0 = 0x00000000, R1 = 0x55557777, R2 = 0xFFFF0000
POST: R0 = 0xAAAA7777

70
 Compare Instructions

CMP R3, R4 Compare R3 – R4, but only flags affected

CMN R3, R4 Compare negated R3 + R4, but only flags affected

TST R3, R4 Test R3 AND R4 but only flags affected

TEQ R3, R4 Test Equivalence R3 OR R4 but only flags affected

Flags SET after compare instructions

If C Z
R3 > R4 1 0
R3 < R4 0 0
R3 = R4 1 1

71
Multiplication
MUL Rd, Rm, Rs

MUL R1, R2, R3 ; R1 = R2 × R3

MULS R1, R2, R3 ; R1 = R2 × R3 and fl ags are also set
MULSEQ R3, R2, R1 ;R1 = R2 × R3 is done only if the Z = 1
;(because of the EQ suffix)
;because of the S suffix, flags are updated
MULEQ R4, R3, R5 ;if Z = 1, R4 = R3 × R5

Multiply and Accumulate

MLA Rd, Rm, Rs, Rn ;Rd = (Rm * Rs) + Rn

This instruction does multiplication and accumulation (addition)

72
73
66
 • What do the following instructions mean and what is accomplished?

MOVAL R7, R5
List of Conditions, Codes and Corresponding Flag Status
MOVGT R2, R5 Mnemonic Meaning Condition Flag State
ADDHI R2, R4, R2
EQ Equal Z=1
ADDLT R5, R6, R7 NE Not Equal Z=0
CS/HS Carry set/unsigned > = C=1
SUBNE R1, R2, R7 CC/LO Carry clear/unsigned < C=0
CMP R1, R2 MI Minus/Negative N=1
PL Plus/Positive or Zero N=0
ANDEQ R1, R2, R4 VS Overflow O= 1
VC No overflow O= 0
TEST R1, R3 HI Unsigned higher C=1&Z =0
LS Unsigned lower or same C=0|Z=1
GE Signed > = N==V
LT Signed < N! = V
GT Signed > Z = = 0, N = = V
LE Signed < = Z = = 1 or N! = V
AL Always
(NV ) Unpredictable
68
End of Unit 3

Thank You

74
16CS402 – Embedded Systems- UNIT 3 COMPANY
LOGO

ARM Embedded Processor

UNIT –IV

Mr. M. Krishna Chennakesava Rao, M.E., (Ph.D.)

Assistant Professor - ECE, VFSTR, Guntur,Company
AP. LOGO

70
 UNIT - IV
COMPANY
LOGO

ARM Embedded Processor

Load and Store Instructions : Single, Multiple Register, Swap

Branch Instructions

Read only and Read/Write

Assembly Programming

General structure of Assembly Program

Mr. M. Krishna Chennakesava Rao, Assistant Professor-ECE, VFSTR, Guntur

71
 ARM Instruction Set
The instruction set can be broadly classified as follows:

i) Data processing instructions

ii) Load store instructions—single register, multiple register
iii) Branch instructions
iv) Status register access instructions

 Note: ARM is a load / store architecture

o These instructions only work on registers, NOT on memory.

Syntax : opcode {s} {cond} Rd, Rn, operand2

 They each perform a specific operation on one or two operands.
o First operand is always a register - Rn
o Second operand is sent to the ALU via barrel shifter. 72
Load-store architecture:
• Load and store instructions, transfer the data between Register
banks and External memory.
• Memory accesses are costly, so separating memory accesses from
data processing provides an advantage because you can use data
items held in the register bank multiple times without needing
multiple memory accesses.
• In contrast, with a CISC design the data processing operations can
act on memory directly.

73
 Load and Store Instructions

Memory
Load
Rn

Rm
Store

• Loading is the process of getting data from memory into a register.

• Storing is process of sending data from a register to memory .
• 3 types of Load and store instructions.
• Single Register Load- Store
• Multiple Register Load- Store
• Swap
74
 Single-Register Transfer
 These instructions are used for moving a single data item in and out
of a register.
 The datatypes supported are
 signed and unsigned words (32-bit), halfwords (16-bit), and bytes.
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRSH Load Signed Half Word
LDRB Load Byte STRB Store Byte
LDRSB Load Signed Byte

75
76
 Syntax for load or store

LDR/STR {<cond>} <Rd>, <addressing mode>

• Rd is the source register for store and destination register for load.
• The addressing mode gives the information to get the ‘effective address’, which
is the actual memory address to be accessed.

• The addressing mode is indirect because the memory address is not to

be specified directly in the instruction, rather a base register is mandatorily
used.
• [addressing mode]  [ Base + offset]

LDR R1, [R2] ;copy into R1 the content of memory specified in R2

LDR R1, [R2, #4] ;copy into R1 the content of memory specified in [R2+4]

STR R1, [R2] ;store the content of R1 into the memory address
specified in R2
77
 Example:

How is the effective memory address calculated in the following load and store instructions?
i) LDR R3, [R2, LSL #2] ii) STR R9, [R1, R2, ROR #2]
iii) LDR R4, [R3, R2] iv) STR R5, [R4, R3, ASL #4]

Solution:

i) LDR R3, [R2, LSL #2]

• Effective address is the content of [ R2<<2] or [4R2]

ii) STR R9, [R1, R2, ROR #2]

• Effective address is specified by R1, R2 and a right rotation.
• To calculate EA, the content of R2 is rotated twice by 2, and then added to the
content of R1.

iii) LDR R4, [R3, R2]

• The Effective address is the sum of R3 and R2.

iv) STR R5, [R4, R3, ASR #4]

• The effective address is the sum of the content of R4 and the arithmetically right
shifted (by 4) content of R3.
78
 Example: Two memory areas are being referenced and two registers are used as pointers:
R1 = 0x00000100 and R2 = 0x40001200
Table shows the data addresses and corresponding data.
Show the content of memory, after the execution of the following instructions:
i) LDR R3, [R1] ii) LDRB R3, [R1] iii) LDRH R3, [R1] Address Byte Stored
iv) STRB R3, [R2] given that R3 = 0xAE0D2356 0 x00000100 56
0 x00000101 23
Solution : Assume Little Endian process. 0 x00000102 0D
0 x00000103 AE
i) LDR R3,[R1]
The complete 32-bit data in the address pointed to by R1 is copied to R3.
R3 = 0xAE0D2356
ii) LDRB R3,[R1]
The byte (LSB) of the word alone is copied to R3.
Since it is an unsigned byte, the remaining bytes of R3 contain 0.
So R3 = 0x00000056
iii) LDRH R3,[R1] STRB R3, [R2]
0 x40001200 56
The half word (lower two bytes) of the address is copied to R3. 00
R3 = 0x00002356 00
00
iv) STRB R3,[R2] given that R3 = 0xAE0D2356
The byte corresponding to the LSB of the data in R3 is copied to the address pointed by R2.
79
 Loading Signed Numbers

LDR R1, [R7] R1 = 0xCDEF8204

LDRSH R2, [R7] R2 = 0xFFFF8204

LDRSB R3, [R7] R3 = 0x00000004

80
 Types of Indexed Addressing Modes
1. Pre-index Addressing Mode :
• Effective address is calculation is done before the execution of load/store.
• Effective address is not stored in base register .
• LDR r1, [r2, #4]

2. Auto index or Pre index with write back (!)Addressing Mode

• Effective address is calculated before load/store execution.
• Effective address is stored back in base register .
• LDR r1, [r2, #4]!
3. Post Index Addressing Mode
• Effective address calculation is done after the execution of the specific
instruction has been done.

• LDR r1, [r2], #4

81
Pre or Post Indexed Addressing …(Cont’d)

82
Pre-indexed Addressing Mode

LDR R0, [R7, #4].

• Here R7 is the base register and the effective address is R7 + 4.
• The data at this effective address is copied to R7.

STR R1, [R5, R6, LSL #2]

The effective address = R5 +R6 left shifted twice.

Note: After the load/store is done, the base address content remains unchanged,
the effective address is not copied to the base register.

! : Write back
Effective address is copied to the base register,

LDR R2, [R6, #-8] !.

In this, after the loading operation is done, R6 has the effective address written back
into it.

83
 Assume Little Endian process
R1= 0x0000 0000 ; R2= 0x0000 9000. Find the content of registers of the execution.

Address Data
1. LDR R1, [R2] 2. LDR R1, [R2]! 0x00009007 04
0x00009006 03
EA= 0x 0000 9000 EA= 0x 0000 9000
0x00009005 02
R1= 0x 5040 3020 R1=0x 5040 3020
0x00009004 01
R2= 0x 0000 9000 R2= EA= 0x 0000 9000
0x00009003 50
0x00009002 40
3. LDR R1, [R2,#4] 4. LDR R1, [R2,#4]! 0x00009001 30
0x00009000 20
EA= 0x 0000 9004 EA= 0x 0000 9004
R1=0x 0403 0201 R1=0x 0403 0201 5. LDR R1, [R2],#4
R2=0x 0000 9000 R2= EA= 0x 0000 9004 R1=0x 5040 3020
EA= 0x 0000 9004
R2= EA= 0x 0000 9004
84
Assume r0=0x00000000, r1=0x00009000, [0x00009000]=0x03030303,
[0x00009004]=0x 0x05050505. Find the register and memory contents after the
following instructions execution.
STR r0, [r1, #4]
STR r0, [r1, #4]!
STR r0, [r1], #4
STR r0, [r1]

i) STR r0, [r1, #4] ii) STR r0, [r1, #4]! iii) STR r0, [r1], #4
EA= 0x 0000 9004 EA= 0x 0000 9004
R0  [EA] R0  [EA] R0  [R1]
[EA] = 0x 0000 0000 [EA] = 0x 0000 0000 R0  [0x0000 9000]
R0= 0x 0000 0000 R0= 0x 0000 0000 [0x0000 9000] = 0000 000
R1= 0x 0000 9000 R1= 0x 0000 9004
[EA] = 0x 0000 0004
R0= 0x 0000 0000
iv) STR r0, [r1] R1= 0x 0000 9004
EA= 0x 0000 9000
R0  [EA]
[0x0000 0000] = 0x 0000 0000
R0= 0x 0000 0000
R1= 0x 0000 9000 85
Assume r0=0x00000000, r1=0x00009000, [0x00009000]=0x03030303,
[0x00009004]=0x 0x05050505. Find the register and memory contents after the
following instructions execution. i) STR r0, [r1, #4] ii) STR r0, [r1, #4]!
STR r0, [r1, #4] EA= 0x 0000 9004 EA= 0x 0000 9004
STR r0, [r1, #4]! R0  [EA] R0  [EA]
STR r0, [r1], #4 R0= 0x 0000 0000 R0= 0x 0000 0000
STR r0, [r1] R1= 0x 0000 9000 R1= 0x 0000 9004

Memory Pre- 1- 2-Post 3-Post 4-Post

iii) STR r0, [r1], #4
Address Data Post Data Data Data
R0  [R1]
Data
R0  [0x0000 9000]
R0= 0x 0000 0000
0x0000 9000 03 03 03 00 00 [EA] = 0x 0000 0004
0x0000 9001 03 03 03 00 00 R1= 0x 0000 9004
0x0000 9002 03 03 03 00 00
iv) STR r0, [r1]
0x0000 9003 03 03 03 00 00 EA= 0x 0000 9000
0x0000 9004 05 00 00 05 05 R0  [EA]
[0x0000 0000] = 0x 00000000
0x0000 9005 05 00 00 05 05 R0= 0x 0000 0000
0x0000 9006 05 00 00 05 05 R1= 0x 0000 9000

0x0000 9007 05 00 00 05 05
86
Assume r1=0x00000000, r2=0x00009000, [0x00009000]=0x03030303,
[0x00009004]=0x05050505. Find the register contents of r1 and r2 after the following
instructions execution.
LDR r1, [r2, #4]
LDR r1, [r2, #4]!
LDR r1, [r2], #4
LDR r1, [r2]

87
 LDM / STM Instructions:
• LoaD Multiple Registers / STore Multiple Registers
• Allow the data transfer between ARM registers (1 and 16 registers) and
memory (to or from).
• Multiple Registers are involved.
• It is equivalent to multiple LDR/ STR
• LDM/STM instructions can be used only for words (32 bits).

Syntax: LDM Rn!, { Reg. List} ; Rn  Base Address

STM Rn!, { Reg. List}

<LDM|STM>{<cond>}<addr_mode> Rb{!}, <reg list>

LDM R5!, {R1,R2,R3} STM R5!, {R1,R2,R3}
LDM R5!, {R1-R3} STM R5!, {R1-R3}
LDM R5!, {R1-R3, R5, R7-R8} STM R5!, {R1-R3, R5, R7-R8}
LDM R5!, {R6, R4, R0-R2} STM R5!, {R6, R4, R0-R2}
88
 Syntax:

<LDM|STM>{<cond>}<addr_mode> Rb{!}, <reg list>

LDM R5!, {R9, R4, R0-R2}

• Here the base address is in R5, and after each data transfer, it is incremented by 4.
• In the destination register list, though R9 is specified first, the lowest register will
always be loaded from the lowest address in memory, and the highest register
from the highest address.
• Here R0 gets the data in the address pointed by R5.

89
4 addressing modes:

 LDMIA / STMIA increment after

 LDMIB / STMIB increment before
 LDMDA / STMDA decrement after
 LDMDB / STMDB decrement before

90
 Swap Instructions:
Swap Memory and Register Instructions (SWP)
Swap instructions combine a load and a store of a word or an
unsigned byte in a single instruction.
Syntax: SWP {Cond} {B} Rd, Rm, [Rn]

Binary Encoding:

Binary Encoding:
Swap Instruction…… (Cont’d) Example
 Branch Instructions

• Change the sequence of execution

• may be conditional or conditional
• List of Branch Instructions
B Branch
BL Branch and link
BX Branch and Exchange
BLX Branch Exchange with link
• Branch (B) instruction is similar to Jump instruction (no need to return)
• Branch with Link (BL) instruction is similar to CALL instruction
(need to return)
• Branch and Exchange (BX) : for switching the processor between
ARM instructions Thumb instructions
93
 Branch Instruction B
• Branch (B) instruction is similar to Jump instruction (no need to return)

• Branching implies transferring control to a new memory location

which is expressed as a ‘label’.

• Format of any branch instruction : B label

• Unconditional B
• Conditional B

Branching is made conditional by appending the mnemonic B with the

necessary condition.
e.g., :
1. BEQ 2. BNE 3. BHI 4. BGT

B NEW ;transfers control unconditionally to location NEW

STOP B STOP ;continually branches to its own label STOP
BNE NOO ;branch to NOO if Z flag is not set
BHI LUX ;branch if high, i.e., if C = 1 94
 Format of a branch instruction

Example 1
 Shows a forward and backward branch.
 The forward branch skips three instructions.
 The backward branch creates an infinite loop.

95
 Branch with Link Instruction BL
• Branch with Link (BL) instruction is similar to CALL instruction
(need to return)
 This example shows a simple part of code that branches to a subroutine using
the BL instruction.
 To return from a subroutine, move the link register to the pc.

96
General Structure of an Assembly Language Line
i) Label Space: Extreme left of the line

ii) Use White Space:

• Instructions & directives must be preceded by a white space,
such as a space or a tab, even if there is no label.
This means that they should not be written in the label space .

iii) Instruction mnemonics and register names can be written in either

uppercase or lowercase, but not mixed.

iii) Labels are the symbols that represent addresses.

The address given by a label is calculated during assembly.

iv) Directives:
AREA ENTRY END
DCB DCW DCD
EQU
RN
Constants 97
 ARM- Starting Assembly Language Programming

The output of compilation process has atleast two memory areas.

i) A code area. This is usually a read-only area. (non volatile / ROM)
ii) A data area. This is usually a read-write area. (volatile / RAM)

1. AREA Directive
• In ARM ALP, initially we define an area, using the directive named ‘AREA’.
• This directive names the area and sets its attributes.
• The attributes are placed after the name, separated by commas.
Example
AREA SORT, CODE, READ ONLY * (*optional)
AREA TABLE, DATA
2. ENTRY Directive
• It marks the first instruction to be executed within a program.
3. END Directive
• It is the END of ALP module.
• It tells the assembler to stop reading.
• Anything written after the END directive will be ignored by the assembler. 98
 Directives for defining Data:

• Define and describe different kinds of data.

• Data which is used in a program can be bytes or half words or words.
• DCB defines data byte,
• DCW defines 16 bits or a half word and
• DCD defines a word (32 bits).

• Defining data implies allocating space for data.

• The allocated space corresponds to memory addresses, which are identified by
labels.
Examples

NUMS DCB 9, 82, 71

The first byte 9, has the address NUMS, 82 has the address NUMS + 1, and 71 has the address NUMS + 1.
NUMB DCW 0x6787, 0x4564
The second line has address NUMB for the first half word, and NUMB + 2 for the second half word.
NUMBR DCD 0x00000123, 0x67890900
the addresses of the words are NUMBR and NUMBR + 4.
99
The EQU Directive
• used to equate a numeric constant to a label.
• The constant may be data or address.
• Examples :
FACTR EQU 35
BASE_ADDR EQU 0x40000000

The RN Directive

• Used to give variable names to registers.

X RN 0 ; R0 is named as X
Y RN 1 ; R1 is named as Y

100
Constants Allowed
• Decimal : e.g., 346, 6748, etc.
• Hexadecimal. e.g., 0x12345678, 0xFCE45, etc.
• n_xxx where:
n is a base between 2 and 9 and
xxx is a number in that base
• Characters: enclosed within single quotes, e.g., ‘e’, ‘R’, etc.
• Strings: enclosed within double quotes. e.g., “mine”, “non”, etc.
• Boolean: TRUE or FALSE

101
1. Write a program to find factorial of a given number

AREA FACTO, CODE ;define the code area

ENTRY ;entry point
R2 R1 Result=R2 Count=R1
MOV R1, #04 ;R1 = 04
1 4 4 3

MOV R2, #1 ;R2 = 1 4 3 12 2

12 2 24 1
REPT MUL R2, R1, R2 ;R2 = R1 xR2
24 1 24 0
SUBS R1, R1, #1 ;R1 = R1- 1
BNE REPT ;branch to REPT if Z! = 0
STOP B STOP ;last line

END

102
2. Perform division by repeated subtraction using ARM.
R4 R2 R4 R3 --> Q Reminder
AREA DIV, CODE 7 2 5 1
5 2 3 2
3 2 1 3
ENTRY 1 2 -1 1

MOV R1, #07 ;Move the dividend to R1

MOV R2, #02 ;Move the divisor to R2
MOV R3, #0 ;R3 = 0
MOV R4, R1 ;copy the dividend to R4
REPT SUBS R4, R4, R2 ;subtract and set flags
ADDPL R3, R3, #1 ;add if N = 0 i.e. MSB of R3 is +ve R3Q
BPL REPT ;repeat the loop if the MSB is +ve
ADDMI R4, R4, R2 ;if MSB of R4 is –ve, add R2 to R4
STOP B STOP
END
103
3. Write a program to calculate 3X2 + 5Y2, where X = 8 and Y = 5

AREA PROCED,CODE
ENTRY
MOV R2,#8 ;to calculate 3X2 +5Y2
BL SQUARE ;call the SQUARE procedure
ADD R1,R3,R3,LSL #1 ;3X2
MOV R2,#5 ;R2 = 5
BL SQUARE ;call the SQUARE procedure
ADD R0,R3,R3,LSL #2 ;5Y2
ADD R4,R1,R0 ;R4 = R1+R0 i.e 3X2 +5Y2
STOP B STOP ;last line in the execution
SQUARE MUL R3,R2,R2 ;the SQUARE procedure
MOV PC,LR ;return LR back to PC
END

104
4. Write a program to find the sum of 3X + 4Y + 9Z, where X = 2, Y = 3 and Z = 4
AREA SUMM, CODE ;READONLY
X RN 1 ;register R1 is named X
Y RN 2 ;register R2 is named Y
Z RN 3 ;register R3 is named Z
ENTRY
MOV X,#2 ;load X = 2 into register R1
MOV Y,#3 ;load Y = 3 into register R2
MOV Z,#4 ;load Z = 4 into register R3
ADD R1,R1,R1,LSL#1 ;R1 = 3X
MOV R2,R2,LSL#2 ;R2 = 4Y
ADD R3,R3,R3,LSL#3 ;R3 = 9Z
ADD R1,R1,R2 ;R1 = R1+R2 i.e. 3X+4Y
ADD R1,R1,R3 ;R1 = R1+R3 i.e. 3X+4Y+9Z
STOP B STOP ;continue branching at STOP
END ;end of the assembly fi le 105