Product Order Technical Tools & Support &

Folder Now Documents Software Community

ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

ISO224 Reinforced Isolated Amplifier

With Single-Ended Input of ±12 V and Differential Output of ±4 V
1 Features 3 Description
1• Offered in High-Grade (ISO224B) and Low-Grade The ISO224 is a precision isolated amplifier with an
(ISO224A) Versions output separated from the input circuitry by an
isolation barrier with high immunity to magnetic
• ±12-V Input Voltage Range Optimized for Isolated interference. This barrier is certified to provide
Voltage Measurement in Industrial Applications reinforced galvanic isolation of up to 5 kVRMS with an
• Overvoltage Input Clamp With 9-kV ESD exceptionally long lifetime and low power dissipation.
• ±4-V Differential Output Voltage Range With When used with isolated power supplies, this device
Common-Mode at VDD2 / 2 separates parts of the system that operate on
different common-mode voltage levels and protects
• Low DC-Error Operation (ISO224B): lower-voltage devices from damage.
– Input Offset: ±5 mV at 25°C, ±15 µV/°C max
The input of the ISO224 is optimized for accurate
– Gain Error: ±0.3% at 25°C, ±35 ppm/°C max sensing of ±10-V signals that are widely used in
– Nonlinearity: ±0.01% max, ±0.1 ppm/°C typ industrial applications. The device operates of a
• 4.5-V to 18-V Single-Supply on High-Side single supply on the high-side. This unique feature
simplifies the design of the isolated power supply and
• 4.5-V to 5.5-V Operation on Low-Side reduces the system cost. The integrated high-side
• Safety-Related Certifications: supply voltage detection feature simplifies system
– 7071-VPEAK Reinforced Isolation per DIN VDE level diagnostics. The ±4-V output of the ISO224
V 0884-11: 2017-01 allows lower-cost analog-to-digital converters (ADCs)
to be used. The differential structure of the output
– 5000-VRMS Isolation for 1 Minute per UL1577 supports high immunity to noise.
• High CMTI (ISO224B): 80 kV/µs (typ)
The ISO224 is fully specified over the extended
industrial temperature range of –55°C to +125°C and
2 Applications is available in a wide-body 8-pin SOIC (DWV)
• Isolated Analog Signal Acquisition in: package.
– Grid Automation
Device Information(1)
– Protection Relays
DEVICE NAME PACKAGE BODY SIZE
– Factory Automation and Control ISO224 SOIC (8) 5.85 mm × 7.5 mm
– Rail Transport
(1) For all available packages, see the orderable addendum at
– Motor Drives the end of the datasheet.
– Power Analyzers

Simplified Schematic
ISO224

OUTP
optional
Reinforced Isolation

IN ADS7945
Up to ±12 V Clamp
OUTN 14-Bit ADC
optional
Isolated
VDD1 VDD2 4.5 V to 5.5 V
4.5 V to 18 V
GND1 GND2
GND1 GND2
VCAP

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 17
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 17
3 Description ............................................................. 1 8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 21
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3 9 Application and Implementation ........................ 22
9.1 Application Information............................................ 22
6 Pin Configuration and Functions ......................... 3
9.2 Typical Application .................................................. 22
7 Specifications......................................................... 4
9.3 What to Do and What Not to Do ............................. 24
7.1 Absolute Maximum Ratings ...................................... 4
10 Power Supply Recommendations ..................... 25
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
7.4 Thermal Information .................................................. 5
11.2 Layout Example .................................................... 26
7.5 Power Ratings........................................................... 5
7.6 Insulation Specifications............................................ 6 12 Device and Documentation Support ................. 27
7.7 Safety-Related Certifications..................................... 7 12.1 Documentation Support ........................................ 27
7.8 Safety Limiting Values .............................................. 7 12.2 Receiving Notification of Documentation Updates 27
7.9 Electrical Characteristics........................................... 7 12.3 Community Resources.......................................... 27
7.10 Switching Characteristics ........................................ 9 12.4 Trademarks ........................................................... 27
7.11 Insulation Characteristics Curves ......................... 10 12.5 Electrostatic Discharge Caution ............................ 27
7.12 Typical Characteristics .......................................... 11 12.6 Glossary ................................................................ 27
8 Detailed Description ............................................ 17 13 Mechanical, Packaging, and Orderable
Information ........................................................... 28

4 Revision History
Changes from Original (June 2018) to Revision A Page

• Changed document status from Advance Information to Production Data ........................................................................... 1

2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

5 Device Comparison Table

PARAMETER ISO224B ISO224A

Input offset voltage, VOS ±5 mV (max) ±50 mV (max)
Input offset drift, TCVOS ±15 µV/°C (max) ±60 µV/°C (max)
Input-referred noise 3 µV/√Hz (typ) 4 µV/√Hz (typ)
Gain error, EG ±0.3% (max) ±1% (max)
Gain error drift, TCEG ±35 ppm/°C (max) ±60 ppm/°C (max)
Nonlinearity ±0.01% (max) ±0.02% (max)
Output bandwidth, BW 275 kHz (typ) 185 kHz (typ)
Common-mode transient immunity, CMTI 80 kV/µs (typ) 30 kV/µs (typ)
IN to OUTP, OUTN signal delay (50% – 50%) 2.2 µs (typ) 2.8 µs (typ)

6 Pin Configuration and Functions

DWV Package
8-Pin SOIC
Top View

VCAP 1 8 VDD2

IN 2 7 OUTP

VDD1 3 6 OUTN

GND1 4 5 GND2

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
Supply decoupling capacitor.
1 VCAP —
Connect a 0.22-µF capacitor between this pin and the high-side analog ground.
2 IN I Analog input
High-side power supply, 4.5 V to 18 V.
3 VDD1 —
See the Power Supply Recommendations section for decoupling recommendations.
4 GND1 — High-side analog ground
5 GND2 — Low-side analog ground
6 OUTN O Inverting analog output
7 OUTP O Noninverting analog output
Low-side power supply, 4.5 V to 5.5 V.
8 VDD2 —
See the Power Supply Recommendations section for decoupling recommendations.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

7 Specifications
7.1 Absolute Maximum Ratings
(1)
see
MIN MAX UNIT
VDD1 to GND1 –0.3 26
Power-supply voltage V
VDD2 to GND2 –0.3 6.5
Input voltage IN to GND1 (2) –15 15 V
Input current Continuous, at IN pin (3) –10 10 mA
Output voltage OUTP, OUTN GND2 – 0.3 VDD2 + 0.3 V
Junction, TJ 150
Temperature °C
Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Exposure to absolute-maximum-rated condition for extended periods may increase input leakage current.
(3) Limit the input current at IN pin to prevent permanent damage to the device. The IN pin is internally protected by a voltage clamp. See
Figure 42 for a typical current versus voltage characteristic curve of the input clamp.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), IN pin only ±9000
Electrostatic per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD) All pins except IN ±3000 V
discharge
(2)
Charged-device model (CDM), per JEDEC specification JESD22-C101 ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
High-side power supply VDD1 to GND1 4.5 5 18 V
Low-side power supply VDD2 to GND2 4.5 5 5.5 V
ANALOG INPUT
VClipping Input voltage before clipping output (1) IN to GND1 ±13.8 V
VFSR Specified linear input full-scale voltage (1) IN to GND1 –12 12 V
TEMPERATURE RANGE
TA Specified ambient temperature –55 25 125 °C

(1) See the Analog Input section for more details.

4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

7.4 Thermal Information

ISO224x
(1)
THERMAL METRIC DWV (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 96.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.9 °C/W
RθJB Junction-to-board thermal resistance 60.1 °C/W
ψJT Junction-to-top characterization parameter 16.9 °C/W
ψJB Junction-to-board characterization parameter 58.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Power Ratings (1)

PARAMETER TEST CONDITIONS VALUE UNIT
VDD1 = 18 V, VDD2 = 5.5 V 194.9
PD Maximum power dissipation (both sides) mW
VDD1 = VDD2 = 5.5 V 97.4
VDD1 = 18 V 140.4
PD1 Maximum power dissipation (high-side supply) mW
VDD1 = 5.5 V 42.9
PD2 Maximum power dissipation (low-side supply) VDD2 = 5.5 V 54.5 mW

(1) See the Electrical Characteristics table for maximum supply current specifications.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

7.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance (1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage (1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation ≥ 0.021 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category per Rated mains voltage ≤ 600 VRMS I-IV
IEC 60664-1 Rated mains voltage ≤ 1000 VRMS I-III
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
Maximum repetitive peak
VIORM At AC voltage (bipolar or unipolar) 2121 VPK
isolation voltage
At AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test;
Maximum-rated 1500 VRMS
VIOWM see Figure 4
isolation working voltage
At DC voltage 2121 VDC
Maximum transient VTEST = VIOTM, t = 60 s (qualification test) 7071
VIOTM VPK
isolation voltage VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 8485
Maximum surge Test method per IEC 60065, 1.2/50-µs waveform,
VIOSM 8000 VPK
isolation voltage (3) VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
Method A, after input/output safety test subgroup 2/3,
≤5
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
Method A, after environmental tests subgroup 1,
qpd Apparent charge (4) ≤5 pC
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
Method B1, at routine test (100% production) and preconditioning (type test),
≤5
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
Barrier capacitance,
CIO VIO = 0.5 VPP at 1 MHz ~1 pF
input to output (5)
VIO = 500 V at TA = 25°C > 1012
Insulation resistance,
RIO VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 Ω
input to output (5)
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL1577
VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),
VISO Withstand isolation voltage 5000 VRMS
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.

6 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

7.7 Safety-Related Certifications

VDE UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
Recognized under 1577 component recognition and
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, CSA component acceptance NO 5 programs
and DIN EN 60065 (VDE 0860): 2005-11
Reinforced insulation Single protection
File number: 40040142 File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA = 96.3°C/W, TJ = 150°C, TA = 25°C,
55
Safety input, output, or supply VDD1 = 18 V, VDD2 = 5.5 V, see Figure 2
IS mA
current RθJA = 96.3°C/W, TJ = 150°C, TA = 25°C,
236
VDD1 = VDD2 = 5.5 V, see Figure 2
Safety input, output, or total RθJA = 96.3°C/W, TJ = 150°C, TA = 25°C,
PS 1298 (1) mW
power see Figure 3
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDD1max + IS × VDD2max, where VDD1max is the maximum high-side supply voltage and VDD2max is the maximum low-side
supply voltage.

7.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 4.5 V to 18 V, VDD2 = 4.5 V to 5.5 V, VIN =
–12 V to 12 V, and RLOAD = 10 kΩ; typical specifications are at TA = 25°C, and VDD1 = VDD2 = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Initial, at TA = 25°C, IN = GND1, ISO224B –5 ±1 5
VOS Input offset voltage (1) mV
Initial, at TA = 25°C, IN = GND1, ISO224A –50 ±1 50
ISO224B –15 ±3 15
TCVOS Input offset voltage drift (1) µV/°C
ISO224A –60 ±12 60
CIN Input capacitance IN to GND1 2 pF
RIN Input resistance IN to GND1 1 1.25 MΩ
IIB Input bias current IN = GND1 ±15 nA
TCIIB Input bias current drift IN = GND1 ±30 pA/°C
Input-referred noise ISO224B 3
en µV/√Hz
density ISO224A 4

(1) The typical value includes one sigma statistical variation.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 4.5 V to 18 V, VDD2 = 4.5 V to 5.5 V, VIN =
–12 V to 12 V, and RLOAD = 10 kΩ; typical specifications are at TA = 25°C, and VDD1 = VDD2 = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUTS
Nominal gain (VOUTP – VOUTN) / VIN 1/3 V/V
Initial, at TA = 25°C, ISO224B –0.3% ±0.05% 0.3%
EG Gain error (1)
Initial, at TA = 25°C, ISO224A –1% 0.4% 1%
ISO224B –35 ±10 35
TCEG Gain error drift (1) ppm/°C
ISO224A –60 ±20 60
ISO224B –0.01% ±0.003% 0.01%
Nonlinearity
ISO224A –0.02% ±0.003% 0.02%
Nonlinearity drift ±0.1 ppm/°C
THD Total harmonic distortion fIN = 10 kHz –84 dB
IN = GND1, fIN = 0 Hz, BW = 10 kHz 300
Output noise µVRMS
IN = GND1, fIN = 0 Hz, BW = 100 kHz 360
vs VDD1, at DC –107
Power-supply rejection vs VDD1, 100-mV and 10-kHz ripple –101
PSRR dB
ratio (2) vs VDD2, at DC –71
vs VDD2, 100-mV and 10-kHz ripple –56
VOUT Output voltage OUTP or OUTN to GND2 GND2 + 0.2 VDD2 – 0.2 V
Common-mode output
VCMout (VOUTP + VOUTN) / 2 0.48 × VDD2 VDD2 / 2 0.52 × VDD2 V
voltage
VDD1 missing, OUTP and OUTN forced to
VFAILSAFE Failsafe output voltage GND2 + 0.1 V
GND2
Output short-circuit
ISC On OUTP or OUTN to GND2 ±18 mA
current
Overload recovery time 5 µs
ROUT Output resistance On OUTP or OUTN to GND2 < 0.5 Ω
On OUTP or OUTN to GND2 100
CLOAD Capacitive load drive (3) pF
OUTP to OUTN 50
RLOAD Resistive load On OUTP or OUTN 10 kΩ
Small signal output ISO224B 220 275
BW kHz
bandwidth ISO224A 150 185
Common-mode transient |GND1 – GND2| = 1 kV, ISO224B 55 80
CMTI kV/µs
immunity |GND1 – GND2| = 1 kV, ISO224A 15 30
POWER SUPPLY
IDD1 High-side supply current 6.1 7.8 mA
IDD2 Low-side supply current 7.8 9.9 mA

(2) This parameter is output referred.

(3) Use series resistor to decouple higher capacilive load.

8 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

7.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO224B on OUTP, OUTN 1.5 µs
tr, tf Rise time, fall time
ISO224A on OUTP, OUTN 2 µs
IN to OUTP, OUTN signal delay ISO224B, unfiltered output, see Figure 1 1.5 2
µs
(50% – 10%) ISO224A, unfiltered output, see Figure 1 1.9 2.9
IN to OUTP, OUTN signal delay ISO224B, unfiltered output, see Figure 1 2.2 2.7
µs
(50% – 50%) ISO224A, unfiltered output, see Figure 1 2.8 3.8
IN to OUTP, OUTN signal delay ISO224B, unfiltered output, see Figure 1 3 3.5
µs
(50% – 90%) ISO224A, unfiltered output, see Figure 1 3.8 4.8
VDD1 step to 4.5 V with VDD2 ≥ 4.5 V,
tAS Analog startup time 250 µs
to OUTP, OUTN valid, 0.1% settling

12 V
50%
0V

IN -12 V

50% - 90%

50% - 50%

50% - 10%

OUTN

90%
50%
VCMout
10%

OUTP
tr tf

Figure 1. Delay Time Test Waveforms

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

7.11 Insulation Characteristics Curves

250 1600
VDD1 = VDD2 = 5.5 V
225 VDD1 = 18 V, VDD2 = 5.5 V 1400
200
1200
175
150 1000

PS (mW)
IS (mA)

125 800
100 600
75
400
50
25 200

0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TA (°C) D001
TA (°C) D002

Figure 2. Thermal Derating Curve for Safety-Limiting Figure 3. Thermal Derating Curve for Safety-Limiting
Current per VDE Power per VDE
1.E+11 Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
1.E+10 TDDB Line (<1 PPM Fail Rate)
87.5%

1.E+9

1.E+8
Time to Fail (s)

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3
20%
1.E+2

1.E+1
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years

Figure 4. Reinforced Isolation Capacitor Lifetime Projection

10 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

7.12 Typical Characteristics

at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.

60 5
4
50
3

40 2
Devices (%)

VOS (mV)
30 0
-1
20
-2

10 -3
-4
0
-5
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
4.5 6 7.5 9 10.5 12 13.5 15 16.5 18
D003 VDD1 (V)
VOS (mV) D004
ISO224B

Figure 5. Input Offset Voltage Histogram Figure 6. Input Offset Voltage vs High-Side Supply Voltage
5 5
4 4
3 3
2 2
1 1
VOS (mV)

VOS (mV)

0 0
-1 -1
-2 -2
-3 -3 Device 1
-4 -4 Device 2
Device 3
-5 -5
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD2 (V) D005
Temperature (°C) D006
ISO224B

Figure 7. Input Offset Voltage vs Low-Side Supply Voltage Figure 8. Input Offset Voltage vs Temperature
60 -13

-13.5
50
-14
40
-14.5
Devices (%)

IIB (nA)

30 -15

-15.5
20
-16
10
-16.5

0 -17
-15
-13
-11
-9
-7
-5
-3
-1

11
13
15
1
3
5
7
9

4.5 6 7.5 9 10.5 12 13.5 15 16.5 18

D007
VDD1 (V) D008
TCVOS (PV/qC)
ISO224B

Figure 9. Input Offset Drift Histogram Figure 10. Input Bias Current vs High-Side Supply Voltage

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

Typical Characteristics (continued)

at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
-13 1000

-13.5

Noise Density (PV/—Hz)

-14 100

-14.5
IIB (nA)

-15 10

-15.5

-16 1

-16.5

-17 0.1
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.01 0.1 1 10 100 1000
Temperature (°C) D009
Frequency (kHz) D010
ISO224B

Figure 11. Input Bias Current vs Temperature Figure 12. Input-Referred Noise Density vs Frequency
60 70

50 60

50
40
Devices (%)
Devices (%)

40
30
30
20
20

10 10

0 0
-0.3

-1
-0.25

-0.2

-0.15

-0.1

-0.05

-0.8

-0.6

-0.4

-0.2
0

0
0.1

0.2

0.3

0.2

0.4

0.6

0.8

1
0.05

0.15

0.25

D011 D012
EG (%) EG (%)
ISO224B ISO224A

Figure 13. Gain Error Histogram Figure 14. Gain Error Histogram
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
EG (%)

EG (%)

0 0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 ISO224A -0.8 ISO224A
ISO224B ISO224B
-1 -1
4.5 6 7.5 9 10.5 12 13.5 15 16.5 18 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
VDD1 (V) D013
VDD2 (V) D014

Figure 15. Gain Error vs High-Side Supply Voltage Figure 16. Gain Error vs Low-Side Supply Voltage

12 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

Typical Characteristics (continued)

at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
1 70

0.8
60
0.6
50
0.4

Devices (%)
0.2 40
EG (%)

0
30
-0.2
-0.4 20

-0.6 Device 1 10
-0.8 Device 2
Device 3 0
-1

-35
-30
-25
-20
-15
-10
-5

10
15
20
25
30
35
5
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) D016
D015 TCEG (ppm/qC)
ISO224B ISO224B

Figure 17. Gain Error vs Temperature Figure 18. Gain Error Drift Histogram
5 0°
0
-45°
-5
-90°
Normalized Gain (dB)

-10
Output Phase

-15 -135°
-20
-180°
-25
-30 -225°
-35 -270°
-40
ISO224A -315° ISO224A
-45
ISO224B ISO224B
-50 -360°
0.1 1 10 100 1000 0.1 1 10 100 1000
fIN (kHz) D017
fIN (kHz) D018

Figure 19. Normalized Gain vs Input Frequency Figure 20. Output Phase vs Input Frequency
7 0.01
VOUTP
VOUTN 0.008
6
0.006
5 0.004
Nonlinearity (%)

0.002
VOUTx (V)

4
0
3
-0.002

2 -0.004
-0.006
1
-0.008
0 -0.01
-16 -12 -8 -4 0 4 8 12 16 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
VIN (V) D019
VIN (V) D020

Figure 21. Output Voltage vs Input Voltage Figure 22. Nonlinearity vs Input Voltage

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

Typical Characteristics (continued)

at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
0.02 0.02

0.015 0.015

0.01 0.01

Nonlinearity (%)
Nonlinearity (%)

0.005 0.005

0 0

-0.005 -0.005

-0.01 -0.01

-0.015 -0.015

-0.02 -0.02
4.5 6 7.5 9 10.5 12 13.5 15 16.5 18 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
VDD1 (V) D021
VDD2 (V) D022

Figure 23. Nonlinearity vs High-Side Supply Voltage Figure 24. Nonlinearity vs Low-Side Supply Voltage
0.02 -74

0.015 -76
-78
0.01
-80
Nonlinearity (%)

0.005 -82
THD (dB)

0 -84

-0.005 -86
-88
-0.01
Device 1 -90
-0.015 Device 2 -92
Device 3
-0.02 -94
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 4.5 6 7.5 9 10.5 12 13.5 15 16.5 18
Temperature (°C) D023
VDD1 (V) D024

Figure 25. Nonlinearity vs Temperature Figure 26. Total Harmonic Distortion

vs High-Side Supply Voltage
-74 -74
Device 1
-76 -76 Device 2
-78 -78 Device 3

-80 -80
-82 -82
THD (dB)

THD (dB)

-84 -84
-86 -86
-88 -88
-90 -90
-92 -92
-94 -94
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD2 (V) D025
Temperature (°C) D026

Figure 27. Total Harmonic Distortion Figure 28. Total Harmonic Distortion vs Temperature
vs Low-Side Supply Voltage

14 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

Typical Characteristics (continued)

at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
0 2.9

2.8
-20
2.7
-40
2.6
PSRR (dB)

VCMout (V)
-60 2.5

2.4
-80
2.3
-100
vs VDD2 2.2
vs VDD1
-120 2.1
0.1 1 10 100 1000 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
Ripple Frequency (kHz) D027
VDD2 (V) D028

Figure 29. Power-Supply Rejection Ratio Figure 30. Output Common-Mode Voltage
vs Ripple Frequency vs Low-Side Supply Voltage
2.9 8

2.8 7.5

2.7
7
2.6
IDD1 (mA)
VCMout (V)

6.5
2.5
6
2.4
5.5
2.3

2.2 5

2.1 4.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 4.5 6 7.5 9 10.5 12 13.5 15 16.5 18
Temperature (°C) D029
VDD1 (V) D030

Figure 31. Output Common-Mode Voltage vs Temperature Figure 32. High-Side Supply Current
vs High-Side Supply Voltage
10 10
IDD2
9.5 9.5 IDD1
9 9

8.5 8.5
IDD2 (mA)

IDDx (mA)

8 8

7.5 7.5

7 7

6.5 6.5

6 6

5.5 5.5
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD2 (V) D031
Temperature (°C) D032

Figure 33. Low-Side Supply Current Figure 34. Supply Current vs Temperature
vs Low-Side Supply Voltage

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

Typical Characteristics (continued)

at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
2.1 2.1

2 2

1.9 1.9

1.8 1.8
tr, tf (Ps)

tr, tf (Ps)
1.7 1.7

1.6 1.6

1.5 1.5

1.4 ISO224A 1.4 ISO224A

ISO224B ISO224B
1.3 1.3
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD2 (V) D033
Temperature (°C) D034

Figure 35. Output Rise and Fall Time Figure 36. Output Rise and Fall Time vs Temperature
vs Low-Side Supply Voltage
3.5 5

4.5
3
4
Signal Delay (Ps)

Signal Delay (Ps)

2.5 3.5

3
2
2.5

1.5 2

1.5
1 50% - 90% 50% - 90%
50% - 50% 1 50% - 50%
50% - 10% 50% - 10%
0.5 0.5
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
VDD2 (V) D035
VDD2 (V) D036
ISO224B ISO224A

Figure 37. VIN to VOUT Signal Delay Figure 38. VIN to VOUT Signal Delay
vs Low-Side Supply Voltage vs Low-Side Supply Voltage
3.5 5

4.5
3
4
Signal Delay (Ps)
Signal Delay (Ps)

2.5 3.5

3
2
2.5

1.5 2

1.5
1 50% - 90% 50% - 90%
50% - 50% 1 50% - 50%
50% - 10% 50% - 10%
0.5 0.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) D037
Temperature (°C) D038
ISO224B ISO224A

Figure 39. VIN to VOUT Signal Delay vs Temperature Figure 40. VIN to VOUT Signal Delay vs Temperature

16 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

8 Detailed Description

8.1 Overview
The ISO224 is a precision, isolated amplifier with a high input impedance and wide input voltage range suitable
for wide range of industrial applications. The input stage of the device drives a delta-sigma (ΔΣ) modulator. The
modulator uses the internal voltage reference and clock generator to convert the analog input signal to a digital
bitstream. The drivers (called TX in the Functional Block Diagram section) transfer the output of the modulator
across the isolation barrier that separates the high-side and low-side voltage domains. The received bitstream
and clock are synchronized and processed by a digital-to-analog conversion stage on the low-side and presented
as a differential analog output.
The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as described
in ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the ISO224 and the isolation
barrier characteristics result in high reliability and high common-mode transient immunity.

8.2 Functional Block Diagram

VDD1 VDD2

Reinforced
Voltage Regulator VDD1 Isolation Bandgap
VCAP
(LDO) Detection Barrier Reference

Data OUTP
û
Clamp TX RX
IN Modulator
OUTN

Bandgap CLK
RX TX Oscillator
Reference

ISO224

GND1 GND2

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

8.3 Feature Description

8.3.1 Analog Input
The input stage of the ISO224 feeds a switched capacitor, feed-forward ΔΣ modulator. The modulator converts
the analog signal into a bitstream that is transferred over the isolation barrier, as described in the Isolation
Channel Signal Transmission section. The high-impedance and low bias-current input of the ISO224 makes the
device suitable for isolated voltage sensing applications.
Figure 41 visualizes the difference in the transfer function of the ISO224 depending on the input signal VIN, as
specified in the Recommended Operating Conditions table. With the input voltage within the specified full-scale
range VFSR, the output of the device changes in a linear way with small error as specified by the nonlinearity
parameter in the Electrical Characteristics table. If the input signal exceeds the VFSR range, the nonlinearity of
the output signals increases and the amplitude clips at VIN = VCLIPPING.
6
VOUTP
VOUTN

5
VCLIPPING

VFSR
4
VOUTx (V)

VCMout

0
-15 -10 -5 0 5 10 15
VIN (V)

Figure 41. Transfer Function of the ISO224

There are two restrictions on the analog input signal at the IN pin. First, if the input voltage VIN exceeds the
range of –15 V to 15 V, the current must be limited to 10 mA to prevent damage to the input clamp, see the Input
Clamp Protection Circuit section for further information. In addition, the linearity and noise performance of the
ISO224 are ensured only when the analog input voltage remains within the specified linear full-scale range
(VFSR).

18 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

Feature Description (continued)

8.3.2 Input Clamp Protection Circuit
As illustrated in the Functional Block Diagram, the ISO224 features an internal clamp protection circuit on the
analog input IN. Using external protection circuits is recommended as a secondary protection scheme to protect
the device against surges, ESD events, and electrical fast transient (EFT) conditions.
Figure 42 shows a typical current versus voltage characteristic curve for the input clamp. Limit either the voltage
VIN at the input pin IN to the voltage range as defined in the Recommended Operating Conditions table or the
input current to the limits as defined in the Absolute Maximum Ratings table.
50
40
30
Input Clamp Current (mA)

20
10
0
-10
-20
-30
-40
-50
-20 -15 -10 -5 0 5 10 15 20
Input Voltage (V) D007

Figure 42. I-V Curve of the Input Clamp Protection Circuit

Figure 43 shows a simple method to limit the input current with an external series resistor that is also used as
part of the input low-pass filter.

ISO224

RFLT IN
Clamp
CFLT
Input
Signal
GND1

GND1

Figure 43. Series Resistor-Based Input Current Limitation on the Analog Inputs of ISO224

The input overvoltage protection clamp on the ISO224 is intended to control transient excursions on the input
pins. Leaving the device in a state such that the clamp circuit is activated for extended periods of time in normal
or power-down mode is not recommended because this fault condition can degrade device performance and
reliability.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

Feature Description (continued)

8.3.3 Isolation Channel Signal Transmission
The ISO224 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream across
the SiO2-based isolation barrier. As shown in Figure 44, the transmitter modulates the bitstream at TX IN with an
internally-generated, high-frequency carrier across the isolation barrier to represent a digital one and does not
send a signal to represent the digital zero. The nominal frequency of the carrier used inside the ISO224 is
480 MHz.
The receiver demodulates the signal after advanced signal conditioning and produces the output. The ISO224
also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions caused by the high-frequency carrier and IO buffer switching.

Transmitter Receiver

OOK
Modulation
SiO2-Based
TX IN Capacitive
TX Signal RX Signal Envelope
Reinforced RX OUT
Conditioning Conditioning Detection
Isolation
Barrier

Oscillator

Figure 44. Block Diagram of an Isolation Channel

Figure 45 shows the concept of the OOK scheme.

TX IN

Carrier Signal Across

the Isolation Barrier

RX OUT

Figure 45. OOK-Based Modulation Scheme

20 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

Feature Description (continued)

8.3.4 Fail-Safe Output
The ISO224 offers a fail-safe output that simplifies diagnostics on system level. The fail-safe output is active
when the high-side power supply VDD1 of the device is missing, independent of the input signal at the IN pin.
Figure 46 shows that in that case both outputs, OUTP and OUTN, of the device are actively driven close to
GND2 (see the VFAILSAFE specification in the Electrical Characteristics table for details). For easy visualization, an
example with the input signal VIN = 0 V is shown for the valid VDD1 range of 4.5 V to 5.5 V.
3.5

2.5

2
VOUTx (V)

Outputs are not specified

in this VDD1 range
1.5

0.5

VFAILSAFEmax
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VDD1 (V)

Figure 46. ISO224 Failsafe Output Behavior With VIN = 0 V

The ISO224 Fail-Safe Output Feature application report describes an example of a comparator-based circuit that
detects the missing high-side supply in a system.

8.4 Device Functional Modes

The ISO224 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO224 enables high-precision measurement of ±10-V signals that are used in a harsh environment in a
wide range of industrial applications. The high input resistance of the device simplifies the connection of its input
to different sensors or other signal sources. The very low nonlinearity, AC and DC errors, and temperature drift
make the ISO224 a robust, high-performance, isolated amplifier for applications where high voltage isolation is
required. The differential output with a full-scale voltage of 4 V offers high immunity to noise and allows
connection to a wide range of analog-to-digital converters (ADCs) powered on a 5-V nominal supply.

9.2 Typical Application

Isolated amplifiers are often used for data acquisition in industrial applications to safely separate the low-voltage
portion of the system from the high common-mode voltage input of the system. The input structure of the ISO224
is optimized for isolated voltage sensing in this kind of application.
Figure 47 shows a typical operation of the device for voltage sensing as used in power line monitoring systems.
The phase voltage amplitude is reduced with a resistive divider to match the input voltage range of the ISO224.
The high input voltage range and the high common-mode transient immunity of the device ensure reliable and
accurate operation even in high-noise environments.
5V ISO224 5V

VDD1 VDD2
RFLTout
R1
AC RFLTin
Voltage VAC IAC CFLTout ADC
CFLTin RFLTout
Source VIN
R2
GND1 GND2
GND2
GND1

Figure 47. Using the ISO224 for AC Voltage Sensing

9.2.1 Design Requirements

Table 1 summarizes the typical design requirements for an AC power line voltage sensing application.

Table 1. Design Requirements

PARAMETER VALUE
AC voltage range, VAC 50 V to 750 V
Bandwidth 600 Hz (minimum)
Current through the resistive divider, IAC 1 mA (maximum)

22 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

9.2.2 Detailed Design Procedure

The high-side power supply (VDD1) for the device is generated with a suitable isolated power source. An
example of such a circuit is provided in the Power Supply Recommendations section.
The floating ground reference (GND1) is derived from one of the ends of the shunt resistor that is connected to
the negative input of the device (VINN). If a four-pin shunt is used, the inputs of the device are connected to the
inner leads and GND1 is connected to one of the outer shunt leads.
Use Ohm's Law to calculate the minimum total resistance of the resistive divider to limit the cross current IAC to
the desired value: R1 + R2 = VAC / IAC. The input voltage at the ISO224 results from the resistance ratio of R1 and
R2 and the actual AC voltage: VIN = VAC x R2 / (R1 + R2).
Consider the following two restrictions to choose the proper value of the R1 and R2 resistors:
• The voltage drop on R2 caused by the nominal AC voltage range of the system must not exceed the
recommended input voltage range VIN of the ISO224
• The voltage drop on R2 caused by the maximum allowed system overvoltage must not exceed the input
voltage that causes a clipping output: VIN ≤ VClipping
Table 2 lists examples of nominal E96-series (1% accuracy) resistor values for AC systems using 120 V, 240 V,
and 400 V as nominal voltages.

Table 2. Resistor Value Examples

PARAMETER 120-VAC SYSTEM 240-VAC SYSTEM 400-VAC SYSTEM
Resistive divider resistor R1 115 kΩ 237 kΩ 392 kΩ
Resistive divider resistor R2 12.7 kΩ 12.4 kΩ 12.1 kΩ
Resulting current through resistive divider IAC 0.93 mA 0.93 mA 0.98 mA
Resulting input voltage VIN ±11.934 V ±11.933 V ±11.977 V

For systems using single-ended input ADCs with a 5-V supply, Figure 48 shows an example of a TLV6001-based
signal conversion and filter circuit. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system and use NP0-type capacitors for best performance.

ISO224 VCMADC

VDD1 VDD2
TLV6001
VIN VOUTP +
To ADC
VCAP VOUTN ±

GND1 GND2

GND2

Figure 48. Connecting the ISO224 Output to a Single-Ended Input 5-V ADC

For systems using single-ended, ±10-V input ADCs, the ISO224EVM offers a signal path based on an OPA277
that converts the differential output of the ISO224 and limits the signal bandwidth to 50 kHz.
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, consult
the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power TI Precision Designs, available for download at
www.ti.com.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

9.2.3 Application Curves

In some applications the system must be protected in case of an overvoltage condition. To allow for fast
powering off of the system, a low delay caused by the isolated amplifier is required. Figure 49 shows the typical
full-scale step response of the device. Consider the delay of the required window comparator and the MCU to
calculate the overall response time of the system.

VIN

VOUTN

VOUTP

Figure 49. Step Response of the ISO224

Figure 50 shows the typical AC response of the device with a full-scale sine wave with a frequency of 20 kHz
applied at the input.

VIN

VOUTP

VOUTN

Figure 50. AC Response of the ISO224 at fIN = 20 kHz

9.3 What to Do and What Not to Do

Do not leave the input of the ISO224 unconnected (floating) when the device is powered up. If the device input is
left floating, both outputs are at the common-mode output voltage level VCMout as specified in the Switching
Characteristics table. See the ISO224 Fail-Safe Output Feature application report for more details.

24 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

10 Power Supply Recommendations

In a typical application, the high-side power supply (VDD1) for the ISO224 is generated from the low-side supply
(VDD2) of the device by an isolated DC/DC converter circuit. A low-cost solution is based on the push-pull driver
SN6501 and a transformer that supports the desired isolation voltage ratings. TI recommends using a low-ESR
decoupling capacitor of 0.1 µF and an additional capacitor of a minimum 1 µF for both supplies of the ISO224.
Figure 51 shows the recommended placement of these decoupling capacitors as close as possible to the ISO224
power-supply pins to minimize supply current loops and electromagnetic emissions.
To decouple the output of the integrated LDO, use a 0.22-µF capacitor placed as close to the VCAP pin of the
ISO224 as possible.
The ISO224 does not require any specific power up sequencing. Consider the analog settling time tAS as
specified in the Switching Characteristics table after ramp up of the VDD1 high-side supply.

ISO224

VDD1
Detection
OUTP

Reinforced Isolation
IN
VDD1
OUTN
VDD1 VDD2
1 …F 0.1 …F
VCAP VDD2
0.1 …F 1 …F
0.22 µF
GND1 GND2
GND1
GND2

TLV70450 VDD2
VDD2
OUT IN SN6501

10 …F 0.1 …F 10 …F 20 V D1 VCC
0.1 …F
GND
D2 GND2
GND1

20 V 10 …F
GND2
GND1
GND2

Figure 51. SN6501-Based, High-Side Power Supply

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

11 Layout

11.1 Layout Guidelines

For best performance, place the 0.22-µF capacitor (C7, as shown in Figure 52) required for decoupling of the
internal LDO output as close as possible to the ISO224 VCAP pin. The 0.1-µF ceramic decoupling capacitors for
both power supplies (C8 and C9) are located as close as possible to the corresponding VDDx pins followed by
the additional 1-µF ceramic capacitors for lower-frequency decoupling (C3 and C12). The resistor and capacitor
used for the analog input (R1 and C2) are placed next to the decoupling capacitors. For best performance, use
0603-size or 1206-size, SMD-type, ceramic capacitors with low ESR. Connect the supply voltage sources in a
way that allows the supply current to flow through the pads of the decoupling capacitors before powering the
device.
Figure 52 shows this approach as implemented on the ISO224EVM. Capacitors C3 and C8 decouple the high-
side supply VDD1 and capacitors C9 and C12 are used to support the low-side supply VDD2 of the ISO224.

11.2 Layout Example

Clearance area,
to be kept free of any
To VDD2 Power
conductive materials
Supply Source

To Input
Signal
Source ISO224 To Filter
or ADC

To Isolated
VDD1 Power
Supply Source

LEGEND

Top-Layer Traces
Bottom-Layer (or Inner-Layer) GND1 and GND2 Copper Pour
Clearance Area to be kept free of conductive materials on all layers

Figure 52. Recommended Layout of the ISO224

26 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 ISO224
www.ti.com SBAS738A – JUNE 2018 – REVISED OCTOBER 2018

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, ADS794x 14-Bit, 2 MSPS, Dual-Channel, Differential/Single-Ended, Ultralow-Power
Analog-to-Digital Converters data sheet
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, ISO224 Fail-Safe Output Feature application report
• Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
• Texas Instruments, OPAx277 High Precision Operational Amplifiers data sheet
• Texas Instruments, 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
TI design
• Texas Instruments, 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power TI design
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, TLV704 24-V Input Voltage, 150-mA, Ultralow IQ Low-Dropout Regulators data sheet
• Texas Instruments, ISO224EVM Evaluation Module users guide

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: ISO224
ISO224
SBAS738A – JUNE 2018 – REVISED OCTOBER 2018 www.ti.com

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: ISO224

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO224ADWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO224A

ISO224ADWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO224A

ISO224BDWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO224B

ISO224BDWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO224B

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO224ADWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1
ISO224BDWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO224ADWVR SOIC DWV 8 1000 350.0 350.0 43.0
ISO224BDWVR SOIC DWV 8 1000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO224ADWV DWV SOIC 8 64 505.46 13.94 4826 6.6
ISO224BDWV DWV SOIC 8 64 505.46 13.94 4826 6.6

Pack Materials-Page 3
 PACKAGE OUTLINE

DWV0008A SCALE 2.000

SOIC - 2.8 mm max height
SOIC

SEATING PLANE
11.5 0.25
PIN 1 ID TYP 0.1 C
AREA
6X 1.27
8
1

5.95 2X
5.75 3.81
NOTE 3

4
5
0.51
8X
0.31
7.6 0.25 C A B
A B 2.8 MAX
7.4
NOTE 4

0.33
TYP
0.13

SEE DETAIL A

(2.286)
0.25
GAGE PLANE

0.46
0.36
0 -8
1.0
0.5 DETAIL A
(2) TYPICAL

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT

DWV0008A SOIC - 2.8 mm max height

SOIC

8X (1.8) SEE DETAILS

SYMM

8X (0.6) SYMM

6X (1.27)
(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X

SOLDER MASK SOLDER MASK METAL

METAL
OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN

DWV0008A SOIC - 2.8 mm max height

SOIC

8X (1.8) SYMM

8X (0.6)
SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated