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ILI9320 v0.41

This document provides information about the ILI9320 a-Si TFT LCD single-chip driver, including: - An overview of its features such as 240RGBx320 resolution and 262K colors. - Descriptions of its system interfaces like SPI and RGB input. - Explanations of its register descriptions and functionality. - Details on pin descriptions, pad arrangement, block diagrams and timing diagrams. The document contains technical specifications and register information to help integrate and control the ILI9320 LCD driver chip.

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0% found this document useful (0 votes)

157 views115 pages

ILI9320 v0.41

Uploaded by

priyanka choudhry

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ILI9320

a-Si TFT LCD Single Chip Driver

240RGBx320 Resolution and 16.7M color

Datasheet
Preliminary

Version: V0.41
Document No.: ILI9320DS_V0.41.pdf

ILI TECHNOLOGY CORP.

4F, No. 2, Tech. 5th Rd., Hsinchu Science Park,
Taiwan 300, R.O.C.
Tel.886-3-5670095; Fax.886-3-5670096
http://www.ilitek.com
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
Table of Contents
Section Page
1. Introduction.................................................................................................................................................... 7
2. Features ........................................................................................................................................................ 7
3. Block Diagram ............................................................................................................................................... 9
4. Pin Descriptions .......................................................................................................................................... 10
5. Pad Arrangement and Coordination............................................................................................................ 15
6. Block Description ........................................................................................................................................ 22
7. System Interface ......................................................................................................................................... 25
7.1. Interface Specifications .................................................................................................................. 25
7.2. Input Interfaces .............................................................................................................................. 26
7.2.1. i80/18-bit System Interface.................................................................................................. 27
7.2.2. i80/16-bit System Interface.................................................................................................. 28
7.2.3. i80/9-bit System Interface.................................................................................................... 29
7.2.4. i80/8-bit System Interface.................................................................................................... 29
7.3. Serial Peripheral Interface (SPI) .................................................................................................... 30
7.4. VSYNC Interface............................................................................................................................ 35
7.5. RGB Input Interface ....................................................................................................................... 39
7.5.1. RGB Interface...................................................................................................................... 40
7.5.2. RGB Interface Timing .......................................................................................................... 41
7.5.3. Moving Picture Mode........................................................................................................... 43
7.5.4. 6-bit RGB Interface.............................................................................................................. 44
7.5.5. 16-bit RGB Interface............................................................................................................ 45
7.5.6. 18-bit RGB Interface............................................................................................................ 45
7.6. Interface Timing.............................................................................................................................. 48
8. Register Descriptions .................................................................................................................................. 49
8.1. Registers Access............................................................................................................................ 49
8.2. Instruction Descriptions.................................................................................................................. 52
8.2.1. Index (IR)............................................................................................................................. 54
8.2.2. Status Read (RS)................................................................................................................. 54
8.2.3. Start Oscillation (R00h)........................................................................................................ 54
8.2.4. Driver Output Control (R01h) .............................................................................................. 54
8.2.5. LCD Driving Wave Control (R02h) ...................................................................................... 56
8.2.6. Entry Mode (R03h) .............................................................................................................. 56
8.2.7. Resizing Control Register (R04h)........................................................................................ 58
8.2.8. Display Control 1 (R07h) ..................................................................................................... 59
8.2.9. Display Control 2 (R08h) ..................................................................................................... 60
8.2.10. Display Control 3 (R09h) ..................................................................................................... 61
8.2.11. Display Control 4 (R0Ah)..................................................................................................... 62

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 2 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
8.2.12. RGB Display Interface Control 1 (R0Ch)............................................................................. 62
8.2.13. Frame Marker Position (R0Dh) ........................................................................................... 63
8.2.14. RGB Display Interface Control 2 (R0Fh) ............................................................................. 64
8.2.15. Power Control 1 (R10h)....................................................................................................... 64
8.2.16. Power Control 2 (R11h) ....................................................................................................... 66
8.2.17. Power Control 3 (R12h)....................................................................................................... 66
8.2.18. Power Control 4 (R13h)....................................................................................................... 67
8.2.19. GRAM Horizontal/Vertical Address Set (R20h, R21h) ........................................................ 67
8.2.20. Write Data to GRAM (R22h)................................................................................................ 68
8.2.21. Read Data from GRAM (R22h) ........................................................................................... 68
8.2.22. Power Control 7 (R29h)....................................................................................................... 70
8.2.23. Frame Rate and Color Control (R2Bh)................................................................................ 71
8.2.24. Gamma Control (R30h ~ R3Dh).......................................................................................... 72
8.2.25. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) ....................... 72
8.2.26. Gate Scan Control (R60h, R61h, R6Ah) ............................................................................. 73
8.2.27. Partial Image 1 Display Position (R80h).............................................................................. 76
8.2.28. Partial Image 1 RAM Start/End Address (R81h, R82h)....................................................... 76
8.2.29. Partial Image 2 Display Position (R83h).............................................................................. 76
8.2.30. Partial Image 2 RAM Start/End Address (R84h, R85h)....................................................... 76
8.2.31. Panel Interface Control 1 (R90h)......................................................................................... 76
8.2.32. Panel Interface Control 2 (R92h)......................................................................................... 77
8.2.33. Panel Interface Control 3 (R93h)......................................................................................... 78
8.2.34. Panel Interface Control 4 (R95h)......................................................................................... 78
8.2.35. Panel Interface Control 5 (R97h)......................................................................................... 79
8.2.36. Panel Interface Control 6 (R98h)......................................................................................... 79
9. GRAM Address Map & Read/Write ............................................................................................................. 80
10. Window Address Function........................................................................................................................... 86
11. Gamma Correction...................................................................................................................................... 88
12. Application................................................................................................................................................... 97
12.1. Configuration of Power Supply Circuit ........................................................................................... 97
12.2. Display ON/OFF Sequence ......................................................................................................... 100
12.3. Standby and Sleep Mode ............................................................................................................. 101
12.4. Power Supply Configuration ........................................................................................................ 102
12.5. Voltage Generation ...................................................................................................................... 103
12.6. Applied Voltage to the TFT panel................................................................................................. 104
12.7. Oscillator ...................................................................................................................................... 104
12.8. Frame Rate Adjustment ............................................................................................................... 105
12.9. Partial Display Function ............................................................................................................... 105
12.10. Resizing Function......................................................................................................................... 106

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 4 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
Figures
FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION .................................................................................... 26
FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 27
FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 28
FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 29
FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 30
FIGURE6 DATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE.................................................................. 30
FIGURE 7 DATA FORMAT OF SPI INTERFACE ..................................................................................................................... 32
FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ............................................................... 33
FIGURE9 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=”1” AND DFM=”10”).................... 34
FIGURE10 DATA TRANSMISSION THROUGH VSYNC INTERFACE)....................................................................................... 35
FIGURE11 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE ............................................................ 35
FIGURE12 OPERATION THROUGH VSYNC INTERFACE ...................................................................................................... 36
FIGURE13 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES ............................................ 38
FIGURE14 RGB INTERFACE DATA FORMAT ...................................................................................................................... 39
FIGURE15 GRAM ACCESS AREA BY RGB INTERFACE ..................................................................................................... 40
FIGURE16 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE .................................................................. 41
FIGURE17 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ............................................................................ 42
FIGURE18 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE .................................................................................... 43
FIGURE19 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ................................................................... 46
FIGURE20 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE .............................................................. 47
FIGURE21 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ..................................... 48
FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)...................................................................... 49
FIGURE23 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................................................................................ 50
FIGURE 24 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ........................................................................... 51
FIGURE25 GRAM ACCESS DIRECTION SETTING ............................................................................................................... 56
FIGURE26 16-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................. 57
FIGURE27 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 58
FIGURE 28 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE .............. 69
FIGURE 29 GRAM DATA READ BACK FLOW CHART ........................................................................................................ 70
FIGURE 30 GRAM ACCESS RANGE CONFIGURATION ........................................................................................................ 73
FIGURE31 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ............................................................................... 80
FIGURE32 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=”0”, BGR=”0”) ................................................. 82
FIGURE33 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=”0”, BGR=”0”) .............................................................. 83
FIGURE 34 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=”1”, BGR=”1”) ....................................................... 85
FIGURE 35 GRAM ACCESS WINDOW MAP ....................................................................................................................... 86
FIGURE 36 GRAYSCALE VOLTAGE GENERATION ............................................................................................................... 88
FIGURE 37 GRAYSCALE VOLTAGE ADJUSTMENT .............................................................................................................. 89
FIGURE 38 GAMMA CURVE ADJUSTMENT ......................................................................................................................... 90

The dithering image processing is implemented in ILI9320 to provide the 16 million colors display quality and
the Multi-domain Vertical Alignment (MVA) wide view angle display is also supported in the ILI9320.

ILI9320 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width),
VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer interface (SPI)
and RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]).

In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow
address function enables to display a moving picture at a position specified by a user and still pictures in other
areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to
minimize data transfers and power consumption.

ILI9320 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate
voltage levels for driving an LCD. The ILI9320 also supports a function to display in 8 colors and a sleep mode,
allowing for precise power control by software and these features make the ILI9320 an ideal LCD driver for
medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where
long battery life is a major concern.

2. Features
Single chip solution for a liquid crystal QVGA TFT LCD display
240RGBx320-dot resolution capable with real 262,144 display color
Dithering image processing implemented to provide 16.7-million color display quality
Support MVA (Multi-domain Vertical Alignment) wide view display
Incorporate 720-channel source driver and 320-channel gate driver
Internal 172,800 bytes graphic RAM
High-speed RAM burst write function
System interfaces
¾ i80 system interface with 8-/ 9-/16-/18-bit bus width
¾ Serial Peripheral Interface (SPI)
¾ RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])
¾ VSYNC interface (System interface + VSYNC)
n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily n lines (n: 1 ~ 64)
Internal oscillator and hardware reset
Resizing function (×1/2, ×1/4)
Reversible source/gate driver shift direction
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 7 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
Window address function to specify a rectangular area for internal GRAM access
Bit operation function for facilitating graphics data processing
¾ Bit-unit write data mask function
¾ Pixel-unit logical/conditional write function
Abundant functions for color display control
¾ γ-correction function enabling display in 262,144 colors
¾ Line-unit vertical scrolling function
Partial drive function, enabling partially driving an LCD panel at positions specified by user
Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6)
Power saving functions
¾ 8-color mode
¾ standby mode
¾ sleep mode
Low -power consumption architecture
¾ Low operating power supplies:
IOVcc = 1.65V ~ 3.3 V (interface I/O)
Vcc = 2.4V ~ 3.3 V (internal logic)
Vci = 2.5V ~ 3.3 V (analog)
LCD Voltage drive:
¾ Source/VCOM power supply voltage
DVDH - GND = 4.5V ~ 6.0
VCL – GND = -2.0V ~ -3.0V
VCI – VCL ≦ 6.0V
¾ Gate driver output voltage
VGH - GND = 10V ~ 20V
VGL – GND = -5V ~ -15V
VGH – VGL ≦ 32V
¾ VCOM driver output voltage
VCOMH = 3.0V ~ (DDVDH-0.5)V
VCOML = (VCL+0.5)V ~ 0V
VCOMH-VCOML ≦ 6.0V
a-TFT LCD storage capacitor: Cst only

IOVCC Index
IM[3:0] Register
nRESET (IR)
nCS MPU I/F
7
nWR/SCL 18-bit
nRD 16-bit
Control Address
9-bit 18 LCD
RS Register Counter
8-bit Source S[720:1]
SDI (CR) (AC)
Driver
SDO SPI I/F
DB[17:0]
HSYNC RGB I/F
18-bit 18 Graphics 18
VSYNC
16-bit Operation
DOTCLK
6-bit
ENABLE V63 ~ 0

TEST1 VSYNC I/F VREG1OUT

18 Read Write Grayscale
TEST2
Latch Latch Reference
TS[7:0]
Voltage
72 72 VGS

VCC Graphics RAM

VDD Regulator (GRAM)
GND

LCD
OSC1 Gate G[320:1]
Timing
RC-OSC. Driver
OSC2
Controller

VCI
VCI1
VCOM
VCILVL Charge-pump Power Circuit VCOM
Generator
AGND
C21+

C22+

C23+
VLOUT2
VLOUT3

C21-

C22-

C23-
VCL

VCOML
C11+

DDVDH
C11-

VCOMR

VCOMH
C12-

C13-
C12+

C13+

VGH
VLOUT1

VGL

18-bit parallel bi-directional data bus for RGB interface operation

6-bit RGB I/F: DB[17:12] are used.
16-bit RGB I/F: DB[17:13] and DB[11:1] are used.

Unused pins must be fixed either IOVcc or DGND level.

Data ENEABLE signal for RGB interface operation.
Low: Select (access enabled)
MPU High: Not select (access inhibited)
ENABLE I
IOVcc The EPL bit inverts the polarity of the ENABLE signal.

Fix to either IOVcc or DGND level when not in use.

Dot clock signal for RGB interface operation.
MPU DPL = “0”: Input data on the rising edge of DOTCLK
DOTCLK I
IOVcc DPL = “1”: Input data on the falling edge of DOTCLK
Fix to the IOVcc level when not in use
Frame synchronizing signal for RGB interface operation.
MPU VSPL = “0”: Active low.
VSYNC I
IOVcc VSPL = “1”: Active high.
Fix to the IOVcc level when not in use.
Line synchronizing signal for RGB interface operation.
MPU HSPL = “0”: Active low.
HSYNC I
IOVcc HSPL = “1”: Active high.
Fix to the IOVcc level when not in use
Output a frame head pulse signal.
MPU
FMARK O The FMARK signal is used when writing RAM data in synchronization
IOVcc
with frame. Leave the pin open when not in use.
OSC1 I Oscillation Connect an external resistor for generating internal clock by internal
OSC2 O resistor R-C oscillation, or an external clock signal is supplied through OSC1.
LCD Driving signals
Source output voltage signals applied to liquid crystal.
To change the shift direction of signal outputs, use the SS bit.
SS = “0”, the data in the RAM address “h00000” is output from S1.
S720~S1 O LCD
SS = “1”, the data in the RAM address “h00000” is output from S720.
S1, S4, S7, … display red (R), S2, S5, S8, ... display green (G), and
S3, S6, S9, ... display blue (B) (SS = 0).
Gate line output signals.
G320~G1 O LCD VGH: the level selecting gate lines
VGL: the level not selecting gate lines
TFT A supply voltage to the common electrode of TFT panel.
VCOM O common VCOM is AC voltage alternating signal between the VCOMH and
electrode VCOML levels.
Stabilizing The high level of VCOM AC voltage. Connect to a stabilizing
VCOMH O
capacitor capacitor.
Stabilizing The low level of VCOM AC voltage. Adjust the VCOML level with the
VCOML O
capacitor VDV bits. Connect to a stabilizing capacitor.
A reference level to generate the VCOMH level either with an
externally connected variable resistor or by setting the register of the
Variable
ILI9320. When using a variable resistor, halt the internal VCOMH
VCOMR I resistor or
adjusting circuit by setting the register and place the resister between
open
VREG1OUT and AGND. When generating the VCOMH level by
setting the register, leave this pin open.
AGND or
Reference level for the grayscale voltage generating circuit. The VGS
VGS I external
level can be changed by connecting to an external resistor.
resistor
Charge-pump and Regulator Circuit
Power A supply voltage to the analog circuit. Connect to an external power
Vci I
supply supply of 2.5 ~ 3.3V.
AGND I Power AGND for the analog side: AGND = 0V. In case of COG, connect to

Liquid crystal power supply specifications Table 1

No. Item Description
1 TFT Source Driver 720 pins (240 x RGB)
2 TFT Gate Driver 320 pins
3 TFT Display’s Capacitor Structure Cst structure only (Common VCOM)
S1 ~ S720 V0 ~ V63 grayscales
Liquid Crystal Drive G1 ~ G320 VGH - VGL
4
Output VCOMH - VCOML: Amplitude = electronic volumes
VCOM
VCOMH=VCOMR: Adjusted with an external resistor
IOVcc 1.65 ~ 3.30V
5 Input Voltage Vcc 2.40 ~ 3.30V
Vci 2.50 ~ 3.30V
6 Liquid Crystal Drive DDVDH 4.5V ~ 6.0V

(1-a) TESTO38
TESTO37
DUMMYR10
DUMMYR9
VGLDMY4
DUMMYR1

1
G2
DUMMYR2

Chip Size: 21680um x 1250um

TESTO1
G4
VCCDUM1 G6
VPP1 G8
VPP1 G10
VPP1
VPP2
VPP2
VPP2

Chip thickness : 400 um (typ.)

0
1
VPP2
VPP2
VPP3
VPP3

……………………….
……………………….
VPP3
TESTO2
IOGNDDUM1

Pad Location: Pad Center.

TESTO3
TEST1
TEST2

0
2
TEST4
TEST5
TEST3
IM0/ID

Coordinate Origin: Chip center

IM1
IM2
IM3
TESTO4
IOVCCDUM1
TESTO5

0
3
nRESET
VSYNC

Au bump height: 15um (typ.)

HSYNC
DOTCLK
G312
ENABLE
DB17 G314
DB16 G316
DB15 G318
DB14 G320
DB13

Au Bump Size:
VGLDMY3

0
4
DB12 TESTO36
DB11
DB10
DB9

220um
DB8
TESTO6
IOGNDDUM2

1. 21um x 100um (No. 299 ~ 1354)

TESTO7
DB7
DB6

0
5
DB5 TESTO35

Gate: G1 ~ G320
DB4 S1
DB3 S2
DB2
DB1
S3

Source: S1 ~ S720 DB0 S4

SDO S5
SDI S6
nRD S7
nWR/SCL

0
6
S8
RS S9
nCS

2. 50um x 80um (No. 1 ~ 298)

TESTO8
IOVCCDUM2
TESTO9
FMARK

Input Pads
TS8
TS7
TS6
TS5

Pad 1 to 298.

0
7
TS4
TS3
TS2
TS1
TS0
TSC
TESTO10
IOGNDDUM3
TESTO11
TESTO12

0
8
OSC1DUM1
OSC1DUM2
OSC1
OSC1DUM3

(Bump View)
OSC1DUM4
OSC2
OSC2DUM1
OSC2DUM2
DUMMYR3

Face Up
DUMMYR4

0
9
IOGND
IOGND
IOGND
IOGND
IOGND
IOGND

Alignment Marks
IOGND
IOVCC
IOVCC
IOVCC

0
0
1
IOVCC
IOVCC
IOVCC
IOVCC

Alignment Mark: 1-a, 1-b.

VCC
VCC
VCC
VCC
VCC
VCC

0
1
1
VCC

30 40 30
VCC
VDD
VDD
VDD

………………………………………………………………………………………………..

………………………………………………………………………………………………..
VDD
VDD
VDD
VDD
VDD
0
2
1

VDD
VDD
VDD
VDD
VDD
TESTO13
30

VREFD
TESTO14
VREF
TESTO15
0
3
1

VREFC
TESTO16
VDDTEST
AGND
AGND
AGND
40

AGND
AGND
AGND
AGND
0
4
1

AGND
AGND
AGND
AGND
GND
Y
30

GND
GND
GND
GND
GND
0
5
1

GND
GND

100um GND
GND
GND
GND
GND
GND
GND
X

GND
0
6
1

TESTO17
VTEST
TESTO18
VGS
TESTO19
V0T
TESTO20
VMON
TESTO21
V31T
0
7
1

VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOMH
VCOMH
VCOMH
VCOMH
0
8
1

VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
TESTO22
TESTO23
0
9
1

VREG1OUT
TESTO24
TESTA5
TESTO25
VCOMR
TESTO26
VCL
VCL
VCL
VLOUT1
0
0
2

VLOUT1
VLOUT1
DDVDH
S712
DDVDH
DDVDH S713
DDVDH S714
DDVDH S715
DDVDH S716
DDVDH S717
VCIOUT
0
1
2

S718
VCIOUT S719
VCIOUT S720
VCI1
TESTO34
VCI1
VCI1
VCI1
VCI1
220um

VCILVL
VCI
VCI
0
2
2

VCI
VCI
VCI
TESTO33
VCI
VCI VGLDMY2
VCI G319
C12- G317
C12- G315
C12- G313
C12-
0
3
2

G311
C12-
C12+
C12+
C12+
C12+
C12+
C11-
C11-
C11-
C11-
0
4
2

C11-
C11+
C11+
………………………………………………………………………………………...

………………………………………………………………………………………...

C11+
C11+
C11+
AGNDDUM1
VLOUT3
VLOUT3
VGL
0
5
2

VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL

Bump View
VGL
AGNDDUM2
0
6
2

AGNDDUM3
AGNDDUM4

ILI9320
VLOUT2
VLOUT2
VGH
VGH
VGH
VGH
TESTO27
C13-
0
7
2

C13-
C13-
TESTO28
C13+
C13+
C13+
TESTO29
C21-
C21-
C21-
0
8
2

C21+
C21+
C21+
C22-
C22-
C22-
C22+
C22+
C22+
C23-
0
9
2

C23-
C23-
C23+ G9
C23+ G7
C23+ G5
TESTO30
G3
DUMMYR5
DUMMYR6 G1
8
9
2

VGLDMY1
DUMMYR8
DUMMYR7
TESTO32
TESTO31
(1-b)

No. Name X Y No. Name X Y No. Name X Y No. Name X Y No. Name X Y
1 DUMMYR1 -10395.0 -517.5 61 RS -6195.0 -517.5 121 VDD -1995.0 -517.5 181 VCOMH 2205.0 -517.5 241 C11- 6405.0 -517.5
2 DUMMYR2 -10325.0 -517.5 62 CS* -6125.0 -517.5 122 VDD -1925.0 -517.5 182 VCOMH 2275.0 -517.5 242 C11+ 6475.0 -517.5
3 TESTO1 -10255.0 -517.5 63 TESTO8 -6055.0 -517.5 123 VDD -1855.0 -517.5 183 VCOML 2345.0 -517.5 243 C11+ 6545.0 -517.5
4 VCCDUM1 -10185.0 -517.5 64 IOVCCDUM2 -5985.0 -517.5 124 VDD -1785.0 -517.5 184 VCOML 2415.0 -517.5 244 C11+ 6615.0 -517.5
5 VPP1 -10115.0 -517.5 65 TESTO9 -5915.0 -517.5 125 VDD -1715.0 -517.5 185 VCOML 2485.0 -517.5 245 C11+ 6685.0 -517.5
6 VPP1 -10045.0 -517.5 66 FMARK -5845.0 -517.5 126 TESTO13 -1645.0 -517.5 186 VCOML 2555.0 -517.5 246 C11+ 6755.0 -517.5
7 VPP1 -9975.0 -517.5 67 TS8 -5775.0 -517.5 127 VREFD -1575.0 -517.5 187 VCOML 2625.0 -517.5 247 AGNDDUM1 6825.0 -517.5
8 VPP2 -9905.0 -517.5 68 TS7 -5705.0 -517.5 128 TESTO14 -1505.0 -517.5 188 VCOML 2695.0 -517.5 248 VLOUT3 6895.0 -517.5
9 VPP2 -9835.0 -517.5 69 TS6 -5635.0 -517.5 129 VREF -1435.0 -517.5 189 TESTO22 2765.0 -517.5 249 VLOUT3 6965.0 -517.5
10 VPP2 -9765.0 -517.5 70 TS5 -5565.0 -517.5 130 TESTO15 -1365.0 -517.5 190 TESTO23 2835.0 -517.5 250 VGL 7035.0 -517.5
11 VPP2 -9695.0 -517.5 71 TS4 -5495.0 -517.5 131 VREFC -1295.0 -517.5 191 VREG1OUT 2905.0 -517.5 251 VGL 7105.0 -517.5
12 VPP2 -9625.0 -517.5 72 TS3 -5425.0 -517.5 132 TESTO16 -1225.0 -517.5 192 TESTO24 2975.0 -517.5 252 VGL 7175.0 -517.5
13 VPP3 -9555.0 -517.5 73 TS2 -5355.0 -517.5 133 VDDTEST -1155.0 -517.5 193 TESTA5 3045.0 -517.5 253 VGL 7245.0 -517.5
14 VPP3 -9485.0 -517.5 74 TS1 -5285.0 -517.5 134 AGND -1085.0 -517.5 194 TESTO25 3115.0 -517.5 254 VGL 7315.0 -517.5
15 VPP3 -9415.0 -517.5 75 TS0 -5215.0 -517.5 135 AGND -1015.0 -517.5 195 VCOMR 3185.0 -517.5 255 VGL 7385.0 -517.5
16 TESTO2 -9345.0 -517.5 76 TSC -5145.0 -517.5 136 AGND -945.0 -517.5 196 TESTO26 3255.0 -517.5 256 VGL 7455.0 -517.5
17 IOGNDDUM1 -9275.0 -517.5 77 TESTO10 -5075.0 -517.5 137 AGND -875.0 -517.5 197 VCL 3325.0 -517.5 257 VGL 7525.0 -517.5
18 TESTO3 -9205.0 -517.5 78 IOGNDDUM3 -5005.0 -517.5 138 AGND -805.0 -517.5 198 VCL 3395.0 -517.5 258 VGL 7595.0 -517.5
19 TEST1 -9135.0 -517.5 79 TESTO11 -4935.0 -517.5 139 AGND -735.0 -517.5 199 VCL 3465.0 -517.5 259 VGL 7665.0 -517.5
20 TEST2 -9065.0 -517.5 80 TESTO12 -4865.0 -517.5 140 AGND -665.0 -517.5 200 VLOUT1 3535.0 -517.5 260 AGNDDUM2 7735.0 -517.5
21 TEST4 -8995.0 -517.5 81 OSC1DUM1 -4795.0 -517.5 141 AGND -595.0 -517.5 201 VLOUT1 3605.0 -517.5 261 AGNDDUM3 7805.0 -517.5
22 TEST5 -8925.0 -517.5 82 OSC1DUM2 -4725.0 -517.5 142 AGND -525.0 -517.5 202 VLOUT1 3675.0 -517.5 262 AGNDDUM4 7875.0 -517.5
23 TEST3 -8855.0 -517.5 83 OSC1 -4655.0 -517.5 143 AGND -455.0 -517.5 203 DDVDH 3745.0 -517.5 263 VLOUT2 7945.0 -517.5
24 IM0/ID -8785.0 -517.5 84 OSC1DUM3 -4585.0 -517.5 144 AGND -385.0 -517.5 204 DDVDH 3815.0 -517.5 264 VLOUT2 8015.0 -517.5
25 IM1 -8715.0 -517.5 85 OSC1DUM4 -4515.0 -517.5 145 GND -315.0 -517.5 205 DDVDH 3885.0 -517.5 265 VGH 8085.0 -517.5
26 IM2 -8645.0 -517.5 86 OSC2 -4445.0 -517.5 146 GND -245.0 -517.5 206 DDVDH 3955.0 -517.5 266 VGH 8155.0 -517.5
27 IM3 -8575.0 -517.5 87 OSC2DUM1 -4375.0 -517.5 147 GND -175.0 -517.5 207 DDVDH 4025.0 -517.5 267 VGH 8225.0 -517.5
28 TESTO4 -8505.0 -517.5 88 OSC2DUM2 -4305.0 -517.5 148 GND -105.0 -517.5 208 DDVDH 4095.0 -517.5 268 VGH 8295.0 -517.5
29 IOVCCDUM1 -8435.0 -517.5 89 DUMMYR3 -4235.0 -517.5 149 GND -35.0 -517.5 209 DDVDH 4165.0 -517.5 269 TESTO27 8365.0 -517.5
30 TESTO5 -8365.0 -517.5 90 DUMMYR4 -4165.0 -517.5 150 GND 35.0 -517.5 210 VCIOUT 4235.0 -517.5 270 C13- 8435.0 -517.5
31 RESET* -8295.0 -517.5 91 IOGND -4095.0 -517.5 151 GND 105.0 -517.5 211 VCIOUT 4305.0 -517.5 271 C13- 8505.0 -517.5
32 VSYNC -8225.0 -517.5 92 IOGND -4025.0 -517.5 152 GND 175.0 -517.5 212 VCIOUT 4375.0 -517.5 272 C13- 8575.0 -517.5
33 HSYNC -8155.0 -517.5 93 IOGND -3955.0 -517.5 153 GND 245.0 -517.5 213 VCI1 4445.0 -517.5 273 TESTO28 8645.0 -517.5
34 DOTCLK -8085.0 -517.5 94 IOGND -3885.0 -517.5 154 GND 315.0 -517.5 214 VCI1 4515.0 -517.5 274 C13+ 8715.0 -517.5
35 ENABLE -8015.0 -517.5 95 IOGND -3815.0 -517.5 155 GND 385.0 -517.5 215 VCI1 4585.0 -517.5 275 C13+ 8785.0 -517.5
36 DB17 -7945.0 -517.5 96 IOGND -3745.0 -517.5 156 GND 455.0 -517.5 216 VCI1 4655.0 -517.5 276 C13+ 8855.0 -517.5
37 DB16 -7875.0 -517.5 97 IOGND -3675.0 -517.5 157 GND 525.0 -517.5 217 VCI1 4725.0 -517.5 277 TESTO29 8925.0 -517.5
38 DB15 -7805.0 -517.5 98 IOVCC -3605.0 -517.5 158 GND 595.0 -517.5 218 VCILVL 4795.0 -517.5 278 C21- 8995.0 -517.5
39 DB14 -7735.0 -517.5 99 IOVCC -3535.0 -517.5 159 GND 665.0 -517.5 219 VCI 4865.0 -517.5 279 C21- 9065.0 -517.5
40 DB13 -7665.0 -517.5 100 IOVCC -3465.0 -517.5 160 GND 735.0 -517.5 220 VCI 4935.0 -517.5 280 C21- 9135.0 -517.5
41 DB12 -7595.0 -517.5 101 IOVCC -3395.0 -517.5 161 TESTO17 805.0 -517.5 221 VCI 5005.0 -517.5 281 C21+ 9205.0 -517.5
42 DB11 -7525.0 -517.5 102 IOVCC -3325.0 -517.5 162 VTEST 875.0 -517.5 222 VCI 5075.0 -517.5 282 C21+ 9275.0 -517.5
43 DB10 -7455.0 -517.5 103 IOVCC -3255.0 -517.5 163 TESTO18 945.0 -517.5 223 VCI 5145.0 -517.5 283 C21+ 9345.0 -517.5
44 DB9 -7385.0 -517.5 104 IOVCC -3185.0 -517.5 164 VGS 1015.0 -517.5 224 VCI 5215.0 -517.5 284 C22- 9415.0 -517.5
45 DB8 -7315.0 -517.5 105 VCC -3115.0 -517.5 165 TESTO19 1085.0 -517.5 225 VCI 5285.0 -517.5 285 C22- 9485.0 -517.5
46 TESTO6 -7245.0 -517.5 106 VCC -3045.0 -517.5 166 V0T 1155.0 -517.5 226 VCI 5355.0 -517.5 286 C22- 9555.0 -517.5
47 IOGNDDUM2 -7175.0 -517.5 107 VCC -2975.0 -517.5 167 TESTO20 1225.0 -517.5 227 C12- 5425.0 -517.5 287 C22+ 9625.0 -517.5
48 TESTO7 -7105.0 -517.5 108 VCC -2905.0 -517.5 168 VMON 1295.0 -517.5 228 C12- 5495.0 -517.5 288 C22+ 9695.0 -517.5
49 DB7 -7035.0 -517.5 109 VCC -2835.0 -517.5 169 TESTO21 1365.0 -517.5 229 C12- 5565.0 -517.5 289 C22+ 9765.0 -517.5
50 DB6 -6965.0 -517.5 110 VCC -2765.0 -517.5 170 V31T 1435.0 -517.5 230 C12- 5635.0 -517.5 290 C23- 9835.0 -517.5
51 DB5 -6895.0 -517.5 111 VCC -2695.0 -517.5 171 VCOM 1505.0 -517.5 231 C12- 5705.0 -517.5 291 C23- 9905.0 -517.5
52 DB4 -6825.0 -517.5 112 VCC -2625.0 -517.5 172 VCOM 1575.0 -517.5 232 C12+ 5775.0 -517.5 292 C23- 9975.0 -517.5
53 DB3 -6755.0 -517.5 113 VDD -2555.0 -517.5 173 VCOM 1645.0 -517.5 233 C12+ 5845.0 -517.5 293 C23+ 10045.0 -517.5
54 DB2 -6685.0 -517.5 114 VDD -2485.0 -517.5 174 VCOM 1715.0 -517.5 234 C12+ 5915.0 -517.5 294 C23+ 10115.0 -517.5
55 DB1 -6615.0 -517.5 115 VDD -2415.0 -517.5 175 VCOM 1785.0 -517.5 235 C12+ 5985.0 -517.5 295 C23+ 10185.0 -517.5
56 DB0 -6545.0 -517.5 116 VDD -2345.0 -517.5 176 VCOM 1855.0 -517.5 236 C12+ 6055.0 -517.5 296 TESTO30 10255.0 -517.5
57 SDO -6475.0 -517.5 117 VDD -2275.0 -517.5 177 VCOMH 1925.0 -517.5 237 C11- 6125.0 -517.5 297 DUMMYR5 10325.0 -517.5
58 SDI -6405.0 -517.5 118 VDD -2205.0 -517.5 178 VCOMH 1995.0 -517.5 238 C11- 6195.0 -517.5 298 DUMMYR6 10395.0 -517.5
59 RD* -6335.0 -517.5 119 VDD -2135.0 -517.5 179 VCOMH 2065.0 -517.5 239 C11- 6265.0 -517.5 299 TESTO31 10670.0 511.5
60 WR*/SCL -6265.0 -517.5 120 VDD -2065.0 -517.5 180 VCOMH 2135.0 -517.5 240 C11- 6335.0 -517.5 300 TESTO32 10650.0 386.5

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 16 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
No. Name X Y No. Name X Y No. Name X Y No. Name X Y No. Name X Y
301 DUMMYR7 10630.0 511.5 361 G115 9430.0 511.5 421 G235 8230.0 511.5 481 S706 6830.0 386.5 541 S646 5630.0 386.5
302 DUMMYR8 10610.0 386.5 362 G117 9410.0 386.5 422 G237 8210.0 386.5 482 S705 6810.0 511.5 542 S645 5610.0 511.5
303 VGLDMY1 10590.0 511.5 363 G119 9390.0 511.5 423 G239 8190.0 511.5 483 S704 6790.0 386.5 543 S644 5590.0 386.5
304 G1 10570.0 386.5 364 G121 9370.0 386.5 424 G241 8170.0 386.5 484 S703 6770.0 511.5 544 S643 5570.0 511.5
305 G3 10550.0 511.5 365 G123 9350.0 511.5 425 G243 8150.0 511.5 485 S702 6750.0 386.5 545 S642 5550.0 386.5
306 G5 10530.0 386.5 366 G125 9330.0 386.5 426 G245 8130.0 386.5 486 S701 6730.0 511.5 546 S641 5530.0 511.5
307 G7 10510.0 511.5 367 G127 9310.0 511.5 427 G247 8110.0 511.5 487 S700 6710.0 386.5 547 S640 5510.0 386.5
308 G9 10490.0 386.5 368 G129 9290.0 386.5 428 G249 8090.0 386.5 488 S699 6690.0 511.5 548 S639 5490.0 511.5
309 G11 10470.0 511.5 369 G131 9270.0 511.5 429 G251 8070.0 511.5 489 S698 6670.0 386.5 549 S638 5470.0 386.5
310 G13 10450.0 386.5 370 G133 9250.0 386.5 430 G253 8050.0 386.5 490 S697 6650.0 511.5 550 S637 5450.0 511.5
311 G15 10430.0 511.5 371 G135 9230.0 511.5 431 G255 8030.0 511.5 491 S696 6630.0 386.5 551 S636 5430.0 386.5
312 G17 10410.0 386.5 372 G137 9210.0 386.5 432 G257 8010.0 386.5 492 S695 6610.0 511.5 552 S635 5410.0 511.5
313 G19 10390.0 511.5 373 G139 9190.0 511.5 433 G259 7990.0 511.5 493 S694 6590.0 386.5 553 S634 5390.0 386.5
314 G21 10370.0 386.5 374 G141 9170.0 386.5 434 G261 7970.0 386.5 494 S693 6570.0 511.5 554 S633 5370.0 511.5
315 G23 10350.0 511.5 375 G143 9150.0 511.5 435 G263 7950.0 511.5 495 S692 6550.0 386.5 555 S632 5350.0 386.5
316 G25 10330.0 386.5 376 G145 9130.0 386.5 436 G265 7930.0 386.5 496 S691 6530.0 511.5 556 S631 5330.0 511.5
317 G27 10310.0 511.5 377 G147 9110.0 511.5 437 G267 7910.0 511.5 497 S690 6510.0 386.5 557 S630 5310.0 386.5
318 G29 10290.0 386.5 378 G149 9090.0 386.5 438 G269 7890.0 386.5 498 S689 6490.0 511.5 558 S629 5290.0 511.5
319 G31 10270.0 511.5 379 G151 9070.0 511.5 439 G271 7870.0 511.5 499 S688 6470.0 386.5 559 S628 5270.0 386.5
320 G33 10250.0 386.5 380 G153 9050.0 386.5 440 G273 7850.0 386.5 500 S687 6450.0 511.5 560 S627 5250.0 511.5
321 G35 10230.0 511.5 381 G155 9030.0 511.5 441 G275 7830.0 511.5 501 S686 6430.0 386.5 561 S626 5230.0 386.5
322 G37 10210.0 386.5 382 G157 9010.0 386.5 442 G277 7810.0 386.5 502 S685 6410.0 511.5 562 S625 5210.0 511.5
323 G39 10190.0 511.5 383 G159 8990.0 511.5 443 G279 7790.0 511.5 503 S684 6390.0 386.5 563 S624 5190.0 386.5
324 G41 10170.0 386.5 384 G161 8970.0 386.5 444 G281 7770.0 386.5 504 S683 6370.0 511.5 564 S623 5170.0 511.5
325 G43 10150.0 511.5 385 G163 8950.0 511.5 445 G283 7750.0 511.5 505 S682 6350.0 386.5 565 S622 5150.0 386.5
326 G45 10130.0 386.5 386 G165 8930.0 386.5 446 G285 7730.0 386.5 506 S681 6330.0 511.5 566 S621 5130.0 511.5
327 G47 10110.0 511.5 387 G167 8910.0 511.5 447 G287 7710.0 511.5 507 S680 6310.0 386.5 567 S620 5110.0 386.5
328 G49 10090.0 386.5 388 G169 8890.0 386.5 448 G289 7690.0 386.5 508 S679 6290.0 511.5 568 S619 5090.0 511.5
329 G51 10070.0 511.5 389 G171 8870.0 511.5 449 G291 7670.0 511.5 509 S678 6270.0 386.5 569 S618 5070.0 386.5
330 G53 10050.0 386.5 390 G173 8850.0 386.5 450 G293 7650.0 386.5 510 S677 6250.0 511.5 570 S617 5050.0 511.5
331 G55 10030.0 511.5 391 G175 8830.0 511.5 451 G295 7630.0 511.5 511 S676 6230.0 386.5 571 S616 5030.0 386.5
332 G57 10010.0 386.5 392 G177 8810.0 386.5 452 G297 7610.0 386.5 512 S675 6210.0 511.5 572 S615 5010.0 511.5
333 G59 9990.0 511.5 393 G179 8790.0 511.5 453 G299 7590.0 511.5 513 S674 6190.0 386.5 573 S614 4990.0 386.5
334 G61 9970.0 386.5 394 G181 8770.0 386.5 454 G301 7570.0 386.5 514 S673 6170.0 511.5 574 S613 4970.0 511.5
335 G63 9950.0 511.5 395 G183 8750.0 511.5 455 G303 7550.0 511.5 515 S672 6150.0 386.5 575 S612 4950.0 386.5
336 G65 9930.0 386.5 396 G185 8730.0 386.5 456 G305 7530.0 386.5 516 S671 6130.0 511.5 576 S611 4930.0 511.5
337 G67 9910.0 511.5 397 G187 8710.0 511.5 457 G307 7510.0 511.5 517 S670 6110.0 386.5 577 S610 4910.0 386.5
338 G69 9890.0 386.5 398 G189 8690.0 386.5 458 G309 7490.0 386.5 518 S669 6090.0 511.5 578 S609 4890.0 511.5
339 G71 9870.0 511.5 399 G191 8670.0 511.5 459 G311 7470.0 511.5 519 S668 6070.0 386.5 579 S608 4870.0 386.5
340 G73 9850.0 386.5 400 G193 8650.0 386.5 460 G313 7450.0 386.5 520 S667 6050.0 511.5 580 S607 4850.0 511.5
341 G75 9830.0 511.5 401 G195 8630.0 511.5 461 G315 7430.0 511.5 521 S666 6030.0 386.5 581 S606 4830.0 386.5
342 G77 9810.0 386.5 402 G197 8610.0 386.5 462 G317 7410.0 386.5 522 S665 6010.0 511.5 582 S605 4810.0 511.5
343 G79 9790.0 511.5 403 G199 8590.0 511.5 463 G319 7390.0 511.5 523 S664 5990.0 386.5 583 S604 4790.0 386.5
344 G81 9770.0 386.5 404 G201 8570.0 386.5 464 VGLDMY2 7370.0 386.5 524 S663 5970.0 511.5 584 S603 4770.0 511.5
345 G83 9750.0 511.5 405 G203 8550.0 511.5 465 TESTO33 7350.0 511.5 525 S662 5950.0 386.5 585 S602 4750.0 386.5
346 G85 9730.0 386.5 406 G205 8530.0 386.5 466 TESTO34 7130.0 511.5 526 S661 5930.0 511.5 586 S601 4730.0 511.5
347 G87 9710.0 511.5 407 G207 8510.0 511.5 467 S720 7110.0 386.5 527 S660 5910.0 386.5 587 S600 4710.0 386.5
348 G89 9690.0 386.5 408 G209 8490.0 386.5 468 S719 7090.0 511.5 528 S659 5890.0 511.5 588 S599 4690.0 511.5
349 G91 9670.0 511.5 409 G211 8470.0 511.5 469 S718 7070.0 386.5 529 S658 5870.0 386.5 589 S598 4670.0 386.5
350 G93 9650.0 386.5 410 G213 8450.0 386.5 470 S717 7050.0 511.5 530 S657 5850.0 511.5 590 S597 4650.0 511.5
351 G95 9630.0 511.5 411 G215 8430.0 511.5 471 S716 7030.0 386.5 531 S656 5830.0 386.5 591 S596 4630.0 386.5
352 G97 9610.0 386.5 412 G217 8410.0 386.5 472 S715 7010.0 511.5 532 S655 5810.0 511.5 592 S595 4610.0 511.5
353 G99 9590.0 511.5 413 G219 8390.0 511.5 473 S714 6990.0 386.5 533 S654 5790.0 386.5 593 S594 4590.0 386.5
354 G101 9570.0 386.5 414 G221 8370.0 386.5 474 S713 6970.0 511.5 534 S653 5770.0 511.5 594 S593 4570.0 511.5
355 G103 9550.0 511.5 415 G223 8350.0 511.5 475 S712 6950.0 386.5 535 S652 5750.0 386.5 595 S592 4550.0 386.5
356 G105 9530.0 386.5 416 G225 8330.0 386.5 476 S711 6930.0 511.5 536 S651 5730.0 511.5 596 S591 4530.0 511.5
357 G107 9510.0 511.5 417 G227 8310.0 511.5 477 S710 6910.0 386.5 537 S650 5710.0 386.5 597 S590 4510.0 386.5
358 G109 9490.0 386.5 418 G229 8290.0 386.5 478 S709 6890.0 511.5 538 S649 5690.0 511.5 598 S589 4490.0 511.5
359 G111 9470.0 511.5 419 G231 8270.0 511.5 479 S708 6870.0 386.5 539 S648 5670.0 386.5 599 S588 4470.0 386.5
360 G113 9450.0 386.5 420 G233 8250.0 386.5 480 S707 6850.0 511.5 540 S647 5650.0 511.5 600 S587 4450.0 511.5

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 17 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
No. Name X Y No. Name X Y No. Name X Y No. Name X Y No. Name X Y
601 S586 4430.0 386.5 661 S526 3230.0 386.5 721 S466 2030.0 386.5 781 S406 830.0 386.5 841 S346 -370.0 386.5
602 S585 4410.0 511.5 662 S525 3210.0 511.5 722 S465 2010.0 511.5 782 S405 810.0 511.5 842 S345 -390.0 511.5
603 S584 4390.0 386.5 663 S524 3190.0 386.5 723 S464 1990.0 386.5 783 S404 790.0 386.5 843 S344 -410.0 386.5
604 S583 4370.0 511.5 664 S523 3170.0 511.5 724 S463 1970.0 511.5 784 S403 770.0 511.5 844 S343 -430.0 511.5
605 S582 4350.0 386.5 665 S522 3150.0 386.5 725 S462 1950.0 386.5 785 S402 750.0 386.5 845 S342 -450.0 386.5
606 S581 4330.0 511.5 666 S521 3130.0 511.5 726 S461 1930.0 511.5 786 S401 730.0 511.5 846 S341 -470.0 511.5
607 S580 4310.0 386.5 667 S520 3110.0 386.5 727 S460 1910.0 386.5 787 S400 710.0 386.5 847 S340 -490.0 386.5
608 S579 4290.0 511.5 668 S519 3090.0 511.5 728 S459 1890.0 511.5 788 S399 690.0 511.5 848 S339 -510.0 511.5
609 S578 4270.0 386.5 669 S518 3070.0 386.5 729 S458 1870.0 386.5 789 S398 670.0 386.5 849 S338 -530.0 386.5
610 S577 4250.0 511.5 670 S517 3050.0 511.5 730 S457 1850.0 511.5 790 S397 650.0 511.5 850 S337 -550.0 511.5
611 S576 4230.0 386.5 671 S516 3030.0 386.5 731 S456 1830.0 386.5 791 S396 630.0 386.5 851 S336 -570.0 386.5
612 S575 4210.0 511.5 672 S515 3010.0 511.5 732 S455 1810.0 511.5 792 S395 610.0 511.5 852 S335 -590.0 511.5
613 S574 4190.0 386.5 673 S514 2990.0 386.5 733 S454 1790.0 386.5 793 S394 590.0 386.5 853 S334 -610.0 386.5
614 S573 4170.0 511.5 674 S513 2970.0 511.5 734 S453 1770.0 511.5 794 S393 570.0 511.5 854 S333 -630.0 511.5
615 S572 4150.0 386.5 675 S512 2950.0 386.5 735 S452 1750.0 386.5 795 S392 550.0 386.5 855 S332 -650.0 386.5
616 S571 4130.0 511.5 676 S511 2930.0 511.5 736 S451 1730.0 511.5 796 S391 530.0 511.5 856 S331 -670.0 511.5
617 S570 4110.0 386.5 677 S510 2910.0 386.5 737 S450 1710.0 386.5 797 S390 510.0 386.5 857 S330 -690.0 386.5
618 S569 4090.0 511.5 678 S509 2890.0 511.5 738 S449 1690.0 511.5 798 S389 490.0 511.5 858 S329 -710.0 511.5
619 S568 4070.0 386.5 679 S508 2870.0 386.5 739 S448 1670.0 386.5 799 S388 470.0 386.5 859 S328 -730.0 386.5
620 S567 4050.0 511.5 680 S507 2850.0 511.5 740 S447 1650.0 511.5 800 S387 450.0 511.5 860 S327 -750.0 511.5
621 S566 4030.0 386.5 681 S506 2830.0 386.5 741 S446 1630.0 386.5 801 S386 430.0 386.5 861 S326 -770.0 386.5
622 S565 4010.0 511.5 682 S505 2810.0 511.5 742 S445 1610.0 511.5 802 S385 410.0 511.5 862 S325 -790.0 511.5
623 S564 3990.0 386.5 683 S504 2790.0 386.5 743 S444 1590.0 386.5 803 S384 390.0 386.5 863 S324 -810.0 386.5
624 S563 3970.0 511.5 684 S503 2770.0 511.5 744 S443 1570.0 511.5 804 S383 370.0 511.5 864 S323 -830.0 511.5
625 S562 3950.0 386.5 685 S502 2750.0 386.5 745 S442 1550.0 386.5 805 S382 350.0 386.5 865 S322 -850.0 386.5
626 S561 3930.0 511.5 686 S501 2730.0 511.5 746 S441 1530.0 511.5 806 S381 330.0 511.5 866 S321 -870.0 511.5
627 S560 3910.0 386.5 687 S500 2710.0 386.5 747 S440 1510.0 386.5 807 S380 310.0 386.5 867 S320 -890.0 386.5
628 S559 3890.0 511.5 688 S499 2690.0 511.5 748 S439 1490.0 511.5 808 S379 290.0 511.5 868 S319 -910.0 511.5
629 S558 3870.0 386.5 689 S498 2670.0 386.5 749 S438 1470.0 386.5 809 S378 270.0 386.5 869 S318 -930.0 386.5
630 S557 3850.0 511.5 690 S497 2650.0 511.5 750 S437 1450.0 511.5 810 S377 250.0 511.5 870 S317 -950.0 511.5
631 S556 3830.0 386.5 691 S496 2630.0 386.5 751 S436 1430.0 386.5 811 S376 230.0 386.5 871 S316 -970.0 386.5
632 S555 3810.0 511.5 692 S495 2610.0 511.5 752 S435 1410.0 511.5 812 S375 210.0 511.5 872 S315 -990.0 511.5
633 S554 3790.0 386.5 693 S494 2590.0 386.5 753 S434 1390.0 386.5 813 S374 190.0 386.5 873 S314 -1010.0 386.5
634 S553 3770.0 511.5 694 S493 2570.0 511.5 754 S433 1370.0 511.5 814 S373 170.0 511.5 874 S313 -1030.0 511.5
635 S552 3750.0 386.5 695 S492 2550.0 386.5 755 S432 1350.0 386.5 815 S372 150.0 386.5 875 S312 -1050.0 386.5
636 S551 3730.0 511.5 696 S491 2530.0 511.5 756 S431 1330.0 511.5 816 S371 130.0 511.5 876 S311 -1070.0 511.5
637 S550 3710.0 386.5 697 S490 2510.0 386.5 757 S430 1310.0 386.5 817 S370 110.0 386.5 877 S310 -1090.0 386.5
638 S549 3690.0 511.5 698 S489 2490.0 511.5 758 S429 1290.0 511.5 818 S369 90.0 511.5 878 S309 -1110.0 511.5
639 S548 3670.0 386.5 699 S488 2470.0 386.5 759 S428 1270.0 386.5 819 S368 70.0 386.5 879 S308 -1130.0 386.5
640 S547 3650.0 511.5 700 S487 2450.0 511.5 760 S427 1250.0 511.5 820 S367 50.0 511.5 880 S307 -1150.0 511.5
641 S546 3630.0 386.5 701 S486 2430.0 386.5 761 S426 1230.0 386.5 821 S366 30.0 386.5 881 S306 -1170.0 386.5
642 S545 3610.0 511.5 702 S485 2410.0 511.5 762 S425 1210.0 511.5 822 S365 10.0 511.5 882 S305 -1190.0 511.5
643 S544 3590.0 386.5 703 S484 2390.0 386.5 763 S424 1190.0 386.5 823 S364 -10.0 386.5 883 S304 -1210.0 386.5
644 S543 3570.0 511.5 704 S483 2370.0 511.5 764 S423 1170.0 511.5 824 S363 -30.0 511.5 884 S303 -1230.0 511.5
645 S542 3550.0 386.5 705 S482 2350.0 386.5 765 S422 1150.0 386.5 825 S362 -50.0 386.5 885 S302 -1250.0 386.5
646 S541 3530.0 511.5 706 S481 2330.0 511.5 766 S421 1130.0 511.5 826 S361 -70.0 511.5 886 S301 -1270.0 511.5
647 S540 3510.0 386.5 707 S480 2310.0 386.5 767 S420 1110.0 386.5 827 S360 -90.0 386.5 887 S300 -1290.0 386.5
648 S539 3490.0 511.5 708 S479 2290.0 511.5 768 S419 1090.0 511.5 828 S359 -110.0 511.5 888 S299 -1310.0 511.5
649 S538 3470.0 386.5 709 S478 2270.0 386.5 769 S418 1070.0 386.5 829 S358 -130.0 386.5 889 S298 -1330.0 386.5
650 S537 3450.0 511.5 710 S477 2250.0 511.5 770 S417 1050.0 511.5 830 S357 -150.0 511.5 890 S297 -1350.0 511.5
651 S536 3430.0 386.5 711 S476 2230.0 386.5 771 S416 1030.0 386.5 831 S356 -170.0 386.5 891 S296 -1370.0 386.5
652 S535 3410.0 511.5 712 S475 2210.0 511.5 772 S415 1010.0 511.5 832 S355 -190.0 511.5 892 S295 -1390.0 511.5
653 S534 3390.0 386.5 713 S474 2190.0 386.5 773 S414 990.0 386.5 833 S354 -210.0 386.5 893 S294 -1410.0 386.5
654 S533 3370.0 511.5 714 S473 2170.0 511.5 774 S413 970.0 511.5 834 S353 -230.0 511.5 894 S293 -1430.0 511.5
655 S532 3350.0 386.5 715 S472 2150.0 386.5 775 S412 950.0 386.5 835 S352 -250.0 386.5 895 S292 -1450.0 386.5
656 S531 3330.0 511.5 716 S471 2130.0 511.5 776 S411 930.0 511.5 836 S351 -270.0 511.5 896 S291 -1470.0 511.5
657 S530 3310.0 386.5 717 S470 2110.0 386.5 777 S410 910.0 386.5 837 S350 -290.0 386.5 897 S290 -1490.0 386.5
658 S529 3290.0 511.5 718 S469 2090.0 511.5 778 S409 890.0 511.5 838 S349 -310.0 511.5 898 S289 -1510.0 511.5
659 S720 3270.0 386.5 719 S468 2070.0 386.5 779 S408 870.0 386.5 839 S348 -330.0 386.5 899 S288 -1530.0 386.5
660 S527 3250.0 511.5 720 S467 2050.0 511.5 780 S407 850.0 511.5 840 S347 -350.0 511.5 900 S287 -1550.0 511.5

No. Name X Y No. Name X Y No. Name X Y No. Name X Y No. Name X Y
901 S286 -1570.0 386.5 961 S226 -2770.0 386.5 1021 S166 -3970.0 386.5 1081 S106 -5170.0 386.5 1141 S46 -6370.0 386.5
902 S285 -1590.0 511.5 962 S225 -2790.0 511.5 1022 S165 -3990.0 511.5 1082 S105 -5190.0 511.5 1142 S45 -6390.0 511.5
903 S284 -1610.0 386.5 963 S224 -2810.0 386.5 1023 S164 -4010.0 386.5 1083 S104 -5210.0 386.5 1143 S44 -6410.0 386.5
904 S283 -1630.0 511.5 964 S223 -2830.0 511.5 1024 S163 -4030.0 511.5 1084 S103 -5230.0 511.5 1144 S43 -6430.0 511.5
905 S282 -1650.0 386.5 965 S222 -2850.0 386.5 1025 S162 -4050.0 386.5 1085 S102 -5250.0 386.5 1145 S42 -6450.0 386.5
906 S281 -1670.0 511.5 966 S221 -2870.0 511.5 1026 S161 -4070.0 511.5 1086 S101 -5270.0 511.5 1146 S41 -6470.0 511.5
907 S280 -1690.0 386.5 967 S220 -2890.0 386.5 1027 S160 -4090.0 386.5 1087 S100 -5290.0 386.5 1147 S40 -6490.0 386.5
908 S279 -1710.0 511.5 968 S219 -2910.0 511.5 1028 S159 -4110.0 511.5 1088 S99 -5310.0 511.5 1148 S39 -6510.0 511.5
909 S278 -1730.0 386.5 969 S218 -2930.0 386.5 1029 S158 -4130.0 386.5 1089 S98 -5330.0 386.5 1149 S38 -6530.0 386.5
910 S277 -1750.0 511.5 970 S217 -2950.0 511.5 1030 S157 -4150.0 511.5 1090 S97 -5350.0 511.5 1150 S37 -6550.0 511.5
911 S276 -1770.0 386.5 971 S216 -2970.0 386.5 1031 S156 -4170.0 386.5 1091 S96 -5370.0 386.5 1151 S36 -6570.0 386.5
912 S275 -1790.0 511.5 972 S215 -2990.0 511.5 1032 S155 -4190.0 511.5 1092 S95 -5390.0 511.5 1152 S35 -6590.0 511.5
913 S274 -1810.0 386.5 973 S214 -3010.0 386.5 1033 S154 -4210.0 386.5 1093 S94 -5410.0 386.5 1153 S34 -6610.0 386.5
914 S273 -1830.0 511.5 974 S213 -3030.0 511.5 1034 S153 -4230.0 511.5 1094 S93 -5430.0 511.5 1154 S33 -6630.0 511.5
915 S272 -1850.0 386.5 975 S212 -3050.0 386.5 1035 S152 -4250.0 386.5 1095 S92 -5450.0 386.5 1155 S32 -6650.0 386.5
916 S271 -1870.0 511.5 976 S211 -3070.0 511.5 1036 S151 -4270.0 511.5 1096 S91 -5470.0 511.5 1156 S31 -6670.0 511.5
917 S270 -1890.0 386.5 977 S210 -3090.0 386.5 1037 S150 -4290.0 386.5 1097 S90 -5490.0 386.5 1157 S30 -6690.0 386.5
918 S269 -1910.0 511.5 978 S209 -3110.0 511.5 1038 S149 -4310.0 511.5 1098 S89 -5510.0 511.5 1158 S29 -6710.0 511.5
919 S268 -1930.0 386.5 979 S208 -3130.0 386.5 1039 S148 -4330.0 386.5 1099 S88 -5530.0 386.5 1159 S28 -6730.0 386.5
920 S267 -1950.0 511.5 980 S207 -3150.0 511.5 1040 S147 -4350.0 511.5 1100 S87 -5550.0 511.5 1160 S27 -6750.0 511.5
921 S266 -1970.0 386.5 981 S206 -3170.0 386.5 1041 S146 -4370.0 386.5 1101 S86 -5570.0 386.5 1161 S26 -6770.0 386.5
922 S265 -1990.0 511.5 982 S205 -3190.0 511.5 1042 S145 -4390.0 511.5 1102 S85 -5590.0 511.5 1162 S25 -6790.0 511.5
923 S264 -2010.0 386.5 983 S204 -3210.0 386.5 1043 S144 -4410.0 386.5 1103 S84 -5610.0 386.5 1163 S24 -6810.0 386.5
924 S263 -2030.0 511.5 984 S203 -3230.0 511.5 1044 S143 -4430.0 511.5 1104 S83 -5630.0 511.5 1164 S23 -6830.0 511.5
925 S262 -2050.0 386.5 985 S202 -3250.0 386.5 1045 S142 -4450.0 386.5 1105 S82 -5650.0 386.5 1165 S22 -6850.0 386.5
926 S261 -2070.0 511.5 986 S201 -3270.0 511.5 1046 S141 -4470.0 511.5 1106 S81 -5670.0 511.5 1166 S21 -6870.0 511.5
927 S260 -2090.0 386.5 987 S200 -3290.0 386.5 1047 S140 -4490.0 386.5 1107 S80 -5690.0 386.5 1167 S20 -6890.0 386.5
928 S259 -2110.0 511.5 988 S199 -3310.0 511.5 1048 S139 -4510.0 511.5 1108 S79 -5710.0 511.5 1168 S19 -6910.0 511.5
929 S258 -2130.0 386.5 989 S198 -3330.0 386.5 1049 S138 -4530.0 386.5 1109 S78 -5730.0 386.5 1169 S18 -6930.0 386.5
930 S257 -2150.0 511.5 990 S197 -3350.0 511.5 1050 S137 -4550.0 511.5 1110 S77 -5750.0 511.5 1170 S17 -6950.0 511.5
931 S256 -2170.0 386.5 991 S196 -3370.0 386.5 1051 S136 -4570.0 386.5 1111 S76 -5770.0 386.5 1171 S16 -6970.0 386.5
932 S255 -2190.0 511.5 992 S195 -3390.0 511.5 1052 S135 -4590.0 511.5 1112 S75 -5790.0 511.5 1172 S15 -6990.0 511.5
933 S254 -2210.0 386.5 993 S194 -3410.0 386.5 1053 S134 -4610.0 386.5 1113 S74 -5810.0 386.5 1173 S14 -7010.0 386.5
934 S253 -2230.0 511.5 994 S193 -3430.0 511.5 1054 S133 -4630.0 511.5 1114 S73 -5830.0 511.5 1174 S13 -7030.0 511.5
935 S252 -2250.0 386.5 995 S192 -3450.0 386.5 1055 S132 -4650.0 386.5 1115 S72 -5850.0 386.5 1175 S12 -7050.0 386.5
936 S251 -2270.0 511.5 996 S191 -3470.0 511.5 1056 S131 -4670.0 511.5 1116 S71 -5870.0 511.5 1176 S11 -7070.0 511.5
937 S250 -2290.0 386.5 997 S190 -3490.0 386.5 1057 S130 -4690.0 386.5 1117 S70 -5890.0 386.5 1177 S10 -7090.0 386.5
938 S249 -2310.0 511.5 998 S189 -3510.0 511.5 1058 S129 -4710.0 511.5 1118 S69 -5910.0 511.5 1178 S9 -7110.0 511.5
939 S248 -2330.0 386.5 999 S188 -3530.0 386.5 1059 S128 -4730.0 386.5 1119 S68 -5930.0 386.5 1179 S8 -7130.0 386.5
940 S247 -2350.0 511.5 1000 S187 -3550.0 511.5 1060 S127 -4750.0 511.5 1120 S67 -5950.0 511.5 1180 S7 -7150.0 511.5
941 S246 -2370.0 386.5 1001 S186 -3570.0 386.5 1061 S126 -4770.0 386.5 1121 S66 -5970.0 386.5 1181 S6 -7170.0 386.5
942 S245 -2390.0 511.5 1002 S185 -3590.0 511.5 1062 S125 -4790.0 511.5 1122 S65 -5990.0 511.5 1182 S5 -7190.0 511.5
943 S244 -2410.0 386.5 1003 S184 -3610.0 386.5 1063 S124 -4810.0 386.5 1123 S64 -6010.0 386.5 1183 S4 -7210.0 386.5
944 S243 -2430.0 511.5 1004 S183 -3630.0 511.5 1064 S123 -4830.0 511.5 1124 S63 -6030.0 511.5 1184 S3 -7230.0 511.5
945 S242 -2450.0 386.5 1005 S182 -3650.0 386.5 1065 S122 -4850.0 386.5 1125 S62 -6050.0 386.5 1185 S2 -7250.0 386.5
946 S241 -2470.0 511.5 1006 S181 -3670.0 511.5 1066 S121 -4870.0 511.5 1126 S61 -6070.0 511.5 1186 S1 -7270.0 511.5
947 S240 -2490.0 386.5 1007 S180 -3690.0 386.5 1067 S120 -4890.0 386.5 1127 S60 -6090.0 386.5 1187 TESTO35 -7290.0 386.5
948 S239 -2510.0 511.5 1008 S179 -3710.0 511.5 1068 S119 -4910.0 511.5 1128 S59 -6110.0 511.5 1188 TESTO36 -7350.0 511.5
949 S238 -2530.0 386.5 1009 S178 -3730.0 386.5 1069 S118 -4930.0 386.5 1129 S58 -6130.0 386.5 1189 VGLDMY3 -7370.0 386.5
950 S237 -2550.0 511.5 1010 S177 -3750.0 511.5 1070 S117 -4950.0 511.5 1130 S57 -6150.0 511.5 1190 G320 -7390.0 511.5
951 S236 -2570.0 386.5 1011 S176 -3770.0 386.5 1071 S116 -4970.0 386.5 1131 S56 -6170.0 386.5 1191 G318 -7410.0 386.5
952 S235 -2590.0 511.5 1012 S175 -3790.0 511.5 1072 S115 -4990.0 511.5 1132 S55 -6190.0 511.5 1192 G316 -7430.0 511.5
953 S234 -2610.0 386.5 1013 S174 -3810.0 386.5 1073 S114 -5010.0 386.5 1133 S54 -6210.0 386.5 1193 G314 -7450.0 386.5
954 S233 -2630.0 511.5 1014 S173 -3830.0 511.5 1074 S113 -5030.0 511.5 1134 S53 -6230.0 511.5 1194 G312 -7470.0 511.5
955 S232 -2650.0 386.5 1015 S172 -3850.0 386.5 1075 S112 -5050.0 386.5 1135 S52 -6250.0 386.5 1195 G310 -7490.0 386.5
956 S231 -2670.0 511.5 1016 S171 -3870.0 511.5 1076 S111 -5070.0 511.5 1136 S51 -6270.0 511.5 1196 G308 -7510.0 511.5
957 S230 -2690.0 386.5 1017 S170 -3890.0 386.5 1077 S110 -5090.0 386.5 1137 S50 -6290.0 386.5 1197 G306 -7530.0 386.5
958 S229 -2710.0 511.5 1018 S169 -3910.0 511.5 1078 S109 -5110.0 511.5 1138 S49 -6310.0 511.5 1198 G304 -7550.0 511.5
959 S228 -2730.0 386.5 1019 S168 -3930.0 386.5 1079 S108 -5130.0 386.5 1139 S48 -6330.0 386.5 1199 G302 -7570.0 386.5
960 S227 -2750.0 511.5 1020 S167 -3950.0 511.5 1080 S107 -5150.0 511.5 1140 S47 -6350.0 511.5 1200 G300 -7590.0 511.5

No. Name X Y No. Name X Y No. Name X Y

1201 G298 -7610.0 386.5 1261 G178 -8810.0 386.5 1321 G58 -10010.0 386.5
1202 G296 -7630.0 511.5 1262 G176 -8830.0 511.5 1322 G56 -10030.0 511.5
1203 G294 -7650.0 386.5 1263 G174 -8850.0 386.5 1323 G54 -10050.0 386.5
1204 G292 -7670.0 511.5 1264 G172 -8870.0 511.5 1324 G52 -10070.0 511.5
1205 G290 -7690.0 386.5 1265 G170 -8890.0 386.5 1325 G50 -10090.0 386.5
1206 G288 -7710.0 511.5 1266 G168 -8910.0 511.5 1326 G48 -10110.0 511.5
1207 G286 -7730.0 386.5 1267 G166 -8930.0 386.5 1327 G46 -10130.0 386.5
1208 G284 -7750.0 511.5 1268 G164 -8950.0 511.5 1328 G44 -10150.0 511.5
1209 G282 -7770.0 386.5 1269 G162 -8970.0 386.5 1329 G42 -10170.0 386.5
1210 G280 -7790.0 511.5 1270 G160 -8990.0 511.5 1330 G40 -10190.0 511.5
1211 G278 -7810.0 386.5 1271 G158 -9010.0 386.5 1331 G38 -10210.0 386.5
1212 G276 -7830.0 511.5 1272 G156 -9030.0 511.5 1332 G36 -10230.0 511.5
1213 G274 -7850.0 386.5 1273 G154 -9050.0 386.5 1333 G34 -10250.0 386.5
1214 G272 -7870.0 511.5 1274 G152 -9070.0 511.5 1334 G32 -10270.0 511.5
1215 G270 -7890.0 386.5 1275 G150 -9090.0 386.5 1335 G30 -10290.0 386.5
1216 G268 -7910.0 511.5 1276 G148 -9110.0 511.5 1336 G28 -10310.0 511.5
1217 G266 -7930.0 386.5 1277 G146 -9130.0 386.5 1337 G26 -10330.0 386.5
1218 G264 -7950.0 511.5 1278 G144 -9150.0 511.5 1338 G24 -10350.0 511.5
1219 G262 -7970.0 386.5 1279 G142 -9170.0 386.5 1339 G22 -10370.0 386.5
1220 G260 -7990.0 511.5 1280 G140 -9190.0 511.5 1340 G20 -10390.0 511.5
1221 G258 -8010.0 386.5 1281 G138 -9210.0 386.5 1341 G18 -10410.0 386.5
1222 G256 -8030.0 511.5 1282 G136 -9230.0 511.5 1342 G16 -10430.0 511.5
1223 G254 -8050.0 386.5 1283 G134 -9250.0 386.5 1343 G14 -10450.0 386.5
1224 G252 -8070.0 511.5 1284 G132 -9270.0 511.5 1344 G12 -10470.0 511.5
1225 G250 -8090.0 386.5 1285 G130 -9290.0 386.5 1345 G10 -10490.0 386.5
1226 G248 -8110.0 511.5 1286 G128 -9310.0 511.5 1346 G8 -10510.0 511.5
1227 G246 -8130.0 386.5 1287 G126 -9330.0 386.5 1347 G6 -10530.0 386.5
1228 G244 -8150.0 511.5 1288 G124 -9350.0 511.5 1348 G4 -10550.0 511.5
1229 G242 -8170.0 386.5 1289 G122 -9370.0 386.5 1349 G2 -10570.0 386.5
1230 G240 -8190.0 511.5 1290 G120 -9390.0 511.5 1350 VGLDMY4 -10590.0 511.5
1231 G238 -8210.0 386.5 1291 G118 -9410.0 386.5 1351 DUMMYR9 -10610.0 386.5
1232 G236 -8230.0 511.5 1292 G116 -9430.0 511.5 1352 DUMMYR10 -10630.0 511.5
1233 G234 -8250.0 386.5 1293 G114 -9450.0 386.5 1353 TESTO37 -10650.0 386.5
1234 G232 -8270.0 511.5 1294 G112 -9470.0 511.5 1354 TESTO38 -10670.0 511.5
1235 G230 -8290.0 386.5 1295 G110 -9490.0 386.5
1236 G228 -8310.0 511.5 1296 G108 -9510.0 511.5
1237 G226 -8330.0 386.5 1297 G106 -9530.0 386.5
1238 G224 -8350.0 511.5 1298 G104 -9550.0 511.5
1239 G222 -8370.0 386.5 1299 G102 -9570.0 386.5
1240 G220 -8390.0 511.5 1300 G100 -9590.0 511.5
1241 G218 -8410.0 386.5 1301 G98 -9610.0 386.5
1242 G216 -8430.0 511.5 1302 G96 -9630.0 511.5
1243 G214 -8450.0 386.5 1303 G94 -9650.0 386.5
1244 G212 -8470.0 511.5 1304 G92 -9670.0 511.5
1245 G210 -8490.0 386.5 1305 G90 -9690.0 386.5
1246 G208 -8510.0 511.5 1306 G88 -9710.0 511.5
1247 G206 -8530.0 386.5 1307 G86 -9730.0 386.5
1248 G204 -8550.0 511.5 1308 G84 -9750.0 511.5
1249 G202 -8570.0 386.5 1309 G82 -9770.0 386.5
1250 G200 -8590.0 511.5 1310 G80 -9790.0 511.5
1251 G198 -8610.0 386.5 1311 G78 -9810.0 386.5
1252 G196 -8630.0 511.5 1312 G76 -9830.0 511.5
1253 G194 -8650.0 386.5 1313 G74 -9850.0 386.5
1254 G192 -8670.0 511.5 1314 G72 -9870.0 511.5
1255 G190 -8690.0 386.5 1315 G70 -9890.0 386.5
1256 G188 -8710.0 511.5 1316 G68 -9910.0 511.5
1257 G186 -8730.0 386.5 1317 G66 -9930.0 386.5
1258 G184 -8750.0 511.5 1318 G64 -9950.0 511.5 Alignment mark X Y
1259 G182 -8770.0 386.5 1319 G62 -9970.0 386.5 1-a -10613.0 -468.0
1260 G180 -8790.0 511.5 1320 G60 -9990.0 511.5 1-b 10613.0 -468.0

20 21

S1 ~ S720
G1 ~ G320

100
DUMMY
DUMMYR

25
TESTO
VGLDMY

100
(No. 299 ~ 1354) Unit: um

50 20 50

I/O Pads

Pad Pump

80
(No. 1 ~ 298)

MPU System Interface

ILI9320 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit
parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins.

ILI9320 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register
(RDR). The IR is the register to store index information from control registers and the internal GRAM. The
WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The
RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the
internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal
operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data
bus when the ILI9320 read the first data from the internal GRAM. Valid data are read out after the ILI9320
performs the second read operation.
Registers are written consecutively as the register execution time except starting oscillator takes 0 clock
cycle.

Registers selection by system interface (8-/9-/16-/18-bit bus width) I80

Function RS nWR nRD
Write an index to IR register 0 0 1
Read an internal status 0 1 0
Write to control registers or the internal GRAM by WDR register. 1 0 1
Read from the internal GRAM by RDR register. 1 1 0

Registers selection by the SPI system interface

Function R/W RS
Write an index to IR register 0 0
Read an internal status 1 0
Write to control registers or the internal GRAM by WDR register. 0 1
Read from the internal GRAM by RDR register. 1 1

Parallel RGB Interface

ILI9320 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving
picture. When the RGB interface is selected, display operations are synchronized with externally supplied
signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization
with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while
updating display data.
In VSYNC interface mode, the display operation is synchronized with the internal clock except frame
synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the
internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data
to the internal RAM. For details, see the “External Display Interface” section. The ILI9320 allows for switching
between the external display interface and the system interface by instruction so that the optimum interface is

Bit Operation
The ILI9320 supports a write data mask function for selectively writing data to the internal RAM in units of bits
and a logical/compare operation to write data to the GRAM only when a condition is met as a result of
comparing the data and the compare register bits. For details, see “Graphics Operation Functions”.

Address Counter (AC)

The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a
RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing
data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window
address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.

Graphics RAM (GRAM)

GRAM is graphics RAM storing bit-pattern data of 172,820 (240 x 320x 18/8) bytes with 18 bits per pixel.

Grayscale Voltage Generating Circuit

The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data
set in the γ-correction register to display in 262,144 colors. For details, see the “γ-Correction Register”
section.

Timing Controller
The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM.
The timing for the display operation such as RAM read operation and the timing for the internal operation such
as access from the MPU are generated in the way not to interfere each other.

Oscillator (OSC)
ILI9320 generates RC oscillation with an external oscillation resistor placed between the OSC1 and OSC2
pins. The oscillation frequency is changed according to the value of an external resistor. Adjust the oscillation
frequency in accordance to the operating voltage or the frame frequency. An operating clock can be input
externally. During standby mode, RC oscillation is halted to reduce power consumption. For details, see
“Oscillator”.

LCD Driver Circuit

The LCD driver circuit of ILI9320 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate
driver (G1~G320). Display pattern data are latched when the 720th bit data are input. The latched data control

LCD Driver Power Supply Circuit

The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for
driving an LCD.

7.1. Interface Specifications

ILI9320 has the system interface to read/write the control registers and display graphics memory (GRAM),
and the RGB Input Interface for displaying a moving picture. User can select an optimum interface to display
the moving or still picture with efficient data transfer. All display data are stored in the GRAM to reduce the
data transfer efforts and only the updating data is necessary to be transferred. User can only update a
sub-range of GRAM by using the window address function.

ILI9320 also has the RGB interface and VSYNC interface to transfer the display data without flicker the
moving picture on the screen. In RGB interface mode, the display data is written into the GRAM through the
control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:0].

In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal
(VSYNC). The VSYNC interface mode enables to display the moving picture display through the system
interface. In this case, there are some constraints of speed and method to write data to the internal RAM.

ILI9320 operates in one of the following 4 modes. The display mode can be switched by the control register.
When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and
VSYNC interfaces.

Operation Mode RAM Access Setting Display Operation Mode

(RM) (DM[1:0])
Internal operating clock only System interface Internal operating clock
(Displaying still pictures) (RM = 0) (DM[1:0] = 00)
RGB interface (1) RGB interface RGB interface
(Displaying moving pictures) (RM = 1) (DM[1:0] = 01)
RGB interface (2) System interface RGB interface
(Rewriting still pictures while (RM = 0) (DM[1:0] = 01)
displaying moving pictures)
VSYNC interface System interface VSYNC interface
(Displaying moving pictures) (RM = 0) (DM[1:0] = 01)
Note 1) Registers are set only via the system interface.

Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously.

nCS
System RS
Interface nWR
nRD
DB[17:0]
18/16/6
System ILI9320

ENABLE
RGB VSYNC
Interface HSYNC
DOTCLK

Figure1 System Interface and RGB Interface connection

7.2. Input Interfaces

The following are the system interfaces available with the ILI9320. The interface is selected by setting the
IM[3:0] pins. The system interface is used for setting registers and GRAM access.

IM3 IM2 IM1 IM0/ID Interface Mode DB Pin

0 0 0 0 Setting invalid
0 0 0 1 Setting invalid
0 0 1 0 i80-system 16-bit interface DB[17:10], DB[8:1]
0 0 1 1 i80-system 8-bit interface DB[17:10]
0 1 0 ID Serial Peripheral Interface (SPI) SDI, SDO (DB[1:0])
0 1 1 * Setting invalid
1 0 0 0 Setting invalid
1 0 0 1 Setting invalid
1 0 1 0 i80-system18-bit interface DB[17:0]
1 0 1 1 i80-system 9-bit interface DB[17:9]
1 1 * * Setting invalid

nCS nCS
A2 RS
System nWR nWR
nRD nRD
D[31:0] DB[17:0]
18

18-bit System Interface (262K colors) TRI=0, DFM[1:0]=00

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write Data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Figure2 18-bit System Interface Data Format

nCS nCS
A1 RS
System nWR nWR
nRD nRD
D[15:0] DB[17:10], DB[8:1]
16

TRI DFM 16-bit MPU System Interface Data Format

system 16-bit interface (1 transfers/pixel) 65,536 colors

1st Transfer
0 * DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 16-bit interface (2 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer

1 0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 16-bit interface (2 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer

1 1 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Figure3 16-bit System Interface Data Format

nCS nCS
A1 RS
System nWR nWR
nRD nRD
D[8:0] DB[17:9]
9

9-bit System Interface (262K colors) TRI=0, DFM[1:0]=00

1st Transfer (Upper bits) 2nd Transfer (Lower bits)
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9

Write Data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Figure4 9-bit System Interface Data Format

7.2.4. i80/8-bit System Interface

The i80/8-bit system interface is selected by setting the IM[3:0] as “0011” and the DB17~DB10 pins are used
to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not
used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (8 bits)
and lower byte, and the upper byte is transferred first. The written data is expanded into 18 bits internally (see
the figure below) and then written into GRAM. The unused DB[9:0] pins must be tied to either Vcc or AGND.

system 8-bit interface (2 transfers/pixel) 65,536 colors

1st Transfer 2nd Transfer

0 * DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 8-bit interface (3 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer 3rd Transfer

1 0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 8-bit interface (3 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer 3rd Transfer

1 1 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Figure5 8-bit System Interface Data Format

Data transfer synchronization in 8/9-bit bus interface mode

ILI9320 supports a data transfer synchronization function to reset upper and lower counters which count the
transfers numbers of upper and lower byte in 8/9-bit interface mode. If a mismatch arises in the numbers of
transfers between the upper and lower byte counters due to noise and so on, the “00”h register is written 4
times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of
upper byte. This synchronization function can effectively prevent display error if the upper/lower counters are
periodically reset.

nWR

Upper/
DB[17:9] “00”h “00”h “00”h “00”h Upper Lower
Lower

8-/9-bit transfer
synchronization

Figure6 Data Transfer Synchronization in 8/9-bit System Interface

7.3. Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as “010x” level. The chip select pin

The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge
of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information
are also included in the start byte. When the start byte is matched, the subsequent data is received by
ILI9320.

The seventh bit of start byte is RS bit. When RS = “0”, either index write operation or status read operation is
executed. When RS = “1”, either register write operation or RAM read/write operation is executed. The eighth
bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is
“0” and read back when the R/W bit is “1”.

After receiving the start byte, ILI9320 starts to transfer or receive the data in unit of byte and the data transfer
starts from the MSB bit. All the registers of the ILI9320 are 16-bit format and receive the first and the second
byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes
dummy read is necessary and the valid data starts from 6th byte of read back data.

Start Byte Format

Transferred bits S 1 2 3 4 5 6 7 8
Start byte format Transfer start Device ID code RS R/W
0 1 1 1 0 ID 1/0 1/0
Note: ID bit is selected by setting the IM0/ID pin.

RS and R/W Bit Function

RS R/W Function
0 0 Set an index register
0 1 Read a status
1 0 Write a register or GRAM data
1 1 Read a register or GRAM data

Serial Peripheral Interface for register access

D D D D D D D D D D D D D D D D
SPI Input Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB
Register Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Serial Peripheral Interface 65K colors

D D D D D D D D D D D D D D D D
Input Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Write Data Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GRAM Data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB mapping

Figure 7 Data Format of SPI Interface

nCS
(Input)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCL
(Input)

SDI 0 1 1 1 0 ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

(Input)

Start Byte Index register, registers setting, and GRAM write

SDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(Output)

Status, registers read and GRAM read

(b) Consecutive data transmission through SPI

Start
nCS
(Input)

1 8 9 16 17 24 25 32
SCL
(Input)

SDI Register 1 Register 1 Register 2 Register 2

Start Byte
(Input) upper eight bits lower eight bits upper eight bits lower eight bits

Note: The first byte after the start byte is always the upper eight bits .
Register 1
execution time

(c) GRAM data read transmission

Start End

nCS
(Input)

SCL
(Input)

SDI Start Byte

(Input) RS=1, RW=1

SDO Dummy Dummy Dummy Dummy Dummy RAM read RAM read
(Output) read 1 read 2 read 3 read 4 read 5 upper byte lower byte
Note: Five bytes of invalid dummy data read after the start byte .

(d) Status/registers read transmission

Start End

nCS
(Input)

1 8 9 16 17 24
SCL
(Input)

SDI
Start Byte
(Input)

SDO Register 1 Register 1

(Output) upper eight bits lower eight bits
Note: One byte of invalid dummy data read after the start byte .

Figure8 Data transmission through serial peripheral interface (SPI)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCL
(Input)

SDI 0 1 1 1 0 ID RS RW D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(Input)

Start Byte GRAM data write

SDO
D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(Output)

GRAM data read

(f) GRAM data write transmission

Start End

nCS
(Input)

SCL
(Input)

SDI RAM data 1 RAM data 1 RAM data 1 RAM data 2 RAM data 2 RAM data 2
Start Byte
(Input) 1st transfer 2nd transfer 3rd transfer 1st transfer 2nd transfer 3rd transfer

SDO
(Output)
GRAM Data (1) GRAM Data (2)
Note: Five bytes of invalid dummy data read after the start byte. execution time execution time

(g) GRAM data read transmission

Start End

nCS
(Input)

SCL
(Input)

SDI Start Byte

(Input) RS=1, RW=1

SDO Dummy Dummy Dummy Dummy Dummy RAM read RAM read RAM read
(Output) read 1 read 2 read 3 read 4 read 5 1st byte 2nd byte 3rd byte
Note: Five bytes of invalid dummy data read after the start byte.

RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10.

Figure9 Data transmission through serial peripheral interface (SPI), TRI=”1” and DFM=”10”)

VSYNC

MPU nCS
RS
nWR
DB[17:0]

Figure10 Data transmission through VSYNC interface)

In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the
frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize
total data transfer required for moving picture display.

VSYNC
Rewriting Rewriting
Write data to RAM
screen data screen data
through system
interface
Display operation
synchronized with
internal clocks

Figure11 Moving picture data transmission through VSYNC interface

VSYNC RAM
Write
Display
Back porch (14 lines)
operation

Display
(320 lines)

Front porch (2 lines)

Black period

Figure12 Operation through VSYNC Interface

The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system
interface, which are calculated from the following formula.

Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch
(BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.

320 x DisplayLines (NL)

Minimum RAM write speed (HZ)
[(BackPorch(BP)+DisplayLines(NL) - margins] x 16 (clocks) x 1/fosc

Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling
edge of VSYNC until the start of RAM write operation must also be taken into account.

An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as
below.
[Example]
Display size: 240 RGB × 320 lines
Lines: 320 lines (NL = 1000111)
Back porch: 14 lines (BP = 1110)
Front porch: 2 lines (FP = 0010)
Frame frequency: 60 Hz
Frequency fluctuation: 10%

Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) ≒ 394KHz

Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 – 2)lines x 16clocks] ≒ 5.7 MHz

The above theoretical value is calculated based on the premise that the ILI9320 starts to write data into the
internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical
display line and the GRAM line address where data writing operation is performed. The GRAM write speed of
5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9320 starts to display
the GRAM data on the screen and enable to rewrite the entire screen without flicker.

Notes in using the VSYNC interface

1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into
consideration.
2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than
the scan period of an entire display.
3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface mode or
inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame.
4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode
and set the AM bit to “0” to transfer display data.

System Interface Mode to VSYNC interface mode VSYNC interface mode to System Interface Mode

Opeartion through
System Interface VSYNC interface

Set DM[1:0]=00, RM=0 Display operation in

Set HWM=1, AM=0
for system interface mode synchronization with
Display operation in VSYNC
synchronization with
Set GRAM Address internal clocks DM[1:0], RM become
enable after completion
of displaying 1 frame
Wait more than 1 frame
Set DM[1:0]=10, RM=0
for VSYNC interface mode Display operation in
DM[1:0], RM become synchronization with
enable after completion internal clocks
of displaying 1 frame System Interface
Set index register to R22h

Note: input VSYNC for more than 1 frame

period after setting the DM, RM register.
Wait more than 1 frame

Display operation in
synchronization with
Write data to GRAM VSYNC
through VSYNC interface

Opeartion through
VSYNC interface

Figure13 Transition flow between VSYNC and internal clock operation modes

RIM1 RIM0 RGB Interface DB pins

0 0 18-bit RGB Interface DB[17:0]
0 1 16-bit RGB Interface DB[17:13], DB[11:1]
1 0 6-bit RGB Interface DB[17:12]
1 1 Setting prohibited

18-bit RGB Interface (262K colors)

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write Data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

16-bit RGB Interface (65K colors)

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

Write Data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Register 17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

6-bit RGB Interface (262K colors)

1st Transfer 2nd Transfer 3rd Transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

Write Data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Figure14 RGB Interface Data Format

Back porch
period (BP[3:0])

RAM data display area

Display period
Moving picture (NL[4:0]
display area

Front porch
period (FP[3:0])

HSYNC Note 1: Front porch period continues until

the next input of VSYNC.
DOTCLK
Note 2: Input DOTCLK throughout the
ENABLE operation.

Note 3: Supply the VSYNC, HSYNC and

DB[17:0] DOTCLK with frequency that can meet the
resolution requirement of panel.

Figure15 GRAM Access Area by RGB Interface

1 frame

Back porch Front porch

VLW >= 1H
VSYNC

HSYNC

DOTCLK

ENABLE

DB[17:0]

HLW >= 3 DOTCLK

//
HSYNC 1H

//
DOTCLK

DTST >= HLW

ENABLE
//

DB[17:0]

Valid data

VLW: VSYNC low period

HLW: HSYNC low period

DTST: data transfer startup time
Note 1: Use the high speed write mode (HWM=1) to write data through the RGB interface.

Figure16 Timing Chart of Signals in 18-/16-bit RGB Interface Mode

1 frame

Back porch Front porch

VSYNC VLW >= 1H

HSYNC

DOTCLK

ENABLE

DB[17:12]

HLW >= 3 DOTCLK

//
HSYNC 1H

//
DOTCLK

DTST >= HLW

ENABLE
//

R G B R G B B R G B
//
DB[17:12]

Valid data

VLW: VSYNC low period

HLW: HSYNC low period

DTST: data transfer startup time
Note 1: Use the high speed write mode (HWM=1) to write data through the RGB interface.
Note 2) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with
DOTCLKs.

Note 3) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs.

Figure17 Timing chart of signals in 6-bit RGB interface mode

• The window address function defined the update area of GRAM.

• Only the moving picture area of GRAM is updated.
• When display the moving picture in RGB interface mode, the DB[17:0] can be switched as system
interface to update still picture area and registers, such as icons.

RAM access via a system interface in RGB-I/F mode

ILI9320 allows GRAM access via the system interface in RGB interface mode. In RGB interface mode, data
are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals. When write data to
the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the
system interface to update the registers (RM = “0”) and the still picture of GRAM. When restart RAM access in
RGB interface mode, wait one read/write cycle and then set RM = “1” and the index register to R22h to start
accessing RAM via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that
data are written to the internal GRAM.
The following figure illustrates the operation of the ILI9320 when displaying a moving picture via the RGB
interface and rewriting the still picture RAM area via the system interface.

Still Picture Area

Moving
Picture Area

Update Update a
a frame frame

VSYNC

ENABLE

DOTCLK

DB[17:0]
Update
moving Update
Set picture Set Set
Set Update display data in
Set Set
Set moving
IR to IR to other than the moving IR to
R22h area RM=0 AD[15:0]
R22h picture area
AD[15:0] RM=1
R22h
picture
area

Figure18 Example of update the still and moving picture

RGB interface with 6-bit data bus

1st Transfer 2nd Transfer 3rd Transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Data transfer synchronization in 6-bit RGB interface mode

ILI9320 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode.
The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a
mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at
the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the
next frame. This function is expedient for moving picture display, which requires consecutive data transfer in
light of minimizing effects from failed data transfer and enabling the system to return to a normal state.
Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK).
Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data
transfer correctly. Otherwise it will affect the display of that frame as well as the next frame.

HSYNC

ENABLE

DOTCLK

DB[17:12] 1st 2nd 3rd 1st 2nd 3rd 1 2 3 1st 2nd 3rd
st nd rd

Transfer synchronization

16-bit RGB Interface (65K colors)

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

Write Data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
Register 17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

7.5.6. 18-bit RGB Interface

The 18-bit RGB interface is selected by setting the RIM[1:0] bits to “00”. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in
synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable
signal (ENABLE). Registers are set only via the system interface.

RGB interface with 18-bit data bus

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Input Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Notes in using the RGB Input Interface

1. The following are the functions not available in RGB Input Interface mode.

Function RGB interface I80 system interface

Partial display Not available Available
Scroll function Not available Available
Interlaced scan Not available Available
Graphics operation function Not available Available

2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period.
3. The periods set with the NO[1:0] bits (gate output non-overlap period), STD[1:0] bits (source output delay
period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 45 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
RGB interface mode.
4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input. In
other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure to complete data transfer in units of 3
DOTCLK inputs in 6-bit RGB interface mode.
5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of
3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE,
DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels.
6. When switching from the internal operation mode to the RGB Input Interface mode, or the other way around,
follow the sequence below.
7. In RGB interface mode, the front porch period continues until the next VSYNC input is detected after
drawing one frame.
8. In RGB interface mode, a RAM address (AD[15:0]) is set in the address counter every frame on the falling
edge of VSYNC.

Internal clock operation RGB I/F to Internal clock

to RGB I/F operation

Internal clock operation RGB Interface Operation RGB Interface

(Display operation in
Internal clock Set Internal Clock synchronization with
HWM = 1, AM=0 VSYNC, HSYNC,
operation Operation mode
DM[1:0]=00 and RM=0 DOTCLK)
* SPI interface can
Set AD[15:0] be used to set the * DM[1:0] and RM
registers and data become enable after
completion of
Wait for more than 1 frame display 1 frame
Set RGB Interface mode * DM[1:0] and
DM[1:0]=01 and RM=1 RM become
Note enable after
completion of Display operation in
display 1 frame Internal clock operation synchronization with
Set IR to R22h internal clock
(GRAM data write)

Wait for more than 1 frame

RGB Interface
Write data (Display operation in
through RGB I/F synchronization with VSYNC,
HSYNC, DOTCLK)

RGB Interface Operation

Note: Input RGB Interface signals (VSYNC, HSYNC, DOTCLK)

before setting DM[1;0] and RM to the RGB interface mode

Figure19 Internal clock operation/RGB interface mode switching

Write data through RGB Write data through system

interface to write data interface to write data
through system interface through RGB interface

System Interface operation

RGB Interface operation
Write data to GRAM
Set DM[1:0]=01, RM=0 through system interface
with RGB interface mode

HWM=1/0 HWM=1/0

Set AD[15;0] Set AD[15;0]

Set DM[1:0]=01, RM=1

Set IR to R22h with RGB interface mode
(GRAM data write)

Set IR to R22h
Write data to GRAM (GRAM data write)
through system interface

RGB Interface operation

System Interface operation

Figure20 GRAM access between system interface and RGB interface

//
VSYNC

//
HSYNC

DOTCLK
//

ENABLE
//
//
DB[17:0] 1 2 3 4 5 318 319 320 1 2 3 4

FLM

G2
…..

G320

//
S[720:1] 1 2 3 4 5 318 319 320

VCOM

Figure21 Relationship between RGB I/F signals and LCD Driving Signals for Panel

8.1. Registers Access

ILI9320 adopts 18-bit bus interface architecture for high-performance microprocessor. All the functional
blocks of ILI9320 starts to work after receiving the correct instruction from the external microprocessor by the
18-, 16-, 9-, 8-bit interface. The index register (IR) stores the register address to which the instructions and
display data will be written. The register selection signal (RS), the read/write signals (nRD/nWR) and data
bus D17-0 are used to read/write the instructions and data of ILI9320. The registers of the ILI9320 are
categorized into the following groups.
1. Specify the index of register (IR)
2. Read a status
3. Display control
4. Power management Control
5. Graphics data processing
6. Set internal GRAM address (AC)
7. Transfer data to/from the internal GRAM (R22)
8. Internal grayscale γ-correction (R30 ~ R39)

Normally, the display data (GRAM) is most often updated, and in order since the ILI9320 can update internal
GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the
window address function, there are fewer loads on the program in the microprocessor. As the following figure
shows, the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Send registers in
accordance with the following data transfer format.

Serial Peripheral Interface for register access

D D D D D D D D D D D D D D D D
SPI Input Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D D D D D D D D D D D D D D D D
Register Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure22 Register Setting with Serial Peripheral Interface (SPI)

i80/M68 system 18-bit data bus interface

Data Bus DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
(DB[17:0]) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

i80/M68 system 16-bit data bus interface

Data Bus
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
(DB[17:10]), 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
(DB[8:1])

i80/M68 system 9-bit data bus interface

1st Transfer 2nd Transfer

Data Bus DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
(DB[17:9]) 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9

i80/M68 system 8-bit data bus interface/Serial peripheral interface (2/3 transmission)

1st Transfer 2nd Transfer

Data Bus DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
(DB[17:10]) 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

Figure23 Register setting with i80 System Interface

i80 18-/16-bit System Bus Interface Timing

(a) Write to register

nCS

nRD

nWR

DB[17:0] Write register “index” Write register “data”

(b) Read from register

nCS

nRD

nWR

DB[17:0] Write register “index” Read register “data”

i80 9-/8-bit System Bus Interface Timing

(a) Write to register

nCS

nRD

nWR

Write register Write register

DB[17:10] “00h” Write register “index”
“high byte data” “low byte data”

(b) Read from register

nCS

nRD

nWR

Read register Read register

DB[17:10] “00h” Write register “index”
“high byte data” “low byte data”

Figure 24 Register Read/Write Timing of i80 System Interface

29h Power Control 7 W 1 0 0 0 0 0 0 0 0 0 0 0 VCM4 VCM3 VCM2 VCM1 VCM0

2Bh Frame Rate and Color Control W 1 16M_EN Dither 0 0 0 0 0 0 EXT_R 0 FR_SEL1 FR_SEL0 0 0 0 0
30h Gamma Control 1 W 1 0 0 0 0 0 KP1[2] KP1[1] KP1[0] 0 0 0 0 0 KP0[2] KP0[1] KP0[0]
31h Gamma Control 2 W 1 0 0 0 0 0 KP3[2] KP3[1] KP3[0] 0 0 0 0 0 KP2[2] KP2[1] KP2[0]
32h Gamma Control 3 W 1 0 0 0 0 0 KP5[2] KP5[1] KP5[0] 0 0 0 0 0 KP4[2] KP4[1] KP4[0]
35h Gamma Control 4 W 1 0 0 0 0 0 RP1[2] RP1[1] RP1[0] 0 0 0 0 0 RP0[2] RP0[1] RP0[0]
36h Gamma Control 5 W 1 0 0 0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 VRP0[4] VRP0[3] VRP0[2] VRP0[1] VRP0[0]
37h Gamma Control 6 W 1 0 0 0 0 0 KN1[2] KN1[1] KN1[0] 0 0 0 0 0 KN0[2] KN0[1] KN0[0]
38h Gamma Control 7 W 1 0 0 0 0 0 KN3[2] KN3[1] KN3[0] 0 0 0 0 0 KN2[2] KN2[1] KN2[0]
39h Gamma Control 8 W 1 0 0 0 0 0 KN5[2] KN5[1] KN5[0] 0 0 0 0 0 KN4[2] KN4[1] KN4[0]
3Ch Gamma Control 9 W 1 0 0 0 0 0 RN1[2] RN1[1] RN1[0] 0 0 0 0 0 RN0[2] RN0[1] RN0[0]

The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed.

8.2.2. Status Read (RS)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R 0 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0

The SR bits represent the internal status of the ILI9320.

L[7:0] Indicates the position of driving line which is driving the TFT panel currently.

8.2.3. Start Oscillation (R00h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 - - - - - - - - - - - - - - - 1

R 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0

Set the OSC bit as ‘1’ to start the internal oscillator and as ‘0’ to stop the oscillator. Wait at least 10ms to let
the frequency of oscillator stable and then do the other function setting. The device code “9320”h is read out
when read this register.

8.2.4. Driver Output Control (R01h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0

SS: Select the shift direction of outputs from the source driver.
When SS = 0, the shift direction of outputs is from S1 to S720
When SS = 1, the shift direction of outputs is from S720 to S1.
In addition to the shift direction, the settings for both SS and BGR bits are required to change the
assignment of R, G, B dots to the source driver pins.
To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0.
To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1.
When changing SS or BGR bits, RAM data must be rewritten.

SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan
mode for the module.

SM GS Scan Direction Gate Output Sequence

G1 G2
G3 G4

Odd-number TFT Panel Even-number

G1, G2, G3, G4, …,G316

0 0
G317, G318, G319, G320
G1 to G319

G2 to G320
G317 G318
G319 G320

ILI9320

G1 G2
G3 G4

Odd-number TFT Panel Even-number

G320, G319, G318, …,

0 1
G6, G5, G4, G3, G2, G1
G319 to G1

G320 to G2

G317 G318
G319 G320

ILI9320

Odd-number G1 G2

TFT Panel
G1, G3, G5, G7, …,G311
G1 to G319

G319
G313, G315, G317, G319
G2
1 0 Even-number
G2, G4, G6, G8, …,G312
G2 to G320

G320 G314, G316, G318, G320

ILI9320

Odd-number G1 G2

TFT Panel G320, G318, G316, …,

G319 to G1

G319 G10, G8, G6, G4, G2

G2
1 1 Even-number
G319, G317, G315, …,
G320 to G2

G9, G78, G5, G3, G1

G320

ILI9320

8.2.5. LCD Driving Wave Control (R02h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 1 B/C EOR 0 0 0 0 0 0 0 0

.B/C 0 : Frame/Field inversion

1 : Line inversion

EOR: EOR = 1 and B/C=1 to set the line inversion.

8.2.6. Entry Mode (R03h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 TRI DFM 0 BGR 0 0 HWM 0 ORG 0 I/D1 I/D0 AM 0 0 0

AM Control the GRAM update direction.

When AM = “0”, the address is updated in horizontal writing direction.
When AM = “1”, the address is updated in vertical writing direction.
When a window area is set by registers R16h and R17h, only the addressed GRAM area is updated
based on I/D[1:0] and AM bits setting.

I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel
display data. Refer to the following figure for the details.

I/D[1:0] = 00 I/D[1:0] = 01 I/D[1:0] = 10 I/D[1:0] = 11

Horizontal : decrement Horizontal : increment Horizontal : decrement Horizontal : increment
Vertical : decrement Vertical : decrement Vertical : increment Vertical : increment

E E B B
AM = 0

Horizontal
B B E E

E E B B
AM = 1

Vertical
B B E E

Figure25 GRAM Access Direction Setting

ORG Moves the origin address according to the ID setting when a window address area is made. This
function is enabled when writing data with the window address area using high-speed RAM write.
ORG = “0”: The origin address is not moved. In this case, specify the address to start write operation
according to the GRAM address map within the window address area.

Notes: 1. When ORG=1, only the origin address address”00000h” can be set in the RAM address set
registers R20h, and R21h.
2. In RAM read operation, make sure to set ORG=0.

BGR Swap the R and B order of written data.

BGR=”0”: Follow the RGB order to write the pixel data.
BGR=”1”: Swap the RGB data to BGR in writing into GRAM.

TRI When TRI = “1”, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface.
It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k
colors in combination with DFM bits. When not using these interface modes, be sure to set TRI = “0”.

DFM Set the mode of transferring data to the internal RAM when TRI = “1”. See the following figures for
details.

TRI DFM 16-bit MPU System Interface Data Format

system 16-bit interface (1 transfers/pixel) 65,536 colors

1st Transfer
0 * DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 16-bit interface (2 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer

1 0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 16-bit interface (2 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer

1 1 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Figure26 16-bit MPU System Interface Data Format

system 8-bit interface (2 transfers/pixel) 65,536 colors

1st Transfer 2nd Transfer

0 * DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 8-bit interface (3 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer 3rd Transfer

1 0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

80-system 8-bit interface (3 transfers/pixel) 262,144 colors

1st Transfer 2nd Transfer 3rd Transfer

1 1 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Figure27 8-bit MPU System Interface Data Format

8.2.7. Resizing Control Register (R04h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 RCV1 RCV0 0 0 RCH1 RCH0 0 0 RSZ1 RSZ0

RSZ[1:0] Sets the resizing factor.

When the RSZ bits are set for resizing, the ILI9320 writes the data according to the resizing factor
so that the original image is displayed in horizontal and vertical dimensions, which are contracted
according to the factor respectively. See “Resizing function”.
RCH[1:0] Sets the number of remainder pixels in horizontal direction when resizing a picture.
By specifying the number of remainder pixels by RCH bits, the data can be transferred without
taking the reminder pixels into consideration. Make sure that RCH = 2’h0 when not using the
resizing function (RSZ = 2’h0) or there are no remainder pixels.

RCV[1:0] Sets the number of remainder pixels in vertical direction when resizing a picture.
By specifying the number of remainder pixels by RCV bits, the data can be transferred without
taking the reminder pixels into consideration. Make sure that RCV = 2’h0 when not using the
resizing function (RSZ = 2’h0) or there are no remainder pixels.

RSZ[1:0] Resizing factor

00 No resizing (x1)
01 x 1/2
10 Setting prohibited
11 x 1/4

RCH[1:0] Number of remainder Pixels in Horizontal Direction

00 0 pixel*
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 58 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
01 1 pixel
10 2 pixel
11 3 pixel

RCV[1:0] Number of remainder Pixels in Vertical Direction

00 0 pixel*
01 1 pixel
10 2 pixel
11 3 pixel
*1 pixel = 1RGB

8.2.8. Display Control 1 (R07h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 PTDE1 PTDE0 0 0 BASEE 0 0 0 GON DTE CL 0 D1 D0

D[1:0] Set D[1:0]=”11” to turn on the display panel, and D[1:0]=”00” to turn off the display panel.
A graphics display is turned on the panel when writing D1 = “1”, and is turned off when writing
D1 = “0”.
When writing D1 = “0”, the graphics display data is retained in the internal GRAM and the
ILI9320 displays the data when writing D1 = “1”. When D1 = “0”, i.e. while no display is shown on the
panel, all source outputs becomes the GND level to reduce charging/discharging current, which is
generated within the LCD while driving liquid crystal with AC voltage.
When the display is turned off by setting D[1:0] = “01”, the ILI9320 continues internal display
operation. When the display is turned off by setting D[1:0] = “00”, the ILI9320 internal display
operation is halted completely. In combination with the GON, DTE setting, the D[1:0] setting controls
display ON/OFF.
D1 D0 BASEE Source, VCOM Output ILI9320 internal operation
0 0 0 GND Halt
0 1 1 GND Operate
1 0 0 Non-lit display Operate
1 1 0 Non-lit display Operate
1 1 1 Base image display Operate
Note: 1. data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits.
2. The internal state of the ILI9320 in standby mode become the same as when D[1:0] = “00”. This does
not mean the D[1:0] setting is changed when setting the standby mode.
3. The D[1:0] setting is valid on both 1st and 2nd displays.
4. The non-lit display level from the source output pins is determined by instruction (PTS).

CL When CL = “1”, the 8-color display mode is selected.

CL Colors
0 262,144
1 8

GON and DTE Set the output level of gate driver G1 ~ G320 as follows

BASEE
Base image display enable bit. When BASEE = “0”, no base image is displayed. The ILI9320 drives
liquid crystal at non-lit display level or displays only partial images. When BASEE = “1”, the base
image is displayed. The D[1:0] setting has higher priority over the BASEE setting.
PTDE[1:0]
Partial image 2 and Partial image 1 enable bits
PTDE1/0 = 0: turns off partial image. Only base image is displayed.
PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0).

8.2.9. Display Control 2 (R08h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 FP3 FP2 FP1 FP0 0 0 0 0 BP3 BP2 BP1 BP0

FP[3:0]/BP[3:0]
The FP[3:0] and BP[3:0] bits specify the line number of front and back porch periods respectively.
When setting the FP[3:0] and BP[3:0] value, the following conditions shall be met:
BP + FP ≤ 16 lines
FP ≥ 2 lines
BP ≥ 2 lines

Set the BP[3:0] and FP[3:0] bits as below for each operation modes
Operation Mode BP FP BP+FP
I80 System Interface Operation Mode BP ≥ 2 lines FP ≥ 2 lines FP +BP ≤ 16 lines
RGB interface Operation BP ≥ 2 lines FP ≥ 2 lines FP +BP ≤ 16 lines
VSYNC interface Operation BP ≥ 2 lines FP ≥ 2 lines FP +BP = 16 lines

FP[3:0] Number of lines for Front Porch

BP[3:0] Number of lines for Back Porch
0000 Setting Prohibited
0001 Setting Prohibited Back Porch
0010 2 lines
0011 3 lines
0100 4 lines Display
VSYNC

0101 5 lines Area

0110 6 lines
0111 7 lines
1000 8 lines Front Porch

1001 9 lines

8.2.10. Display Control 3 (R09h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 PTS2 PTS1 PTS0 0 0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0

ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=”10” to select
interval scan. Then scan cycle is set as odd number from 0~31 frame periods. The polarity is
inverted every scan cycle.
ISC3 ISC3 ISC3 ISC3 Scan Cycle fFLM=60 Hz
0 0 0 0 0 frame -
0 0 0 1 3 frame 50ms
0 0 1 0 5 frame 84ms
0 0 1 1 7 frame 117ms
0 1 0 0 9 frame 150ms
0 1 0 1 11 frame 184ms
0 1 1 0 13 frame 217ms
0 1 1 1 15 frame 251ms
1 0 0 0 17 frame 284ms
1 0 0 1 19 frame 317ms
1 0 1 0 21 frame 351ms
1 0 1 1 23 frame 384ms
1 1 0 0 25 frame 418ms
1 1 0 1 27 frame 451ms
1 1 1 0 29 frame 484ms
1 1 1 1 31 frame 518ms

PTG[1:0] Set the scan mode in non-display area.

PTG1 PTG0 Gate outputs in non-display area Source outputs in non-display area Vcom output
0 0 Normal scan Set with the PTS[2:0] bits VcomH/VcomL
0 1 Setting Disabled - -
1 0 Interval scan Set with the PTS[2:0] bits VcomH/VcomL
1 1 Setting Disabled - -

PTS[2:0]
Set the source output level in non-display area drive period (front/back porch period and blank area
between partial displays).
When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V63
are halted and the step-up clock frequency becomes half the normal frequency in non-display drive
period in order to reduce power consumption.

PTS[2:0] Source output level Grayscale amplifier Step-up clock frequency

8.2.11. Display Control 4 (R0Ah)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 0 0 0 0 0 FMARKOE FMI2 FMI1 FMI0

FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer
rate.

FMARKOE When FMARKOE=1, ILI9320 starts to output FMARK signal in the output interval set by FMI[2:0]
bits.
FMI[2:0] Output Interval
000 1 frame
001 2 frame
011 4 frame
101 6 frame
Others Setting disabled

8.2.12. RGB Display Interface Control 1 (R0Ch)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 ENC2 ENC1 ENC0 0 0 0 0 RM 0 0 DM1 DM0 0 0 RIM1 RIM0

RIM[1:0] Select the RGB interface data width.

RIM1 RIM0 RGB Interface Mode
0 0 18-bit RGB interface (1 transfer/pixel), DB[17:0]
0 1 16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1]
1 0 6-bit RGB interface (3 transfers/pixel), DB[17:12]
1 1 Setting disabled
Note1: Registers are set only by the system interface.

Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch.

DM[1:0] Select the display operation mode.

DM1 DM0 Display Interface
0 0 Internal system clock
0 1 RGB interface
1 0 VSYNC interface

RM Select the interface to access the GRAM.

Set RM to “1” when writing display data by the RGB interface.
RM Interface for RAM Access
0 System interface/VSYNC interface
1 RGB interface

Display State Operation Mode RAM Access (RM) Display Operation Mode (DM[1:0]
System interface Internal clock operation
Still pictures Internal clock operation
(RM = 0) (DM[1:0] = 00)
RGB interface RGB interface
Moving pictures RGB interface (1)
(RM = 1) (DM[1:0] = 01)
Rewrite still picture area while RGB interface System interface RGB interface
Displaying moving pictures. (RM = 0) (DM[1:0] = 01)
System interface VSYNC interface
Moving pictures VSYNC interface
(RM = 0) (DM[1:0] = 10)
Note 1: Registers are set only via the system interface or SPI interface.

Note 2: Refer to the flowcharts of “RGB Input Interface” section for the mode switch.

ENC[2:0] Set the GRAM write cycle through the RGB interface
ENC[2:0] GRAM Write Cycle (Frame periods)
000 1 Frame
001 2 Frames
010 3 Frames
011 4 Frames
100 5 Frames
101 6 Frames
110 7 Frames
111 8 Frames

8.2.13. Frame Marker Position (R0Dh)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0

EMP[8:0] Sets the output position of frame cycle (frame marker).

When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display line
period (1H).

Make sure the 9’h000 ≦ FMP ≦ BP+NL+FP

FMP[8:0] FMARK Output Position
9’h000 0th line
9’h001 1st line
9’h002 2nd line

8.2.14. RGB Display Interface Control 2 (R0Fh)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 EPL DPL

DPL: Sets the signal polarity of the DOTCLK pin.

DPL = “0” The data is input on the rising edge of DOTCLK
DPL = “1” The data is input on the falling edge of DOTCLK
EPL: Sets the signal polarity of the ENABLE pin.
EPL = “0” The data DB17-0 is written when ENABLE = “0”. Disable data write operation when
ENABLE = “1”.
EPL = “1” The data DB17-0 is written when ENABLE = “1”. Disable data write operation when
ENABLE = “0”.
HSPL: Sets the signal polarity of the SYNC pin.
HSPL = “0” Low active
HSPL = “1” High active
VSPL: Sets the signal polarity of the VSYNC pin.
VSPL = “0” Low active
VSPL = “1” High active

8.2.15. Power Control 1 (R10h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 SAP BT3 BT2 BT1 BT0 APE AP2 AP1 AP0 0 DSTB SLP 0

SLP: When SLP = 1, ILI9320 enters the sleep mode and the display operation stops except the RC oscillator
to reduce the power consumption. In the sleep mode, the GRAM data and instructions cannot be
updated except the following two instructions.
a. Exit sleep mode (SLP = “0”)
b. Start oscillation

DSTB: When DSTB = 1, the ILI9320 enters the deep standby mode. In deep standby mode, the internal logic
power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not
maintained when the ILI9320 enters the deep standby mode, and they must be reset after exiting deep
standby mode.

AP[2:0] In LCD drive power supply amplifiers In Source driver amplifiers

000 Halt operational amplifiers and step-up circuits Halt
001 0.5 0.62
010 0.75 0.71
011 1 1
100
101 0.5 0.62
110 0.75 0.71
111 1 1

SAP: Source Driver output control

SAP=0, Source driver output is disabled.
SAP=1, Source driver output is enabled.
When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=0, and set the
SAP=1, after starting up the LCD power supply circuit.

APE: Power supply enable bit.

Set APE = “1” to start the generation of power supply according to the power supply startup sequence.

BT[3:0]: Sets the factor used in the step-up circuits.

Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller
factor.
BT[3:0] DDVDH VCL VGH VGL
4’h0 Vci1 x 2 - Vci1 Vci1 x 6 - Vci1 x 5
4’h1 - Vci1 x 4
Vci1 x 2 - Vci1 Vci1 x 8
4’h2 - Vci1 x 3
4’h3 - Vci1 x 5
4’h4 Vci1 x 2 - Vci1 Vci1 x 7 - Vci1 x 4
4’h5 - Vci1 x 3
4’h6 - Vci1 x 4
Vci1 x 2 - Vci1 Vci1 x 6
4’h7 - Vci1 x 3
4’h8 Vci1 x 3 - Vci1 Vci1 x 9 - Vci1 x 7
4’h9 - Vci1 x 6
Vci1 x 3 - Vci1 Vci1 x 12
4’hA - Vci1 x 4
4’hB - Vci1 x 7
4’hC Vci1 x 3 - Vci1 Vci1 x 10 - Vci1 x 6
4’hD - Vci1 x 4
4’hE - Vci1 x 6
Vci1 x 3 - Vci1 Vci1 x 9
4’hF - Vci1 x 4

Notes: 1. Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels.

8.2.16. Power Control 2 (R11h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 DC12 DC11 DC10 0 DC02 DC01 DC00 0 VC2 VC1 VC0

VC[2:0] Sets the ratio factor of VciLVL to generate the reference voltages VciOUT and Vci1.

VC2 VC1 VC0 VciOUT reference voltage Vci1 voltage

0 0 0 0.94 x Vci
0 0 1 0.89 x Vci
0 1 0 Setting disabled
0 1 1 Setting disabled
1 0 0 0.76 x Vci
1 0 1 Setting disabled
1 1 0 Setting disabled
1 1 1 1.0 x Vci

DC0[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency
enhances the drivability of the step-up circuit and the quality of display but increases the current
consumption. Adjust the frequency taking the trade-off between the display quality and the current
consumption into account.
DC1[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency
enhances the drivability of the step-up circuit and the quality of display but increases the current
consumption. Adjust the frequency taking the trade-off between the display quality and the current
consumption into account.

DC02 DC01 DC00 Step-up circuit1 DC12 DC11 DC10 Step-up circuit2
step-up frequency (fDCDC1) step-up frequency (fDCDC2)
0 0 0 Fosc 0 0 0 Fosc / 16
0 0 1 Fosc / 2 0 0 1 Fosc / 32
0 1 0 Fosc / 4 0 1 0 Fosc / 64
0 1 1 Fosc / 8 0 1 1 Fosc / 128
1 0 0 Fosc / 16 1 0 0 Fosc / 256
1 0 1 Setting disabled 1 0 1 Setting disabled
1 1 0 Halt step-up circuit 1 1 1 0 Halt step-up circuit 2
1 1 1 Setting disabled 1 1 1 Setting disabled
Note: Be sure fDCDC1≥fDCDC2 when setting DC0[2:0] and DC1[2:0].

8.2.17. Power Control 3 (R12h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 VCMR 0 0 0 PON VRH3 VRH2 VRH1 VRH0

VRH[3:0] Set the amplifying rate (1.6 ~ 1.9) of VciLVL applied to output the VREG1OUT level, which is a
reference level for the VCOM level and the grayscale voltage level.

PON: Control ON/OFF of circuit3 (VGL) output.

PON=0 VGL output is disable
PON=1 VGL output is enable

VCMR: Selects either external resistor (VcomR) or internal electric volume (VCM) to set the electrical
potential of VcomH (Vcom center voltage level).
VCMR = 0 Æ Using the external variable resistor to adjust the VcomH voltage level

VCMR = 1 Æ Using the Internal electronic volume (VCM[4:0]) to adjust the VcomH voltage level.

8.2.18. Power Control 4 (R13h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 0

VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.70 to 1.24 x
VREG1OUT .

VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude
0 0 0 0 0 VREG1OUT x 0.70 1 0 0 0 0 VREG1OUT x 0.87
0 0 0 0 1 VREG1OUT x 0.72 1 0 0 0 1 VREG1OUT x 0.89
0 0 0 1 0 VREG1OUT x 0.74 1 0 0 1 0 VREG1OUT x 0.92
0 0 0 1 1 VREG1OUT x 0.76 1 0 0 1 1 VREG1OUT x 0.94
0 0 1 0 0 VREG1OUT x 0.78 1 0 1 0 0 VREG1OUT x 0.96
0 0 1 0 1 VREG1OUT x 0.80 1 0 1 0 1 VREG1OUT x 0.99
0 0 1 1 0 VREG1OUT x 0.82 1 0 1 1 0 VREG1OUT x 1.01
0 0 1 1 1 VREG1OUT x 0.84 1 0 1 1 1 VREG1OUT x 1.04
0 1 0 0 0 VREG1OUT x 0.86 1 1 0 0 0 VREG1OUT x 1.06
0 1 0 0 1 VREG1OUT x 0.88 1 1 0 0 1 VREG1OUT x 1.09
0 1 0 1 0 VREG1OUT x 0.90 1 1 0 1 0 VREG1OUT x 1.11
0 1 1 1 1 VREG1OUT x 0.92 1 1 1 1 1 VREG1OUT x 1.14
0 1 1 0 0 VREG1OUT x 0.94 1 1 1 0 0 VREG1OUT x 1.16
0 1 1 0 1 VREG1OUT x 0.96 1 1 1 0 1 VREG1OUT x 1.19
0 1 1 1 0 VREG1OUT x 0.98 1 1 1 1 0 VREG1OUT x 1.21
0 1 1 1 1 VREG1OUT x 1.00 1 1 1 1 1 VREG1OUT x 1.24

Set VDV[4:0] to let Vcom amplitude less than 6V.

8.2.19. GRAM Horizontal/Vertical Address Set (R20h, R21h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

W 1 0 0 0 0 0 0 0 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8

AD[16:0] Set the initial value of address counter (AC).

AD[16:0] GRAM Data Map

17’h00000 ~ 17’h000EF 1st line GRAM Data
17’h00100 ~ 17’h001EF 2nd line GRAM Data
17’h00200 ~ 17’h002EF 3rd line GRAM Data
17’h00300 ~ 17’h003EF 4th line GRAM Data

17’h13D00 ~ 17’ h13DEF 318th line GRAM Data

17’h13E00 ~ 17’ h13EEF 319th line GRAM Data
17’h13F00 ~ 17’h13FEF 320th line GRAM Data
Note1: When the RGB interface is selected (RM = “1”), the address AD[16:0] is set to the address counter
every frame on the falling edge of VSYNC.
Note2: When the internal clock operation or the VSYNC interface mode is selected (RM = “0”), the address
AD[16:0] is set to address counter when update register R21.

8.2.20. Write Data to GRAM (R22h)

R/W RS D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 RAM write data (WD[17:0], the DB[17:0] pin assignment differs for each interface.

This register is the GRAM access port. When update the display data through this register, the address
counter (AC) is increased/decreased automatically.

8.2.21. Read Data from GRAM (R22h)

R/W RS D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R 1 RAM Read Data (RD[17:0], the DB[17:0] pin assignment differs for each interface.

RD[17:0] Read 18-bit data from GRAM through the read data register (RDR).

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Write Data RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Output Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

16-bit System Interface

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Write Data RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Output Data 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

9-bit System Interface

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Write Data RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Output Data 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
1st Transfer 2nd Transfer

8-bit System Interface / Serial Data Transfer Interface

GRAM Data &

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RGB Mapping

Write Data RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
Register 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
Output Data 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
1st Transfer 2nd Transfer

Figure 28 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode

Set I/D AM, HAS/HEA, VSA/VEA

Set address M

Dummy read (invalid data)

GRAM -> Read data latch

Read Output (data of address M)

Read datalatch -> DB[17:0]

Read Output (data of address M+1)

Read datalatch -> DB[17:0]

Set address N

Dummy read (invalid data)

GRAM -> Read data latch

Read Output (data of address N)

Read datalatch -> DB[17:0]

Figure 29 GRAM Data Read Back Flow Chart

8.2.22. Power Control 7 (R29h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 0 0 0 0 VCM4 VCM3 VCM2 VCM1 VCM0

VCM[4:0] Set the internal VcomH voltage.

VCMR =1, the VcomH voltage is generated based on the VCM[4:0] setting value.
VCMR =0, the VcomH voltage is generated based on the external reference voltage VCOMR.

VCM4 VCM3 VCM2 VCM1 VCM0 VCOMH VCM4 VCM3 VCM2 VCM1 VCM0 VCOMH
0 0 0 0 0 VREG1OUT x 0.69 1 0 0 0 0 VREG1OUT x 0.85
0 0 0 0 1 VREG1OUT x 0.70 1 0 0 0 1 VREG1OUT x 0.86
0 0 0 1 0 VREG1OUT x 0.71 1 0 0 1 0 VREG1OUT x 0.87
0 0 0 1 1 VREG1OUT x 0.72 1 0 0 1 1 VREG1OUT x 0.88
0 0 1 0 0 VREG1OUT x 0.73 1 0 1 0 0 VREG1OUT x 0.89

8.2.23. Frame Rate and Color Control (R2Bh)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 16M_EN Dither 0 0 0 0 0 0 EXT_R 0 FR_SEL1 FR_SEL0 0 0 0 0

EXT_R External or internal resistor selection for oscillator circuit.

EXT_R Resistor Selection

0 Internal Resistor (default)
1 External Resistor

FR_SEL[1:0] Set the frame rate when the internal resistor is used for oscillator circuit.

FR_SEL1 FR_SEL0 Frame Rate (Hz)

0 0 90 (default)
0 1 80
1 0 110
1 1 100

16M_EN Select the color depth.

16M_EN Color Depth Selection

0 262K Color (default)
1 16M Color

Dither Dithering function control.

When the dithering function is enabled, the 24-bit input data will be dithered into 18-bit and the display
quality is close to 16.7 million colors.

Dither Dither Function

0 Disable (default)
1 Enable

The input data transfer format is as below (16M_EN=1, Dither=1).

¾ 18bit interface: 2 transfer mode

1st Transfer: DB[17:10], DB[8:1]

¾ 16 bit interface: 2 transfer mode (TRIREG =1, DFM=0)

1st Transfer: DB[17:10], DB[8:1]
2nd Transfer: DB[17:10]

¾ 8 bit interface: 3 transfer mode (TRIREG =1, DFM=1)

1st Transfer: DB[17:10]
2nd Transfer: DB[17:10]
3rd Transfer: DB[17:10]

8.2.24. Gamma Control (R30h ~ R3Dh)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R30h W 1 0 0 0 0 0 KP1[2] KP1[1] KP1[0] 0 0 0 0 0 KP0[2] KP0[1] KP0[0]

R31h W 1 0 0 0 0 0 KP3[2] KP3[1] KP3[0] 0 0 0 0 0 KP2[2] KP2[1] KP2[0]

R32h W 1 0 0 0 0 0 KP5[2] KP5[1] KP5[0] 0 0 0 0 0 KP4[2] KP4[1] KP4[0]

R35h W 1 0 0 0 0 0 RP1[2] RP1[1] RP1[0] 0 0 0 0 0 RP0[2] RP0[1] RP0[0]

R36h W 1 0 0 0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 VRP0[4] VRP0[3] VRP0[2] VRP0[1] VRP0[0]

R37h W 1 0 0 0 0 0 KN1[2] KN1[1] KN1[0] 0 0 0 0 0 KN0[2] KN0[1] KN0[0]

R38h W 1 0 0 0 0 0 KN3[2] KN3[1] KN3[0] 0 0 0 0 0 KN2[2] KN2[1] KN2[0]

R39h W 1 0 0 0 0 0 KN5[2] KN5[1] KN5[0] 0 0 0 0 0 KN4[2] KN4[1] KN4[0]

R3Ch W 1 0 0 0 0 0 RN1[2] RN1[1] RN1[0] 0 0 0 0 0 RN0[2] RN0[1] RN0[0]

R3Dh W 1 0 0 0 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0 0 0 VRN0[4] VRN0[3] VRN0[2] VRN0[1] VRN0[0]

KP5-0[2:0] : γfine adjustment register for positive polarity

RP1-0[2:0] : γgradient adjustment register for positive polarity
VRP1-0[4:0] : γamplitude adjustment register for positive polarity
KN5-0[2:0] : γfine adjustment register for negative polarity
RN1-0[2:0] : γgradient adjustment register for negative polarity
VRN1-0[4:0] : γamplitude adjustment register for negative polarity
For details “γ-Correction Function” section.

8.2.25. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h)
R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R50h W 1 0 0 0 0 0 0 0 0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0

R51h W 1 0 0 0 0 0 0 0 0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0

R52h W 1 0 0 0 0 0 0 0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0

R53h W 1 0 0 0 0 0 0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0

HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the

VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the
window address area in vertical direction. By setting VSA and VEA bits, it is possible to limit the
area on the GRAM vertically for writing data. The VSA and VEA bits must be set before starting
RAM write operation. In setting, be sure “000”h ≤ VSA[8:0]< VEA[8:0] ≤ “13F”h.

HSA HEA
0000h

VSA

Window Address
Area

VEA
GRAM Address Area

13FEFh

Figure 30 GRAM Access Range Configuration

“00”h ≤HAS[7:0] ≤HEA[7:0] ≤”EF”h

“00”h ≤VSA[7:0] ≤VEA[7:0] ≤”13F”h
Note1. The window address range must be within the GRAM address space.
Note2. Data are written to GRAM in four-words when operating in high speed mode, the dummy write
operations should be inserted depending on the window address area. For details, see the High-Speed RAM
Write Function section.

8.2.26. Gate Scan Control (R60h, R61h, R6Ah)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R60h W 1 GS 0 NL5 NL4 NL3 NL2 NL1 NL0 0 0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0

R61h W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 NDL VLE REV

R6Ah W 1 0 0 0 0 0 0 0 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0

SCN[5:0] The ILI9320 allows to specify the gate line from which the gate driver starts to scan by setting the
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
SCN[5:0] bits.

Scanning Start Position

SCN[5:0] SM=0 SM=1
GS=0 GS=1 GS=0 GS=1
00h G1 G320 G1 G320
01h G9 G312 G17 G304
02h G17 G304 G33 G288
03h G25 G296 G49 G272
04h G33 G288 G65 G256
05h G41 G280 G81 G240
06h G49 G272 G97 G224
07h G57 G264 G113 G208
08h G65 G256 G129 G192
09h G73 G248 G145 G176
0Ah G81 G240 G161 G160
0Bh G89 G232 G177 G144
0Ch G97 G224 G193 G128
0Dh G105 G216 G209 G112
0Eh G113 G208 G2 G96
0Fh G121 G200 G18 G80
10h G129 G192 G34 G64
11h G137 G184 G50 G48
12h G145 G176 G66 G32
13h G153 G168 G82 G16
14h G161 G160 G98 G319
15h G169 G152 G114 G303
16h G177 G144 G130 G287
17h G185 G136 G146 G271
18h G193 G128 G162 G255
19h G201 G120 G178 G239
1Ah G209 G112 G194 G223
1Bh G217 G104 G114 G207
1Ch G225 G96 G130 G191
1Dh G233 G88 G146 G175
1Eh G241 G80 G162 G159
1Fh G249 G72 G178 G143
20h G257 G64 G194 G127
21h G265 G56 G210 G111
22h G273 G48 G226 G95
23h G281 G40 G242 G79
24h G289 G32 G258 G63
25h G297 G24 G274 G47
26h G305 G16 G290 G31
27h G313 G8 G306 G15
28h ~ 3Fh Setting disabled Setting disabled Setting disabled Setting disabled

NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is
not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more
than the number of lines necessary for the size of the liquid crystal panel.

NL[5:0] LCD Drive Line

NDL: Sets the source driver output level in the non-display area.
Non-Display Area
NDL
Positive Polarity Negative Polarity
0 V63 V0
1 V0 V63

GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. The scan
direction determined by GS = 0 can be reversed by setting GS = 1.
When GS = 0, the scan direction is from G1 to G320.
When GS = 1, the scan direction is from G320 to G1

REV: Enables the grayscale inversion of the image by setting REV=1.

Source Output in Display Area

REV GRAM Data
Positive polarity negative polarity
18’h00000 V63 V0
. . .
0 . . .
. . .
18’h3FFFF V0 V63
18’h00000 V0 V63
. . .
1 . . .
. . .
18’h3FFFF V63 V0

VLE: Vertical scroll display enable bit. When VLE = 1, the ILI9320 starts displaying the base image from the
line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the
number of lines to shift the start line of the display from the first line of the physical display. Note that the
partial image display position is not affected by the base image scrolling.
The vertical scrolling is not available in external display interface operation. In this case, make sure to
set VLE = “0”.

VLE Base Image Display

0 Fixed
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
1 Enable Scrolling

VL[8:0]: Sets the scrolling amount of base image. The base image is scrolled in vertical direction and
displayed from the line determined by VL[8:0]. Make sure that VL[8:0] ≦ 320.

8.2.27. Partial Image 1 Display Position (R80h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTD PTD PTD PTD PTD PTD PTD PTD PTD
W 1 0 0 0 0 0 0 0
P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]

PTDP0[8:0]: Sets the display position of partial image 1. The display areas of the partial images 1 and 2 must
not overlap each another.

8.2.28. Partial Image 1 RAM Start/End Address (R81h, R82h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTS PTS PTS PTS PTS PTS PTS PTS PTS
W 1 0 0 0 0 0 0 0
A0[8] A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0]

W 1 0 0 0 0 0 0 0 PTE PTE PTE PTE PTE PTE PTE PTE PTE

A0[8] A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0]

PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the
data of partial image 1. Make sure PTSA0[8:0] ≤ PTEA0[8:0].

8.2.29. Partial Image 2 Display Position (R83h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTS PTD PTD PTD PTD PTD PTD PTD PTD
W 1 0 0 0 0 0 0 0
A1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]

PTDP1[8:0]: Sets the display position of partial image 2 The display areas of the partial images 1 and 2 must
not overlap each another.

8.2.30. Partial Image 2 RAM Start/End Address (R84h, R85h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTS PTS PTS PTS PTS PTS PTS PTS PTS
W 1 0 0 0 0 0 0 0
A1[8] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0]

W 1 0 0 0 0 0 0 0 PTE PTE PTE PTE PTE PTE PTE PTE PTE

A1[8] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0]

PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the
data of partial image 2 Make sure PTSA1[8:0] ≤ PTEA1[8:0].

8.2.31. Panel Interface Control 1 (R90h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 76 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
W 1 0 0 0 0 0 0 0 DIVI1 DIVI0 0 0 RTNI4 RTNI3 RTNI2 RTNI1 RTNI0

RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. In this mode, ILI9320 display
operation is synchronized with internal clock signal.
RTNI[4:0] Clocks/Line RTNI[4:0] Clocks/Line
00000~01111 Setting Disabled 11000 24 clocks
10000 16 clocks 11001 25 clocks
10001 17 clocks 11010 26 clocks
10010 18 clocks 11011 27 clocks
10011 19 clocks 11100 28 clocks
10100 20 clocks 11101 29 clocks
10101 21 clocks 11110 30 clocks
10110 22 clocks 11111 31 clocks
10111 23 clocks

DIVI[1:0]: Sets the division ratio of internal clock frequency.

DIVI1 DIVI0 Division Ratio Internal Operation Clock Frequency

0 0 1 fosc / 1
0 1 2 fosc / 2
1 0 4 fosc / 4
1 1 8 fosc / 8

Formula to calculate frame frequency

fosc.
Frame Rate =
Clock cycles per line x division ratio x (Lines +BP+FP)

fosc. : frequency if RC oscillation.

Clock cycles per line : RTN bits
Division ratio : DIV bits
Lines : number of lines for driving the LCD panel.
FP: Front porch lines
BP; Back porch lines

8.2.32. Panel Interface Control 2 (R92h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 NOWI[2] NOWI[1] NOWI[0] 0 0 0 0 0 0 0 0

NOWI[2:0]: Sets the gate output non-overlap period when ILI9320 display operation is synchronized with
internal clock signal.
NOWI[2:0] Gate Non-overlap Period
000 0 clocks
001 1 clocks
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks

8.2.33. Panel Interface Control 3 (R93h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MCPI2 MCPI1 MCPI0

MCPI[2:0]: Sets the source output position when ILI9320 display operation is synchronized with internal clock
signal.

MCPI[2:0] Source Output Position

000 Setting inhibited
001 1 clocks
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the
frequency of which is determined by instruction (DIVI[1:0]), from the reference point.

8.2.34. Panel Interface Control 4 (R95h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 DIVE1 DIVE0 0 0 RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0

RTNE[5:0]: Sets 1H (line) clock number of RGB interface mode. In this mode, ILI9320 display operation is
synchronized with RGB interface signals.

DIVE (division ratio) x RTNE (DOTCLKs) ≤ DOTCLKs in 1H period.

Clocks per line period Clocks per line period Clocks per line period Clocks per line period
RTNE[5:0] RTNE[5:0] RTNE[5:0] RTNE[5:0]
(1H) (1H) (1H) (1H)
00h Setting Prohibited 10h 16 clocks 20h 32 clocks 30h 48 clocks
01h Setting Prohibited 11h 17 clocks 21h 33 clocks 31h 49 clocks
02h Setting Prohibited 12h 18 clocks 22h 34 clocks 32h 50 clocks
03h Setting Prohibited 13h 19 clocks 23h 35 clocks 33h 51 clocks
04h Setting Prohibited 14h 20 clocks 24h 36 clocks 34h 52 clocks
05h Setting Prohibited 15h 21 clocks 25h 37 clocks 35h 53 clocks
06h Setting Prohibited 16h 22 clocks 26h 38 clocks 36h 54 clocks
07h Setting Prohibited 17h 23 clocks 27h 39 clocks 37h 55 clocks
08h Setting Prohibited 18h 24 clocks 28h 40 clocks 38h 56 clocks
09h Setting Prohibited 19h 25 clocks 29h 41 clocks 39h 57 clocks
0ah Setting Prohibited 1ah 26 clocks 2ah 42 clocks 3ah 58 clocks
0bh Setting Prohibited 1bh 27 clocks 2bh 43 clocks 3bh 59 clocks
0ch Setting Prohibited 1ch 28 clocks 2ch 44 clocks 3ch 60 clocks
0dh Setting Prohibited 1dh 29 clocks 2dh 45 clocks 3dh 61 clocks
0eh Setting Prohibited 1eh 30 clocks 2eh 46 clocks 3eh 62 clocks
0fh Setting Prohibited 1fh 31 clocks 2fh 47 clocks 3fh 63 clocks

DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9320 display operation is synchronized with RGB
interface signals.

DIVE[1:0] Division Ratio 18/16-bit RGB Interface DOTCLK=5MHz 6-bit x 3 Transfers RGB Interface DOTCLK=5MHz
00 Setting Prohibited Setting Prohibited - Setting Prohibited -
01 1/4 4 DOTCLKS 0.8 μs 12 DOTCLKS 0.8 μs
10 1/8 8 DOTCLKS 1.6 μs 24 DOTCLKS 1.6 μs
11 1/16 16 DOTCLKS 3.2 μs 48 DOTCLKS 3.2 μs

8.2.35. Panel Interface Control 5 (R97h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 NOWE3 NOWE2 NOWE1 NOWE0 0 0 0 0 0 0 0 0

NOWE[2:0]: Sets the gate output non-overlap period when the ILI9320 display operation is synchronized with
RGB interface signals.
NOWE[3:0] Gate Non-overlap Period NOWE[3:0] Gate Non-overlap Period
0000 0 clocks 1000 8 clocks
0001 1 clocks 1001 9 clocks
0010 2 clocks 1010 10 clocks
0011 3 clocks 1011 11 clocks
0100 4 clocks 1100 12 clocks
0101 5 clocks 1101 13 clocks
0110 6 clocks 1110 14 clocks
0111 7 clocks 1111 15 clocks
Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK]

8.2.36. Panel Interface Control 6 (R98h)

R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MCPE2 MCPE1 MCPE0

MCPE[2:0]: Sets the source output position when the ILI9320 display operation is synchronized with RGB
interface signals.

MCPE[2:0] Source Output Position

000 0 clocks
001 1 clocks
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK]

i80 18-/16-bit System Bus Interface Timing

(a) Write to GRAM

nCS

nRD

nWR

Write “0022h” to Write GRAM “data” Write GRAM “data” Write GRAM “data” Write GRAM “data”
DB[17:0] index register Nth pixel (N+1)th pixel (N+2)th pixel (N+3)th pixel

(b) Read from GRAM

nCS

nRD

nWR

Write “0022h” to Dummy 1st Read “data” 2nd Read “data” 3rd Read “data”
DB[17:0] index register Read Nth pixel (N+1)th pixel (N+2)th pixel

i80 9-/8-bit System Bus Interface Timing

(a) Write to GRAM

nCS

nRD

nWR

1st write 1st write 2nd write 2nd write 3rd write 3rd write
DB[17:9] “00h” “22h”
high byte low byte high byte low byte high byte low byte

Nth pixel (N+1)th pixel (N+2)th pixel

(b) Read from GRAM

nCS

nRD

nWR

Dummy Dummy 1st read 1st read 2nd read 2nd read
DB[17:9] “00h” “22h”
Read 1 Read 2 high byte low byte high byte low byte

Nth pixel (N+1)th pixel

Figure31 GRAM Read/Write Timing of i80-System Interface

GRAM address map table of SS=0, BGR=0

SS=0, BGR=0 S1…S3 S4…S6 S7…S9 S10…S12 … S517…S519 S520…S522 S523…S525 S526…S720
GS=0 GS=1 DB17…0 DB17…0 DB17…0 DB17…0 … DB17…0 DB17…0 DB17…0 DB17…0
G1 G320 “00000h” “00001h” “00002h” “00003h” … “000ECh” “000EDh” “000EEh” “000EFh”
G2 G319 “00100h” “00101h” “00102h” “00103h” … “001ECh” “001EDh” “001EEh” “001EFh”
G3 G318 “00200h” “00201h” “00202h” “00203h” … “002ECh” “002EDh” “002EEh” “002EFh”
G4 G317 “00300h” “00301h” “00302h” “00303h” … “003ECh” “003EDh” “003EEh” “003EFh”
G5 G316 “00400h” “00401h” “00402h” “00403h” … “004ECh” “004EDh” “004EEh” “004EFh”
G6 G315 “00500h” “00501h” “00502h” “00503h” … “005ECh” “005EDh” “005EEh” “005EFh”
G7 G314 “00600h” “00601h” “00602h” “00603h” … “006ECh” “006EDh” “006EEh” “006EFh”
G8 G313 “00700h” “00701h” “00702h” “00703h” … “007ECh” “007EDh” “007EEh” “007EFh”
G9 G312 “00800h” “00801h” “00802h” “00803h” … “008ECh” “008EDh” “008EEh” “008EFh”
G10 G311 “00900h” “00901h” “00902h” “00903h” … “009ECh” “009EDh” “009EEh” “009EFh”
. . . . . . … . . . .
. . . . . . . . . .
. . . . . . . . . .
G311 G10 “13600h” “13601h” “13602h” “13603h” … “136ECh” “136EDh” “136EEh” “136EFh”
G312 G9 “13700h” “13701h” “13702h” “13703h” … “137ECh” “137EDh” “137EEh” “137EFh”
G313 G8 “13800h” “13801h” “13802h” “13803h” … “138ECh” “138EDh” “138EEh” “138EFh”
G314 G7 “13900h” “13901h” “13902h” “13903h” … “139ECh” “139EDh” “139EEh” “139EFh”
G315 G6 “13A00h” “13A01h” “13A02h” “13A03h” … “13AECh” “13AEDh” “13AEEh” “13AEFh”
G316 G5 “13B00h” “13B01h” “13B02h” “13B03h” … “13BECh” “13BEDh” “13BEEh” “13BEFh”
G317 G4 “13C00h” “13C01h” “13C02h” “13C03h” … “13CECh” “13CEDh” “13CEEh” “13CEFh”
G318 G3 “13D00h” “13D01h” “13D02h” “13D03h” … “13DECh” “13DEDh” “13DEEh” “13DEFh”
G319 G2 “13E00h” “13E01h” “13E02h” “13E03h” … “13EECh” “13EEDh” “13EEEh” “13EEFh”
G320 G1 “13F00h” “13F01h” “13F02h” “13F03h” … “13FECh” “13FEDh” “13FEEh” “13FEFh”

i80/M68 system 18-bit data bus interface

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (3n+1) S (3n+2) S (3n+3)

N=0 to 175

i80/M68 system 16-bit data bus interface

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (3n+1) S (3n+2) S (3n+3)

N=0 to 175

i80/M68 system 9-bit data bus interface

1st Transfer 2nd Transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (3n+1) S (3n+2) S (3n+3)

N=0 to 175

GRAM Data and display data of 18-/16-/9-bit system interface (SS=”0", BGR=”0")

Figure32 i80-System Interface with 18-/16-/9-bit Data Bus (SS=”0”, BGR=”0”)

i80/M68 system 8-bit interface / SPI Interface (2 transfers/pixel)

1st transfer 2nd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (3n+1) S (3n+2) S (3n+3)

N=0 to 175

i80/M68 system 8-bit interface (3 transfers/pixel, TRI=”1", DFM[1:0]=”00")

1st Transfer 2nd Transfer 3rd Transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data
11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (3n+1) S (3n+2) S (3n+3)

N=0 to 175

i80/M68 system 8-bit interface (3 transfers/pixel, TRI=”1", DFM[1:0]=”10)

1st Transfer 2nd Transfer 3rd Transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (3n+1) S (3n+2) S (3n+3)

N=0 to 175

i80/M68 system 8-bit interface (SS=”0", BGR=”0")

Figure33 i80-System Interface with 8-bit Data Bus (SS=”0”, BGR=”0”)

GRAM address map table of SS=1, BGR=1

SS=0, BGR=0 S720…S718 S717…S715 S714…S712 S711…S709 … S12…S10 S9…S7 S6…S4 S3…S1
GS=0 GS=1 DB17…0 DB17…0 DB17…0 DB17…0 … DB17…0 DB17…0 DB17…0 DB17…0
G1 G320 “00000h” “00001h” “00002h” “00003h” … “000ECh” “000EDh” “000EEh” “000EFh”
G2 G319 “00100h” “00101h” “00102h” “00103h” … “001ECh” “001EDh” “001EEh” “001EFh”
G3 G318 “00200h” “00201h” “00202h” “00203h” … “002ECh” “002EDh” “002EEh” “002EFh”
G4 G317 “00300h” “00301h” “00302h” “00303h” … “003ECh” “003EDh” “003EEh” “003EFh”
G5 G316 “00400h” “00401h” “00402h” “00403h” … “004ECh” “004EDh” “004EEh” “004EFh”
G6 G315 “00500h” “00501h” “00502h” “00503h” … “005ECh” “005EDh” “005EEh” “005EFh”
G7 G314 “00600h” “00601h” “00602h” “00603h” … “006ECh” “006EDh” “006EEh” “006EFh”
G8 G313 “00700h” “00701h” “00702h” “00703h” … “007ECh” “007EDh” “007EEh” “007EFh”
G9 G312 “00800h” “00801h” “00802h” “00803h” … “008ECh” “008EDh” “008EEh” “008EFh”
G10 G311 “00900h” “00901h” “00902h” “00903h” … “009ECh” “009EDh” “009EEh” “009EFh”
. . . . . . … . . . .
. . . . . . . . . .
. . . . . . . . . .
G311 G10 “13600h” “13601h” “13602h” “13603h” … “136ECh” “136EDh” “136EEh” “136EFh”
G312 G9 “13700h” “13701h” “13702h” “13703h” … “137ECh” “137EDh” “137EEh” “137EFh”
G313 G8 “13800h” “13801h” “13802h” “13803h” … “138ECh” “138EDh” “138EEh” “138EFh”
G314 G7 “13900h” “13901h” “13902h” “13903h” … “139ECh” “139EDh” “139EEh” “139EFh”
G315 G6 “13A00h” “13A01h” “13A02h” “13A03h” … “13AECh” “13AEDh” “13AEEh” “13AEFh”
G316 G5 “13B00h” “13B01h” “13B02h” “13B03h” … “13BECh” “13BEDh” “13BEEh” “13BEFh”
G317 G4 “13C00h” “13C01h” “13C02h” “13C03h” … “13CECh” “13CEDh” “13CEEh” “13CEFh”
G318 G3 “13D00h” “13D01h” “13D02h” “13D03h” … “13DECh” “13DEDh” “13DEEh” “13DEFh”
G319 G2 “13E00h” “13E01h” “13E02h” “13E03h” … “13EECh” “13EEDh” “13EEEh” “13EEFh”
G320 G1 “13F00h” “13F01h” “13F02h” “13F03h” … “13FECh” “13FEDh” “13FEEh” “13FEFh”

i80/M68 system 18-bit data bus interface

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (528-3n) S (527-3n) S (526-3n)

N=0 to 175

i80/M68 system 9-bit data bus interface

1st Transfer 2nd Transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9

RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

Source Output Pin S (528-3n) S (527-3n) S (526-3n)

N=0 to 175

GRAM Data and display data of 18-/9-bit system interface (SS=”1", BGR=”1")

Figure 34 i80-System Interface with 18-/9-bit Data Bus (SS=”1”, BGR=”1”)

[Window address setting area]

(Horizontal direction) 00H ≤ HSA[7:0] ≤ HEA[7:0] ≤ “EF”H
(Vertical direction) 00H ≤ VSA[8:0] ≤ VEA[8:0]≤ “13F”H
[RAM address, AD (an address within a window address area)]]
(RAM address) HSA[7:0] ≤ AD[7:0] ≤ HEA[7:0]
VSA[8:0] ≤ AD[15:8] ≤ VEA[8:0]

GRAM Address Map

“00000”h “000EF”h

Window Address Area

2010h 203Fh
2110h 213Fh

4F10h 4F3Fh

“13F00”h “13FEF”h

Window address setting area

HSA[7:0] = 10h, HSA[7:0] = 3Fh, I/D = 1 (increment)

VSA[8:0] = 20h, VSA[8:0] = 4Fh, AM = 0 (horizontal writing)
Figure 35 GRAM Access Window Map
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 86 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320

Gradient Amplitude
Adjustment Fine Adjustment Registers (6 x 3 bits) Adjustment
Register Register
VREG1OUT PRP/N0 PRP/N1 PKP/N5 PKP/N4 PKP/N3 PKP/N2 PKP/N1 PKP/N0 VRP/N0 VRP/N1

VgP0/VgN0
V0

selection
8 to 1 VgP1/VgN1
V1
V2

…...
V7
selection

VgP8/VgN8
8 to 1

…...
selection

VgP20/VgN20
8 to 1

V20

…...
selection

VgP43/VgN43
8 to 1

V43

…...
selection

VgP55/VgN55
8 to 1

V55
V56
…...

V61
selection

VgP62/VgN62
8 to 1

V62

VgP63/VgN63
V63

VGS

Figure 36 Grayscale Voltage Generation

VgP0 VgN0
VROP0 VRON0
VRP0[4:0] VRN0[4:0]
0 ~ 30R 0 ~ 30R
1uF/10V
5R RP0
PKP0[2:0] 5R RN0
PKN0[2:0]
VP1 VN1
RP1 VP2 RN1 VN2

{ RP2 VP3

{ RN2 VN3

Selection

Selection
RP3 VP4 RN3 VN4

8 to 1

8 to 1
4R RP4 VP5 VgP1 4R RN4 VN5 VgN1
RP5 VP6 RN5 VN6
RP6 VP7 RN6 VN7
RP7 VP8 RN7 VN8

VRCP0 VRCP0
PRP0[2:0] PRN0[2:0]
0 ~ 28R PKP1[2:0] 0 ~ 28R PKN1[2:0]
VP9 VN9
RP8 VP10 RN8 VN10

{ RP9 VP11

Selection
{ RN9 VN11

Selection
RP10 VP12 RN10 VN12
8 to 1

8 to 1
1R RP11 VP13 VgP8 1R RN11 VN13 VgN8
RP12 VP14 RN12 VN14
RP13 VP15 RN13 VN15
RP14 VP16 RN14 VN16

RP15 PKP2[2:0] RN15 PKN2[2:0]

VP17 VN17
RP16 VP18 RN16 VN18

{ RP17 VP19

{ RN17 VN19
Selection

Selection
RP18 VP20 RN18 VN20
8 to 1

8 to 1
1R RP19 VP21 VgP20 1R RN19 VN21 VgN20
RP20 VP22 RN20 VN22
RP21 VP23 RN21 VN23
RP22 VP24 RN22 VN24

RP23 PKP3[2:0] RN23 PKN3[2:0]

VP25 VN25
RP24 VP26 RN24 VN26

{ RP25 VP27

{ RN25 VN27
Selection

Selection
RP26 VP28 RN26 VN28
8 to 1

8 to 1
1R RP27 VP29 VgP43 1R RN27 VN29 VgN43
RP28 VP30 RN28 VN30
RP29 VP31 RN29 VN31
RP30 VP32 RN30 VN32

RP31 PKP4[2:0] RN31 PKN4[2:0]

VP33 VN33
RP32 VP34 RN32 VN34

{ RP33 VP35

{ RN33 VN35
Selection

Selection
RP34 VP36 RN34 VN36
8 to 1

1R VP37 1R VN37
8 to 1
RP35 VgP55 RN35 VgN55
RP36 VP38 RN36 VN38
RP37 VP39 RN37 VN39
RP38 VP40 RN38 VN40

VRCP1 VRCN1
PRP1[2:0] PRN1[2:0]
0 ~ 28R PKP5[2:0] 0 ~ 28R PKN5[2:0]
VP41 VN41
RP39 VP42 RN39 VN42

{ RP40 VP43

{ RN40 VN43
Selection

Selection

RP41 VP44 RN41 VN44

8 to 1

4R RP42 VP45 VgP62 4R RN42 VN45 VgN62

RP43 VP46 RN43 VN46
RP44 VP47 RN44 VN47
RP45 VP48 RN45 VN48

5R RP46 5R RN46
VP49 VN49
VgP63 VgN63
VROP1 VRON1
VRP1[4:0] VRN1[4:0]
0 ~ 31R 0 ~ 31R

RP47 RN47
8R 8R
VGS

Figure 37 Grayscale Voltage Adjustment

2. Amplitude adjustment registers

The amplitude adjustment registers, VRP0[4:0]/VRN0[4:0], VRP1[4:0]/VRN1[4:0], are used to adjust the
amplitude of grayscale voltages. To adjust the amplitude, the resistance values of variable resistors at the top
and bottom of the ladder resistor are adjusted. Same as the gradient registers, the amplitude adjustment
registers consist of positive and negative polarity registers.

3. Fine adjustment registers

The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale
voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register
generated from the ladder resistor, in respective 8-to-1 selectors. Same with other registers, the fine
adjustment registers consist of positive and negative polarity registers.
Grayscale voltage

Grayscale voltage

Gradient adjustment Amplitude adjustment Fine adjustment

Figure 38 Gamma Curve Adjustment

Register Groups Positive Polarity Negative Polarity Description

Gradient PRP0 [2:0] PRN0 [2:0] Variable resistor VRCP0, VRCN0
adjustment PRP1 [2:0] PRN1 [2:0] Variable resistor VRCP1, VRCN1
Amplitude VRP0 [4:0] VRN0 [4:0] Variable resistor VROP0, VRON0
adjustment VRP1 [4:0] VRN1 [4:0] Variable resistor VROP1, VRON1
KP0 [2:0] KN0 [2:0] 8-to-1 selector (voltage level of grayscale 1)
KP1 [2:0] KN1 [2:0] 8-to-1 selector (voltage level of grayscale 8)
KP2 [2:0] KN2 [2:0] 8-to-1 selector (voltage level of grayscale 20)
Fine adjustment
KP3 [2:0] KN3 [2:0] 8-to-1 selector (voltage level of grayscale 43)
KP4 [2:0] KN4 [2:0] 8-to-1 selector (voltage level of grayscale 55)
KP5 [2:0] KN5 [2:0] 8-to-1 selector (voltage level of grayscale 62)

Ladder resistors and 8-to-1 selector Block configuration

The reference voltage generating block consists of two ladder resistor units including variable resistors and
8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor
unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled
according to the γ-correction registers. This unit has pins to connect a volume resistor externally to
compensate differences in various characteristics of panels.

Variable resistors
ILI9320 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1);
amplitude adjustment (1) (VROP(N)0); and the amplitude adjustment (2) (VROP(N)1). The resistance values
of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as
follows.

Gradient adjustment Amplitude adjustment (1) Amplitude adjustment (2)

PRP(N)0/1[2:0] VRCP(N)0 VRP(N)0[4:0] VROP(N)0 VRP(N)1[4:0] VROP(N)1
Register Resistance Register Resistance Register Resistance
000 0R 0000 0R 00000 0R
001 4R 0001 2R 00001 1R
010 8R 0010 4R 00010 2R
011 12R : : : :
100 16R : : : :
101 20R 1101 26R 11101 29R
110 24R 1111 28R 11110 30R
111 28R 1111 30R 11111 31R

8-to-1 selectors
The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the
fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6).
The table below shows the setting in the fine adjustment register and the selected voltage levels for
respective reference grayscale voltages.

Fine adjustment registers and selected voltage

Register Selected Voltage
KP(N)[2:0] VgP(N)1 VgP(N)8 VgP(N)20 VgP(N)43 VgP(N)55 VgP(N)62
000 VP(N)1 VP(N)9 VP(N)17 VP(N)25 VP(N)33 VP(N)41
001 VP(N)2 VP(N)10 VP(N)18 VP(N)26 VP(N)34 VP(N)42
010 VP(N)3 VP(N)11 VP(N)19 VP(N)27 VP(N)35 VP(N)43
011 VP(N)4 VP(N)12 VP(N)20 VP(N)28 VP(N)36 VP(N)44
100 VP(N)5 VP(N)13 VP(N)21 VP(N)29 VP(N)37 VP(N)45
101 VP(N)6 VP(N)14 VP(N)22 VP(N)30 VP(N)38 VP(N)46
110 VP(N)7 VP(N)15 VP(N)23 VP(N)31 VP(N)39 VP(N)47
111 VP(N)8 VP(N)16 VP(N)24 VP(N)32 VP(N)40 VP(N)48

Reference
Fine Adjustment Value Formula Vout
Voltage
VgP0 –––– VREG1OUT –VD*VROP0/sumRP VP0
KP0[2:0]=000 VREG1OUT –VD*(VROP0+5R)/sumRP VP1
KP0[2:0]=001 VREG1OUT –VD*(VROP0+9R)/sumRP VP2
KP0[2:0]=010 VREG1OUT –VD*(VROP0+13R)/sumRP VP3
KP0[2:0]=011 VREG1OUT –VD*(VROP0+17R)/sumRP VP4
VgP1
KP0[2:0]=100 VREG1OUT –VD*(VROP0+21R)/sumRP VP5
KP0[2:0]=101 VREG1OUT –VD*(VROP0+25R)/sumRP VP6
KP0[2:0]=110 VREG1OUT –VD*(VROP0+29R)/sumRP VP7
KP0[2:0]=111 VREG1OUT –VD*(VROP0+33R)/sumRP VP8
KP1[2:0]=000 VREG1OUT –VD*(VROP0+33R+VRCP0)/sumRP VP9
KP1[2:0]=001 VREG1OUT –VD*(VROP0+34R+VRCP0)/sumRP VP10
KP1[2:0]=010 VREG1OUT –VD*(VROP0+35R+VRCP0)/sumRP VP11
KP1[2:0]=011 VREG1OUT –VD*(VROP0+36R+VRCP0)/sumRP VP12
VgP8
KP1[2:0]=100 VREG1OUT –VD*(VROP0+37R+VRCP0)/sumRP VP13
KP1[2:0]=101 VREG1OUT –VD*(VROP0+38R+VRCP0)/sumRP VP14
KP1[2:0]=110 VREG1OUT –VD*(VROP0+39R+VRCP0)/sumRP VP15
KP1[2:0]=111 VREG1OUT –VD*(VROP0+40R+VRCP0)/sumRP VP16
KP2[2:0]=000 VREG1OUT –VD*(VROP0+45R+VRCP0)/sumRP VP17
KP2[2:0]=001 VREG1OUT –VD*(VROP0+46R+VRCP0)/sumRP VP18
KP2[2:0]=010 VREG1OUT –VD*(VROP0+47R+VRCP0)/sumRP VP19
KP2[2:0]=011 VREG1OUT –VD*(VROP0+48R+VRCP0)/sumRP VP20
VgP20
KP2[2:0]=100 VREG1OUT –VD*(VROP0+49R+VRCP0)/sumRP VP21
KP2[2:0]=101 VREG1OUT –VD*(VROP0+50R+VRCP0)/sumRP VP22
KP2[2:0]=110 VREG1OUT –VD*(VROP0+51R+VRCP0)/sumRP VP23
KP2[2:0]=111 VREG1OUT –VD*(VROP0+52R+VRCP0)/sumRP VP24
KP3[2:0]=000 VREG1OUT –VD*(VROP0+68R+VRCP0)/sumRP VP25
KP3[2:0]=001 VREG1OUT –VD*(VROP0+69R+VRCP0)/sumRP VP26
KP3[2:0]=010 VREG1OUT –VD*(VROP0+70R+VRCP0)/sumRP VP27
KP3[2:0]=011 VREG1OUT –VD*(VROP0+71R+VRCP0)/sumRP VP28
VgP43
KP3[2:0]=100 VREG1OUT –VD*(VROP0+72R+VRCP0)/sumRP VP29
KP3[2:0]=101 VREG1OUT –VD*(VROP0+73R+VRCP0)/sumRP VP30
KP3[2:0]=110 VREG1OUT –VD*(VROP0+74R+VRCP0)/sumRP VP31
KP3[2:0]=111 VREG1OUT –VD*(VROP0+75R+VRCP0)/sumRP VP32
KP4[2:0]=000 VREG1OUT –VD*(VROP0+80R+VRCP0)/sumRP VP33
KP4[2:0]=001 VREG1OUT –VD*(VROP0+81R+VRCP0)/sumRP VP34
KP4[2:0]=010 VREG1OUT –VD*(VROP0+82R+VRCP0)/sumRP VP35
KP4[2:0]=011 VREG1OUT –VD*(VROP0+83R+VRCP0)/sumRP VP36
VgP55
KP4[2:0]=100 VREG1OUT –VD*(VROP0+84R+VRCP0)/sumRP VP37
KP4[2:0]=101 VREG1OUT –VD*(VROP0+85R+VRCP0)/sumRP VP38
KP4[2:0]=110 VREG1OUT –VD*(VROP0+86R+VRCP0)/sumRP VP39
KP4[2:0]=111 VREG1OUT –VD*(VROP0+87R+VRCP0)/sumRP VP40
KP5[2:0]=000 VREG1OUT –VD*(VROP0+87R+VRCP0+VRCP1)/sumRP VP41
KP5[2:0]=001 VREG1OUT –VD*(VROP0+91R+VRCP0+VRCP1)/sumRP VP42
KP5[2:0]=010 VREG1OUT –VD*(VROP0+95R+VRCP0+VRCP1)/sumRP VP43
KP5[2:0]=011 VREG1OUT –VD*(VROP0+99R+VRCP0+VRCP1)/sumRP VP44
VgP62
KP5[2:0]=100 VREG1OUT –VD*(VROP0+103R+VRCP0+VRCP1)/sumRP VP45
KP5[2:0]=101 VREG1OUT –VD*(VROP0+107R+VRCP0+VRCP1)/sumRP VP46
KP5[2:0]=110 VREG1OUT –VD*(VROP0+111R+VRCP0+VRCP1)/sumRP VP47
KP5[2:0]=111 VREG1OUT –VD*(VROP0+115R+VRCP0+VRCP1)/sumRP VP48

Formulae for calculating voltage (Positive polarity)

Grayscale Voltage Formula Grayscale Voltage Formula
V0 VgP0 V32 V43+(V20–V43)*(11/23)
V1 VgP1 V33 V43+(V20–V43)*(10/23)
V2 V3+(V1–V3)*(8/24) V34 V43+(V20–V43)*(9/23)
V3 V8+(V1–V8)*(450/800) V35 V43+(V20–V43)*(8/23)
V4 V8+(V3–V8)*(16/24) V36 V43+(V20–V43)*(7/23)
V5 V8+(V3–V8)*(12/24) V37 V43+(V20–V43)*(6/23)
V6 V8+(V3–V8)*(8/24) V38 V43+(V20–V43)*(5/23)
V7 V8+(V3–V8)*(4/24) V39 V43+(V20–V43)*(4/23)
V8 VgP8 V40 V43+(V20–V43)*(3/23)
V9 V20+(V8–V20)*(22/24) V41 V43+(V20–V43)*(2/23)
V10 V20+(V8–V20)*(20/24) V42 V43+(V20–V43)*(1/23)
V11 V20+(V8–V20)*(18/24) V43 VgP43
V12 V20+(V8–V20)*(16/24) V44 V55+(V43–V55)*(22/24)
V13 V20+(V8–V20)*(14/24) V45 V55+(V43–V55)*(20/24)
V14 V20+(V8–V20)*(12/24) V46 V55+(V43–V55)*(18/24)
V15 V20+(V8–V20)*(10/24) V47 V55+(V43–V55)*(16/24)
V16 V20+(V8–V20)*(8/24) V48 V55+(V43–V55)*(14/24)
V17 V20+(V8–V20)*(6/24) V49 V55+(V43–V55)*(12/24)
V18 V20+(V8–V20)*(4/24) V50 V55+(V43–V55)*(10/24)
V19 V20+(V8–V20)*(2/24) V51 V55+(V43–V55)*(8/24)
V20 VgP20 V52 V55+(V43–V55)*(6/24)
V21 V43+(V20–V43)*(22/23) V53 V55+(V43–V55)*(4/24)
V22 V43+(V20–V43)*(21/23) V54 V55+(V43–V55)*(2/24)
V23 V43+(V20–V43)*(20/23) V55 VgP55
V24 V43+(V20–V43)*(19/23) V56 V60+(V55–V60)*(20/24)
V25 V43+(V20–V43)*(18/23) V57 V60+(V55–V60)*(16/24)
V26 V43+(V20–V43)*(17/23) V58 V60+(V55–V60)*(12/24)
V27 V43+(V20–V43)*(16/23) V59 V60+(V55–V60)*(8/24)
V28 V43+(V20–V43)*(15/23) V60 V62+(V55–V62)*(350/800)
V29 V43+(V20–V43)*(14/23) V61 V62+(V60–V62)*(16/24)
V30 V43+(V20–V43)*(13/23) V62 VgP62
V31 V43+(V20–V43)*(12/23) V63 VgP63
Note: The following condition shall be always retained.
DDVDH – V0 > 0.5V
DDVDH – V8 > 1.1V
V55 – AGND > 1.1V

Grayscale Voltage Formula Grayscale Voltage Formula

V0 VgN0 V32 V43+(V20–V43)*(11/23)
V1 VgN1 V33 V43+(V20–V43)*(10/23)
V2 V3+(V1–V3)*(8/24) V34 V43+(V20–V43)*(9/23)
V3 V8+(V1–V8)*(450/800) V35 V43+(V20–V43)*(8/23)
V4 V8+(V3–V8)*(16/24) V36 V43+(V20–V43)*(7/23)
V5 V8+(V3–V8)*(12/24) V37 V43+(V20–V43)*(6/23)
V6 V8+(V3–V8)*(8/24) V38 V43+(V20–V43)*(5/23)
V7 V8+(V3–V8)*(4/24) V39 V43+(V20–V43)*(4/23)
V8 VgN8 V40 V43+(V20–V43)*(3/23)
V9 V20+(V8–V20)*(22/24) V41 V43+(V20–V43)*(2/23)
V10 V20+(V8–V20)*(20/24) V42 V43+(V20–V43)*(1/23)
V11 V20+(V8–V20)*(18/24) V43 VgN43
V12 V20+(V8–V20)*(16/24) V44 V55+(V43–V55)*(22/24)
V13 V20+(V8–V20)*(14/24) V45 V55+(V43–V55)*(20/24)
V14 V20+(V8–V20)*(12/24) V46 V55+(V43–V55)*(18/24)
V15 V20+(V8–V20)*(10/24) V47 V55+(V43–V55)*(16/24)
V16 V20+(V8–V20)*(8/24) V48 V55+(V43–V55)*(14/24)
V17 V20+(V8–V20)*(6/24) V49 V55+(V43–V55)*(12/24)
V18 V20+(V8–V20)*(4/24) V50 V55+(V43–V55)*(10/24)
V19 V20+(V8–V20)*(2/24) V51 V55+(V43–V55)*(8/24)
V20 VgN20 V52 V55+(V43–V55)*(6/24)
V21 V43+(V20–V43)*(22/23) V53 V55+(V43–V55)*(4/24)
V22 V43+(V20–V43)*(21/23) V54 V55+(V43–V55)*(2/24)
V23 V43+(V20–V43)*(20/23) V55 VgN55
V24 V43+(V20–V43)*(19/23) V56 V60+(V55–V60)*(20/24)
V25 V43+(V20–V43)*(18/23) V57 V60+(V55–V60)*(16/24)
V26 V43+(V20–V43)*(17/23) V58 V60+(V55–V60)*(12/24)
V27 V43+(V20–V43)*(16/23) V59 V60+(V55–V60)*(8/24)
V28 V43+(V20–V43)*(15/23) V60 V62+(V55–V62)*(350/800)
V29 V43+(V20–V43)*(14/23) V61 V62+(V60–V62)*(16/24)
V30 V43+(V20–V43)*(13/23) V62 VgN62
V31 V43+(V20–V43)*(12/23) V63 VgN63
Relationship between RAM data and voltage output levels (REV = “0”)

Source
Driver
Output
(S[384:1])

VCOM

Negative polarity Postive polarity

Figure 39 Relationship between Source Output and VCOM

Negative Polarity
Source Output Levels

Positive Polarity

V63

000000 111111
GRAM Data

Figure 40 Relationship between GRAM Data and Output Level

1
G2
DUMMYR2
TESTO1 G4
VCCDUM1 G6
VPP1 G8
VPP1 < 25 ohm VPP1 G10
VPP1
VPP2
VPP2
VPP2 < 25 ohm VPP2

0
1
VPP2
VPP2
VPP3
VPP3 < 25 ohm VPP3

……………………….
……………………….
VPP3
TESTO2
IOGNDDUM1
TESTO3
TEST1
IOVCC TEST2

0
2
< 100 ohm TEST4
TEST5
TEST3
IM0 < 100 ohm IM0/ID
IM1 < 100 ohm IM1
IM2 < 100 ohm IM2
IM3 < 100 ohm IM3
TESTO4
IOVCCDUM1
TESTO5

0
3
nRESET < 100 ohm nRESET
VSYNC < 100 ohm VSYNC
HSYNC < 100 ohm HSYNC
DOTCLK < 100 ohm DOTCLK
ENABLE < 100 ohm ENABLE
G312
DB17 < 100 ohm DB17 G314
DB16 < 100 ohm DB16 G316
DB15 < 100 ohm DB15 G318
DB14 < 100 ohm DB14 G320
DB13 < 100 ohm DB13 VGLDMY3

0
4
DB12 < 100 ohm DB12 TESTO36
DB11 < 100 ohm DB11
DB10 < 100 ohm DB10
DB9 < 100 ohm DB9
DB8

220um
< 100 ohm DB8
TESTO6
IOGNDDUM2
TESTO7
DB7 < 100 ohm DB7
DB6 < 100 ohm

0
5
DB6
DB5 < 100 ohm DB5 TESTO35
DB4 < 100 ohm DB4 S1
DB3 < 100 ohm DB3 S2
DB2 < 100 ohm DB2
S3
DB1 < 100 ohm DB1
S4
DB0 < 100 ohm DB0
SDO < 100 ohm SDO S5
SDI < 100 ohm SDI S6
nRD < 100 ohm nRD S7
nWR < 100 ohm nWR/SCL

0
6
S8
RS < 100 ohm RS S9
nCS < 100 ohm nCS
TESTO8
IOVCCDUM2
TESTO9
FLM < 100 ohm FMARK
TS8
TS7
TS6
TS5
0
7
TS4
TS3
TS2
TS1
TS0
TSC
TESTO10
IOGNDDUM3
TESTO11
TESTO12
0
8

150K ohm OSC1DUM1

OSC1DUM2
< 100 ohm OSC1
OSC1DUM3
OSC1DUM4
< 100 ohm OSC2
OSC2DUM1
OSC2DUM2
DUMMYR3
DUMMYR4
0
9

IOGND
IOGND
IOGND
< 10 ohm IOGND
IOGND
IOGND
IOGND
IOVCC
IOVCC
IOVCC
0
0
1

IOVCC < 10 ohm IOVCC

IOVCC
(Bump View)

IOVCC
IOVCC
VCC
VCC
VCC
Face Up

VCC
VCC < 5 ohm VCC
VCC
0
1
1

VCC
VCC
VDD
VDD
VDD

………………………………………………………………………………………………..
………………………………………………………………………………………………..

VDD

1uF/6.3V VDD
VDD
< 5 ohm VDD
VDD
0
2
1

VDD
VDD
VDD
VDD
VDD
TESTO13
VREFD
TESTO14
VREF
TESTO15
0
3
1

VREFC
TESTO16
VDDTEST
AGND
AGND
AGND
AGND
AGND
AGND
< 5 ohm AGND
0
4
1

AGND
AGND
Y

AGND
AGND
GND
GND
GND
GND
GND
GND
0
5
1

GND
< 5 ohm GND
GND
GND
GND
GND
GND
GND
GND
GND
0
6
1

TESTO17
VTEST
TESTO18
< 100 ohm VGS
TESTO19
V0T
TESTO20
VMON
TESTO21
V31T
0
7
1

VCOM
VCOM
VCOM
< 10 ohm VCOM
VCOM
VCOM
VCOMH
VCOMH
1uF/6.3V < 10 ohm
VCOMH
VCOMH
0
8
1

VCOMH
VCOMH
VCOML
1uF/6.3V VCOML
VCOML
< 10 ohm VCOML
VCOML
VCOML
TESTO22
1uF/6.3V TESTO23
0
9
1

< 50 ohm VREG1OUT

TESTO24
TESTA5
TESTO25
< 50 ohm VCOMR
TESTO26
1uF/6.3V VCL
< 25 ohm VCL
VCL
VLOUT1
0
0
2

VLOUT1
VLOUT1
1uF/6.3V < 5 ohm
DDVDH
DDVDH
S712
DDVDH S713
DDVDH S714
DDVDH S715
DDVDH S716
DDVDH S717
VCIOUT
0
1
2

S718
VCIOUT S719
1uF/6.3V VCIOUT S720
< 5 ohm VCI1
TESTO34
VCI1
VCI1
VCI1
VCI1
220um

< 100 ohm VCILVL

VCI
VCI
0
2
2

VCI
VCC < 5 ohm VCI
VCI
TESTO33
VCI
VCI VGLDMY2
VCI G319
G317
1uF/10V
C12-
C12- G315
< 15 ohm C12-
C12-
G313
0
3
2

G311
C12-
C12+
C12+
< 15 ohm C12+
C12+
C12+
C11-
1uF/10V C11-
< 15 ohm C11-
C11-
0
4
2

C11-
C11+
C11+
………………………………………………………………………………………...

………………………………………………………………………………………...

< 15 ohm C11+

C11+
C11+
AGNDDUM1
VLOUT3
VLOUT3
VGL
0
5
2

1uF/25V VGL
VGL
< 10 ohm VGL
VGL
VGL
VGL
VGL
VGL
VGL
AGNDDUM2
Vci
0
6
2

AGNDDUM3
AGNDDUM4
VLOUT2
VLOUT2
1uF/25V < 20 ohm VGH
VGH
VGH
VGH
TESTO27
1uF/10V C13-
0
7
2

< 20 ohm C13-

C13-
TESTO28
C13+
< 20 ohm C13+
C13+
1uF/10V TESTO29
C21-
< 20 ohm C21-
C21-
0
8
2

C21+
< 20 ohm C21+
C21+
1uF/10V < 20 ohm
C22-
C22-
C22-
C22+
< 20 ohm C22+
C22+
1uF/10V C23-
0
9
2

< 20 ohm C23-

C23-
C23+ G9
< 20 ohm C23+ G7
C23+ G5
TESTO30
G3
DUMMYR5
DUMMYR6 G1
8
9
2

VGLDMY1
DUMMYR8
DUMMYR7
TESTO32
TESTO31

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
(1-b)

reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 98 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
Figure 41 Power Supply Circuit Block

The following table shows specifications of external elements connected to the ILI9320’s power supply circuit.
Items Recommended Specification Pin connection

VREG1OUT, VCI1, VDD, VCL, VCOMH,

6V
Capacity VCOML, C11+/-, C12+/-
1 µF (B characteristics) 10V DDVDH, C21+/-, C22+/-

25V VGH, VGL

Schottky diode VF<0.4V/20mA at 25°C, VR ≥30V
(AGND – VGL), (Vci – VGH), (Vci – DDVDH)
(Recommended diode: HSC226)

Variable resistor > 200 kΩ VCOMR

Display Off Flow Display On Flow

Set EQ = 0 Power Setting

Set SAP[2:0]
Display OFF

GON = 1
DTE = 1 Display On
D[1:0] = 10
GON = 0
DTE = 0
D[1:0] = 01

Wait for 2 frames

or more
Wait for 2 frames
or more

Display OFF
Display On
GON = 1
DTE = 0
GON = 1
D[1:0] = 10
DTE = 0
D[1:0] = 01

Wait for 2 frames

or more Display On

GON = 1
DTE = 0
D[1:0] = 11
Display OFF

GON = 0
DTE = 0
D[1:0] = 00 Wait for 2 frames
or more

Display Supply Off

Display On
SAP[2:0] = 000
AP[2:0] = 000 GON = 1
PON = 0 DTE = 1
VCOMG=0 D[1:0] = 11

Display Off Display ON

Figure 42 Display On/Off Register Setting Sequence

Standby Sleep

Display Off Sequence Display Off Sequence

Set Standby (STB = 1) Set Sleep (SLP = 1)

Start Oscillation Release

Release from Sleep
(SLP = 0)
from
Sleep
Release
Wait for 10 ms from
Power Supply Seeting
standby

Release from Standby

(STB = 0) Display On Sequence

Power Supply Seeting

Display On Sequence

Figure 43 Standby/Sleep Mode Register Setting Sequence

Display ON Setting
Power Supply ON (VCC, VCI, IOVCC)
Normal Display DTE=1
D[1:0]=11
VCC IOVCC VCI GON=1

GND
Display OFF
VCC IOVCC VCI or
Sequence
VCC, IOVCC, VCI Simultaneously

Display OFF Setting

DTE = 0
1ms or more Power On Reset D[1:0] = 00
and GON = 0
Display OFF
Display OFF PON = 0
VCOMG = 0
10ms or more
Oscillator
Stabilizing time
SAP[2:0] = 000
LCD Power Registers setting Power Supply AP[2:0] = 000
Power supply initial setting
Supply ON before power supply Set VC[2:0], VRH[3:0], VCM[4;0], Halt Setting PON = 0
VCOMG = 0
Sequence startup VDV[4:0], PON=0, DK=1

Power supply operation setting (1)

Registers setting for BT[2:0] = 000 Power Supply OFF (VCC, VCI, IOVCC)
power supply startup Set DC1[2:0], DC0[2:0]
(1) PON = 1
Set AP[2:0] VCI IOVCC VCC
40ms or more
Step-up circuit GND
stabilizing time VCI IOVCC VCC or

Power supply operation setting (2) VCC, IOVCC, VCI Simultaneously

Registers setting for
power supply startup Set BT[2:0]
DK=0
(2) VCOMG=1 Power OFF Sequence
Operational
Amplifier
stabilizing time Set the other
registers

Display ON
Set SAP[2:0]
Sequence

DTE=1
Display ON D[1:0]=11
GON=1

Power ON Sequence

Figure 44 Power Supply ON/OFF Sequence

BT VGH
VGH (+9 ~ 16.5V)

DDVDH
VLCD (4.5 ~ 5.5V)
VRH
VGAM1OUT (3.0 ~ (VLCD-0.5)V )
VCM/VcomR
VCOMH (3.0 ~ (VLCD-0.5)V )
REGP, VDV
(2.5 ~ 3.3V) VC VCI1
Vci

VciLVL

VCOML (VCL+0.5) ~ -1V )

VCOMG VCL
VCL (0 ~ -3.3V)

BT VGL
VGL (-4.0 ~ -16.5V)

Figure 45 Voltage Configuration Diagram

Note: The DDVDH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal
voltage levels) due to current consumption at respective outputs. The voltage levels in the following
relationships (DDVDH – VREG1OUT ) > 0.5V, (VCOML1 – VCL) > 0.5V, (VCOML2 – VCL) > 0.5V are the
actual voltage levels. When the alternating cycles of VCOM are set high (e.g. the polarity inverts every line
cycle), current consumption is large. In this case, check the voltage before use.

VGH

Gate
Output
Source
VCOM
output

VGL

Figure 46 Voltage Output to TFT LCD Panel

12.7. Oscillator
ILI9320 generates oscillation with the ILI9320’s internal RC oscillators by placing an external resistor between
the OSC1 and OSC2 pins. The oscillation frequency varies with resistance value of external resistor, wiring
distance, and operating supply voltage. For example, placing a Rosc resistor of larger resistance value or
lower the supply voltage level will generate a lower oscillation frequency. See the “Notes to Electrical
Characteristics” section for the relationship between resistance value of Rosc resistor and oscillation
frequency.

External Input Clock Example. Internal RC Oscillator Example

OSC1
External
OSC1
Clock Rosc
Damping
Resistor (2K AGND
ohm) Rosc shall be placed
AGND
as close to OSC1 and
AGND as possible.

Figure 47 Oscillation Connection

12.8. Frame Rate Adjustment

The ILI9320 has a frame frequency adjustment function. The frame frequency for driving LCDs can be
adjusted by registers (using the DIV, RTN bits) without changing the oscillation frequency.
To switch frame frequencies between when displaying a moving picture and when displaying a still picture,
set a high oscillation frequency in advance. By doing so, it becomes possible to set a low frame frequency
when displaying a still picture for saving power consumption and to set a high frame frequency when
displaying a moving picture.

Relationship between Liquid Crystal Drive Duty and Frame Frequency

The relationship between the liquid crystal drive duty and the frame frequency is calculated from the following
formula. The frame frequency is adjusted by register using the 1H period adjustment bits (RTN bits) and the
operation clock division bits (DIV bits).

Formula to calculate frame frequency

fosc.
Formula rate =
Clock cycles per line x division ratio x (Lines +BP+FP)

fosc. : frequency if RC oscillation.

Clock cycles per line : RTN bits
Division ratio : DIV bits
Lines : number of lines for driving the LCD panel.
FP: Front porch lines
BP; Back porch lines

Example of Calculation: when maximum frame frequency = 60 Hz

Number of lines to drive the LCD: 320 lines
1H period: 16 clock cycle (RTNI[4:0] = “00000”)
Operational clock division ratio: 1/1
fosc = 60 Hz × (0 + 16) clock × 1/1 × (320 + 16) lines = 322.56 (kHz)
In this case, the RC oscillation frequency is 322.56kHz. Adjust the external resistor of the RC oscillator to
322.56kHz.

12.9. Partial Display Function

The ILI9320 allows selectively driving two partial images on the screen at arbitrary positions set in the screen
drive position registers.
The following example shows the setting for partial display function:

Base Image Display Setting

BASEE 0
NL[5:0] 6’h27

GRAM MAP LCD Panel

PTSA0=9'h000 0 (1st line)
1 (2nd line)
Partial Image 1 2 (3rd line)

GRAM Area
PTEA0=9'h00F

PTSA1=9'h020
PTDP0=9'h080
Partial Image 2
Partial Image 1
GRAM Area
Display Area
PTEA1=9'h02F

PTDP1=9'h0C0
Partial Image 1
Display Area

319 (320th line)

Figure 48 Partial Display Example

12.10. Resizing Function

ILI9320 supports resizing function (x1/2, x1/4), which is performed when writing image data to GRAM. The
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 106 of 115 Version: 0.41
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color ILI9320
resizing function is enabled by setting a window address area and the RSZ bit which represents the resizing
factor (x1/2, x1/4) of image. The resizing function allows the system to transfer the original-size image data
into the GRAM with resized image data.

Original Image Data GRAM Data

0 1 2 3 4 5 6
0 (0,0) (0,1) (0,2) (0,3) (0,4) (0,5) (0,6)
1 (1,0) (1,1) (1,2) (1,3) (1,4) (1,5) (1,6) (0,0) (0,2) (0,4) (0,6)
2 (2,0) (2,1) (2,2) (2,3) (2,4) (2,5) (2,6) (2,0) (2,2) (2,4) (2,6)
? resizing
3 (3,0) (3,1) (3,2) (3,3) (3,4) (3,5) (3,6) (4,0) (4,2) (4,4) (4,6)
4 (4,0) (4,1) (4,2) (4,3) (4,4) (4,5) (4,6) (6,0) (6,2) (6,4) (6,6)
5 (5,0) (5,1) (5,2) (5,3) (5,4) (5,5) (5,6)
6 (6,0) (6,1) (6,2) (6,3) (6,4) (6,5) (6,6)

Figure 49 Data transfer in resizing

Original Data
Panel Display
240

120

RSZ=2'h1
320

160

Write to GRAM

Figure 50 Resizing Example

Resized Image Resolution

Original Image Size (X × Y)
1/2 (RSZ=2’h1) 1/4 (RSZ=2’h3)
640 × 480 320 × 240 160 × 120
352 × 288 176 × 144 88 × 72
320 × 240 160 × 120 80× 60
176 × 144 88 × 72 44× 36
120 × 160 60× 80 30 × 40
132 × 132 66 × 66 33 × 33

X
GRAM Address

dx= (X-H)/N, H=X mod N

dy= (Y-V)/N, V=Y mod N
(X0, Y0) dx

Y Original Image dy
Size

(X0+dx-1, Y0+dy-1)

Original image data number in horizontal direction X

Original image data number in Vertical direction Y
Resizing Ration 1/N
Resizing Setting RSZ N-1
Remainder pixels in horizontal direction RCH H
Remainder pixels in vertical direction RCV V
GRAM writing start address AD (x0, y0)
HSA x0
HEA x0+dx-1
GRAM window setting
VSA y0
VEA y0+dy-1

13.1. Absolute Maximum Ratings

The absolute maximum rating is listed on following table. When ILI9320 is used out of the absolute maximum
ratings, the ILI9320 may be permanently damaged. To use the ILI9320 within the following electrical
characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions
are exceeded during normal operation, the ILI9320 will malfunction and cause poor reliability.

Item Symbol Unit Value Note

Power supply voltage (1) VCC, IOVCC V -0.3 ~ + 4.6 1, 2
Power supply voltage (1) VCI - AGND V -0.3 ~ + 4.6 1, 4
Power supply voltage (1) DDVDH - AGND V -0.3 ~ + 6.0 1, 4
Power supply voltage (1) AGND -VCL V -0.3 ~ + 4.6 1
Power supply voltage (1) DDVDH - VCL V -0.3 ~ + 9.0 1, 5
Power supply voltage (1) VGH - AGND V -0.3 ~ + 18.5 1, 5
Power supply voltage (1) AGND - VGL V -0.3 ~ + 18.5 1, 6
Input voltage Vt V -0.3 ~ VCC+ 0.3 1
Operating temperature Topr °C -40 ~ + 85 8, 9
Storage temperature Tstg °C -55 ~ + 110 8, 9
Notes:
1. VCC,DGND must be maintained
2. (High) (VCC = VCC) ≥ DGND (Low), (High) IOVCC ≥ DGND (Low).
3. Make sure (High) VCI ≥ DGND (Low).
4. Make sure (High) DDVDH ≥ ASSD (Low).
5. Make sure (High) DDVDH ≥ VCL (Low).
6. Make sure (High) VGH ≥ ASSD (Low).
7. Make sure (High) ASSD ≥ VGL (Low).
8. For die and wafer products, specified up to 85°C.
9. This temperature specifications apply to the TCP package

13.3. Clock Characteristics

VCC = 2.40 ~ 3.30V, IOVCC = 1.65 ~ 3.30V
Item Symbol Test Condition Min. Typ. Max. Unit
External Clock Frequency fcp VCC = 2.4 ~ 3.3V 275 335 395 KHz
External Clock Duty fDuty VCC = 2.4 ~ 3.3V 45 50 55
External Clock Rising Time Trcp VCC = 2.4 ~ 3.3V - - 0.2 µs
External Clock Falling Time Tfcp VCC = 2.4 ~ 3.3V - - 0.2 µs
RC oscillation clock fOSC Rf = 130KΩ, VCC = 2.8V 275 335 395 KHz

13.4. Reset Timing Characteristics

Reset Timing Characteristics (VCC = 1.8 ~ 3.3 V, IOVCC = 1.65 ~ 3.3 V)

Item Symbol Unit Min. Typ. Max.
Reset low-level width tRES ms 1 - -
Reset rise time trRES µs - - 10

trRES
tRES
VIH
nRESET
VIL

13.5. LCD Driver Output Characteristics

13.6. AC Characteristics

13.6.1. i80-System Interface Timing Characteristics

Normal Write Mode (IOVCC = 1.65~3.3V, VCC=2.4~3.3V)

Item Symbol Unit Min. Typ. Max. Test Condition
Write tCYCW ns 100 - - -
Bus cycle time
Read tCYCR ns 300 - - -
Write low-level pulse width PWLW ns 50 - 500 -
Write high-level pulse width PWHW ns 50 - - -
Read low-level pulse width PWLR ns 150 - - -
Read high-level pulse width PWHR ns 150 - -
Write / Read rise / fall time tWRr/tWRf ns - - 25
Write ( RS to nCS, E/nWR ) 10 - -
Setup time tAS ns
Read ( RS to nCS, RW/nRD ) 5 - -
Address hold time tAH ns 5 - -
Write data set up time tDSW ns 10 - -
Write data hold time tH ns 15 - -
Read data delay time tDDR ns - - 100
Read data hold time tDHR ns 5 - -

VIH VIH
RS
VIL VIL
tAS tAH

nCS

PWLW, PWLR PWHW, PWHR

VIH VIH VIH

nWR, nRD VIL
VIL
tWRf tWRr tCYCW, tCYCR

tDSW tH

Write Data VIH VIH

Valid Data
DB[17:0] VIL VIL

tDDR tDHR

Read Data VOH VOH

DB[17:0] Valid Data VOL
VOL

Figure 51 i80-System Bus Timing

13.6.2. Serial Data Transfer Interface Timing Characteristics

(IOVCC= 1.653.3V and VCC=2.4~3.3V)

Item Symbol Unit Min. Typ. Max. Test Condition
Write ( received ) tSCYC µs 100 - -
Serial clock cycle time
Read ( transmitted ) tSCYC µs 200 - -
Serial clock high – level Write ( received ) tSCH ns 40 - -
pulse width Read ( transmitted ) tSCH ns 100 - -
Serial clock low – level Write ( received ) tSCL ns 40 - -
pulse width Read ( transmitted ) tSCL ns 100 - -
Serial clock rise / fall time tSCr, tSCf ns - - 5
Chip select set up time tCSU ns 10 - -
Chip select hold time tCH ns 50 - -
Serial input data set up time tSISU ns 20 - -
Serial input data hold time tSIH ns 20 - -
Serial output data set up time tSOD ns - - 100
Serial output data hold time tSOH ns 5 - -

VIH
nCS
VIL

tCSU tSCYC
tSCH
tSCr tSCf tSCL tCH
VIH VIH VIH VIH
SCL
VIL VIL VIL VIL

tSISU tSIH

VIH VIH
SDI Input Data Input Data
VIL VIL

tSOD

VOH VOH VOH

SDO Output Data Output Data
VOL VOL VOL

Figure 52 SPI System Bus Timing

13.6.3. RGB Interface Timing Characteristics

18/16-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V, VCC=2.4~3.3V)

Item Symbol Unit Min. Typ. Max. Test Condition
VSYNC/HSYNC setup time tSYNCS ns 0 - - -
ENABLE setup time tENS ns 10 - - -
ENABLE hold time tENH ns 10 - - -
PD Data setup time tPDS ns 10 - - -
PD Data hold time tPDH ns 40 - - -
DOTCLK high-level pulse width PWDH ns 40 - - -
DOTCLK low-level pulse width PWDL ns 40 - - -
DOTCLK cycle time tCYCD ns 100 - - -
DOTCLK, VSYNC, HSYNC, rise/fall time trghr, trghf ns - - 25 -

6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V, VCC=2.4~3.3V)

Item Symbol Unit Min. Typ. Max. Test Condition
VSYNC/HSYNC setup time tSYNCS ns 0 - - -
ENABLE setup time tENS ns 10 - - -
ENABLE hold time tENH ns 10 - - -
PD Data setup time tPDS ns 10 - - -
PD Data hold time tPDH ns 30 - - -
DOTCLK high-level pulse width PWDH ns 30 - - -
DOTCLK low-level pulse width PWDL ns 30 - - -
DOTCLK cycle time tCYCD ns 80 - - -
DOTCLK, VSYNC, HSYNC, rise/fall time trghr, trghf ns - - 25 -

trgbf
trgbr tSYNCS

HSYNC VIH
VSYNC VIL
tASE
tENS tENH

HSYNC VIH VIH

VSYNC VIL VIL

trgbr
trgbf PWDL PWDH

VIH VIH VIH

VIL VIL
tCYCD
tPDS tPDH

VIH VIH
Write Data
VIL VIL

Figure53 RGB Interface Timing

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