TE X AS I NS TRUM E NTS - P RO DUCTION D ATA

®
Stellaris LM3S1968 Microcontroller
D ATA SHE E T

D S -LM3S 1968 - 1 5 8 5 2 . 2 7 4 3 C o p yri g h t © 2 0 07-2014

S P M S 037I Te xa s In stru me n ts In co rporated
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

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Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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Table of Contents
Revision History ............................................................................................................................. 24
About This Document .................................................................................................................... 31
Audience .............................................................................................................................................. 31
About This Manual ................................................................................................................................ 31
Related Documents ............................................................................................................................... 31
Documentation Conventions .................................................................................................................. 32
1 Architectural Overview .......................................................................................... 34
1.1 Product Features .......................................................................................................... 34
1.2 Target Applications ........................................................................................................ 42
1.3 High-Level Block Diagram ............................................................................................. 43
1.4 Functional Overview ...................................................................................................... 45
1.4.1 ARM Cortex™-M3 ......................................................................................................... 45
1.4.2 Motor Control Peripherals .............................................................................................. 46
1.4.3 Analog Peripherals ........................................................................................................ 47
1.4.4 Serial Communications Peripherals ................................................................................ 47
1.4.5 System Peripherals ....................................................................................................... 49
1.4.6 Memory Peripherals ...................................................................................................... 49
1.4.7 Additional Features ....................................................................................................... 50
1.4.8 Hardware Details .......................................................................................................... 50
2 The Cortex-M3 Processor ...................................................................................... 52
2.1 Block Diagram .............................................................................................................. 53
2.2 Overview ...................................................................................................................... 54
2.2.1 System-Level Interface .................................................................................................. 54
2.2.2 Integrated Configurable Debug ...................................................................................... 54
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 55
2.2.4 Cortex-M3 System Component Details ........................................................................... 55
2.3 Programming Model ...................................................................................................... 56
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 56
2.3.2 Stacks .......................................................................................................................... 56
2.3.3 Register Map ................................................................................................................ 57
2.3.4 Register Descriptions .................................................................................................... 58
2.3.5 Exceptions and Interrupts .............................................................................................. 71
2.3.6 Data Types ................................................................................................................... 71
2.4 Memory Model .............................................................................................................. 71
2.4.1 Memory Regions, Types and Attributes ........................................................................... 73
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 73
2.4.3 Behavior of Memory Accesses ....................................................................................... 73
2.4.4 Software Ordering of Memory Accesses ......................................................................... 74
2.4.5 Bit-Banding ................................................................................................................... 75
2.4.6 Data Storage ................................................................................................................ 77
2.4.7 Synchronization Primitives ............................................................................................. 78
2.5 Exception Model ........................................................................................................... 79
2.5.1 Exception States ........................................................................................................... 80
2.5.2 Exception Types ............................................................................................................ 80
2.5.3 Exception Handlers ....................................................................................................... 83

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2.5.4 Vector Table .................................................................................................................. 83

2.5.5 Exception Priorities ....................................................................................................... 84
2.5.6 Interrupt Priority Grouping .............................................................................................. 85
2.5.7 Exception Entry and Return ........................................................................................... 85
2.6 Fault Handling .............................................................................................................. 87
2.6.1 Fault Types ................................................................................................................... 88
2.6.2 Fault Escalation and Hard Faults .................................................................................... 88
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 89
2.6.4 Lockup ......................................................................................................................... 89
2.7 Power Management ...................................................................................................... 89
2.7.1 Entering Sleep Modes ................................................................................................... 90
2.7.2 Wake Up from Sleep Mode ............................................................................................ 90
2.8 Instruction Set Summary ............................................................................................... 91
3 Cortex-M3 Peripherals ........................................................................................... 94
3.1 Functional Description ................................................................................................... 94
3.1.1 System Timer (SysTick) ................................................................................................. 94
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 95
3.1.3 System Control Block (SCB) .......................................................................................... 97
3.1.4 Memory Protection Unit (MPU) ....................................................................................... 97
3.2 Register Map .............................................................................................................. 102
3.3 System Timer (SysTick) Register Descriptions .............................................................. 104
3.4 NVIC Register Descriptions .......................................................................................... 108
3.5 System Control Block (SCB) Register Descriptions ........................................................ 121
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 148
4 JTAG Interface ...................................................................................................... 158
4.1 Block Diagram ............................................................................................................ 159
4.2 Signal Description ....................................................................................................... 159
4.3 Functional Description ................................................................................................. 160
4.3.1 JTAG Interface Pins ..................................................................................................... 160
4.3.2 JTAG TAP Controller ................................................................................................... 162
4.3.3 Shift Registers ............................................................................................................ 163
4.3.4 Operational Considerations .......................................................................................... 163
4.4 Initialization and Configuration ..................................................................................... 166
4.5 Register Descriptions .................................................................................................. 166
4.5.1 Instruction Register (IR) ............................................................................................... 166
4.5.2 Data Registers ............................................................................................................ 169
5 System Control ..................................................................................................... 171
5.1 Signal Description ....................................................................................................... 171
5.2 Functional Description ................................................................................................. 171
5.2.1 Device Identification .................................................................................................... 172
5.2.2 Reset Control .............................................................................................................. 172
5.2.3 Power Control ............................................................................................................. 176
5.2.4 Clock Control .............................................................................................................. 177
5.2.5 System Control ........................................................................................................... 182
5.3 Initialization and Configuration ..................................................................................... 183
5.4 Register Map .............................................................................................................. 183
5.5 Register Descriptions .................................................................................................. 185

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6 Hibernation Module .............................................................................................. 238

6.1 Block Diagram ............................................................................................................ 239
6.2 Signal Description ....................................................................................................... 239
6.3 Functional Description ................................................................................................. 240
6.3.1 Register Access Timing ............................................................................................... 240
6.3.2 Clock Source .............................................................................................................. 241
6.3.3 Battery Management ................................................................................................... 242
6.3.4 Real-Time Clock .......................................................................................................... 242
6.3.5 Battery-Backed Memory .............................................................................................. 243
6.3.6 Power Control ............................................................................................................. 243
6.3.7 Initiating Hibernate ...................................................................................................... 243
6.3.8 Interrupts and Status ................................................................................................... 244
6.4 Initialization and Configuration ..................................................................................... 244
6.4.1 Initialization ................................................................................................................. 244
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 244
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 245
6.4.4 External Wake-Up from Hibernation .............................................................................. 245
6.4.5 RTC/External Wake-Up from Hibernation ...................................................................... 245
6.5 Register Map .............................................................................................................. 245
6.6 Register Descriptions .................................................................................................. 246
7 Internal Memory ................................................................................................... 259
7.1 Block Diagram ............................................................................................................ 259
7.2 Functional Description ................................................................................................. 259
7.2.1 SRAM Memory ............................................................................................................ 259
7.2.2 Flash Memory ............................................................................................................. 260
7.3 Flash Memory Initialization and Configuration ............................................................... 262
7.3.1 Flash Programming ..................................................................................................... 262
7.3.2 Nonvolatile Register Programming ............................................................................... 263
7.4 Register Map .............................................................................................................. 264
7.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 265
7.6 Flash Register Descriptions (System Control Offset) ...................................................... 273
8 General-Purpose Input/Outputs (GPIOs) ........................................................... 286
8.1 Signal Description ....................................................................................................... 286
8.2 Functional Description ................................................................................................. 292
8.2.1 Data Control ............................................................................................................... 293
8.2.2 Interrupt Control .......................................................................................................... 294
8.2.3 Mode Control .............................................................................................................. 295
8.2.4 Commit Control ........................................................................................................... 295
8.2.5 Pad Control ................................................................................................................. 295
8.2.6 Identification ............................................................................................................... 296
8.3 Initialization and Configuration ..................................................................................... 296
8.4 Register Map .............................................................................................................. 297
8.5 Register Descriptions .................................................................................................. 299
9 General-Purpose Timers ...................................................................................... 334
9.1 Block Diagram ............................................................................................................ 335
9.2 Signal Description ....................................................................................................... 336
9.3 Functional Description ................................................................................................. 336
9.3.1 GPTM Reset Conditions .............................................................................................. 336

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9.3.2 32-Bit Timer Operating Modes ...................................................................................... 337

9.3.3 16-Bit Timer Operating Modes ...................................................................................... 338
9.4 Initialization and Configuration ..................................................................................... 342
9.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 342
9.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 343
9.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 343
9.4.4 16-Bit Input Edge Count Mode ..................................................................................... 344
9.4.5 16-Bit Input Edge Timing Mode .................................................................................... 344
9.4.6 16-Bit PWM Mode ....................................................................................................... 345
9.5 Register Map .............................................................................................................. 345
9.6 Register Descriptions .................................................................................................. 346
10 Watchdog Timer ................................................................................................... 371
10.1 Block Diagram ............................................................................................................ 372
10.2 Functional Description ................................................................................................. 372
10.3 Initialization and Configuration ..................................................................................... 373
10.4 Register Map .............................................................................................................. 373
10.5 Register Descriptions .................................................................................................. 374
11 Analog-to-Digital Converter (ADC) ..................................................................... 395
11.1 Block Diagram ............................................................................................................ 395
11.2 Signal Description ....................................................................................................... 396
11.3 Functional Description ................................................................................................. 397
11.3.1 Sample Sequencers .................................................................................................... 397
11.3.2 Module Control ............................................................................................................ 398
11.3.3 Hardware Sample Averaging Circuit ............................................................................. 399
11.3.4 Analog-to-Digital Converter .......................................................................................... 399
11.3.5 Differential Sampling ................................................................................................... 399
11.3.6 Test Modes ................................................................................................................. 401
11.3.7 Internal Temperature Sensor ........................................................................................ 401
11.4 Initialization and Configuration ..................................................................................... 402
11.4.1 Module Initialization ..................................................................................................... 402
11.4.2 Sample Sequencer Configuration ................................................................................. 402
11.5 Register Map .............................................................................................................. 403
11.6 Register Descriptions .................................................................................................. 404
12 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 432
12.1 Block Diagram ............................................................................................................ 433
12.2 Signal Description ....................................................................................................... 433
12.3 Functional Description ................................................................................................. 434
12.3.1 Transmit/Receive Logic ............................................................................................... 434
12.3.2 Baud-Rate Generation ................................................................................................. 435
12.3.3 Data Transmission ...................................................................................................... 435
12.3.4 Serial IR (SIR) ............................................................................................................. 436
12.3.5 FIFO Operation ........................................................................................................... 437
12.3.6 Interrupts .................................................................................................................... 437
12.3.7 Loopback Operation .................................................................................................... 438
12.3.8 IrDA SIR block ............................................................................................................ 439
12.4 Initialization and Configuration ..................................................................................... 439
12.5 Register Map .............................................................................................................. 440
12.6 Register Descriptions .................................................................................................. 441

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13 Synchronous Serial Interface (SSI) .................................................................... 475

13.1 Block Diagram ............................................................................................................ 475
13.2 Signal Description ....................................................................................................... 476
13.3 Functional Description ................................................................................................. 476
13.3.1 Bit Rate Generation ..................................................................................................... 476
13.3.2 FIFO Operation ........................................................................................................... 477
13.3.3 Interrupts .................................................................................................................... 477
13.3.4 Frame Formats ........................................................................................................... 478
13.4 Initialization and Configuration ..................................................................................... 485
13.5 Register Map .............................................................................................................. 486
13.6 Register Descriptions .................................................................................................. 487
14 Inter-Integrated Circuit (I2C) Interface ................................................................ 513
14.1 Block Diagram ............................................................................................................ 514
14.2 Signal Description ....................................................................................................... 514
14.3 Functional Description ................................................................................................. 515
14.3.1 I2C Bus Functional Overview ........................................................................................ 515
14.3.2 Available Speed Modes ............................................................................................... 517
14.3.3 Interrupts .................................................................................................................... 518
14.3.4 Loopback Operation .................................................................................................... 519
14.3.5 Command Sequence Flow Charts ................................................................................ 519
14.4 Initialization and Configuration ..................................................................................... 526
14.5 Register Map .............................................................................................................. 527
14.6 Register Descriptions (I2C Master) ............................................................................... 528
14.7 Register Descriptions (I2C Slave) ................................................................................. 541
15 Analog Comparators ............................................................................................ 550
15.1 Block Diagram ............................................................................................................ 551
15.2 Signal Description ....................................................................................................... 551
15.3 Functional Description ................................................................................................. 552
15.3.1 Internal Reference Programming .................................................................................. 553
15.4 Initialization and Configuration ..................................................................................... 554
15.5 Register Map .............................................................................................................. 554
15.6 Register Descriptions .................................................................................................. 555
16 Pulse Width Modulator (PWM) ............................................................................ 563
16.1 Block Diagram ............................................................................................................ 564
16.2 Signal Description ....................................................................................................... 565
16.3 Functional Description ................................................................................................. 566
16.3.1 PWM Timer ................................................................................................................. 566
16.3.2 PWM Comparators ...................................................................................................... 566
16.3.3 PWM Signal Generator ................................................................................................ 567
16.3.4 Dead-Band Generator ................................................................................................. 568
16.3.5 Interrupt/ADC-Trigger Selector ..................................................................................... 568
16.3.6 Synchronization Methods ............................................................................................ 569
16.3.7 Fault Conditions .......................................................................................................... 569
16.3.8 Output Control Block ................................................................................................... 569
16.4 Initialization and Configuration ..................................................................................... 569
16.5 Register Map .............................................................................................................. 570
16.6 Register Descriptions .................................................................................................. 572

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17 Quadrature Encoder Interface (QEI) ................................................................... 602

17.1 Block Diagram ............................................................................................................ 602
17.2 Signal Description ....................................................................................................... 603
17.3 Functional Description ................................................................................................. 604
17.4 Initialization and Configuration ..................................................................................... 606
17.5 Register Map .............................................................................................................. 606
17.6 Register Descriptions .................................................................................................. 607
18 Pin Diagram .......................................................................................................... 620
19 Signal Tables ........................................................................................................ 622
19.1 100-Pin LQFP Package Pin Tables ............................................................................... 622
19.1.1 Signals by Pin Number ................................................................................................ 622
19.1.2 Signals by Signal Name ............................................................................................... 626
19.1.3 Signals by Function, Except for GPIO ........................................................................... 631
19.1.4 GPIO Pins and Alternate Functions .............................................................................. 634
19.2 108-Ball BGA Package Pin Tables ................................................................................ 636
19.2.1 Signals by Pin Number ................................................................................................ 636
19.2.2 Signals by Signal Name ............................................................................................... 640
19.2.3 Signals by Function, Except for GPIO ........................................................................... 645
19.2.4 GPIO Pins and Alternate Functions .............................................................................. 648
19.3 Connections for Unused Signals ................................................................................... 650
20 Operating Characteristics ................................................................................... 652
21 Electrical Characteristics .................................................................................... 653
21.1 DC Characteristics ...................................................................................................... 653
21.1.1 Maximum Ratings ....................................................................................................... 653
21.1.2 Recommended DC Operating Conditions ...................................................................... 653
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 654
21.1.4 GPIO Module Characteristics ....................................................................................... 654
21.1.5 Power Specifications ................................................................................................... 654
21.1.6 Flash Memory Characteristics ...................................................................................... 656
21.1.7 Hibernation ................................................................................................................. 656
21.2 AC Characteristics ....................................................................................................... 656
21.2.1 Load Conditions .......................................................................................................... 656
21.2.2 Clocks ........................................................................................................................ 657
21.2.3 JTAG and Boundary Scan ............................................................................................ 658
21.2.4 Reset ......................................................................................................................... 660
21.2.5 Sleep Modes ............................................................................................................... 661
21.2.6 Hibernation Module ..................................................................................................... 661
21.2.7 General-Purpose I/O (GPIO) ........................................................................................ 662
21.2.8 Analog-to-Digital Converter .......................................................................................... 663
21.2.9 Synchronous Serial Interface (SSI) ............................................................................... 664
21.2.10 Inter-Integrated Circuit (I2C) Interface ........................................................................... 665
21.2.11 Analog Comparator ..................................................................................................... 666
A Serial Flash Loader .............................................................................................. 667
A.1 Serial Flash Loader ..................................................................................................... 667
A.2 Interfaces ................................................................................................................... 667
A.2.1 UART ......................................................................................................................... 667
A.2.2 SSI ............................................................................................................................. 667

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A.3 Packet Handling .......................................................................................................... 668

A.3.1 Packet Format ............................................................................................................ 668
A.3.2 Sending Packets ......................................................................................................... 668
A.3.3 Receiving Packets ....................................................................................................... 668
A.4 Commands ................................................................................................................. 669
A.4.1 COMMAND_PING (0X20) ............................................................................................ 669
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 669
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 669
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 670
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 670
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 670
B Register Quick Reference ................................................................................... 672
C Ordering and Contact Information ..................................................................... 695
C.1 Ordering Information .................................................................................................... 695
C.2 Part Markings .............................................................................................................. 695
C.3 Kits ............................................................................................................................. 695
C.4 Support Information ..................................................................................................... 696
D Package Information ............................................................................................ 697
D.1 100-Pin LQFP Package ............................................................................................... 697
D.1.1 Package Dimensions ................................................................................................... 697
D.1.2 Tray Dimensions ......................................................................................................... 699
D.1.3 Tape and Reel Dimensions .......................................................................................... 699
D.2 108-Ball BGA Package ................................................................................................ 701
D.2.1 Package Dimensions ................................................................................................... 701
D.2.2 Tray Dimensions ......................................................................................................... 703
D.2.3 Tape and Reel Dimensions .......................................................................................... 704

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List of Figures
Figure 1-1. Stellaris LM3S1968 Microcontroller High-Level Block Diagram ............................... 44
Figure 2-1. CPU Block Diagram ............................................................................................. 54
Figure 2-2. TPIU Block Diagram ............................................................................................ 55
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 57
Figure 2-4. Bit-Band Mapping ................................................................................................ 77
Figure 2-5. Data Storage ....................................................................................................... 78
Figure 2-6. Vector Table ........................................................................................................ 84
Figure 2-7. Exception Stack Frame ........................................................................................ 86
Figure 3-1. SRD Use Example ............................................................................................. 100
Figure 4-1. JTAG Module Block Diagram .............................................................................. 159
Figure 4-2. Test Access Port State Machine ......................................................................... 163
Figure 4-3. IDCODE Register Format ................................................................................... 169
Figure 4-4. BYPASS Register Format ................................................................................... 169
Figure 4-5. Boundary Scan Register Format ......................................................................... 170
Figure 5-1. Basic RST Configuration .................................................................................... 173
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 174
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 174
Figure 5-4. Power Architecture ............................................................................................ 176
Figure 5-5. Main Clock Tree ................................................................................................ 179
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 239
Figure 6-2. Clock Source Using Crystal ................................................................................ 241
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 242
Figure 7-1. Flash Block Diagram .......................................................................................... 259
Figure 8-1. GPIO Port Block Diagram ................................................................................... 293
Figure 8-2. GPIODATA Write Example ................................................................................. 294
Figure 8-3. GPIODATA Read Example ................................................................................. 294
Figure 9-1. GPTM Module Block Diagram ............................................................................ 335
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 340
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 341
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 342
Figure 10-1. WDT Module Block Diagram .............................................................................. 372
Figure 11-1. ADC Module Block Diagram ............................................................................... 396
Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 400
Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 400
Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 401
Figure 11-5. Internal Temperature Sensor Characteristic ......................................................... 402
Figure 12-1. UART Module Block Diagram ............................................................................. 433
Figure 12-2. UART Character Frame ..................................................................................... 435
Figure 12-3. IrDA Data Modulation ......................................................................................... 437
Figure 13-1. SSI Module Block Diagram ................................................................................. 475
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 478
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 479
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 480
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 480
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 481
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 482

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Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 482
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 483
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 484
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 485
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 485
Figure 14-1. I2C Block Diagram ............................................................................................. 514
Figure 14-2. I2C Bus Configuration ........................................................................................ 515
Figure 14-3. START and STOP Conditions ............................................................................. 515
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 516
Figure 14-5. R/S Bit in First Byte ............................................................................................ 516
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 516
Figure 14-7. Master Single SEND .......................................................................................... 520
Figure 14-8. Master Single RECEIVE ..................................................................................... 521
Figure 14-9. Master Burst SEND ........................................................................................... 522
Figure 14-10. Master Burst RECEIVE ...................................................................................... 523
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 524
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 525
Figure 14-13. Slave Command Sequence ................................................................................ 526
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 551
Figure 15-2. Structure of Comparator Unit .............................................................................. 552
Figure 15-3. Comparator Internal Reference Structure ............................................................ 553
Figure 16-1. PWM Unit Diagram ............................................................................................ 564
Figure 16-2. PWM Module Block Diagram .............................................................................. 565
Figure 16-3. PWM Count-Down Mode .................................................................................... 567
Figure 16-4. PWM Count-Up/Down Mode .............................................................................. 567
Figure 16-5. PWM Generation Example In Count-Up/Down Mode ........................................... 568
Figure 16-6. PWM Dead-Band Generator ............................................................................... 568
Figure 17-1. QEI Block Diagram ............................................................................................ 603
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 605
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 620
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 621
Figure 21-1. Load Conditions ................................................................................................ 656
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 659
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 659
Figure 21-4. JTAG TRST Timing ............................................................................................ 659
Figure 21-5. External Reset Timing (RST) .............................................................................. 660
Figure 21-6. Power-On Reset Timing ..................................................................................... 660
Figure 21-7. Brown-Out Reset Timing .................................................................................... 661
Figure 21-8. Software Reset Timing ....................................................................................... 661
Figure 21-9. Watchdog Reset Timing ..................................................................................... 661
Figure 21-10. Hibernation Module Timing ................................................................................. 662
Figure 21-11. ADC Input Equivalency Diagram ......................................................................... 663
Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 664
Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 665
Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 665
Figure 21-15. I2C Timing ......................................................................................................... 666
Figure D-1. Stellaris LM3S1968 100-Pin LQFP Package Dimensions ..................................... 697

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Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 699

Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 700
Figure D-4. Stellaris LM3S1968 108-Ball BGA Package Dimensions ...................................... 701
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 703
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 704

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List of Tables
Table 1. Revision History .................................................................................................. 24
Table 2. Documentation Conventions ................................................................................ 32
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 57
Table 2-2. Processor Register Map ....................................................................................... 58
Table 2-3. PSR Register Combinations ................................................................................. 63
Table 2-4. Memory Map ....................................................................................................... 71
Table 2-5. Memory Access Behavior ..................................................................................... 73
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 76
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 76
Table 2-8. Exception Types .................................................................................................. 81
Table 2-9. Interrupts ............................................................................................................ 82
Table 2-10. Exception Return Behavior ................................................................................... 87
Table 2-11. Faults ................................................................................................................. 88
Table 2-12. Fault Status and Fault Address Registers .............................................................. 89
Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 91
Table 3-1. Core Peripheral Register Regions ......................................................................... 94
Table 3-2. Memory Attributes Summary ................................................................................ 97
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 100
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 101
Table 3-5. AP Bit Field Encoding ........................................................................................ 101
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 101
Table 3-7. Peripherals Register Map ................................................................................... 102
Table 3-8. Interrupt Priority Levels ...................................................................................... 127
Table 3-9. Example SIZE Field Values ................................................................................ 155
Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 159
Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 160
Table 4-3. JTAG Port Pins Reset State ............................................................................... 160
Table 4-4. JTAG Instruction Register Commands ................................................................. 167
Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 171
Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 171
Table 5-3. Reset Sources ................................................................................................... 172
Table 5-4. Clock Source Options ........................................................................................ 177
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 180
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 180
Table 5-7. System Control Register Map ............................................................................. 184
Table 5-8. RCC2 Fields that Override RCC fields ................................................................. 199
Table 6-1. Hibernate Signals (100LQFP) ............................................................................. 239
Table 6-2. Hibernate Signals (108BGA) .............................................................................. 240
Table 6-3. Hibernation Module Register Map ....................................................................... 246
Table 7-1. Flash Protection Policy Combinations ................................................................. 260
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 264
Table 7-3. Flash Register Map ............................................................................................ 264
Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 287
Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 287
Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 288
Table 8-4. GPIO Signals (100LQFP) ................................................................................... 289

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Table 8-5. GPIO Signals (108BGA) ..................................................................................... 291

Table 8-6. GPIO Pad Configuration Examples ..................................................................... 296
Table 8-7. GPIO Interrupt Configuration Example ................................................................ 296
Table 8-8. GPIO Register Map ........................................................................................... 298
Table 9-1. Available CCP Pins ............................................................................................ 335
Table 9-2. General-Purpose Timers Signals (100LQFP) ....................................................... 336
Table 9-3. General-Purpose Timers Signals (108BGA) ......................................................... 336
Table 9-4. 16-Bit Timer With Prescaler Configurations ......................................................... 338
Table 9-5. Timers Register Map .......................................................................................... 345
Table 10-1. Watchdog Timer Register Map ............................................................................ 373
Table 11-1. ADC Signals (100LQFP) .................................................................................... 396
Table 11-2. ADC Signals (108BGA) ...................................................................................... 396
Table 11-3. Samples and FIFO Depth of Sequencers ............................................................ 397
Table 11-4. Differential Sampling Pairs ................................................................................. 399
Table 11-5. ADC Register Map ............................................................................................. 403
Table 12-1. UART Signals (100LQFP) .................................................................................. 433
Table 12-2. UART Signals (108BGA) .................................................................................... 434
Table 12-3. UART Register Map ........................................................................................... 440
Table 13-1. SSI Signals (100LQFP) ...................................................................................... 476
Table 13-2. SSI Signals (108BGA) ........................................................................................ 476
Table 13-3. SSI Register Map .............................................................................................. 487
Table 14-1. I2C Signals (100LQFP) ...................................................................................... 514
Table 14-2. I2C Signals (108BGA) ........................................................................................ 514
Table 14-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 517
Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 527
Table 14-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 532
Table 15-1. Analog Comparators Signals (100LQFP) ............................................................. 551
Table 15-2. Analog Comparators Signals (108BGA) .............................................................. 552
Table 15-3. Internal Reference Voltage and ACREFCTL Field Values ..................................... 553
Table 15-4. Analog Comparators Register Map ..................................................................... 555
Table 16-1. PWM Signals (100LQFP) ................................................................................... 565
Table 16-2. PWM Signals (108BGA) ..................................................................................... 565
Table 16-3. PWM Register Map ............................................................................................ 571
Table 17-1. QEI Signals (100LQFP) ...................................................................................... 603
Table 17-2. QEI Signals (108BGA) ....................................................................................... 603
Table 17-3. QEI Register Map .............................................................................................. 607
Table 19-1. Signals by Pin Number ....................................................................................... 622
Table 19-2. Signals by Signal Name ..................................................................................... 626
Table 19-3. Signals by Function, Except for GPIO ................................................................. 631
Table 19-4. GPIO Pins and Alternate Functions ..................................................................... 634
Table 19-5. Signals by Pin Number ....................................................................................... 636
Table 19-6. Signals by Signal Name ..................................................................................... 640
Table 19-7. Signals by Function, Except for GPIO ................................................................. 645
Table 19-8. GPIO Pins and Alternate Functions ..................................................................... 648
Table 19-9. Connections for Unused Signals (100-pin LQFP) ................................................. 650
Table 19-10. Connections for Unused Signals, 108-pin BGA .................................................... 651
Table 20-1. Temperature Characteristics ............................................................................... 652
Table 20-2. Thermal Characteristics ..................................................................................... 652

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Table 20-3. ESD Absolute Maximum Ratings ........................................................................ 652

Table 21-1. Maximum Ratings .............................................................................................. 653
Table 21-2. Recommended DC Operating Conditions ............................................................ 653
Table 21-3. LDO Regulator Characteristics ........................................................................... 654
Table 21-4. GPIO Module DC Characteristics ........................................................................ 654
Table 21-5. Detailed Power Specifications ............................................................................ 655
Table 21-6. Flash Memory Characteristics ............................................................................ 656
Table 21-7. Hibernation Module DC Characteristics ............................................................... 656
Table 21-8. Phase Locked Loop (PLL) Characteristics ........................................................... 657
Table 21-9. Actual PLL Frequency ........................................................................................ 657
Table 21-10. Clock Characteristics ......................................................................................... 657
Table 21-11. Crystal Characteristics ....................................................................................... 658
Table 21-12. System Clock Characteristics with ADC Operation ............................................... 658
Table 21-13. JTAG Characteristics ......................................................................................... 658
Table 21-14. Reset Characteristics ......................................................................................... 660
Table 21-15. Sleep Modes AC Characteristics ......................................................................... 661
Table 21-16. Hibernation Module AC Characteristics ............................................................... 662
Table 21-17. GPIO Characteristics ......................................................................................... 662
Table 21-18. ADC Characteristics ........................................................................................... 663
Table 21-19. ADC Module Internal Reference Characteristics .................................................. 664
Table 21-20. SSI Characteristics ............................................................................................ 664
Table 21-21. I2C Characteristics ............................................................................................. 665
Table 21-22. Analog Comparator Characteristics ..................................................................... 666
Table 21-23. Analog Comparator Voltage Reference Characteristics ........................................ 666

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List of Registers
The Cortex-M3 Processor ............................................................................................................. 52
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 59
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 59
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 59
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 59
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 59
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 59
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 59
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 59
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 59
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 59
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 59
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 59
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 59
Register 14: Stack Pointer (SP) ........................................................................................................... 60
Register 15: Link Register (LR) ............................................................................................................ 61
Register 16: Program Counter (PC) ..................................................................................................... 62
Register 17: Program Status Register (PSR) ........................................................................................ 63
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 67
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 68
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 69
Register 21: Control Register (CONTROL) ........................................................................................... 70
Cortex-M3 Peripherals ................................................................................................................... 94
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 105
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 107
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 108
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 109
Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................ 110
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 111
Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................ 112
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 113
Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 114
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 115
Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 116
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 117
Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 118
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 119
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 119
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 119
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 119
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 119
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 119
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 119
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 119
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 119

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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 119
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 119
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 121
Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 122
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 123
Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 126
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 127
Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 129
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 131
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 133
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 134
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 135
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 136
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 140
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 146
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 147
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 148
Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 149
Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 150
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 152
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 153
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 153
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 153
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 153
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 155
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 155
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 155
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 155
System Control ............................................................................................................................ 171
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 186
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 188
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 189
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 190
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 191
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 192
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 193
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 194
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 198
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 199
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 201
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 202
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 204
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 205
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 207
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 209
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 212
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 213
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 215

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Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 217
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 219
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 222
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 225
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 228
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 230
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 232
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 234
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 235
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 237
Hibernation Module ..................................................................................................................... 238
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 247
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 248
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 249
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 250
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 251
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 253
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 254
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 255
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 256
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 257
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 258
Internal Memory ........................................................................................................................... 259
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 266
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 267
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 268
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 270
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 271
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 272
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 274
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 275
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 276
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 277
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 278
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 279
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 280
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 281
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 282
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 283
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 284
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 285
General-Purpose Input/Outputs (GPIOs) ................................................................................... 286
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 300
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 301
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 302
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 303
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 304
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 305

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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 306
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 307
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 308
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 309
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 311
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 312
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 313
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 314
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 315
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 316
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 317
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 318
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 319
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 320
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 322
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 323
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 324
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 325
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 326
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 327
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 328
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 329
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 330
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 331
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 332
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 333
General-Purpose Timers ............................................................................................................. 334
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 347
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 348
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 350
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 352
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 355
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 357
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 358
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 359
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 361
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 362
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 363
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 364
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 365
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 366
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 367
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 368
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 369
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 370
Watchdog Timer ........................................................................................................................... 371
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 375
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 376

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Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 377

Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 378
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 379
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 380
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 381
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 382
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 383
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 384
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 385
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 386
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 387
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 388
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 389
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 390
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 391
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 392
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 393
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 394
Analog-to-Digital Converter (ADC) ............................................................................................. 395
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 405
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 406
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 407
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 408
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 409
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 410
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 414
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 415
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 417
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 418
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 419
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 421
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 424
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 424
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 424
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 424
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 425
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 425
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 425
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 425
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 426
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 426
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 427
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 427
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 429
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 430
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 431
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 432
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 442

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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 444
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 446
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 448
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 449
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 450
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 451
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 453
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 455
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 457
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 459
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 460
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 461
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 463
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 464
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 465
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 466
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 467
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 468
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 469
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 470
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 471
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 472
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 473
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 474
Synchronous Serial Interface (SSI) ............................................................................................ 475
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 488
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 490
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 492
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 493
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 495
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 496
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 498
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 499
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 500
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 501
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 502
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 503
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 504
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 505
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 506
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 507
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 508
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 509
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 510
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 511
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 512
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 513
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 529

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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 530

Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 534
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 535
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 536
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 537
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 538
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 539
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 540
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 542
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 543
Register 12: I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 545
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 546
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 547
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 548
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 549
Analog Comparators ................................................................................................................... 550
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 556
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 557
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 558
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 559
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 560
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 560
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 560
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 561
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 561
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 561
Pulse Width Modulator (PWM) .................................................................................................... 563
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 573
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 574
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 575
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 576
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 577
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 578
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 579
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 580
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 581
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 582
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 582
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 582
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 584
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 584
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 584
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 587
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 587
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 587
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 588
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 588

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Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 588
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 589
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 589
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 589
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 590
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 590
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 590
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 591
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 591
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 591
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 592
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 592
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 592
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 593
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 593
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 593
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 596
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 596
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 596
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 599
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 599
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 599
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 600
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 600
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 600
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 601
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 601
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 601
Quadrature Encoder Interface (QEI) .......................................................................................... 602
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 608
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 610
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 611
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 612
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 613
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 614
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 615
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 616
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 617
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 618
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 619

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Revision History

Revision History
The revision history table notes changes made between the indicated revisions of the LM3S1968
data sheet.

Table 1. Revision History

Date Revision Description
July 2014 15852.2743 ■ In JTAG chapter, clarified JTAG-to-SWD Switching and SWD-to-JTAG Switching.

■ In System Control chapter, clarified behavior of Reset Cause (RESC) register external reset bit.

■ In Internal Memory chapter:

– Added sections on Execute-Only Protection, Read-Only Protection, and Permanently Disabling
Debug.
– Noted that the Boot Configuration (BOOTCFG) register requires a POR before committed
changes to the Flash-resident registers take effect.

■ In UART chapter:
– Clarified that the transmit interrupt is based on a transition through level.
– Corrected reset for UART Raw Interrupt Status (UARTRIS) register.

■ In Electrical Characteristics chapter, updated Crystal Characteristics table.

■ In Ordering and Contact Information appendix, moved orderable part numbers table to addendum.

■ Additional minor data sheet clarifications and corrections.

June 2012 12746.2515 ■ Corrected missing interrupt 9 in "Interrupts" table.

■ Removed extended temperature package.

■ Minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date Revision Description
November 2011 11108 ■ Added module-specific pin tables to each chapter in the new Signal Description sections.

■ In Hibernation chapter:

– Changed terminology from non-volatile memory to battery-backed memory.

– Clarified Hibernation module register reset conditions.

■ In Timer chapter, clarified that in 16-Bit Input Edge Time Mode, the timer is capable of capturing
three types of events: rising edge, falling edge, or both.

■ In UART chapter, clarified interrupt behavior.

■ In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)".

■ In Signal Tables chapter:

– Corrected pin numbers in table "Connections for Unused Signals" (other pin tables were correct).

– Corrected buffer type for PWMn signals in pin tables.

■ In Electrical Characteristics chapter:

– Added parameter "Input voltage for a GPIO configured as an analog input" to the "Maximum
Ratings" table.

– Corrected Nom values for parameters "TCK clock Low time" and "TCK clock High time" in "JTAG
Characteristics" table.

– Corrected missing values for "Conversion time" and "Conversion rate" parameters in "ADC
Characteristics" table.

■ Additional minor data sheet clarifications and corrections.

January 2011 9102 ■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.

■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.

■ Added "Reset Sources" table to System Control chapter.

■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.

■ Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.

■ Changed I2C slave register base addresses and offsets to be relative to the I2C module base address
of 0x4002.0000 and 0x4002.1000, so register bases and offsets were changed for all I2C slave
®
registers. Note that the hw_i2c.h file in the StellarisWare Driver Library uses a base address of
0x4002.0800 and 0x4002.1800 for the I2C slave registers. Be aware when using registers with
offsets between 0x800 and 0x818 that StellarisWare uses the old slave base address for these
offsets.

■ Added GNDPHY and VCCPHY to Connections for Unused Signals tables.

■ Corrected nonlinearity and offset error parameters (EL, ED and EO) in ADC Characteristics table.

■ Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (VNON parameter in Maximum Ratings table).

■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date Revision Description
September 2010 7787 ■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.

■ Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control
and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the
Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register.

■ Added clarification of instruction execution during Flash operations.

■ Modified Figure 8-1 on page 293 to clarify operation of the GPIO inputs when used as an alternate
function.

■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.

■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.

■ In Electrical Characteristics chapter:

– Added ILKG parameter (GPIO input leakage current) to Table 21-4 on page 654.
– Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 21-20 on page 664.

■ Added dimensions for Tray and Tape and Reel shipping mediums.

June 2010 7393 ■ Corrected base address for SRAM in architectural overview chapter.

■ Clarified system clock operation, adding content to “Clock Control” on page 177.

■ In Signal Tables chapter, added table "Connections for Unused Signals."

■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.

■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.

■ Additional minor data sheet clarifications and corrections.

April 2010 7007 ■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.

■ Removed erroneous text about restoring the Flash Protection registers.

■ Added note about RST signal routing.

■ Clarified the function of the TnSTALL bit in the GPTMCTL register.

■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date Revision Description
January 2010 6712 ■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.

■ Clarified wording on Flash memory access errors.

■ Added section on Flash interrupts.

■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers
to be indeterminate.

■ Clarified operation of SSI transmit FIFO.

■ Made these changes to the Operating Characteristics chapter:

– Added storage temperature ratings to "Temperature Characteristics" table

– Added "ESD Absolute Maximum Ratings" table

■ Made these changes to the Electrical Characteristics chapter:

– In "Flash Memory Characteristics" table, corrected Mass erase time

– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)

– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time

October 2009 6462 ■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.

■ Removed erroneous reference to the WRC bit in the Hibernation chapter.

■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.

■ Clarified PWM source for ADC triggering.

■ Made these changes to the Electrical Characteristics chapter:

– Removed VSIH and VSIL parameters from Operating Conditions table.

– Added table showing actual PLL frequency depending on input crystal.

– Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.

– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.

– Changed SSI set up and hold times to be expressed in system clocks, not ns.

July 2009 5920 Corrected ordering numbers.

July 2009 5902 ■ Clarified Power-on reset and RST pin operation; added new diagrams.

■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.

■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.

■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1

registers.

■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.

■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR
(Internal voltage reference error) parameter.

■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date Revision Description
April 2009 5367 ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 165).

■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.

■ Added "GPIO Module DC Characteristics" table (see Table 21-4 on page 654).

■ Additional minor data sheet clarifications and corrections.

January 2009 4660 ■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.

■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.

■ Additional minor data sheet clarifications and corrections.

November 2008 4283 ■ Revised High-Level Block Diagram.

■ Additional minor data sheet clarifications and corrections were made.

October 2008 4149 ■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.

■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.

■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.

August 2008 3447 ■ Added note on clearing interrupts to Interrupts chapter.

■ Added Power Architecture diagram to System Control chapter.

■ Additional minor data sheet clarifications and corrections.

July 2008 3108 ■ Additional minor data sheet clarifications and corrections.

May 2008 2972 ■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
indicated as available and have now been changed to a No Connect (NC):

– Ball C1: Changed PE7 to NC

– Ball C2: Changed PE6 to NC

– Ball D2: Changed PE5 to NC

– Ball D1: Changed PE4 to NC

– Ball F1: Changed PD7 to NC

– Ball F2: Changed PD6 to NC

– Ball E2: Changed PD5 to NC

– Ball E1: Changed PD4 to NC

■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.

■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date Revision Description
April 2008 2881 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.

■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.

■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.

■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.

■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter
was changed from a max of 100 to 250.

■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical
Characteristics" chapter was changed from 4 to 3.

■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).

■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.

■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).

■ Two figures on clock source were added to the "Hibernation Module":

– Clock Source Using Crystal

– Clock Source Using Dedicated Oscillator

■ The following notes on battery management were added to the "Hibernation Module" chapter:

– Battery voltage is not measured while in Hibernate mode.

– System level factors may affect the accuracy of the low battery detect circuit. The designer
should consider battery type, discharge characteristics, and a test load during battery voltage
measurements.

■ A note on high-current applications was added to the GPIO chapter:

For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.

■ A note on Schmitt inputs was added to the GPIO chapter:

Pins configured as digital inputs are Schmitt-triggered.

■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.

■ The "Differential Sampling Range" figures in the ADC chapter were clarified.

■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:

– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.

– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.

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Revision History

Table 1. Revision History (continued)

Date Revision Description
■ Additional minor data sheet clarifications and corrections.

March 2008 2550 Started tracking revision history.

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About This Document

This data sheet provides reference information for the LM3S1968 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.

Audience
This manual is intended for system software developers, hardware designers, and application
developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Related Documents
®
The following related documents are available on the Stellaris web site at www.ti.com/stellaris:

■ Stellaris® Errata

■ ARM® Cortex™-M3 Errata

■ Cortex™-M3/M4 Instruction Set Technical User's Manual

■ Stellaris® Graphics Library User's Guide

■ Stellaris® Peripheral Driver Library User's Guide

The following related documents are also referenced:

■ ARM® Debug Interface V5 Architecture Specification

■ ARM® Embedded Trace Macrocell Architecture Specification

■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture

This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.

July 15, 2014 31

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About This Document

Documentation Conventions
This document uses the conventions shown in Table 2 on page 32.

Table 2. Documentation Conventions

Notation Meaning
General Register Notation
REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit A single bit in a register.
bit field Two or more consecutive and related bits.
offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 71.
Register N Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field This value in the register bit diagram indicates whether software running on the controller can
Types change the value of the bit field.
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
R/WC Software can read or write this field. Writing to it with any value clears the register.
R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.

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Table 2. Documentation Conventions (continued)

Notation Meaning
assert a signal Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal Change the value of the signal from the logically True state to the logically False state.
SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.

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1 Architectural Overview
®
The Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The Stellaris family offers efficient performance and extensive integration, favorably positioning the
device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris LM3S1000 series extends the Stellaris family with larger on-chip memories,
enhanced power management, and expanded I/O and control capabilities.
The LM3S1968 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S1968 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S1968 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S1968 microcontroller perfectly for
battery applications.
In addition, the LM3S1968 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S1968 microcontroller is code-compatible
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 695 for ordering information for Stellaris family devices.

1.1 Product Features

The LM3S1968 microcontroller includes the following product features:

■ 32-Bit RISC Performance

– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded

applications

– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero

counter with a flexible control mechanism

– Thumb®-compatible Thumb-2-only instruction set processor core for high code density

– 50-MHz operation

– Hardware-division and single-cycle-multiplication

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– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt

handling

– 40 interrupts with eight priority levels

– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality

– Unaligned data access, enabling data to be efficiently packed into memory

– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control

■ ARM® Cortex™-M3 Processor Core

– Compact core.

– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.

– Rapid application execution through Harvard architecture characterized by separate buses

for instruction and data.

– Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.

– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining

– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.

– Migration from the ARM7™ processor family for better performance and power efficiency.

– Full-featured debug solution

• Serial Wire JTAG Debug Port (SWJ-DP)

• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling

• Instrumentation Trace Macrocell (ITM) for support of printf style debugging

• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

– Optimized for single-cycle flash usage

– Three sleep modes with clock gating for low power

– Single-cycle multiply instruction and hardware divide

– Atomic operations

– ARM Thumb2 mixed 16-/32-bit instruction set

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– 1.25 DMIPS/MHz

■ JTAG

– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

– Four-bit Instruction Register (IR) chain for storing JTAG instructions

– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST

– ARM additional instructions: APACC, DPACC and ABORT

– Integrated ARM Serial Wire Debug (SWD)

■ Hibernation

– System power control using discrete external regulator

– Dedicated pin for waking from an external signal

– Low-battery detection, signaling, and interrupt generation

– 32-bit real-time clock (RTC)

– Two 32-bit RTC match registers for timed wake-up and interrupt generation

– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal

– RTC predivider trim for making fine adjustments to the clock rate

– 64 32-bit words of non-volatile memory

– Programmable interrupts for RTC match, external wake, and low battery events

■ Internal Memory

– 256 KB single-cycle flash

• User-managed flash block protection on a 2-KB block basis

• User-managed flash data programming

• User-defined and managed flash-protection block

– 64 KB single-cycle SRAM

■ GPIOs

– 5-52 GPIOs, depending on configuration

– 5-V-tolerant in input configuration

– Fast toggle capable of a change every two clock cycles

– Programmable control for GPIO interrupts

• Interrupt generation masking

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• Edge-triggered on rising, falling, or both

• Level-sensitive on High or Low values

– Bit masking in both read and write operations through address lines

– Can initiate an ADC sample sequence

– Pins configured as digital inputs are Schmitt-triggered.

– Programmable control for GPIO pad configuration

• Weak pull-up or pull-down resistors

• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications

• Slew rate control for the 8-mA drive

• Open drain enables

• Digital input enables

■ General-Purpose Timers

– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:

• As a single 32-bit timer

• As one 32-bit Real-Time Clock (RTC) to event capture

• For Pulse Width Modulation (PWM)

• To trigger analog-to-digital conversions

– 32-bit Timer modes

• Programmable one-shot timer

• Programmable periodic timer

• Real-Time Clock when using an external 32.768-KHz clock as the input

• User-enabled stalling when the controller asserts CPU Halt flag during debug

• ADC event trigger

– 16-bit Timer modes

• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)

• Programmable one-shot timer

• Programmable periodic timer

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• User-enabled stalling when the controller asserts CPU Halt flag during debug

• ADC event trigger

– 16-bit Input Capture modes

• Input edge count capture

• Input edge time capture

– 16-bit PWM mode

• Simple PWM mode with software-programmable output inversion of the PWM signal

■ ARM FiRM-compliant Watchdog Timer

– 32-bit down counter with a programmable load register

– Separate watchdog clock with an enable

– Programmable interrupt generation logic with interrupt masking

– Lock register protection from runaway software

– Reset generation logic with an enable/disable

– User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ ADC

– Eight analog input channels

– Single-ended and differential-input configurations

– On-chip internal temperature sensor

– Sample rate of one million samples/second

– Flexible, configurable analog-to-digital conversion

– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs

– Flexible trigger control

• Controller (software)

• Timers

• Analog Comparators

• PWM

• GPIO

– Hardware averaging of up to 64 samples for improved accuracy

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– Converter uses an internal 3-V reference

– Power and ground for the analog circuitry is separate from the digital power and ground

■ UART

– Three fully programmable 16C550-type UARTs with IrDA support

– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

– Programmable baud-rate generator allowing speeds up to 3.125 Mbps

– Programmable FIFO length, including 1-byte deep operation providing conventional

double-buffered interface

– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

– Standard asynchronous communication bits for start, stop, and parity

– Line-break generation and detection

– Fully programmable serial interface characteristics

• 5, 6, 7, or 8 data bits

• Even, odd, stick, or no-parity bit generation/detection

• 1 or 2 stop bit generation

– IrDA serial-IR (SIR) encoder/decoder providing

• Programmable use of IrDA Serial Infrared (SIR) or UART input/output

• Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex

• Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations

• Programmable internal clock generator enabling division of reference clock by 1 to 256

for low-power mode bit duration

■ Synchronous Serial Interface (SSI)

– Two SSI modules, each with the following features:

– Master or slave operation

– Programmable clock bit rate and prescale

– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments

synchronous serial interfaces

– Programmable data frame size from 4 to 16 bits

– Internal loopback test mode for diagnostic/debug testing

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■ I2C

– Two I2C modules, each with the following features:

– Devices on the I2C bus can be designated as either a master or a slave

• Supports both sending and receiving data as either a master or a slave

• Supports simultaneous master and slave operation

– Four I2C modes

• Master transmit

• Master receive

• Slave transmit

• Slave receive

– Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)

– Master and slave interrupt generation

• Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)

• Slave generates interrupts when data has been sent or requested by a master

– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode

■ Analog Comparators

– Three independent integrated analog comparators

– Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample
sequence

– Compare external pin input to external pin input or to internal programmable voltage reference

– Compare a test voltage against any one of these voltages

• An individual external reference voltage

• A shared single external reference voltage

• A shared internal reference voltage

■ PWM

– Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM
signal generator, a dead-band generator, and an interrupt/ADC-trigger selector

– One fault input in hardware to promote low-latency shutdown

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– One 16-bit counter

• Runs in Down or Up/Down mode

• Output frequency controlled by a 16-bit load value

• Load value updates can be synchronized

• Produces output signals at zero and load value

– Two PWM comparators

• Comparator value updates can be synchronized

• Produces output signals on match

– PWM generator

• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals

• Produces two independent PWM signals

– Dead-band generator

• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge

• Can be bypassed, leaving input PWM signals unmodified

– Flexible output control block with PWM output enable of each PWM signal

• PWM output enable of each PWM signal

• Optional output inversion of each PWM signal (polarity control)

• Optional fault handling for each PWM signal

• Synchronization of timers in the PWM generator blocks

• Interrupt status summary of the PWM generator blocks

– Can initiate an ADC sample sequence

■ QEI

– Two QEI modules, each with the following features:

– Position integrator that tracks the encoder position

– Velocity capture using built-in timer

– The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)

– Interrupt generation on:

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• Index pulse

• Velocity-timer expiration

• Direction change

• Quadrature error detection

■ Power

– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V

– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits

– Low-power options on controller: Sleep and Deep-sleep modes

– Low-power options for peripherals: software controls shutdown of individual peripherals

– 3.3-V supply brown-out detection and reporting via interrupt or reset

■ Flexible Reset Sources

– Power-on reset (POR)

– Reset pin assertion

– Brown-out (BOR) detector alerts to system power drops

– Software reset

– Watchdog timer reset

– Internal low drop-out (LDO) regulator output goes unregulated

■ Industrial temperature 100-pin RoHS-compliant LQFP package

■ Industrial-range 108-ball RoHS-compliant BGA package

1.2 Target Applications

■ Remote monitoring

■ Electronic point-of-sale (POS) machines

■ Test and measurement equipment

■ Network appliances and switches

■ Factory automation

■ HVAC and building control

■ Gaming equipment

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■ Motion control

■ Medical instrumentation

■ Fire and security

■ Power and energy

■ Transportation

1.3 High-Level Block Diagram

Figure 1-1 on page 44 depicts the features on the Stellaris LM3S1968 microcontroller.

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Figure 1-1. Stellaris LM3S1968 Microcontroller High-Level Block Diagram

JTAG/SWD
ARM®
Cortex™-M3
(50MHz)

System
Control and DCode bus Flash
Clocks (256KB)
(w/ Precis. Osc.) NVIC MPU
ICode bus
System Bus

LM3S1968 Bus Matrix SRAM

(64KB)

SYSTEM PERIPHERALS

Watchdog
Hibernation Timer
Module
(1)

GPIOs General-
Purpose
(5-52) Timer (4)

SERIAL PERIPHERALS
Advanced Peripheral Bus (APB)

I2C UART
(2) (3)

SSI
(2)

ANALOG PERIPHERALS

Analog 10- Bit ADC

Comparator Channels
(3) (8)

MOTION CONTROL PERIPHERALS

PWM QEI
(6) (2)

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1.4 Functional Overview

The following sections provide an overview of the features of the LM3S1968 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 695.

1.4.1 ARM Cortex™-M3

1.4.1.1 Processor Core (see page 52)
All members of the Stellaris product family, including the LM3S1968 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.

1.4.1.2 Memory Map (see page 71)

A memory map lists the location of instructions and data in memory. The memory map for the
LM3S1968 controller can be found in Table 2-4 on page 71. Register addresses are given as a
hexadecimal increment, relative to the module's base address as shown in the memory map.

1.4.1.3 System Timer (SysTick) (see page 94)

Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:

■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.

■ A high-speed alarm timer using the system clock.

■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.

■ A simple counter. Software can use this to measure time to completion and time used.

■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.

1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 95)

The LM3S1968 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 40 interrupts.

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1.4.1.5 System Control Block (SCB) (see page 97)

The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.

1.4.1.6 Memory Protection Unit (MPU) (see page 97)

The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model.
The MPU provides full support for protection regions, overlapping protection regions, access
permissions, and exporting memory attributes to the system.

1.4.2 Motor Control Peripherals

To enhance motor control, the LM3S1968 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).

1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S1968, PWM motion control functionality can be achieved through:

■ Dedicated, flexible motion control hardware using the PWM pins

■ The motion control features of the general-purpose timers using the CCP pins

PWM Pins (see page 563)

The LM3S1968 PWM module consists of three PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.

CCP Pins (see page 341)

The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.

Fault Pin (see page 569)

The LM3S1968 PWM module includes one fault-condition handling input to quickly provide low-latency
shutdown and prevent damage to the motor being controlled.

1.4.2.2 QEI (see page 602)

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In

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addition, it can capture a running estimate of the velocity of the encoder wheel. The LM3S1968
microcontroller includes two QEI modules, which enables control of two motors at the same time.

1.4.3 Analog Peripherals

To handle analog signals, the LM3S1968 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S1968 microcontroller offers three analog comparators.

1.4.3.1 ADC (see page 395)

An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S1968 ADC module features 10-bit conversion resolution and supports eight input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.

1.4.3.2 Analog Comparators (see page 550)

An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S1968 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:

■ An individual external reference voltage

■ A shared single external reference voltage

■ A shared internal reference voltage

The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.

1.4.4 Serial Communications Peripherals

The LM3S1968 controller supports both asynchronous and synchronous serial communications
with:

■ Three fully programmable 16C550-type UARTs

■ Two SSI modules

■ Two I2C modules

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1.4.4.1 UART (see page 432)

A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S1968 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.

1.4.4.2 SSI (see page 475)

Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications
interface.
The LM3S1968 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.

1.4.4.3 I2C (see page 513)

The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S1968 controller includes two I2C modules that provide the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. Each I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).

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Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.

1.4.5 System Peripherals

1.4.5.1 Programmable GPIOs (see page 286)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris GPIO module is comprised of eight physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 5-52 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 622 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.

1.4.5.2 Four Programmable Timers (see page 334)

Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.

1.4.5.3 Watchdog Timer (see page 371)

A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.

1.4.6 Memory Peripherals

The LM3S1968 controller offers both single-cycle SRAM and single-cycle Flash memory.

1.4.6.1 SRAM (see page 259)

The LM3S1968 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain

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regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.

1.4.6.2 Flash (see page 260)

The LM3S1968 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.

1.4.7 Additional Features

1.4.7.1 JTAG TAP Controller (see page 158)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.

1.4.7.2 System Control and Clocks (see page 171)

System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.

1.4.7.3 Hibernation Module (see page 238)

The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.

1.4.8 Hardware Details

Details on the pins and package can be found in the following sections:

■ “Pin Diagram” on page 620

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■ “Signal Tables” on page 622

■ “Operating Characteristics” on page 652

■ “Electrical Characteristics” on page 653

■ “Package Information” on page 697

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2 The Cortex-M3 Processor

The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:

■ Compact core.

■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.

■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.

■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.

■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining

■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.

■ Migration from the ARM7™ processor family for better performance and power efficiency.

■ Full-featured debug solution

– Serial Wire JTAG Debug Port (SWJ-DP)

– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling

– Instrumentation Trace Macrocell (ITM) for support of printf style debugging

– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

■ Optimized for single-cycle flash usage

■ Three sleep modes with clock gating for low power

■ Single-cycle multiply instruction and hardware divide

■ Atomic operations

■ ARM Thumb2 mixed 16-/32-bit instruction set

■ 1.25 DMIPS/MHz
®
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motor control.

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This chapter provides information on the Stellaris implementation of the Cortex-M3 processor,
including the programming model, the memory model, the exception model, fault handling, and
power management.
For technical details on the instruction set, see the Cortex™-M3/M4 Instruction Set Technical User's
Manual.

2.1 Block Diagram

The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including a range of single-cycle and SIMD multiplication
and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction
set based on Thumb-2 technology, ensuring high code density and reduced program memory
requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a
modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI)
and provides eight interrupt priority levels. The tight integration of the processor core and NVIC
provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.

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Figure 2-1. CPU Block Diagram

Nested Interrupts
Vectored Serial
Sleep CM3 Core ARM
Interrupt Wire
Controller Debug
Cortex-M3 Output
Instructions Data Trace
Trace Port
Memory
Port (SWO)
Protection
Unit Interface
Unit

Data Instrumentation
Flash Watchpoint Trace Macrocell
Patch and and Trace
Breakpoint
ROM
Table

Private Peripheral
Bus Adv. Peripheral
(internal) Bus
I-code bus
Bus
Matrix D-code bus
Serial Wire JTAG Debug System bus
Debug Port Access Port

2.2 Overview
2.2.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.

2.2.2 Integrated Configurable Debug

The Cortex-M3 processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris
implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification
for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.

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The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.

2.2.3 Trace Port Interface Unit (TPIU)

The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 55.

Figure 2-2. TPIU Block Diagram

Debug
ATB Trace Out Serial Wire
ATB Asynchronous FIFO
Interface (serializer) Trace Port
Slave
(SWO)
Port

APB
APB
Slave
Interface
Port

2.2.4 Cortex-M3 System Component Details

The Cortex-M3 includes the following system components:

■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 94).

■ Nested Vectored Interrupt Controller (NVIC)

An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 95).

■ System Control Block (SCB)

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The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 97).

■ Memory Protection Unit (MPU)

Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 97).

2.3 Programming Model

This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.

2.3.1 Processor Mode and Privilege Levels for Software Execution

The Cortex-M3 has two modes of operation:

■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.

■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.

In addition, the Cortex-M3 has two privilege levels:

■ Unprivileged
In this mode, software has the following restrictions:

– Limited access to the MSR and MRS instructions and no use of the CPS instruction

– No access to the system timer, NVIC, or system control block

– Possibly restricted access to memory or peripherals

■ Privileged
In this mode, software can use all the instructions and has access to all resources.

In Thread mode, the CONTROL register (see page 70) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.

2.3.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:

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the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 60).
In Thread mode, the CONTROL register (see page 70) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 57.

Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode Use Privilege Level Stack Used
a a
Thread Applications Privileged or unprivileged Main stack or process stack
Handler Exception handlers Always privileged Main stack
a. See CONTROL (page 70).

2.3.3 Register Map

Figure 2-3 on page 57 shows the Cortex-M3 register set. Table 2-2 on page 58 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.

Figure 2-3. Cortex-M3 Register Set

R0
R1
R2
R3
Low registers
R4
R5
R6 General-purpose registers
R7
R8
R9
High registers R10
R11
R12
Stack Pointer SP (R13) PSP‡ MSP‡ ‡
Banked version of SP
Link Register LR (R14)
Program Counter PC (R15)

PSR Program status register

PRIMASK
FAULTMASK Exception mask registers Special registers
BASEPRI
CONTROL CONTROL register

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Table 2-2. Processor Register Map

See
Offset Name Type Reset Description
page

- R0 R/W - Cortex General-Purpose Register 0 59

- R1 R/W - Cortex General-Purpose Register 1 59

- R2 R/W - Cortex General-Purpose Register 2 59

- R3 R/W - Cortex General-Purpose Register 3 59

- R4 R/W - Cortex General-Purpose Register 4 59

- R5 R/W - Cortex General-Purpose Register 5 59

- R6 R/W - Cortex General-Purpose Register 6 59

- R7 R/W - Cortex General-Purpose Register 7 59

- R8 R/W - Cortex General-Purpose Register 8 59

- R9 R/W - Cortex General-Purpose Register 9 59

- R10 R/W - Cortex General-Purpose Register 10 59

- R11 R/W - Cortex General-Purpose Register 11 59

- R12 R/W - Cortex General-Purpose Register 12 59

- SP R/W - Stack Pointer 60

- LR R/W 0xFFFF.FFFF Link Register 61

- PC R/W - Program Counter 62

- PSR R/W 0x0100.0000 Program Status Register 63

- PRIMASK R/W 0x0000.0000 Priority Mask Register 67

- FAULTMASK R/W 0x0000.0000 Fault Mask Register 68

- BASEPRI R/W 0x0000.0000 Base Priority Mask Register 69

- CONTROL R/W 0x0000.0000 Control Register 70

2.3.4 Register Descriptions

This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 57.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.

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Register 1: Cortex General-Purpose Register 0 (R0)

Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.

Cortex General-Purpose Register 0 (R0)

Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 DATA R/W - Register data.

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Register 14: Stack Pointer (SP)

The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.

Stack Pointer (SP)

Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SP

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SP

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 SP R/W - This field is the address of the stack pointer.

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Register 15: Link Register (LR)

The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 87 for the values and
description.

Link Register (LR)

Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LINK

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LINK

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 LINK R/W 0xFFFF.FFFF This field is the return address.

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Register 16: Program Counter (PC)

The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.

Program Counter (PC)

Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PC

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PC

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 PC R/W - This field is the current program address.

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Register 17: Program Status Register (PSR)

Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:

■ Application Program Status Register (APSR), bits 31:27,

■ Execution Program Status Register (EPSR), bits 26:24, 15:10

■ Interrupt Program Status Register (IPSR), bits 5:0

The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 85).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 63 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information about how to access the program status registers.

Table 2-3. PSR Register Combinations

Register Type Combination
a, b
PSR R/W APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
a
IAPSR R/W APSR and IPSR
b
EAPSR R/W APSR and EPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.

Program Status Register (PSR)

Type R/W, reset 0x0100.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

N Z C V Q ICI / IT THUMB reserved

Type R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ICI / IT reserved ISRNUM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31 N R/W 0 APSR Negative or Less Flag

Value Description
1 The previous operation result was negative or less than.
0 The previous operation result was positive, zero, greater than,
or equal.

The value of this bit is only meaningful when accessing PSR or APSR.

30 Z R/W 0 APSR Zero Flag

Value Description
1 The previous operation result was zero.
0 The previous operation result was non-zero.

The value of this bit is only meaningful when accessing PSR or APSR.

29 C R/W 0 APSR Carry or Borrow Flag

Value Description
1 The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0 The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.

The value of this bit is only meaningful when accessing PSR or APSR.

28 V R/W 0 APSR Overflow Flag

Value Description
1 The previous operation resulted in an overflow.
0 The previous operation did not result in an overflow.

The value of this bit is only meaningful when accessing PSR or APSR.

27 Q R/W 0 APSR DSP Overflow and Saturation Flag

Value Description
1 DSP Overflow or saturation has occurred.
0 DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.

The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.

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Bit/Field Name Type Reset Description

26:25 ICI / IT RO 0x0 EPSR ICI / IT status

These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.

24 THUMB RO 1 EPSR Thumb State

This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:

■ The BLX, BX and POP{PC} instructions

■ Restoration from the stacked xPSR value on an exception return

■ Bit 0 of the vector value on an exception entry or reset

Attempting to execute instructions when this bit is clear results in a fault

or lockup. See “Lockup” on page 89 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.

23:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:10 ICI / IT RO 0x0 EPSR ICI / IT status

These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
or POP instruction, the processor stops the load multiple or store multiple
instruction operation temporarily and stores the next register operand
in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes
execution of the multiple load or store instruction. When EPSR holds
the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.

9:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

5:0 ISRNUM RO 0x00 IPSR ISR Number

This field contains the exception type number of the current Interrupt
Service Routine (ISR).

Value Description
0x00 Thread mode
0x01 Reserved
0x02 NMI
0x03 Hard fault
0x04 Memory management fault
0x05 Bus fault
0x06 Usage fault
0x07-0x0A Reserved
0x0B SVCall
0x0C Reserved for Debug
0x0D Reserved
0x0E PendSV
0x0F SysTick
0x10 Interrupt Vector 0
0x11 Interrupt Vector 1
... ...
0x3B Interrupt Vector 43
0x3C-0x3F Reserved

See “Exception Types” on page 80 for more information.

The value of this field is only meaningful when accessing PSR or IPSR.

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Register 18: Priority Mask Register (PRIMASK)

The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on these instructions.
For more information on exception priority levels, see “Exception Types” on page 80.

Priority Mask Register (PRIMASK)

Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PRIMASK

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 PRIMASK R/W 0 Priority Mask

Value Description
1 Prevents the activation of all exceptions with configurable
priority.
0 No effect.

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Register 19: Fault Mask Register (FAULTMASK)

The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see “Exception
Types” on page 80.

Fault Mask Register (FAULTMASK)

Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FAULTMASK

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 FAULTMASK R/W 0 Fault Mask

Value Description
1 Prevents the activation of all exceptions except for NMI.
0 No effect.

The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.

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Register 20: Base Priority Mask Register (BASEPRI)

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 80.

Base Priority Mask Register (BASEPRI)

Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BASEPRI reserved

Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 BASEPRI R/W 0x0 Base Priority

Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.

Value Description
0x0 All exceptions are unmasked.
0x1 All exceptions with priority level 1-7 are masked.
0x2 All exceptions with priority level 2-7 are masked.
0x3 All exceptions with priority level 3-7 are masked.
0x4 All exceptions with priority level 4-7 are masked.
0x5 All exceptions with priority level 5-7 are masked.
0x6 All exceptions with priority level 6-7 are masked.
0x7 All exceptions with priority level 7 are masked.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 21: Control Register (CONTROL)

The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 87).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex™-M3/M4 Instruction Set Technical User's Manual, or perform an exception
return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 87.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M3/M4 Instruction Set Technical User's Manual.

Control Register (CONTROL)

Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ASP TMPL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 ASP R/W 0 Active Stack Pointer

Value Description
1 PSP is the current stack pointer.
0 MSP is the current stack pointer

In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.

0 TMPL R/W 0 Thread Mode Privilege Level

Value Description
1 Unprivileged software can be executed in Thread mode.
0 Only privileged software can be executed in Thread mode.

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2.3.5 Exceptions and Interrupts

The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 85 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 95 for more information.

2.3.6 Data Types

The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 73 for more information.

2.4 Memory Model

This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S1968 controller is provided in Table 2-4 on page 71. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 75).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 94).
Note: Within the memory map, all reserved space returns a bus fault when read or written.

Table 2-4. Memory Map

Start End Description For details,
see page ...
Memory
0x0000.0000 0x0003.FFFF On-chip Flash 265
0x0004.0000 0x1FFF.FFFF Reserved -
0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAM 259
0x2001.0000 0x21FF.FFFF Reserved -
0x2200.0000 0x221F.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 259
0x2000.0000
0x2220.0000 0x3FFF.FFFF Reserved -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 0 374
0x4000.1000 0x4000.3FFF Reserved -
0x4000.4000 0x4000.4FFF GPIO Port A 299
0x4000.5000 0x4000.5FFF GPIO Port B 299
0x4000.6000 0x4000.6FFF GPIO Port C 299
0x4000.7000 0x4000.7FFF GPIO Port D 299
0x4000.8000 0x4000.8FFF SSI0 487

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Table 2-4. Memory Map (continued)

Start End Description For details,
see page ...
0x4000.9000 0x4000.9FFF SSI1 487
0x4000.A000 0x4000.BFFF Reserved -
0x4000.C000 0x4000.CFFF UART0 441
0x4000.D000 0x4000.DFFF UART1 441
0x4000.E000 0x4000.EFFF UART2 441
0x4000.F000 0x4001.FFFF Reserved -
Peripherals
0x4002.0000 0x4002.0FFF I2C 0 528
0x4002.1000 0x4002.1FFF I2C 1 528
0x4002.2000 0x4002.3FFF Reserved -
0x4002.4000 0x4002.4FFF GPIO Port E 299
0x4002.5000 0x4002.5FFF GPIO Port F 299
0x4002.6000 0x4002.6FFF GPIO Port G 299
0x4002.7000 0x4002.7FFF GPIO Port H 299
0x4002.8000 0x4002.8FFF PWM 572
0x4002.9000 0x4002.BFFF Reserved -
0x4002.C000 0x4002.CFFF QEI0 607
0x4002.D000 0x4002.DFFF QEI1 607
0x4002.E000 0x4002.FFFF Reserved -
0x4003.0000 0x4003.0FFF Timer 0 346
0x4003.1000 0x4003.1FFF Timer 1 346
0x4003.2000 0x4003.2FFF Timer 2 346
0x4003.3000 0x4003.3FFF Timer 3 346
0x4003.4000 0x4003.7FFF Reserved -
0x4003.8000 0x4003.8FFF ADC0 404
0x4003.9000 0x4003.BFFF Reserved -
0x4003.C000 0x4003.CFFF Analog Comparators 550
0x4003.D000 0x400F.BFFF Reserved -
0x400F.C000 0x400F.CFFF Hibernation Module 246
0x400F.D000 0x400F.DFFF Flash memory control 265
0x400F.E000 0x400F.EFFF System control 185
0x400F.F000 0x41FF.FFFF Reserved -
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
0x4400.0000 0xDFFF.FFFF Reserved -
Private Peripheral Bus
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 54
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 54
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 54
0xE000.3000 0xE000.DFFF Reserved -
0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB) 102
0xE000.F000 0xE003.FFFF Reserved -

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Table 2-4. Memory Map (continued)

Start End Description For details,
see page ...
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 55
0xE004.1000 0xFFFF.FFFF Reserved -

2.4.1 Memory Regions, Types and Attributes

The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:

■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.

■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.

■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.

The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.

2.4.2 Memory System Ordering of Memory Accesses

For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 74).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.

2.4.3 Behavior of Memory Accesses

Table 2-5 on page 73 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 73 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 71 for more information).

Table 2-5. Memory Access Behavior

Address Range Memory Region Memory Type Execute Description
Never
(XN)
0x0000.0000 - 0x1FFF.FFFF Code Normal - This executable region is for program code.
Data can also be stored here.

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Table 2-5. Memory Access Behavior (continued)

Address Range Memory Region Memory Type Execute Description
Never
(XN)
0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 76).
0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band
alias areas (see Table 2-7 on page 76).
0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data.
0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral Strongly XN This region includes the NVIC, system
bus Ordered timer, and system control block.
0xE010.0000- 0xFFFF.FFFF Reserved - - -

The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 97.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.

2.4.4 Software Ordering of Memory Accesses

The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:

■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.

■ The processor has multiple bus interfaces.

■ Memory or devices in the memory map have different wait states.

■ Some memory accesses are buffered or speculative.

“Memory System Ordering of Memory Accesses” on page 73 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:

■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.

■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.

■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.

Memory barrier instructions can be used in the following situations:

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■ MPU programming

– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.

– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.

■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.

■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.

■ Memory map switching

If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.

■ Dynamic exception priority change

When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.

Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M3/M4 Instruction Set
Technical User's Manual.

2.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 76. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 76. For the specific address range of the bit-band regions,
see Table 2-4 on page 71.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.

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Table 2-6. SRAM Memory Bit-Banding Regions

Address Range
Memory Region Instruction and Data Accesses
Start End
0x2000.0000 0x2000.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x2200.0000 0x221F.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.

Table 2-7. Peripheral Memory Bit-Banding Regions

Address Range
Memory Region Instruction and Data Accesses
Start End
0x4000.0000 0x400F.FFFF Peripheral bit-band Direct accesses to this memory range behave as
region peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
0x4200.0000 0x43FF.FFFF Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.

The following formula shows how the alias region maps onto the bit-band region:

bit_word_offset = (byte_offset x 32) + (bit_number x 4)

bit_word_addr = bit_band_base + bit_word_offset

where:

bit_word_offset
The position of the target bit in the bit-band memory region.

bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.

bit_band_base
The starting address of the alias region.

byte_offset
The number of the byte in the bit-band region that contains the targeted bit.

bit_number
The bit position, 0-7, of the targeted bit.

Figure 2-4 on page 77 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:

■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:

0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)

■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:

0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)

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■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:

0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)

■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:

0x2200.001C = 0x2200.0000+ (0*32) + (7*4)

Figure 2-4. Bit-Band Mapping

32-MB Alias Region

0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0

0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000

1-MB SRAM Bit-Band Region

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0x200F.FFFF 0x200F.FFFE 0x200F.FFFD 0x200F.FFFC

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0x2000.0003 0x2000.0002 0x2000.0001 0x2000.0000

2.4.5.1 Directly Accessing an Alias Region

Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.

2.4.5.2 Directly Accessing a Bit-Band Region

“Behavior of Memory Accesses” on page 73 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.

2.4.6 Data Storage

The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the

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lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 78 illustrates how data is stored.

Figure 2-5. Data Storage

Memory Register
7 0

31 24 23 16 15 8 7 0
Address A B0 lsbyte B3 B2 B1 B0

A+1 B1

A+2 B2

A+3 B3 msbyte

2.4.7 Synchronization Primitives

The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:

■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.

■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.

The pairs of Load-Exclusive and Store-Exclusive instructions are:

■ The word instructions LDREX and STREX

■ The halfword instructions LDREXH and STREXH

■ The byte instructions LDREXB and STREXB

Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:

1. Use a Load-Exclusive instruction to read the value of the location.

2. Modify the value, as required.

3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.

4. Test the returned status bit.

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If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.

Software can use the synchronization primitives to implement a semaphore as follows:

1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.

2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.

3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.

The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:

■ It executes a CLREX instruction.

■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.

■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.

For more information about the synchronization primitive instructions, see the Cortex™-M3/M4
Instruction Set Technical User's Manual.

2.5 Exception Model

The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 81 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 40 interrupts (listed in Table 2-9 on page 82).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 95.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.

Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be

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re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).

See “Nested Vectored Interrupt Controller (NVIC)” on page 95 for more information on exceptions
and interrupts.

2.5.1 Exception States

Each exception is in one of the following states:

■ Inactive. The exception is not active and not pending.

■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.

■ Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.

■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.

2.5.2 Exception Types

The exception types are:

■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.

■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.

■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.

■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.

■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.

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■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:

– An undefined instruction

– An illegal unaligned access

– Invalid state on instruction execution

– An error on exception return

An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.

■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.

■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.

■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS

environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.

■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.

■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by

a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 82 lists the interrupts on the LM3S1968 controller.

For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 81 shows as having
configurable priority (see the SYSHNDCTRL register on page 136 and the DIS0 register on page 111).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 87.

Table 2-8. Exception Types

a
Exception Type Vector Priority Vector Address or Activation
b
Number Offset
- 0 - 0x0000.0000 Stack top is loaded from the first
entry of the vector table on reset.
Reset 1 -3 (highest) 0x0000.0004 Asynchronous
Non-Maskable Interrupt 2 -2 0x0000.0008 Asynchronous
(NMI)
Hard Fault 3 -1 0x0000.000C -
c
Memory Management 4 programmable 0x0000.0010 Synchronous

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Table 2-8. Exception Types (continued)

a
Exception Type Vector Priority Vector Address or Activation
b
Number Offset
c
Bus Fault 5 programmable 0x0000.0014 Synchronous when precise and
asynchronous when imprecise
c
Usage Fault 6 programmable 0x0000.0018 Synchronous
- 7-10 - - Reserved
c
SVCall 11 programmable 0x0000.002C Synchronous
c
Debug Monitor 12 programmable 0x0000.0030 Synchronous
- 13 - - Reserved
c
PendSV 14 programmable 0x0000.0038 Asynchronous
c
SysTick 15 programmable 0x0000.003C Asynchronous
d
Interrupts 16 and above programmable 0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 83.
c. See SYSPRI1 on page 133.
d. See PRIn registers on page 119.

Table 2-9. Interrupts

Vector Number Interrupt Number (Bit Vector Address or Description
in Interrupt Registers) Offset
0-15 - 0x0000.0000 - Processor exceptions
0x0000.003C
16 0 0x0000.0040 GPIO Port A
17 1 0x0000.0044 GPIO Port B
18 2 0x0000.0048 GPIO Port C
19 3 0x0000.004C GPIO Port D
20 4 0x0000.0050 GPIO Port E
21 5 0x0000.0054 UART0
22 6 0x0000.0058 UART1
23 7 0x0000.005C SSI0
24 8 0x0000.0060 I2C0
25 9 0x0000.0064 PWM Fault
26 10 0x0000.0068 PWM Generator 0
27 11 0x0000.006C PWM Generator 1
28 12 0x0000.0070 PWM Generator 2
29 13 0x0000.0074 QEI0
30 14 0x0000.0078 ADC0 Sequence 0
31 15 0x0000.007C ADC0 Sequence 1
32 16 0x0000.0080 ADC0 Sequence 2
33 17 0x0000.0084 ADC0 Sequence 3
34 18 0x0000.0088 Watchdog Timer 0
35 19 0x0000.008C Timer 0A
36 20 0x0000.0090 Timer 0B
37 21 0x0000.0094 Timer 1A

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Table 2-9. Interrupts (continued)

Vector Number Interrupt Number (Bit Vector Address or Description
in Interrupt Registers) Offset
38 22 0x0000.0098 Timer 1B
39 23 0x0000.009C Timer 2A
40 24 0x0000.00A0 Timer 2B
41 25 0x0000.00A4 Analog Comparator 0
42 26 0x0000.00A8 Analog Comparator 1
43 27 0x0000.00AC Analog Comparator 2
44 28 0x0000.00B0 System Control
45 29 0x0000.00B4 Flash Memory Control
46 30 0x0000.00B8 GPIO Port F
47 31 0x0000.00BC GPIO Port G
48 32 0x0000.00C0 GPIO Port H
49 33 0x0000.00C4 UART2
50 34 0x0000.00C8 SSI1
51 35 0x0000.00CC Timer 3A
52 36 0x0000.00D0 Timer 3B
53 37 0x0000.00D4 I2C1
54 38 0x0000.00D8 QEI1
55-58 39-42 - Reserved
59 43 0x0000.00EC Hibernation Module

2.5.3 Exception Handlers

The processor handles exceptions using:

■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.

■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.

■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.

2.5.4 Vector Table

The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 81. Figure 2-6 on page 84 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code

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Figure 2-6. Vector Table

Exception number IRQ number Offset Vector

59 43 IRQ43
0x00EC
. . .
. . .
. . .
0x004C
18 2 IRQ2
0x0048
17 1 IRQ1
0x0044
16 0 IRQ0
0x0040
15 -1 Systick
0x003C
14 -2 PendSV
0x0038
13 Reserved
12 Reserved for Debug
11 -5 SVCall
0x002C
10
9
Reserved
8
7
6 -10 Usage fault
0x0018
5 -11 Bus fault
0x0014
4 -12 Memory management fault
0x0010
3 -13 Hard fault
0x000C
2 -14 NMI
0x0008
1 Reset
0x0004
Initial SP value
0x0000

On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 83). Note
that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary.

2.5.5 Exception Priorities

As Table 2-8 on page 81 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 133 and
page 119.
Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means
that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always
have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].

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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.

2.5.6 Interrupt Priority Grouping

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:

■ An upper field that defines the group priority

■ A lower field that defines a subpriority within the group

Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 127.

2.5.7 Exception Entry and Return

Descriptions of exception handling use the following terms:

■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 85 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 86 more information.

■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 87 for
more information.

■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception

handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.

■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs

during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On

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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.

2.5.7.1 Exception Entry

Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 67, FAULTMASK on page 68, and BASEPRI on page 69). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.

Figure 2-7. Exception Stack Frame

...
Pre-IRQ top of stack
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0 IRQ top of stack

Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless
stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN
bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during
stacking.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.

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2.5.7.2 Exception Return

Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:

■ An LDM or POP instruction that loads the PC

■ A BX instruction using any register

■ An LDR instruction with the PC as the destination

EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 87
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.

Table 2-10. Exception Return Behavior

EXC_RETURN[31:0] Description
0xFFFF.FFF0 Reserved
0xFFFF.FFF1 Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved
0xFFFF.FFF9 Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC Reserved
0xFFFF.FFFD Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF Reserved

2.6 Fault Handling

Faults are a subset of the exceptions (see “Exception Model” on page 79). The following conditions
generate a fault:

■ A bus error on an instruction fetch or vector table load or a data access.

■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.

■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).

■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.

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2.6.1 Fault Types

Table 2-11 on page 88 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 140 for more
information about the fault status registers.

Table 2-11. Faults

Fault Handler Fault Status Register Bit Name
Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT
Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED
a
MPU or default memory mismatch on Memory management Memory Management Fault Status IERR
instruction access fault (MFAULTSTAT)
MPU or default memory mismatch on Memory management Memory Management Fault Status DERR
data access fault (MFAULTSTAT)
MPU or default memory mismatch on Memory management Memory Management Fault Status MSTKE
exception stacking fault (MFAULTSTAT)
MPU or default memory mismatch on Memory management Memory Management Fault Status MUSTKE
exception unstacking fault (MFAULTSTAT)
Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE
Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE
Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS
Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE
Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE
Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP
Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF
Attempt to enter an invalid instruction Usage fault Usage Fault Status (UFAULTSTAT) INVSTAT
b
set state
Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC
Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN
Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.

2.6.2 Fault Escalation and Hard Faults

All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 133). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 136).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 79.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:

■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.

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■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.

■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.

■ A fault occurs and the handler for that fault is not enabled.

If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.

2.6.3 Fault Status Registers and Fault Address Registers

The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 89.

Table 2-12. Fault Status and Fault Address Registers

Handler Status Register Name Address Register Name Register Description
Hard fault Hard Fault Status (HFAULTSTAT) - page 146
Memory management Memory Management Fault Status Memory Management Fault page 140
fault (MFAULTSTAT) Address (MMADDR) page 147
Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address page 140
(FAULTADDR) page 148
Usage fault Usage Fault Status (UFAULTSTAT) - page 140

2.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.

2.7 Power Management

The Cortex-M3 processor sleep modes reduce power consumption:

■ Sleep mode stops the processor clock.

■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.

The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 129). For more information about the behavior of the sleep modes, see “System
Control” on page 182.

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This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.

2.7.1 Entering Sleep Modes

This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.

2.7.1.1 Wait for Interrupt

The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 90). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.

2.7.1.2 Wait for Event

The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.

2.7.1.3 Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.

2.7.2 Wake Up from Sleep Mode

The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.

2.7.2.1 Wake Up from WFI or Sleep-on-Exit

Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 67 and page 68.

2.7.2.2 Wake Up from WFE

The processor wakes up if it detects an exception with sufficient priority to cause exception entry.

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In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 129.

2.8 Instruction Set Summary

The processor implements a version of the Thumb instruction set. Table 2-13 on page 91 lists the
supported instructions.
Note: In Table 2-13 on page 91:

■ Angle brackets, <>, enclose alternative forms of the operand

■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix

For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.

Table 2-13. Cortex-M3 Instruction Summary

Mnemonic Operands Brief Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V
ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V
ADR Rd, label Load PC-relative address -
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N,Z,C
B label Branch -
BFC Rd, #lsb, #width Bit field clear -
BFI Rd, Rn, #lsb, #width Bit field insert -
BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C
BKPT #imm Breakpoint -
BL label Branch with link -
BLX Rm Branch indirect with link -
BX Rm Branch indirect -
CBNZ Rn, label Compare and branch if non-zero -
CBZ Rn, label Compare and branch if zero -
CLREX - Clear exclusive -
CLZ Rd, Rm Count leading zeros -
CMN Rn, Op2 Compare negative N,Z,C,V
CMP Rn, Op2 Compare N,Z,C,V
CPSID i Change processor state, disable -
interrupts
CPSIE i Change processor state, enable -
interrupts
DMB - Data memory barrier -
DSB - Data synchronization barrier -

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Table 2-13. Cortex-M3 Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C
ISB - Instruction synchronization barrier -
IT - If-Then condition block -
LDM Rn{!}, reglist Load multiple registers, increment after -
LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement -
before
LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after -
LDR Rt, [Rn, #offset] Load register with word -
LDRB, LDRBT Rt, [Rn, #offset] Load register with byte -
LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes -
LDREX Rt, [Rn, #offset] Load register exclusive -
LDREXB Rt, [Rn] Load register exclusive with byte -
LDREXH Rt, [Rn] Load register exclusive with halfword -
LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword -
LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte -
LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword -
LDRT Rt, [Rn, #offset] Load register with word -
LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N,Z,C
MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result -
MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result -
MOV, MOVS Rd, Op2 Move N,Z,C
MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C
MOVT Rd, #imm16 Move top -
MRS Rd, spec_reg Move from special register to general -
register
MSR spec_reg, Rm Move from general register to special N,Z,C,V
register
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N,Z,C
NOP - No operation -
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C
POP reglist Pop registers from stack -
PUSH reglist Push registers onto stack -
RBIT Rd, Rn Reverse bits -
REV Rd, Rn Reverse byte order in a word -
REV16 Rd, Rn Reverse byte order in each halfword -
REVSH Rd, Rn Reverse byte order in bottom halfword -
and sign extend
ROR, RORS Rd, Rm, <Rs|#n> Rotate right N,Z,C
RRX, RRXS Rd, Rm Rotate right with extend N,Z,C

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Table 2-13. Cortex-M3 Instruction Summary (continued)

Mnemonic Operands Brief Description Flags
RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V
SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V
SBFX Rd, Rn, #lsb, #width Signed bit field extract -
SDIV {Rd,} Rn, Rm Signed divide -
SEV - Send event -
SMLAL RdLo, RdHi, Rn, Rm Signed multiply with accumulate -
(32x32+64), 64-bit result
SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result -
SSAT Rd, #n, Rm {,shift #s} Signed saturate Q
STM Rn{!}, reglist Store multiple registers, increment after -
STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement -
before
STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after -
STR Rt, [Rn {, #offset}] Store register word -
STRB, STRBT Rt, [Rn {, #offset}] Store register byte -
STRD Rt, Rt2, [Rn {, #offset}] Store register two words -
STREX Rt, Rt, [Rn {, #offset}] Store register exclusive -
STREXB Rd, Rt, [Rn] Store register exclusive byte -
STREXH Rd, Rt, [Rn] Store register exclusive halfword -
STRH, STRHT Rt, [Rn {, #offset}] Store register halfword -
STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte -
STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword -
STRT Rt, [Rn {, #offset}] Store register word -
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V
SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V
SVC #imm Supervisor call -
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte -
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword -
TBB [Rn, Rm] Table branch byte -
TBH [Rn, Rm, LSL #1] Table branch halfword -
TEQ Rn, Op2 Test equivalence N,Z,C
TST Rn, Op2 Test N,Z,C
UBFX Rd, Rn, #lsb, #width Unsigned bit field extract -
UDIV {Rd,} Rn, Rm Unsigned divide -
UMLAL RdLo, RdHi, Rn, Rm Unsigned multiply with accumulate -
(32x32+32+32), 64-bit result
UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result -
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
UXTB {Rd,} Rm, {,ROR #n} Zero extend a Byte -
UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword -
WFE - Wait for event -
WFI - Wait for interrupt -

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3 Cortex-M3 Peripherals
®
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals, including:

■ SysTick (see page 94)

Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.

■ Nested Vectored Interrupt Controller (NVIC) (see page 95)

– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers

■ System Control Block (SCB) (see page 97)

Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.

■ Memory Protection Unit (MPU) (see page 97)

Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.

Table 3-1 on page 94 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.

Table 3-1. Core Peripheral Register Regions

Address Core Peripheral Description (see page ...)
0xE000.E010-0xE000.E01F System Timer 94
0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 95
0xE000.EF00-0xE000.EF03
0xE000.ED00-0xE000.ED3F System Control Block 97
0xE000.ED90-0xE000.EDB8 Memory Protection Unit 97

3.1 Functional Description

This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.

3.1.1 System Timer (SysTick)

Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:

■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.

■ A high-speed alarm timer using the system clock.

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■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.

■ A simple counter used to measure time to completion and time used.

■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.

The timer consists of three registers:

■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.

■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.

■ SysTick Current Value (STCURRENT): The current value of the counter.

When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
Note: When the processor is halted for debugging, the counter does not decrement.

3.1.2 Nested Vectored Interrupt Controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:

■ 40 interrupts.

■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.

■ Low-latency exception and interrupt handling.

■ Level and pulse detection of interrupt signals.

■ Dynamic reprioritization of interrupts.

■ Grouping of priority values into group priority and subpriority fields.

■ Interrupt tail-chaining.

■ An external Non-maskable interrupt (NMI).

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The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.

3.1.2.1 Level-Sensitive and Pulse Interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 96 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.

3.1.2.2 Hardware and Software Control of Interrupts

The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:

■ The NVIC detects that the interrupt signal is High and the interrupt is not active.

■ The NVIC detects a rising edge on the interrupt signal.

■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 113 or SWTRIG on page 121.

A pending interrupt remains pending until one of the following:

■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:

– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.

– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.

■ Software writes to the corresponding interrupt clear-pending register bit

– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.

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– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.

3.1.3 System Control Block (SCB)

The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.

3.1.4 Memory Protection Unit (MPU)

This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 73 for more information).
Table 3-2 on page 97 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Stellaris Microcontroller” on page 101 for guidelines for programming a
microcontroller implementation.

Table 3-2. Memory Attributes Summary

Memory Type Description
Strongly Ordered All accesses to Strongly Ordered memory occur in program order.
Device Memory-mapped peripherals
Normal Normal memory

To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:

■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.

■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.

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The processor does not support unaligned accesses to MPU registers.

When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.

3.1.4.1 Updating an MPU Region

To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.

Updating an MPU Region Using Separate Words

This example simple code configures one region:

; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute

Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:

; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable

Software must use memory barrier instructions:

■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.

■ After MPU setup, if it includes memory transfers that must use the new MPU settings.

However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.

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For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.

Updating an MPU Region Using Multi-Word Writes

The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:

; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable

An STM instruction can be used to optimize this:

; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable

This operation can be done in two words for pre-packed information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 153) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:

; R1 = address and region number in one

; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable

Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 155) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.

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Example of SRD Use

Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 100 shows.

Figure 3-1. SRD Use Example

Region 2, with Offset from
subregions base address
512KB
448KB
384KB
320KB
256KB
Region 1 192KB
128KB
Disabled subregion
64KB
Disabled subregion
Base address of both regions 0

3.1.4.2 MPU Access Permission Attributes

The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 100 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M3 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Stellaris Microcontroller” on page 101 for information on programming the MPU for Stellaris
implementations.

Table 3-3. TEX, S, C, and B Bit Field Encoding

TEX S C B Memory Type Shareability Other Attributes
a
000b x 0 0 Strongly Ordered Shareable -
a
000 x 0 1 Device Shareable -
000 0 1 0 Normal Not shareable
000 1 1 0 Normal Shareable Outer and inner
write-through. No write
000 0 1 1 Normal Not shareable allocate.
000 1 1 1 Normal Shareable
001 0 0 0 Normal Not shareable Outer and inner
001 1 0 0 Normal Shareable noncacheable.
a
001 x 0 1 Reserved encoding - -
a
001 x 1 0 Reserved encoding - -
001 0 1 1 Normal Not shareable Outer and inner
write-back. Write and
001 1 1 1 Normal Shareable
read allocate.
a
010 x 0 0 Device Not shareable Nonshared Device.
a
010 x 0 1 Reserved encoding - -
a a
010 x 1 x Reserved encoding - -

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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)

TEX S C B Memory Type Shareability Other Attributes
1BB 0 A A Normal Not shareable Cached memory (BB =
outer policy, AA = inner
1BB 1 A A Normal Shareable
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
a. The MPU ignores the value of this bit.

Table 3-4 on page 101 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.

Table 3-4. Cache Policy for Memory Attribute Encoding

Encoding, AA or BB Corresponding Cache Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate

Table 3-5 on page 101 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.

Table 3-5. AP Bit Field Encoding

AP Bit Field Privileged Unprivileged Description
Permissions Permissions
000 No access No access All accesses generate a permission fault.
001 R/W No access Access from privileged software only.
010 R/W RO Writes by unprivileged software generate a
permission fault.
011 R/W R/W Full access.
100 Unpredictable Unpredictable Reserved.
101 RO No access Reads by privileged software only.
110 RO RO Read-only, by privileged or unprivileged software.
111 RO RO Read-only, by privileged or unprivileged software.

MPU Configuration for a Stellaris Microcontroller

Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should
be programmed as shown in Table 3-6 on page 101.

Table 3-6. Memory Region Attributes for Stellaris Microcontrollers

Memory Region TEX S C B Memory Type and Attributes
Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through
Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through
External SRAM 000b 1 1 1 Normal memory, shareable, write-back,
write-allocate
Peripherals 000b 1 0 1 Device memory, shareable

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In current Stellaris microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.

3.1.4.3 MPU Mismatch

When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 71 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 140 for more information.

3.2 Register Map

Table 3-7 on page 102 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU and SCB registers. The
offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.

Table 3-7. Peripherals Register Map

See
Offset Name Type Reset Description
page

System Timer (SysTick) Registers

0x010 STCTRL R/W 0x0000.0000 SysTick Control and Status Register 105

0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 107

0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 108

Nested Vectored Interrupt Controller (NVIC) Registers

0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 109

0x104 EN1 R/W 0x0000.0000 Interrupt 32-43 Set Enable 110

0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 111

0x184 DIS1 R/W 0x0000.0000 Interrupt 32-43 Clear Enable 112

0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 113

0x204 PEND1 R/W 0x0000.0000 Interrupt 32-43 Set Pending 114

0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 115

0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-43 Clear Pending 116

0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 117

0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-43 Active Bit 118

0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 119

0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 119

0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 119

0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 119

0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 119

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Table 3-7. Peripherals Register Map (continued)

See
Offset Name Type Reset Description
page

0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 119

0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 119

0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 119

0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 119

0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 119

0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 119

0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 121

System Control Block (SCB) Registers

0xD00 CPUID RO 0x411F.C231 CPU ID Base 122

0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 123

0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 126

0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 127

0xD10 SYSCTRL R/W 0x0000.0000 System Control 129

0xD14 CFGCTRL R/W 0x0000.0000 Configuration and Control 131

0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 133

0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 134

0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 135

0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 136

0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 140

0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 146

0xD34 MMADDR R/W - Memory Management Fault Address 147

0xD38 FAULTADDR R/W - Bus Fault Address 148

Memory Protection Unit (MPU) Registers

0xD90 MPUTYPE RO 0x0000.0800 MPU Type 149

0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 150

0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 152

0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 153

0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 155

0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 153

0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 155

0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 153

0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 155

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Table 3-7. Peripherals Register Map (continued)

See
Offset Name Type Reset Description
page

0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 153

0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 155

3.3 System Timer (SysTick) Register Descriptions

This section lists and describes the System Timer registers, in numerical order by address offset.

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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010

Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.

SysTick Control and Status Register (STCTRL)

Base 0xE000.E000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COUNT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CLK_SRC INTEN ENABLE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 COUNT RO 0 Count Flag

Value Description
0 The SysTick timer has not counted to 0 since the last time
this bit was read.
1 The SysTick timer has counted to 0 since the last time
this bit was read.

This bit is cleared by a read of the register or if the STCURRENT register

is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.

15:3 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 CLK_SRC R/W 0 Clock Source

Value Description
0 External reference clock. (Not implemented for most Stellaris
microcontrollers.)
1 System clock

Because an external reference clock is not implemented, this bit must

be set in order for SysTick to operate.

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Bit/Field Name Type Reset Description

1 INTEN R/W 0 Interrupt Enable

Value Description
0 Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
1 An interrupt is generated to the NVIC when SysTick counts
to 0.

0 ENABLE R/W 0 Enable

Value Description
0 The counter is disabled.
1 Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.

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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014

Note: This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.

SysTick Reload Value Register (STRELOAD)

Base 0xE000.E000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved RELOAD

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RELOAD

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:0 RELOAD R/W 0x00.0000 Reload Value

Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.

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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018

Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.

SysTick Current Value Register (STCURRENT)

Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved CURRENT

Type RO RO RO RO RO RO RO RO R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CURRENT

Type R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:0 CURRENT R/WC 0x00.0000 Current Value

This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.

3.4 NVIC Register Descriptions

This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 126.

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Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100

Note: This register can only be accessed from privileged mode.
The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.

Interrupt 0-31 Set Enable (EN0)

Base 0xE000.E000
Offset 0x100
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT R/W 0x0000.0000 Interrupt Enable

Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can only be cleared by setting the corresponding INT[n] bit in

the DISn register.

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Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104

Note: This register can only be accessed from privileged mode.
The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.

Interrupt 32-43 Set Enable (EN1)

Base 0xE000.E000
Offset 0x104
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INT

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 INT R/W 0x000 Interrupt Enable

Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can only be cleared by setting the corresponding INT[n] bit in

the DIS1 register.

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Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180

Note: This register can only be accessed from privileged mode.
The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt
31.
See Table 2-9 on page 82 for interrupt assignments.

Interrupt 0-31 Clear Enable (DIS0)

Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT R/W 0x0000.0000 Interrupt Disable

Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].

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Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184

Note: This register can only be accessed from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt
43. See Table 2-9 on page 82 for interrupt assignments.

Interrupt 32-43 Clear Enable (DIS1)

Base 0xE000.E000
Offset 0x184
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INT

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 INT R/W 0x000 Interrupt Disable

Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN1
register, disabling interrupt [n].

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Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200

Note: This register can only be accessed from privileged mode.
The PEND0 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.

Interrupt 0-31 Set Pending (PEND0)

Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT R/W 0x0000.0000 Interrupt Set Pending

Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

If the corresponding interrupt is already pending, setting a bit has no

effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.

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Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204

Note: This register can only be accessed from privileged mode.
The PEND1 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for
interrupt assignments.

Interrupt 32-43 Set Pending (PEND1)

Base 0xE000.E000
Offset 0x204
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INT

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 INT R/W 0x000 Interrupt Set Pending

Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

If the corresponding interrupt is already pending, setting a bit has no

effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND1 register.

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Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280

Note: This register can only be accessed from privileged mode.
The UNPEND0 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.

Interrupt 0-31 Clear Pending (UNPEND0)

Base 0xE000.E000
Offset 0x280
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT R/W 0x0000.0000 Interrupt Clear Pending

Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.

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Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284

Note: This register can only be accessed from privileged mode.
The UNPEND1 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table
2-9 on page 82 for interrupt assignments.

Interrupt 32-43 Clear Pending (UNPEND1)

Base 0xE000.E000
Offset 0x284
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INT

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 INT R/W 0x000 Interrupt Clear Pending

Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND1
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.

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Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300

Note: This register can only be accessed from privileged mode.
The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31
corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.

Caution – Do not manually set or clear the bits in this register.

Interrupt 0-31 Active Bit (ACTIVE0)

Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 INT RO 0x0000.0000 Interrupt Active

Value Description
0 The corresponding interrupt is not active.
1 The corresponding interrupt is active, or active and pending.

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Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304

Note: This register can only be accessed from privileged mode.
The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit
11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments.

Caution – Do not manually set or clear the bits in this register.

Interrupt 32-43 Active Bit (ACTIVE1)

Base 0xE000.E000
Offset 0x304
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 INT RO 0x000 Interrupt Active

Value Description
0 The corresponding interrupt is not active.
1 The corresponding interrupt is active, or active and pending.

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Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400

Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420
Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428
Note: This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible.
Each register holds four priority fields that are assigned to interrupts as follows:

PRIn Register Bit Field Interrupt

Bits 31:29 Interrupt [4n+3]
Bits 23:21 Interrupt [4n+2]
Bits 15:13 Interrupt [4n+1]
Bits 7:5 Interrupt [4n]

See Table 2-9 on page 82 for interrupt assignments.

Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 127) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.

Interrupt 0-3 Priority (PRI0)

Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INTD reserved INTC reserved

Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTB reserved INTA reserved

Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31:29 INTD R/W 0x0 Interrupt Priority for Interrupt [4n+3]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 INTC R/W 0x0 Interrupt Priority for Interrupt [4n+2]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:13 INTB R/W 0x0 Interrupt Priority for Interrupt [4n+1]

This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 INTA R/W 0x0 Interrupt Priority for Interrupt [4n]

This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00

Note: Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 82 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 131) is
set, unprivileged software can access the SWTRIG register.

Software Trigger Interrupt (SWTRIG)

Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INTID

Type RO RO RO RO RO RO RO RO RO RO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:0 INTID WO 0x00 Interrupt ID

This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.

3.5 System Control Block (SCB) Register Descriptions

This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.

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Register 26: CPU ID Base (CPUID), offset 0xD00

Note: This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and
implementation information.

CPU ID Base (CPUID)

Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x411F.C231
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IMP VAR CON

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PARTNO REV

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1

Bit/Field Name Type Reset Description

31:24 IMP RO 0x41 Implementer Code

Value Description
0x41 ARM

23:20 VAR RO 0x1 Variant Number

Value Description
0x1 The rn value in the rnpn product revision identifier, for example,
the 1 in r1p1.

19:16 CON RO 0xF Constant

Value Description
0xF Always reads as 0xF.

15:4 PARTNO RO 0xC23 Part Number

Value Description
0xC23 Cortex-M3 processor.

3:0 REV RO 0x1 Revision Number

Value Description
0x1 The pn value in the rnpn product revision identifier, for example,
the 1 in r1p1.

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Register 27: Interrupt Control and State (INTCTRL), offset 0xD04

Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.

Interrupt Control and State (INTCTRL)

Base 0xE000.E000
Offset 0xD04
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NMISET reserved PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND reserved VECPEND

Type R/W RO RO R/W WO R/W WO RO RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VECPEND RETBASE reserved VECACT

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 NMISET R/W 0 NMI Set Pending

Value Description
0 On a read, indicates an NMI exception is not pending.
On a write, no effect.
1 On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.

Because NMI is the highest-priority exception, normally the processor

enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.

30:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

28 PENDSV R/W 0 PendSV Set Pending

Value Description
0 On a read, indicates a PendSV exception is not pending.
On a write, no effect.
1 On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.

Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.

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Bit/Field Name Type Reset Description

27 UNPENDSV WO 0 PendSV Clear Pending

Value Description
0 On a write, no effect.
1 On a write, removes the pending state from the PendSV
exception.

This bit is write only; on a register read, its value is unknown.

26 PENDSTSET R/W 0 SysTick Set Pending

Value Description
0 On a read, indicates a SysTick exception is not pending.
On a write, no effect.
1 On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.

This bit is cleared by writing a 1 to the PENDSTCLR bit.

25 PENDSTCLR WO 0 SysTick Clear Pending

Value Description
0 On a write, no effect.
1 On a write, removes the pending state from the SysTick
exception.

This bit is write only; on a register read, its value is unknown.

24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23 ISRPRE RO 0 Debug Interrupt Handling

Value Description
0 The release from halt does not take an interrupt.
1 The release from halt takes an interrupt.

This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.

22 ISRPEND RO 0 Interrupt Pending

Value Description
0 No interrupt is pending.
1 An interrupt is pending.

This bit provides status for all interrupts excluding NMI and Faults.

21:18 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

17:12 VECPEND RO 0x00 Interrupt Pending Vector Number

This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.

Value Description
0x00 No exceptions are pending
0x01 Reserved
0x02 NMI
0x03 Hard fault
0x04 Memory management fault
0x05 Bus fault
0x06 Usage fault
0x07-0x0A Reserved
0x0B SVCall
0x0C Reserved for Debug
0x0D Reserved
0x0E PendSV
0x0F SysTick
0x10 Interrupt Vector 0
0x11 Interrupt Vector 1
... ...
0x3B Interrupt Vector 43
0x3C-0x3F Reserved

11 RETBASE RO 0 Return to Base

Value Description
0 There are preempted active exceptions to execute.
1 There are no active exceptions, or the currently executing
exception is the only active exception.

This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).

10:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:0 VECACT RO 0x00 Interrupt Pending Vector Number

This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 63).

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Register 28: Vector Table Offset (VTABLE), offset 0xD08

Note: This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.

Vector Table Offset (VTABLE)

Base 0xE000.E000
Offset 0xD08
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved BASE OFFSET

Type RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET reserved

Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:30 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

29 BASE R/W 0 Vector Table Base

Value Description
0 The vector table is in the code memory region.
1 The vector table is in the SRAM memory region.

28:8 OFFSET R/W 0x000.00 Vector Table Offset

When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 43
interrupts, the offset must be aligned on a 256-byte boundary.

7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note: This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-8 on page 127 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.

Table 3-8. Interrupt Priority Levels

a
PRIGROUP Bit Field Binary Point Group Priority Field Subpriority Field Group Subpriorities
Priorities
0x0 - 0x4 bxxx. [7:5] None 8 1
0x5 bxx.y [7:6] [5] 4 2
0x6 bx.yy [7] [6:5] 2 4
0x7 b.yyy None [7:5] 1 8
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.

Application Interrupt and Reset Control (APINT)

Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VECTKEY

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ENDIANESS reserved PRIGROUP reserved SYSRESREQ VECTCLRACT VECTRESET

Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO WO WO WO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 VECTKEY R/W 0xFA05 Register Key

This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.

15 ENDIANESS RO 0 Data Endianess

The Stellaris implementation uses only little-endian mode so this is
cleared to 0.

14:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

10:8 PRIGROUP R/W 0x0 Interrupt Priority Grouping

This field determines the split of group priority from subpriority (see
Table 3-8 on page 127 for more information).

7:3 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 SYSRESREQ WO 0 System Reset Request

Value Description
0 No effect.
1 Resets the core and all on-chip peripherals except the Debug
interface.

This bit is automatically cleared during the reset of the core and reads
as 0.

1 VECTCLRACT WO 0 Clear Active NMI / Fault

This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.

0 VECTRESET WO 0 System Reset

This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.

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Register 30: System Control (SYSCTRL), offset 0xD10

Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.

System Control (SYSCTRL)

Base 0xE000.E000
Offset 0xD10
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved

Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 SEVONPEND R/W 0 Wake Up on Pending

Value Description
0 Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1 Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.

When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 SLEEPDEEP R/W 0 Deep Sleep Enable

Value Description
0 Use Sleep mode as the low power mode.
1 Use Deep-sleep mode as the low power mode.

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Bit/Field Name Type Reset Description

1 SLEEPEXIT R/W 0 Sleep on ISR Exit

Value Description
0 When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
1 When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.

Setting this bit enables an interrupt-driven application to avoid returning

to an empty main application.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 31: Configuration and Control (CFGCTRL), offset 0xD14

Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 121).

Configuration and Control (CFGCTRL)

Base 0xE000.E000
Offset 0xD14
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved STKALIGN BFHFNMIGN reserved DIV0 UNALIGNED reserved MAINPEND BASETHR

Type RO RO RO RO RO RO R/W R/W RO RO RO R/W R/W RO R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 STKALIGN R/W 0 Stack Alignment on Exception Entry

Value Description
0 The stack is 4-byte aligned.
1 The stack is 8-byte aligned.

On exception entry, the processor uses bit 9 of the stacked PSR to

indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.

8 BFHFNMIGN R/W 0 Ignore Bus Fault in NMI and Fault

This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.

Value Description
0 Data bus faults caused by load and store instructions cause a
lock-up.
1 Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.

Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.

7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

4 DIV0 R/W 0 Trap on Divide by 0

This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.

Value Description
0 Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1 Trap on divide by 0.

3 UNALIGNED R/W 0 Trap on Unaligned Access

Value Description
0 Do not trap on unaligned halfword and word accesses.
1 Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.

Unaligned LDM, STM, LDRD, and STRD instructions always fault

regardless of whether UNALIGNED is set.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 MAINPEND R/W 0 Allow Main Interrupt Trigger

Value Description
0 Disables unprivileged software access to the SWTRIG register.
1 Enables unprivileged software access to the SWTRIG register
(see page 121).

0 BASETHR R/W 0 Thread State Control

Value Description
0 The processor can enter Thread mode only when no exception
is active.
1 The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 87 for more information).

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Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18

Note: This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.

System Handler Priority 1 (SYSPRI1)

Base 0xE000.E000
Offset 0xD18
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved USAGE reserved

Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUS reserved MEM reserved

Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 USAGE R/W 0x0 Usage Fault Priority

This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.

20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:13 BUS R/W 0x0 Bus Fault Priority

This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.

12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 MEM R/W 0x0 Memory Management Fault Priority

This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.

4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C

Note: This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.

System Handler Priority 2 (SYSPRI2)

Base 0xE000.E000
Offset 0xD1C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SVC reserved

Type R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 SVC R/W 0x0 SVCall Priority

This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.

28:0 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20

Note: This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.

System Handler Priority 3 (SYSPRI3)

Base 0xE000.E000
Offset 0xD20
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TICK reserved PENDSV reserved

Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DEBUG reserved

Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 TICK R/W 0x0 SysTick Exception Priority

This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.

28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:21 PENDSV R/W 0x0 PendSV Priority

This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.

20:8 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 DEBUG R/W 0x0 Debug Priority

This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.

4:0 reserved RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note: This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.

Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.

System Handler Control and State (SYSHNDCTRL)

Base 0xE000.E000
Offset 0xD24
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved USAGE BUS MEM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SVC BUSP MEMP USAGEP TICK PNDSV reserved MON SVCA reserved USGA reserved BUSA MEMA

Type R/W R/W R/W R/W R/W R/W RO R/W R/W RO RO RO R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

18 USAGE R/W 0 Usage Fault Enable

Value Description
0 Disables the usage fault exception.
1 Enables the usage fault exception.

17 BUS R/W 0 Bus Fault Enable

Value Description
0 Disables the bus fault exception.
1 Enables the bus fault exception.

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Bit/Field Name Type Reset Description

16 MEM R/W 0 Memory Management Fault Enable

Value Description
0 Disables the memory management fault exception.
1 Enables the memory management fault exception.

15 SVC R/W 0 SVC Call Pending

Value Description
0 An SVC call exception is not pending.
1 An SVC call exception is pending.

This bit can be modified to change the pending status of the SVC call
exception.

14 BUSP R/W 0 Bus Fault Pending

Value Description
0 A bus fault exception is not pending.
1 A bus fault exception is pending.

This bit can be modified to change the pending status of the bus fault
exception.

13 MEMP R/W 0 Memory Management Fault Pending

Value Description
0 A memory management fault exception is not pending.
1 A memory management fault exception is pending.

This bit can be modified to change the pending status of the memory
management fault exception.

12 USAGEP R/W 0 Usage Fault Pending

Value Description
0 A usage fault exception is not pending.
1 A usage fault exception is pending.

This bit can be modified to change the pending status of the usage fault
exception.

11 TICK R/W 0 SysTick Exception Active

Value Description
0 A SysTick exception is not active.
1 A SysTick exception is active.

This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.

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Bit/Field Name Type Reset Description

10 PNDSV R/W 0 PendSV Exception Active

Value Description
0 A PendSV exception is not active.
1 A PendSV exception is active.

This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.

9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 MON R/W 0 Debug Monitor Active

Value Description
0 The Debug monitor is not active.
1 The Debug monitor is active.

7 SVCA R/W 0 SVC Call Active

Value Description
0 SVC call is not active.
1 SVC call is active.

This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.

6:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 USGA R/W 0 Usage Fault Active

Value Description
0 Usage fault is not active.
1 Usage fault is active.

This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BUSA R/W 0 Bus Fault Active

Value Description
0 Bus fault is not active.
1 Bus fault is active.

This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.

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Bit/Field Name Type Reset Description

0 MEMA R/W 0 Memory Management Fault Active

Value Description
0 Memory management fault is not active.
1 Memory management fault is active.

This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.

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Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28

Note: This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:

■ Usage Fault Status (UFAULTSTAT), bits 31:16

■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0

FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:

■ The complete FAULTSTAT register, with a word access to offset 0xD28

■ The MFAULTSTAT, with a byte access to offset 0xD28
■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
■ The BFAULTSTAT, with a byte access to offset 0xD29
■ The UFAULTSTAT, with a halfword access to offset 0xD2A

Bits are cleared by writing a 1 to them.

In a fault handler, the true faulting address can be determined by:

1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.

2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.

Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.

Configurable Fault Status (FAULTSTAT)

Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved DIV0 UNALIGN reserved NOCP INVPC INVSTAT UNDEF

Type RO RO RO RO RO RO R/W1C R/W1C RO RO RO RO R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BFARV reserved BSTKE BUSTKE IMPRE PRECISE IBUS MMARV reserved MSTKE MUSTKE reserved DERR IERR

Type R/W1C RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO RO R/W1C R/W1C RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:26 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

25 DIV0 R/W1C 0 Divide-by-Zero Usage Fault

Value Description
0 No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
1 The processor has executed an SDIV or UDIV instruction with
a divisor of 0.

When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 131).
This bit is cleared by writing a 1 to it.

24 UNALIGN R/W1C 0 Unaligned Access Usage Fault

Value Description
0 No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
1 The processor has made an unaligned memory access.

Unaligned LDM, STM, LDRD, and STRD instructions always fault

regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 131).
This bit is cleared by writing a 1 to it.

23:20 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 NOCP R/W1C 0 No Coprocessor Usage Fault

Value Description
0 A usage fault has not been caused by attempting to access a
coprocessor.
1 The processor has attempted to access a coprocessor.

This bit is cleared by writing a 1 to it.

18 INVPC R/W1C 0 Invalid PC Load Usage Fault

Value Description
0 A usage fault has not been caused by attempting to load an
invalid PC value.
1 The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.

When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

17 INVSTAT R/W1C 0 Invalid State Usage Fault

Value Description
0 A usage fault has not been caused by an invalid state.
1 The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.

When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.

16 UNDEF R/W1C 0 Undefined Instruction Usage Fault

Value Description
0 A usage fault has not been caused by an undefined instruction.
1 The processor has attempted to execute an undefined
instruction.

When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.

15 BFARV R/W1C 0 Bus Fault Address Register Valid

Value Description
0 The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
1 The FAULTADDR register is holding a valid fault address.

This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.

14:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

12 BSTKE R/W1C 0 Stack Bus Fault

Value Description
0 No bus fault has occurred on stacking for exception entry.
1 Stacking for an exception entry has caused one or more bus
faults.

When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.

11 BUSTKE R/W1C 0 Unstack Bus Fault

Value Description
0 No bus fault has occurred on unstacking for a return from
exception.
1 Unstacking for a return from exception has caused one or more
bus faults.

This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.

10 IMPRE R/W1C 0 Imprecise Data Bus Error

Value Description
0 An imprecise data bus error has not occurred.
1 A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.

When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.

9 PRECISE R/W1C 0 Precise Data Bus Error

Value Description
0 A precise data bus error has not occurred.
1 A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.

When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

8 IBUS R/W1C 0 Instruction Bus Error

Value Description
0 An instruction bus error has not occurred.
1 An instruction bus error has occurred.

The processor detects the instruction bus error on prefetching an

instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.

7 MMARV R/W1C 0 Memory Management Fault Address Register Valid

Value Description
0 The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1 The MMADDR register is holding a valid fault address.

If a memory management fault occurs and is escalated to a hard fault

because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.

6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 MSTKE R/W1C 0 Stack Access Violation

Value Description
0 No memory management fault has occurred on stacking for
exception entry.
1 Stacking for an exception entry has caused one or more access
violations.

When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.

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Bit/Field Name Type Reset Description

3 MUSTKE R/W1C 0 Unstack Access Violation

Value Description
0 No memory management fault has occurred on unstacking for
a return from exception.
1 Unstacking for a return from exception has caused one or more
access violations.

This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
This bit is cleared by writing a 1 to it.

2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 DERR R/W1C 0 Data Access Violation

Value Description
0 A data access violation has not occurred.
1 The processor attempted a load or store at a location that does
not permit the operation.

When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
This bit is cleared by writing a 1 to it.

0 IERR R/W1C 0 Instruction Access Violation

Value Description
0 An instruction access violation has not occurred.
1 The processor attempted an instruction fetch from a location
that does not permit execution.

This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.

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Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C

Note: This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.

Hard Fault Status (HFAULTSTAT)

Base 0xE000.E000
Offset 0xD2C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBG FORCED reserved

Type R/W1C R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VECT reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 DBG R/W1C 0 Debug Event

This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.

30 FORCED R/W1C 0 Forced Hard Fault

Value Description
0 No forced hard fault has occurred.
1 A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.

When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.

29:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 VECT R/W1C 0 Vector Table Read Fault

Value Description
0 No bus fault has occurred on a vector table read.
1 A bus fault occurred on a vector table read.

This error is always handled by the hard fault handler.

When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 38: Memory Management Fault Address (MMADDR), offset 0xD34

Note: This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 140).

Memory Management Fault Address (MMADDR)

Base 0xE000.E000
Offset 0xD34
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 ADDR R/W - Fault Address

When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.

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Register 39: Bus Fault Address (FAULTADDR), offset 0xD38

Note: This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 140).

Bus Fault Address (FAULTADDR)

Base 0xE000.E000
Offset 0xD38
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 ADDR R/W - Fault Address

When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.

3.6 Memory Protection Unit (MPU) Register Descriptions

This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.

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Register 40: MPU Type (MPUTYPE), offset 0xD90

Note: This register can only be accessed from privileged mode.
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.

MPU Type (MPUTYPE)

Base 0xE000.E000
Offset 0xD90
Type RO, reset 0x0000.0800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved IREGION

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DREGION reserved SEPARATE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:16 IREGION RO 0x00 Number of I Regions

This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.

15:8 DREGION RO 0x08 Number of D Regions

Value Description
0x08 Indicates there are eight supported MPU data regions.

7:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 SEPARATE RO 0 Separate or Unified MPU

Value Description
0 Indicates the MPU is unified.

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Register 41: MPU Control (MPUCTRL), offset 0xD94

Note: This register can only be accessed from privileged mode.
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:

■ For privileged accesses, the default memory map is as described in “Memory Model” on page 71.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.

■ Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.

Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPU is not implemented (see Table 2-5 on page 73 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.

MPU Control (MPUCTRL)

Base 0xE000.E000
Offset 0xD94
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PRIVDEFEN HFNMIENA ENABLE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

2 PRIVDEFEN R/W 0 MPU Default Region

This bit enables privileged software access to the default memory map.

Value Description
0 If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
1 If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.

When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.

1 HFNMIENA R/W 0 MPU Enabled During Faults

This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.

Value Description
0 The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
1 The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.

When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.

0 ENABLE R/W 0 MPU Enable

Value Description
0 The MPU is disabled.
1 The MPU is enabled.

When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.

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Register 42: MPU Region Number (MPUNUMBER), offset 0xD98

Note: This register can only be accessed from privileged mode.
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 153). This write updates the value of the REGION field.

MPU Region Number (MPUNUMBER)

Base 0xE000.E000
Offset 0xD98
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved NUMBER

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 NUMBER R/W 0x0 MPU Region to Access

This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.

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Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C

Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
Note: This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of N where:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.

MPU Region Base Address (MPUBASE)

Base 0xE000.E000
Offset 0xD9C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR VALID reserved REGION

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 ADDR R/W 0x0000.000 Base Address Mask

Bits 31:N in this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

4 VALID WO 0 Region Number Valid

Value Description
0 The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
1 The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.

This bit is always read as 0.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 REGION R/W 0x0 Region Number

On a write, contains the value to be written to the MPUNUMBER register.
On a read, returns the current region number in the MPUNUMBER
register.

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Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note: This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-9 on page 155 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.

Table 3-9. Example SIZE Field Values

a
SIZE Encoding Region Size Value of N Note
00100b (0x4) 32 B 5 Minimum permitted size
01001b (0x9) 1 KB 10 -
10011b (0x13) 1 MB 20 -
11101b (0x1D) 1 GB 30 -
11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size
region occupies the complete
memory map.
a. Refers to the N parameter in the MPUBASE register (see page 153).

MPU Region Attribute and Size (MPUATTR)

Base 0xE000.E000
Offset 0xDA0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved XN reserved AP reserved TEX S C B

Type RO RO RO R/W RO R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRD reserved SIZE ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit/Field Name Type Reset Description

31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

28 XN R/W 0 Instruction Access Disable

Value Description
0 Instruction fetches are enabled.
1 Instruction fetches are disabled.

27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26:24 AP R/W 0 Access Privilege

For information on using this bit field, see Table 3-5 on page 101.

23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

21:19 TEX R/W 0x0 Type Extension Mask

For information on using this bit field, see Table 3-3 on page 100.

18 S R/W 0 Shareable
For information on using this bit, see Table 3-3 on page 100.

17 C R/W 0 Cacheable
For information on using this bit, see Table 3-3 on page 100.

16 B R/W 0 Bufferable
For information on using this bit, see Table 3-3 on page 100.

15:8 SRD R/W 0x00 Subregion Disable Bits

Value Description
0 The corresponding subregion is enabled.
1 The corresponding subregion is disabled.

Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 99 for more information.

7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:1 SIZE R/W 0x0 Region Size Mask

The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-9 on page 155 for more
information.

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Bit/Field Name Type Reset Description

0 ENABLE R/W 0 Region Enable

Value Description
0 The region is disabled.
1 The region is enabled.

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4 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
®
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
The Stellaris JTAG module has the following features:

■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

■ Four-bit Instruction Register (IR) chain for storing JTAG instructions

■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST

■ ARM additional instructions: APACC, DPACC and ABORT

■ Integrated ARM Serial Wire Debug (SWD)

See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.

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4.1 Block Diagram

Figure 4-1. JTAG Module Block Diagram

TRST
TCK TAP Controller
TMS

TDI Instruction Register (IR)

BYPASS Data Register

TDO

Boundary Scan Data Register

IDCODE Data Register

ABORT Data Register

DPACC Data Register

APACC Data Register

Cortex-M3
Debug
Port

4.2 Signal Description

Table 4-1 on page 159 and Table 4-2 on page 160 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The JTAG/SWD controller signals are under commit protection and require a special process to be
configured as GPIOs, see “Commit Control” on page 295. The column in the table below titled "Pin
Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in
the GPIO Alternate Function Select (GPIOAFSEL) register (page 309) is set to choose the
JTAG/SWD function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 286.

Table 4-1. JTAG_SWD_SWO Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
SWCLK 80 I TTL JTAG/SWD CLK.
SWDIO 79 I/O TTL JTAG TMS and SWDIO.
SWO 77 O TTL JTAG TDO and SWO.
TCK 80 I TTL JTAG/SWD CLK.
TDI 78 I TTL JTAG TDI.
TDO 77 O TTL JTAG TDO and SWO.
TMS 79 I/O TTL JTAG TMS and SWDIO.
TRST 89 I TTL JTAG TRST.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

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Table 4-2. JTAG_SWD_SWO Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
SWCLK A9 I TTL JTAG/SWD CLK.
SWDIO B9 I/O TTL JTAG TMS and SWDIO.
SWO A10 O TTL JTAG TDO and SWO.
TCK A9 I TTL JTAG/SWD CLK.
TDI B8 I TTL JTAG TDI.
TDO A10 O TTL JTAG TDO and SWO.
TMS B9 I/O TTL JTAG TMS and SWDIO.
TRST A8 I TTL JTAG TRST.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

4.3 Functional Description

A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 159. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-4 on page 167 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 658 for JTAG timing diagrams.

4.3.1 JTAG Interface Pins

The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 4-3 on page 160. Detailed information on each pin
follows.

Table 4-3. JTAG Port Pins Reset State

Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z

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4.3.1.1 Test Reset Input (TRST)

The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.

4.3.1.2 Test Clock Input (TCK)

The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.

4.3.1.3 Test Mode Select (TMS)

The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 4-2 on page 163.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.

4.3.1.4 Test Data Input (TDI)

The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.

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4.3.1.5 Test Data Output (TDO)

The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.

4.3.2 JTAG TAP Controller

The JTAG TAP controller state machine is shown in Figure 4-2 on page 163. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.

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Figure 4-2. Test Access Port State Machine

Test Logic Reset

1 0

Run Test Idle Select DR Scan Select IR Scan

1 1 1
0 0 0

Capture DR Capture IR
1 1
0 0

Shift DR Shift IR
1 0 1 0

Exit 1 DR Exit 1 IR
1 1
0 0

Pause DR Pause IR

1 0 1 0

Exit 2 DR Exit 2 IR
0 0
1 1

Update DR Update IR
1 0 1 0

4.3.3 Shift Registers

The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 166.

4.3.4 Operational Considerations

There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.

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4.3.4.1 GPIO Functionality

When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.

Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins
to their GPIO functionality, the debugger may not have enough time to connect and halt the controller
before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be
avoided with a software routine that restores JTAG functionality based on an external or software
trigger.

The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 309) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 319) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 320) have been set to 1.

Recovering a "Locked" Device

Note: The mass erase of the flash memory caused by the below sequence erases the entire flash
memory, regardless of the settings in the Flash Memory Protection Program Enable n
(FMPPEn) registers. Performing the sequence below does not affect the nonvolatile registers
discussed in “Nonvolatile Register Programming” on page 263.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:

1. Assert and hold the RST signal.

2. Apply power to the device.

3. Perform the JTAG-to-SWD switch sequence.

4. Perform the SWD-to-JTAG switch sequence.

5. Perform the JTAG-to-SWD switch sequence.

6. Perform the SWD-to-JTAG switch sequence.

7. Perform the JTAG-to-SWD switch sequence.

8. Perform the SWD-to-JTAG switch sequence.

9. Perform the JTAG-to-SWD switch sequence.

10. Perform the SWD-to-JTAG switch sequence.

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11. Perform the JTAG-to-SWD switch sequence.

12. Perform the SWD-to-JTAG switch sequence.

13. Release the RST signal.

14. Wait 400 ms.

15. Power-cycle the device.

The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 165. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence in the section called
“JTAG-to-SWD Switching” on page 165 must be performed.

4.3.4.2 Communication with JTAG/SWD

Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.

4.3.4.3 ARM Serial Wire Debug (SWD)

In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Debug Interface V5 Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.

JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit
TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted
LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The
complete switch sequence should consist of the following transactions on the TCK/SWCLK and
TMS/SWDIO signals:

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1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.

2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO.

3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in SWD mode before sending the switch sequence, the SWD goes into the line reset state.

To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating
mode, perform a SWD READID operation. The ID value can be compared against the device's
known ID to verify the switch.

SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:

1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.

2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO.

3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset
state.

To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the device's known IDCODE to verify the switch.

4.4 Initialization and Configuration

After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to
enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG
pins (PB7 andPC[3:0]) should be reverted to their default settings.

4.5 Register Descriptions

There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.

4.5.1 Instruction Register (IR)

The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction

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Register bits is shown in Table 4-4 on page 167. A detailed explanation of each instruction, along
with its associated Data Register, follows.

Table 4-4. JTAG Instruction Register Commands

IR[3:0] Instruction Description
0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0001 INTEST Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
0010 SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
1110 IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.

4.5.1.1 EXTEST Instruction

The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan
Data Register can be accessed to sample and shift out the current data and load new data into the
Boundary Scan Data Register.

4.5.1.2 INTEST Instruction

The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary
Scan Data Register can be accessed to sample and shift out the current data and load new data
into the Boundary Scan Data Register.

4.5.1.3 SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while

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the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 169 for more information.

4.5.1.4 ABORT Instruction

The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 170 for more
information.

4.5.1.5 DPACC Instruction

The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 170 for more information.

4.5.1.6 APACC Instruction

The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 170 for more information.

4.5.1.7 IDCODE Instruction

The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 169 for more
information.

4.5.1.8 BYPASS Instruction

The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 169 for
more information.

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4.5.2 Data Registers

The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.

4.5.2.1 IDCODE Data Register

The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3 on page 169. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure
themselves to work correctly with the Cortex-M3 during debug.

Figure 4-3. IDCODE Register Format

31 28 27 12 11 1 0
TDI TDO
Version Part Number Manufacturer ID 1

4.5.2.2 BYPASS Data Register

The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4 on page 169. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.

Figure 4-4. BYPASS Register Format

0
TDI 0 TDO

4.5.2.3 Boundary Scan Data Register

The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 170. Each GPIO
pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with

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the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.

Figure 4-5. Boundary Scan Register Format

TDI I
N
O
U
T
O
E ... I
N
O
U
T
O
E
I
N
I
N
O
U
T
O
E ... I
N
O
U
T
O TDO
E

GPIO PB6 GPIO m RST GPIO m+1 GPIO n

4.5.2.4 APACC Data Register

The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.

4.5.2.5 DPACC Data Register

The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.

4.5.2.6 ABORT Data Register

The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.

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5 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.

5.1 Signal Description

Table 5-1 on page 171 and Table 5-2 on page 171 list the external signals of the System Control
module and describe the function of each. The NMI signal is the alternate function for and functions
as a GPIO after reset. under commit protection and require a special process to be configured as
any alternate function or to subsequently return to the GPIO function, see “Commit
Control” on page 295. The column in the table below titled "Pin Assignment" lists the GPIO pin
placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 309) should be set to choose the NMI function. For more information on configuring
GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286. The remaining signals (with the
word "fixed" in the Pin Assignment column) have a fixed pin assignment and function.

Table 5-1. System Control & Clocks Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
OSC0 48 I Analog Main oscillator crystal input or an external clock reference
input.
OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
RST 64 I TTL System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 5-2. System Control & Clocks Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
OSC0 L11 I Analog Main oscillator crystal input or an external clock reference
input.
OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
RST H11 I TTL System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

5.2 Functional Description

The System Control module provides the following capabilities:

■ Device identification (see “Device Identification” on page 172)

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■ Local control, such as reset (see “Reset Control” on page 172), power (see “Power
Control” on page 176) and clock control (see “Clock Control” on page 177)

■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 182

5.2.1 Device Identification

Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.

5.2.2 Reset Control

This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.

5.2.2.1 CMOD0 and CMOD1 Test-Mode Control Pins

Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.

5.2.2.2 Reset Sources

The controller has five sources of reset:

1. External reset input pin (RST) assertion; see “External RST Pin” on page 173.

2. Power-on reset (POR); see “Power-On Reset (POR)” on page 173.

3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 174.

4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 175.

5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 175.

Table 5-3 provides a summary of results of the various reset operations.

Table 5-3. Reset Sources

Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset?
Power-On Reset Yes Yes Yes
RST Yes Pin Config Only Yes
Brown-Out Reset Yes No Yes
Software System Request Yes No Yes
a
Reset
b
Software Peripheral Reset No No Yes
Watchdog Reset Yes No Yes
a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.

After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
or an external reset is the cause, and then all the other bits in the RESC register are cleared except
for the POR or EXT indicator.

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5.2.2.3 Power-On Reset (POR)

Note: The power-on reset also resets the JTAG controller. An external reset does not.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 173.
The Power-On Reset sequence is as follows:

1. The microcontroller waits for internal POR to go inactive.

2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.

The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 21-6 on page 660.

5.2.2.4 External RST Pin

Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 173.

Figure 5-1. Basic RST Configuration

VDD
Stellaris®
RPU
RST

RPU = 0 to 100 kΩ

The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 158). The external reset
sequence is as follows:

1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 660).

2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.

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To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 174.

Figure 5-2. External Circuitry to Extend Power-On Reset

VDD
Stellaris®
RPU
RST

C1

RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 µF

If the application requires the use of an external reset switch, Figure 5-3 on page 174 shows the
proper circuitry to use.

Figure 5-3. Reset Circuit Controlled by Switch

VDD
Stellaris®
RPU
RST
RS
C1

Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF

The RPU and C1 components define the power-on delay.

The external reset timing is shown in Figure 21-5 on page 660.

5.2.2.5 Brown-Out Reset (BOR)

A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.

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The brown-out reset is equivalent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 21-7 on page 661.

5.2.2.6 Software Reset

Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 182). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:

1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.

2. An internal reset is asserted.

3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.

The software-initiated system reset timing is shown in Figure 21-8 on page 661.

5.2.2.7 Watchdog Timer Reset

The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:

1. The watchdog timer times out for the second time without being serviced.

2. An internal reset is asserted.

3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.

The watchdog reset timing is shown in Figure 21-9 on page 661.

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5.2.3 Power Control

®
The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the controller's internal logic. For power reduction, the LDO regulator provides
software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range
of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of
the VADJ field in the LDO Power Control (LDOPCTL) register.
Figure 5-4 on page 176 shows the power architecture.
Note: On the printed circuit board, use the LDO output as the source of VDD25 input. Do not use
an external regulator to supply the voltage to VDD25. In addition, the LDO requires decoupling
capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 654.
VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA
is the supply for all of the analog circuitry on the device, including the LDO and the clock
circuitry.

Figure 5-4. Power Architecture

VDD25 GND
VDD25 GND
Internal
VDD25 GND
Logic and PLL
VDD25 GND

LDO

Low-noise
LDO

+3.3V
VDDA GNDA
VDDA Analog circuits GNDA

VDD GND
VDD GND
VDD I/O Buffers GND
VDD GND

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5.2.4 Clock Control

System control determines the control of clocks in this part.

5.2.4.1 Fundamental Clock Sources

There are multiple clock sources for use in the device:

■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.

■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 194).

■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.

■ External Real-Time Oscillator. The external real-time oscillator provides a low-frequency,

accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (see “Hibernation Module” on page 238) and
may also provide an accurate source of Deep-Sleep or Hibernate mode power savings.

The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 5-4 on page 177 shows how the various clock sources can be used in a system.

Table 5-4. Clock Source Options

Clock Source Drive PLL? Used as SysClk?
Internal Oscillator (12 MHz) No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x1
Internal Oscillator divide by 4 (3 No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x2
MHz)
Main Oscillator Yes BYPASS = 0, OSCSRC = Yes BYPASS = 1, OSCSRC = 0x0
0x0
Internal 30-kHz Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x3
External Real-Time Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC2 = 0x7

5.2.4.2 Clock Configuration

The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that

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offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:

■ Source of clocks in sleep and deep-sleep modes

■ System clock derived from PLL or other clock source

■ Enabling/disabling of oscillators and PLL

■ Clock divisors

■ Crystal input selection

Figure 5-5 on page 179 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled. The ADC clock signal is
automatically divided down to 16 MHz for proper ADC operation. The PWM clock signal is a
synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV
in RCC).
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.

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Figure 5-5. Main Clock Tree

USEPWMDIV a

PWMDW a

PWM Clock

XTALa
PWRDN b
MOSCDIS a

PLL USESYSDIV a,d

Main OSC ÷2
(400 MHz)

IOSCDIS a
System Clock
Internal
OSC SYSDIV b,d
(12 MHz)
÷4 b,d
BYPASS PWRDN
Internal
OSC
(30 kHz)

Hibernation OSCSRC b,d ADC Clock

Module
(32.768 kHz) ÷ 25

÷ 50 CAN Clock

a. Control provided by RCC register bit/field.

b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.

Note: The figure above shows all features available on all Stellaris® Fury-class devices. Not all peripherals may be
available on this device.

In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 177.

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Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
a
SYSDIV Divisor Frequency Frequency (BYPASS=1) StellarisWare Parameter
(BYPASS=0)
b
0x0 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1
0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2
0x2 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3
0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4
0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5
0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6
0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7
0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8
0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9
0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10
0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11
0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12
0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13
0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14
0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15
0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.

The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-4 on page 177.

Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
a
SYSDIV2 Divisor Frequency Frequency (BYPASS2=1) StellarisWare Parameter
(BYPASS2=0)
b
0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1
0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2
0x02 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3
0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4
0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5
0x05 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6
0x06 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7
0x07 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8
0x08 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9
0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10
... ... ... ... ...

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Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
a
SYSDIV2 Divisor Frequency Frequency (BYPASS2=1) StellarisWare Parameter
(BYPASS2=0)
0x3F /64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.

5.2.4.3 Crystal Configuration for the Main Oscillator (MOSC)

The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 194) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.

5.2.4.4 Main PLL Frequency Configuration

The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 198). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 21-9 on page 657 shows the actual PLL frequency and error for
a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 194)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2
field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7.

5.2.4.5 PLL Modes

The PLL has two modes of operation: Normal and Power-Down

■ Normal: The PLL multiplies the input clock reference and drives the output.

■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.

The modes are programmed using the RCC/RCC2 register fields (see page 194 and page 199).

5.2.4.6 PLL Operation

If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
21-8 on page 657). During the relock time, the affected PLL is not usable as a clock reference.

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PLL is changed by one of the following:

■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.

■ Change in the PLL from Power-Down to Normal mode.

A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
the PLL from being used as a system clock until the TREADY condition is met after one of the two
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.

5.2.5 System Control

For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
There are four levels of operation for the device defined as:

■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.

■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt)
instruction. Any properly configured interrupt event in the system will bring the processor back
into Run mode. See “Power Management” on page 89 for more details.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.

■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep
modes are entered on request from the code. Deep-Sleep mode is entered by first writing the
Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
a WFI instruction. Any properly configured interrupt event in the system will bring the processor
back into Run mode. See “Power Management” on page 89 for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the

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WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register,
up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system
clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling
the clocks that had been stopped during the Deep-Sleep duration.

■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.

Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.

5.3 Initialization and Configuration

The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:

1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source and allows
for the new PLL configuration to be validated before switching the system clock to the PLL.

2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.

3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.

4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.

5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.

5.4 Register Map

Table 5-7 on page 184 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.

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Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.

Table 5-7. System Control Register Map

See
Offset Name Type Reset Description
page

0x000 DID0 RO - Device Identification 0 186

0x004 DID1 RO - Device Identification 1 202

0x008 DC0 RO 0x00FF.007F Device Capabilities 0 204

0x010 DC1 RO 0x0011.33FF Device Capabilities 1 205

0x014 DC2 RO 0x070F.5337 Device Capabilities 2 207

0x018 DC3 RO 0x8FFF.B7FF Device Capabilities 3 209

0x01C DC4 RO 0x0000.00FF Device Capabilities 4 212

0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 188

0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 189

0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 234

0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 235

0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 237

0x050 RIS RO 0x0000.0000 Raw Interrupt Status 190

0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 191

0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 192

0x05C RESC R/W - Reset Cause 193

0x060 RCC R/W 0x078E.3AD1 Run-Mode Clock Configuration 194

0x064 PLLCFG RO - XTAL to PLL Translation 198

0x070 RCC2 R/W 0x0780.2810 Run-Mode Clock Configuration 2 199

0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 213

0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 219

0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 228

0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 215

0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 222

0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 230

0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 217

0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 225

0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 232

0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 201

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5.5 Register Descriptions

All addresses given are relative to the System Control base address of 0x400F.E000.

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Register 1: Device Identification 0 (DID0), offset 0x000

This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register.

Device Identification 0 (DID0)

Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved VER reserved CLASS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAJOR MINOR

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

30:28 VER RO 0x1 DID0 Version

This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:

Value Description
0x1 Second version of the DID0 register format.

27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

23:16 CLASS RO 0x1 Device Class

The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):

Value Description
0x1 Stellaris® Fury-class devices.

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Bit/Field Name Type Reset Description

15:8 MAJOR RO - Major Revision

This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:

Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)

and so on.

7:0 MINOR RO - Minor Revision

This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:

Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.

and so on.

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Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030

This register is responsible for controlling reset conditions after initial power-on reset.

Brown-Out Reset Control (PBORCTL)

Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BORIOR reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORIOR R/W 0 BOR Interrupt or Reset

This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 3: LDO Power Control (LDOPCTL), offset 0x034

The VADJ field in this register adjusts the on-chip output voltage (VOUT).

LDO Power Control (LDOPCTL)

Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VADJ

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:0 VADJ R/W 0x0 LDO Output Voltage

This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.

Value VOUT (V)

0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55

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Register 4: Raw Interrupt Status (RIS), offset 0x050

Central location for system control raw interrupts. These are set and cleared by hardware.

Raw Interrupt Status (RIS)

Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PLLLRIS reserved BORRIS reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status

This bit is set when the PLL TREADY Timer asserts.

5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status

This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 5: Interrupt Mask Control (IMC), offset 0x054

Central location for system control interrupt masks.

Interrupt Mask Control (IMC)

Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PLLLIM reserved BORIM reserved

Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 PLLLIM R/W 0 PLL Lock Interrupt Mask

This bit specifies whether a PLL Lock interrupt is promoted to a controller
interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set;
otherwise, an interrupt is not generated.

5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORIM R/W 0 Brown-Out Reset Interrupt Mask

This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058

On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 190).

Masked Interrupt Status and Clear (MISC)

Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PLLLMIS reserved BORMIS reserved

Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status

This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.

5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 BORMIS R/W1C 0 BOR Masked Interrupt Status

The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 7: Reset Cause (RESC), offset 0x05C

This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when a power- on reset or an external reset is
the cause, in which case, all bits other than POR or EXT in the RESC register are cleared.

Reset Cause (RESC)

Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SW WDT BOR POR EXT

Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 - - - - -

Bit/Field Name Type Reset Description

31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 SW R/W - Software Reset

When set, indicates a software reset is the cause of the reset event.

3 WDT R/W - Watchdog Timer Reset

When set, indicates a watchdog reset is the cause of the reset event.

2 BOR R/W - Brown-Out Reset

When set, indicates a brown-out reset is the cause of the reset event.

1 POR R/W - Power-On Reset

When set, indicates a power-on reset is the cause of the reset event.

0 EXT R/W - External Reset

When set, indicates an external reset (RST assertion) is the cause of
the reset event.

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Register 8: Run-Mode Clock Configuration (RCC), offset 0x060

This register is defined to provide source control and frequency speed.

Run-Mode Clock Configuration (RCC)

Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved

Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS

Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1

Bit/Field Name Type Reset Description

31:28 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

27 ACG R/W 0 Auto Clock Gating

This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.

26:23 SYSDIV R/W 0xF System Clock Divisor

Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-5 on page 180 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 205), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.

22 USESYSDIV R/W 0 Enable System Clock Divider

Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.

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Bit/Field Name Type Reset Description

21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20 USEPWMDIV R/W 0 Enable PWM Clock Divisor

Use the PWM clock divider as the source for the PWM clock.

19:17 PWMDIV R/W 0x7 PWM Unit Clock Divisor

This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.

Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)

16:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13 PWRDN R/W 1 PLL Power Down

This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.

12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11 BYPASS R/W 1 PLL Bypass

Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-5 on page 180 for programming guidelines.

Note: The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.

10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9:6 XTAL R/W 0xB Crystal Value

This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz (see Table
21-9 on page 657 for more information).

Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using

Using the PLL the PLL
0x0 1.000 reserved
0x1 1.8432 reserved
0x2 2.000 reserved
0x3 2.4576 reserved
0x4 3.579545 MHz
0x5 3.6864 MHz
0x6 4 MHz
0x7 4.096 MHz
0x8 4.9152 MHz
0x9 5 MHz
0xA 5.12 MHz
0xB 6 MHz (reset value)
0xC 6.144 MHz
0xD 7.3728 MHz
0xE 8 MHz
0xF 8.192 MHz

5:4 OSCSRC R/W 0x1 Oscillator Source

Selects the input source for the OSC. The values are:

Value Input Source

0x0 MOSC
Main oscillator
0x1 IOSC
Internal oscillator (default)
0x2 IOSC/4
Internal oscillator / 4
0x3 30 kHz
30-KHz internal oscillator

For additional oscillator sources, see the RCC2 register.

3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 IOSCDIS R/W 0 Internal Oscillator Disable

0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.

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Bit/Field Name Type Reset Description

0 MOSCDIS R/W 1 Main Oscillator Disable

0: Main oscillator is enabled .
1: Main oscillator is disabled (default).

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Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064

This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 194).
The PLL frequency is calculated using the PLLCFG field values, as follows:

PLLFreq = OSCFreq * F / (R + 1)

XTAL to PLL Translation (PLLCFG)

Base 0x400F.E000
Offset 0x064
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved F R

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13:5 F RO - PLL F Value

This field specifies the value supplied to the PLL’s F input.

4:0 R RO - PLL R Value

This field specifies the value supplied to the PLL’s R input.

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Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070

This register overrides the RCC equivalent register fields, as shown in Table 5-8, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.

Table 5-8. RCC2 Fields that Override RCC fields

RCC2 Field... Overrides RCC Field
SYSDIV2, bits[28:23] SYSDIV, bits[26:23]
PWRDN2, bit[13] PWRDN, bit[13]
BYPASS2, bit[11] BYPASS, bit[11]
OSCSRC2, bits[6:4] OSCSRC, bits[5:4]

Run-Mode Clock Configuration 2 (RCC2)

Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2810
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USERCC2 reserved SYSDIV2 reserved

Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO

Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved

Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO

Reset 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0

Bit/Field Name Type Reset Description

31 USERCC2 R/W 0 Use RCC2

When set, overrides the RCC register fields.

30:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

28:23 SYSDIV2 R/W 0x0F System Clock Divisor

Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 5-6 on page 180 for programming guidelines.

22:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13 PWRDN2 R/W 1 Power-Down PLL

When set, powers down the PLL.

12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

11 BYPASS2 R/W 1 Bypass PLL

When set, bypasses the PLL for the clock source.
See Table 5-6 on page 180 for programming guidelines.

10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:4 OSCSRC2 R/W 0x1 Oscillator Source

Selects the input source for the OSC. The values are:

Value Description
0x0 MOSC
Main oscillator
0x1 IOSC
Internal oscillator
0x2 IOSC/4
Internal oscillator / 4
0x3 30 kHz
30-kHz internal oscillator
0x4 Reserved
0x5 Reserved
0x6 Reserved
0x7 32 kHz
32.768-kHz external oscillator

3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144

This register provides configuration information for the hardware control of Deep Sleep Mode.

Deep Sleep Clock Configuration (DSLPCLKCFG)

Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved DSDIVORIDE reserved

Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO

Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DSOSCSRC reserved

Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

28:23 DSDIVORIDE R/W 0x0F Divider Field Override

6-bit system divider field to override when Deep-Sleep occurs with PLL
running.

22:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:4 DSOSCSRC R/W 0x0 Clock Source

Specifies the clock source during Deep-Sleep mode.

Value Description
0x0 MOSC
Use main oscillator as source.
0x1 IOSC
Use internal 12-MHz oscillator as source.
0x2 Reserved
0x3 30 kHz
Use 30-kHz internal oscillator as source.
0x4 Reserved
0x5 Reserved
0x6 Reserved
0x7 32 kHz
Use 32.768-kHz external oscillator as source.

3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 12: Device Identification 1 (DID1), offset 0x004

This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.

Device Identification 1 (DID1)

Base 0x400F.E000
Offset 0x004
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VER FAM PARTNO

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PINCOUNT reserved TEMP PKG ROHS QUAL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 - - - - - 1 - -

Bit/Field Name Type Reset Description

31:28 VER RO 0x1 DID1 Version

This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):

Value Description
0x1 Second version of the DID1 register format.

27:24 FAM RO 0x0 Family

This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):

Value Description
0x0 Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.

23:16 PARTNO RO 0xB8 Part Number

This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):

Value Description
0xB8 LM3S1968

15:13 PINCOUNT RO 0x2 Package Pin Count

This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):

Value Description
0x2 100-pin or 108-ball package

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Bit/Field Name Type Reset Description

12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:5 TEMP RO - Temperature Range

This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):

Value Description
0x0 Commercial temperature range (0°C to 70°C)
0x1 Industrial temperature range (-40°C to 85°C)
0x2 Extended temperature range (-40°C to 105°C)

4:3 PKG RO - Package Type

This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):

Value Description
0x0 SOIC package
0x1 LQFP package
0x2 BGA package

2 ROHS RO 1 RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.

1:0 QUAL RO - Qualification Status

This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):

Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified

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Register 13: Device Capabilities 0 (DC0), offset 0x008

This register is predefined by the part and can be used to verify features.

Device Capabilities 0 (DC0)

Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRAMSZ

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FLASHSZ

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 SRAMSZ RO 0x00FF SRAM Size

Indicates the size of the on-chip SRAM memory.

Value Description
0x00FF 64 KB of SRAM

15:0 FLASHSZ RO 0x007F Flash Size

Indicates the size of the on-chip flash memory.

Value Description
0x007F 256 KB of Flash

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Register 14: Device Capabilities 1 (DC1), offset 0x010

This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.

Device Capabilities 1 (DC1)

Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0011.33FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved PWM reserved ADC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MINSYSDIV reserved MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20 PWM RO 1 PWM Module Present

When set, indicates that the PWM module is present.

19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 ADC RO 1 ADC Module Present

When set, indicates that the ADC module is present.

15:12 MINSYSDIV RO 0x3 System Clock Divider

Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.

Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.

11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9:8 MAXADCSPD RO 0x3 Max ADC Speed

Indicates the maximum rate at which the ADC samples data.

Value Description
0x3 1M samples/second

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Bit/Field Name Type Reset Description

7 MPU RO 1 MPU Present

When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the "Cortex-M3 Peripherals" chapter in the
Stellaris Data Sheet for details on the MPU.

6 HIB RO 1 Hibernation Module Present

When set, indicates that the Hibernation module is present.

5 TEMPSNS RO 1 Temp Sensor Present

When set, indicates that the on-chip temperature sensor is present.

4 PLL RO 1 PLL Present

When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.

3 WDT RO 1 Watchdog Timer Present

When set, indicates that a watchdog timer is present.

2 SWO RO 1 SWO Trace Port Present

When set, indicates that the Serial Wire Output (SWO) trace port is
present.

1 SWD RO 1 SWD Present

When set, indicates that the Serial Wire Debugger (SWD) is present.

0 JTAG RO 1 JTAG Present

When set, indicates that the JTAG debugger interface is present.

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Register 15: Device Capabilities 2 (DC2), offset 0x014

This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.

Device Capabilities 2 (DC2)

Base 0x400F.E000
Offset 0x014
Type RO, reset 0x070F.5337
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1

Bit/Field Name Type Reset Description

31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 COMP2 RO 1 Analog Comparator 2 Present

When set, indicates that analog comparator 2 is present.

25 COMP1 RO 1 Analog Comparator 1 Present

When set, indicates that analog comparator 1 is present.

24 COMP0 RO 1 Analog Comparator 0 Present

When set, indicates that analog comparator 0 is present.

23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 TIMER3 RO 1 Timer 3 Present

When set, indicates that General-Purpose Timer module 3 is present.

18 TIMER2 RO 1 Timer 2 Present

When set, indicates that General-Purpose Timer module 2 is present.

17 TIMER1 RO 1 Timer 1 Present

When set, indicates that General-Purpose Timer module 1 is present.

16 TIMER0 RO 1 Timer 0 Present

When set, indicates that General-Purpose Timer module 0 is present.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

14 I2C1 RO 1 I2C Module 1 Present

When set, indicates that I2C module 1 is present.

13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 I2C0 RO 1 I2C Module 0 Present

When set, indicates that I2C module 0 is present.

11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 QEI1 RO 1 QEI1 Present

When set, indicates that QEI module 1 is present.

8 QEI0 RO 1 QEI0 Present

When set, indicates that QEI module 0 is present.

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 SSI1 RO 1 SSI1 Present

When set, indicates that SSI module 1 is present.

4 SSI0 RO 1 SSI0 Present

When set, indicates that SSI module 0 is present.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 UART2 RO 1 UART2 Present

When set, indicates that UART module 2 is present.

1 UART1 RO 1 UART1 Present

When set, indicates that UART module 1 is present.

0 UART0 RO 1 UART0 Present

When set, indicates that UART module 0 is present.

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Register 16: Device Capabilities 3 (DC3), offset 0x018

This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.

Device Capabilities 3 (DC3)

Base 0x400F.E000
Offset 0x018
Type RO, reset 0x8FFF.B7FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

32KHZ reserved CCP3 CCP2 CCP1 CCP0 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWMFAULT reserved C2PLUS C2MINUS reserved C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31 32KHZ RO 1 32KHz Input Clock Available

When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.

30:28 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

27 CCP3 RO 1 CCP3 Pin Present

When set, indicates that Capture/Compare/PWM pin 3 is present.

26 CCP2 RO 1 CCP2 Pin Present

When set, indicates that Capture/Compare/PWM pin 2 is present.

25 CCP1 RO 1 CCP1 Pin Present

When set, indicates that Capture/Compare/PWM pin 1 is present.

24 CCP0 RO 1 CCP0 Pin Present

When set, indicates that Capture/Compare/PWM pin 0 is present.

23 ADC7 RO 1 ADC7 Pin Present

When set, indicates that ADC pin 7 is present.

22 ADC6 RO 1 ADC6 Pin Present

When set, indicates that ADC pin 6 is present.

21 ADC5 RO 1 ADC5 Pin Present

When set, indicates that ADC pin 5 is present.

20 ADC4 RO 1 ADC4 Pin Present

When set, indicates that ADC pin 4 is present.

19 ADC3 RO 1 ADC3 Pin Present

When set, indicates that ADC pin 3 is present.

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Bit/Field Name Type Reset Description

18 ADC2 RO 1 ADC2 Pin Present

When set, indicates that ADC pin 2 is present.

17 ADC1 RO 1 ADC1 Pin Present

When set, indicates that ADC pin 1 is present.

16 ADC0 RO 1 ADC0 Pin Present

When set, indicates that ADC pin 0 is present.

15 PWMFAULT RO 1 PWM Fault Pin Present

When set, indicates that the PWM Fault pin is present.

14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13 C2PLUS RO 1 C2+ Pin Present

When set, indicates that the analog comparator 2 (+) input pin is present.

12 C2MINUS RO 1 C2- Pin Present

When set, indicates that the analog comparator 2 (-) input pin is present.

11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 C1PLUS RO 1 C1+ Pin Present

When set, indicates that the analog comparator 1 (+) input pin is present.

9 C1MINUS RO 1 C1- Pin Present

When set, indicates that the analog comparator 1 (-) input pin is present.

8 C0O RO 1 C0o Pin Present

When set, indicates that the analog comparator 0 output pin is present.

7 C0PLUS RO 1 C0+ Pin Present

When set, indicates that the analog comparator 0 (+) input pin is present.

6 C0MINUS RO 1 C0- Pin Present

When set, indicates that the analog comparator 0 (-) input pin is present.

5 PWM5 RO 1 PWM5 Pin Present

When set, indicates that the PWM pin 5 is present.

4 PWM4 RO 1 PWM4 Pin Present

When set, indicates that the PWM pin 4 is present.

3 PWM3 RO 1 PWM3 Pin Present

When set, indicates that the PWM pin 3 is present.

2 PWM2 RO 1 PWM2 Pin Present

When set, indicates that the PWM pin 2 is present.

1 PWM1 RO 1 PWM1 Pin Present

When set, indicates that the PWM pin 1 is present.

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Bit/Field Name Type Reset Description

0 PWM0 RO 1 PWM0 Pin Present

When set, indicates that the PWM pin 0 is present.

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Register 17: Device Capabilities 4 (DC4), offset 0x01C

This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.

Device Capabilities 4 (DC4)

Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 GPIOH RO 1 GPIO Port H Present

When set, indicates that GPIO Port H is present.

6 GPIOG RO 1 GPIO Port G Present

When set, indicates that GPIO Port G is present.

5 GPIOF RO 1 GPIO Port F Present

When set, indicates that GPIO Port F is present.

4 GPIOE RO 1 GPIO Port E Present

When set, indicates that GPIO Port E is present.

3 GPIOD RO 1 GPIO Port D Present

When set, indicates that GPIO Port D is present.

2 GPIOC RO 1 GPIO Port C Present

When set, indicates that GPIO Port C is present.

1 GPIOB RO 1 GPIO Port B Present

When set, indicates that GPIO Port B is present.

0 GPIOA RO 1 GPIO Port A Present

When set, indicates that GPIO Port A is present.

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Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Run Mode Clock Gating Control Register 0 (RCGC0)

Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved PWM reserved ADC

Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MAXADCSPD reserved HIB reserved WDT reserved

Type RO RO RO RO RO RO R/W R/W RO R/W RO RO R/W RO RO RO

Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20 PWM R/W 0 PWM Clock Gating Control

This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 ADC R/W 0 ADC0 Clock Gating Control

This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9:8 MAXADCSPD R/W 0 ADC Sample Speed

This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:

Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 HIB R/W 1 HIB Clock Gating Control

This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.

5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 WDT R/W 0 WDT Clock Gating Control

This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Sleep Mode Clock Gating Control Register 0 (SCGC0)

Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved PWM reserved ADC

Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MAXADCSPD reserved HIB reserved WDT reserved

Type RO RO RO RO RO RO R/W R/W RO R/W RO RO R/W RO RO RO

Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20 PWM R/W 0 PWM Clock Gating Control

This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 ADC R/W 0 ADC0 Clock Gating Control

This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

9:8 MAXADCSPD R/W 0 ADC Sample Speed

This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:

Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 HIB R/W 1 HIB Clock Gating Control

This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.

5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 WDT R/W 0 WDT Clock Gating Control

This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)

Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved PWM reserved ADC

Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved HIB reserved WDT reserved

Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO

Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20 PWM R/W 0 PWM Clock Gating Control

This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 ADC R/W 0 ADC0 Clock Gating Control

This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 HIB R/W 1 HIB Clock Gating Control

This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.

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Bit/Field Name Type Reset Description

5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 WDT R/W 0 WDT Clock Gating Control

This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.

2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Run Mode Clock Gating Control Register 1 (RCGC1)

Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0

Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0

Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 COMP2 R/W 0 Analog Comparator 2 Clock Gating

This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

25 COMP1 R/W 0 Analog Comparator 1 Clock Gating

This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

24 COMP0 R/W 0 Analog Comparator 0 Clock Gating

This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

19 TIMER3 R/W 0 Timer 3 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

18 TIMER2 R/W 0 Timer 2 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

17 TIMER1 R/W 0 Timer 1 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

16 TIMER0 R/W 0 Timer 0 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 I2C1 R/W 0 I2C1 Clock Gating Control

This bit controls the clock gating for I2C module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 I2C0 R/W 0 I2C0 Clock Gating Control

This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 QEI1 R/W 0 QEI1 Clock Gating Control

This bit controls the clock gating for QEI module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

8 QEI0 R/W 0 QEI0 Clock Gating Control

This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

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Bit/Field Name Type Reset Description

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 SSI1 R/W 0 SSI1 Clock Gating Control

This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

4 SSI0 R/W 0 SSI0 Clock Gating Control

This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 UART2 R/W 0 UART2 Clock Gating Control

This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

1 UART1 R/W 0 UART1 Clock Gating Control

This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

0 UART0 R/W 0 UART0 Clock Gating Control

This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

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Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Sleep Mode Clock Gating Control Register 1 (SCGC1)

Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0

Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0

Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 COMP2 R/W 0 Analog Comparator 2 Clock Gating

This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

25 COMP1 R/W 0 Analog Comparator 1 Clock Gating

This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

24 COMP0 R/W 0 Analog Comparator 0 Clock Gating

This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

19 TIMER3 R/W 0 Timer 3 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

18 TIMER2 R/W 0 Timer 2 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

17 TIMER1 R/W 0 Timer 1 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

16 TIMER0 R/W 0 Timer 0 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 I2C1 R/W 0 I2C1 Clock Gating Control

This bit controls the clock gating for I2C module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 I2C0 R/W 0 I2C0 Clock Gating Control

This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 QEI1 R/W 0 QEI1 Clock Gating Control

This bit controls the clock gating for QEI module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

8 QEI0 R/W 0 QEI0 Clock Gating Control

This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

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Bit/Field Name Type Reset Description

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 SSI1 R/W 0 SSI1 Clock Gating Control

This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

4 SSI0 R/W 0 SSI0 Clock Gating Control

This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 UART2 R/W 0 UART2 Clock Gating Control

This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

1 UART1 R/W 0 UART1 Clock Gating Control

This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

0 UART0 R/W 0 UART0 Clock Gating Control

This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

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Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)

Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0

Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0

Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 COMP2 R/W 0 Analog Comparator 2 Clock Gating

This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

25 COMP1 R/W 0 Analog Comparator 1 Clock Gating

This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

24 COMP0 R/W 0 Analog Comparator 0 Clock Gating

This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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System Control

Bit/Field Name Type Reset Description

19 TIMER3 R/W 0 Timer 3 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

18 TIMER2 R/W 0 Timer 2 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

17 TIMER1 R/W 0 Timer 1 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

16 TIMER0 R/W 0 Timer 0 Clock Gating Control

This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 I2C1 R/W 0 I2C1 Clock Gating Control

This bit controls the clock gating for I2C module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 I2C0 R/W 0 I2C0 Clock Gating Control

This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 QEI1 R/W 0 QEI1 Clock Gating Control

This bit controls the clock gating for QEI module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

8 QEI0 R/W 0 QEI0 Clock Gating Control

This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

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Bit/Field Name Type Reset Description

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 SSI1 R/W 0 SSI1 Clock Gating Control

This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

4 SSI0 R/W 0 SSI0 Clock Gating Control

This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 UART2 R/W 0 UART2 Clock Gating Control

This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

1 UART1 R/W 0 UART1 Clock Gating Control

This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

0 UART0 R/W 0 UART0 Clock Gating Control

This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.

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 System Control

Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Run Mode Clock Gating Control Register 2 (RCGC2)

Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 GPIOH R/W 0 Port H Clock Gating Control

This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

6 GPIOG R/W 0 Port G Clock Gating Control

This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

5 GPIOF R/W 0 Port F Clock Gating Control

This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

4 GPIOE R/W 0 Port E Clock Gating Control

This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

3 GPIOD R/W 0 Port D Clock Gating Control

This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

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Bit/Field Name Type Reset Description

2 GPIOC R/W 0 Port C Clock Gating Control

This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

1 GPIOB R/W 0 Port B Clock Gating Control

This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

0 GPIOA R/W 0 Port A Clock Gating Control

This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

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 System Control

Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Sleep Mode Clock Gating Control Register 2 (SCGC2)

Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 GPIOH R/W 0 Port H Clock Gating Control

This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

6 GPIOG R/W 0 Port G Clock Gating Control

This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

5 GPIOF R/W 0 Port F Clock Gating Control

This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

4 GPIOE R/W 0 Port E Clock Gating Control

This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

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Bit/Field Name Type Reset Description

3 GPIOD R/W 0 Port D Clock Gating Control

This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

2 GPIOC R/W 0 Port C Clock Gating Control

This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

1 GPIOB R/W 0 Port B Clock Gating Control

This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

0 GPIOA R/W 0 Port A Clock Gating Control

This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

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 System Control

Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.

Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)

Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 GPIOH R/W 0 Port H Clock Gating Control

This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

6 GPIOG R/W 0 Port G Clock Gating Control

This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

5 GPIOF R/W 0 Port F Clock Gating Control

This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

4 GPIOE R/W 0 Port E Clock Gating Control

This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

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Bit/Field Name Type Reset Description

3 GPIOD R/W 0 Port D Clock Gating Control

This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

2 GPIOC R/W 0 Port C Clock Gating Control

This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

1 GPIOB R/W 0 Port B Clock Gating Control

This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

0 GPIOA R/W 0 Port A Clock Gating Control

This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.

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 System Control

Register 27: Software Reset Control 0 (SRCR0), offset 0x040

Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.

Software Reset Control 0 (SRCR0)

Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved PWM reserved ADC

Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved HIB reserved WDT reserved

Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

20 PWM R/W 0 PWM Reset Control

Reset control for PWM module.

19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 ADC R/W 0 ADC0 Reset Control

Reset control for SAR ADC module 0.

15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 HIB R/W 0 HIB Reset Control

Reset control for the Hibernation module.

5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 WDT R/W 0 WDT Reset Control

Reset control for Watchdog unit.

2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 28: Software Reset Control 1 (SRCR1), offset 0x044

Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.

Software Reset Control 1 (SRCR1)

Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0

Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0

Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26 COMP2 R/W 0 Analog Comp 2 Reset Control

Reset control for analog comparator 2.

25 COMP1 R/W 0 Analog Comp 1 Reset Control

Reset control for analog comparator 1.

24 COMP0 R/W 0 Analog Comp 0 Reset Control

Reset control for analog comparator 0.

23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

19 TIMER3 R/W 0 Timer 3 Reset Control

Reset control for General-Purpose Timer module 3.

18 TIMER2 R/W 0 Timer 2 Reset Control

Reset control for General-Purpose Timer module 2.

17 TIMER1 R/W 0 Timer 1 Reset Control

Reset control for General-Purpose Timer module 1.

16 TIMER0 R/W 0 Timer 0 Reset Control

Reset control for General-Purpose Timer module 0.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 I2C1 R/W 0 I2C1 Reset Control

Reset control for I2C unit 1.

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Bit/Field Name Type Reset Description

13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 I2C0 R/W 0 I2C0 Reset Control

Reset control for I2C unit 0.

11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 QEI1 R/W 0 QEI1 Reset Control

Reset control for QEI unit 1.

8 QEI0 R/W 0 QEI0 Reset Control

Reset control for QEI unit 0.

7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 SSI1 R/W 0 SSI1 Reset Control

Reset control for SSI unit 1.

4 SSI0 R/W 0 SSI0 Reset Control

Reset control for SSI unit 0.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 UART2 R/W 0 UART2 Reset Control

Reset control for UART unit 2.

1 UART1 R/W 0 UART1 Reset Control

Reset control for UART unit 1.

0 UART0 R/W 0 UART0 Reset Control

Reset control for UART unit 0.

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Register 29: Software Reset Control 2 (SRCR2), offset 0x048

Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.

Software Reset Control 2 (SRCR2)

Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 GPIOH R/W 0 Port H Reset Control

Reset control for GPIO Port H.

6 GPIOG R/W 0 Port G Reset Control

Reset control for GPIO Port G.

5 GPIOF R/W 0 Port F Reset Control

Reset control for GPIO Port F.

4 GPIOE R/W 0 Port E Reset Control

Reset control for GPIO Port E.

3 GPIOD R/W 0 Port D Reset Control

Reset control for GPIO Port D.

2 GPIOC R/W 0 Port C Reset Control

Reset control for GPIO Port C.

1 GPIOB R/W 0 Port B Reset Control

Reset control for GPIO Port B.

0 GPIOA R/W 0 Port A Reset Control

Reset control for GPIO Port A.

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6 Hibernation Module
The Hibernation Module manages removal and restoration of power to provide a means for reducing
power consumption. When the processor and peripherals are idle, power can be completely removed
with only the Hibernation module remaining powered. Power can be restored based on an external
signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can
be independently supplied from a battery or an auxiliary power supply.
The Hibernation module has the following features:

■ System power control using discrete external regulator

■ Dedicated pin for waking from an external signal

■ Low-battery detection, signaling, and interrupt generation

■ 32-bit real-time clock (RTC)

■ Two 32-bit RTC match registers for timed wake-up and interrupt generation

■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal

■ RTC predivider trim for making fine adjustments to the clock rate

■ 64 32-bit words of non-volatile memory

■ Programmable interrupts for RTC match, external wake, and low battery events

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6.1 Block Diagram

Figure 6-1. Hibernation Module Block Diagram

HIBCTL.CLK32EN
32.768 kHz
XOSC0 Pre-Divider
4.194304 MHz
Interrupts
XOSC1 /128 HIBRTCT HIBIM
HIBCTL.CLKSEL HIBRIS Interrupts
HIBMIS to CPU
HIBIC
RTC
Non-Volatile HIBRTCC
MATCH0/1
Memory HIBRTCLD
64 words HIBRTCM0
HIBRTCM1
HIBDATA

WAKE
LOWBAT

VDD Low Battery Power

Sequence HIB
VBAT Detect
Logic

HIBCTL.LOWBATEN HIBCTL.PWRCUT
HIBCTL.RTCWEN
HIBCTL.PINWEN
HIBCTL.VABORT

6.2 Signal Description

Table 6-1 on page 239 and Table 6-2 on page 240 list the external signals of the Hibernation module
and describe the function of each. These signals have dedicated functions and are not alternate
functions for any GPIO signals.

Table 6-1. Hibernate Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
HIB 51 O OD An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
VBAT 55 - Power Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
WAKE 50 I TTL An external input that brings the processor out of Hibernate
mode when asserted.
XOSC0 52 I Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

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Table 6-2. Hibernate Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
HIB M12 O OD An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
VBAT L12 - Power Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
WAKE M10 I TTL An external input that brings the processor out of Hibernate
mode when asserted.
XOSC0 K11 I Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

6.3 Functional Description

The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage
source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate
voltage source. The Hibernation module also has a separate clock source to maintain a real-time
clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on
the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain
value. The Hibernation module can also detect when the battery voltage is low, and optionally
prevent hibernation when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR).

6.3.1 Register Access Timing

Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
restriction on timing for back-to-back reads from the Hibernation module. The following registers
are subject to this timing restriction:

■ Hibernation RTC Counter (HIBRTCC)

■ Hibernation RTC Match 0 (HIBRTCM0)

■ Hibernation RTC Match 1 (HIBRTCM1)

■ Hibernation RTC Load (HIBRTCLD)

■ Hibernation RTC Trim (HIBRTCT)

■ Hibernation Data (HIBDATA)

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6.3.2 Clock Source

The Hibernation module must be clocked by an external source, even if the RTC feature is not used.
An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can
be connected to the XOSC0 pin. See Figure 6-2 on page 241 and Figure 6-3 on page 242. Note that
these diagrams only show the connection to the Hibernation pins and not to the full system. See
“Hibernation Module” on page 661 for specific values.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128,
resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must
leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the
Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator
is used for the clock source, no delay is needed.

Figure 6-2. Clock Source Using Crystal

Regulator Stellaris Microcontroller

or Switch
Input
IN OUT VDD
Voltage
EN

XOSC0

X1 RL
XOSC1

C1 C2

HIB

WAKE VBAT
RPU Open drain 3V
GND
external wake Battery
up circuit

Note: X1 = Crystal frequency is fXOSC_XTAL.

C1,2 = Capacitor value derived from crystal vendor load capacitance specifications.

RL = Load resistor is RXOSC_LOAD.

RPU = Pull-up resistor (1 M½).

See “Hibernation Module” on page 661 for specific parameter values.

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Figure 6-3. Clock Source Using Dedicated Oscillator

Regulator Stellaris Microcontroller

or Switch
Input
IN OUT VDD
Voltage
EN
Clock
Source XOSC0
(fEXT_OSC)

N.C. XOSC1

HIB

WAKE VBAT
RPU Open drain 3V
GND
external wake Battery
up circuit

Note: RPU = Pull-up resistor (1 M½).

6.3.3 Battery Management

The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage drops below
VLOWBAT. When this happens, an interrupt can be generated. The module can also be configured
so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery
voltage is not measured while in Hibernate mode.

Important: System level factors may affect the accuracy of the low battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.

Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD is
available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 244).

6.3.4 Real-Time Clock

The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 241). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF,
and is used for one second out of every 64 seconds to divide the input clock. This allows the software
to make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.

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The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 244). As long as the RTC is enabled and a valid VBAT is present, the
RTC continues counting, regardless of whether VDD is present or if the part is in hibernation.

6.3.5 Battery-Backed Memory

The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The battery-backed memory can be accessed through the HIBDATA registers.

6.3.6 Power Control

Important: The Hibernation Module requires special system implementation considerations when
using HIB to control power, as it is intended to power-down all other sections of its host
device. All system signals and power supplies that connect to the chip must be driven
to 0 VDC or powered down with the same regulator controlled by HIB. See “Hibernation
Module” on page 661 for more details.

The Hibernation module controls power to the microcontroller through the use of the HIB pin. This
pin is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V
and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the
external regulator is turned off and no longer powers the system. The Hibernation module remains
powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake
event. Power to the device is restored by deasserting the HIB signal, which causes the external
regulator to turn power back on to the chip.

6.3.7 Initiating Hibernate

Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register.
Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or
by using an RTC match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. Software
can detect that the power-on was due to a wake from hibernation by examining the raw interrupt
status register (see “Interrupts and Status” on page 244) and by looking for state data in the
battery-backed memory (see “Battery-Backed Memory” on page 243).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.

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6.3.8 Interrupts and Status

The Hibernation module can generate interrupts when the following conditions occur:

■ Assertion of WAKE pin

■ RTC match

■ Low battery detected

All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.

6.4 Initialization and Configuration

The Hibernation module can be set in several different configurations. The following sections show
the recommended programming sequence for various scenarios. The examples below assume that
a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set
to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the
Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the system, software
must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 240). The registers that require a delay are listed in a note in “Register
Map” on page 245 as well as in each register description.

6.4.1 Initialization
The Hibernation module clock source must be enabled first, even if the RTC feature is not used. If
a 4.194304-MHz crystal is used, perform the following steps:

1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.

2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.

If a 32.678-kHz oscillator is used, then perform the following steps:

1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.

2. No delay is necessary.

The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.

6.4.2 RTC Match Functionality (No Hibernation)

Use the following steps to implement the RTC match functionality of the Hibernation module:

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1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.

2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.

4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.

6.4.3 RTC Match/Wake-Up from Hibernation

Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:

1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.

2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.

4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.

6.4.4 External Wake-Up from Hibernation

Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:

1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.

2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.

6.4.5 RTC/External Wake-Up from Hibernation

1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.

2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.

4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.

6.5 Register Map

Table 6-3 on page 246 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled
before the registers can be programmed (see page 213). There must be a delay of 3 system clocks
after the Hibernation module clock is enabled before any Hibernation module registers are accessed.

Important: The Hibernation module registers are reset under two conditions:

1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are
both cleared.

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2. A cold POR, when both the VDD and VBAT supplies are removed.

Any other reset condition is ignored by the Hibernation module.

Table 6-3. Hibernation Module Register Map

See
Offset Name Type Reset Description
page

0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 247

0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 248

0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 249

0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 250

0x010 HIBCTL R/W 0x8000.0000 Hibernation Control 251

0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 253

0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 254

0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 255

0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 256

0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 257

0x030-
HIBDATA R/W - Hibernation Data 258
0x12C

6.6 Register Descriptions

The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.

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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000

This register is the current 32-bit value of the RTC counter.

Hibernation RTC Counter (HIBRTCC)

Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 RTCC RO 0x0000.0000 RTC Counter

A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.

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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004

This register is the 32-bit match 0 register for the RTC counter.

Hibernation RTC Match 0 (HIBRTCM0)

Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCM0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCM0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 RTCM0 R/W 0xFFFF.FFFF RTC Match 0

A write loads the value into the RTC match register.
A read returns the current match value.

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Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008

This register is the 32-bit match 1 register for the RTC counter.

Hibernation RTC Match 1 (HIBRTCM1)

Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCM1

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCM1

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 RTCM1 R/W 0xFFFF.FFFF RTC Match 1

A write loads the value into the RTC match register.
A read returns the current match value.

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Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C

This register is the 32-bit value loaded into the RTC counter.

Hibernation RTC Load (HIBRTCLD)

Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCLD

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTCLD

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 RTCLD R/W 0xFFFF.FFFF RTC Load

A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.

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Register 5: Hibernation Control (HIBCTL), offset 0x010

This register is the control register for the Hibernation module.

Hibernation Control (HIBCTL)

Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x8000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 VABORT R/W 0 Power Cut Abort Enable

Value Description
0 Power cut occurs during a low-battery alert.
1 Power cut is aborted.

6 CLK32EN R/W 0 Clocking Enable

Value Description
0 Disabled
1 Enabled

This bit must be enabled to use the Hibernation module. If a crystal is

used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.

5 LOWBATEN R/W 0 Low Battery Monitoring Enable

Value Description
0 Disabled
1 Enabled

When set, low battery voltage detection is enabled (VBAT < VLOWBAT).

4 PINWEN R/W 0 External WAKE Pin Enable

Value Description
0 Disabled
1 Enabled

When set, an external event on the WAKE pin will re-power the device.

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Bit/Field Name Type Reset Description

3 RTCWEN R/W 0 RTC Wake-up Enable

Value Description
0 Disabled
1 Enabled

When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.

2 CLKSEL R/W 0 Hibernation Module Clock Select

Value Description
0 Use Divide by 128 output. Use this value for a
4.194304-MHz crystal.
1 Use raw output. Use this value for a 32.768-kHz
oscillator.

1 HIBREQ R/W 0 Hibernation Request

Value Description
0 Disabled
1 Hibernation initiated

After a wake-up event, this bit is cleared by hardware.

0 RTCEN R/W 0 RTC Timer Enable

Value Description
0 Disabled
1 Enabled

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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014

This register is the interrupt mask register for the Hibernation module interrupt sources.

Hibernation Interrupt Mask (HIBIM)

Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved EXTW LOWBAT RTCALT1 RTCALT0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 EXTW R/W 0 External Wake-Up Interrupt Mask

Value Description
0 Masked
1 Unmasked

2 LOWBAT R/W 0 Low Battery Voltage Interrupt Mask

Value Description
0 Masked
1 Unmasked

1 RTCALT1 R/W 0 RTC Alert1 Interrupt Mask

Value Description
0 Masked
1 Unmasked

0 RTCALT0 R/W 0 RTC Alert0 Interrupt Mask

Value Description
0 Masked
1 Unmasked

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Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018

This register is the raw interrupt status for the Hibernation module interrupt sources.

Hibernation Raw Interrupt Status (HIBRIS)

Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved EXTW LOWBAT RTCALT1 RTCALT0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 EXTW RO 0 External Wake-Up Raw Interrupt Status

2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status

1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status

0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status

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Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C

This register is the masked interrupt status for the Hibernation module interrupt sources.

Hibernation Masked Interrupt Status (HIBMIS)

Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved EXTW LOWBAT RTCALT1 RTCALT0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 EXTW RO 0 External Wake-Up Masked Interrupt Status

2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status

1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status

0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status

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Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020

This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.

Hibernation Interrupt Clear (HIBIC)

Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved EXTW LOWBAT RTCALT1 RTCALT0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 EXTW R/W1C 0 External Wake-Up Masked Interrupt Clear

Reads return an indeterminate value.

2 LOWBAT R/W1C 0 Low Battery Voltage Masked Interrupt Clear

Reads return an indeterminate value.

1 RTCALT1 R/W1C 0 RTC Alert1 Masked Interrupt Clear

Reads return an indeterminate value.

0 RTCALT0 R/W1C 0 RTC Alert0 Masked Interrupt Clear

Reads return an indeterminate value.

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Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024

This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.

Hibernation RTC Trim (HIBRTCT)

Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRIM

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 TRIM R/W 0x7FFF RTC Trim Value

This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.

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Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C

This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store state information and does not lose power during a power-cut
operation as long as a battery is present.

Hibernation Data (HIBDATA)

Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTD

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTD

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 RTD R/W - Hibernation Module NV Registers[63:0]

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7 Internal Memory
The LM3S1968 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.

7.1 Block Diagram

Figure 7-1 on page 259 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.

Figure 7-1. Flash Block Diagram

Icode Bus Flash Control

Cortex-M3 FMA
Dcode Bus FMD
FMC Flash Array
FCRIS
FCIM
System

FCMISC
Bus

Flash Protection
Bridge
FMPREn
FMPPEn

Flash Timing

USECRL

User Registers
USER_DBG
SRAM Array
USER_REG0
USER_REG1

7.2 Functional Description

This section describes the functionality of the SRAM and Flash memories.

7.2.1 SRAM Memory

®
The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:

bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)

For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:

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0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C

With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 75.

7.2.2 Flash Memory

The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 667 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.

7.2.2.1 Flash Memory Timing

The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.

7.2.2.2 Flash Memory Protection

The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.

■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.

■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.

The policies may be combined as shown in Table 7-1 on page 260.

Table 7-1. Flash Protection Policy Combinations

FMPPEn FMPREn Protection
0 0 Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.

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Table 7-1. Flash Protection Policy Combinations (continued)

FMPPEn FMPREn Protection
1 0 The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
0 1 Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
1 1 No protection. The block may be written, erased, executed or read.

A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register. Details on programming these bits
are discussed in “Nonvolatile Register Programming” on page 263.

7.2.2.3 Execute-Only Protection

Execute-only protection prevents both modification and visibility to a protected flash block. This
mode is intended to be used in situations where a device requires debug capability, yet portions of
the application space must be protected from external access. An example of this is a company
who wishes to sell Stellaris devices with their proprietary software pre-programmed, yet allow the
end user to add custom code to an unprotected region of the flash (such as a motor control module
with a customizable motor configuration section in flash).
Literal data introduces a complication to the protection mechanism. When C code is compiled and
linked, literal data (constants, and so on) is typically placed in the text section, between functions,
by the compiler. The literal data is accessed at run time through the use of the LDR instruction,
which loads the data from memory using a PC-relative memory address. The execution of the LDR
instruction generates a read transaction across the Cortex-M3's DCode bus, which is subject to the
execute-only protection mechanism. If the accessed block is marked as execute only, the transaction
is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting
correct execution. Therefore, using execute-only protection requires that literal data be handled
differently. There are three ways to address this:

1. Use a compiler that allows literal data to be collected into a separate section that is put into one
or more read-enabled flash blocks. Note that the LDR instruction may use a PC-relative
address–-in which case the literal pool cannot be located outside the span of the offset–-or the
software may reserve a register to point to the base address of the literal pool and the LDR
offset is relative to the beginning of the pool.

2. Use a compiler that generates literal data from arithmetic instruction immediate data and
subsequent computation.

3. Use method 1 or 2, but in assembly language, if the compiler does not support either method.

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7.2.2.4 Read-Only Protection

Read-only protection prevents the contents of the flash block from being re-programmed, while still
allowing the content to be read by processor or the debug interface. Note that if a FMPREn bit is
cleared, all read accesses to the Flash memory block are disallowed, including any data accesses.
Care must be taken not to store required data in a Flash memory block that has the associated
FMPREn bit cleared.
The read-only mode does not prevent read access to the stored program, but it does provide
protection against accidental (or malicious) erasure or programming. Read-only is especially useful
for utilities like the boot loader when the debug interface is permanently disabled. In such
combinations, the boot loader, which provides access control to the Flash memory, is protected
from being erased or modified.

7.2.2.5 Permanently Disabling Debug

For extremely sensitive applications, the debug interface to the processor and peripherals can be
permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces.
With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as
boundary scan operations), but access to the processor and peripherals is blocked.
The DBG0 and DBG1 bits of the User Debug (USER_DBG) register control whether the debug
interface is turned on or off.
The debug interface should not be permanently disabled without providing some mechanism–-such
as the boot loader–-to provide customer-installable updates or bug fixes. Disabling the debug
interface is permanent and cannot be reversed.

7.2.2.6 Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:

■ Programming Interrupt - signals when a program or erase action is complete.

■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.

The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 271) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 270).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 272).

7.3 Flash Memory Initialization and Configuration

7.3.1 Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.

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7.3.1.1 To program a 32-bit word

1. Write source data to the FMD register.

2. Write the target address to the FMA register.

3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.

4. Poll the FMC register until the WRITE bit is cleared.

7.3.1.2 To perform an erase of a 1-KB page

1. Write the page address to the FMA register.

2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.

3. Poll the FMC register until the ERASE bit is cleared.

7.3.1.3 To perform a mass erase of the flash

1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.

2. Poll the FMC register until the MERASE bit is cleared.

7.3.2 Nonvolatile Register Programming

Note: The USER_DBG register requires a POR before the committed changes take effect.
This section discusses how to update registers that are resident within the Flash memory itself.
These registers exist in a separate space from the main Flash memory array and are not affected
by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0
with a write operation. Prior to being committed, the register contents are unaffected by any reset
condition except power-on reset, which returns the register contents to the original value. By
committing the register values using the COMT bit in the FMC register, the register contents become
nonvolatile and are therefore retained following power cycling. Once the register contents are
committed, the contents are permanent, and they cannot be restored to their factory default values.
With the exception of the USER_DBG register, the settings in these registers can be tested before
committing them to Flash memory. For the USER_DBG register, the data to be written is loaded
into the FMD register before it is committed. The FMD register is read only and does not allow the
USER_DBG operation to be tried before committing it to nonvolatile memory.

Important: The Flash memory registers can only have bits changed from 1 to 0 by user programming
and can only be committed once. After being committed, these registers cannot be
restored to their factory default values.

In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers

each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be
changed from 1 to 0. These five registers can only be committed once whereas the Flash memory
protection registers may be committed multiple times. Table 7-2 on page 264 provides the FMA
address required for commitment of each of the registers and the source of the data to be written
when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user
may poll the FMC register to wait for the commit operation to complete.

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Table 7-2. User-Programmable Flash Memory Resident Registers

Register to be Committed FMA Value Data Source
FMPRE0 0x0000.0000 FMPRE0
FMPRE1 0x0000.0002 FMPRE1
FMPRE2 0x0000.0004 FMPRE2
FMPRE3 0x0000.0006 FMPRE3
FMPPE0 0x0000.0001 FMPPE0
FMPPE1 0x0000.0003 FMPPE1
FMPPE2 0x0000.0005 FMPPE2
FMPPE3 0x0000.0007 FMPPE3
USER_REG0 0x8000.0000 USER_REG0
USER_REG1 0x8000.0001 USER_REG1
USER_REG2 0x8000.0002 USER_REG2
USER_REG3 0x8000.0003 USER_REG3
USER_DBG 0x7510.0000 FMD

7.4 Register Map

Table 7-3 on page 264 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register
offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory
protection register offsets are relative to the System Control base address of 0x400F.E000.

Table 7-3. Flash Register Map

See
Offset Name Type Reset Description
page

Flash Memory Control Registers (Flash Control Offset)

0x000 FMA R/W 0x0000.0000 Flash Memory Address 266

0x004 FMD R/W 0x0000.0000 Flash Memory Data 267

0x008 FMC R/W 0x0000.0000 Flash Memory Control 268

0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 270

0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 271

0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 272

Flash Memory Protection Registers (System Control Offset)

0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 275

0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 275

0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 276

0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 276

0x140 USECRL R/W 0x31 USec Reload 274

0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 277

0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 278

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Table 7-3. Flash Register Map (continued)

See
Offset Name Type Reset Description
page

0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 279

0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 280

0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 281

0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 282

0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 283

0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 284

0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 285

7.5 Flash Register Descriptions (Flash Control Offset)

This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.

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Register 1: Flash Memory Address (FMA), offset 0x000

During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.

Flash Memory Address (FMA)

Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved OFFSET

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:18 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

17:0 OFFSET R/W 0x0 Address Offset

Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register
Programming” on page 263 for details on values for this field).

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Register 2: Flash Memory Data (FMD), offset 0x004

This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.

Flash Memory Data (FMD)

Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 DATA R/W 0x0 Data Value

Data value for write operation.

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Register 3: Flash Memory Control (FMC), offset 0x008

When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 266). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 267) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.

Flash Memory Control (FMC)

Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WRKEY

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved COMT MERASE ERASE WRITE

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 WRKEY WO 0x0 Flash Write Key

This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.

15:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 COMT R/W 0 Commit Register Value

Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.

2 MERASE R/W 0 Mass Erase Flash Memory

If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.

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Bit/Field Name Type Reset Description

1 ERASE R/W 0 Erase a Page of Flash Memory

If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.

0 WRITE R/W 0 Write a Word into Flash Memory

If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 µs.

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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C

This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.

Flash Controller Raw Interrupt Status (FCRIS)

Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PRIS ARIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 PRIS RO 0 Programming Raw Interrupt Status

This bit provides status on programming cycles which are write or erase
actions generated through the FMC register bits (see page 268).

Value Description
1 The programming cycle has completed.
0 The programming cycle has not completed.

This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.

0 ARIS RO 0 Access Raw Interrupt Status

Value Description
1 A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
0 No access has tried to improperly program or erase the Flash
memory.

This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.

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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010

This register controls whether the flash controller generates interrupts to the controller.

Flash Controller Interrupt Mask (FCIM)

Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PMASK AMASK

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 PMASK R/W 0 Programming Interrupt Mask

This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.

Value Description
1 An interrupt is sent to the interrupt controller when the PRIS bit
is set.
0 The PRIS interrupt is suppressed and not sent to the interrupt
controller.

0 AMASK R/W 0 Access Interrupt Mask

This bit controls the reporting of the access raw interrupt status to the
interrupt controller.

Value Description
1 An interrupt is sent to the interrupt controller when the ARIS bit
is set.
0 The ARIS interrupt is suppressed and not sent to the interrupt
controller.

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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),

offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.

Flash Controller Masked Interrupt Status and Clear (FCMISC)

Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PMISC AMISC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 PMISC R/W1C 0 Programming Masked Interrupt Status and Clear

Value Description
1 When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 270).
0 When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.

0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear

Value Description
1 When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 270).
0 When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.

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7.6 Flash Register Descriptions (System Control Offset)

The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.

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Register 7: USec Reload (USECRL), offset 0x140

Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.

USec Reload (USECRL)

Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved USEC

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 USEC R/W 0x31 Microsecond Reload Value

MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x31 (50 MHz) whenever the flash is being erased or programmed.

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Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130

and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.

Flash Memory Protection Read Enable 0 (FMPRE0)

Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 READ_ENABLE R/W 0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.

Value Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.

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Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset

0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.

Flash Memory Protection Program Enable 0 (FMPPE0)

Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 PROG_ENABLE R/W 0xFFFFFFFF Flash Programming Enable

Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.

Value Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.

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Register 10: User Debug (USER_DBG), offset 0x1D0

Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to
0 disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and
is controlled through hardware to ensure that the register is only committed once. Prior to being
committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on
reset; any other type of reset does not affect this register. Once committed, this register cannot be
restored to the factory default value.

User Debug (USER_DBG)

Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NW DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA DBG1 DBG0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

Bit/Field Name Type Reset Description

31 NW R/W 1 User Debug Not Written

When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.

30:2 DATA R/W 0x1FFFFFFF User Data

Contains the user data value. This field is initialized to all 1s and can
only be committed once.

1 DBG1 R/W 1 Debug Control 1

The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.

0 DBG0 R/W 0 Debug Control 0

The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.

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Register 11: User Register 0 (USER_REG0), offset 0x1E0

Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.

User Register 0 (USER_REG0)

Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NW DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31 NW R/W 1 Not Written

When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.

30:0 DATA R/W 0x7FFFFFFF User Data

Contains the user data value. This field is initialized to all 1s and can
only be committed once.

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Register 12: User Register 1 (USER_REG1), offset 0x1E4

Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.

User Register 1 (USER_REG1)

Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NW DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31 NW R/W 1 Not Written

When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.

30:0 DATA R/W 0x7FFFFFFF User Data

Contains the user data value. This field is initialized to all 1s and can
only be committed once.

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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.

Flash Memory Protection Read Enable 1 (FMPRE1)

Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 READ_ENABLE R/W 0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.

Value Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.

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Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory
Protection" section.

Flash Memory Protection Read Enable 2 (FMPRE2)

Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 READ_ENABLE R/W 0xFFFFFFFF Flash Read Enable

Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.

Value Description
0xFFFFFFFF Enables 256 KB of flash.

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 Internal Memory

Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.

Flash Memory Protection Read Enable 3 (FMPRE3)

Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

READ_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 READ_ENABLE R/W 0xFFFFFFFF Flash Read Enable

Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.

Value Description
0xFFFFFFFF Enables 256 KB of flash.

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Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset

0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.

Flash Memory Protection Program Enable 1 (FMPPE1)

Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 PROG_ENABLE R/W 0xFFFFFFFF Flash Programming Enable

Value Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.

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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset

0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.

Flash Memory Protection Program Enable 2 (FMPPE2)

Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 PROG_ENABLE R/W 0xFFFFFFFF Flash Programming Enable

Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.

Value Description
0xFFFFFFFF Enables 256 KB of flash.

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Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset

0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.

Flash Memory Protection Program Enable 3 (FMPPE3)

Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PROG_ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 PROG_ENABLE R/W 0xFFFFFFFF Flash Programming Enable

Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.

Value Description
0xFFFFFFFF Enables 256 KB of flash.

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8 General-Purpose Input/Outputs (GPIOs)

The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H). The GPIO module supports
5-52 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:

■ 5-52 GPIOs, depending on configuration

■ 5-V-tolerant in input configuration

■ Fast toggle capable of a change every two clock cycles

■ Programmable control for GPIO interrupts

– Interrupt generation masking

– Edge-triggered on rising, falling, or both

– Level-sensitive on High or Low values

■ Bit masking in both read and write operations through address lines

■ Can initiate an ADC sample sequence

■ Pins configured as digital inputs are Schmitt-triggered.

■ Programmable control for GPIO pad configuration

– Weak pull-up or pull-down resistors

– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications

– Slew rate control for the 8-mA drive

– Open drain enables

– Digital input enables

8.1 Signal Description

GPIO signals have alternate hardware functions. Table 8-4 on page 289 and Table 8-5 on page 291
list the GPIO pins and the analog and digital alternate functions. The AINx analog signals are not
5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are
configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register.
Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-,
C1+, C2-, C2+). These signals are configured by clearing the DEN bit in the GPIO Digital Enable
(GPIODEN) register. The digital alternate hardware functions are enabled by setting the appropriate
bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring
the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in
the table below. Note that each pin must be programmed individually; no type of grouping is implied
by the columns in the table.

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Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.

Table 8-1. GPIO Pins With Non-Zero Reset Values

GPIO Pins Default State GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL
PA[1:0] UART0 1 1 0 0 0x1
PA[5:2] SSI0 1 1 0 0 0x1
PB[3:2] I2C0 1 1 0 0 0x1
PC[3:0] JTAG/SWD 1 1 0 1 0x3

Table 8-2. GPIO Pins and Alternate Functions (100LQFP)

IO Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 I2C1SCL
PA7 35 I2C1SDA
PB0 66 CCP0
PB1 67 CCP2
PB2 70 I2C0SCL
PB3 71 I2C0SDA
PB4 92 C0-
PB5 91 C1-
PB6 90 C0+
PB7 89 TRST
PC0 80 TCK SWCLK
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25 PhA0
PC5 24 C1+
PC6 23 C2+
PC7 22 C2-
PD0 10 IDX0
PD1 11 PWM1
PD2 12 U1Rx
PD3 13 U1Tx
PE0 72 SSI1Clk

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Table 8-2. GPIO Pins and Alternate Functions (100LQFP) (continued)

IO Pin Number Multiplexed Function Multiplexed Function
PE1 73 SSI1Fss
PE2 74 SSI1Rx
PE3 75 SSI1Tx
PF0 47 PhB0
PF1 61 IDX1
PF2 60 PWM4
PF3 59 PWM5
PF4 58 C0o
PF5 46
PF6 43 CCP1
PF7 42
PG0 19 U2Rx
PG1 18 U2Tx
PG2 17 PWM0
PG3 16
PG4 41 CCP3
PG5 40
PG6 37 PhA1
PG7 36 PhB1
PH0 86 PWM2
PH1 85 PWM3
PH2 84
PH3 83 Fault

Table 8-3. GPIO Pins and Alternate Functions (108BGA)

IO Pin Number Multiplexed Function Multiplexed Function
PA0 L3 U0Rx
PA1 M3 U0Tx
PA2 M4 SSI0Clk
PA3 L4 SSI0Fss
PA4 L5 SSI0Rx
PA5 M5 SSI0Tx
PA6 L6 I2C1SCL
PA7 M6 I2C1SDA
PB0 E12 CCP0
PB1 D12 CCP2
PB2 C11 I2C0SCL
PB3 C12 I2C0SDA
PB4 A6 C0-
PB5 B7 C1-
PB6 A7 C0+

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Table 8-3. GPIO Pins and Alternate Functions (108BGA) (continued)

IO Pin Number Multiplexed Function Multiplexed Function
PB7 A8 TRST
PC0 A9 TCK SWCLK
PC1 B9 TMS SWDIO
PC2 B8 TDI
PC3 A10 TDO SWO
PC4 L1 PhA0
PC5 M1 C1+
PC6 M2 C2+
PC7 L2 C2-
PD0 G1 IDX0
PD1 G2 PWM1
PD2 H2 U1Rx
PD3 H1 U1Tx
PE0 A11 SSI1Clk
PE1 B12 SSI1Fss
PE2 B11 SSI1Rx
PE3 A12 SSI1Tx
PF0 M9 PhB0
PF1 H12 IDX1
PF2 J11 PWM4
PF3 J12 PWM5
PF4 L9 C0o
PF5 L8
PF6 M8 CCP1
PF7 K4
PG0 K1 U2Rx
PG1 K2 U2Tx
PG2 J1 PWM0
PG3 J2
PG4 K3 CCP3
PG5 M7
PG6 L7 PhA1
PG7 C10 PhB1
PH0 C9 PWM2
PH1 C8 PWM3
PH2 D11
PH3 D10 Fault

Table 8-4. GPIO Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
PA0 26 I/O TTL GPIO port A bit 0.

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Table 8-4. GPIO Signals (100LQFP) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PA1 27 I/O TTL GPIO port A bit 1.
PA2 28 I/O TTL GPIO port A bit 2.
PA3 29 I/O TTL GPIO port A bit 3.
PA4 30 I/O TTL GPIO port A bit 4.
PA5 31 I/O TTL GPIO port A bit 5.
PA6 34 I/O TTL GPIO port A bit 6.
PA7 35 I/O TTL GPIO port A bit 7.
PB0 66 I/O TTL GPIO port B bit 0.
PB1 67 I/O TTL GPIO port B bit 1.
PB2 70 I/O TTL GPIO port B bit 2.
PB3 71 I/O TTL GPIO port B bit 3.
PB4 92 I/O TTL GPIO port B bit 4.
PB5 91 I/O TTL GPIO port B bit 5.
PB6 90 I/O TTL GPIO port B bit 6.
PB7 89 I/O TTL GPIO port B bit 7.
PC0 80 I/O TTL GPIO port C bit 0.
PC1 79 I/O TTL GPIO port C bit 1.
PC2 78 I/O TTL GPIO port C bit 2.
PC3 77 I/O TTL GPIO port C bit 3.
PC4 25 I/O TTL GPIO port C bit 4.
PC5 24 I/O TTL GPIO port C bit 5.
PC6 23 I/O TTL GPIO port C bit 6.
PC7 22 I/O TTL GPIO port C bit 7.
PD0 10 I/O TTL GPIO port D bit 0.
PD1 11 I/O TTL GPIO port D bit 1.
PD2 12 I/O TTL GPIO port D bit 2.
PD3 13 I/O TTL GPIO port D bit 3.
PE0 72 I/O TTL GPIO port E bit 0.
PE1 73 I/O TTL GPIO port E bit 1.
PE2 74 I/O TTL GPIO port E bit 2.
PE3 75 I/O TTL GPIO port E bit 3.
PF0 47 I/O TTL GPIO port F bit 0.
PF1 61 I/O TTL GPIO port F bit 1.
PF2 60 I/O TTL GPIO port F bit 2.
PF3 59 I/O TTL GPIO port F bit 3.
PF4 58 I/O TTL GPIO port F bit 4.
PF5 46 I/O TTL GPIO port F bit 5.
PF6 43 I/O TTL GPIO port F bit 6.
PF7 42 I/O TTL GPIO port F bit 7.
PG0 19 I/O TTL GPIO port G bit 0.
PG1 18 I/O TTL GPIO port G bit 1.

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Table 8-4. GPIO Signals (100LQFP) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PG2 17 I/O TTL GPIO port G bit 2.
PG3 16 I/O TTL GPIO port G bit 3.
PG4 41 I/O TTL GPIO port G bit 4.
PG5 40 I/O TTL GPIO port G bit 5.
PG6 37 I/O TTL GPIO port G bit 6.
PG7 36 I/O TTL GPIO port G bit 7.
PH0 86 I/O TTL GPIO port H bit 0.
PH1 85 I/O TTL GPIO port H bit 1.
PH2 84 I/O TTL GPIO port H bit 2.
PH3 83 I/O TTL GPIO port H bit 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 8-5. GPIO Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
PA0 L3 I/O TTL GPIO port A bit 0.
PA1 M3 I/O TTL GPIO port A bit 1.
PA2 M4 I/O TTL GPIO port A bit 2.
PA3 L4 I/O TTL GPIO port A bit 3.
PA4 L5 I/O TTL GPIO port A bit 4.
PA5 M5 I/O TTL GPIO port A bit 5.
PA6 L6 I/O TTL GPIO port A bit 6.
PA7 M6 I/O TTL GPIO port A bit 7.
PB0 E12 I/O TTL GPIO port B bit 0.
PB1 D12 I/O TTL GPIO port B bit 1.
PB2 C11 I/O TTL GPIO port B bit 2.
PB3 C12 I/O TTL GPIO port B bit 3.
PB4 A6 I/O TTL GPIO port B bit 4.
PB5 B7 I/O TTL GPIO port B bit 5.
PB6 A7 I/O TTL GPIO port B bit 6.
PB7 A8 I/O TTL GPIO port B bit 7.
PC0 A9 I/O TTL GPIO port C bit 0.
PC1 B9 I/O TTL GPIO port C bit 1.
PC2 B8 I/O TTL GPIO port C bit 2.
PC3 A10 I/O TTL GPIO port C bit 3.
PC4 L1 I/O TTL GPIO port C bit 4.
PC5 M1 I/O TTL GPIO port C bit 5.
PC6 M2 I/O TTL GPIO port C bit 6.
PC7 L2 I/O TTL GPIO port C bit 7.
PD0 G1 I/O TTL GPIO port D bit 0.
PD1 G2 I/O TTL GPIO port D bit 1.
PD2 H2 I/O TTL GPIO port D bit 2.

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Table 8-5. GPIO Signals (108BGA) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PD3 H1 I/O TTL GPIO port D bit 3.
PE0 A11 I/O TTL GPIO port E bit 0.
PE1 B12 I/O TTL GPIO port E bit 1.
PE2 B11 I/O TTL GPIO port E bit 2.
PE3 A12 I/O TTL GPIO port E bit 3.
PF0 M9 I/O TTL GPIO port F bit 0.
PF1 H12 I/O TTL GPIO port F bit 1.
PF2 J11 I/O TTL GPIO port F bit 2.
PF3 J12 I/O TTL GPIO port F bit 3.
PF4 L9 I/O TTL GPIO port F bit 4.
PF5 L8 I/O TTL GPIO port F bit 5.
PF6 M8 I/O TTL GPIO port F bit 6.
PF7 K4 I/O TTL GPIO port F bit 7.
PG0 K1 I/O TTL GPIO port G bit 0.
PG1 K2 I/O TTL GPIO port G bit 1.
PG2 J1 I/O TTL GPIO port G bit 2.
PG3 J2 I/O TTL GPIO port G bit 3.
PG4 K3 I/O TTL GPIO port G bit 4.
PG5 M7 I/O TTL GPIO port G bit 5.
PG6 L7 I/O TTL GPIO port G bit 6.
PG7 C10 I/O TTL GPIO port G bit 7.
PH0 C9 I/O TTL GPIO port H bit 0.
PH1 C8 I/O TTL GPIO port H bit 1.
PH2 D11 I/O TTL GPIO port H bit 2.
PH3 D10 I/O TTL GPIO port H bit 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

8.2 Functional Description

Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.

Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 293). The LM3S1968 microcontroller contains eight ports and thus eight of these physical
GPIO blocks.

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Figure 8-1. GPIO Port Block Diagram

Commit Mode
Control Control
GPIOLOCK
GPIOAFSEL
GPIOCR
Alternate Input

DEMUX
Pad Input
Alternate Output
Alternate Output Enable

Digital

MUX
Pad Output Package I/O Pin
GPIO Input
Data I/O Pad
Control
GPIO Output

GPIODATA

MUX
Pad Output Enable
GPIO Output Enable
GPIODIR

Interrupt Pad
Control Control

GPIOIS GPIODR2R
Interrupt
GPIOIBE GPIODR4R
GPIOIEV GPIODR8R
GPIOIM GPIOSLR
GPIORIS GPIOPUR
GPIOMIS GPIOPDR
GPIOICR GPIOODR
GPIODEN

Identification Registers

GPIOPeriphID0 GPIOPeriphID4 GPIOPCellID0

GPIOPeriphID1 GPIOPeriphID5 GPIOPCellID1
GPIOPeriphID2 GPIOPeriphID6 GPIOPCellID2
GPIOPeriphID3 GPIOPeriphID7 GPIOPCellID3

8.2.1 Data Control

The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.

8.2.1.1 Data Direction Operation

The GPIO Direction (GPIODIR) register (see page 301) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.

8.2.1.2 Data Register Operation

To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 300) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.

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During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-2 on page 294, where u is data unchanged by the write.

Figure 8-2. GPIODATA Write Example

ADDR[9:2] 9 8 7 6 5 4 3 2 1 0
0x098 0 0 1 0 0 1 1 0 0 0

0xEB 1 1 1 0 1 0 1 1

GPIODATA u u 1 u u 0 1 u
7 6 5 4 3 2 1 0

During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 294.

Figure 8-3. GPIODATA Read Example

ADDR[9:2] 9 8 7 6 5 4 3 2 1 0
0x0C4 0 0 1 1 0 0 0 1 0 0

GPIODATA 1 0 1 1 1 1 1 0

Returned Value 0 0 1 1 0 0 0 0
7 6 5 4 3 2 1 0

8.2.2 Interrupt Control

The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:

■ GPIO Interrupt Sense (GPIOIS) register (see page 302)

■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 303)

■ GPIO Interrupt Event (GPIOIEV) register (see page 304)

Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 305).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 306 and page 307). As the name implies, the GPIOMIS register only shows interrupt

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conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the PortB interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4,
and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the
PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 109
for more information.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 308).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.

8.2.3 Mode Control

The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 309), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.

8.2.4 Commit Control

The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 309) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 319) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 320) have been set to 1.

8.2.5 Pad Control

The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.

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8.2.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.

8.3 Initialization and Configuration

To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-6 on page 296
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-7 on page 296 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.

Table 8-6. GPIO Pad Configuration Examples

a
GPIO Register Bit Value
Configuration
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Input (GPIO) 0 0 0 1 ? ? X X X X
Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ?
Open Drain Output 0 1 1 1 X X ? ? ? ?
(GPIO)
Open Drain 1 X 1 1 X X ? ? ? ?
Input/Output (I2C)
Digital Input (Timer 1 X 0 1 ? ? X X X X
CCP)
Digital Input (QEI) 1 X 0 1 ? ? X X X X
Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ?
Digital Output (Timer 1 X 0 1 ? ? ? ? ? ?
PWM)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(SSI)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(UART)
Analog Input 0 0 0 0 0 0 X X X X
(Comparator)
Digital Output 1 X 0 1 ? ? ? ? ? ?
(Comparator)
a. X=Ignored (don’t care bit)

?=Can be either 0 or 1, depending on the configuration

Table 8-7. GPIO Interrupt Configuration Example

a
Desired Pin 2 Bit Value
Interrupt
Register 7 6 5 4 3 2 1 0
Event
Trigger
GPIOIS 0=edge X X X X X 0 X X
1=level

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Table 8-7. GPIO Interrupt Configuration Example (continued)

a
Desired Pin 2 Bit Value
Interrupt
Register 7 6 5 4 3 2 1 0
Event
Trigger
GPIOIBE 0=single X X X X X 0 X X
edge
1=both
edges
GPIOIEV 0=Low level, X X X X X 1 X X
or negative
edge
1=High level,
or positive
edge
GPIOIM 0=masked 0 0 0 0 0 1 0 0
1=not
masked
a. X=Ignored (don’t care bit)

8.4 Register Map

Table 8-8 on page 298 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:

■ GPIO Port A: 0x4000.4000

■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
■ GPIO Port H: 0x4002.7000

Note that the GPIO module clock must be enabled before the registers can be programmed (see
page 228). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.

Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect, and reading those unconnected
bits returns no meaningful data.

Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.

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The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-committable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.

Table 8-8. GPIO Register Map

See
Offset Name Type Reset Description
page

0x000 GPIODATA R/W 0x0000.0000 GPIO Data 300

0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 301

0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 302

0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 303

0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 304

0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 305

0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 306

0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 307

0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 308

0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 309

0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 311

0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 312

0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 313

0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 314

0x510 GPIOPUR R/W - GPIO Pull-Up Select 315

0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 316

0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 317

0x51C GPIODEN R/W - GPIO Digital Enable 318

0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 319

0x524 GPIOCR - - GPIO Commit 320

0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 322

0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 323

0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 324

0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 325

0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 326

0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 327

0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 328

0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 329

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Table 8-8. GPIO Register Map (continued)

See
Offset Name Type Reset Description
page

0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 330

0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 331

0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 332

0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 333

8.5 Register Descriptions

The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.

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Register 1: GPIO Data (GPIODATA), offset 0x000

The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 301).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.

GPIO Data (GPIODATA)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DATA R/W 0x00 GPIO Data

This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 293 for examples of
reads and writes.

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Register 2: GPIO Direction (GPIODIR), offset 0x400

The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.

GPIO Direction (GPIODIR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DIR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DIR R/W 0x00 GPIO Data Direction

The DIR values are defined as follows:

Value Description
0 Pins are inputs.
1 Pins are outputs.

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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404

The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.

GPIO Interrupt Sense (GPIOIS)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IS

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 IS R/W 0x00 GPIO Interrupt Sense

The IS values are defined as follows:

Value Description
0 Edge on corresponding pin is detected (edge-sensitive).
1 Level on corresponding pin is detected (level-sensitive).

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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408

The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 302) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 304). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.

GPIO Interrupt Both Edges (GPIOIBE)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IBE

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 IBE R/W 0x00 GPIO Interrupt Both Edges

The IBE values are defined as follows:

Value Description
0 Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 304).
1 Both edges on the corresponding pin trigger an interrupt.

Note: Single edge is determined by the corresponding bit

in GPIOIEV.

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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C

The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 302). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.

GPIO Interrupt Event (GPIOIEV)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IEV

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 IEV R/W 0x00 GPIO Interrupt Event

The IEV values are defined as follows:

Value Description
0 Falling edge or Low levels on corresponding pins trigger
interrupts.
1 Rising edge or High levels on corresponding pins trigger
interrupts.

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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410

The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.

GPIO Interrupt Mask (GPIOIM)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x410
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IME

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 IME R/W 0x00 GPIO Interrupt Mask Enable

The IME values are defined as follows:

Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.

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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414

The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 305). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.

GPIO Raw Interrupt Status (GPIORIS)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x414
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 RIS RO 0x00 GPIO Interrupt Raw Status

Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:

Value Description
0 Corresponding pin interrupt requirements not met.
1 Corresponding pin interrupt has met requirements.

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Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418

The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the PortB interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4,
and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the
PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 109
for more information.
GPIOMIS is the state of the interrupt after masking.

GPIO Masked Interrupt Status (GPIOMIS)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x418
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 MIS RO 0x00 GPIO Masked Interrupt Status

Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:

Value Description
0 Corresponding GPIO line interrupt not active.
1 Corresponding GPIO line asserting interrupt.

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Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C

The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.

GPIO Interrupt Clear (GPIOICR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x41C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IC

Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 IC W1C 0x00 GPIO Interrupt Clear

The IC values are defined as follows:

Value Description
0 Corresponding interrupt is unaffected.
1 Corresponding interrupt is cleared.

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Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420

The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 309) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 319) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 320) have been set to 1.

Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.

Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.

GPIO Alternate Function Select (GPIOAFSEL)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x420
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved AFSEL

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 - - - - - - - -

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

7:0 AFSEL R/W - GPIO Alternate Function Select

The AFSEL values are defined as follows:

Value Description
0 Software control of corresponding GPIO line (GPIO mode).
1 Hardware control of corresponding GPIO line (alternate
hardware function).

Note: The default reset value for the GPIOAFSEL,

GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.

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Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500

The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.

GPIO 2-mA Drive Select (GPIODR2R)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x500
Type R/W, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DRV2

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DRV2 R/W 0xFF Output Pad 2-mA Drive Enable

A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.

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Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504

The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.

GPIO 4-mA Drive Select (GPIODR4R)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x504
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DRV4

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DRV4 R/W 0x00 Output Pad 4-mA Drive Enable

A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.

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Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508

The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.

GPIO 8-mA Drive Select (GPIODR8R)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x508
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DRV8

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DRV8 R/W 0x00 Output Pad 8-mA Drive Enable

A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.

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Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C

The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 318).
Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and
GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain
input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the
GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no
effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see
examples in “Initialization and Configuration” on page 296).

GPIO Open Drain Select (GPIOODR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x50C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ODE

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 ODE R/W 0x00 Output Pad Open Drain Enable

The ODE values are defined as follows:

Value Description
0 Open drain configuration is disabled.
1 Open drain configuration is enabled.

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Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510

The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 316).

GPIO Pull-Up Select (GPIOPUR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x510
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PUE

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 - - - - - - - -

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PUE R/W - Pad Weak Pull-Up Enable

Value Description
0 The corresponding pin's weak pull-up resistor is disabled.
1 The corresponding pin's weak pull-up resistor is enabled.

A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]

enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.

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Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514

The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 315).

GPIO Pull-Down Select (GPIOPDR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x514
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PDE

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PDE R/W 0x00 Pad Weak Pull-Down Enable

Value Description
0 The corresponding pin's weak pull-down resistor is disabled.
1 The corresponding pin's weak pull-down resistor is enabled.

A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]

enables. The change is effective on the second clock cycle after the
write.

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Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 313).

GPIO Slew Rate Control Select (GPIOSLR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x518
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SRL

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 SRL R/W 0x00 Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:

Value Description
0 Slew rate control disabled.
1 Slew rate control enabled.

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Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C

Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.

GPIO Digital Enable (GPIODEN)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x51C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DEN

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 - - - - - - - -

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DEN R/W - Digital Enable

The DEN values are defined as follows:

Value Description
0 Digital functions disabled.
1 Digital functions enabled.

Note: The default reset value for the GPIOAFSEL,

GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.

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Register 19: GPIO Lock (GPIOLOCK), offset 0x520

The GPIOLOCK register enables write access to the GPIOCR register (see page 320). Writing
0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.

GPIO Lock (GPIOLOCK)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x520
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LOCK

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LOCK

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:0 LOCK R/W 0x0000.0001 GPIO Lock

A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR)
register for write access.
A write of any other value or a write to the GPIOCR register reapplies
the lock, preventing any register updates. A read of this register returns
the following values:

Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked

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Register 20: GPIO Commit (GPIOCR), offset 0x524

The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed.
If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the
GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR
register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be
committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.

Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR
register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted
to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the
corresponding registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSELregister bits of these other pins.

GPIO Commit (GPIOCR)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x524
Type -, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CR

Type RO RO RO RO RO RO RO RO - - - - - - - -
Reset 0 0 0 0 0 0 0 0 - - - - - - - -

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

7:0 CR - - GPIO Commit

On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.

Note: The default register type for the GPIOCR register is RO for
all GPIO pins with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.

The default reset value for the GPIOCR register is

0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-committable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.

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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0

The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 4 (GPIOPeriphID4)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID4

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]

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Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4

The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 5 (GPIOPeriphID5)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID5

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]

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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8

The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 6 (GPIOPeriphID6)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID6

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]

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Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC

The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 7 (GPIOPeriphID7)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID7

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]

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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0

The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 0 (GPIOPeriphID0)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE0
Type RO, reset 0x0000.0061
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID0 RO 0x61 GPIO Peripheral ID Register[7:0]

Can be used by software to identify the presence of this peripheral.

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Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4

The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 1 (GPIOPeriphID1)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID1 RO 0x00 GPIO Peripheral ID Register[15:8]

Can be used by software to identify the presence of this peripheral.

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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8

The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 2 (GPIOPeriphID2)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID2 RO 0x18 GPIO Peripheral ID Register[23:16]

Can be used by software to identify the presence of this peripheral.

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Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC

The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.

GPIO Peripheral Identification 3 (GPIOPeriphID3)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID3 RO 0x01 GPIO Peripheral ID Register[31:24]

Can be used by software to identify the presence of this peripheral.

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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0

The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.

GPIO PrimeCell Identification 0 (GPIOPCellID0)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID0 RO 0x0D GPIO PrimeCell ID Register[7:0]

Provides software a standard cross-peripheral identification system.

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Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4

The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.

GPIO PrimeCell Identification 1 (GPIOPCellID1)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID1 RO 0xF0 GPIO PrimeCell ID Register[15:8]

Provides software a standard cross-peripheral identification system.

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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8

The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.

GPIO PrimeCell Identification 2 (GPIOPCellID2)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID2 RO 0x05 GPIO PrimeCell ID Register[23:16]

Provides software a standard cross-peripheral identification system.

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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC

The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.

GPIO PrimeCell Identification 3 (GPIOPCellID3)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID3 RO 0xB1 GPIO PrimeCell ID Register[31:24]

Provides software a standard cross-peripheral identification system.

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9 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
®
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1,
Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger
signals from all of the general-purpose timers are ORed together before reaching the ADC module,
so only one timer should be used to trigger ADC events.
The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer
resources include the System Timer (SysTick) (see 94) and the PWM timer in the PWM module
(see “PWM Timer” on page 566).
The General-Purpose Timers provide the following features:

■ Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters.
Each GPTM can be configured to operate independently:

– As a single 32-bit timer

– As one 32-bit Real-Time Clock (RTC) to event capture

– For Pulse Width Modulation (PWM)

– To trigger analog-to-digital conversions

■ 32-bit Timer modes

– Programmable one-shot timer

– Programmable periodic timer

– Real-Time Clock when using an external 32.768-KHz clock as the input

– User-enabled stalling when the controller asserts CPU Halt flag during debug

– ADC event trigger

■ 16-bit Timer modes

– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)

– Programmable one-shot timer

– Programmable periodic timer

– User-enabled stalling when the controller asserts CPU Halt flag during debug

– ADC event trigger

■ 16-bit Input Capture modes

– Input edge count capture

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– Input edge time capture

■ 16-bit PWM mode

– Simple PWM mode with software-programmable output inversion of the PWM signal

9.1 Block Diagram

Note: In Figure 9-1 on page 335, the specific CCP pins available depend on the Stellaris device.
See Table 9-1 on page 335 for the available CCPs.

Figure 9-1. GPTM Module Block Diagram

0x0000 (Down Counter Modes)

TimerA Control

GPTMTAPMR TA Comparator
GPTMTAPR
GPTMTAMATCHR Clock / Edge
Detect
Interrupt / Config GPTMTAILR 32 KHz or
GPTMAR En
Even CCP Pin
GPTMTAMR
GPTMCFG
TimerA
Interrupt GPTMCTL
GPTMIMR RTC Divider
GPTMRIS
TimerB
Interrupt GPTMMIS TimerB Control
GPTMICR
GPTMTBPMR GPTMTBR En
Clock / Edge
GPTMTBPR Detect
Odd CCP Pin
GPTMTBMATCHR
GPTMTBILR TB Comparator

GPTMTBMR

0x0000 (Down Counter Modes)

System
Clock

Table 9-1. Available CCP Pins

Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA CCP0 -
TimerB - CCP1
Timer 1 TimerA CCP2 -
TimerB - CCP3
Timer 2 TimerA - -
TimerB - -
Timer 3 TimerA - -
TimerB - -

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9.2 Signal Description

Table 9-2 on page 336 and Table 9-3 on page 336 list the external signals of the GP Timer module
and describe the function of each. The GP Timer signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 309) should be set to choose the GP Timer
function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 286.

Table 9-2. General-Purpose Timers Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
CCP0 66 I/O TTL Capture/Compare/PWM 0.
CCP1 43 I/O TTL Capture/Compare/PWM 1.
CCP2 67 I/O TTL Capture/Compare/PWM 2.
CCP3 41 I/O TTL Capture/Compare/PWM 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 9-3. General-Purpose Timers Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
CCP0 E12 I/O TTL Capture/Compare/PWM 0.
CCP1 M8 I/O TTL Capture/Compare/PWM 1.
CCP2 D12 I/O TTL Capture/Compare/PWM 2.
CCP3 K3 I/O TTL Capture/Compare/PWM 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

9.3 Functional Description

The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 347),
the GPTM TimerA Mode (GPTMTAMR) register (see page 348), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 350). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.

9.3.1 GPTM Reset Conditions

After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 361) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 362). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 365) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 366).

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9.3.2 32-Bit Timer Operating Modes

This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:

■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 361

■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 362

■ GPTM TimerA (GPTMTAR) register [15:0], see page 369

■ GPTM TimerB (GPTMTBR) register [15:0], see page 370

In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:

GPTMTBILR[15:0]:GPTMTAILR[15:0]

Likewise, a read access to GPTMTAR returns the value:

GPTMTBR[15:0]:GPTMTAR[15:0]

9.3.2.1 32-Bit One-Shot/Periodic Timer Mode

In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 348), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 352), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 357), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 359). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTMIMR) register (see page 355), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 358). The ADC trigger is enabled by setting the
TAOTE bit in GPTMCTL.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.

9.3.2.2 32-Bit Real-Time Clock Timer Mode

In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is

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loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 363) by the controller.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the
GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.

9.3.3 16-Bit Timer Operating Modes

The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 347). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.

9.3.3.1 16-Bit One-Shot/Periodic Timer Mode

In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger is
enabled by setting the TnOTE bit in the GPTMCTL register.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).

Table 9-4. 16-Bit Timer With Prescaler Configurations

a
Prescale #Clock (T c) Max Time Units
00000000 1 1.3107 mS

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Table 9-4. 16-Bit Timer With Prescaler Configurations (continued)

a
Prescale #Clock (T c) Max Time Units
00000001 2 2.6214 mS
00000010 3 3.9322 mS
------------ -- -- --
11111101 254 332.9229 mS
11111110 255 334.2336 mS
11111111 256 335.5443 mS
a. Tc is the clock period.

9.3.3.2 16-Bit Input Edge Count Mode

Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 9-2 on page 340 shows how input edge count mode works. In this case, the timer start value
is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that
four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMTnMATCHR register.

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Figure 9-2. 16-Bit Input Edge Count Mode Example

Timer stops, Timer reload

Count flags on next cycle Ignored Ignored
asserted

0x000A
0x0009
0x0008
0x0007
0x0006

Input Signal

9.3.3.3 16-Bit Input Edge Time Mode

Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). The timer is capable of capturing three
types of events: rising edge, falling edge, or both. The timer is placed into Edge Time mode by
setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is
determined by the TnEVENT fields of the GPTMCTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMTnILR register.
Figure 9-3 on page 341 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).

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Figure 9-3. 16-Bit Input Edge Time Mode Example

Count
0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z

Y
Time

Input Signal

9.3.3.4 16-Bit PWM Mode

Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM
frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 on page 342 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is
GPTMTnMATCHR=0x411A.

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Figure 9-4. 16-Bit PWM Mode Example

Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR

0xC350

0x411A

Time

TnEN set

TnPWML = 0
Output
Signal
TnPWML = 1

9.4 Initialization and Configuration

To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.

9.4.1 32-Bit One-Shot/Periodic Timer Mode

The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:

1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.

2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.

3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):

a. Write a value of 0x1 for One-Shot mode.

b. Write a value of 0x2 for Periodic mode.

4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).

5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).

6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.

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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).

In One-Shot mode, the timer stops counting after step 7 on page 343. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.

9.4.2 32-Bit Real-Time Clock (RTC) Mode

To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:

1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.

2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.

3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).

4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.

5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).

6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.

When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the
RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware
reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register.

9.4.3 16-Bit One-Shot/Periodic Timer Mode

A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:

1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.

3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:

a. Write a value of 0x1 for One-Shot mode.

b. Write a value of 0x2 for Periodic mode.

4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).

5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).

6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).

7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.

8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).

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In One-Shot mode, the timer stops counting after step 8 on page 343. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.

9.4.4 16-Bit Input Edge Count Mode

A timer is configured to Input Edge Count mode by the following sequence:

1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.

3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.

4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.

5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.

6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.

7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.

8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.

9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.

In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 344
through step 9 on page 344.

9.4.5 16-Bit Input Edge Timing Mode

A timer is configured to Input Edge Timing mode by the following sequence:

1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.

3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.

4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.

5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.

6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.

7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.

8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM

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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.

In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.

9.4.6 16-Bit PWM Mode

A timer is configured to PWM mode using the following sequence:

1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.

3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.

4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.

5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.

6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.

7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.

In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.

9.5 Register Map

Table 9-5 on page 345 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:

■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
■ Timer3: 0x4003.3000

Note that the Timer module clock must be enabled before the registers can be programmed (see
page 219). There must be a delay of 3 system clocks after the Timer module clock is enabled before
any Timer module registers are accessed.

Table 9-5. Timers Register Map

See
Offset Name Type Reset Description
page

0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 347

0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 348

0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 350

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Table 9-5. Timers Register Map (continued)

See
Offset Name Type Reset Description
page

0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 352

0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 355

0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 357

0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 358

0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 359

0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM TimerA Interval Load 361

0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 362

0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM TimerA Match 363

0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 364

0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 365

0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 366

0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 367

0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 368

0x048 GPTMTAR RO 0xFFFF.FFFF GPTM TimerA 369

0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 370

9.6 Register Descriptions

The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.

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Register 1: GPTM Configuration (GPTMCFG), offset 0x000

This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.

GPTM Configuration (GPTMCFG)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GPTMCFG

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 GPTMCFG R/W 0x0 GPTM Configuration

The GPTMCFG values are defined as follows:

Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved
0x3 Reserved
0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.

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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004

This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.

GPTM TimerA Mode (GPTMTAMR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TAAMS TACMR TAMR

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TAAMS R/W 0 GPTM TimerA Alternate Mode Select

The TAAMS values are defined as follows:

Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.

Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.

2 TACMR R/W 0 GPTM TimerA Capture Mode

The TACMR values are defined as follows:

Value Description
0 Edge-Count mode
1 Edge-Time mode

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Bit/Field Name Type Reset Description

1:0 TAMR R/W 0x0 GPTM TimerA Mode

The TAMR values are defined as follows:

Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode

The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.

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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008

This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.

GPTM TimerB Mode (GPTMTBMR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TBAMS TBCMR TBMR

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TBAMS R/W 0 GPTM TimerB Alternate Mode Select

The TBAMS values are defined as follows:

Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.

Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.

2 TBCMR R/W 0 GPTM TimerB Capture Mode

The TBCMR values are defined as follows:

Value Description
0 Edge-Count mode
1 Edge-Time mode

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Bit/Field Name Type Reset Description

1:0 TBMR R/W 0x0 GPTM TimerB Mode

The TBMR values are defined as follows:

Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode

The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.

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Register 4: GPTM Control (GPTMCTL), offset 0x00C

This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.

GPTM Control (GPTMCTL)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN

Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14 TBPWML R/W 0 GPTM TimerB PWM Output Level

The TBPWML values are defined as follows:

Value Description
0 Output is unaffected.
1 Output is inverted.

13 TBOTE R/W 0 GPTM TimerB Output Trigger Enable

The TBOTE values are defined as follows:

Value Description
0 The output TimerB ADC trigger is disabled.
1 The output TimerB ADC trigger is enabled.

In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 410).

12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

11:10 TBEVENT R/W 0x0 GPTM TimerB Event Mode

The TBEVENT values are defined as follows:

Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges

9 TBSTALL R/W 0 GPTM Timer B Stall Enable

The TBSTALL values are defined as follows:

Value Description
0 Timer B continues counting while the processor is halted by the
debugger.
1 Timer B freezes counting while the processor is halted by the
debugger.

If the processor is executing normally, the TBSTALL bit is ignored.

8 TBEN R/W 0 GPTM TimerB Enable

The TBEN values are defined as follows:

Value Description
0 TimerB is disabled.
1 TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 TAPWML R/W 0 GPTM TimerA PWM Output Level

The TAPWML values are defined as follows:

Value Description
0 Output is unaffected.
1 Output is inverted.

5 TAOTE R/W 0 GPTM TimerA Output Trigger Enable

The TAOTE values are defined as follows:

Value Description
0 The output TimerA ADC trigger is disabled.
1 The output TimerA ADC trigger is enabled.

In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 410).

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Bit/Field Name Type Reset Description

4 RTCEN R/W 0 GPTM RTC Enable

The RTCEN values are defined as follows:

Value Description
0 RTC counting is disabled.
1 RTC counting is enabled.

3:2 TAEVENT R/W 0x0 GPTM TimerA Event Mode

The TAEVENT values are defined as follows:

Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges

1 TASTALL R/W 0 GPTM Timer A Stall Enable

The TASTALL values are defined as follows:

Value Description
0 Timer A continues counting while the processor is halted by the
debugger.
1 Timer A freezes counting while the processor is halted by the
debugger.

If the processor is executing normally, the TASTALL bit is ignored.

0 TAEN R/W 0 GPTM TimerA Enable

The TAEN values are defined as follows:

Value Description
0 TimerA is disabled.
1 TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.

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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018

This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.

GPTM Interrupt Mask (GPTMIMR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM

Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 CBEIM R/W 0 GPTM CaptureB Event Interrupt Mask

The CBEIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

9 CBMIM R/W 0 GPTM CaptureB Match Interrupt Mask

The CBMIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

8 TBTOIM R/W 0 GPTM TimerB Time-Out Interrupt Mask

The TBTOIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

3 RTCIM R/W 0 GPTM RTC Interrupt Mask

The RTCIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

2 CAEIM R/W 0 GPTM CaptureA Event Interrupt Mask

The CAEIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

1 CAMIM R/W 0 GPTM CaptureA Match Interrupt Mask

The CAMIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

0 TATOIM R/W 0 GPTM TimerA Time-Out Interrupt Mask

The TATOIM values are defined as follows:

Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.

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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C

This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.

GPTM Raw Interrupt Status (GPTMRIS)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 CBERIS RO 0 GPTM CaptureB Event Raw Interrupt

This is the CaptureB Event interrupt status prior to masking.

9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt

This is the CaptureB Match interrupt status prior to masking.

8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt

This is the TimerB time-out interrupt status prior to masking.

7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 RTCRIS RO 0 GPTM RTC Raw Interrupt

This is the RTC Event interrupt status prior to masking.

2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt

This is the CaptureA Event interrupt status prior to masking.

1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt

This is the CaptureA Match interrupt status prior to masking.

0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt

This the TimerA time-out interrupt status prior to masking.

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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020

This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.

GPTM Masked Interrupt Status (GPTMMIS)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 CBEMIS RO 0 GPTM CaptureB Event Masked Interrupt

This is the CaptureB event interrupt status after masking.

9 CBMMIS RO 0 GPTM CaptureB Match Masked Interrupt

This is the CaptureB match interrupt status after masking.

8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt

This is the TimerB time-out interrupt status after masking.

7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 RTCMIS RO 0 GPTM RTC Masked Interrupt

This is the RTC event interrupt status after masking.

2 CAEMIS RO 0 GPTM CaptureA Event Masked Interrupt

This is the CaptureA event interrupt status after masking.

1 CAMMIS RO 0 GPTM CaptureA Match Masked Interrupt

This is the CaptureA match interrupt status after masking.

0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt

This is the TimerA time-out interrupt status after masking.

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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024

This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.

GPTM Interrupt Clear (GPTMICR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT

Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 CBECINT W1C 0 GPTM CaptureB Event Interrupt Clear

The CBECINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

9 CBMCINT W1C 0 GPTM CaptureB Match Interrupt Clear

The CBMCINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

8 TBTOCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear

The TBTOCINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

3 RTCCINT W1C 0 GPTM RTC Interrupt Clear

The RTCCINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

2 CAECINT W1C 0 GPTM CaptureA Event Interrupt Clear

The CAECINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

1 CAMCINT W1C 0 GPTM CaptureA Match Interrupt Clear

The CAMCINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

0 TATOCINT W1C 0 GPTM TimerA Time-Out Interrupt Clear

The TATOCINT values are defined as follows:

Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.

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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028

This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.

GPTM TimerA Interval Load (GPTMTAILR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x028
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TAILRH

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAILRL

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 TAILRH R/W 0xFFFF GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.

15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.

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Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C

This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.

GPTM TimerB Interval Load (GPTMTBILR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TBILRL

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 TBILRL R/W 0xFFFF GPTM TimerB Interval Load Register

When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.

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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030

This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.

GPTM TimerA Match (GPTMTAMATCHR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TAMRH

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAMRL

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 TAMRH R/W 0xFFFF GPTM TimerA Match Register High

When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.

15:0 TAMRL R/W 0xFFFF GPTM TimerA Match Register Low

When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.

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Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034

This register is used in 16-bit PWM and Input Edge Count modes.

GPTM TimerB Match (GPTMTBMATCHR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TBMRL

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 TBMRL R/W 0xFFFF GPTM TimerB Match Register Low

When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.

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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038

This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.

GPTM TimerA Prescale (GPTMTAPR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TAPSR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 TAPSR R/W 0x00 GPTM TimerA Prescale

The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 9-4 on page 338 for more details and an example.

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Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C

This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.

GPTM TimerB Prescale (GPTMTBPR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TBPSR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 TBPSR R/W 0x00 GPTM TimerB Prescale

The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 9-4 on page 338 for more details and an example.

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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040

This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.

GPTM TimerA Prescale Match (GPTMTAPMR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TAPSMR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 TAPSMR R/W 0x00 GPTM TimerA Prescale Match

This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.

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Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044

This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.

GPTM TimerB Prescale Match (GPTMTBPMR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TBPSMR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 TBPSMR R/W 0x00 GPTM TimerB Prescale Match

This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.

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Register 17: GPTM TimerA (GPTMTAR), offset 0x048

This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.

GPTM TimerA (GPTMTAR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x048
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TARH

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TARL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 TARH RO 0xFFFF GPTM TimerA Register High

If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.

15:0 TARL RO 0xFFFF GPTM TimerA Register Low

A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.

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Register 18: GPTM TimerB (GPTMTBR), offset 0x04C

This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.

GPTM TimerB (GPTMTBR)

Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TBRL

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 TBRL RO 0xFFFF GPTM TimerB

A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.

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10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
®
The Stellaris Watchdog Timer module has the following features:

■ 32-bit down counter with a programmable load register

■ Separate watchdog clock with an enable

■ Programmable interrupt generation logic with interrupt masking

■ Lock register protection from runaway software

■ Reset generation logic with an enable/disable

■ User-enabled stalling when the controller asserts the CPU Halt flag during debug

The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.

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10.1 Block Diagram

Figure 10-1. WDT Module Block Diagram

Control / Clock / WDTLOAD

Interrupt
Generation

WDTCTL
WDTICR
Interrupt WDTRIS
32-Bit Down
WDTMIS Counter

WDTLOCK 0x00000000

System Clock WDTTEST

Comparator

WDTVALUE

Identification Registers

WDTPCellID0 WDTPeriphID0 WDTPeriphID4

WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7

10.2 Functional Description

The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.

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Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.

10.3 Initialization and Configuration

To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:

1. Load the WDTLOAD register with the desired timer load value.

2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.

3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.

If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.

10.4 Register Map

Table 10-1 on page 373 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.

Table 10-1. Watchdog Timer Register Map

See
Offset Name Type Reset Description
page

0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 375

0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 376

0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 377

0x00C WDTICR WO - Watchdog Interrupt Clear 378

0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 379

0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 380

0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 381

0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 382

0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 383

0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 384

0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 385

0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 386

0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 387

0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 388

0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 389

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Table 10-1. Watchdog Timer Register Map (continued)

See
Offset Name Type Reset Description
page

0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 390

0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 391

0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 392

0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 393

0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 394

10.5 Register Descriptions

The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.

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Register 1: Watchdog Load (WDTLOAD), offset 0x000

This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.

Watchdog Load (WDTLOAD)

Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WDTLoad

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDTLoad

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value

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Register 2: Watchdog Value (WDTVALUE), offset 0x004

This register contains the current count value of the timer.

Watchdog Value (WDTVALUE)

Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WDTValue

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDTValue

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit/Field Name Type Reset Description

31:0 WDTValue RO 0xFFFF.FFFF Watchdog Value

Current value of the 32-bit down counter.

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Register 3: Watchdog Control (WDTCTL), offset 0x008

This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.

Watchdog Control (WDTCTL)

Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RESEN INTEN

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 RESEN R/W 0 Watchdog Reset Enable

The RESEN values are defined as follows:

Value Description
0 Disabled.
1 Enable the Watchdog module reset output.

0 INTEN R/W 0 Watchdog Interrupt Enable

The INTEN values are defined as follows:

Value Description
0 Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
1 Interrupt event enabled. Once enabled, all writes are ignored.

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Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C

This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.

Watchdog Interrupt Clear (WDTICR)

Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WDTIntClr

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDTIntClr

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:0 WDTIntClr WO - Watchdog Interrupt Clear

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Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010

This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.

Watchdog Raw Interrupt Status (WDTRIS)

Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved WDTRIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 WDTRIS RO 0 Watchdog Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of WDTINTR.

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Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014

This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.

Watchdog Masked Interrupt Status (WDTMIS)

Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved WDTMIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 WDTMIS RO 0 Watchdog Masked Interrupt Status

Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.

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Register 7: Watchdog Test (WDTTEST), offset 0x418

This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.

Watchdog Test (WDTTEST)

Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved STALL reserved

Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 STALL R/W 0 Watchdog Stall Enable

When set to 1, if the Stellaris microcontroller is stopped with a debugger,
the watchdog timer stops counting. Once the microcontroller is restarted,
the watchdog timer resumes counting.

7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 8: Watchdog Lock (WDTLOCK), offset 0xC00

Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).

Watchdog Lock (WDTLOCK)

Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WDTLock

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDTLock

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 WDTLock R/W 0x0000 Watchdog Lock

A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:

Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked

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Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0

The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 4 (WDTPeriphID4)

Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID4

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]

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Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset

0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 5 (WDTPeriphID5)

Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID5

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]

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Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset

0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 6 (WDTPeriphID6)

Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID6

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]

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Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset

0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 7 (WDTPeriphID7)

Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID7

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]

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Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset

0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 0 (WDTPeriphID0)

Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]

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Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset

0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 1 (WDTPeriphID1)

Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]

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Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset

0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 2 (WDTPeriphID2)

Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]

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Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset

0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog Peripheral Identification 3 (WDTPeriphID3)

Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]

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Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0

The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog PrimeCell Identification 0 (WDTPCellID0)

Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]

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Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4

The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog PrimeCell Identification 1 (WDTPCellID1)

Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]

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Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8

The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog PrimeCell Identification 2 (WDTPCellID2)

Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]

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Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC

The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.

Watchdog PrimeCell Identification 3 (WDTPCellID3)

Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]

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11 Analog-to-Digital Converter (ADC)

An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
®
The Stellaris ADC module features 10-bit conversion resolution and supports eight input channels,
plus an internal temperature sensor. The ADC module contains four programmable sequencer which
allows for the sampling of multiple analog input sources without controller intervention. Each sample
sequence provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequence priority.
The Stellaris ADC module provides the following features:

■ Eight analog input channels

■ Single-ended and differential-input configurations

■ On-chip internal temperature sensor

■ Sample rate of one million samples/second

■ Flexible, configurable analog-to-digital conversion

■ Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs

■ Flexible trigger control

– Controller (software)

– Timers

– Analog Comparators

– PWM

– GPIO

■ Hardware averaging of up to 64 samples for improved accuracy

■ Converter uses an internal 3-V reference

■ Power and ground for the analog circuitry is separate from the digital power and ground

11.1 Block Diagram

Figure 11-1 on page 396 provides details on the internal configuration of the ADC controls and data
registers.

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Figure 11-1. ADC Module Block Diagram

Trigger Events
Analog Inputs
Comparator Sample
Control/Status Sequencer 0
GPIO (PB4)
Timer SS3
PWM ADCACTSS ADCSSMUX0
ADCOSTAT ADCSSCTL0 Analog-to-Digital
Converter
Comparator ADCUSTAT ADCSSFSTAT0
GPIO (PB4) ADCSSPRI
Timer SS2
PWM Sample
Sequencer 1

Comparator ADCSSMUX1
GPIO (PB4) ADCSSCTL1 Hardware Averager
Timer SS1
PWM ADCSSFSTAT1
ADCSAC

Comparator Sample
GPIO (PB4) Sequencer 2
Timer SS0
PWM ADCSSMUX2
ADCSSCTL2 FIFO Block
ADCSSFSTAT2
ADCSSFIFO0
ADCEMUX ADCSSFIFO1
ADCPSSI Sample ADCSSFIFO2
Interrupt Control Sequencer 3
ADCSSFIFO3
SS0 Interrupt ADCIM ADCSSMUX3
SS1 Interrupt ADCRIS ADCSSCTL3
SS2 Interrupt
SS3 Interrupt ADCISC ADCSSFSTAT3

11.2 Signal Description

Table 11-1 on page 396 and Table 11-2 on page 396 list the external signals of the ADC module and
describe the function of each. The signals are analog functions for some GPIO signals. The column
in the table below titled "Pin Assignment" lists the GPIO pin placement for the ADC signals. The
AINx analog signals are not 5-V tolerant and go through an isolation circuit before reaching their
circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital
Enable (GPIODEN) register. For more information on configuring GPIOs, see “General-Purpose
Input/Outputs (GPIOs)” on page 286.

Table 11-1. ADC Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.
ADC4 100 I Analog Analog-to-digital converter input 4.
ADC5 99 I Analog Analog-to-digital converter input 5.
ADC6 96 I Analog Analog-to-digital converter input 6.
ADC7 95 I Analog Analog-to-digital converter input 7.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 11-2. ADC Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 B1 I Analog Analog-to-digital converter input 0.

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Table 11-2. ADC Signals (108BGA) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC1 A1 I Analog Analog-to-digital converter input 1.
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
ADC4 A2 I Analog Analog-to-digital converter input 4.
ADC5 A3 I Analog Analog-to-digital converter input 5.
ADC6 B4 I Analog Analog-to-digital converter input 6.
ADC7 A4 I Analog Analog-to-digital converter input 7.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

11.3 Functional Description

The Stellaris ADC collects sample data by using a programmable sequence-based approach instead
of the traditional single or double-sampling approaches found on many ADC modules. Each sample
sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC
to collect data from multiple input sources without having to be re-configured or serviced by the
controller. The programming of each sample in the sample sequence includes parameters such as
the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.

11.3.1 Sample Sequencers

The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 11-3 on page 397 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.

Table 11-3. Samples and FIFO Depth of Sequencers

Sequencer Number of Samples Depth of FIFO
SS3 1 1
SS2 4 4
SS1 4 4
SS0 8 8

For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, and should be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples,
allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END
bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END

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bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete
execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.

11.3.2 Module Control

Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such
as:

■ Interrupt generation

■ Sequence prioritization

■ Trigger configuration

Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris devices.

11.3.2.1 Interrupts
The register configurations of the sample sequencers dictate which events generate raw interrupts,
but do not have control over whether the interrupt is actually sent to the interrupt controller. The
ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt
Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt
Status (ADCRIS) register, which shows the raw status of the various interrupt signals, and the ADC
Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by
the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.

11.3.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.

11.3.2.3 Sampling Events

Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member,
but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
Care must be taken when using the "Always" trigger. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.

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11.3.3 Hardware Sample Averaging Circuit

Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 418). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.

11.3.4 Analog-to-Digital Converter

The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input. An internal 3 V reference is used by the converter
resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended
input mode.

11.3.5 Differential Sampling

In addition to traditional single-ended sampling, the ADC module supports differential sampling of
two analog input channels. To enable differential sampling, software must set the Dn bit in the
ADCSSCTL0n register in a step's configuration nibble.
When a sequence step is configured for differential sampling, its corresponding value in the
ADCSSMUXn register must be set to one of the four differential pairs, numbered 0-3. Differential
pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on
(see Table 11-4 on page 399). The ADC does not support other differential pairings such as analog
input 0 with analog input 3. The number of differential pairs supported is dependent on the number
of analog inputs (see Table 11-4 on page 399).

Table 11-4. Differential Sampling Pairs

Differential Pair Analog Inputs
0 0 and 1
1 2 and 3
2 4 and 5
3 6 and 7

The voltage sampled in differential mode is the difference between the odd and even channels:
∆V (differential voltage) = VIN_EVEN (even channels) – VIN_ODD (odd channels), therefore:

■ If ∆V = 0, then the conversion result = 0x1FF

■ If ∆V > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF)

■ If ∆V < 0, then the conversion result < 0x1FF (range is 0–0x1FF)

The differential pairs assign polarities to the analog inputs: the even-numbered input is always
positive, and the odd-numbered input is always negative. In order for a valid conversion result to
appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input
is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped,
meaning it appears as either 3 V or 0 V, respectively, to the ADC.

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Figure 11-2 on page 400 shows an example of the negative input centered at 1.5 V. In this
configuration, the differential range spans from -1.5 V to 1.5 V. Figure 11-3 on page 400 shows an
example where the negative input is centered at -0.75 V, meaning inputs on the positive input
saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure
11-4 on page 401 shows an example of the negative input centered at 2.25 V, where inputs on the
positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater
than 3 V.

Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V

ADC Conversion Result

0x3FF

0x1FF

0V 1.5 V 3.0 V VIN_EVEN

-1.5 V 0V 1.5 V DV
VIN_ODD = 1.5 V

- Input Saturation

Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V

ADC Conversion Result

0x3FF

0x1FF

0x0FF

0V +0.75 V +2.25 V VIN_EVEN

-1.5 V -0.75 V +1.5 V DV

- Input Saturation

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Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V

ADC Conversion Result

0x3FF

0x2FF

0x1FF

0.75 V 2.25 V 3.0 V VIN_EVEN

-1.5 V 0.75 V 1.5 V DV

- Input Saturation

11.3.6 Test Modes

There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual analog
stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see
page 431).

11.3.7 Internal Temperature Sensor

The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature
is too high or low for reliable operation, and 2) to provide temperature measurements for calibration
of the Hibernate module RTC trim value.
The temperature sensor does not have a separate enable, since it also contains the bandgap
reference and must always be enabled. The reference is supplied to other analog modules; not just
the ADC.
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:

SENSO = 2.7 - ((T + 55) / 75)

This relation is shown in Figure 11-5 on page 402.

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Figure 11-5. Internal Temperature Sensor Characteristic

11.4 Initialization and Configuration

In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.

11.4.1 Module Initialization

Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:

1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register (see page 213).

2. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.

11.4.2 Sample Sequencer Configuration

Configuration of the sample sequencers is slightly more complex than the module initialization since
each sample sequence is completely programmable.
The configuration for each sample sequencer should be as follows:

1. Ensure that the sample sequencer is disabled by writing a 0 to the corresponding ASENn bit in
the ADCACTSS register. Programming of the sample sequencers is allowed without having
them enabled. Disabling the sequencer during programming prevents erroneous execution if a
trigger event were to occur during the configuration process.

2. Configure the trigger event for the sample sequencer in the ADCEMUX register.

3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.

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4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.

5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.

6. Enable the sample sequencer logic by writing a 1 to the corresponding ASENn bit in the
ADCACTSS register.

11.5 Register Map

Table 11-5 on page 403 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 213). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.

Table 11-5. ADC Register Map

See
Offset Name Type Reset Description
page

0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 405

0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 406

0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 407

0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 408

0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 409

0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 410

0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 414

0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 415

0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 417

0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 418

0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 419

0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 421

0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 424

0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 425

0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 426

0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 427

0x068 ADCSSFIFO1 RO - ADC Sample Sequence Result FIFO 1 424

0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 425

0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 426

0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 427

0x088 ADCSSFIFO2 RO - ADC Sample Sequence Result FIFO 2 424

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Table 11-5. ADC Register Map (continued)

See
Offset Name Type Reset Description
page

0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 425

0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 429

0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 430

0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 424

0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 425

0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 431

11.6 Register Descriptions

The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.

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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000

This register controls the activation of the sample sequencers. Each sample sequencer can be
enabled or disabled independently.

ADC Active Sample Sequencer (ADCACTSS)

Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ASEN3 ASEN2 ASEN1 ASEN0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 ASEN3 R/W 0 ADC SS3 Enable

Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the sequencer is
inactive.

2 ASEN2 R/W 0 ADC SS2 Enable

Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the sequencer is
inactive.

1 ASEN1 R/W 0 ADC SS1 Enable

Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the sequencer is
inactive.

0 ASEN0 R/W 0 ADC SS0 Enable

Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the sequencer is
inactive.

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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004

This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without having to generate controller interrupts.

ADC Raw Interrupt Status (ADCRIS)

Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved INR3 INR2 INR1 INR0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 INR3 RO 0 SS3 Raw Interrupt Status

This bit is set by hardware when a sample with its respective
ADCSSCTL3 IE bit has completed conversion. This bit is cleared by
setting the IN3 bit in the ADCISC register.

2 INR2 RO 0 SS2 Raw Interrupt Status

This bit is set by hardware when a sample with its respective
ADCSSCTL2 IE bit has completed conversion. This bit is cleared by
setting the IN2 bit in the ADCISC register.

1 INR1 RO 0 SS1 Raw Interrupt Status

This bit is set by hardware when a sample with its respective
ADCSSCTL1 IE bit has completed conversion. This bit is cleared by
setting the IN1 bit in the ADCISC register.

0 INR0 RO 0 SS0 Raw Interrupt Status

This bit is set by hardware when a sample with its respective
ADCSSCTL0 IE bit has completed conversion. This bit is cleared by
setting the IN30 bit in the ADCISC register.

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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008

This register controls whether the sample sequencer raw interrupt signals are promoted to controller
interrupts. Each raw interrupt signal can be masked independently.

ADC Interrupt Mask (ADCIM)

Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MASK3 MASK2 MASK1 MASK0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 MASK3 R/W 0 SS3 Interrupt Mask

When set, this bit allows the raw interrupt signal from Sample Sequencer
3 (ADCRIS register INR3 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 3 does not affect the SS3
interrupt status.

2 MASK2 R/W 0 SS2 Interrupt Mask

When set, this bit allows the raw interrupt signal from Sample Sequencer
2 (ADCRIS register INR2 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 2 does not affect the SS2
interrupt status.

1 MASK1 R/W 0 SS1 Interrupt Mask

When set, this bit allows the raw interrupt signal from Sample Sequencer
1 (ADCRIS register INR1 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 1 does not affect the SS1
interrupt status.

0 MASK0 R/W 0 SS0 Interrupt Mask

When set, this bit allows the raw interrupt signal from Sample Sequencer
0 (ADCRIS register INR0 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 0 does not affect the SS0
interrupt status.

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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C

This register provides the mechanism for clearing sample sequence interrupt conditions and shows
the status of controller interrupts generated by the sample sequencers. When read, each bit field
is the logical AND of the respective INR and MASK bits. Sample sequence nterrupts are cleared by
setting the corresponding bit position. If software is polling the ADCRIS instead of generating
interrupts, the sample sequence INR bits are still cleared via the ADCISC register, even if the IN
bit is not set.

ADC Interrupt Status and Clear (ADCISC)

Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IN3 IN2 IN1 IN0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 IN3 R/W1C 0 SS3 Interrupt Status and Clear

This bit is set when both the INR3 bit in the ADCRIS register and the
MASK3 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit.

2 IN2 R/W1C 0 SS2 Interrupt Status and Clear

This bit is set when both the INR2 bit in the ADCRIS register and the
MASK2 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit.

1 IN1 R/W1C 0 SS1 Interrupt Status and Clear

This bit is set when both the INR1 bit in the ADCRIS register and the
MASK1 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR1
bit.

0 IN0 R/W1C 0 SS0 Interrupt Status and Clear

This bit is set when both the INR0 bit in the ADCRIS register and the
MASK0 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR0
bit.

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Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010

This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.

ADC Overflow Status (ADCOSTAT)

Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OV3 OV2 OV1 OV0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 OV3 R/W1C 0 SS3 FIFO Overflow

When set, this bit specifies that the FIFO for Sample Sequencer 3 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.

2 OV2 R/W1C 0 SS2 FIFO Overflow

When set, this bit specifies that the FIFO for Sample Sequencer 2 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.

1 OV1 R/W1C 0 SS1 FIFO Overflow

When set, this bit specifies that the FIFO for Sample Sequencer 1 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.

0 OV0 R/W1C 0 SS0 FIFO Overflow

When set, this bit specifies that the FIFO for Sample Sequencer 0 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.

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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014

The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each
sample sequencer can be configured with a unique trigger source.

ADC Event Multiplexer Select (ADCEMUX)

Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EM3 EM2 EM1 EM0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:12 EM3 R/W 0x0 SS3 Trigger Select

This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:

Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 352).
0x6 PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 584.
0x7 PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 584.
0x8 PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 584.
0x9-0xE reserved
0xF Always (continuously sample)

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Bit/Field Name Type Reset Description

11:8 EM2 R/W 0x0 SS2 Trigger Select

This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:

Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 352).
0x6 PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 584.
0x7 PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 584.
0x8 PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 584.
0x9-0xE reserved
0xF Always (continuously sample)

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Bit/Field Name Type Reset Description

7:4 EM1 R/W 0x0 SS1 Trigger Select

This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:

Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 352).
0x6 PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 584.
0x7 PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 584.
0x8 PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 584.
0x9-0xE reserved
0xF Always (continuously sample)

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Bit/Field Name Type Reset Description

3:0 EM0 R/W 0x0 SS0 Trigger Select

This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:

Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 352).
0x6 PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 584.
0x7 PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 584.
0x8 PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 584.
0x9-0xE reserved
0xF Always (continuously sample)

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Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018

This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.

ADC Underflow Status (ADCUSTAT)

Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved UV3 UV2 UV1 UV0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 UV3 R/W1C 0 SS3 FIFO Underflow

When set, this bit specifies that the FIFO for Sample Sequencer 3 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.

2 UV2 R/W1C 0 SS2 FIFO Underflow

When set, this bit specifies that the FIFO for Sample Sequencer 2 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.

1 UV1 R/W1C 0 SS1 FIFO Underflow

When set, this bit specifies that the FIFO for Sample Sequencer 1 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.

0 UV0 R/W1C 0 SS0 FIFO Underflow

When set, this bit specifies that the FIFO for Sample Sequencer 0 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.

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Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020

This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the
highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities,
each sequence must have a unique priority for the ADC to operate properly.

ADC Sample Sequencer Priority (ADCSSPRI)

Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SS3 reserved SS2 reserved SS1 reserved SS0

Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W

Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0

Bit/Field Name Type Reset Description

31:14 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13:12 SS3 R/W 0x3 SS3 Priority

This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.

11:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9:8 SS2 R/W 0x2 SS2 Priority

This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.

7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:4 SS1 R/W 0x1 SS1 Priority

This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.

3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

1:0 SS0 R/W 0x0 SS0 Priority

This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.

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Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028

This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.

ADC Processor Sample Sequence Initiate (ADCPSSI)

Base 0x4003.8000
Offset 0x028
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SS3 SS2 SS1 SS0

Type RO RO RO RO RO RO RO RO RO RO RO RO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 - - - -

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 SS3 WO - SS3 Initiate

When set, this bit triggers sampling on Sample Sequencer 3 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.

2 SS2 WO - SS2 Initiate

When set, this bit triggers sampling on Sample Sequencer 2 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.

1 SS1 WO - SS1 Initiate

When set, this bit triggers sampling on Sample Sequencer 1 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.

0 SS0 WO - SS0 Initiate

When set, this bit triggers sampling on Sample Sequencer 0 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.

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Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030

This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.

ADC Sample Averaging Control (ADCSAC)

Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved AVG

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 AVG R/W 0x0 Hardware Averaging Control

Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.

Value Description
0x0 No hardware oversampling
0x1 2x hardware oversampling
0x2 4x hardware oversampling
0x3 8x hardware oversampling
0x4 16x hardware oversampling
0x5 32x hardware oversampling
0x6 64x hardware oversampling
0x7 Reserved

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Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),

offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible
samples.

ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)

Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4

Type RO R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0

Type RO R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

30:28 MUX7 R/W 0x0 8th Sample Input Select

The MUX7 field is used during the eighth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.

27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

26:24 MUX6 R/W 0x0 7th Sample Input Select

The MUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.

23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

22:20 MUX5 R/W 0x0 6th Sample Input Select

The MUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.

19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Bit/Field Name Type Reset Description

18:16 MUX4 R/W 0x0 5th Sample Input Select

The MUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.

15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14:12 MUX3 R/W 0x0 4th Sample Input Select

The MUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.

11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10:8 MUX2 R/W 0x0 3rd Sample Input Select

The MUX72 field is used during the third sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:4 MUX1 R/W 0x0 2nd Sample Input Select

The MUX1 field is used during the second sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 MUX0 R/W 0x0 1st Sample Input Select

The MUX0 field is used during the first sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.

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Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044

This register contains the configuration information for each sample for a sequence executed with
a sample sequencer. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between. This register is 32-bits
wide and contains information for eight possible samples.

ADC Sample Sequence Control 0 (ADCSSCTL0)

Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31 TS7 R/W 0 8th Sample Temp Sensor Select

This bit is used during the eighth sample of the sample sequence and
and specifies the input source of the sample.
When set, the temperature sensor is read.
When clear, the input pin specified by the ADCSSMUX register is read.

30 IE7 R/W 0 8th Sample Interrupt Enable

This bit is used during the eighth sample of the sample sequence and
specifies whether the raw interrupt signal (INR0 bit) is asserted at the
end of the sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted.
When this bit is clear, the raw interrupt is not asserted.
It is legal to have multiple samples within a sequence generate interrupts.

29 END7 R/W 0 8th Sample is End of Sequence

The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.

28 D7 R/W 0 8th Sample Diff Input Select

The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". The temperature sensor
does not have a differential option. When set, the analog inputs are
differentially sampled.

27 TS6 R/W 0 7th Sample Temp Sensor Select

Same definition as TS7 but used during the seventh sample.

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Bit/Field Name Type Reset Description

26 IE6 R/W 0 7th Sample Interrupt Enable

Same definition as IE7 but used during the seventh sample.

25 END6 R/W 0 7th Sample is End of Sequence

Same definition as END7 but used during the seventh sample.

24 D6 R/W 0 7th Sample Diff Input Select

Same definition as D7 but used during the seventh sample.

23 TS5 R/W 0 6th Sample Temp Sensor Select

Same definition as TS7 but used during the sixth sample.

22 IE5 R/W 0 6th Sample Interrupt Enable

Same definition as IE7 but used during the sixth sample.

21 END5 R/W 0 6th Sample is End of Sequence

Same definition as END7 but used during the sixth sample.

20 D5 R/W 0 6th Sample Diff Input Select

Same definition as D7 but used during the sixth sample.

19 TS4 R/W 0 5th Sample Temp Sensor Select

Same definition as TS7 but used during the fifth sample.

18 IE4 R/W 0 5th Sample Interrupt Enable

Same definition as IE7 but used during the fifth sample.

17 END4 R/W 0 5th Sample is End of Sequence

Same definition as END7 but used during the fifth sample.

16 D4 R/W 0 5th Sample Diff Input Select

Same definition as D7 but used during the fifth sample.

15 TS3 R/W 0 4th Sample Temp Sensor Select

Same definition as TS7 but used during the fourth sample.

14 IE3 R/W 0 4th Sample Interrupt Enable

Same definition as IE7 but used during the fourth sample.

13 END3 R/W 0 4th Sample is End of Sequence

Same definition as END7 but used during the fourth sample.

12 D3 R/W 0 4th Sample Diff Input Select

Same definition as D7 but used during the fourth sample.

11 TS2 R/W 0 3rd Sample Temp Sensor Select

Same definition as TS7 but used during the third sample.

10 IE2 R/W 0 3rd Sample Interrupt Enable

Same definition as IE7 but used during the third sample.

9 END2 R/W 0 3rd Sample is End of Sequence

Same definition as END7 but used during the third sample.

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Bit/Field Name Type Reset Description

8 D2 R/W 0 3rd Sample Diff Input Select

Same definition as D7 but used during the third sample.

7 TS1 R/W 0 2nd Sample Temp Sensor Select

Same definition as TS7 but used during the second sample.

6 IE1 R/W 0 2nd Sample Interrupt Enable

Same definition as IE7 but used during the second sample.

5 END1 R/W 0 2nd Sample is End of Sequence

Same definition as END7 but used during the second sample.

4 D1 R/W 0 2nd Sample Diff Input Select

Same definition as D7 but used during the second sample.

3 TS0 R/W 0 1st Sample Temp Sensor Select

Same definition as TS7 but used during the first sample.

2 IE0 R/W 0 1st Sample Interrupt Enable

Same definition as IE7 but used during the first sample.

1 END0 R/W 0 1st Sample is End of Sequence

Same definition as END7 but used during the first sample.

0 D0 R/W 0 1st Sample Diff Input Select

Same definition as D7 but used during the first sample.

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Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
Important: This register is read-sensitive. See the register description for details.

This register contains the conversion results for samples collected with the sample sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.

ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)

Base 0x4003.8000
Offset 0x048
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATA

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -

Bit/Field Name Type Reset Description

31:10 reserved RO - Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9:0 DATA RO - Conversion Result Data

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Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset

0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the sample sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIFO0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.

ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)

Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FULL reserved EMPTY HPTR TPTR

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:13 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 FULL RO 0 FIFO Full

When set, this bit indicates that the FIFO is currently full.

11:9 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

8 EMPTY RO 1 FIFO Empty

When set, this bit indicates that the FIFO is currently empty.

7:4 HPTR RO 0x0 FIFO Head Pointer

This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.

3:0 TPTR RO 0x0 FIFO Tail Pointer

This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.

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Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),

offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 419 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.

ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)

Base 0x4003.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0

Type RO R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:15 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

14:12 MUX3 R/W 0x0 4th Sample Input Select

11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10:8 MUX2 R/W 0x0 3rd Sample Input Select

7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:4 MUX1 R/W 0x0 2nd Sample Input Select

3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 MUX0 R/W 0x0 1st Sample Input Select

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Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064

Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. These registers
are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0 register
on page 421 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer
1 and the ADCSSCTL2 register configures Sample Sequencer 2.

ADC Sample Sequence Control 1 (ADCSSCTL1)

Base 0x4003.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15 TS3 R/W 0 4th Sample Temp Sensor Select

Same definition as TS7 but used during the fourth sample.

14 IE3 R/W 0 4th Sample Interrupt Enable

Same definition as IE7 but used during the fourth sample.

13 END3 R/W 0 4th Sample is End of Sequence

Same definition as END7 but used during the fourth sample.

12 D3 R/W 0 4th Sample Diff Input Select

Same definition as D7 but used during the fourth sample.

11 TS2 R/W 0 3rd Sample Temp Sensor Select

Same definition as TS7 but used during the third sample.

10 IE2 R/W 0 3rd Sample Interrupt Enable

Same definition as IE7 but used during the third sample.

9 END2 R/W 0 3rd Sample is End of Sequence

Same definition as END7 but used during the third sample.

8 D2 R/W 0 3rd Sample Diff Input Select

Same definition as D7 but used during the third sample.

7 TS1 R/W 0 2nd Sample Temp Sensor Select

Same definition as TS7 but used during the second sample.

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Bit/Field Name Type Reset Description

6 IE1 R/W 0 2nd Sample Interrupt Enable

Same definition as IE7 but used during the second sample.

5 END1 R/W 0 2nd Sample is End of Sequence

Same definition as END7 but used during the second sample.

4 D1 R/W 0 2nd Sample Diff Input Select

Same definition as D7 but used during the second sample.

3 TS0 R/W 0 1st Sample Temp Sensor Select

Same definition as TS7 but used during the first sample.

2 IE0 R/W 0 1st Sample Interrupt Enable

Same definition as IE7 but used during the first sample.

1 END0 R/W 0 1st Sample is End of Sequence

Same definition as END7 but used during the first sample.

0 D0 R/W 0 1st Sample Diff Input Select

Same definition as D7 but used during the first sample.

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Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),

offset 0x0A0
This register defines the analog input configuration for a sample executed with Sample Sequencer
3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0
register on page 419 for detailed bit descriptions.

ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)

Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MUX0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2:0 MUX0 R/W 0 1st Sample Input Select

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Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4

This register contains the configuration information for a sample executed with Sample Sequencer
3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits
wide and contains information for one possible sample. See the ADCSSCTL0 register on page 421
for detailed bit descriptions.

ADC Sample Sequence Control 3 (ADCSSCTL3)

Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TS0 IE0 END0 D0

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TS0 R/W 0 1st Sample Temp Sensor Select

Same definition as TS7 but used during the first sample.

2 IE0 R/W 0 1st Sample Interrupt Enable

Same definition as IE7 but used during the first sample.

1 END0 R/W 1 1st Sample is End of Sequence

Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.

0 D0 R/W 0 1st Sample Diff Input Select

Same definition as D7 but used during the first sample.

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Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100

This register provides loopback operation within the digital logic of the ADC, which can be useful in
debugging software without having to provide actual analog stimulus. This test mode is entered by
writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode,
the read-only portion of this register is returned.

ADC Test Mode Loopback (ADCTMLB)

Base 0x4003.8000
Offset 0x100
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved LB

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 LB R/W 0 Loopback Mode Enable

When set, forces a loopback within the digital block to provide information
on input and unique numbering. The ADCSSFIFOn registers do not
provide sample data, but instead provide the 10-bit loopback data as
shown below.

Bit/Field Name Description

9:6 CNT Continuous Sample Counter
Continuous sample counter that is initialized to 0
and counts each sample as it processed. This
helps provide a unique value for the data received.
5 CONT Continuation Sample Indicator
When set, indicates that this is a continuation
sample. For example, if two sequencers were to
run back-to-back, this indicates that the controller
kept continuously sampling at full rate.
4 DIFF Differential Sample Indicator
When set, indicates that this is a differential
sample.
3 TS Temp Sensor Sample Indicator
When set, indicates that this is a temperature
sensor sample.
2:0 MUX Analog Input Indicator
Indicates which analog input is to be sampled.

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12 Universal Asynchronous Receivers/Transmitters

(UARTs)
®
Each Stellaris Universal Asynchronous Receiver/Transmitter (UART) has the following features:

■ Three fully programmable 16C550-type UARTs with IrDA support

■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps

■ Programmable FIFO length, including 1-byte deep operation providing conventional

double-buffered interface

■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

■ Standard asynchronous communication bits for start, stop, and parity

■ Line-break generation and detection

■ Fully programmable serial interface characteristics

– 5, 6, 7, or 8 data bits

– Even, odd, stick, or no-parity bit generation/detection

– 1 or 2 stop bit generation

■ IrDA serial-IR (SIR) encoder/decoder providing

– Programmable use of IrDA Serial Infrared (SIR) or UART input/output

– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex

– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations

– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration

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12.1 Block Diagram

Figure 12-1. UART Module Block Diagram

System Clock

Interrupt
Interrupt Control TxFIFO
16 x 8

UARTIFLS
UARTIM .
.
Identification UARTMIS
.
Registers UARTRIS
UARTICR Transmitter
UARTPCellID0 (with SIR UnTx
UARTPCellID1 Transmit
UARTPCellID2 Baud Rate Encoder)
UARTPCellID3 Generator
UARTPeriphID0 UARTDR UARTIBRD
UARTPeriphID1 UARTFBRD Receiver
UARTPeriphID2 (with SIR UnRx
UARTPeriphID3 Receive
UARTPeriphID4 Decoder)
Control/Status RxFIFO
UARTPeriphID5
16 x 8
UARTPeriphID6
UARTPeriphID7
UARTRSR/ECR .
UARTFR .
UARTLCRH .
UARTCTL
UARTILPR

12.2 Signal Description

Table 12-1 on page 433 and Table 12-2 on page 434 list the external signals of the UART module
and describe the function of each. The UART signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default
to the UART function. The column in the table below titled "Pin Assignment" lists the possible GPIO
pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 309) should be set to choose the UART function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286.

Table 12-1. UART Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
U1Rx 12 I TTL UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.

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Table 12-1. UART Signals (100LQFP) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
U1Tx 13 O TTL UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
U2Rx 19 I TTL UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
U2Tx 18 O TTL UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 12-2. UART Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
U1Rx H2 I TTL UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
U1Tx H1 O TTL UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
U2Rx K1 I TTL UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
U2Tx K2 O TTL UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

12.3 Functional Description

Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 453). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.

12.3.1 Transmit/Receive Logic

The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 12-2 on page 435 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.

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Figure 12-2. UART Character Frame

UnTX 1-2
LSB MSB stop bits
1
0 5-8 data bits
n Parity bit
Start if enabled

12.3.2 Baud-Rate Generation

The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 449) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 450). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)

BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)

where UARTSysClk is the system clock connected to the UART.

The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:

UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)

The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 451), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:

■ UARTIBRD write, UARTFBRD write, and UARTLCRH write

■ UARTFBRD write, UARTIBRD write, and UARTLCRH write

■ UARTIBRD write and UARTLCRH write

■ UARTFBRD write and UARTLCRH write

12.3.3 Data Transmission

Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 446) is asserted as soon as

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data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 434).
The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it
is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle
of Baud16 (that is, one bit period later) according to the programmed length of the data characters.
The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the
UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.

12.3.4 Serial IR (SIR)

The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:

■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.

■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 448 for more
information on IrDA low-power pulse-duration configuration.

Figure 12-3 on page 437 shows the UART transmit and receive signals, with and without IrDA
modulation.

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Figure 12-3. IrDA Data Modulation

Start Data bits Stop
bit bit

UnTx 0 1 0 1 0 0 1 1 0 1

UnTx with IrDA

Bit period 3
16 Bit period
UnRx with IrDA

UnRx 0 1 0 1 0 0 1 1 0 1

Start Data bits Stop

In both normal and low-power IrDA modes:

■ During transmission, the UART data bit is used as the base for encoding

■ During reception, the decoded bits are transferred to the UART receive logic

The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal
as an alternate function must be configured as the UnRx signal and pulled High.

12.3.5 FIFO Operation

The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 442). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 451).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 446) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 455). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.

12.3.6 Interrupts
The UART can generate interrupts when the following conditions are observed:

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■ Overrun Error

■ Break Error

■ Parity Error

■ Framing Error

■ Receive Timeout

■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)

■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)

All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 460).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 457) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 459).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 461).
The receive interrupt changes state when one of the following events occurs:

■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.

■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.

The transmit interrupt changes state when one of the following events occurs:

■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.

■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.

12.3.7 Loopback Operation

The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 453). In loopback mode,
data transmitted on UnTx is received on the UnRx input.

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12.3.8 IrDA SIR block

The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.

12.4 Initialization and Configuration

To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2
bits in the RCGC1 register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:

■ 115200 baud rate

■ Data length of 8 bits

■ One stop bit

■ No parity

■ FIFOs disabled

■ No interrupts

The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 435, the BRD can be calculated:

BRD = 20,000,000 / (16 * 115,200) = 10.8507

which means that the DIVINT field of the UARTIBRD register (see page 449) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 450) is calculated by the equation:

UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54

With the BRD values in hand, the UART configuration is written to the module in the following order:

1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.

2. Write the integer portion of the BRD to the UARTIBRD register.

3. Write the fractional portion of the BRD to the UARTFBRD register.

4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).

5. Enable the UART by setting the UARTEN bit in the UARTCTL register.

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12.5 Register Map

Table 12-3 on page 440 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:

■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000

Note that the UART module clock must be enabled before the registers can be programmed (see
page 219). There must be a delay of 3 system clocks after the UART module clock is enabled before
any UART module registers are accessed.
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 453)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.

Table 12-3. UART Register Map

See
Offset Name Type Reset Description
page

0x000 UARTDR R/W 0x0000.0000 UART Data 442

0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 444

0x018 UARTFR RO 0x0000.0090 UART Flag 446

0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 448

0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 449

0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 450

0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 451

0x030 UARTCTL R/W 0x0000.0300 UART Control 453

0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 455

0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 457

0x03C UARTRIS RO 0x0000.0000 UART Raw Interrupt Status 459

0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 460

0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 461

0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 463

0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 464

0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 465

0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 466

0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 467

0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 468

0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 469

0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 470

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Table 12-3. UART Register Map (continued)

See
Offset Name Type Reset Description
page

0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 471

0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 472

0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 473

0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 474

12.6 Register Descriptions

The remainder of this section lists and describes the UART registers, in numerical order by address
offset.

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Register 1: UART Data (UARTDR), offset 0x000

Important: This register is read-sensitive. See the register description for details.

This register is the data register (the interface to the FIFOs).

When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.

UART Data (UARTDR)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OE BE PE FE DATA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11 OE RO 0 UART Overrun Error

The OE values are defined as follows:

Value Description
0 There has been no data loss due to a FIFO overrun.
1 New data was received when the FIFO was full, resulting in
data loss.

10 BE RO 0 UART Break Error

This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.

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Bit/Field Name Type Reset Description

9 PE RO 0 UART Parity Error

This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.

8 FE RO 0 UART Framing Error

This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).

7:0 DATA R/W 0 Data Transmitted or Received

When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.

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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset

0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.

Reads

UART Receive Status/Error Clear (UARTRSR/UARTECR)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OE BE PE FE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 OE RO 0 UART Overrun Error

When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.

2 BE RO 0 UART Break Error

This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.

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Bit/Field Name Type Reset Description

1 PE RO 0 UART Parity Error

This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.

0 FE RO 0 UART Framing Error

This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.

Writes

UART Receive Status/Error Clear (UARTRSR/UARTECR)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATA

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved WO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DATA WO 0 Error Clear

A write to this register of any data clears the framing, parity, break, and
overrun flags.

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Register 3: UART Flag (UARTFR), offset 0x018

The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.

UART Flag (UARTFR)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TXFE RXFF TXFF RXFE BUSY reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 TXFE RO 1 UART Transmit FIFO Empty

The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.

6 RXFF RO 0 UART Receive FIFO Full

The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.

5 TXFF RO 0 UART Transmit FIFO Full

The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.

4 RXFE RO 1 UART Receive FIFO Empty

The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.

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Bit/Field Name Type Reset Description

3 BUSY RO 0 UART Busy

When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).

2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020

The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:

ILPDVSR = SysClk / FIrLPBaud16

where FIrLPBaud16 is nominally 1.8432 MHz.

You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.

UART IrDA Low-Power Register (UARTILPR)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ILPDVSR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 ILPDVSR R/W 0x00 IrDA Low-Power Divisor

This is an 8-bit low-power divisor value.

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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024

The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 435
for configuration details.

UART Integer Baud-Rate Divisor (UARTIBRD)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIVINT

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor

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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028

The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 435
for configuration details.

UART Fractional Baud-Rate Divisor (UARTFBRD)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x028
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DIVFRAC

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor

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Register 7: UART Line Control (UARTLCRH), offset 0x02C

The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.

UART Line Control (UARTLCRH)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SPS WLEN FEN STP2 EPS PEN BRK

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 SPS R/W 0 UART Stick Parity Select

When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.

6:5 WLEN R/W 0 UART Word Length

The bits indicate the number of data bits transmitted or received in a
frame as follows:

Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)

4 FEN R/W 0 UART Enable FIFOs

If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.

3 STP2 R/W 0 UART Two Stop Bits Select

If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.

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Bit/Field Name Type Reset Description

2 EPS R/W 0 UART Even Parity Select

If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.

1 PEN R/W 0 UART Parity Enable

If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.

0 BRK R/W 0 UART Send Break

If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.

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Register 8: UART Control (UARTCTL), offset 0x030

The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.

1. Disable the UART.

2. Wait for the end of transmission or reception of the current character.

3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).

4. Reprogram the control register.

5. Enable the UART.

UART Control (UARTCTL)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RXE TXE LBE reserved SIRLP SIREN UARTEN

Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 RXE R/W 1 UART Receive Enable

If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.

Note: To enable reception, the UARTEN bit must also be set.

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Bit/Field Name Type Reset Description

8 TXE R/W 1 UART Transmit Enable

If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.

Note: To enable transmission, the UARTEN bit must also be set.

7 LBE R/W 0 UART Loop Back Enable

If this bit is set to 1, the UnTX path is fed through the UnRX path.

6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 SIRLP R/W 0 UART SIR Low Power Mode

This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 448 for more
information.

1 SIREN R/W 0 UART SIR Enable

If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.

0 UARTEN R/W 0 UART Enable

If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.

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Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034

The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.

UART Interrupt FIFO Level Select (UARTIFLS)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x034
Type R/W, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RXIFLSEL TXIFLSEL

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5:3 RXIFLSEL R/W 0x2 UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:

Value Description
0x0 RX FIFO ≥ ⅛ full
0x1 RX FIFO ≥ ¼ full
0x2 RX FIFO ≥ ½ full (default)
0x3 RX FIFO ≥ ¾ full
0x4 RX FIFO ≥ ⅞ full
0x5-0x7 Reserved

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Bit/Field Name Type Reset Description

2:0 TXIFLSEL R/W 0x2 UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:

Value Description
0x0 TX FIFO ≤ ⅞ empty
0x1 TX FIFO ≤ ¾ empty
0x2 TX FIFO ≤ ½ empty (default)
0x3 TX FIFO ≤ ¼ empty
0x4 TX FIFO ≤ ⅛ empty
0x5-0x7 Reserved

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Register 10: UART Interrupt Mask (UARTIM), offset 0x038

The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.

UART Interrupt Mask (UARTIM)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved

Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 OEIM R/W 0 UART Overrun Error Interrupt Mask

On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.

9 BEIM R/W 0 UART Break Error Interrupt Mask

On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.

8 PEIM R/W 0 UART Parity Error Interrupt Mask

On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.

7 FEIM R/W 0 UART Framing Error Interrupt Mask

On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.

6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask

On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.

5 TXIM R/W 0 UART Transmit Interrupt Mask

On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.

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Bit/Field Name Type Reset Description

4 RXIM R/W 0 UART Receive Interrupt Mask

On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.

3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C

The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.

UART Raw Interrupt Status (UARTRIS)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 OERIS RO 0 UART Overrun Error Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

9 BERIS RO 0 UART Break Error Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

8 PERIS RO 0 UART Parity Error Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

7 FERIS RO 0 UART Framing Error Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

5 TXRIS RO 0 UART Transmit Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

4 RXRIS RO 0 UART Receive Raw Interrupt Status

Gives the raw interrupt state (prior to masking) of this interrupt.

3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040

The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.

UART Masked Interrupt Status (UARTMIS)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

9 BEMIS RO 0 UART Break Error Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

8 PEMIS RO 0 UART Parity Error Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

7 FEMIS RO 0 UART Framing Error Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

5 TXMIS RO 0 UART Transmit Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

4 RXMIS RO 0 UART Receive Masked Interrupt Status

Gives the masked interrupt state of this interrupt.

3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 13: UART Interrupt Clear (UARTICR), offset 0x044

The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.

UART Interrupt Clear (UARTICR)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved

Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

10 OEIC W1C 0 Overrun Error Interrupt Clear

The OEIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

9 BEIC W1C 0 Break Error Interrupt Clear

The BEIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

8 PEIC W1C 0 Parity Error Interrupt Clear

The PEIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

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Bit/Field Name Type Reset Description

7 FEIC W1C 0 Framing Error Interrupt Clear

The FEIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

6 RTIC W1C 0 Receive Time-Out Interrupt Clear

The RTIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

5 TXIC W1C 0 Transmit Interrupt Clear

The TXIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

4 RXIC W1C 0 Receive Interrupt Clear

The RXIC values are defined as follows:

Value Description
0 No effect on the interrupt.
1 Clears interrupt.

3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 4 (UARTPeriphID4)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID4

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID4 RO 0x0000 UART Peripheral ID Register[7:0]

Can be used by software to identify the presence of this peripheral.

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Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 5 (UARTPeriphID5)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID5

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID5 RO 0x0000 UART Peripheral ID Register[15:8]

Can be used by software to identify the presence of this peripheral.

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Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 6 (UARTPeriphID6)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID6

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID6 RO 0x0000 UART Peripheral ID Register[23:16]

Can be used by software to identify the presence of this peripheral.

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Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 7 (UARTPeriphID7)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID7

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID7 RO 0x0000 UART Peripheral ID Register[31:24]

Can be used by software to identify the presence of this peripheral.

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Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 0 (UARTPeriphID0)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE0
Type RO, reset 0x0000.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID0 RO 0x11 UART Peripheral ID Register[7:0]

Can be used by software to identify the presence of this peripheral.

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Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 1 (UARTPeriphID1)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID1 RO 0x00 UART Peripheral ID Register[15:8]

Can be used by software to identify the presence of this peripheral.

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Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 2 (UARTPeriphID2)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID2 RO 0x18 UART Peripheral ID Register[23:16]

Can be used by software to identify the presence of this peripheral.

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Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC

The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.

UART Peripheral Identification 3 (UARTPeriphID3)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID3 RO 0x01 UART Peripheral ID Register[31:24]

Can be used by software to identify the presence of this peripheral.

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Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0

The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.

UART PrimeCell Identification 0 (UARTPCellID0)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID0 RO 0x0D UART PrimeCell ID Register[7:0]

Provides software a standard cross-peripheral identification system.

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Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4

The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.

UART PrimeCell Identification 1 (UARTPCellID1)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID1 RO 0xF0 UART PrimeCell ID Register[15:8]

Provides software a standard cross-peripheral identification system.

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Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8

The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.

UART PrimeCell Identification 2 (UARTPCellID2)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID2 RO 0x05 UART PrimeCell ID Register[23:16]

Provides software a standard cross-peripheral identification system.

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Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC

The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.

UART PrimeCell Identification 3 (UARTPCellID3)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID3 RO 0xB1 UART PrimeCell ID Register[31:24]

Provides software a standard cross-peripheral identification system.

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13 Synchronous Serial Interface (SSI)

®
The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI
is a master or slave interface for synchronous serial communication with peripheral devices that
have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
Each Stellaris SSI module has the following features:

■ Two SSI modules, each with the following features:

■ Master or slave operation

■ Programmable clock bit rate and prescale

■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments

synchronous serial interfaces

■ Programmable data frame size from 4 to 16 bits

■ Internal loopback test mode for diagnostic/debug testing

13.1 Block Diagram

Figure 13-1. SSI Module Block Diagram
Interrupt
Interrupt Control

SSIIM TxFIFO
SSIMIS 8 x16
Control/ Status SSIRIS
.
SSIICR .
SSICR0
.
SSICR1 SSITx
SSISR
SSIRx
SSIDR Transmit /
Receive SSIClk
RxFIFO Logic
8 x16
SSIFss
System Clock .
Clock .
Prescaler .
Identification
Registers SSICPSR
SSIPCellID0 SSIPeriphID0 SSIPeriphID 4
SSIPCellID1 SSIPeriphID 1 SSIPeriphID 5
SSIPCellID2 SSIPeriphID 2 SSIPeriphID 6
SSIPCellID3 SSIPeriphID 3 SSIPeriphID7

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13.2 Signal Description

Table 13-1 on page 476 and Table 13-2 on page 476 list the external signals of the SSI module and
describe the function of each. The SSI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and
SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 309) should be set to choose the SSI function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286.

Table 13-1. SSI Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
SSI0Clk 28 I/O TTL SSI module 0 clock.
SSI0Fss 29 I/O TTL SSI module 0 frame signal.
SSI0Rx 30 I TTL SSI module 0 receive.
SSI0Tx 31 O TTL SSI module 0 transmit.
SSI1Clk 72 I/O TTL SSI module 1 clock.
SSI1Fss 73 I/O TTL SSI module 1 frame signal.
SSI1Rx 74 I TTL SSI module 1 receive.
SSI1Tx 75 O TTL SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 13-2. SSI Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
SSI0Clk M4 I/O TTL SSI module 0 clock.
SSI0Fss L4 I/O TTL SSI module 0 frame signal.
SSI0Rx L5 I TTL SSI module 0 receive.
SSI0Tx M5 O TTL SSI module 0 transmit.
SSI1Clk A11 I/O TTL SSI module 1 clock.
SSI1Fss B12 I/O TTL SSI module 1 frame signal.
SSI1Rx B11 I TTL SSI module 1 receive.
SSI1Tx A12 O TTL SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

13.3 Functional Description

The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.

13.3.1 Bit Rate Generation

The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale

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(SSICPSR) register (see page 495). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 488).
The frequency of the output clock SSIClk is defined by:

SSIClk = FSysClk / (CPSDVSR * (1 + SCR))

Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 664 to view SSI timing parameters.

13.3.2 FIFO Operation

13.3.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 492), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
when the FIFO is empty.

13.3.2.2 Receive FIFO

The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.

13.3.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:

■ Transmit FIFO service

■ Receive FIFO service

■ Receive FIFO time-out

■ Receive FIFO overrun

All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 496). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and

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receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 498 and page 499, respectively).

13.3.4 Frame Formats

Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:

■ Texas Instruments synchronous serial

■ Freescale SPI

■ MICROWIRE

For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.

13.3.4.1 Texas Instruments Synchronous Serial Frame Format

Figure 13-2 on page 478 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.

Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer)

SSIClk

SSIFss

SSITx/SSIRx MSB LSB

4 to 16 bits

In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is

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pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 13-3 on page 479 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.

Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer)

SSIClk

SSIFss

SSITx/SSIRx MSB LSB

4 to 16 bits

13.3.4.2 Freescale SPI Frame Format

The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.

SPO Clock Polarity Bit

When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.

SPH Phase Control Bit

The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.

13.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0

Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 13-4 on page 480 and Figure 13-5 on page 480.

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Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0

SSIClk

SSIFss

SSIRx MSB LSB Q

4 to 16 bits

SSITx MSB LSB

Note: Q is undefined.

Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0

SSIClk

SSIFss

SSIRx LSB MSB LSB MSB

4 to16 bits

SSITx LSB MSB LSB MSB

In this configuration, during idle periods:

■ SSIClk is forced Low

■ SSIFss is forced High

■ The transmit data line SSITx is arbitrarily forced Low

■ When the SSI is configured as a master, it enables the SSIClk pad

■ When the SSI is configured as a slave, it disables the SSIClk pad

If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to

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enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.

13.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1

The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
13-6 on page 481, which covers both single and continuous transfers.

Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1

SSIClk

SSIFss

SSIRx Q Q
MSB LSB Q
4 to 16 bits
SSITx MSB LSB

Note: Q is undefined.

In this configuration, during idle periods:

■ SSIClk is forced Low

■ SSIFss is forced High

■ The transmit data line SSITx is arbitrarily forced Low

■ When the SSI is configured as a master, it enables the SSIClk pad

■ When the SSI is configured as a slave, it disables the SSIClk pad

If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.

13.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0

Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 13-7 on page 482 and Figure 13-8 on page 482.

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Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0

SSIClk

SSIFss

SSIRx MSB LSB Q

4 to 16 bits

SSITx MSB LSB

Note: Q is undefined.

Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0

SSIClk

SSIFss

SSITx/SSIRx LSB MSB LSB MSB

4 to 16 bits

In this configuration, during idle periods:

■ SSIClk is forced High

■ SSIFss is forced High

■ The transmit data line SSITx is arbitrarily forced Low

■ When the SSI is configured as a master, it enables the SSIClk pad

■ When the SSI is configured as a slave, it disables the SSIClk pad

If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.

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13.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1

The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
13-9 on page 483, which covers both single and continuous transfers.

Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1

SSIClk

SSIFss

SSIRx Q MSB LSB Q

4 to 16 bits

SSITx MSB LSB

Note: Q is undefined.

In this configuration, during idle periods:

■ SSIClk is forced High

■ SSIFss is forced High

■ The transmit data line SSITx is arbitrarily forced Low

■ When the SSI is configured as a master, it enables the SSIClk pad

■ When the SSI is configured as a slave, it disables the SSIClk pad

If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.

13.3.4.7 MICROWIRE Frame Format

Figure 13-10 on page 484 shows the MICROWIRE frame format, again for a single frame. Figure
13-11 on page 485 shows the same format when back-to-back frames are transmitted.

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Figure 13-10. MICROWIRE Frame Format (Single Frame)

SSIClk

SSIFss

SSITx MSB LSB

8-bit control
SSIRx 0 MSB LSB
4 to 16 bits
output data

MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:

■ SSIClk is forced Low

■ SSIFss is forced High

■ The transmit data line SSITx is arbitrarily forced Low

A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.

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Figure 13-11. MICROWIRE Frame Format (Continuous Transfer)

SSIClk

SSIFss

SSITx LSB MSB LSB

8-bit control

SSIRx 0 MSB LSB MSB

4 to 16 bits
output data

In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 13-12 on page 485 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.

Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements

tSetup=(2*tSSIClk)

tHold=tSSIClk

SSIClk

SSIFss

SSIRx

First RX data to be
sampled by SSI slave

13.4 Initialization and Configuration

To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:

1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.

2. Select whether the SSI is a master or slave:

a. For master operations, set the SSICR1 register to 0x0000.0000.

b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.

c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.

3. Configure the clock prescale divisor by writing the SSICPSR register.

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4. Write the SSICR0 register with the following configuration:

■ Serial clock rate (SCR)

■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)

■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)

■ The data size (DSS)

5. Enable the SSI by setting the SSE bit in the SSICR1 register.

As an example, assume the SSI must be configured to operate with the following parameters:

■ Master operation

■ Freescale SPI mode (SPO=1, SPH=1)

■ 1 Mbps bit rate

■ 8 data bits

Assuming the system clock is 20 MHz, the bit rate calculation would be:

FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))

1x106 = 20x106 / (CPSDVSR * (1 + SCR))

In this case, if CPSDVSR=2, SCR must be 9.

The configuration sequence would be as follows:

1. Ensure that the SSE bit in the SSICR1 register is disabled.

2. Write the SSICR1 register with a value of 0x0000.0000.

3. Write the SSICPSR register with a value of 0x0000.0002.

4. Write the SSICR0 register with a value of 0x0000.09C7.

5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.

13.5 Register Map

Table 13-3 on page 487 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:

■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000

Note that the SSI module clock must be enabled before the registers can be programmed (see
page 219). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.

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Table 13-3. SSI Register Map

See
Offset Name Type Reset Description
page

0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 488

0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 490

0x008 SSIDR R/W 0x0000.0000 SSI Data 492

0x00C SSISR RO 0x0000.0003 SSI Status 493

0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 495

0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 496

0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 498

0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 499

0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 500

0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 501

0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 502

0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 503

0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 504

0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 505

0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 506

0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 507

0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 508

0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 509

0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 510

0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 511

0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 512

13.6 Register Descriptions

The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.

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Register 1: SSI Control 0 (SSICR0), offset 0x000

SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.

SSI Control 0 (SSICR0)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCR SPH SPO FRF DSS

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:8 SCR R/W 0x0000 SSI Serial Clock Rate

The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:

BR=FSSIClk/(CPSDVSR * (1 + SCR))

where CPSDVSR is an even value from 2-254 programmed in the

SSICPSR register, and SCR is a value from 0-255.

7 SPH R/W 0 SSI Serial Clock Phase

This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.

6 SPO R/W 0 SSI Serial Clock Polarity

This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.

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Bit/Field Name Type Reset Description

5:4 FRF R/W 0x0 SSI Frame Format Select

The FRF values are defined as follows:

Value Frame Format

0x0 Freescale SPI Frame Format
0x1 Texas Instruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved

3:0 DSS R/W 0x00 SSI Data Size Select

The DSS values are defined as follows:

Value Data Size

0x0-0x2 Reserved
0x3 4-bit data
0x4 5-bit data
0x5 6-bit data
0x6 7-bit data
0x7 8-bit data
0x8 9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data

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Register 2: SSI Control 1 (SSICR1), offset 0x004

SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.

SSI Control 1 (SSICR1)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SOD MS SSE LBM

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 SOD R/W 0 SSI Slave Mode Output Disable

This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:

Value Description
0 SSI can drive SSITx output in Slave Output mode.
1 SSI must not drive the SSITx output in Slave mode.

2 MS R/W 0 SSI Master/Slave Select

This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:

Value Description
0 Device configured as a master.
1 Device configured as a slave.

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Bit/Field Name Type Reset Description

1 SSE R/W 0 SSI Synchronous Serial Port Enable

Setting this bit enables SSI operation.
The SSE values are defined as follows:

Value Description
0 SSI operation disabled.
1 SSI operation enabled.

Note: This bit must be set to 0 before any control registers

are reprogrammed.

0 LBM R/W 0 SSI Loopback Mode

Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:

Value Description
0 Normal serial port operation enabled.
1 Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.

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Register 3: SSI Data (SSIDR), offset 0x008

Important: This register is read-sensitive. See the register description for details.

SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.

SSI Data (SSIDR)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 DATA R/W 0x0000 SSI Receive/Transmit Data

A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.

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Register 4: SSI Status (SSISR), offset 0x00C

SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.

SSI Status (SSISR)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BSY RFF RNE TNF TFE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:5 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 BSY RO 0 SSI Busy Bit

The BSY values are defined as follows:

Value Description
0 SSI is idle.
1 SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.

3 RFF RO 0 SSI Receive FIFO Full

The RFF values are defined as follows:

Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.

2 RNE RO 0 SSI Receive FIFO Not Empty

The RNE values are defined as follows:

Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.

1 TNF RO 1 SSI Transmit FIFO Not Full

The TNF values are defined as follows:

Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.

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Bit/Field Name Type Reset Description

0 TFE R0 1 SSI Transmit FIFO Empty

The TFE values are defined as follows:

Value Description
0 Transmit FIFO is not empty.
1 Transmit FIFO is empty.

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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010

SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.

SSI Clock Prescale (SSICPSR)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CPSDVSR

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CPSDVSR R/W 0x00 SSI Clock Prescale Divisor

This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.

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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014

The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.

SSI Interrupt Mask (SSIIM)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TXIM RXIM RTIM RORIM

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask

The TXIM values are defined as follows:

Value Description
0 TX FIFO half-empty or less condition interrupt is masked.
1 TX FIFO half-empty or less condition interrupt is not masked.

2 RXIM R/W 0 SSI Receive FIFO Interrupt Mask

The RXIM values are defined as follows:

Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.

1 RTIM R/W 0 SSI Receive Time-Out Interrupt Mask

The RTIM values are defined as follows:

Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.

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Bit/Field Name Type Reset Description

0 RORIM R/W 0 SSI Receive Overrun Interrupt Mask

The RORIM values are defined as follows:

Value Description
0 RX FIFO overrun interrupt is masked.
1 RX FIFO overrun interrupt is not masked.

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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018

The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.

SSI Raw Interrupt Status (SSIRIS)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
Type RO, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TXRIS RXRIS RTRIS RORRIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status

Indicates that the transmit FIFO is half empty or less, when set.

2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status

Indicates that the receive FIFO is half full or more, when set.

1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status

Indicates that the receive time-out has occurred, when set.

0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status

Indicates that the receive FIFO has overflowed, when set.

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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C

The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.

SSI Masked Interrupt Status (SSIMIS)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TXMIS RXMIS RTMIS RORMIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status

Indicates that the transmit FIFO is half empty or less, when set.

2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status

Indicates that the receive FIFO is half full or more, when set.

1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status

Indicates that the receive time-out has occurred, when set.

0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status

Indicates that the receive FIFO has overflowed, when set.

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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020

The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.

SSI Interrupt Clear (SSIICR)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RTIC RORIC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear

The RTIC values are defined as follows:

Value Description
0 No effect on interrupt.
1 Clears interrupt.

0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear

The RORIC values are defined as follows:

Value Description
0 No effect on interrupt.
1 Clears interrupt.

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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 4 (SSIPeriphID4)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID4

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID4 RO 0x00 SSI Peripheral ID Register[7:0]

Can be used by software to identify the presence of this peripheral.

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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 5 (SSIPeriphID5)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID5

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID5 RO 0x00 SSI Peripheral ID Register[15:8]

Can be used by software to identify the presence of this peripheral.

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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 6 (SSIPeriphID6)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID6

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID6 RO 0x00 SSI Peripheral ID Register[23:16]

Can be used by software to identify the presence of this peripheral.

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Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 7 (SSIPeriphID7)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID7

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID7 RO 0x00 SSI Peripheral ID Register[31:24]

Can be used by software to identify the presence of this peripheral.

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Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 0 (SSIPeriphID0)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
Type RO, reset 0x0000.0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID0 RO 0x22 SSI Peripheral ID Register[7:0]

Can be used by software to identify the presence of this peripheral.

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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 1 (SSIPeriphID1)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID1 RO 0x00 SSI Peripheral ID Register [15:8]

Can be used by software to identify the presence of this peripheral.

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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 2 (SSIPeriphID2)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID2 RO 0x18 SSI Peripheral ID Register [23:16]

Can be used by software to identify the presence of this peripheral.

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Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.

SSI Peripheral Identification 3 (SSIPeriphID3)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 PID3 RO 0x01 SSI Peripheral ID Register [31:24]

Can be used by software to identify the presence of this peripheral.

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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0

The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.

SSI PrimeCell Identification 0 (SSIPCellID0)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID0 RO 0x0D SSI PrimeCell ID Register [7:0]

Provides software a standard cross-peripheral identification system.

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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4

The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.

SSI PrimeCell Identification 1 (SSIPCellID1)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID1

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID1 RO 0xF0 SSI PrimeCell ID Register [15:8]

Provides software a standard cross-peripheral identification system.

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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8

The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.

SSI PrimeCell Identification 2 (SSIPCellID2)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID2

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID2 RO 0x05 SSI PrimeCell ID Register [23:16]

Provides software a standard cross-peripheral identification system.

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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC

The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.

SSI PrimeCell Identification 3 (SSIPCellID3)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CID3

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 CID3 RO 0xB1 SSI PrimeCell ID Register [31:24]

Provides software a standard cross-peripheral identification system.

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14 Inter-Integrated Circuit (I2C) Interface

The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S1968 microcontroller includes two I2C modules, providing the ability to
interact (both send and receive) with other I2C devices on the bus.
®
The Stellaris I2C interface has the following features:

■ Two I2C modules, each with the following features:

■ Devices on the I2C bus can be designated as either a master or a slave

– Supports both sending and receiving data as either a master or a slave

– Supports simultaneous master and slave operation

■ Four I2C modes

– Master transmit

– Master receive

– Slave transmit

– Slave receive

■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)

■ Master and slave interrupt generation

– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)

– Slave generates interrupts when data has been sent or requested by a master

■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode

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14.1 Block Diagram

Figure 14-1. I2C Block Diagram

I2CSCL
I2C Control

I2CMSA I2CSOAR I2C Master Core

I2CSDA
I2CMCS I2CSCSR
I2CMDR I2CSDR I2CSCL
Interrupt
I2CMTPR I2CSIM I2C I/O Select
I2CMIMR I2CSRIS I2CSDA
I2CMRIS I2CSMIS
I2CSCL
I2CMMIS I2CSICR
I2CMICR I2C Slave Core
I2CSDA
I2CMCR

14.2 Signal Description

Table 14-1 on page 514 and Table 14-2 on page 514 list the external signals of the I2C interface and
describe the function of each. The I2C interface signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which
default to the I2C function. The column in the table below titled "Pin Assignment" lists the possible
GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 309) should be set to choose the I2C function. Note that the I2C pins
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286.

Table 14-1. I2C Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
I2C0SCL 70 I/O OD I2C module 0 clock.
I2C0SDA 71 I/O OD I2C module 0 data.
I2C1SCL 34 I/O OD I2C module 1 clock.
I2C1SDA 35 I/O OD I2C module 1 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 14-2. I2C Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
I2C0SCL C11 I/O OD I2C module 0 clock.
I2C0SDA C12 I/O OD I2C module 0 data.
I2C1SCL L6 I/O OD I2C module 1 clock.
I2C1SDA M6 I/O OD I2C module 1 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

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14.3 Functional Description

Each I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 14-2 on page 515.
See “Inter-Integrated Circuit (I2C) Interface” on page 665 for I2C timing diagrams.

Figure 14-2. I2C Bus Configuration

RPUP RPUP
SCL
SDA I2C Bus

I2CSCL I2CSDA SCL SDA SCL SDA

Stellaris® 3rd Party Device 3rd Party Device

with I2C Interface with I2C Interface

14.3.1 I2C Bus Functional Overview

The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 515) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.

14.3.1.1 START and STOP Conditions

The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
14-3 on page 515.

Figure 14-3. START and STOP Conditions

SDA SDA

SCL SCL
START STOP
condition condition

14.3.1.2 Data Format with 7-Bit Address

Data transfers follow the format shown in Figure 14-4 on page 516. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction

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bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.

Figure 14-4. Complete Data Transfer with a 7-Bit Address

SDA MSB LSB R/S ACK MSB LSB ACK

SCL 1 2 7 8 9 1 2 7 8 9
Slave address Data

The first seven bits of the first byte make up the slave address (see Figure 14-5 on page 516). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.

Figure 14-5. R/S Bit in First Byte

MSB LSB
R/S

Slave address

14.3.1.3 Data Validity

The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 14-6 on page 516).

Figure 14-6. Data Validity During Bit Transfer on the I2C Bus

SDA

SCL
Data line Change
stable of data
allowed

14.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 516.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end

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of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.

14.3.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.

14.3.2 Available Speed Modes

The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 535).
The I2C clock period is calculated as follows:

SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD

For example:

CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4

yields a SCL frequency of:

1/T = 333 Khz

Table 14-3 on page 517 gives examples of timer period, system clock, and speed mode (Standard
or Fast).

Table 14-3. Examples of I2C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 MHz 0x01 100 Kbps - -
6 MHz 0x02 100 Kbps - -
12.5 MHz 0x06 89 Kbps 0x01 312 Kbps
16.7 MHz 0x08 93 Kbps 0x02 278 Kbps
20 MHz 0x09 100 Kbps 0x02 333 Kbps

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Table 14-3. Examples of I2C Master Timer Period versus Speed Mode (continued)
System Clock Timer Period Standard Mode Timer Period Fast Mode
25 MHz 0x0C 96.2 Kbps 0x03 312 Kbps
33 MHz 0x10 97.1 Kbps 0x04 330 Kbps
40 MHz 0x13 100 Kbps 0x04 400 Kbps
50 MHz 0x18 100 Kbps 0x06 357 Kbps

14.3.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:

■ Master transaction completed

■ Master arbitration lost

■ Master transaction error

■ Slave transaction received

■ Slave transaction requested

There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.

14.3.3.1 I2C Master Interrupts

The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C
master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I2C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.

14.3.3.2 I2C Slave Interrupts

The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register.
Software determines whether the module should write (transmit) or read (receive) data from the I2C
Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit
in the I2C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.

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14.3.4 Loopback Operation

The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.

14.3.5 Command Sequence Flow Charts

This section details the steps required to perform the various I2C transfer types in both master and
slave mode.

14.3.5.1 I2C Master Command Sequences

The figures that follow show the command sequences available for the I2C master.

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Figure 14-7. Master Single SEND

Idle

Write Slave
Address to Sequence
I2CMSA may be
omitted in a
Single Master
system
Write data to
I2CMDR

Read I2CMCS

NO
BUSBSY bit=0?

YES

Write ---0-111 to
I2CMCS

Read I2CMCS

NO
BUSY bit=0?

YES

NO
Error Service ERROR bit=0?

YES

Idle

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Figure 14-8. Master Single RECEIVE

Idle

Sequence may be
Write Slave omitted in a Single
Address to Master system
I2CMSA

Read I2CMCS

NO
BUSBSY bit=0?

YES

Write ---00111 to
I2CMCS

Read I2CMCS

NO
BUSY bit=0?

YES

NO
Error Service ERROR bit=0?

YES

Read data from

I2CMDR

Idle

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Figure 14-9. Master Burst SEND

Idle

Write Slave Sequence

Address to may be Read I2CMCS
I2CMSA omitted in a
Single Master
system
Write data to
I2CMDR NO
BUSY bit=0?

YES
Read I2CMCS

NO
ERROR bit=0?

NO
BUSBSY bit=0?
YES

NO
Write data to ARBLST bit=1?
YES
I2CMDR

Write ---0-011 to YES

I2CMCS
Write ---0-100 to
Write ---0-001 to NO I2CMCS
Index=n?
I2CMCS

YES
Error Service

Write ---0-101 to
I2CMCS
Idle

Read I2CMCS

NO
BUSY bit=0?

YES

NO
Error Service ERROR bit=0?

YES

Idle

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Figure 14-10. Master Burst RECEIVE

Idle

Sequence
may be
Write Slave omitted in a
Address to Single Master Read I2CMCS
I2CMSA system

Read I2CMCS BUSY bit=0? NO

YES

NO
BUSBSY bit=0?
NO
ERROR bit=0?

YES

NO
Write ---01011 to Read data from ARBLST bit=1?
I2CMCS I2CMDR

YES
Write ---0-100 to
Write ---01001 to NO
I2CMCS
Index=m-1?
I2CMCS

Error Service
YES

Write ---00101 to
I2CMCS
Idle

Read I2CMCS

NO
BUSY bit=0?

YES

NO
ERROR bit=0?

YES

Read data from

Error Service
I2CMDR

Idle

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Figure 14-11. Master Burst RECEIVE after Burst SEND

Idle

Master operates in
Master Transmit mode

STOP condition is not

generated

Write Slave
Address to
I2CMSA

Write ---01011 to
I2CMCS

Repeated START
condition is generated
with changing data
Master operates in direction
Master Receive mode

Idle

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Figure 14-12. Master Burst SEND after Burst RECEIVE

Idle

Master operates in
Master Receive mode

STOP condition is not

generated

Write Slave
Address to
I2CMSA

Write ---0-011 to
I2CMCS

Repeated START
condition is generated
with changing data
Master operates in direction
Master Transmit mode

Idle

14.3.5.2 I2C Slave Command Sequences

Figure 14-13 on page 526 presents the command sequence available for the I2C slave.

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Figure 14-13. Slave Command Sequence

Idle

Write OWN Slave

Address to
I2CSOAR

Write -------1 to
I2CSCSR

Read I2CSCSR

NO NO
TREQ bit=1? RREQ bit=1?

FBR is
YES also valid YES

Write data to Read data from

I2CSDR I2CSDR

14.4 Initialization and Configuration

The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.

1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.

2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.

3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.

4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.

5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:

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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;

TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9

Write the I2CMTPR register with the value of 0x0000.0009.

6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.

7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.

8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).

9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.

14.5 Register Map

Table 14-4 on page 527 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:

■ I2C 0: 0x4002.0000
■ I2C 1: 0x4002.1000

Note that the I2C module clock must be enabled before the registers can be programmed (see
page 219). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
®
The hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare
uses an offset between 0x000 and 0x018 with the slave base address.

Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map

See
Offset Name Type Reset Description
page

I2C Master

0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 529

0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 530

0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 534

0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 535

0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 536

0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 537

0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 538

0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 539

0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 540

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Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued)

See
Offset Name Type Reset Description
page

I2C Slave

0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 542

0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 543

0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 545

0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 546

0x810 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 547

0x814 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 548

0x818 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 549

14.6 Register Descriptions (I2C Master)

The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 541.

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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000

This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).

I2C Master Slave Address (I2CMSA)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SA R/S

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:1 SA R/W 0 I2C Slave Address

This field specifies bits A6 through A0 of the slave address.

0 R/S R/W 0 Receive/Send

The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).

Value Description
0 Send.
1 Receive.

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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004

This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.

Reads

I2C Master Control/Status (I2CMCS)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 BUSBSY RO 0 Bus Busy

This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.

5 IDLE RO 0 I2C Idle

This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.

4 ARBLST RO 0 Arbitration Lost

This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.

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Bit/Field Name Type Reset Description

3 DATACK RO 0 Acknowledge Data

This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.

2 ADRACK RO 0 Acknowledge Address

This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.

1 ERROR RO 0 Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.

0 BUSY RO 0 I2C Busy

This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.

Writes

I2C Master Control/Status (I2CMCS)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ACK STOP START RUN

Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved WO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 ACK WO 0 Data Acknowledge Enable

When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 14-5 on page 532.

2 STOP WO 0 Generate STOP

When set, causes the generation of the STOP condition. See field
decoding in Table 14-5 on page 532.

1 START WO 0 Generate START

When set, causes the generation of a START or repeated START
condition. See field decoding in Table 14-5 on page 532.

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Bit/Field Name Type Reset Description

0 RUN WO 0 I2C Master Enable

When set, allows the master to send or receive data. See field decoding
in Table 14-5 on page 532.

Table 14-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)

Current I2CMSA[0] I2CMCS[3:0]
Description
State R/S ACK STOP START RUN
a
0 X 0 1 1 START condition followed by SEND (master goes to the
Master Transmit state).
0 X 1 1 1 START condition followed by a SEND and STOP
condition (master remains in Idle state).
1 0 0 1 1 START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
Idle
1 0 1 1 1 START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1 1 0 1 1 START condition followed by RECEIVE (master goes
to the Master Receive state).
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
X X 0 0 1 SEND operation (master remains in Master Transmit
state).
X X 1 0 0 STOP condition (master goes to Idle state).
X X 1 0 1 SEND followed by STOP condition (master goes to Idle
state).
0 X 0 1 1 Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0 X 1 1 1 Repeated START condition followed by SEND and STOP
Master condition (master goes to Idle state).
Transmit 1 0 0 1 1 Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 0 1 1 1 Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1 1 0 1 1 Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.

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Table 14-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued)
Current I2CMSA[0] I2CMCS[3:0]
Description
State R/S ACK STOP START RUN
X 0 0 0 1 RECEIVE operation with negative ACK (master remains
in Master Receive state).
b
X X 1 0 0 STOP condition (master goes to Idle state).
X 0 1 0 1 RECEIVE followed by STOP condition (master goes to
Idle state).
X 1 0 0 1 RECEIVE operation (master remains in Master Receive
state).
X 1 1 0 1 Illegal.
1 0 0 1 1 Repeated START condition followed by RECEIVE
Master operation with a negative ACK (master remains in Master
Receive Receive state).
1 0 1 1 1 Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1 1 0 1 1 Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
0 X 0 1 1 Repeated START condition followed by SEND (master
goes to Master Transmit state).
0 X 1 1 1 Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.

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Register 3: I2C Master Data (I2CMDR), offset 0x008

Important: This register is read-sensitive. See the register description for details.

This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.

I2C Master Data (I2CMDR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DATA R/W 0x00 Data Transferred

Data transferred during transaction.

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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C

This register specifies the period of the SCL clock.

Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur.

I2C Master Timer Period (I2CMTPR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x00C
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TPR

Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:0 TPR R/W 0x1 SCL Clock Period

This field specifies the period of the SCL clock.

SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD

where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).

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Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010

This register controls whether a raw interrupt is promoted to a controller interrupt.

I2C Master Interrupt Mask (I2CMIMR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 IM R/W 0 Interrupt Mask

This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.

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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014

This register specifies whether an interrupt is pending.

I2C Master Raw Interrupt Status (I2CMRIS)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 RIS RO 0 Raw Interrupt Status

This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.

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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018

This register specifies whether an interrupt was signaled.

I2C Master Masked Interrupt Status (I2CMMIS)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved MIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 MIS RO 0 Masked Interrupt Status

This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.

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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C

This register clears the raw interrupt.

I2C Master Interrupt Clear (I2CMICR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x01C
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 IC WO 0 Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.

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Register 9: I2C Master Configuration (I2CMCR), offset 0x020

This register configures the mode (Master or Slave) and sets the interface for test mode loopback.

I2C Master Configuration (I2CMCR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SFE MFE reserved LPBK

Type RO RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 SFE R/W 0 I2C Slave Function Enable

This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.

4 MFE R/W 0 I2C Master Function Enable

This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.

3:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 LPBK R/W 0 I2C Loopback

This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.

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14.7 Register Descriptions (I2C Slave)

The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 528.

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Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800

This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.

I2C Slave Own Address (I2CSOAR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x800
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OAR

Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6:0 OAR R/W 0x00 I2C Slave Own Address

This field specifies bits A6 through A0 of the slave address.

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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804

This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and
receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that
the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the
I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into
the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I2C slave operation.

Reads

I2C Slave Control/Status (I2CSCSR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x804
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FBR TREQ RREQ

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 FBR RO 0 First Byte Received

Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.

Note: This bit is not used for slave transmit operations.

1 TREQ RO 0 Transmit Request

This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.

0 RREQ RO 0 Receive Request

This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.

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Writes

I2C Slave Control/Status (I2CSCSR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x804
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DA

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 DA WO 0 Device Active

Value Description
0 Disables the I2C slave operation.
1 Enables the I2C slave operation.

Once this bit has been set, it should not be set again unless it has been
cleared by writing a 0 or by a reset, otherwise transfer failures may
occur.

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Register 12: I2C Slave Data (I2CSDR), offset 0x808

Important: This register is read-sensitive. See the register description for details.

This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.

I2C Slave Data (I2CSDR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x808
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DATA R/W 0x0 Data for Transfer

This field contains the data for transfer during a slave receive or transmit
operation.

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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C

This register controls whether a raw interrupt is promoted to a controller interrupt.

I2C Slave Interrupt Mask (I2CSIMR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x80C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATAIM

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 DATAIM R/W 0 Data Interrupt Mask

This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.

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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.

I2C Slave Raw Interrupt Status (I2CSRIS)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x810
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATARIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 DATARIS RO 0 Data Raw Interrupt Status

This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I2C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.

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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.

I2C Slave Masked Interrupt Status (I2CSMIS)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x814
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATAMIS

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 DATAMIS RO 0 Data Masked Interrupt Status

This bit specifies the interrupt state for data received and data requested
(after masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.

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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818

This register clears the raw interrupt. A read of this register returns no meaningful data.

I2C Slave Interrupt Clear (I2CSICR)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x818
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATAIC

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 DATAIC WO 0 Data Interrupt Clear

This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.

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15 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
Note: Not all comparators have the option to drive an output pin.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
®
The Stellaris Analog Comparators module has the following features:

■ Three independent integrated analog comparators

■ Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample
sequence

■ Compare external pin input to external pin input or to internal programmable voltage reference

■ Compare a test voltage against any one of these voltages

– An individual external reference voltage

– A shared single external reference voltage

– A shared internal reference voltage

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15.1 Block Diagram

Figure 15-1. Analog Comparator Module Block Diagram
C2- -ve input
Comparator 2
C2+ +ve input
output <none>
+ve input (alternate)
ACCTL2 trigger trigger
ACSTAT2 interrupt
reference input

C1- -ve input

Comparator 1
C1+ +ve input
output <none>
+ve input (alternate)
ACCTL1 trigger trigger
ACSTAT1 interrupt
reference input

C0- -ve input

Comparator 0
C0+ +ve input
output C0o
+ve input (alternate)
ACCTL0 trigger trigger
ACSTAT0 interrupt
reference input

Voltage Interrupt Control

Ref
ACRIS
internal ACREFCTL
bus ACMIS

ACINTEN

interrupt

15.2 Signal Description

Table 15-1 on page 551 and Table 15-2 on page 552 list the external signals of the Analog Comparators
and describe the function of each. The Analog Comparator output signals are alternate functions
for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled
"Pin Assignment" lists the possible GPIO pin placements for the Analog Comparator signals. The
AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 309) should be set
to choose the Analog Comparator function. The positive and negative input signals are configured
by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286.

Table 15-1. Analog Comparators Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
C0+ 90 I Analog Analog comparator 0 positive input.
C0- 92 I Analog Analog comparator 0 negative input.
C0o 58 O TTL Analog comparator 0 output.
C1+ 24 I Analog Analog comparator 1 positive input.
C1- 91 I Analog Analog comparator 1 negative input.

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Table 15-1. Analog Comparators Signals (100LQFP) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
C2+ 23 I Analog Analog comparator 2 positive input.
C2- 22 I Analog Analog comparator 2 negative input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 15-2. Analog Comparators Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
C0+ A7 I Analog Analog comparator 0 positive input.
C0- A6 I Analog Analog comparator 0 negative input.
C0o L9 O TTL Analog comparator 0 output.
C1+ M1 I Analog Analog comparator 1 positive input.
C1- B7 I Analog Analog comparator 1 negative input.
C2+ M2 I Analog Analog comparator 2 positive input.
C2- L2 I Analog Analog comparator 2 negative input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

15.3 Functional Description

Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.

The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.

VIN- < VIN+, VOUT = 1

VIN- > VIN+, VOUT = 0

As shown in Figure 15-2 on page 552, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.

Figure 15-2. Structure of Comparator Unit

- ve input
0 output
+ ve input

1 CINV
+ ve input (alternate) IntGen

2 TrigGen
reference input

ACCTL ACSTAT
internal
bus

interrupt
trigger

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A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS, ACRIS, and ACINTEN).
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin or generate an analog-to-digital converter (ADC) trigger.

Important: The ASRCP bits in the ACCTLn register must be set before using the analog
comparators.

15.3.1 Internal Reference Programming

The structure of the internal reference is shown in Figure 15-3 on page 553. This is controlled by a
single configuration register (ACREFCTL). Table 15-3 on page 553 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.

Figure 15-3. Comparator Internal Reference Structure

8R
AVDD
8R R R R
•••

EN
15 14 1 0
••• internal
reference
VREF Decoder

RNG

Table 15-3. Internal Reference Voltage and ACREFCTL Field Values

ACREFCTL Register
Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
EN=0 RNG=X 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and
VREF=0 for the least noisy ground reference.

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Table 15-3. Internal Reference Voltage and ACREFCTL Field Values (continued)
ACREFCTL Register
Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
RNG=0 Total resistance in ladder is 31 R.

The range of internal reference in this mode is 0.85-2.448 V.

EN=1
RNG=1 Total resistance in ladder is 23 R.

The range of internal reference for this mode is 0-2.152 V.

15.4 Initialization and Configuration

The following example shows how to configure an analog comparator to read back its output value
from an internal register.

1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.

2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.

3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.

4. Configure comparator 0 to use the internal voltage reference and to not invert the output by
writing the ACCTL0 register with the value of 0x0000.040C.

5. Delay for some time.

6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.

Change the level of the signal input on C0- to see the OVAL value change.

15.5 Register Map

Table 15-4 on page 555 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
Note that the analog comparator module clock must be enabled before the registers can be
programmed (see page 219). There must be a delay of 3 system clocks after the ADC module clock
is enabled before any ADC module registers are accessed.

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Table 15-4. Analog Comparators Register Map

See
Offset Name Type Reset Description
page

0x000 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 556

0x004 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 557

0x008 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 558

0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 559

0x020 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 560

0x024 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 561

0x040 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 560

0x044 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 561

0x060 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 560

0x064 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 561

15.6 Register Descriptions

The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.

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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000

This register provides a summary of the interrupt status (masked) of the comparator.

Analog Comparator Masked Interrupt Status (ACMIS)

Base 0x4003.C000
Offset 0x000
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IN2 IN1 IN0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 IN2 R/W1C 0 Comparator 2 Masked Interrupt Status

Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.

1 IN1 R/W1C 0 Comparator 1 Masked Interrupt Status

Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.

0 IN0 R/W1C 0 Comparator 0 Masked Interrupt Status

Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.

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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004

This register provides a summary of the interrupt status (raw) of the comparator.

Analog Comparator Raw Interrupt Status (ACRIS)

Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IN2 IN1 IN0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 IN2 RO 0 Comparator 2 Interrupt Status

When set, indicates that an interrupt has been generated by comparator
2.

1 IN1 RO 0 Comparator 1 Interrupt Status

When set, indicates that an interrupt has been generated by comparator
1.

0 IN0 RO 0 Comparator 0 Interrupt Status

When set, indicates that an interrupt has been generated by comparator
0.

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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008

This register provides the interrupt enable for the comparator.

Analog Comparator Interrupt Enable (ACINTEN)

Base 0x4003.C000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IN2 IN1 IN0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 IN2 R/W 0 Comparator 2 Interrupt Enable

When set, enables the controller interrupt from the comparator 2 output

1 IN1 R/W 0 Comparator 1 Interrupt Enable

When set, enables the controller interrupt from the comparator 1 output.

0 IN0 R/W 0 Comparator 0 Interrupt Enable

When set, enables the controller interrupt from the comparator 0 output.

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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset

0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.

Analog Comparator Reference Voltage Control (ACREFCTL)

Base 0x4003.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved EN RNG reserved VREF

Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:10 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

9 EN R/W 0 Resistor Ladder Enable

The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.

8 RNG R/W 0 Resistor Ladder Range

The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 31 R. If 1, the resistor ladder has a total
resistance of 23 R.

7:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3:0 VREF R/W 0x00 Resistor Ladder Voltage Ref

The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
15-3 on page 553 for some output reference voltage examples.

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 Analog Comparators

Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020

Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060
These registers specify the current output value of the comparator.

Analog Comparator Status 0 (ACSTAT0)

Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved OVAL reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 OVAL RO 0 Comparator Output Value

The OVAL bit specifies the current output value of the comparator.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024

Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064
These registers configure the comparator’s input and output.

Analog Comparator Control 0 (ACCTL0)

Base 0x4003.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TOEN ASRCP reserved TSLVAL TSEN ISLVAL ISEN CINV reserved

Type RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11 TOEN R/W 0 Trigger Output Enable

The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.

10:9 ASRCP R/W 0x00 Analog Source Positive

The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:

Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved

8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 TSLVAL R/W 0 Trigger Sense Level Value

The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.

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Bit/Field Name Type Reset Description

6:5 TSEN R/W 0x0 Trigger Sense

The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:

Value Function
0x0 Level sense, see TSLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge

4 ISLVAL R/W 0 Interrupt Sense Level Value

The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.

3:2 ISEN R/W 0x0 Interrupt Sense

The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:

Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge

1 CINV R/W 0 Comparator Output Invert

The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.

0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

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16 Pulse Width Modulator (PWM)

Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
®
The Stellaris PWM module consists of three PWM generator blocks and a control block. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals
(other than being based on the same timer and therefore having the same frequency) or a single
pair of complementary signals with dead-band delays inserted. The output of the PWM generation
blocks are managed by the output control block before being passed to the device pins.
The Stellaris PWM module provides a great deal of flexibility. It can generate simple PWM signals,
such as those required by a simple charge pump. It can also generate paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver. Three generator blocks can
also generate the full six channels of gate controls required by a 3-phase inverter bridge.
Each Stellaris PWM module has the following features:

■ Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM
signal generator, a dead-band generator, and an interrupt/ADC-trigger selector

■ One fault input in hardware to promote low-latency shutdown

■ One 16-bit counter

– Runs in Down or Up/Down mode

– Output frequency controlled by a 16-bit load value

– Load value updates can be synchronized

– Produces output signals at zero and load value

■ Two PWM comparators

– Comparator value updates can be synchronized

– Produces output signals on match

■ PWM generator

– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals

– Produces two independent PWM signals

■ Dead-band generator

– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge

– Can be bypassed, leaving input PWM signals unmodified

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■ Flexible output control block with PWM output enable of each PWM signal

– PWM output enable of each PWM signal

– Optional output inversion of each PWM signal (polarity control)

– Optional fault handling for each PWM signal

– Synchronization of timers in the PWM generator blocks

– Interrupt status summary of the PWM generator blocks

■ Can initiate an ADC sample sequence

16.1 Block Diagram

Figure 16-1 on page 564 provides the Stellaris PWM module unit diagram and Figure 16-2 on page 565
provides a more detailed diagram of a Stellaris PWM generator. The LM3S1968 controller contains
three generator blocks (PWM0, PWM1, and PWM2) and generates six independent PWM signals
or three paired PWM signals with dead-band delays inserted.

Figure 16-1. PWM Unit Diagram

PWM Clock
PWM0_A
Fault PWM 0
PWM PWM0_B
System Clock Generator 0 PWM 1
Control and PWM0_Fault

Status
PWMCTL PWM
PWMSYNC PWM1_A
PWM 2
PWMSTATUS Output
PWM PWM1_B
Generator 1 PWM 3
PWM1_Fault Control

Logic
Interrupt
PWM2_A
PWM 4
PWMINTEN
Interrupts PWM PWM2_B
PWMRIS
Generator 2 PWM 5
PWMISC PWM2_Fault

Triggers

Output

PWMENABLE
PWMINVERT
PWMFAULT

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Figure 16-2. PWM Module Block Diagram

PWM Generator Block

Interrupts /
Triggers Interrupt and Fault
Trigger Condition
Generator Fault(s)
Control PWMnFLTSRC0
PWMnINTEN PWMnMINFLTPER
PWMnCTL PWMnRIS PWMnFLTSEN
PWMnISC PWMnFLTSTAT0

Timer zero
load PWMn_Fault
dir
PWMnLOAD
PWMnCOUNT

Dead-Band
Signal PWMn_A
Generator
Comparators Generator
PWMnDBCTL PWMn_B
cmp A
PWMnCMPA PWMnGENA PWMnDBRISE
PWM Clock cmp B
PWMnCMPB PWMnGENB PWMnDBFALL

16.2 Signal Description

Table 16-1 on page 565 and Table 16-2 on page 565 list the external signals of the PWM module and
describe the function of each. The PWM controller signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for these PWM signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 309) should be set to choose the PWM function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286.

Table 16-1. PWM Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
Fault 83 I TTL PWM Fault.
PWM0 17 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PWM1 11 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PWM2 86 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PWM3 85 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PWM4 60 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PWM5 59 O TTL PWM 5. This signal is controlled by PWM Generator 2.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 16-2. PWM Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
Fault D10 I TTL PWM Fault.
PWM0 J1 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PWM1 G2 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PWM2 C9 O TTL PWM 2. This signal is controlled by PWM Generator 1.

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Table 16-2. PWM Signals (108BGA) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PWM3 C8 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PWM4 J11 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PWM5 J12 O TTL PWM 5. This signal is controlled by PWM Generator 2.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

16.3 Functional Description

16.3.1 PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse.

16.3.2 PWM Comparators

There are two comparators in each PWM generator that monitor the value of the counter; when
either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down
mode, these comparators match both when counting up and when counting down; they are therefore
qualified by the counter direction signal. These qualified pulses are used in the PWM generation
process. If either comparator match value is greater than the counter load value, then that comparator
never outputs a High pulse.
Figure 16-3 on page 567 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 16-4 on page 567 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode.

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Figure 16-3. PWM Count-Down Mode

Load

CompA

CompB

Zero

Load
Zero
A
B
Dir

BDown
ADown

Figure 16-4. PWM Count-Up/Down Mode

Load

CompA

CompB

Zero

Load

Zero

Dir

BUp BDown
AUp ADown

16.3.3 PWM Signal Generator

The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM
signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load,
match A down, and match B down. In Count-Up/Down mode, there are six events that can affect
the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match
A or match B events are ignored when they coincide with the zero or load events. If the match A
and match B events coincide, the first signal, PWMA, is generated based only on the match A event,
and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 16-5 on page 568 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.

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Figure 16-5. PWM Generation Example In Count-Up/Down Mode

Load

CompA

CompB

Zero

PWMA

PWMB

In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.

16.3.4 Dead-Band Generator

The two PWM signals produced by the PWM generator are passed to the dead-band generator. If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal
is the input signal with the rising edge delayed by a programmable amount. The second output
PWM signal is the inversion of the input signal with a programmable delay added between the falling
edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a programmable
amount of time at transitions where both are Low. These signals are therefore suitable for driving
a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the
power electronics. Figure 16-6 on page 568 shows the effect of the dead-band generator on an input
PWM signal.

Figure 16-6. PWM Dead-Band Generator

Input

PWMA

PWMB

Rising Edge Falling Edge

Delay Delay

16.3.5 Interrupt/ADC-Trigger Selector

The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
within the PWM signal. Note that interrupts and ADC triggers are based on the raw events; delays
in the PWM signal edges caused by the dead-band generator are not taken into account.

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16.3.6 Synchronization Methods

There is a global reset capability that can synchronously reset any or all of the counters in the PWM
generators. If multiple PWM generators are configured with the same counter load value, this can
be used to guarantee that they also have the same count value (this does imply that the PWM
generators must be configured before they are synchronized). With this, more than two PWM signals
can be produced with a known relationship between the edges of those signals since the counters
always have the same values.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly
short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global synchronized
update signal is asserted, at which point the new value is used as soon as the counter reaches
zero. This second mode allows multiple items in multiple PWM generators to be updated
simultaneously without odd effects during the update; everything runs from the old values until a
point at which they all run from the new values. The Update mode of the load and comparator match
values can be individually configured in each PWM generator block. It typically makes sense to use
the synchronous update mechanism across PWM generator blocks when the timers in those blocks
are synchronized, though this is not required in order for this mechanism to function properly.

16.3.7 Fault Conditions

There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interrupt.
Each PWM generator can also be configured to stop counting during a stall condition. The user can
select for the counters to run until they reach zero then stop, or to continue counting and reloading.
A stall condition does not generate a controller interrupt.

16.3.8 Output Control Block

With each PWM generator block producing two raw PWM signals, the output control block takes
care of the final conditioning of the PWM signals before they go to the pins. Via a single register,
the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for
example, to perform commutation of a brushless DC motor with a single register write (and without
modifying the individual PWM generators, which are modified by the feedback control loop). Similarly,
fault control can disable any of the PWM signals as well. A final inversion can be applied to any of
the PWM signals, making them active Low instead of the default active High.

16.4 Initialization and Configuration

The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes
the system clock is 20 MHz.

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1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module.

2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.

3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.

4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).

5. Configure the PWM generator for countdown mode with immediate updates to the parameters.

■ Write the PWM0CTL register with a value of 0x0000.0000.

■ Write the PWM0GENA register with a value of 0x0000.008C.

■ Write the PWM0GENB register with a value of 0x0000.080C.

6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field
in the PWM0LOAD register to the requested period minus one.

■ Write the PWM0LOAD register with a value of 0x0000.018F.

7. Set the pulse width of the PWM0 pin for a 25% duty cycle.

■ Write the PWM0CMPA register with a value of 0x0000.012B.

8. Set the pulse width of the PWM1 pin for a 75% duty cycle.

■ Write the PWM0CMPB register with a value of 0x0000.0063.

9. Start the timers in PWM generator 0.

■ Write the PWM0CTL register with a value of 0x0000.0001.

10. Enable PWM outputs.

■ Write the PWMENABLE register with a value of 0x0000.0003.

16.5 Register Map

Table 16-3 on page 571 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000. Note that the PWM module
clock must be enabled before the registers can be programmed (see page 213). There must be a
delay of 3 system clocks after the PWM module clock is enabled before any PWM module registers
are accessed.

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Table 16-3. PWM Register Map

See
Offset Name Type Reset Description
page

0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 573

0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 574

0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 575

0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 576

0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 577

0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 578

0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 579

0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 580

0x020 PWMSTATUS RO 0x0000.0000 PWM Status 581

0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 582

0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt and Trigger Enable 584

0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 587

0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 588

0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 589

0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 590

0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 591

0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 592

0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 593

0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 596

0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 599

0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 600

0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 601

0x080 PWM1CTL R/W 0x0000.0000 PWM1 Control 582

0x084 PWM1INTEN R/W 0x0000.0000 PWM1 Interrupt and Trigger Enable 584

0x088 PWM1RIS RO 0x0000.0000 PWM1 Raw Interrupt Status 587

0x08C PWM1ISC R/W1C 0x0000.0000 PWM1 Interrupt Status and Clear 588

0x090 PWM1LOAD R/W 0x0000.0000 PWM1 Load 589

0x094 PWM1COUNT RO 0x0000.0000 PWM1 Counter 590

0x098 PWM1CMPA R/W 0x0000.0000 PWM1 Compare A 591

0x09C PWM1CMPB R/W 0x0000.0000 PWM1 Compare B 592

0x0A0 PWM1GENA R/W 0x0000.0000 PWM1 Generator A Control 593

0x0A4 PWM1GENB R/W 0x0000.0000 PWM1 Generator B Control 596

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Table 16-3. PWM Register Map (continued)

See
Offset Name Type Reset Description
page

0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 599

0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 600

0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 601

0x0C0 PWM2CTL R/W 0x0000.0000 PWM2 Control 582

0x0C4 PWM2INTEN R/W 0x0000.0000 PWM2 Interrupt and Trigger Enable 584

0x0C8 PWM2RIS RO 0x0000.0000 PWM2 Raw Interrupt Status 587

0x0CC PWM2ISC R/W1C 0x0000.0000 PWM2 Interrupt Status and Clear 588

0x0D0 PWM2LOAD R/W 0x0000.0000 PWM2 Load 589

0x0D4 PWM2COUNT RO 0x0000.0000 PWM2 Counter 590

0x0D8 PWM2CMPA R/W 0x0000.0000 PWM2 Compare A 591

0x0DC PWM2CMPB R/W 0x0000.0000 PWM2 Compare B 592

0x0E0 PWM2GENA R/W 0x0000.0000 PWM2 Generator A Control 593

0x0E4 PWM2GENB R/W 0x0000.0000 PWM2 Generator B Control 596

0x0E8 PWM2DBCTL R/W 0x0000.0000 PWM2 Dead-Band Control 599

0x0EC PWM2DBRISE R/W 0x0000.0000 PWM2 Dead-Band Rising-Edge Delay 600

0x0F0 PWM2DBFALL R/W 0x0000.0000 PWM2 Dead-Band Falling-Edge-Delay 601

16.6 Register Descriptions

The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.

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Register 1: PWM Master Control (PWMCTL), offset 0x000

This register provides master control over the PWM generation blocks.

PWM Master Control (PWMCTL)

Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GlobalSync2

GlobalSync1

GlobalSync0
reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 GlobalSync2 R/W 0 Update PWM Generator 2

Same as GlobalSync0 but for PWM generator 2.

1 GlobalSync1 R/W 0 Update PWM Generator 1

Same as GlobalSync0 but for PWM generator 1.

0 GlobalSync0 R/W 0 Update PWM Generator 0

Setting this bit causes any queued update to a load or comparator
register in PWM generator 0 to be applied the next time the
corresponding counter becomes zero. This bit automatically clears when
the updates have completed; it cannot be cleared by software.

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Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004

This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing
multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred;
reading them back as zero indicates that the synchronization has completed.

PWM Time Base Sync (PWMSYNC)

Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved Sync2 Sync1 Sync0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 Sync2 R/W 0 Reset Generator 2 Counter

Performs a reset of the PWM generator 2 counter.

1 Sync1 R/W 0 Reset Generator 1 Counter

Performs a reset of the PWM generator 1 counter.

0 Sync0 R/W 0 Reset Generator 0 Counter

Performs a reset of the PWM generator 0 counter.

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Register 3: PWM Output Enable (PWMENABLE), offset 0x008

This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example, when the time bases
are synchronized) without driving PWM signals to the pins. When bits in this register are set, the
corresponding PWM signal is passed through to the output stage, which is controlled by the
PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is
also passed to the output stage.

PWM Output Enable (PWMENABLE)

Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 PWM5En R/W 0 PWM5 Output Enable

When set, allows the generated PWM5 signal to be passed to the device
pin.

4 PWM4En R/W 0 PWM4 Output Enable

When set, allows the generated PWM4 signal to be passed to the device
pin.

3 PWM3En R/W 0 PWM3 Output Enable

When set, allows the generated PWM3 signal to be passed to the device
pin.

2 PWM2En R/W 0 PWM2 Output Enable

When set, allows the generated PWM2 signal to be passed to the device
pin.

1 PWM1En R/W 0 PWM1 Output Enable

When set, allows the generated PWM1 signal to be passed to the device
pin.

0 PWM0En R/W 0 PWM0 Output Enable

When set, allows the generated PWM0 signal to be passed to the device
pin.

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Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C

This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.

PWM Output Inversion (PWMINVERT)

Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 PWM5Inv R/W 0 Invert PWM5 Signal

When set, the generated PWM5 signal is inverted.

4 PWM4Inv R/W 0 Invert PWM4 Signal

When set, the generated PWM4 signal is inverted.

3 PWM3Inv R/W 0 Invert PWM3 Signal

When set, the generated PWM3 signal is inverted.

2 PWM2Inv R/W 0 Invert PWM2 Signal

When set, the generated PWM2 signal is inverted.

1 PWM1Inv R/W 0 Invert PWM1 Signal

When set, the generated PWM1 signal is inverted.

0 PWM0Inv R/W 0 Invert PWM0 Signal

When set, the generated PWM0 signal is inverted.

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Register 5: PWM Output Fault (PWMFAULT), offset 0x010

This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault inputs and debug events are considered fault conditions. On a fault condition, each PWM signal
can be passed through unmodified or driven Low. For outputs that are configured for pass-through,
the debug event handling on the corresponding PWM generator also determines if the PWM signal
continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).

PWM Output Fault (PWMFAULT)

Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved Fault5 Fault4 Fault3 Fault2 Fault1 Fault0

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 Fault5 R/W 0 PWM5 Fault

When set, the PWM5 output signal is driven Low on a fault condition.

4 Fault4 R/W 0 PWM4 Fault

When set, the PWM4 output signal is driven Low on a fault condition.

3 Fault3 R/W 0 PWM3 Fault

When set, the PWM3 output signal is driven Low on a fault condition.

2 Fault2 R/W 0 PWM2 Fault

When set, the PWM2 output signal is driven Low on a fault condition.

1 Fault1 R/W 0 PWM1 Fault

When set, the PWM1 output signal is driven Low on a fault condition.

0 Fault0 R/W 0 PWM0 Fault

When set, the PWM0 output signal is driven Low on a fault condition.

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Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014

This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.

PWM Interrupt Enable (PWMINTEN)

Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved IntFault

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntPWM2 IntPWM1 IntPWM0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 IntFault R/W 0 Fault Interrupt Enable

When set, an interrupt occurs when the fault input is asserted.

15:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 IntPWM2 R/W 0 PWM2 Interrupt Enable

When set, an interrupt occurs when the PWM generator 2 block asserts
an interrupt.

1 IntPWM1 R/W 0 PWM1 Interrupt Enable

When set, an interrupt occurs when the PWM generator 1 block asserts
an interrupt.

0 IntPWM0 R/W 0 PWM0 Interrupt Enable

When set, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.

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Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018

This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 580).
The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared
via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that
are active; zero bits indicate that the event in question is not active.

PWM Raw Interrupt Status (PWMRIS)

Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved IntFault

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntPWM2 IntPWM1 IntPWM0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 IntFault RO 0 Fault Interrupt Asserted

Indicates that the fault input is asserting.

15:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 IntPWM2 RO 0 PWM2 Interrupt Asserted

Indicates that the PWM generator 2 block is asserting its interrupt.

1 IntPWM1 RO 0 PWM1 Interrupt Asserted

Indicates that the PWM generator 1 block is asserting its interrupt.

0 IntPWM0 RO 0 PWM0 Interrupt Asserted

Indicates that the PWM generator 0 block is asserting its interrupt.

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Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C

This register provides a summary of the interrupt status of the individual PWM generator blocks. A
bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual
interrupt status registers in each block must be consulted to determine the reason for the interrupt,
and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched
interrupt status.

PWM Interrupt Status and Clear (PWMISC)

Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved IntFault

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntPWM2 IntPWM1 IntPWM0

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:17 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

16 IntFault R/W1C 0 Fault Interrupt Asserted

Indicates that the fault input is asserting an interrupt.

15:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

2 IntPWM2 RO 0 PWM2 Interrupt Status

Indicates if the PWM generator 2 block is asserting an interrupt.

1 IntPWM1 RO 0 PWM1 Interrupt Status

Indicates if the PWM generator 1 block is asserting an interrupt.

0 IntPWM0 RO 0 PWM0 Interrupt Status

Indicates if the PWM generator 0 block is asserting an interrupt.

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Register 9: PWM Status (PWMSTATUS), offset 0x020

This register provides the status of the FAULT input signal.

PWM Status (PWMSTATUS)

Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved Fault

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 Fault RO 0 Fault Interrupt Status

When set, indicates the fault input is asserted.

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Register 10: PWM0 Control (PWM0CTL), offset 0x040

Register 11: PWM1 Control (PWM1CTL), offset 0x080
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and
PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs.

PWM0 Control (PWM0CTL)

Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CmpBUpd CmpAUpd LoadUpd Debug Mode Enable

Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 CmpBUpd R/W 0 Comparator B Update Mode

Same as CmpAUpd but for the comparator B register.

4 CmpAUpd R/W 0 Comparator A Update Mode

The Update mode for the comparator A register. When not set, updates
to the register are reflected to the comparator the next time the counter
is 0. When set, updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been requested through
the PWM Master Control (PWMCTL) register (see page 573).

3 LoadUpd R/W 0 Load Register Update Mode

The Update mode for the load register. When not set, updates to the
register are reflected to the counter the next time the counter is 0. When
set, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register.

2 Debug R/W 0 Debug Mode

The behavior of the counter in Debug mode. When not set, the counter
stops running when it next reaches 0, and continues running again when
no longer in Debug mode. When set, the counter always runs.

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Bit/Field Name Type Reset Description

1 Mode R/W 0 Counter Mode

The mode for the counter. When not set, the counter counts down from
the load value to 0 and then wraps back to the load value (Count-Down
mode). When set, the counter counts up from 0 to the load value, back
down to 0, and then repeats (Count-Up/Down mode).

0 Enable R/W 0 PWM Block Enable

Master enable for the PWM generation block. When not set, the entire
block is disabled and not clocked. When set, the block is enabled and
produces PWM signals.

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Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:

■ The counter being equal to the load register

■ The counter being equal to zero

■ The counter being equal to the comparator A register while counting up

■ The counter being equal to the comparator A register while counting down

■ The counter being equal to the comparator B register while counting up

■ The counter being equal to the comparator B register while counting down

Any combination of these events can generate either an interrupt, or an ADC trigger; though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified.

PWM0 Interrupt and Trigger Enable (PWM0INTEN)

Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero reserved IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

Type RO RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:14 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

13 TrCmpBD R/W 0 Trigger for Counter=Comparator B Down

Value Description
1 An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting down.
0 No ADC trigger is output.

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Bit/Field Name Type Reset Description

12 TrCmpBU R/W 0 Trigger for Counter=Comparator B Up

Value Description
1 An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting up.
0 No ADC trigger is output.

11 TrCmpAD R/W 0 Trigger for Counter=Comparator A Down

Value Description
1 An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting down.
0 No ADC trigger is output.

10 TrCmpAU R/W 0 Trigger for Counter=Comparator A Up

Value Description
1 An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting up.
0 No ADC trigger is output.

9 TrCntLoad R/W 0 Trigger for Counter=Load

Value Description
1 An ADC trigger pulse is output when the counter matches the
PWMnLOAD register.
0 No ADC trigger is output.

8 TrCntZero R/W 0 Trigger for Counter=0

Value Description
1 An ADC trigger pulse is output when the counter is 0.
0 No ADC trigger is output.

7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 IntCmpBD R/W 0 Interrupt for Counter=Comparator B Down

Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
0 No interrupt.

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Bit/Field Name Type Reset Description

4 IntCmpBU R/W 0 Interrupt for Counter=Comparator B Up

Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting up.
0 No interrupt.

3 IntCmpAD R/W 0 Interrupt for Counter=Comparator A Down

Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting down.
0 No interrupt.

2 IntCmpAU R/W 0 Interrupt for Counter=Comparator A Up

Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting up.
0 No interrupt.

1 IntCntLoad R/W 0 Interrupt for Counter=Load

Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnLOAD register value.
0 No interrupt.

0 IntCntZero R/W 0 Interrupt for Counter=0

Value Description
1 A raw interrupt occurs when the counter is zero.
0 No interrupt.

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Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048

Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). Bits set to 1 indicate the latched events that have occurred; bits set to 0 indicate
that the event in question has not occurred.

PWM0 Raw Interrupt Status (PWM0RIS)

Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 IntCmpBD RO 0 Comparator B Down Interrupt Status

Indicates that the counter has matched the comparator B value while
counting down.

4 IntCmpBU RO 0 Comparator B Up Interrupt Status

Indicates that the counter has matched the comparator B value while
counting up.

3 IntCmpAD RO 0 Comparator A Down Interrupt Status

Indicates that the counter has matched the comparator A value while
counting down.

2 IntCmpAU RO 0 Comparator A Up Interrupt Status

Indicates that the counter has matched the comparator A value while
counting up.

1 IntCntLoad RO 0 Counter=Load Interrupt Status

Indicates that the counter has matched the PWMnLOAD register.

0 IntCntZero RO 0 Counter=0 Interrupt Status

Indicates that the counter has matched 0.

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Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; bits set to 0 indicate that the event in question has not occurred. These are
R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.

PWM0 Interrupt Status and Clear (PWM0ISC)

Base 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

Type RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

5 IntCmpBD R/W1C 0 Comparator B Down Interrupt

Indicates that the counter has matched the comparator B value while
counting down.

4 IntCmpBU R/W1C 0 Comparator B Up Interrupt

Indicates that the counter has matched the comparator B value while
counting up.

3 IntCmpAD R/W1C 0 Comparator A Down Interrupt

Indicates that the counter has matched the comparator A value while
counting down.

2 IntCmpAU R/W1C 0 Comparator A Up Interrupt

Indicates that the counter has matched the comparator A value while
counting up.

1 IntCntLoad R/W1C 0 Counter=Load Interrupt

Indicates that the counter has matched the PWMnLOAD register.

0 IntCntZero R/W1C 0 Counter=0 Interrupt

Indicates that the counter has matched 0.

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Register 22: PWM0 Load (PWM0LOAD), offset 0x050

Register 23: PWM1 Load (PWM1LOAD), offset 0x090
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter
after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero.
If the Load Value Update mode is immediate, this value is used the next time the counter reaches
zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 573).
If this register is re-written before the actual update occurs, the previous value is never used and is
lost.

PWM0 Load (PWM0LOAD)

Base 0x4002.8000
Offset 0x050
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Load

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 Load R/W 0 Counter Load Value

The counter load value.

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Register 25: PWM0 Counter (PWM0COUNT), offset 0x054

Register 26: PWM1 Counter (PWM1COUNT), offset 0x094
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches the load register, a pulse is output;
this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see
page 593 and page 596) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see
page 584). A pulse with the same capabilities is generated when this value is zero.

PWM0 Counter (PWM0COUNT)

Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Count

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 Count RO 0x00 Counter Value

The current value of the counter.

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Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058

Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register (see page 589), then no pulse is ever output.
If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),
this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 573). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.

PWM0 Compare A (PWM0CMPA)

Base 0x4002.8000
Offset 0x058
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CompA

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 CompA R/W 0x00 Comparator A Value

The value to be compared against the counter.

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Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C

Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register, no pulse is ever output.
If the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL register),
this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 573). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.

PWM0 Compare B (PWM0CMPB)

Base 0x4002.8000
Offset 0x05C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CompB

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

15:0 CompB R/W 0x00 Comparator B Value

The value to be compared against the counter.

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Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060

Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
These registers control the generation of the PWMnA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that
is produced.
The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal;
and PWM2GENA, the PWM2A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.

PWM0 Generator A Control (PWM0GENA)

Base 0x4002.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:10 ActCmpBD R/W 0x0 Action for Comparator B Down

The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

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Bit/Field Name Type Reset Description

9:8 ActCmpBU R/W 0x0 Action for Comparator B Up

The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 582) is set to 1.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

7:6 ActCmpAD R/W 0x0 Action for Comparator A Down

The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

5:4 ActCmpAU R/W 0x0 Action for Comparator A Up

The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

3:2 ActLoad R/W 0x0 Action for Counter=Load

The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

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Bit/Field Name Type Reset Description

1:0 ActZero R/W 0x0 Action for Counter=0

The action to be taken when the counter is zero.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

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Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064

Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
These registers control the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These
events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal;
and PWM2GENB, the PWM2B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.

PWM0 Generator B Control (PWM0GENB)

Base 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:10 ActCmpBD R/W 0x0 Action for Comparator B Down

The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

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Bit/Field Name Type Reset Description

9:8 ActCmpBU R/W 0x0 Action for Comparator B Up

The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

7:6 ActCmpAD R/W 0x0 Action for Comparator A Down

The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

5:4 ActCmpAU R/W 0x0 Action for Comparator A Up

The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

3:2 ActLoad R/W 0x0 Action for Counter=Load

The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

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Bit/Field Name Type Reset Description

1:0 ActZero R/W 0x0 Action for Counter=0

The action to be taken when the counter is 0.
The table below defines the effect of the event on the output signal.

Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.

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Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068

Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1
signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through
to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and
inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by
delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see
page 600), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by
the value in the PWM0DBFALL register (see page 601). In a similar manner, PWM2 and PWM3 are
produced from the PWM1A and PWM1B signals, and PWM4 and PWM5 are produced from the PWM2A
and PWM2B signals.

PWM0 Dead-Band Control (PWM0DBCTL)

Base 0x4002.8000
Offset 0x068
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved Enable

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0 Enable R/W 0 Dead-Band Generator Enable

When set, the dead-band generator inserts dead bands into the output
signals; when clear, it simply passes the PWM signals through.

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Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset

0x06C
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge
delayed.

PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)

Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved RiseDelay

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 RiseDelay R/W 0 Dead-Band Rise Delay

The number of clock ticks to delay the rising edge.

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Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset

0x070
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed and PWM5
is produced from PWM2A with its falling edge delayed.

PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)

Base 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved FallDelay

Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

11:0 FallDelay R/W 0x00 Dead-Band Fall Delay

The number of clock ticks to delay the falling edge.

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17 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The LM3S1968 microcontroller includes two quadrature encoder interface (QEI) modules. Each
QEI module interprets the code produced by a quadrature encoder wheel to integrate position over
time and determine direction of rotation. In addition, it can capture a running estimate of the velocity
of the encoder wheel.
®
Each Stellaris quadrature encoder has the following features:

■ Two QEI modules, each with the following features:

■ Position integrator that tracks the encoder position

■ Velocity capture using built-in timer

■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)

■ Interrupt generation on:

– Index pulse

– Velocity-timer expiration

– Direction change

– Quadrature error detection

17.1 Block Diagram

Figure 17-1 on page 603 provides a block diagram of a Stellaris QEI module.

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Figure 17-1. QEI Block Diagram

QEILOAD

Control & Status Velocity Timer

QEITIME
QEICTL
QEISTAT

Velocity Accumulator
Velocity QEICOUNT
Predivider QEISPEED

clk
PhA QEIMAXPOS
Quadrature
Encoder dir Position Integrator
PhB QEIPOS

IDX

QEIINTEN

Interrupt Control Interrupt

QEIRIS
QEIISC

17.2 Signal Description

Table 17-1 on page 603 and Table 17-2 on page 603 list the external signals of the QEI module and
describe the function of each. The QEI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the
possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 309) should be set to choose the QEI function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 286.

Table 17-1. QEI Signals (100LQFP)

a
Pin Name Pin Number Pin Type Buffer Type Description
IDX0 10 I TTL QEI module 0 index.
IDX1 61 I TTL QEI module 1 index.
PhA0 25 I TTL QEI module 0 phase A.
PhA1 37 I TTL QEI module 1 phase A.
PhB0 47 I TTL QEI module 0 phase B.
PhB1 36 I TTL QEI module 1 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 17-2. QEI Signals (108BGA)

a
Pin Name Pin Number Pin Type Buffer Type Description
IDX0 G1 I TTL QEI module 0 index.
IDX1 H12 I TTL QEI module 1 index.
PhA0 L1 I TTL QEI module 0 phase A.
PhA1 L7 I TTL QEI module 1 phase A.

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Table 17-2. QEI Signals (108BGA) (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PhB0 M9 I TTL QEI module 0 phase B.
PhB1 C10 I TTL QEI module 1 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

17.3 Functional Description

The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA
and PhB, can be swapped before being interpreted by the QEI module to change the meaning of
forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see
page 608).
When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the
capture mode for the position integrator can be set to update the position counter on every edge of
the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on
every PhA and PhB provides more positional resolution at the cost of less range in the positional
counter.
When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB
lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is
seen on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI
Control (QEICTL) register.
When ResMode is 1, the positional counter is reset when the index pulse is sensed. This limits the
positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution
of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse
direction from position 0 can move the position counter to N-1. In this mode, the position register
contains the absolute position of the encoder relative to the index (or home) position once an index
pulse has been seen.
When ResMode is 0, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
The velocity capture has a configurable timer and a count register. It counts the number of phase
edges (using the same configuration as for the position integrator) in a given time period. The edge
count from the previous time period is available to the controller via the QEISPEED register, while
the edge count for the current time period is being accumulated in the QEICOUNT register. As soon
as the current time period is complete, the total number of edges counted in that time period is made
available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and

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counting commences on a new time period. The number of edges counted in a given time period
is directly proportional to the velocity of the encoder.
Figure 17-2 on page 605 shows how the Stellaris quadrature encoder converts the phase input signals
into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode).

Figure 17-2. Quadrature Encoder and Velocity Predivider Operation

PhA
PhB

clk
clkdiv
dir
pos -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
rel +1 +1 +1 +1 +1 +1 +1 +1

The period of the timer is configurable by specifying the load value for the timer in the QEILOAD
register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the
timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer
timer period is needed to be able to capture enough edges to have a meaningful result. At higher
encoder speeds, both a shorter timer period and/or the velocity predivider can be used.
The following equation converts the velocity counter value into an rpm value:

rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges)

where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and
4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
÷1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:

rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm

Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:

rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm

Care must be taken when evaluating this equation since intermediate values may exceed the capacity
of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could
be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if
they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled
by the ÷4 for the edge-count factor.

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Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation, as well as reducing the processing requirement of computing
this equation.

The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a
load value must be selected such that the product is very close to a power of two. For example, a
100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor,
which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the
divide in most cases. If absolute accuracy were required, the controller’s divide instruction could be
used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.

17.4 Initialization and Configuration

The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:

1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module.

2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.

3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.

4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there
are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the
count is zero-based.

■ Write the QEICTL register with the value of 0x0000.0018.

■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.

5. Enable the quadrature encoder by setting bit 0 of the QEICTL register.

6. Delay for some time.

7. Read the encoder position by reading the QEIPOS register value.

17.5 Register Map

Table 17-3 on page 607 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:

■ QEI0: 0x4002.C000
■ QEI1: 0x4002.D000

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Note that the QEI module clock must be enabled before the registers can be programmed (see
page 219). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.

Table 17-3. QEI Register Map

See
Offset Name Type Reset Description
page

0x000 QEICTL R/W 0x0000.0000 QEI Control 608

0x004 QEISTAT RO 0x0000.0000 QEI Status 610

0x008 QEIPOS R/W 0x0000.0000 QEI Position 611

0x00C QEIMAXPOS R/W 0x0000.0000 QEI Maximum Position 612

0x010 QEILOAD R/W 0x0000.0000 QEI Timer Load 613

0x014 QEITIME RO 0x0000.0000 QEI Timer 614

0x018 QEICOUNT RO 0x0000.0000 QEI Velocity Counter 615

0x01C QEISPEED RO 0x0000.0000 QEI Velocity 616

0x020 QEIINTEN R/W 0x0000.0000 QEI Interrupt Enable 617

0x024 QEIRIS RO 0x0000.0000 QEI Raw Interrupt Status 618

0x028 QEIISC R/W1C 0x0000.0000 QEI Interrupt Status and Clear 619

17.6 Register Descriptions

The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.

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 Quadrature Encoder Interface (QEI)

Register 1: QEI Control (QEICTL), offset 0x000

This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.

QEI Control (QEICTL)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable

Type RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:13 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

12 STALLEN R/W 0 Stall QEI

When set, the QEI stalls when the microcontroller asserts Halt.

11 INVI R/W 0 Invert Index Pulse

When set , the input Index Pulse is inverted.

10 INVB R/W 0 Invert PhB

When set, the PhB input is inverted.

9 INVA R/W 0 Invert PhA

When set, the PhA input is inverted.

8:6 VelDiv R/W 0x0 Predivide Velocity

A predivider of the input quadrature pulses before being applied to the
QEICOUNT accumulator. This field can be set to the following values:

Value Predivider
0x0 ÷1
0x1 ÷2
0x2 ÷4
0x3 ÷8
0x4 ÷16
0x5 ÷32
0x6 ÷64
0x7 ÷128

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Bit/Field Name Type Reset Description

5 VelEn R/W 0 Capture Velocity

When set, enables capture of the velocity of the quadrature encoder.

4 ResMode R/W 0 Reset Mode

The Reset mode for the position counter. When 0, the position counter
is reset when it reaches the maximum; when 1, the position counter is
reset when the index pulse is captured.

3 CapMode R/W 0 Capture Mode

The Capture mode defines the phase edges that are counted in the
position. When 0, only the PhA edges are counted; when 1, the PhA
and PhB edges are counted, providing twice the positional resolution
but half the range.

2 SigMode R/W 0 Signal Mode

When 1, the PhA and PhB signals are clock and direction; when 0, they
are quadrature phase signals.

1 Swap R/W 0 Swap Signals

Swaps the PhA and PhB signals.

0 Enable R/W 0 Enable QEI

Enables the quadrature encoder module.

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 Quadrature Encoder Interface (QEI)

Register 2: QEI Status (QEISTAT), offset 0x004

This register provides status about the operation of the QEI module.

QEI Status (QEISTAT)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved Direction Error

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

1 Direction RO 0 Direction of Rotation

Indicates the direction the encoder is rotating.
The Direction values are defined as follows:

Value Description
0 Forward rotation
1 Reverse rotation

0 Error RO 0 Error Detected

Indicates that an error was detected in the gray code sequence (that is,
both signals changing at the same time).

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Register 3: QEI Position (QEIPOS), offset 0x008

This register contains the current value of the position integrator. Its value is updated by inputs on
the QEI phase inputs, and can be set to a specific value by writing to it.

QEI Position (QEIPOS)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Position

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Position

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 Position R/W 0x00 Current Position Integrator Value

The current value of the position integrator.

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Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C

This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving backward, the
position register resets to this value when it decrements from zero.

QEI Maximum Position (QEIMAXPOS)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MaxPos

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MaxPos

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 MaxPos R/W 0x00 Maximum Position Integrator Value

The maximum value of the position integrator.

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Register 5: QEI Timer Load (QEILOAD), offset 0x010

This register contains the load value for the velocity timer. Since this value is loaded into the timer
the clock cycle after the timer is zero, this value should be one less than the number of clocks in
the desired period. So, for example, to have 2000 clocks per timer period, this register should contain
1999.

QEI Timer Load (QEILOAD)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Load

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Load

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 Load R/W 0x00 Velocity Timer Load Value

The load value for the velocity timer.

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 Quadrature Encoder Interface (QEI)

Register 6: QEI Timer (QEITIME), offset 0x014

This register contains the current value of the velocity timer. This counter does not increment when
VelEn in QEICTL is 0.

QEI Timer (QEITIME)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Time

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Time

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 Time RO 0x00 Velocity Timer Current Value

The current value of the velocity timer.

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Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018

This register contains the running count of velocity pulses for the current time period. Since this is
a running total, the time period to which it applies cannot be known with precision (that is, a read of
this register does not necessarily correspond to the time returned by the QEITIME register since
there is a small window of time between the two reads, during which time either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when VelEn in
QEICTL is 0.

QEI Velocity Counter (QEICOUNT)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Count

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Count

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 Count RO 0x00 Velocity Pulse Count

The running total of encoder pulses during this velocity timer period.

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 Quadrature Encoder Interface (QEI)

Register 8: QEI Velocity (QEISPEED), offset 0x01C

This register contains the most recently measured velocity of the quadrature encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when VelEn in QEICTL is 0.

QEI Velocity (QEISPEED)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Speed

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Speed

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:0 Speed RO 0x00 Velocity

The measured speed of the quadrature encoder in pulses per period.

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Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020

This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.

QEI Interrupt Enable (QEIINTEN)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntError IntDir IntTimer IntIndex

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 IntError R/W 0 Phase Error Interrupt Enable

When 1, an interrupt occurs when a phase error is detected.

2 IntDir R/W 0 Direction Change Interrupt Enable

When 1, an interrupt occurs when the direction changes.

1 IntTimer R/W 0 Timer Expires Interrupt Enable

When 1, an interrupt occurs when the velocity timer expires.

0 IntIndex R/W 0 Index Pulse Detected Interrupt Enable

When 1, an interrupt occurs when the index pulse is detected.

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 Quadrature Encoder Interface (QEI)

Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024

This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.

QEI Raw Interrupt Status (QEIRIS)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x024
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntError IntDir IntTimer IntIndex

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 IntError RO 0 Phase Error Detected

Indicates that a phase error was detected.

2 IntDir RO 0 Direction Change Detected

Indicates that the direction has changed.

1 IntTimer RO 0 Velocity Timer Expired

Indicates that the velocity timer has expired.

0 IntIndex RO 0 Index Pulse Asserted

Indicates that the index pulse has occurred.

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Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.

QEI Interrupt Status and Clear (QEIISC)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved IntError IntDir IntTimer IntIndex

Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

3 IntError R/W1C 0 Phase Error Interrupt

Indicates that a phase error was detected.

2 IntDir R/W1C 0 Direction Change Interrupt

Indicates that the direction has changed.

1 IntTimer R/W1C 0 Velocity Timer Expired Interrupt

Indicates that the velocity timer has expired.

0 IntIndex R/W1C 0 Index Pulse Interrupt

Indicates that the index pulse has occurred.

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Pin Diagram

18 Pin Diagram
The LM3S1968 microcontroller pin diagrams are shown below.

Figure 18-1. 100-Pin LQFP Package Pin Diagram

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Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View)

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Signal Tables

19 Signal Tables
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.

The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.

■ Signals by Pin Number

■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals

19.1 100-Pin LQFP Package Pin Tables

19.1.1 Signals by Pin Number

Table 19-1. Signals by Pin Number

a
Pin Number Pin Name Pin Type Buffer Type Description
1 ADC0 I Analog Analog-to-digital converter input 0.
2 ADC1 I Analog Analog-to-digital converter input 1.
VDDA - Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
3
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 653, regardless of system implementation.
GNDA - Power The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
4
the electrical noise contained on VDD from affecting the analog
functions.
5 ADC2 I Analog Analog-to-digital converter input 2.
6 ADC3 I Analog Analog-to-digital converter input 3.
LDO - Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
7
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
8 VDD - Power Positive supply for I/O and some logic.
9 GND - Power Ground reference for logic and I/O pins.
PD0 I/O TTL GPIO port D bit 0.
10
IDX0 I TTL QEI module 0 index.
PD1 I/O TTL GPIO port D bit 1.
11
PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PD2 I/O TTL GPIO port D bit 2.
12 U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.

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Table 19-1. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
PD3 I/O TTL GPIO port D bit 3.
13 U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
VDD25 - Power Positive supply for most of the logic function, including the
14
processor core and most peripherals.
15 GND - Power Ground reference for logic and I/O pins.
16 PG3 I/O TTL GPIO port G bit 3.
PG2 I/O TTL GPIO port G bit 2.
17
PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PG1 I/O TTL GPIO port G bit 1.
18 U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PG0 I/O TTL GPIO port G bit 0.
19 U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
20 VDD - Power Positive supply for I/O and some logic.
21 GND - Power Ground reference for logic and I/O pins.
PC7 I/O TTL GPIO port C bit 7.
22
C2- I Analog Analog comparator 2 negative input.
PC6 I/O TTL GPIO port C bit 6.
23
C2+ I Analog Analog comparator 2 positive input.
PC5 I/O TTL GPIO port C bit 5.
24
C1+ I Analog Analog comparator 1 positive input.
PC4 I/O TTL GPIO port C bit 4.
25
PhA0 I TTL QEI module 0 phase A.
PA0 I/O TTL GPIO port A bit 0.
26 U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
PA1 I/O TTL GPIO port A bit 1.
27 U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA2 I/O TTL GPIO port A bit 2.
28
SSI0Clk I/O TTL SSI module 0 clock.
PA3 I/O TTL GPIO port A bit 3.
29
SSI0Fss I/O TTL SSI module 0 frame signal.
PA4 I/O TTL GPIO port A bit 4.
30
SSI0Rx I TTL SSI module 0 receive.
PA5 I/O TTL GPIO port A bit 5.
31
SSI0Tx O TTL SSI module 0 transmit.
32 VDD - Power Positive supply for I/O and some logic.
33 GND - Power Ground reference for logic and I/O pins.
PA6 I/O TTL GPIO port A bit 6.
34
I2C1SCL I/O OD I2C module 1 clock.

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Signal Tables

Table 19-1. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
PA7 I/O TTL GPIO port A bit 7.
35
I2C1SDA I/O OD I2C module 1 data.
PG7 I/O TTL GPIO port G bit 7.
36
PhB1 I TTL QEI module 1 phase B.
PG6 I/O TTL GPIO port G bit 6.
37
PhA1 I TTL QEI module 1 phase A.
VDD25 - Power Positive supply for most of the logic function, including the
38
processor core and most peripherals.
39 GND - Power Ground reference for logic and I/O pins.
40 PG5 I/O TTL GPIO port G bit 5.
PG4 I/O TTL GPIO port G bit 4.
41
CCP3 I/O TTL Capture/Compare/PWM 3.
42 PF7 I/O TTL GPIO port F bit 7.
PF6 I/O TTL GPIO port F bit 6.
43
CCP1 I/O TTL Capture/Compare/PWM 1.
44 VDD - Power Positive supply for I/O and some logic.
45 GND - Power Ground reference for logic and I/O pins.
46 PF5 I/O TTL GPIO port F bit 5.
PF0 I/O TTL GPIO port F bit 0.
47
PhB0 I TTL QEI module 0 phase B.
48 OSC0 I Analog Main oscillator crystal input or an external clock reference input.
OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a
49
single-ended clock source.
WAKE I TTL An external input that brings the processor out of Hibernate mode
50
when asserted.
HIB O OD An open-drain output with internal pull-up that indicates the
51
processor is in Hibernate mode.
XOSC0 I Analog Hibernation module oscillator crystal input or an external clock
52 reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected
53
when using a single-ended clock source.
54 GND - Power Ground reference for logic and I/O pins.
VBAT - Power Power source for the Hibernation module. It is normally connected
55 to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
56 VDD - Power Positive supply for I/O and some logic.
57 GND - Power Ground reference for logic and I/O pins.
PF4 I/O TTL GPIO port F bit 4.
58
C0o O TTL Analog comparator 0 output.
PF3 I/O TTL GPIO port F bit 3.
59
PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2.
PF2 I/O TTL GPIO port F bit 2.
60
PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2.

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Table 19-1. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
PF1 I/O TTL GPIO port F bit 1.
61
IDX1 I TTL QEI module 1 index.
VDD25 - Power Positive supply for most of the logic function, including the
62
processor core and most peripherals.
63 GND - Power Ground reference for logic and I/O pins.
64 RST I TTL System reset input.
CMOD0 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other
65
encodings reserved.
PB0 I/O TTL GPIO port B bit 0.
66
CCP0 I/O TTL Capture/Compare/PWM 0.
PB1 I/O TTL GPIO port B bit 1.
67
CCP2 I/O TTL Capture/Compare/PWM 2.
68 VDD - Power Positive supply for I/O and some logic.
69 GND - Power Ground reference for logic and I/O pins.
PB2 I/O TTL GPIO port B bit 2.
70
I2C0SCL I/O OD I2C module 0 clock.
PB3 I/O TTL GPIO port B bit 3.
71
I2C0SDA I/O OD I2C module 0 data.
PE0 I/O TTL GPIO port E bit 0.
72
SSI1Clk I/O TTL SSI module 1 clock.
PE1 I/O TTL GPIO port E bit 1.
73
SSI1Fss I/O TTL SSI module 1 frame signal.
PE2 I/O TTL GPIO port E bit 2.
74
SSI1Rx I TTL SSI module 1 receive.
PE3 I/O TTL GPIO port E bit 3.
75
SSI1Tx O TTL SSI module 1 transmit.
CMOD1 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other
76
encodings reserved.
PC3 I/O TTL GPIO port C bit 3.
77 SWO O TTL JTAG TDO and SWO.
TDO O TTL JTAG TDO and SWO.
PC2 I/O TTL GPIO port C bit 2.
78
TDI I TTL JTAG TDI.
PC1 I/O TTL GPIO port C bit 1.
79 SWDIO I/O TTL JTAG TMS and SWDIO.
TMS I/O TTL JTAG TMS and SWDIO.
PC0 I/O TTL GPIO port C bit 0.
80 SWCLK I TTL JTAG/SWD CLK.
TCK I TTL JTAG/SWD CLK.
81 VDD - Power Positive supply for I/O and some logic.
82 GND - Power Ground reference for logic and I/O pins.

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Signal Tables

Table 19-1. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
PH3 I/O TTL GPIO port H bit 3.
83
Fault I TTL PWM Fault.
84 PH2 I/O TTL GPIO port H bit 2.
PH1 I/O TTL GPIO port H bit 1.
85
PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PH0 I/O TTL GPIO port H bit 0.
86
PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1.
87 GND - Power Ground reference for logic and I/O pins.
VDD25 - Power Positive supply for most of the logic function, including the
88
processor core and most peripherals.
PB7 I/O TTL GPIO port B bit 7.
89
TRST I TTL JTAG TRST.
PB6 I/O TTL GPIO port B bit 6.
90
C0+ I Analog Analog comparator 0 positive input.
PB5 I/O TTL GPIO port B bit 5.
91
C1- I Analog Analog comparator 1 negative input.
PB4 I/O TTL GPIO port B bit 4.
92
C0- I Analog Analog comparator 0 negative input.
93 VDD - Power Positive supply for I/O and some logic.
94 GND - Power Ground reference for logic and I/O pins.
95 ADC7 I Analog Analog-to-digital converter input 7.
96 ADC6 I Analog Analog-to-digital converter input 6.
GNDA - Power The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
97
the electrical noise contained on VDD from affecting the analog
functions.
VDDA - Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
98
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 653, regardless of system implementation.
99 ADC5 I Analog Analog-to-digital converter input 5.
100 ADC4 I Analog Analog-to-digital converter input 4.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

19.1.2 Signals by Signal Name

Table 19-2. Signals by Signal Name

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.

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Table 19-2. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC4 100 I Analog Analog-to-digital converter input 4.
ADC5 99 I Analog Analog-to-digital converter input 5.
ADC6 96 I Analog Analog-to-digital converter input 6.
ADC7 95 I Analog Analog-to-digital converter input 7.
C0+ 90 I Analog Analog comparator 0 positive input.
C0- 92 I Analog Analog comparator 0 negative input.
C0o 58 O TTL Analog comparator 0 output.
C1+ 24 I Analog Analog comparator 1 positive input.
C1- 91 I Analog Analog comparator 1 negative input.
C2+ 23 I Analog Analog comparator 2 positive input.
C2- 22 I Analog Analog comparator 2 negative input.
CCP0 66 I/O TTL Capture/Compare/PWM 0.
CCP1 43 I/O TTL Capture/Compare/PWM 1.
CCP2 67 I/O TTL Capture/Compare/PWM 2.
CCP3 41 I/O TTL Capture/Compare/PWM 3.
CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
Fault 83 I TTL PWM Fault.
GND 9 - Power Ground reference for logic and I/O pins.
15
21
33
39
45
54
57
63
69
82
87
94
GNDA 4 - Power The ground reference for the analog circuits (ADC, Analog
97 Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
HIB 51 O OD An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
I2C0SCL 70 I/O OD I2C module 0 clock.
I2C0SDA 71 I/O OD I2C module 0 data.
I2C1SCL 34 I/O OD I2C module 1 clock.
I2C1SDA 35 I/O OD I2C module 1 data.
IDX0 10 I TTL QEI module 0 index.
IDX1 61 I TTL QEI module 1 index.

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Table 19-2. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
LDO 7 - Power Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. The LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
OSC0 48 I Analog Main oscillator crystal input or an external clock reference
input.
OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0 26 I/O TTL GPIO port A bit 0.
PA1 27 I/O TTL GPIO port A bit 1.
PA2 28 I/O TTL GPIO port A bit 2.
PA3 29 I/O TTL GPIO port A bit 3.
PA4 30 I/O TTL GPIO port A bit 4.
PA5 31 I/O TTL GPIO port A bit 5.
PA6 34 I/O TTL GPIO port A bit 6.
PA7 35 I/O TTL GPIO port A bit 7.
PB0 66 I/O TTL GPIO port B bit 0.
PB1 67 I/O TTL GPIO port B bit 1.
PB2 70 I/O TTL GPIO port B bit 2.
PB3 71 I/O TTL GPIO port B bit 3.
PB4 92 I/O TTL GPIO port B bit 4.
PB5 91 I/O TTL GPIO port B bit 5.
PB6 90 I/O TTL GPIO port B bit 6.
PB7 89 I/O TTL GPIO port B bit 7.
PC0 80 I/O TTL GPIO port C bit 0.
PC1 79 I/O TTL GPIO port C bit 1.
PC2 78 I/O TTL GPIO port C bit 2.
PC3 77 I/O TTL GPIO port C bit 3.
PC4 25 I/O TTL GPIO port C bit 4.
PC5 24 I/O TTL GPIO port C bit 5.
PC6 23 I/O TTL GPIO port C bit 6.
PC7 22 I/O TTL GPIO port C bit 7.
PD0 10 I/O TTL GPIO port D bit 0.
PD1 11 I/O TTL GPIO port D bit 1.
PD2 12 I/O TTL GPIO port D bit 2.
PD3 13 I/O TTL GPIO port D bit 3.
PE0 72 I/O TTL GPIO port E bit 0.
PE1 73 I/O TTL GPIO port E bit 1.
PE2 74 I/O TTL GPIO port E bit 2.
PE3 75 I/O TTL GPIO port E bit 3.
PF0 47 I/O TTL GPIO port F bit 0.
PF1 61 I/O TTL GPIO port F bit 1.

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Table 19-2. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PF2 60 I/O TTL GPIO port F bit 2.
PF3 59 I/O TTL GPIO port F bit 3.
PF4 58 I/O TTL GPIO port F bit 4.
PF5 46 I/O TTL GPIO port F bit 5.
PF6 43 I/O TTL GPIO port F bit 6.
PF7 42 I/O TTL GPIO port F bit 7.
PG0 19 I/O TTL GPIO port G bit 0.
PG1 18 I/O TTL GPIO port G bit 1.
PG2 17 I/O TTL GPIO port G bit 2.
PG3 16 I/O TTL GPIO port G bit 3.
PG4 41 I/O TTL GPIO port G bit 4.
PG5 40 I/O TTL GPIO port G bit 5.
PG6 37 I/O TTL GPIO port G bit 6.
PG7 36 I/O TTL GPIO port G bit 7.
PH0 86 I/O TTL GPIO port H bit 0.
PH1 85 I/O TTL GPIO port H bit 1.
PH2 84 I/O TTL GPIO port H bit 2.
PH3 83 I/O TTL GPIO port H bit 3.
PhA0 25 I TTL QEI module 0 phase A.
PhA1 37 I TTL QEI module 1 phase A.
PhB0 47 I TTL QEI module 0 phase B.
PhB1 36 I TTL QEI module 1 phase B.
PWM0 17 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PWM1 11 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PWM2 86 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PWM3 85 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PWM4 60 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PWM5 59 O TTL PWM 5. This signal is controlled by PWM Generator 2.
RST 64 I TTL System reset input.
SSI0Clk 28 I/O TTL SSI module 0 clock.
SSI0Fss 29 I/O TTL SSI module 0 frame signal.
SSI0Rx 30 I TTL SSI module 0 receive.
SSI0Tx 31 O TTL SSI module 0 transmit.
SSI1Clk 72 I/O TTL SSI module 1 clock.
SSI1Fss 73 I/O TTL SSI module 1 frame signal.
SSI1Rx 74 I TTL SSI module 1 receive.
SSI1Tx 75 O TTL SSI module 1 transmit.
SWCLK 80 I TTL JTAG/SWD CLK.
SWDIO 79 I/O TTL JTAG TMS and SWDIO.
SWO 77 O TTL JTAG TDO and SWO.
TCK 80 I TTL JTAG/SWD CLK.

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Table 19-2. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
TDI 78 I TTL JTAG TDI.
TDO 77 O TTL JTAG TDO and SWO.
TMS 79 I/O TTL JTAG TMS and SWDIO.
TRST 89 I TTL JTAG TRST.
U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
U1Rx 12 I TTL UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
U1Tx 13 O TTL UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
U2Rx 19 I TTL UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
U2Tx 18 O TTL UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
VBAT 55 - Power Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
VDD 8 - Power Positive supply for I/O and some logic.
20
32
44
56
68
81
93
VDD25 14 - Power Positive supply for most of the logic function, including the
38 processor core and most peripherals.
62
88
VDDA 3 - Power The positive supply for the analog circuits (ADC, Analog
98 Comparators, etc.). These are separated from VDD to
minimize the electrical noise contained on VDD from affecting
the analog functions. VDDA pins must be supplied with a
voltage that meets the specification in “Recommended DC
Operating Conditions” on page 653, regardless of system
implementation.
WAKE 50 I TTL An external input that brings the processor out of Hibernate
mode when asserted.
XOSC0 52 I Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

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19.1.3 Signals by Function, Except for GPIO

Table 19-3. Signals by Function, Except for GPIO

a
Function Pin Name Pin Number Pin Type Buffer Type Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.
ADC
ADC4 100 I Analog Analog-to-digital converter input 4.
ADC5 99 I Analog Analog-to-digital converter input 5.
ADC6 96 I Analog Analog-to-digital converter input 6.
ADC7 95 I Analog Analog-to-digital converter input 7.
C0+ 90 I Analog Analog comparator 0 positive input.
C0- 92 I Analog Analog comparator 0 negative input.
C0o 58 O TTL Analog comparator 0 output.
Analog Comparators C1+ 24 I Analog Analog comparator 1 positive input.
C1- 91 I Analog Analog comparator 1 negative input.
C2+ 23 I Analog Analog comparator 2 positive input.
C2- 22 I Analog Analog comparator 2 negative input.
CCP0 66 I/O TTL Capture/Compare/PWM 0.

General-Purpose CCP1 43 I/O TTL Capture/Compare/PWM 1.

Timers CCP2 67 I/O TTL Capture/Compare/PWM 2.
CCP3 41 I/O TTL Capture/Compare/PWM 3.
HIB 51 O OD An open-drain output with internal pull-up that
indicates the processor is in Hibernate mode.
VBAT 55 - Power Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE 50 I TTL An external input that brings the processor out of
Hibernate Hibernate mode when asserted.
XOSC0 52 I Analog Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
I2C0SCL 70 I/O OD I2C module 0 clock.
I2C0SDA 71 I/O OD I2C module 0 data.
I2C
I2C1SCL 34 I/O OD I2C module 1 clock.
I2C1SDA 35 I/O OD I2C module 1 data.

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Table 19-3. Signals by Function, Except for GPIO (continued)

a
Function Pin Name Pin Number Pin Type Buffer Type Description
SWCLK 80 I TTL JTAG/SWD CLK.
SWDIO 79 I/O TTL JTAG TMS and SWDIO.
SWO 77 O TTL JTAG TDO and SWO.
TCK 80 I TTL JTAG/SWD CLK.
JTAG/SWD/SWO
TDI 78 I TTL JTAG TDI.
TDO 77 O TTL JTAG TDO and SWO.
TMS 79 I/O TTL JTAG TMS and SWDIO.
TRST 89 I TTL JTAG TRST.
Fault 83 I TTL PWM Fault.
PWM0 17 O TTL PWM 0. This signal is controlled by PWM Generator
0.
PWM1 11 O TTL PWM 1. This signal is controlled by PWM Generator
0.
PWM2 86 O TTL PWM 2. This signal is controlled by PWM Generator
PWM 1.
PWM3 85 O TTL PWM 3. This signal is controlled by PWM Generator
1.
PWM4 60 O TTL PWM 4. This signal is controlled by PWM Generator
2.
PWM5 59 O TTL PWM 5. This signal is controlled by PWM Generator
2.

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Table 19-3. Signals by Function, Except for GPIO (continued)

a
Function Pin Name Pin Number Pin Type Buffer Type Description
GND 9 - Power Ground reference for logic and I/O pins.
15
21
33
39
45
54
57
63
69
82
87
94
GNDA 4 - Power The ground reference for the analog circuits (ADC,
97 Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
LDO 7 - Power Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDD25 pins at the board level in
Power addition to the decoupling capacitor(s).
VDD 8 - Power Positive supply for I/O and some logic.
20
32
44
56
68
81
93
VDD25 14 - Power Positive supply for most of the logic function,
38 including the processor core and most peripherals.
62
88
VDDA 3 - Power The positive supply for the analog circuits (ADC,
98 Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in “Recommended DC Operating
Conditions” on page 653, regardless of system
implementation.
IDX0 10 I TTL QEI module 0 index.
IDX1 61 I TTL QEI module 1 index.
PhA0 25 I TTL QEI module 0 phase A.
QEI
PhA1 37 I TTL QEI module 1 phase A.
PhB0 47 I TTL QEI module 0 phase B.
PhB1 36 I TTL QEI module 1 phase B.

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Table 19-3. Signals by Function, Except for GPIO (continued)

a
Function Pin Name Pin Number Pin Type Buffer Type Description
SSI0Clk 28 I/O TTL SSI module 0 clock.
SSI0Fss 29 I/O TTL SSI module 0 frame signal.
SSI0Rx 30 I TTL SSI module 0 receive.
SSI0Tx 31 O TTL SSI module 0 transmit.
SSI
SSI1Clk 72 I/O TTL SSI module 1 clock.
SSI1Fss 73 I/O TTL SSI module 1 frame signal.
SSI1Rx 74 I TTL SSI module 1 receive.
SSI1Tx 75 O TTL SSI module 1 transmit.
CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
System Control &
OSC0 48 I Analog Main oscillator crystal input or an external clock
Clocks
reference input.
OSC1 49 O Analog Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST 64 I TTL System reset input.
U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Rx 12 I TTL UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
UART
U1Tx 13 O TTL UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx 19 I TTL UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx 18 O TTL UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

19.1.4 GPIO Pins and Alternate Functions

Table 19-4. GPIO Pins and Alternate Functions

IO Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 I2C1SCL
PA7 35 I2C1SDA
PB0 66 CCP0
PB1 67 CCP2

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Table 19-4. GPIO Pins and Alternate Functions (continued)

IO Pin Number Multiplexed Function Multiplexed Function
PB2 70 I2C0SCL
PB3 71 I2C0SDA
PB4 92 C0-
PB5 91 C1-
PB6 90 C0+
PB7 89 TRST
PC0 80 TCK SWCLK
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25 PhA0
PC5 24 C1+
PC6 23 C2+
PC7 22 C2-
PD0 10 IDX0
PD1 11 PWM1
PD2 12 U1Rx
PD3 13 U1Tx
PE0 72 SSI1Clk
PE1 73 SSI1Fss
PE2 74 SSI1Rx
PE3 75 SSI1Tx
PF0 47 PhB0
PF1 61 IDX1
PF2 60 PWM4
PF3 59 PWM5
PF4 58 C0o
PF5 46
PF6 43 CCP1
PF7 42
PG0 19 U2Rx
PG1 18 U2Tx
PG2 17 PWM0
PG3 16
PG4 41 CCP3
PG5 40
PG6 37 PhA1
PG7 36 PhB1
PH0 86 PWM2
PH1 85 PWM3
PH2 84

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Table 19-4. GPIO Pins and Alternate Functions (continued)

IO Pin Number Multiplexed Function Multiplexed Function
PH3 83 Fault

19.2 108-Ball BGA Package Pin Tables

19.2.1 Signals by Pin Number

Table 19-5. Signals by Pin Number

a
Pin Number Pin Name Pin Type Buffer Type Description
A1 ADC1 I Analog Analog-to-digital converter input 1.
A2 ADC4 I Analog Analog-to-digital converter input 4.
A3 ADC5 I Analog Analog-to-digital converter input 5.
A4 ADC7 I Analog Analog-to-digital converter input 7.
GNDA - Power The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
A5
the electrical noise contained on VDD from affecting the analog
functions.
PB4 I/O TTL GPIO port B bit 4.
A6
C0- I Analog Analog comparator 0 negative input.
PB6 I/O TTL GPIO port B bit 6.
A7
C0+ I Analog Analog comparator 0 positive input.
PB7 I/O TTL GPIO port B bit 7.
A8
TRST I TTL JTAG TRST.
PC0 I/O TTL GPIO port C bit 0.
A9 SWCLK I TTL JTAG/SWD CLK.
TCK I TTL JTAG/SWD CLK.
PC3 I/O TTL GPIO port C bit 3.
A10 SWO O TTL JTAG TDO and SWO.
TDO O TTL JTAG TDO and SWO.
PE0 I/O TTL GPIO port E bit 0.
A11
SSI1Clk I/O TTL SSI module 1 clock.
PE3 I/O TTL GPIO port E bit 3.
A12
SSI1Tx O TTL SSI module 1 transmit.
B1 ADC0 I Analog Analog-to-digital converter input 0.
B2 ADC3 I Analog Analog-to-digital converter input 3.
B3 ADC2 I Analog Analog-to-digital converter input 2.
B4 ADC6 I Analog Analog-to-digital converter input 6.
GNDA - Power The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
B5
the electrical noise contained on VDD from affecting the analog
functions.
B6 GND - Power Ground reference for logic and I/O pins.
PB5 I/O TTL GPIO port B bit 5.
B7
C1- I Analog Analog comparator 1 negative input.

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Table 19-5. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
PC2 I/O TTL GPIO port C bit 2.
B8
TDI I TTL JTAG TDI.
PC1 I/O TTL GPIO port C bit 1.
B9 SWDIO I/O TTL JTAG TMS and SWDIO.
TMS I/O TTL JTAG TMS and SWDIO.
CMOD1 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other
B10
encodings reserved.
PE2 I/O TTL GPIO port E bit 2.
B11
SSI1Rx I TTL SSI module 1 receive.
PE1 I/O TTL GPIO port E bit 1.
B12
SSI1Fss I/O TTL SSI module 1 frame signal.
C1 NC - - No connect. Leave the pin electrically unconnected/isolated.
C2 NC - - No connect. Leave the pin electrically unconnected/isolated.
VDD25 - Power Positive supply for most of the logic function, including the
C3
processor core and most peripherals.
C4 GND - Power Ground reference for logic and I/O pins.
C5 GND - Power Ground reference for logic and I/O pins.
VDDA - Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
C6
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 653, regardless of system implementation.
VDDA - Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
C7
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 653, regardless of system implementation.
PH1 I/O TTL GPIO port H bit 1.
C8
PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PH0 I/O TTL GPIO port H bit 0.
C9
PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PG7 I/O TTL GPIO port G bit 7.
C10
PhB1 I TTL QEI module 1 phase B.
PB2 I/O TTL GPIO port B bit 2.
C11
I2C0SCL I/O OD I2C module 0 clock.
PB3 I/O TTL GPIO port B bit 3.
C12
I2C0SDA I/O OD I2C module 0 data.
D1 NC - - No connect. Leave the pin electrically unconnected/isolated.
D2 NC - - No connect. Leave the pin electrically unconnected/isolated.
VDD25 - Power Positive supply for most of the logic function, including the
D3
processor core and most peripherals.
PH3 I/O TTL GPIO port H bit 3.
D10
Fault I TTL PWM Fault.

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Table 19-5. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
D11 PH2 I/O TTL GPIO port H bit 2.
PB1 I/O TTL GPIO port B bit 1.
D12
CCP2 I/O TTL Capture/Compare/PWM 2.
E1 NC - - No connect. Leave the pin electrically unconnected/isolated.
E2 NC - - No connect. Leave the pin electrically unconnected/isolated.
LDO - Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
E3
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
E10 VDD33 - Power Positive supply for I/O and some logic.
CMOD0 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other
E11
encodings reserved.
PB0 I/O TTL GPIO port B bit 0.
E12
CCP0 I/O TTL Capture/Compare/PWM 0.
F1 NC - - No connect. Leave the pin electrically unconnected/isolated.
F2 NC - - No connect. Leave the pin electrically unconnected/isolated.
VDD25 - Power Positive supply for most of the logic function, including the
F3
processor core and most peripherals.
F10 GND - Power Ground reference for logic and I/O pins.
F11 GND - Power Ground reference for logic and I/O pins.
F12 GND - Power Ground reference for logic and I/O pins.
PD0 I/O TTL GPIO port D bit 0.
G1
IDX0 I TTL QEI module 0 index.
PD1 I/O TTL GPIO port D bit 1.
G2
PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0.
VDD25 - Power Positive supply for most of the logic function, including the
G3
processor core and most peripherals.
G10 VDD33 - Power Positive supply for I/O and some logic.
G11 VDD33 - Power Positive supply for I/O and some logic.
G12 VDD33 - Power Positive supply for I/O and some logic.
PD3 I/O TTL GPIO port D bit 3.
H1 U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PD2 I/O TTL GPIO port D bit 2.
H2 U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
H3 GND - Power Ground reference for logic and I/O pins.
H10 VDD33 - Power Positive supply for I/O and some logic.
H11 RST I TTL System reset input.
PF1 I/O TTL GPIO port F bit 1.
H12
IDX1 I TTL QEI module 1 index.
PG2 I/O TTL GPIO port G bit 2.
J1
PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0.
J2 PG3 I/O TTL GPIO port G bit 3.

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Table 19-5. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
J3 GND - Power Ground reference for logic and I/O pins.
J10 GND - Power Ground reference for logic and I/O pins.
PF2 I/O TTL GPIO port F bit 2.
J11
PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PF3 I/O TTL GPIO port F bit 3.
J12
PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2.
PG0 I/O TTL GPIO port G bit 0.
K1 U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
PG1 I/O TTL GPIO port G bit 1.
K2 U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PG4 I/O TTL GPIO port G bit 4.
K3
CCP3 I/O TTL Capture/Compare/PWM 3.
K4 PF7 I/O TTL GPIO port F bit 7.
K5 GND - Power Ground reference for logic and I/O pins.
K6 GND - Power Ground reference for logic and I/O pins.
K7 VDD33 - Power Positive supply for I/O and some logic.
K8 VDD33 - Power Positive supply for I/O and some logic.
K9 VDD33 - Power Positive supply for I/O and some logic.
K10 GND - Power Ground reference for logic and I/O pins.
XOSC0 I Analog Hibernation module oscillator crystal input or an external clock
K11 reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected
K12
when using a single-ended clock source.
PC4 I/O TTL GPIO port C bit 4.
L1
PhA0 I TTL QEI module 0 phase A.
PC7 I/O TTL GPIO port C bit 7.
L2
C2- I Analog Analog comparator 2 negative input.
PA0 I/O TTL GPIO port A bit 0.
L3 U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
PA3 I/O TTL GPIO port A bit 3.
L4
SSI0Fss I/O TTL SSI module 0 frame signal.
PA4 I/O TTL GPIO port A bit 4.
L5
SSI0Rx I TTL SSI module 0 receive.
PA6 I/O TTL GPIO port A bit 6.
L6
I2C1SCL I/O OD I2C module 1 clock.
PG6 I/O TTL GPIO port G bit 6.
L7
PhA1 I TTL QEI module 1 phase A.
L8 PF5 I/O TTL GPIO port F bit 5.

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Table 19-5. Signals by Pin Number (continued)

a
Pin Number Pin Name Pin Type Buffer Type Description
PF4 I/O TTL GPIO port F bit 4.
L9
C0o O TTL Analog comparator 0 output.
L10 GND - Power Ground reference for logic and I/O pins.
L11 OSC0 I Analog Main oscillator crystal input or an external clock reference input.
VBAT - Power Power source for the Hibernation module. It is normally connected
L12 to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
PC5 I/O TTL GPIO port C bit 5.
M1
C1+ I Analog Analog comparator 1 positive input.
PC6 I/O TTL GPIO port C bit 6.
M2
C2+ I Analog Analog comparator 2 positive input.
PA1 I/O TTL GPIO port A bit 1.
M3 U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA2 I/O TTL GPIO port A bit 2.
M4
SSI0Clk I/O TTL SSI module 0 clock.
PA5 I/O TTL GPIO port A bit 5.
M5
SSI0Tx O TTL SSI module 0 transmit.
PA7 I/O TTL GPIO port A bit 7.
M6
I2C1SDA I/O OD I2C module 1 data.
M7 PG5 I/O TTL GPIO port G bit 5.
PF6 I/O TTL GPIO port F bit 6.
M8
CCP1 I/O TTL Capture/Compare/PWM 1.
PF0 I/O TTL GPIO port F bit 0.
M9
PhB0 I TTL QEI module 0 phase B.
WAKE I TTL An external input that brings the processor out of Hibernate mode
M10
when asserted.
OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a
M11
single-ended clock source.
HIB O OD An open-drain output with internal pull-up that indicates the
M12
processor is in Hibernate mode.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

19.2.2 Signals by Signal Name

Table 19-6. Signals by Signal Name

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 B1 I Analog Analog-to-digital converter input 0.
ADC1 A1 I Analog Analog-to-digital converter input 1.
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
ADC4 A2 I Analog Analog-to-digital converter input 4.
ADC5 A3 I Analog Analog-to-digital converter input 5.
ADC6 B4 I Analog Analog-to-digital converter input 6.

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Table 19-6. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
ADC7 A4 I Analog Analog-to-digital converter input 7.
C0+ A7 I Analog Analog comparator 0 positive input.
C0- A6 I Analog Analog comparator 0 negative input.
C0o L9 O TTL Analog comparator 0 output.
C1+ M1 I Analog Analog comparator 1 positive input.
C1- B7 I Analog Analog comparator 1 negative input.
C2+ M2 I Analog Analog comparator 2 positive input.
C2- L2 I Analog Analog comparator 2 negative input.
CCP0 E12 I/O TTL Capture/Compare/PWM 0.
CCP1 M8 I/O TTL Capture/Compare/PWM 1.
CCP2 D12 I/O TTL Capture/Compare/PWM 2.
CCP3 K3 I/O TTL Capture/Compare/PWM 3.
CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
Fault D10 I TTL PWM Fault.
GND B6 - Power Ground reference for logic and I/O pins.
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
GNDA A5 - Power The ground reference for the analog circuits (ADC, Analog
B5 Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
HIB M12 O OD An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
I2C0SCL C11 I/O OD I2C module 0 clock.
I2C0SDA C12 I/O OD I2C module 0 data.
I2C1SCL L6 I/O OD I2C module 1 clock.
I2C1SDA M6 I/O OD I2C module 1 data.
IDX0 G1 I TTL QEI module 0 index.
IDX1 H12 I TTL QEI module 1 index.
LDO E3 - Power Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. The LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).

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Table 19-6. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
NC C1 - - No connect. Leave the pin electrically unconnected/isolated.
C2
D1
D2
E1
E2
F1
F2
OSC0 L11 I Analog Main oscillator crystal input or an external clock reference
input.
OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0 L3 I/O TTL GPIO port A bit 0.
PA1 M3 I/O TTL GPIO port A bit 1.
PA2 M4 I/O TTL GPIO port A bit 2.
PA3 L4 I/O TTL GPIO port A bit 3.
PA4 L5 I/O TTL GPIO port A bit 4.
PA5 M5 I/O TTL GPIO port A bit 5.
PA6 L6 I/O TTL GPIO port A bit 6.
PA7 M6 I/O TTL GPIO port A bit 7.
PB0 E12 I/O TTL GPIO port B bit 0.
PB1 D12 I/O TTL GPIO port B bit 1.
PB2 C11 I/O TTL GPIO port B bit 2.
PB3 C12 I/O TTL GPIO port B bit 3.
PB4 A6 I/O TTL GPIO port B bit 4.
PB5 B7 I/O TTL GPIO port B bit 5.
PB6 A7 I/O TTL GPIO port B bit 6.
PB7 A8 I/O TTL GPIO port B bit 7.
PC0 A9 I/O TTL GPIO port C bit 0.
PC1 B9 I/O TTL GPIO port C bit 1.
PC2 B8 I/O TTL GPIO port C bit 2.
PC3 A10 I/O TTL GPIO port C bit 3.
PC4 L1 I/O TTL GPIO port C bit 4.
PC5 M1 I/O TTL GPIO port C bit 5.
PC6 M2 I/O TTL GPIO port C bit 6.
PC7 L2 I/O TTL GPIO port C bit 7.
PD0 G1 I/O TTL GPIO port D bit 0.
PD1 G2 I/O TTL GPIO port D bit 1.
PD2 H2 I/O TTL GPIO port D bit 2.
PD3 H1 I/O TTL GPIO port D bit 3.
PE0 A11 I/O TTL GPIO port E bit 0.
PE1 B12 I/O TTL GPIO port E bit 1.
PE2 B11 I/O TTL GPIO port E bit 2.
PE3 A12 I/O TTL GPIO port E bit 3.

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Table 19-6. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
PF0 M9 I/O TTL GPIO port F bit 0.
PF1 H12 I/O TTL GPIO port F bit 1.
PF2 J11 I/O TTL GPIO port F bit 2.
PF3 J12 I/O TTL GPIO port F bit 3.
PF4 L9 I/O TTL GPIO port F bit 4.
PF5 L8 I/O TTL GPIO port F bit 5.
PF6 M8 I/O TTL GPIO port F bit 6.
PF7 K4 I/O TTL GPIO port F bit 7.
PG0 K1 I/O TTL GPIO port G bit 0.
PG1 K2 I/O TTL GPIO port G bit 1.
PG2 J1 I/O TTL GPIO port G bit 2.
PG3 J2 I/O TTL GPIO port G bit 3.
PG4 K3 I/O TTL GPIO port G bit 4.
PG5 M7 I/O TTL GPIO port G bit 5.
PG6 L7 I/O TTL GPIO port G bit 6.
PG7 C10 I/O TTL GPIO port G bit 7.
PH0 C9 I/O TTL GPIO port H bit 0.
PH1 C8 I/O TTL GPIO port H bit 1.
PH2 D11 I/O TTL GPIO port H bit 2.
PH3 D10 I/O TTL GPIO port H bit 3.
PhA0 L1 I TTL QEI module 0 phase A.
PhA1 L7 I TTL QEI module 1 phase A.
PhB0 M9 I TTL QEI module 0 phase B.
PhB1 C10 I TTL QEI module 1 phase B.
PWM0 J1 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PWM1 G2 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PWM2 C9 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PWM3 C8 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PWM4 J11 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PWM5 J12 O TTL PWM 5. This signal is controlled by PWM Generator 2.
RST H11 I TTL System reset input.
SSI0Clk M4 I/O TTL SSI module 0 clock.
SSI0Fss L4 I/O TTL SSI module 0 frame signal.
SSI0Rx L5 I TTL SSI module 0 receive.
SSI0Tx M5 O TTL SSI module 0 transmit.
SSI1Clk A11 I/O TTL SSI module 1 clock.
SSI1Fss B12 I/O TTL SSI module 1 frame signal.
SSI1Rx B11 I TTL SSI module 1 receive.
SSI1Tx A12 O TTL SSI module 1 transmit.
SWCLK A9 I TTL JTAG/SWD CLK.
SWDIO B9 I/O TTL JTAG TMS and SWDIO.

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Table 19-6. Signals by Signal Name (continued)

a
Pin Name Pin Number Pin Type Buffer Type Description
SWO A10 O TTL JTAG TDO and SWO.
TCK A9 I TTL JTAG/SWD CLK.
TDI B8 I TTL JTAG TDI.
TDO A10 O TTL JTAG TDO and SWO.
TMS B9 I/O TTL JTAG TMS and SWDIO.
TRST A8 I TTL JTAG TRST.
U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
U1Rx H2 I TTL UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
U1Tx H1 O TTL UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
U2Rx K1 I TTL UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
U2Tx K2 O TTL UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
VBAT L12 - Power Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
VDD25 C3 - Power Positive supply for most of the logic function, including the
D3 processor core and most peripherals.
F3
G3
VDD33 E10 - Power Positive supply for I/O and some logic.
G10
G11
G12
H10
K7
K8
K9
VDDA C6 - Power The positive supply for the analog circuits (ADC, Analog
C7 Comparators, etc.). These are separated from VDD to
minimize the electrical noise contained on VDD from affecting
the analog functions. VDDA pins must be supplied with a
voltage that meets the specification in “Recommended DC
Operating Conditions” on page 653, regardless of system
implementation.
WAKE M10 I TTL An external input that brings the processor out of Hibernate
mode when asserted.
XOSC0 K11 I Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

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19.2.3 Signals by Function, Except for GPIO

Table 19-7. Signals by Function, Except for GPIO

a
Function Pin Name Pin Number Pin Type Buffer Type Description
ADC0 B1 I Analog Analog-to-digital converter input 0.
ADC1 A1 I Analog Analog-to-digital converter input 1.
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
ADC
ADC4 A2 I Analog Analog-to-digital converter input 4.
ADC5 A3 I Analog Analog-to-digital converter input 5.
ADC6 B4 I Analog Analog-to-digital converter input 6.
ADC7 A4 I Analog Analog-to-digital converter input 7.
C0+ A7 I Analog Analog comparator 0 positive input.
C0- A6 I Analog Analog comparator 0 negative input.
C0o L9 O TTL Analog comparator 0 output.
Analog Comparators C1+ M1 I Analog Analog comparator 1 positive input.
C1- B7 I Analog Analog comparator 1 negative input.
C2+ M2 I Analog Analog comparator 2 positive input.
C2- L2 I Analog Analog comparator 2 negative input.
CCP0 E12 I/O TTL Capture/Compare/PWM 0.

General-Purpose CCP1 M8 I/O TTL Capture/Compare/PWM 1.

Timers CCP2 D12 I/O TTL Capture/Compare/PWM 2.
CCP3 K3 I/O TTL Capture/Compare/PWM 3.
HIB M12 O OD An open-drain output with internal pull-up that
indicates the processor is in Hibernate mode.
VBAT L12 - Power Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE M10 I TTL An external input that brings the processor out of
Hibernate Hibernate mode when asserted.
XOSC0 K11 I Analog Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
I2C0SCL C11 I/O OD I2C module 0 clock.
I2C0SDA C12 I/O OD I2C module 0 data.
I2C
I2C1SCL L6 I/O OD I2C module 1 clock.
I2C1SDA M6 I/O OD I2C module 1 data.

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Table 19-7. Signals by Function, Except for GPIO (continued)

a
Function Pin Name Pin Number Pin Type Buffer Type Description
SWCLK A9 I TTL JTAG/SWD CLK.
SWDIO B9 I/O TTL JTAG TMS and SWDIO.
SWO A10 O TTL JTAG TDO and SWO.
TCK A9 I TTL JTAG/SWD CLK.
JTAG/SWD/SWO
TDI B8 I TTL JTAG TDI.
TDO A10 O TTL JTAG TDO and SWO.
TMS B9 I/O TTL JTAG TMS and SWDIO.
TRST A8 I TTL JTAG TRST.
Fault D10 I TTL PWM Fault.
PWM0 J1 O TTL PWM 0. This signal is controlled by PWM Generator
0.
PWM1 G2 O TTL PWM 1. This signal is controlled by PWM Generator
0.
PWM2 C9 O TTL PWM 2. This signal is controlled by PWM Generator
PWM 1.
PWM3 C8 O TTL PWM 3. This signal is controlled by PWM Generator
1.
PWM4 J11 O TTL PWM 4. This signal is controlled by PWM Generator
2.
PWM5 J12 O TTL PWM 5. This signal is controlled by PWM Generator
2.

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Table 19-7. Signals by Function, Except for GPIO (continued)

a
Function Pin Name Pin Number Pin Type Buffer Type Description
GND B6 - Power Ground reference for logic and I/O pins.
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
GNDA A5 - Power The ground reference for the analog circuits (ADC,
B5 Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
LDO E3 - Power Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDD25 pins at the board level in
Power addition to the decoupling capacitor(s).
VDD25 C3 - Power Positive supply for most of the logic function,
D3 including the processor core and most peripherals.
F3
G3
VDD33 E10 - Power Positive supply for I/O and some logic.
G10
G11
G12
H10
K7
K8
K9
VDDA C6 - Power The positive supply for the analog circuits (ADC,
C7 Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in “Recommended DC Operating
Conditions” on page 653, regardless of system
implementation.
IDX0 G1 I TTL QEI module 0 index.
IDX1 H12 I TTL QEI module 1 index.
PhA0 L1 I TTL QEI module 0 phase A.
QEI
PhA1 L7 I TTL QEI module 1 phase A.
PhB0 M9 I TTL QEI module 0 phase B.
PhB1 C10 I TTL QEI module 1 phase B.

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Table 19-7. Signals by Function, Except for GPIO (continued)

a
Function Pin Name Pin Number Pin Type Buffer Type Description
SSI0Clk M4 I/O TTL SSI module 0 clock.
SSI0Fss L4 I/O TTL SSI module 0 frame signal.
SSI0Rx L5 I TTL SSI module 0 receive.
SSI0Tx M5 O TTL SSI module 0 transmit.
SSI
SSI1Clk A11 I/O TTL SSI module 1 clock.
SSI1Fss B12 I/O TTL SSI module 1 frame signal.
SSI1Rx B11 I TTL SSI module 1 receive.
SSI1Tx A12 O TTL SSI module 1 transmit.
CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
System Control &
OSC0 L11 I Analog Main oscillator crystal input or an external clock
Clocks
reference input.
OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST H11 I TTL System reset input.
U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Rx H2 I TTL UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
UART
U1Tx H1 O TTL UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx K1 I TTL UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx K2 O TTL UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.

19.2.4 GPIO Pins and Alternate Functions

Table 19-8. GPIO Pins and Alternate Functions

IO Pin Number Multiplexed Function Multiplexed Function
PA0 L3 U0Rx
PA1 M3 U0Tx
PA2 M4 SSI0Clk
PA3 L4 SSI0Fss
PA4 L5 SSI0Rx
PA5 M5 SSI0Tx
PA6 L6 I2C1SCL
PA7 M6 I2C1SDA
PB0 E12 CCP0
PB1 D12 CCP2

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Table 19-8. GPIO Pins and Alternate Functions (continued)

IO Pin Number Multiplexed Function Multiplexed Function
PB2 C11 I2C0SCL
PB3 C12 I2C0SDA
PB4 A6 C0-
PB5 B7 C1-
PB6 A7 C0+
PB7 A8 TRST
PC0 A9 TCK SWCLK
PC1 B9 TMS SWDIO
PC2 B8 TDI
PC3 A10 TDO SWO
PC4 L1 PhA0
PC5 M1 C1+
PC6 M2 C2+
PC7 L2 C2-
PD0 G1 IDX0
PD1 G2 PWM1
PD2 H2 U1Rx
PD3 H1 U1Tx
PE0 A11 SSI1Clk
PE1 B12 SSI1Fss
PE2 B11 SSI1Rx
PE3 A12 SSI1Tx
PF0 M9 PhB0
PF1 H12 IDX1
PF2 J11 PWM4
PF3 J12 PWM5
PF4 L9 C0o
PF5 L8
PF6 M8 CCP1
PF7 K4
PG0 K1 U2Rx
PG1 K2 U2Tx
PG2 J1 PWM0
PG3 J2
PG4 K3 CCP3
PG5 M7
PG6 L7 PhA1
PG7 C10 PhB1
PH0 C9 PWM2
PH1 C8 PWM3
PH2 D11

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Table 19-8. GPIO Pins and Alternate Functions (continued)

IO Pin Number Multiplexed Function Multiplexed Function
PH3 D10 Fault

19.3 Connections for Unused Signals

Table 19-9 on page 650 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 100-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.

Table 19-9. Connections for Unused Signals (100-pin LQFP)

Function Signal Name Pin Number Acceptable Practice Preferred Practice
ADC ADC0 1 NC GNDA
ADC1 2
ADC2 5
ADC3 6
ADC4 100
ADC5 99
ADC6 96
ADC7 95
GPIO All unused GPIOs - NC GND
HIB 51 NC NC
VBAT 55 NC GND
Hibernate WAKE 50 NC GND
XOSC0 52 NC GND
XOSC1 53 NC NC
No Connects NC - NC NC
OSC0 48 NC GND
OSC1 49 NC NC
System Control
RST 64 Pull up as shown in Figure Connect through a capacitor
5-1 on page 173 to GND as close to pin as
possible

Table 19-10 on page 651 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 108-pin BGA package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.

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Table 19-10. Connections for Unused Signals, 108-pin BGA

Function Signal Name Pin Number Acceptable Practice Preferred Practice
ADC ADC0 B1 NC GNDA
ADC1 A1
ADC2 B3
ADC3 B2
ADC4 A2
ADC5 A3
ADC6 B4
ADC7 A4
GPIO All unused GPIOs - NC GND
HIB M12 NC NC
VBAT L12 NC GND
Hibernate WAKE M10 NC GND
XOSC0 K11 NC GND
XOSC1 K12 NC NC
No Connects NC - NC NC
OSC0 L11 NC GND
OSC1 M11 NC NC
System Control
RST H11 Pull up as shown in Connect through a capacitor
Figure 5-1 on page 173 to GND as close to pin as
possible

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Operating Characteristics

20 Operating Characteristics
Table 20-1. Temperature Characteristics
Characteristic Symbol Value Unit
Industrial operating temperature range TA -40 to +85 °C
Unpowered storage temperature range TS -65 to +150 °C

Table 20-2. Thermal Characteristics

Characteristic Symbol Value Unit
a
Thermal resistance (junction to ambient) ΘJA 32 °C/W
b
Junction temperature TJ TA + (P • ΘJA) °C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.

a
Table 20-3. ESD Absolute Maximum Ratings
Parameter Name Min Nom Max Unit
VESDHBM - - 2.0 kV
VESDCDM - - 1.0 kV
VESDMM - - 100 V
a. All Stellaris parts are ESD tested following the JEDEC standard.

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21 Electrical Characteristics
21.1 DC Characteristics
21.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.

Table 21-1. Maximum Ratings

a Value
Characteristic Symbol Unit
Min Max
I/O supply voltage (VDD) VDD 0 4 V
Core supply voltage (VDD25) VDD25 0 3 V
Analog supply voltage (VDDA) VDDA 0 4 V
Battery supply voltage (VBAT) VBAT 0 4 V
Input voltage -0.3 5.5 V
VIN
Input voltage for a GPIO configured as an analog input -0.3 VDD + 0.3 V
Maximum current per output pins I - 25 mA
Maximum input voltage on a non-power pin when the VNON - 300 mV
microcontroller is unpowered
a. Voltages are measured with respect to GND.

Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).

21.1.2 Recommended DC Operating Conditions

For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.

Table 21-2. Recommended DC Operating Conditions

Parameter Parameter Name Min Nom Max Unit
VDD I/O supply voltage 3.0 3.3 3.6 V
VDD25 Core supply voltage 2.25 2.5 2.75 V
VDDA Analog supply voltage 3.0 3.3 3.6 V
VBAT Battery supply voltage 2.3 3.0 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V

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Table 21-2. Recommended DC Operating Conditions (continued)

Parameter Parameter Name Min Nom Max Unit
a
VOH High-level output voltage 2.4 - - V
VOLa Low-level output voltage - - 0.4 V
High-level source current, VOH=2.4 V
2-mA Drive 2.0 - - mA
IOH
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
Low-level sink current, VOL=0.4 V
2-mA Drive 2.0 - - mA
IOL
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
a. VOL and VOH shift to 1.2 V when using high-current GPIOs.

21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics

Table 21-3. LDO Regulator Characteristics

Parameter Parameter Name Min Nom Max Unit
Programmable internal (logic) power supply 2.25 2.5 2.75 V
VLDOOUT output value
Output voltage accuracy - 2% - %
tPON Power-on time - - 100 µs
tON Time on - - 200 µs
tOFF Time off - - 100 µs
VSTEP Step programming incremental voltage - 50 - mV
CLDO External filter capacitor size for internal power 1.0 - 3.0 µF
supply

21.1.4 GPIO Module Characteristics

Table 21-4. GPIO Module DC Characteristics

Parameter Parameter Name Min Nom Max Unit
RGPIOPU GPIO internal pull-up resistor 50 - 110 kΩ
RGPIOPD GPIO internal pull-down resistor 55 - 180 kΩ
a
ILKG GPIO input leakage current - - 2 µA
a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is
measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.

21.1.5 Power Specifications

The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):

■ VDD = 3.3 V

■ VDD25 = 2.50 V

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■ VBAT = 3.0 V

■ VDDA = 3.3 V

■ Temperature = 25°C

■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator

■ Main oscillator (MOSC) = enabled

■ Internal oscillator (IOSC) = disabled

Table 21-5. Detailed Power Specifications

3.3 V VDD, 2.5 V VDD25 3.0 V VBAT
Parameter VDDA
Parameter Conditions Unit
Name
Nom Max Nom Max Nom Max
a
Run mode 1 VDD25 = 2.50 V 3 pending 108 pendinga 0 pendinga mA
(Flash loop) Code= while(1){} executed out of
Flash
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 2 VDD25 = 2.50 V 0 pendinga 53 pendinga 0 pendinga mA
(Flash loop) Code= while(1){} executed out of
Flash
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_RUN
Run mode 1 VDD25 = 2.50 V 3 pendinga 102 pendinga 0 pendinga mA
(SRAM loop) Code= while(1){} executed in
SRAM
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 2 VDD25 = 2.50 V 0 pendinga 47 pendinga 0 pendinga mA
(SRAM loop) Code= while(1){} executed in
SRAM
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_SLEEP Sleep mode VDD25 = 2.50 V 0 pendinga 17 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_DEEPSLEEP Deep-Sleep LDO = 2.25 V 0.14 pendinga 0.18 pendinga 0 pendinga mA
mode Peripherals = All OFF
System Clock = IOSC30KHZ/64

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Table 21-5. Detailed Power Specifications (continued)

3.3 V VDD, 2.5 V VDD25 3.0 V VBAT
Parameter VDDA
Parameter Conditions Unit
Name
Nom Max Nom Max Nom Max
IDD_HIBERNATE Hibernate VBAT = 3.0 V 0 0 0 0 16 pendinga µA
mode VDD = 0 V
VDD25 = 0 V
VDDA = 0 V
Peripherals = All OFF
System Clock = OFF
Hibernate Module = 32 kHz
a. Pending characterization completion.

21.1.6 Flash Memory Characteristics

Table 21-6. Flash Memory Characteristics

Parameter Parameter Name Min Nom Max Unit
PECYC Number of guaranteed program/erase cycles 10,000 100,000 - cycles
a
before failure
TRET Data retention at average operating 10 - - years
temperature of 85˚C
TPROG Word program time 20 - - µs
TERASE Page erase time 20 - - ms
TME Mass erase time - - 250 ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.

21.1.7 Hibernation

Table 21-7. Hibernation Module DC Characteristics

Parameter Parameter Name Value Unit
VLOWBAT Low battery detect voltage 2.35 V
RWAKEPU WAKE internal pull-up resistor 200 kΩ

21.2 AC Characteristics
21.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.

Figure 21-1. Load Conditions

pin CL = 50 pF

GND

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21.2.2 Clocks

Table 21-8. Phase Locked Loop (PLL) Characteristics

Parameter Parameter Name Min Nom Max Unit
a
fref_crystal Crystal reference 3.579545 - 8.192 MHz
fref_ext External clock referencea 3.579545 - 8.192 MHz
b
fpll PLL frequency - 400 - MHz
TREADY PLL lock time - - 0.5 ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.

Table 21-9 on page 657 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).

Table 21-9. Actual PLL Frequency

XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error
0x4 3.5795 400.904 0.0023%
0x5 3.6864 398.1312 0.0047%
0x6 4.0 400 -
0x7 4.096 401.408 0.0035%
0x8 4.9152 398.1312 0.0047%
0x9 5.0 400 -
0xA 5.12 399.36 0.0016%
0xB 6.0 400 -
0xC 6.144 399.36 0.0016%
0xD 7.3728 398.1312 0.0047%
0xE 8.0 400 0.0047%
0xF 8.192 398.6773333 0.0033%

Table 21-10. Clock Characteristics

Parameter Parameter Name Min Nom Max Unit
fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz
fIOSC30KHZ Internal 30 KHz oscillator frequency 15 30 45 KHz
fXOSC Hibernation module oscillator frequency - 4.194304 - MHz
fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz
fXOSC_EXT External clock reference for hibernation - 32.768 - KHz
module
fMOSC Main oscillator frequency 1 - 8.192 MHz
tMOSC_per Main oscillator period 125 - 1000 ns
fref_crystal_bypass Crystal reference using the main oscillator 1 - 8.192 MHz
a
(PLL in BYPASS mode)
fref_ext_bypass External clock reference (PLL in BYPASS 0 - 50 MHz
a
mode)
fsystem_clock System clock 0 - 50 MHz
a. The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly.

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Table 21-11. Crystal Characteristics

Parameter Name Value Units
Frequency 8 6 4 3.5 MHz
a
Frequency tolerance ±50 ±50 ±50 ±50 ppm
Oscillation mode Parallel Parallel Parallel Parallel -
Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF
Motional inductance (typ) 14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max) 10 10 10 10 pF
Load capacitance (typ) 16 16 16 16 pF
Drive level (typ) 100 100 100 100 µW
a. This tolerance provides a guard band for temperature stability and aging drift.

21.2.2.1 System Clock Specifications with ADC Operation

Table 21-12. System Clock Characteristics with ADC Operation

Parameter Parameter Name Min Nom Max Unit
fsysadc System clock frequency when the ADC module is 16 - - MHz
operating (when PLL is bypassed)

21.2.3 JTAG and Boundary Scan

Table 21-13. JTAG Characteristics

Parameter Parameter Parameter Name Min Nom Max Unit
No.
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK clock Low time - tTCK/2 - ns
J4 tTCK_HIGH TCK clock High time - tTCK/2 - ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
2-mA drive 23 35 ns
J11 TCK fall to Data 4-mA drive 15 26 ns
-
t TDO_ZDV Valid from High-Z 8-mA drive 14 25 ns
8-mA drive with slew rate control 18 29 ns
2-mA drive 21 35 ns
J12 TCK fall to Data 4-mA drive 14 25 ns
Valid from Data -
t TDO_DV Valid 8-mA drive 13 24 ns
8-mA drive with slew rate control 18 28 ns

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Table 21-13. JTAG Characteristics (continued)

Parameter Parameter Parameter Name Min Nom Max Unit
No.
2-mA drive 9 11 ns
J13 TCK fall to High-Z 4-mA drive 7 9 ns
-
t TDO_DVZ from Data Valid 8-mA drive 6 8 ns
8-mA drive with slew rate control 7 9 ns
J14 tTRST TRST assertion time 100 - - ns
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns

Figure 21-2. JTAG Test Clock Input Timing

J2

J3 J4

TCK

J6 J5

Figure 21-3. JTAG Test Access Port (TAP) Timing

TCK

J7 J8 J7 J8

TMS TMS Input Valid TMS Input Valid

J9 J10 J9 J10

TDI TDI Input Valid TDI Input Valid

J11 J12 J13

TDO TDO Output Valid TDO Output Valid

Figure 21-4. JTAG TRST Timing

TCK

J14 J15

TRST

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21.2.4 Reset

Table 21-14. Reset Characteristics

Parameter Parameter Parameter Name Min Nom Max Unit
No.
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-On Reset timeout - 10 - ms
R4 TBOR Brown-Out timeout - 500 - µs
R5 TIRPOR Internal reset timeout after POR 6 - 11 ms
a
R6 TIRBOR Internal reset timeout after BOR 0 - 1 µs
R7 TIRHWR Internal reset timeout after hardware reset 0 - 1 ms
(RST pin)
R8 TIRSWR Internal reset timeout after software-initiated 2.5 - 20 µs
system reset a
R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 µs
Supply voltage (VDD) rise time (0V-3.3V), - - 100 ms
power on reset
R10 TVDDRISE
Supply voltage (VDD) rise time (0V-3.3V), - - 250 µs
waking from hibernation
R11 TMIN Minimum RST pulse width 2 - - µs
a. 20 * t MOSC_per

Figure 21-5. External Reset Timing (RST)

RST
R11 R7

/Reset
(Internal)

Figure 21-6. Power-On Reset Timing

R1

VDD
R3
/POR
(Internal)
R5

/Reset
(Internal)

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Figure 21-7. Brown-Out Reset Timing

R2

VDD
R4
/BOR
(Internal)
R6
/Reset
(Internal)

Figure 21-8. Software Reset Timing

SW Reset
R8

/Reset
(Internal)

Figure 21-9. Watchdog Reset Timing

WDOG
Reset
(Internal)
R9

/Reset
(Internal)

21.2.5 Sleep Modes

a
Table 21-15. Sleep Modes AC Characteristics
Parameter No Parameter Parameter Name Min Nom Max Unit
D1 tWAKE_S Time to wake from interrupt in sleep or - - 7 system clocks
deep-sleep mode, not using the PLL
D2 tWAKE_PLL_S Time to wake from interrupt in sleep or - - TREADY ms
deep-sleep mode when using the PLL
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.

21.2.6 Hibernation Module

The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 VDC or powered down with the same external voltage
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.

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Table 21-16. Hibernation Module AC Characteristics

Parameter Parameter Parameter Name Min Nom Max Unit
No
H1 tHIB_LOW Internal 32.768 KHz clock reference rising - 200 - μs
edge to /HIB asserted
H2 tHIB_HIGH Internal 32.768 KHz clock reference rising - 30 - μs
edge to /HIB deasserted
H3 tWAKE_ASSERT /WAKE assertion time 62 - - μs
H4 tWAKETOHIB /WAKE assert to /HIB desassert 62 - 124 μs
a
H5 tXOSC_SETTLE XOSC settling time 20 - - ms
H6 tHIB_REG_ACCESS Access time to or from a non-volatile register 92 - - μs
in HIB module to complete
H7 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum - - 250 μs
operational level
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).

Figure 21-10. Hibernation Module Timing

32.768 KHz
(internal)
H1 H2

HIB

H4

WAKE

H3

21.2.7 General-Purpose I/O (GPIO)

Note: All GPIOs are 5 V-tolerant.

Table 21-17. GPIO Characteristics

Parameter Parameter Name Condition Min Nom Max Unit
2-mA drive 17 26 ns
GPIO Rise Time 4-mA drive 9 13 ns
tGPIOR (from 20% to 80% -
of VDD) 8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
2-mA drive 17 25 ns
GPIO Fall Time 4-mA drive 8 12 ns
tGPIOF (from 80% to 20% -
of VDD) 8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns

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21.2.8 Analog-to-Digital Converter

a
Table 21-18. ADC Characteristics
Parameter Parameter Name Min Nom Max Unit
Maximum single-ended, full-scale analog input - - 3.0 V
voltage
Minimum single-ended, full-scale analog input 0.0 - - V
VADCIN voltage
Maximum differential, full-scale analog input voltage - - 1.5 V
Minimum differential, full-scale analog input voltage 0.0 - - V
N Resolution 10 bits
b
fADC ADC internal clock frequency 14 16 18 MHz
c
tADCCONV Conversion time 1 µs
c
f ADCCONV Conversion rate 1000 k samples/s
tLT Latency from trigger to start of conversion - 2 - system clocks
IL ADC input leakage - - ±3.0 µA
RADC ADC equivalent resistance - - 10 kΩ
CADC ADC equivalent capacitance 0.9 1.0 1.1 pF
EL Integral nonlinearity error - - ±3 LSB
ED Differential nonlinearity error - - ±2 LSB
d
EO Offset error - - +6 LSB
EG Full-scale gain error - - ±3 LSB
ETS Temperature sensor accuracy - - ±5 °C
a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band
gap circuit.
b. The ADC must be clocked from the PLL or directly from an external clock source to operate properly.
c. The conversion time and rate scale from the specified number if the ADC internal clock frequency is any value other than
16 MHz.
d. The offset error listed above is the conversion result with 0 V applied to the ADC input.

Figure 21-11. ADC Input Equivalency Diagram

Stellaris® Microcontroller
VDD

RADC
10-bit
converter

VIN IL
CADC

Sample and hold

ADC converter

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Table 21-19. ADC Module Internal Reference Characteristics

Parameter Parameter Name Min Nom Max Unit
VREFI Internal voltage reference for ADC - 3.0 - V
EIR Internal voltage reference error - - ±2.5 %

21.2.9 Synchronous Serial Interface (SSI)

Table 21-20. SSI Characteristics

Parameter Parameter Parameter Name Min Nom Max Unit
No.
S1 tclk_per SSIClk cycle time 2 - 65024 system clocks
S2 tclk_high SSIClk high time - 0.5 - t clk_per
S3 tclk_low SSIClk low time - 0.5 - t clk_per
a
S4 tclkrf SSIClk rise/fall time - 6 10 ns
S5 tDMd Data from master valid delay time 0 - 1 system clocks
S6 tDMs Data from master setup time 1 - - system clocks
S7 tDMh Data from master hold time 2 - - system clocks
S8 tDSs Data from slave setup time 1 - - system clocks
S9 tDSh Data from slave hold time 2 - - system clocks
a. Note that the delays shown are using 8-mA drive strength.

Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement

S1
S2 S4

SSIClk

S3

SSIFss

SSITx
MSB LSB
SSIRx
4 to 16 bits

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Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer

S2 S1

SSIClk

S3

SSIFss

SSITx MSB LSB

8-bit control

SSIRx 0 MSB LSB

4 to 16 bits output data

Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1

S1
S4 S2

SSIClk
(SPO=0)
S3

SSIClk
(SPO=1)
S6 S7

SSITx
MSB LSB
(master)
S5 S8 S9

SSIRx
MSB LSB
(slave)

SSIFss

21.2.10 Inter-Integrated Circuit (I2C) Interface

Table 21-21. I2C Characteristics

Parameter Parameter Parameter Name Min Nom Max Unit
No.
a
I1 tSCH Start condition hold time 36 - - system clocks
a
I2 tLP Clock Low period 36 - - system clocks
b
I3 tSRT I2CSCL/I2CSDA rise time (VIL =0.5 V - - (see note ns
to V IH =2.4 V) b)

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Table 21-21. I2C Characteristics (continued)

Parameter Parameter Parameter Name Min Nom Max Unit
No.
a
I4 tDH Data hold time 2 - - system clocks
c
I5 tSFT I2CSCL/I2CSDA fall time (VIH =2.4 V - 9 10 ns
to V IL =0.5 V)
a
I6 tHT Clock High time 24 - - system clocks
a
I7 tDS Data setup time 18 - - system clocks
a
I8 tSCSR Start condition setup time (for repeated 36 - - system clocks
start condition only)
a
I9 tSCS Stop condition setup time 24 - - system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.

Figure 21-15. I2C Timing

I2 I6 I5

I2CSCL

I1 I4 I7 I8 I3 I9

I2CSDA

21.2.11 Analog Comparator

Table 21-22. Analog Comparator Characteristics

Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ±10 ±25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Common mode rejection ratio 50 - - dB
TRT Response time - - 1 µs
TMC Comparator mode change to Output Valid - - 10 µs

Table 21-23. Analog Comparator Voltage Reference Characteristics

Parameter Parameter Name Min Nom Max Unit
RHR Resolution high range - VDD/31 - LSB
RLR Resolution low range - VDD/23 - LSB
AHR Absolute accuracy high range - - ±1/2 LSB
ALR Absolute accuracy low range - - ±1/4 LSB

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A Serial Flash Loader

A.1 Serial Flash Loader
®
The Stellaris serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.

A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.

A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device
which is calculated as follows:

Max Baud Rate = System Clock Frequency / 16

In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.

A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 478 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running

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the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.

A.3 Packet Handling

All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.

A.3.1 Packet Format

All packets sent and received from the device use the following byte-packed format.

struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};

ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.

A.3.2 Sending Packets

The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 670).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.

A.3.3 Receiving Packets

The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the

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flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.

A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.

A.4.1 COMMAND_PING (0X20)

This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:

Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;

The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.

A.4.2 COMMAND_GET_STATUS (0x23)

This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.

Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS

A.4.3 COMMAND_DOWNLOAD (0x21)

This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:

Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]

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Serial Flash Loader

Byte[8] = Program Size [23:16]

Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]

A.4.4 COMMAND_SEND_DATA (0x24)

This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.

Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]

A.4.5 COMMAND_RUN (0x22)

This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.

Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]

A.4.6 COMMAND_RESET (0x25)

This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.

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Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET

The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.

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Register Quick Reference

B Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The Cortex-M3 Processor

R0, type R/W, , reset - (see page 59)
DATA
DATA
R1, type R/W, , reset - (see page 59)
DATA
DATA
R2, type R/W, , reset - (see page 59)
DATA
DATA
R3, type R/W, , reset - (see page 59)
DATA
DATA
R4, type R/W, , reset - (see page 59)
DATA
DATA
R5, type R/W, , reset - (see page 59)
DATA
DATA
R6, type R/W, , reset - (see page 59)
DATA
DATA
R7, type R/W, , reset - (see page 59)
DATA
DATA
R8, type R/W, , reset - (see page 59)
DATA
DATA
R9, type R/W, , reset - (see page 59)
DATA
DATA
R10, type R/W, , reset - (see page 59)
DATA
DATA
R11, type R/W, , reset - (see page 59)
DATA
DATA
R12, type R/W, , reset - (see page 59)
DATA
DATA
SP, type R/W, , reset - (see page 60)
SP
SP
LR, type R/W, , reset 0xFFFF.FFFF (see page 61)
LINK
LINK
PC, type R/W, , reset - (see page 62)
PC
PC

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSR, type R/W, , reset 0x0100.0000 (see page 63)
N Z C V Q ICI / IT THUMB
ICI / IT ISRNUM
PRIMASK, type R/W, , reset 0x0000.0000 (see page 67)

PRIMASK
FAULTMASK, type R/W, , reset 0x0000.0000 (see page 68)

FAULTMASK

BASEPRI, type R/W, , reset 0x0000.0000 (see page 69)

BASEPRI
CONTROL, type R/W, , reset 0x0000.0000 (see page 70)

ASP TMPL

Cortex-M3 Peripherals
System Timer (SysTick) Registers
Base 0xE000.E000
STCTRL, type R/W, offset 0x010, reset 0x0000.0000
COUNT
CLK_SRC INTEN ENABLE
STRELOAD, type R/W, offset 0x014, reset 0x0000.0000
RELOAD
RELOAD
STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000
CURRENT
CURRENT

Cortex-M3 Peripherals
Nested Vectored Interrupt Controller (NVIC) Registers
Base 0xE000.E000
EN0, type R/W, offset 0x100, reset 0x0000.0000
INT
INT
EN1, type R/W, offset 0x104, reset 0x0000.0000

INT
DIS0, type R/W, offset 0x180, reset 0x0000.0000
INT
INT
DIS1, type R/W, offset 0x184, reset 0x0000.0000

INT
PEND0, type R/W, offset 0x200, reset 0x0000.0000
INT
INT
PEND1, type R/W, offset 0x204, reset 0x0000.0000

INT
UNPEND0, type R/W, offset 0x280, reset 0x0000.0000
INT
INT

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Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNPEND1, type R/W, offset 0x284, reset 0x0000.0000

INT
ACTIVE0, type RO, offset 0x300, reset 0x0000.0000
INT
INT
ACTIVE1, type RO, offset 0x304, reset 0x0000.0000

INT
PRI0, type R/W, offset 0x400, reset 0x0000.0000
INTD INTC
INTB INTA
PRI1, type R/W, offset 0x404, reset 0x0000.0000
INTD INTC
INTB INTA
PRI2, type R/W, offset 0x408, reset 0x0000.0000
INTD INTC
INTB INTA
PRI3, type R/W, offset 0x40C, reset 0x0000.0000
INTD INTC
INTB INTA
PRI4, type R/W, offset 0x410, reset 0x0000.0000
INTD INTC
INTB INTA
PRI5, type R/W, offset 0x414, reset 0x0000.0000
INTD INTC
INTB INTA
PRI6, type R/W, offset 0x418, reset 0x0000.0000
INTD INTC
INTB INTA
PRI7, type R/W, offset 0x41C, reset 0x0000.0000
INTD INTC
INTB INTA
PRI8, type R/W, offset 0x420, reset 0x0000.0000
INTD INTC
INTB INTA
PRI9, type R/W, offset 0x424, reset 0x0000.0000
INTD INTC
INTB INTA
PRI10, type R/W, offset 0x428, reset 0x0000.0000
INTD INTC
INTB INTA
SWTRIG, type WO, offset 0xF00, reset 0x0000.0000

INTID

Cortex-M3 Peripherals
System Control Block (SCB) Registers
Base 0xE000.E000
CPUID, type RO, offset 0xD00, reset 0x411F.C231
IMP VAR CON
PARTNO REV

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000
NMISET PENDSV UNPENDSV PENDSTSET PENDSTCLR ISRPRE ISRPEND VECPEND
VECPEND RETBASE VECACT
VTABLE, type R/W, offset 0xD08, reset 0x0000.0000
BASE OFFSET
OFFSET
APINT, type R/W, offset 0xD0C, reset 0xFA05.0000
VECTKEY
ENDIANESS PRIGROUP SYSRESREQ VECTCLRACT VECTRESET

SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000

SEVONPEND SLEEPDEEP SLEEPEXIT

CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000

STKALIGN BFHFNMIGN DIV0 UNALIGNED MAINPEND BASETHR

SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000
USAGE
BUS MEM
SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000
SVC

SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000

TICK PENDSV
DEBUG
SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000
USAGE BUS MEM
SVC BUSP MEMP USAGEP TICK PNDSV MON SVCA USGA BUSA MEMA
FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000
DIV0 UNALIGN NOCP INVPC INVSTAT UNDEF
BFARV BSTKE BUSTKE IMPRE PRECISE IBUS MMARV MSTKE MUSTKE DERR IERR
HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000
DBG FORCED
VECT
MMADDR, type R/W, offset 0xD34, reset -
ADDR
ADDR
FAULTADDR, type R/W, offset 0xD38, reset -
ADDR
ADDR

Cortex-M3 Peripherals
Memory Protection Unit (MPU) Registers
Base 0xE000.E000
MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800
IREGION
DREGION SEPARATE

MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000

PRIVDEFEN HFNMIENA ENABLE

MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000

NUMBER

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE

System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset - (see page 186)
VER CLASS
MAJOR MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 188)

BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 (see page 189)

VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 190)

PLLLRIS BORRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 191)

PLLLIM BORIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 192)

PLLLMIS BORMIS
RESC, type R/W, offset 0x05C, reset - (see page 193)

SW WDT BOR POR EXT

RCC, type R/W, offset 0x060, reset 0x078E.3AD1 (see page 194)
ACG SYSDIV USESYSDIV USEPWMDIV PWMDIV
PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset - (see page 198)

F R

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCC2, type R/W, offset 0x070, reset 0x0780.2810 (see page 199)
USERCC2 SYSDIV2
PWRDN2 BYPASS2 OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 201)
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset - (see page 202)
VER FAM PARTNO
PINCOUNT TEMP PKG ROHS QUAL
DC0, type RO, offset 0x008, reset 0x00FF.007F (see page 204)
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0011.33FF (see page 205)
PWM ADC
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
DC2, type RO, offset 0x014, reset 0x070F.5337 (see page 207)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
DC3, type RO, offset 0x018, reset 0x8FFF.B7FF (see page 209)
32KHZ CCP3 CCP2 CCP1 CCP0 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
PWMFAULT C2PLUS C2MINUS C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
DC4, type RO, offset 0x01C, reset 0x0000.00FF (see page 212)

GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 213)
PWM ADC
MAXADCSPD HIB WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 215)
PWM ADC
MAXADCSPD HIB WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 217)
PWM ADC
HIB WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 219)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 222)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 225)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 228)

GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 230)

GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 232)

GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 234)
PWM ADC
HIB WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 235)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 237)

GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA

Hibernation Module
Base 0x400F.C000
HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 (see page 247)
RTCC
RTCC
HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF (see page 248)
RTCM0
RTCM0
HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF (see page 249)
RTCM1
RTCM1
HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF (see page 250)
RTCLD
RTCLD
HIBCTL, type R/W, offset 0x010, reset 0x8000.0000 (see page 251)

VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN

HIBIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 253)

EXTW LOWBAT RTCALT1 RTCALT0

HIBRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 254)

EXTW LOWBAT RTCALT1 RTCALT0

HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 255)

EXTW LOWBAT RTCALT1 RTCALT0

HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 (see page 256)

EXTW LOWBAT RTCALT1 RTCALT0

HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF (see page 257)

TRIM
HIBDATA, type R/W, offset 0x030-0x12C, reset - (see page 258)
RTD
RTD

Internal Memory
Flash Memory Control Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT MERASE ERASE WRITE
FCRIS, type RO, offset 0x00C, reset 0x0000.0000

PRIS ARIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000

PMASK AMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000

PMISC AMISC

Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31

USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW DATA
DATA DBG1 DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE

General-Purpose Input/Outputs (GPIOs)

GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 300)

DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 301)

DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 302)

IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 303)

IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 304)

IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 305)

IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 306)

RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 307)

MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 308)

IC
GPIOAFSEL, type R/W, offset 0x420, reset - (see page 309)

AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 311)

DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 312)

DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 313)

DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 314)

ODE

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPUR, type R/W, offset 0x510, reset - (see page 315)

PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 316)

PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 317)

SRL
GPIODEN, type R/W, offset 0x51C, reset - (see page 318)

DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 319)
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset - (see page 320)

CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 322)

PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 323)

PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 324)

PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 325)

PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 326)

PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 327)

PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 328)

PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 329)

PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 330)

CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 331)

CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 332)

CID2

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 333)

CID3

General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 347)

GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 348)

TAAMS TACMR TAMR

GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 350)

TBAMS TBCMR TBMR

GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 352)

TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 355)

CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM

GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 357)

CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS

GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 358)

CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS

GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 359)

CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT

GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 361)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 362)

TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 363)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 364)

TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 365)

TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 366)

TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 367)

TAPSMR

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 368)

TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 369)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 370)

TBRL

Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 375)
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 376)
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (see page 377)

RESEN INTEN
WDTICR, type WO, offset 0x00C, reset - (see page 378)
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 379)

WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 380)

WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 381)

STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 382)
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 383)

PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 384)

PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 385)

PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 386)

PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 387)

PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 388)

PID1

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Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 389)

PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 390)

PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 391)

CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 392)

CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 393)

CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 394)

CID3

Analog-to-Digital Converter (ADC)

Base 0x4003.8000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000 (see page 405)

ASEN3 ASEN2 ASEN1 ASEN0

ADCRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 406)

INR3 INR2 INR1 INR0

ADCIM, type R/W, offset 0x008, reset 0x0000.0000 (see page 407)

MASK3 MASK2 MASK1 MASK0

ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000 (see page 408)

IN3 IN2 IN1 IN0

ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000 (see page 409)

OV3 OV2 OV1 OV0

ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000 (see page 410)

EM3 EM2 EM1 EM0

ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000 (see page 414)

UV3 UV2 UV1 UV0

ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210 (see page 415)

SS3 SS2 SS1 SS0

ADCPSSI, type WO, offset 0x028, reset - (see page 417)

SS3 SS2 SS1 SS0

ADCSAC, type R/W, offset 0x030, reset 0x0000.0000 (see page 418)

AVG
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000 (see page 419)
MUX7 MUX6 MUX5 MUX4
MUX3 MUX2 MUX1 MUX0

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000 (see page 421)
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSFIFO0, type RO, offset 0x048, reset - (see page 424)

DATA
ADCSSFIFO1, type RO, offset 0x068, reset - (see page 424)

DATA
ADCSSFIFO2, type RO, offset 0x088, reset - (see page 424)

DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset - (see page 424)

DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100 (see page 425)

FULL EMPTY HPTR TPTR

ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100 (see page 425)

FULL EMPTY HPTR TPTR

ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100 (see page 425)

FULL EMPTY HPTR TPTR

ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 (see page 425)

FULL EMPTY HPTR TPTR

ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000 (see page 426)

MUX3 MUX2 MUX1 MUX0

ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000 (see page 426)

MUX3 MUX2 MUX1 MUX0

ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000 (see page 427)

TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000 (see page 427)

TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 429)

MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 (see page 430)

TS0 IE0 END0 D0

ADCTMLB, type R/W, offset 0x100, reset 0x0000.0000 (see page 431)

LB

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Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Universal Asynchronous Receivers/Transmitters (UARTs)

UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 442)

OE BE PE FE DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) (see page 444)

OE BE PE FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) (see page 444)

DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 446)

TXFE RXFF TXFF RXFE BUSY

UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 448)

ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 449)

DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 450)

DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 451)

SPS WLEN FEN STP2 EPS PEN BRK

UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 453)

RXE TXE LBE SIRLP SIREN UARTEN

UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 455)

RXIFLSEL TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 457)

OEIM BEIM PEIM FEIM RTIM TXIM RXIM

UARTRIS, type RO, offset 0x03C, reset 0x0000.0000 (see page 459)

OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS

UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 460)

OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS

UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 461)

OEIC BEIC PEIC FEIC RTIC TXIC RXIC

UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 463)

PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 464)

PID5

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 465)

PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 466)

PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 467)

PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 468)

PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 469)

PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 470)

PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 471)

CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 472)

CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 473)

CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 474)

CID3

Synchronous Serial Interface (SSI)

SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 488)

SCR SPH SPO FRF DSS

SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 490)

SOD MS SSE LBM

SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 492)

DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 493)

BSY RFF RNE TNF TFE

SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 495)

CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 496)

TXIM RXIM RTIM RORIM

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 498)

TXRIS RXRIS RTRIS RORRIS

SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 499)

TXMIS RXMIS RTMIS RORMIS

SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 500)

RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 501)

PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 502)

PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 503)

PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 504)

PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 505)

PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 506)

PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 507)

PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 508)

PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 509)

CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 510)

CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 511)

CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 512)

CID3

Inter-Integrated Circuit (I2C) Interface

I2C Master
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000

SA R/S

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads)

BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY

I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes)

ACK STOP START RUN

I2CMDR, type R/W, offset 0x008, reset 0x0000.0000

DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001

TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000

IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000

RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000

MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000

IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000

SFE MFE LPBK

Inter-Integrated Circuit (I2C) Interface

I2C Slave
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000

OAR
I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Reads)

FBR TREQ RREQ

I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Writes)

DA
I2CSDR, type R/W, offset 0x808, reset 0x0000.0000

DATA
I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000

DATAIM
I2CSRIS, type RO, offset 0x810, reset 0x0000.0000

DATARIS
I2CSMIS, type RO, offset 0x814, reset 0x0000.0000

DATAMIS

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Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2CSICR, type WO, offset 0x818, reset 0x0000.0000

DATAIC

Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 556)

IN2 IN1 IN0

ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 557)

IN2 IN1 IN0

ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 558)

IN2 IN1 IN0

ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 559)

EN RNG VREF
ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 560)

OVAL
ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 (see page 560)

OVAL
ACSTAT2, type RO, offset 0x060, reset 0x0000.0000 (see page 560)

OVAL
ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 561)

TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV

ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 561)

TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV

ACCTL2, type R/W, offset 0x064, reset 0x0000.0000 (see page 561)

TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV

Pulse Width Modulator (PWM)

Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 573)
GlobalSync2

GlobalSync1

GlobalSync0

PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 (see page 574)

Sync2 Sync1 Sync0

PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 (see page 575)

PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En

PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 576)

PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 (see page 577)

Fault5 Fault4 Fault3 Fault2 Fault1 Fault0

PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 (see page 578)
IntFault

IntPWM2 IntPWM1 IntPWM0

PWMRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 579)
IntFault

IntPWM2 IntPWM1 IntPWM0

PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 580)
IntFault

IntPWM2 IntPWM1 IntPWM0

PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 581)

Fault
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 582)

CmpBUpd CmpAUpd LoadUpd Debug Mode Enable

PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 582)

CmpBUpd CmpAUpd LoadUpd Debug Mode Enable

PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 582)

CmpBUpd CmpAUpd LoadUpd Debug Mode Enable

PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 (see page 584)

TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 (see page 584)

TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 (see page 584)

TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 (see page 587)

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 (see page 587)

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 (see page 587)

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 (see page 588)

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000 (see page 588)

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000 (see page 588)

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero

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Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 (see page 589)

Load
PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000 (see page 589)

Load
PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000 (see page 589)

Load
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 (see page 590)

Count
PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000 (see page 590)

Count
PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000 (see page 590)

Count
PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 (see page 591)

CompA
PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000 (see page 591)

CompA
PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000 (see page 591)

CompA
PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 (see page 592)

CompB
PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 (see page 592)

CompB
PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 (see page 592)

CompB
PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 (see page 593)

ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 593)

ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000 (see page 593)

ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 (see page 596)

ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 596)

ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000 (see page 596)

ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero

PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 (see page 599)

Enable
PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 599)

Enable
PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000 (see page 599)

Enable
PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 (see page 600)

RiseDelay
PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000 (see page 600)

RiseDelay
PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000 (see page 600)

RiseDelay
PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 (see page 601)

FallDelay
PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 601)

FallDelay
PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 (see page 601)

FallDelay

Quadrature Encoder Interface (QEI)

QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
QEICTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 608)

STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
QEISTAT, type RO, offset 0x004, reset 0x0000.0000 (see page 610)

Direction Error
QEIPOS, type R/W, offset 0x008, reset 0x0000.0000 (see page 611)
Position
Position
QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000 (see page 612)
MaxPos
MaxPos
QEILOAD, type R/W, offset 0x010, reset 0x0000.0000 (see page 613)
Load
Load
QEITIME, type RO, offset 0x014, reset 0x0000.0000 (see page 614)
Time
Time

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Register Quick Reference

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QEICOUNT, type RO, offset 0x018, reset 0x0000.0000 (see page 615)
Count
Count
QEISPEED, type RO, offset 0x01C, reset 0x0000.0000 (see page 616)
Speed
Speed
QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000 (see page 617)

IntError IntDir IntTimer IntIndex

QEIRIS, type RO, offset 0x024, reset 0x0000.0000 (see page 618)

IntError IntDir IntTimer IntIndex

QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000 (see page 619)

IntError IntDir IntTimer IntIndex

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C Ordering and Contact Information

C.1 Ordering Information
®
The figure below defines the full set of potential orderable part numbers for all the Stellaris LM3S
microcontrollers. See the Package Option Addendum for the valid orderable part numbers for the
LM3S1968 microcontroller.

LM3Snnnn–gppss–rrm

Part Number
nnn = Sandstorm-class parts Shipping Medium
nnnn = All other Stellaris® parts T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Temperature
E = –40°C to +105°C Revision
I = –40°C to +85°C
Package Speed
BZ = 108-ball BGA 20 = 20 MHz
QC = 100-pin LQFP 25 = 25 MHz
QN = 48-pin LQFP 50 = 50 MHz
QR = 64-pin LQFP 80 = 80 MHz

C.2 Part Markings

The Stellaris microcontrollers are marked with an identifying number. This code contains the following
information:

■ The first line indicates the part number, for example, LM3S9B90.

■ In the second line, the first eight characters indicate the temperature, package, speed, revision,
and product status. For example in the figure below, IQC80C0X indicates an Industrial temperature
(I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. The letter immediately
following the revision indicates product status. An X indicates experimental and requires a waiver;
an S indicates the part is fully qualified and released to production.

■ The remaining characters contain internal tracking numbers.

C.3 Kits
The Stellaris Family provides the hardware and software tools that engineers need to begin
development quickly.

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Ordering and Contact Information

■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files

■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers
before purchase

■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box

See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor.

C.4 Support Information

For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you:
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm.

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D Package Information
D.1 100-Pin LQFP Package
D.1.1 Package Dimensions

Figure D-1. Stellaris LM3S1968 100-Pin LQFP Package Dimensions

Note: The following notes apply to the package drawing.

1. All dimensions shown in mm.

2. Dimensions shown are nominal with tolerances indicated.

3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.

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Package Information

Body +2.00 mm Footprint, 1.4 mm package thickness

Symbols Leads 100L
A Max. 1.60
A1 - 0.05 Min./0.15 Max.
A2 ±0.05 1.40
D ±0.20 16.00
D1 ±0.05 14.00
E ±0.20 16.00
E1 ±0.05 14.00
L +0.15/-0.10 0.60
e Basic 0.50
b +0.05 0.22
θ - 0˚-7˚
ddd Max. 0.08
ccc Max. 0.08
JEDEC Reference Drawing MS-026
Variation Designator BED

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D.1.2 Tray Dimensions

Figure D-2. 100-Pin LQFP Tray Dimensions

D.1.3 Tape and Reel Dimensions

Note: In the figure that follows, pin 1 is located in the top right corner of the device.

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Package Information

Figure D-3. 100-Pin LQFP Tape and Reel Dimensions

THIS IS A COMPUTER GENERATED

UNCONTROLLED DOCUMENT
06.01.2003
PRINTED ON 06.01.2003
06.01.2003
MUST NOT BE REPRODUCED WITHOUT WRITTEN
PERMISSION FROM SUMICARRIER (S) PTE LTD 06.01.2003

06.01.2003

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Stellaris LM3S1968 Microcontroller

D.2 108-Ball BGA Package

D.2.1 Package Dimensions

Figure D-4. Stellaris LM3S1968 108-Ball BGA Package Dimensions

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Package Information

Note: The following notes apply to the package drawing.

Symbols MIN NOM MAX

A 1.22 1.36 1.50
A1 0.29 0.34 0.39
A3 0.65 0.70 0.75
c 0.28 0.32 0.36
D 9.85 10.00 10.15
D1 8.80 BSC
E 9.85 10.00 10.15
E1 8.80 BSC
b 0.43 0.48 0.53
bbb .20
ddd .12
e 0.80 BSC
f - 0.60 -
M 12
n 108
REF: JEDEC MO-219F

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Stellaris LM3S1968 Microcontroller

D.2.2 Tray Dimensions

Figure D-5. 108-Ball BGA Tray Dimensions

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Package Information

D.2.3 Tape and Reel Dimensions

Figure D-6. 108-Ball BGA Tape and Reel Dimensions

C-PAK PTE LTD

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 PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM3S1968-IQC50-A2 NRND LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LM3S1968
IQC50
LM3S1968-IQC50-A2T NRND LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LM3S1968
IQC50

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2022

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Feb-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3S1968-IQC50-A2T LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Feb-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3S1968-IQC50-A2T LQFP PZ 100 1000 367.0 367.0 45.0

Pack Materials-Page 2
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