12/16/21, 5:04 PM DESIGN FOR TEST (DFT): DFT Interview Questions

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DESIGN FOR TEST (DFT)

Tuesday, 26 April 2016 About Me

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DFT Interview Questions
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DFT  Interview Questions(100 most commonly asked DFT Interview Questions ):

Blog Archive

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2016
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Scan Insertion:

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April
(1)
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1).Explain scan insertion steps?

DFT Interview Questions
2).what are the basic things that needs to taken care for Scan Insertion?

3).what are the DRC Violations that u have faced during Scan Insertion and how did you fix those
?

4).what is test point Insertion? Can you tell and explain one TestPoint Insertion scenario?

5).Some Questions on design complexity like what was the gate and flops count of yours recent
project?

6).Explain Decompression logic?

7).what is sdc file and what does it contains?

8).what is the use of clock gaters in design?

9).Draw the internal diagram of clock gating cell?

10).what is use of latch in clock gating cell?

11).How glitches can be remove through latch?

12).Draw the muxed flip flop and explain?

13).Take three scan flop and stitch it and explain the scan operation?

14).How you will decide the number of scan chains for your core?

15).what is lockup latch and why we use it?

16).what are Manufactured defects?

17).what is clock latency?

18).will latency effect data shifting in scan chain?

19).consider two flop of .2sec and 0.3 sec latency how do you connect the flops in scan chain?

20).write the RTL coding for an asynchronous and a synchronous Flip-flop?

21).Implement a 2 by 1 Mux through gates?

22).How you will decide the compression ratio for the core?

23).what all information you will ask from designer for smooth scan insertion?

24).what all ctls you read while scan insertion?

25).Draw and explain the Structure of the compressor and decompressor circuit?

26).why we don't go for higher compression ratio like 90-100%?

27).How many scan clocks you had for your core?

28).which one is better having single or multiple scan clock?

29).what all things you need to take care while/before inserting on chip clock controller circuit?

30).In which path we insert the lockkup latch, data or clock path?

31).How you will resolve the combinational feedback loop issue in design if present?

32).why we don't connect the capture flop's clock to the lockup latch?

33).why we use flop trays in design?

34).what is the purpose of DFT?

35).why we need scan? or why we convert normal D flip flops to scan flops in design?

36).what work around you can do if you don't have scan equivalent for some flops in design while
scan insertion?

ATPG:

37).Did you worked on Coverage Analysis? How did you improved your Coverage?

38).what are the ATPG Untestable faults?

39).How much test coverage you got in your last project?

40).what are the input files required for scan insertion and ATPG and what all output files we get
after completing scan insertion and ATPG?

41).what is Stuck at fault?

42).How many faults sites are there for a 2 input AND Gate?

43).what is the difference between transition and path delay fault model?

44).what the SPF/test procedure file contains?

45).what are the different types of fault classes?

46).what is fault collapsing?

47).For a given fault coverage the number of patterns for TFT is more than the patterns
generated for Stuck-at-faults. Why so?

48).How the 2 pulses are generated for transition faults?

49).can you draw the on chip clock controller structure diagram?

50).what all DRCs you faced during ATPG?

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12/16/21, 5:04 PM DESIGN FOR TEST (DFT): DFT Interview Questions
51).what is the difference between launch on capture(LOC) and launch on shift(LOS)?

52).which one is widely used in industry? which one is better LOS or LOC?

53).How you will improve transition faults test coverage?

54).why we do IDDQ testing?

55).what is pseudorandom pattern and why it called pseudorandom?

56).Have you ever seen condition statements in spf and how they work?

57).If we have cover all transition faults along a path(critical) already then should we check the
path delay also for that path?

58).what is the test coverage and fault coverage?

59).what is redundant fault explain with example?

60).what are parallel patterns how they work explain with the help of a scan chain?

61).what are the DRCs that can result in low test coverage?

62).what are blocked and unused faults?

63).How the test data valume and tester time reduction happens with compression?

64).what are advantages of modular atpg?

65).How DFT vectors are different from Functional vectors?

66).why we measure PO(primary output) before capture clock?

67).How the IDDQ test vectors is different from stuck at test vectors?

68).How increasing sequential depth helps in improving test coverage?

Simulation:

69).How you will timing simulation debugging for uncompessed and compressed chains?

70).Suppose if you get hold violation how you fix that?

71).Have you ever opened sdf and seen?

72).what is setup and hold?

73).what violation will occur if step and hold time not maintain properly?

74).write the setup slack equation?

75).have you ever done post silicon debug?

76).if scan chain is broken then how you will debug?

77).if the clock skew is more than half clock cycle then how you will avoid the hold violation?

Miscellaneous:

78).why we do MBIST Insertion and verification? Which tool you are using?

79).what is P1500 how it works and useful?

80).How wrapper cell works draw its structure?

81).How you do extest using P1500 and tell what happens in its wrapper cell?

82).Do you know MBIST and how it works?

83).what are typical memory faults?

84).what is neighborhood and coupling faults how these faults are different from each other?

85).which tool did you use for MBIST insertion?

86).what checks(rules) ET checker do?

87).Draw Boundary scan cell and explain its functionality?

89).Explain Sample and Preload operation?

90).what is JTAG? why it is used? How I/O testing happens with JTAG?

91).what are the manadatory instructions in JTAG?

92).what are the default values of JTAG signals(tms,trstn,tdi,tdo,tck)?

93).For an INOUT port how many boundary scan cells you require?

94).Draw and explain the TAP state machine with tms values?

95).why we give tdo value at negedge in JTAG?

96).which instruction is having fix opcode in JTAG?

97).what is the significance of 'pause' state of TAP state machine?

98).How the 'mode' signal(for boundary scan cell) gets generated in JTAG?

99).Explain 8051 microcontroller?

100).How many Timers and memory size of 8051?

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7 comments:

Unknown 15 July 2016 at 06:32

Please provide the answer also

Reply

Unknown 15 July 2016 at 06:32

Please provide the answer also

Reply

Adele 20 November 2016 at 15:26

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