INFLUENCE OF VMIN ON THE SCALABILITY OF 14nm FinFET

BY

SAI MANIVEER.D- 217622977

VARAPRASAD .K- 218024305

SRIVATSAV.B- 218009811

ABDUL ZAMEER- 217657331

LIST OF CONTENTS
1) INTRODUCTION
2) BACKGROUND RESEARCH
3) RESEARCH GAP
4) RESEARCH QUESTION
5) METHODOLOGY
1. PROCEDURE FOR S-EDIT
2. ADDING TO LIBRARY FILES
3. DRAWING THE DIAGRAM
4. EXPORTING THE FILE
5. ANALYSIS AND SIMULATION
6) SIMILAR PROJECT EXPERIMENTAL RESULTS
7) ASSUMPTIONS
8) TIMELINE
9) PROJECT BUDGET
10) TEAM MEMBERS
11) FUTURE SCOPE
12) CONCLUSION
13) REFERENCES

LIST OF FIGURES

FIGURE NUMBER FIGURE NAME

1 Cross-sectional TEM image across fin.
2 DC characteristics of the finFET.
3 Creating a folder
4 Adding library files
5 Creating a design
6 Inserting command for analysis
7 Exporting the file
8 T-spice document
9 Inverter tanner design
10 T-spice document of inverter
11 W-edit waveform of inverter
12 Result of the inverter
 13 Sample inverter circuit developed in TannerEDA
14 Simulation and Quantitative results of the sample inverter circuit

LIST OF TABLES

TABLE NUMBER TABLE NAME

1 Schedule of Project
2 Budget of project
3 Team member description

TEAM CONTRIBUTION

S. No Student Name Student ID Student Contribution

1 Varaprasad 218024305 1. INTRODUCTION

kantipudi 2. BACKGROUND RESEARCH
3. RESEARCH GAP
4. RESEARCH QUESTION

2 Sai maniveer 217622977 1. METHODOLOGY

dhulipudi 2. SIMILAR PROJECT EXPERIMENTAL
RESULTS
3. REFERENCES

3 Bodapati 218009811 1. ASSUMPTIONS

SRIVATSAV 2. TIMELINE
3. FUTURE SCOPE

4 ABDUL ZAMEER 217657331 1. PROJECT BUDGET

2. TEAM MEMBERS
3. CONCLUSION
INFLUENCE OF VMIN ON THE SCALABILITY OF 14nm FinFET
INTRODUCTION
TRANSISTOR scaling continues to be the generating element for CMOS business. It's led to
offering better functionality and also decreasing powerful energy dissipation as well as, in
exactly the same period, allowed minimization inside the price every functionality [1]. With
all the limits within turning planar majority MOSFETs past the 32nm engineering node as a
result of worsening short channel consequences (Ever-Increasing channel and sce’s) doping
focus, FinFETs have been launched in volume manufacturing that is high during the 22nm
engineering node [2].
The much better electrostatic integrity of FinFETs not merely mitigates the overall
performance wreckage because of SCEs but additionally results in general performance
development as well as enhanced perturbation because of decrease in channel doping focus.
There's a lot of work within extending the lifetime of FinFETs to sub-10-nm know-how nodes
by changing the silicon (Si) channel with high-carrier-mobility substances as InxGa1'xAs (for
nMOS) as well as strained germanium (Ge) (for pMOS)[3]. Over and above non Si FinFETs,
heterojunction tunnel FETs (HTFETs) within the diverse arsenide–antimonide supplies
method with their promising sub kT/q high sub threshold conduct is able to outperform CMOS
of conditions of equally dc as well as RF shows, especially from reduced source voltages under
0.3 V. While there's a fair opinion within the local community which intense source voltage,
VCC, [4]turning while keeping huge transistor efficiency is attainable with the brand new
transistor architectures as well as alternative substances as channel it's crucial a
comprehensive relative research of the impact of system variants during these upcoming unit
applicants as well as the impact of theirs on unit along with fixed are conducted by us arbitrary
entry remembering (SRAM) performances[5].
It's crucial a comprehensive relative research of the impact of system variants during these
upcoming unit applicants as well as the impact of theirs on unit along with fixed are conducted
by us arbitrary entry remembering (SRAM) performances [6].

Background Research
The 14nm FinFET have excellent brief channel management, standard electron
transportation, better injection velocity as well as intrinsic mobility gain along with other
styles of lower energy setting derivatives [5]. With the increased use of the electric battery
operated units as cell phones, private healthcare equipment as well as and so on. The need
of reduced energy as well as size system that is small on chip (SoC) has become extremely
improved. So as to satisfy the increasing need, the thought of scalability (which implies the
sizing minimization for portability) with a lot more lots of gates to come down with lesser
region, with effective command above energy is definitely the significant problem within the
FinFETs[7]. In just a few a little fixed location since the improved density of the gates leads to
increased variety of uses though furthermore, it uses a lot more energy and also drains much
more present and also decreases the drive current that is our issue.
Have analysed the outcome of aid circuits about the fixed energy usage of SRAM VMIN. He
declared by decreasing the source voltage with all the usage of help circuit, there's lessen
with strength usage by 45.4 % for 6T HD as well as 12.2 % for 6T HP when set alongside the
non-assist circuits[8]. He stated the perturbation within the variables such as threshold
voltage, DIBL (drain induced screen reducing), leakage electricity, and drive present are
greatly altered by arbitrary dopant fluctuation (RDF) with sufficient significant channel
doping. They pointed out roughly the standard scaling that had attained the boundaries of its
of SCE (short channel effects) as well as electrostatics that threatens to keep Moore's law.
Additionally, they supplied the examination outcomes of a 14nm FinFET with high end as well
as substantial density SRAM.
To attain the 14nm engineering node for lower energy procedure the next obstacles as
scaling, latest fully depleted products, interconnection problems, reliability etc[9]. will be the
crucial considerations. Also, he realized that the difficulties will likely be greeted with new
generation and new methodologies that are extremely targeted at the comprehensive
energy, new algorithms and rc issues for winter and also dependability evaluation [10]. Said
around the scalability by 28nm to 14nm engineering. With the series of his of tests he realized
that 14nm node has thirty % pace increase in the very same energy or maybe it's fifty-five %
energy minimization at identical velocity as compared to 28nm node[11]. Also, he realized
that at lower voltage the advanced returned bias plays an important part of extension of
energy effectiveness.
They targeted at displaying the majority finFETs could be scaled right down to the least
possible limits of its obeying Moore's law. The three dimensional quantum transportation unit
simulation was used by them [12]. They found that electron density division ranges, transfer
attributes of the three dimensional quantum transportation unit simulation to confirm that
here junction a lot less function, inversion setting as well as build up setting is actually
practical for 3nm gate length[13]. They observed that, with current voltage computations the
calibration begun within the weak inversion component in which Leff & gt; Lg as well as
finishes within the strong inversion area[14]. By this particular ions are more and more
screened by effective inversion ask for and then generated 3 times more quickly electron
mobility.

FIG-2 DC characteristics of the finFET.

Nevertheless a good deal reduced effort is pointed out at the context of effect of VMIN on
14nm, like aid circuits on DRAM along with arbitrary dopant fluctuation (RDF) of 14nm with
appreciate to VMIN. Scalability of SRAM was in contrast to 14nm FinFET but absolutely no
outcomes for DRAM and SRAM, DRAM as well as 14nm FinFET [15]. The primary goal on this
analysis is investigating the impact on the VMIN within the scalability of SRAM, DRAM, along
with 14nm FinFET and also additionally to look at the end result during lower energy feedback.

Research Gap
In addition, many research and analysis are conducted on 14nm FinFET by adding additional
impurities for testing the scalability, short channel control, drive current and power
dissipation [13]. There is no trace of explaining Random Dopant Fluctuation (RDF) on 14nm
FinFET with respect to Vmin. The primary goal on this analysis is investigating the impact on the
VMIN within the scalability of SRAM, DRAM, along with 14nm FinFET and also additionally to
look at the end result during lower energy feedback.

Research Question
Till date, RDF has shown phenomenal response to MosFET transistors. No research has been
done on working of RDF on FinFET transistors [16]. Now in this research project by adding
Random Dopant Fluctuation (RDF) to 14nm FinFET and supplying the minimum voltage that
is required for the operation of 14nm FinFET and study the quantitative and qualitative results
of the 14nm FinFET transistors. This analysis and experimental procedure will be done on T-
Spice document which is available free on online [17]. By analysing the results this 14nm
FinFET transistor will be applied to real time projects .

METHODOLOGY
In the below we are explaining about the using of the software. So the software we are using
is TANNER EDA. There are multiple steps in order to simulate a project out of which we
mentioned the required steps in order to execute our project.
PROCEDURE FOR TANNER EDA

1. PROCEDURE FOR S-EDIT

 Open to the s-edit window
 Go to file file  new design
 Create a new folder and name the folder.
So after performing the above steps the display would be like this

FIG-3 Creating a folder

2. Adding to the library files

 Click on add
 click on browsing option
 go to the libraries
 go to the documents
 go to the tanner Eda
 tanner tools 13v
 go to the libraries 


FIG-4adding library files
  go to the all
 click on to the all
 click on to the ok.

3. Drawing the diagram

 Click on the devices
 click on to NMOS
 click on to instance
 done

FIG-5 Creating a design

4. EXPORTING THE FILE

 Go to the file
 export
 click on export spice
 And save the project your folder (i.e., go to the my computer
 local disc C
 and then export.

FIG-6 Exporting the file

5. ANALYSIS AND SIMULATION
 Click on to the Analysis
 click on to the Transient
 giving to the Maximum time and simulation
 click on insert command

FIG-7 Inserting command for analysis

Save the netlist and run the simulation and observe the output wave forms.

FIG-8 T-spice document

By following the above methodology we can design our finFET circuit. In the next section we
explained the similar project which is performed on this software

SIMILAR PROJECT EXPERIMENTAL RESULTS

An inverter circuit is performed in tanner EDA software with the 14nm finFET technology
[18]. The design and results are mentioned below:
1) Tanner design

FIG-9 Inverter tanner design

The above is the tanner design in which all the components are collected from the libraries to the
space model and those are connected according to the design. The above design consists of finFET
inverter in which input is given to both gates and output is taken from the junction of the gates.

2) T-spice document
 FIG-10 T-spice document of inverter

From the T-spice document we can observe the program done to it and the source of the file
and the timing when it is done.
3) W-edit waveform

The waveform are the results which we can analyse the simulated design and
program. Depending upon the outputs given we can obtain same number of
waveforms[19]. In the below waveform there are input and output. By this we can
observe for every value change of output according to input.
 FIG-11 W-edit waveform of inverter

4) RESULT

FIG-12 Result of the inverter

From the result section we can observe the setup time, dc operating point, dc operating
analysis, transient analysis, and overhead.

ASSUMPTIONS
 At the low power input for 14nm node the radiation tolerance is 200 Krad (sio2) for
bulk silicon devices and 300 krad (sio2) for the SOI devices [9].
 [10] They mentioned the critical dimensions for the14nm technology and also
compared the performance of 14nm SOI FinFET to the DRAM memory cell.
 They said that 14nm has >35% performance improvement at an ultra-density of
0.0174um2 and achieves high performance and low power simultaneously on chip
than DRAM memory cell.
 [11]This work presents test exhibit of InAs single and double quantum well (DQW)
heterostructure FinFETs (FF) and their better execution over In0.7Ga0.3As QW FF.
 The point is to outline of tall InAs balance gadgets.
 InAs DQW FF beats the single QW partner because of higher transporter thickness in
the balance.
 [3] SIT designing and high temperature blade carve alongside N2 plasma-TMA
passivated door stack give fantastic SS over all FinFETs.
 They decisively indicated InAs DQW FinFET at low power is appeared to show 15%
higher ION with tantamount DIBL and SS as Si FinFETs making InAs Heterostructure
FinFETs a reasonable choice later on.
 [12] They mentioned about the impact of the SWR and the process variation on the
multiple FinFETs. Her aim is to overcome the device to device variation while scaling
a FinFET over 14nm technology.
 The transistor which is used i.e. Finfet is vertical in nature with a high packing
density.
 The threshold voltage of the Finfet is low.
 Low operating voltage to safeguard the transistor and the circuit.
 Static leakage current flowing through the circuit is less.
 The operating speed of the device is assumed to be greater than the non-FinFet
devices.

TIMELINE:

In order to maintain the quality of the work carried it is important to monitor the all
the activities, duration and performance associated. Here we used MS project tool for
tracking the progress of the project activities. By doing this we will be able to plan, allocate
budget and resources, alter changes and estimate the timeline for completing activities. The
figure below is a snapshot from the MS project office representing the schedule of all our
activities. It gives a brief idea about the milestones and tasks that need to be achieved for
completing this project. Brief description about our timeline scheduling is explained below.
 TASK NAME DURATION START DATE END DATE
Analysis 10 Days Tue 1/05/18 Mon 14/05/18
On site meetings 3 Days Tue 1/05/18 Thu 03/05/18
Discussion about the 3 Days Fri 4/05/18 Tue 08/05/18
FinFet technology and
platform to be used
Studying and documenting 3 Days Wed 09/05/18 Fri 11/05/18
the developments
Analysis complete 1 Day Mon 14/05/18 Mon 14/05/18

Training 8 days Tue 15/05/18 Thu 24/05/18

E learning of TannerEDA 7 days Tue 15/05/18 Wed 23/05/18

software

Purchasing and Licensing 1 day Thu 24/05/18 Thu 24/05/18

of Software

Design 7 days Fri 25/05/18 Mon 4/06/18

Design database of 2 days Fri 25/05/18 Mon 28/05/18

inverter circuit

Software Design 2 days Tue 29/05/18 Wed 30/05/18

Interface design and 2 days Thu 31/05/18 Fri 1/06/18

software implementation

Analysing results 1 day Mon 4/06/18 Mon 4/06/18

Testing 2 days Tue 5/06/18 Wed 6/06/18

Performance test and 1 day Tue 5/06/18 Tue 5/06/18

identifying issues

Debugging and 1 day Wed 6/06/18 Wed 6/06/18

documentation
 Actual FinFet Model 7 days Thu 7/06/18 Fri 15/06/18

Modelling and design 1 day Thu 7/06/18 Thu 7/06/18

Simulation and 1 day Fri 8/06/18 Fri 8/06/18

quantitative analysis

Detailed analysis on 3 days Mon 11/06/18 Wed 13/06/18

Results

Proposal for practical 2 days Thu 14/06/18 Fri 15/06/18

implementation

TOTAL DAYS TAKEN 34 days

Table-1 Schedule of Project

Analysis:
It is very important to have an in-depth knowledge about the technology we study
about. FinFet is an emerging technology in the field of power electronics with a size of 14nm.
We estimated a timeframe of one week to gather, discuss and document the latest
developments in the field of FinFet. By doing this we came to know the existing technology
effect and there is no trace of explaining Random Dopant Fluctuation (RDF) on 14nm
FinFET[20] with respect to Vmin.

Training:
The platform required to carry out all the studies is TannerEDA, which is software
similar to that of MATLAB and is specially used to perform simulation analysis of analog
electronic circuits. We estimated an intensive week of training on this software. We require
one day for the purchase and activation of this software into the system.

Design:
Based on the previous knowledge we have designed an inverter circuit for a couple of
days and performed simulation with the software. The results are compared to test case
values to know the performance of the circuit. Below figure shows the circuit designed in the
software.
 Fig13 Sample inverter circuit developed in TannerEDA

FinFet model development:

We have estimated a period of 2 days for the design and development of FinFet model
by considering some assumptions. Once the design is verified and development is done
simulation can be performed immediately[22]. The sample data is then collected and
documented. Three test cases are studied and quantitative analysis is performed by-
a) Samples by varying dopant concentration.
b) Samples by narrowing the channel region.

c) Samples with random dopant fluctuation (RDF).

Raw data obtained after the simulation will be in the form of wave edit and numerical with
the help of the software. A sample data from the inverter circuit design is shown below for
instance.
 Fig14 Simulation and Quantitative results of the sample inverter circuit

Based on the different data simulation and quantitative analysis can be carried out in a
period of 2 days. This can be studied further and results can be documented.

Testing:
This is the final step in our project before actually proceeding with the practical
implementation. This may take a day or two in which we actually try to find any issues
technically associated with the software or the circuit. Based upon this we will try to solve the
issues and debug any errors. Finally this test results are verified and compared with the other
transistor circuits. By doing this step we will come to know the performance and scope of the
Finfet.

A final documentation of the data, results is carried out to proceed with the practical
implementation where we are going to implement the developed design. This
implementation is going to be carried out with the guidance of the electrical and electronics
engineers. This is estimated to be completed in a period of one week as practical
implementation by varying the transistor properties and condition requires more time.
Similar to the software implementation, in hardware we are going to monitor, analyse the
performance of the transistor by randomly doping and study the effect of Vmin.

Project budget
S.NO PRICE (IND RUPEES)
OFFICE SPACE 5,000
SYSTEMS 1,00,000
TUTOR 10,000
BILLS 2,000
FURNITURE 3,000
IMPLEMENTATION AREA 5,000
RESOURCES 1,00,000
OTHERS 5,000
 CONTRACT SERVICES 2,000
Table2 Budget of project
The most basic common thing before getting anything is to acquire a space to start a business.
The room which is being acquired need to be meets all the credentials of the buyer. To meet
this requirement there charge of the basic room might cost us up to around 5,000. After
getting the room ready we need to buy systems to work on. The system need to be updated
model which can be adapting to the software and runs it. To get all the systems which are
required we need need amount of around 1,00,000. The software is freely available in the
market, so here we don’t have to worry about the software to run the project.
After getting all the everything ready we need to hire some as tutor who is familiar to the
using of the software, and who can guide the newly hire people to give them a training before
they actually start working on the project. As the tutor will be be giving training to the new
comers so he has to start from the basic, so he might be costing us around 10,000. All the
office furniture has to be done before hiring the people, so they can start getting training right
from the next moment which can remove the over cost. To get all the office furniture we need
amount of around 3,000.
Before hiring someone we need to get done with the contract services or a bond which need
to be signed by the person who is being hire which states that he has to be with the company
for next coming up years, because if the person who has being hired gets a new job offer and
there is no such contract then he can leave the company at the very next moment, which can
be the loss of money for the company to start searching for a new person right from starting.
In this the board might cost us around 2,000.
After getting done with the simulation in the systems to know the exact values we need to
implement in the real life to known the exact values when it is being implemented in the real
world. There can be some cases in which results might differ this can be overcome by doing
some changes. To get the open space and where we can do all the implementation of the
simulation model. We need a big open space for this implementation of the model to solve
the real time problems for which, the area might be charging us around 5,000.
There are some bills which are needed to look after to run the project smoothly like internet
bills, which plays most important factors in these sections. There are some other bills which
needed to look after like electricity bills and water bills etc.., for the smooth run of all the bills
we will be need around 2,000 for it.
We also need some other kind of things which needed to look after like beard board, wires
and some other things which are need for the completion of this project. Apart from other
things we also need some of the engineers for the completion of this project. Engineers we
need for this project is electrical engineer, electronics engineer and circuit designer and circuit
analytical. We need to pay all the engineers salary which might cost us around 1, 00,000 per
month.
Team members:
S.NO Engineer name ENGINEER’S post
1. Nikhil Krishna ELECTRICAL ENGINEER
2. Balram reddy ELECTRONICS ENGINEER
3. Yasir khurram CIRCUIT DESIGNER
4. Sravanth Anne SOFTWARE ANALYTICAL
Table 3 Team member description
Nikhil Krishna will be dealing with the electrical engineer department. He is having around 3
years of experience in this department and he was also the team leader in the ECIL Company,
he will be the correct person for leading the company group.
Balram reddy used to work in ALSTOM Company and used to monitor the entire project
personally. His 2 years of experience can be used for uplifting of this project. As this company
mainly focus on the innovation and sustainable energy which will not affect the nature and
gives the effective results.
Yasir khurram has worked in the Bajaj electronics company from the past 4 years; he used to
deal with the circuits in the Bajaj electronics. He used to design the circuit and can use his
experience to train the new person who are selected for the job.

Sravanth Anne has been associated with the Google company, from the past 5 years at which
he used to take care of the server shutdown , where his experience can be used for the
software problem to get the solution for it, which has help the smooth flow of the process.

Future Scope:
The performance of MOSFET device has been practically improved by random dopant
fluctuation and the same was not been performed on Finfet device. It is assumed that it may
improve the performance on this device with respect to low power applications [23]. A new
generation Finfet transistor can be developed with an improved source and drain resistance.
Also power optimization, reliability analysis, stability with improved dopants can be studied
[24].

Conclusion:
Day by day there is increase in interest towards high speed power electronic devices
varying from small scale to large scale integrated circuits. Even though MOSFET is being used
in most of the applications today its limitations include high density control, high I on and Ioff.
Finfet is the emerging technology in the field of power electronics with reduced dimension in
size i.e. 14nm, high density i.e. faster electron transport and with great injection velocity [25].
In this report we came up with a proposal to perform simulation and quantitative analysis on
14nm low powered Finfet by randomly doping. Also to conclude the concerns with this
technology like reliability, scaling and interconnection can be overcome with new generation
and methodology [26].

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