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Subject Code: KEC051

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B. TECH
(SEM-V) THEORY EXAMINATION 2020-21
COMPUTER ARCHITECTURE AND ORGANIZATION
Time: 3 Hours Total Marks: 100
Note: 1. Attempt all Sections. If require any missing data; then choose suitably.
SECTION A

1. Attempt all questions in brief. 2 x 10 = 20

Q no. Question Marks CO
a. Discuss the design levels in the design of computer system. 2 1
b. Discuss the generic block representation of a register level component. 2 1
c. Differentiate between memory-mapped IO & IO-mapped IO. 2 2
d. Categorize various addressing modes. 2 2
e. Tell how normalized number are represented according to IEEE? 2 3
f. Define Hardwired control. 2 3
g. "Hardwired control unit is faster than micro programmed control unit." 2 4
Justify this statement.
h. Justify that the theoretical maximum speedup that a pipeline can provide 2 4
is equal to number of segments in the pipeline.

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i. Illustrate the concept of locality of reference. 2 5
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j. Outline how the performance of cache memory is measured? 2 5

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SECTION B

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2. Attempt any three of the following:

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Q no. Question Marks CO
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a. Design a two-level combinational circuit in the sum-of-products style 10 1

that compares the 3-bit sum of two 2-bit binary numbers. The circuit is
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to be implemented using AND and OR gates.

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b. Illustrate a small accumulator-based CPU using suitable block diagram 10 2

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in detail.
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c. Discuss the Datapath of the Twos complement multiplier in detail. 10 3

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d. Categorize the various microoperations carried out by CPU with 10 4

suitable example each.
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e. A Computer uses a memory unit with 256K words of 32 bits each. A 10 5

binary instruction code is stored in one word of memory. The instruction
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has four parts: an indirect bit, an operation code, a register code part to
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specify one of 64 registers and an address part.

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(i) Calculate how many bits are there in the opcode, the register
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code part and the address part?

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(ii) Illustrate the instruction word format & indicate the number of
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bits in each part.

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SECTION C
3. Attempt any one part of the following:
Q no. Question Marks CO
a. Describe the various Register level components with suitable example. 10 1
b. Design a pipelined 4-bit stream serial adder at register level. 10 1

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Subject Code: KEC051
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4. Attempt any one part of the following:
Q no. Question Marks CO
a. Derive the correct floating representation for the decimal numbers +3.25 10 2
and -3.25 using the 32-bit IEEE 754 floating-point standard.
b. Describe the detailed general register organization of a CPU using block 10 2
diagram.
5. Attempt any one part of the following:
Q no. Question Marks CO
a. Discuss Booth’s algorithm with its flow chart. Multiply (-8) and (+14) 10 3
using Booth’s algorithm.
b. Illustrate the data path of a sequential n-bit binary adder in detail. 10 3
6. Attempt any one part of the following:
Q no. Question Marks CO
a. Draw a flowchart for adding and subtracting two fixed point binary 10 4
numbers where negative numbers are signed 1’s complement
presentation.
b. Formulate the four-segment instruction pipeline for a computer. Specify 10 4
the operation to be performed in each segment.

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7. Attempt any one part of the following:
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Q no. Question Marks CO

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a. RAM chip 4096 X 8 bits has two enable lines. How many pins are 10 5

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needed for the integrated circuits package? Draw a block diagram and

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label all input and outputs of the RAM. Outline the main features of
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random-access memory.
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b. Describe the various types of mapping techniques in cache memory 10 5
organization. Illustrate any two techniques with suitable diagram.
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AKTU_QP20E164QP | 03-Mar-2021 09:05:42 | 103.112.13.100