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IT212 - Lecture 8 - Decoders & Encoders

A decoder is a combinational logic circuit that converts binary inputs into exclusive outputs. It has N inputs and 2^N outputs, with only one output active at a time based on the input code. A decoder can be built by combining two 2-to-4 decoders, with one decoder enabled based on the most significant input bit to selectively output from the first or second decoder. This allows building larger decoders from smaller standard decoder components.

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142 views75 pages

IT212 - Lecture 8 - Decoders & Encoders

A decoder is a combinational logic circuit that converts binary inputs into exclusive outputs. It has N inputs and 2^N outputs, with only one output active at a time based on the input code. A decoder can be built by combining two 2-to-4 decoders, with one decoder enabled based on the most significant input bit to selectively output from the first or second decoder. This allows building larger decoders from smaller standard decoder components.

Uploaded by

Ahmed Alaa
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We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 8: Decoders & Encoders

IT 212: Logic Design

Mohamed Kassem
m.mostafa@fci-cu.edu.eg

Week 7: 16th-17th December


Decoder
● The decoder is a combinational circuit that decodes its input and give specific
output corresponding to it.

● In general, the decoder has N inputs and outputs to cover all input
combinations. Only one of these outputs will have an output equals to 1
based on the combination of the present inputs, in fact this output detects a
the inputs’ code.
Decoder
● The decoder is a minterm generator

N
N to
Inputs Decoder
Outputs
2x4 Decoder
X Y D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Truth Table
2x4 Decoder
X Y D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Truth Table
2x4 Decoder
X Y D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0
Logic Diagram
1 1 0 0 0 1

Truth Table
D2

D1
2x4 Decoder
X Y D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0
Logic Diagram
1 1 0 0 0 1

Truth Table
D2

D1

Block Diagram
3x8 Decoder
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Truth Table
3x8 Decoder

Logic Diagram Block Diagram


Decoder with enable
● A decoder can have an additional input signal called the enable which
enables or disables the output generated by the decoder.

● So a decoder with enable has n input line + an enable and output lines. In
general (active high enable):
○ If enable=0, all the outputs=0
○ If enable=1, the decoder works as usual.
Decoder with enable

N
N to
Inputs Decoder
Outputs

Enable

Block Diagram
2x4 Decoder with enable
E X Y D0 D1 D2 D3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Truth Table
2x4 Decoder with enable
E X Y D0 D1 D2 D3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Truth Table
2x4 Decoder with enable
E X Y D0 D1 D2 D3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0
Logic Diagram
1 1 0 0 0 1 0

1 1 1 0 0 0 1

Truth Table
2x4 Decoder with enable
E X Y D0 D1 D2 D3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0
Logic Diagram
1 1 0 0 0 1 0

1 1 1 0 0 0 1

Truth Table

Block Diagram
3x8 Decoder with enable
E X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 x x x 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0

1 0 1 0 0 0 1 0 0 0 0 0

1 0 1 1 0 0 0 1 0 0 0 0

1 1 0 0 0 0 0 0 1 0 0 0

1 1 0 1 0 0 0 0 0 1 0 0

1 1 1 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 0 0 0 0 0 1

Truth Table
3x8 Decoder with enable

Logic Diagram Block Diagram


Building a 3x8 Decoder using two 2x4 Decoders with
enable?
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1
Building a 3x8 Decoder using two 2x4 Decoders with
enable?
X Y Z

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z

Decoders
Inputs

0 0
X=0

0 1

1 0

1 1

0 0
X=1

0 1

1 0

1 1
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z

Decoders 1st 2nd


Inputs Decoder Decoder

0 0
Enable =

Enable =
X=0

0 1
X’=1

X=0
1 0

1 1

0 0
Enable =

Enable =
X=1

0 1
X’=0

X=1

1 0

1 1
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z

Decoders 1st 2nd Only the first


Inputs Decoder Decoder decoder works

0 0
Enable =

Enable =
X=0

0 1
X’=1

X=0
1 0

1 1
Only the second
decoder works
0 0
Enable =

Enable =
X=1

0 1
X’=0

X=1

1 0

1 1
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z

Decoders 1st 2nd O/P = 1


Inputs Decoder Decoder

0 0 D0
Enable =

Enable =
X=0

0 1 D1
X’=1

X=0
1 0 D2

1 1 D3

0 0 D4
Enable =

Enable =
X=1

0 1 D5
X’=0

X=1

1 0 D6

1 1 D7
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z D0 D1 D2 D3

Decoders 1st 2nd O/P = 1


Outputs of first decoder
Inputs Decoder Decoder

0 0 D0 1 0 0 0
Enable =

Enable =
X=0

0 1 D1 0 1 0 0
X’=1

X=0
1 0 D2 0 0 1 0

1 1 D3 0 0 0 1

0 0 D4 0 0 0 0
Enable =

Enable =
X=1

0 1 D5 0 0 0 0
X’=0

X=1

1 0 D6 0 0 0 0

1 1 D7 0 0 0 0
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z D0 D1 D2 D3

Decoders 1st 2nd O/P = 1


Outputs of first decoder
Inputs Decoder Decoder

0 0 D0 1 0 0 0
Enable =

Enable =
X=0

0 1 D1 0 1 0 0
X’=1

X=0
1 0 D2 0 0 1 0

1 1 D3 0 0 0 1

0 0 D4 0 0 0 0
Enable =

Enable =
X=1

0 1 D5 0 0 0 0
X’=0

X=1

1 0 D6 0 0 0 0

1 1 D7 0 0 0 0
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z D0 D1 D2 D3 D4 D5 D6 D7

Decoders 1st 2nd O/P = 1 Outputs of second


Outputs of first decoder
Inputs Decoder Decoder decoder

0 0 D0 1 0 0 0 0 0 0 0
Enable =

Enable =
X=0

0 1 D1 0 1 0 0 0 0 0 0
X’=1

X=0
1 0 D2 0 0 1 0 0 0 0 0

1 1 D3 0 0 0 1 0 0 0 0

0 0 D4 0 0 0 0 1 0 0 0
Enable =

Enable =
X=1

0 1 D5 0 0 0 0 0 1 0 0
X’=0

X=1

1 0 D6 0 0 0 0 0 0 1 0

1 1 D7 0 0 0 0 0 0 0 1
Building a 3x8 Decoder using two 2x4 Decoders with enable?

Y Z D0 D1 D2 D3 D4 D5 D6 D7

Decoders 1st 2nd O/P = 1 Outputs of second


Outputs of first decoder
Inputs Decoder Decoder decoder

0 0 D0 1 0 0 0 0 0 0 0
Enable =

Enable =
X=0

0 1 D1 0 1 0 0 0 0 0 0
X’=1

X=0
1 0 D2 0 0 1 0 0 0 0 0

1 1 D3 0 0 0 1 0 0 0 0

0 0 D4 0 0 0 0 1 0 0 0
Enable =

Enable =
X=1

0 1 D5 0 0 0 0 0 1 0 0
X’=0

X=1

1 0 D6 0 0 0 0 0 0 1 0

1 1 D7 0 0 0 0 0 0 0 1
Building a 3x8 Decoder using two 2x4 Decoders with enable?

D0
D1
X D2
Y 3-to-8 D3
D4
Decoder
Z D5
D6
D7
Using a decoder to build a function
● As a decoder generates all the minterms of the inputs, design a circuit with N
inputs and Y outputs.
1. Decoder size = N x
2. For each output, do the following:
■ Get the minterms of the output.
■ Connect the outputs of the decoder that correspond to these
minterms to a multi-input OR gate.
Using a decoder to build a function: Example
● Design a circuit that count the number of zeros in a
3-bit binary number.
Using a decoder to build a function: Example
● Design a circuit that count the number of zeros in a Inputs Outputs

3-bit binary number. A B C X Y

0 0 0 1 1

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 0 0
X= D0 OR D1 OR D2 OR D4

A B C D0 D1 D2 D3 D4 D5 D6 D7 Inputs Outputs

A B C X Y
0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 1
0 0 1 0 1 0 0 0 0 0 0
0 0 1 1 0
0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 0
0 1 1 0 0 0 1 0 0 0 0
0 1 1 0 1
1 0 0 0 0 0 0 1 0 0 0
1 0 0 1 0
1 0 1 0 0 0 0 0 1 0 0
1 0 1 0 1
1 1 0 0 0 0 0 0 0 1 0
1 1 0 0 1
1 1 1 0 0 0 0 0 0 0 1
1 1 1 0 0
Y= D0 OR D3 OR D5 OR D6

A B C D0 D1 D2 D3 D4 D5 D6 D7 Inputs Outputs

A B C X Y
0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 1
0 0 1 0 1 0 0 0 0 0 0
0 0 1 1 0
0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 0
0 1 1 0 0 0 1 0 0 0 0
0 1 1 0 1
1 0 0 0 0 0 0 1 0 0 0
1 0 0 1 0
1 0 1 0 0 0 0 0 1 0 0
1 0 1 0 1
1 1 0 0 0 0 0 0 0 1 0
1 1 0 0 1
1 1 1 0 0 0 0 0 0 0 1
1 1 1 0 0
Using a decoder to build a function: Example
● Design a circuit that count the number of zeros in a
3-bit binary number.
Encoder
● The encoder is a combinational circuit that performs the inverse operation of
the decoder.

● It has input lines and N output lines, which generate the binary code
corresponding to the input value, meaning that an encoder converts a code
containing exactly one bit that is 1 to a binary code corresponding to the
position in which the 1 appears.
Encoder

Block Diagram
4x2 Encoder
D3 D2 D1 D0 X Y

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Truth Table
4x2 Encoder
D3 D2 D1 D0 X Y

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Truth Table
4x2 Encoder
D3 D2 D1 D0 X Y

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Truth Table

Logic Diagram
4x2 Encoder
D3 D2 D1 D0 X Y

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Truth Table

D0 Logic Diagram
D1 X
Block 4x2
D2 Y
Diagram Encoder
D3
8x3 Encoder
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Truth Table
8x3 Encoder

Logic Diagram Block Diagram


Encoder with enable
● An encoder can have an additional input signal called the enable which
enables or disables the output generated by the encoder. So an decoder with
enable has N output lines and input line + an enable.

● In general (active high case):


○ If enable=0, all the outputs=0 (there is a problem that it has the same
output as D0 = 1)
○ If enable=1, the encoder works as usual.
4x2 Encoder with enable
Outputs

Block Diagram

Inputs
Building a 8x3 encoder using two 4x2 encoders with enable

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
2nd Encoder 1st Encoder

E D7 D6 D5 D4 D3 D2 D1 D0 A B C

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
2nd Encoder 1st Encoder

E D7 D6 D5 D4 D3 D2 D1 D0 A B C

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
2nd Encoder 1st Encoder

E D7 D6 D5 D4 D3 D2 D1 D0 A B C

0 0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 1 0 0 0 0 1 1

1 0 0 0 1 0 0 0 0 1 0 0

1 0 0 1 0 0 0 0 0 1 0 1

1 0 1 0 0 0 0 0 0 1 1 0

1 1 0 0 0 0 0 0 0 1 1 1
2nd Encoder input 2nd Encoder output

E D7 D6 D5 D4 X2 Y2 D3 D2 D1 D0 X1 Y1 A B C

This encoder is This encoder is

This encoder is
0 0 0 0 0 0 0 0 0 0 1 0 0 0

disabled

disabled
0 0 0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1

1 0 0 0 1 0 0 0 0 0 0 1 0 0
enabled

1 0 0 1 0 0 1 0 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0 1 1 0

1 1 0 0 0 1 1 0 0 0 0 1 1 1
2nd Encoder input 2nd Encoder output

E D7 D6 D5 D4 X2 Y2 D3 D2 D1 D0 X1 Y1 A B C

This encoder is This encoder is


0 0 0 0 0 0 0 0 0 0 1 0 0 0

disabled
0 0 0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1

1 0 0 0 1 0 0 0 0 0 0 1 0 0
enabled

1 0 0 1 0 0 1 0 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0 1 1 0

1 1 0 0 0 1 1 0 0 0 0 1 1 1
1st Encoder input 1st Encoder output
2nd Encoder input 2nd Encoder output

E D7 D6 D5 D4 X2 Y2 D3 D2 D1 D0 X1 Y1 A B C

This encoder is
This encoder is This encoder is
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

disabled

enabled
0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1

0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0

0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1

This encoder is

This encoder is
1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

disabled

disabled
enabled

1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0

1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1
1st Encoder input 1st Encoder output
2nd Encoder 2nd Encoder output
input

E D7 D6 D5 D4 X2 Y2 D3 D2 D1 D0 X1 Y1 A B C

This encoder is
This encoder is This encoder is
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

disabled

enabled
0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1

0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0

0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1

This encoder is
1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

disabled
enabled

1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0

1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1
OR
E D7 D6 D5 D4 X2 Y2 D3 D2 D1 D0 X1 Y1 A B C

This encoder is
This encoder is This encoder is
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

disabled

enabled
0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1

0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0

0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1

This encoder is
1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

disabled
enabled
1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0

1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1

OR
E D7 D6 D5 D4 X2 Y2 D3 D2 D1 D0 X1 Y1 A B C

This encoder is
This encoder is This encoder is
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

disabled

enabled
0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1

0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0

0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1

This encoder is
1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

disabled
enabled
1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0

1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1
Building a 8x3 Encoder using two 4x2 Encoders with enable?
Priority Encoder
● Two problems arises with regular encoders:
○ What happens if more than one input are = 1?
■ We will get wrong outputs.

○ What happens if all inputs = 0?


■ The output will be the same as if the D0 = 1
Priority Encoder
● The priority encoder addresses these two issues:
○ What happens if more than one input are = 1 ?
■ The priority encoder considers the bit with highest priority. (highest
index)
○ What happens if all inputs = 0?
■ The priority encoder add another output V to indicate this
combination.
4x2 Priority Encoder

First condition: All inputs = 0

Set V = 0, meaning that is


invalid input
4x2 Priority Encoder

Second condition: More than one


input = 1

Choose the bit with highest


priority (highest index)
4x2 Priority Encoder

D3 D2 D1 D0 X Y V

0 0 0 0 X X 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

Truth Table
4x2 Priority Encoder

D3 D2 D1 D0 X Y V D1D0
0 0 0 0 X X 0 D3D2 00 01 11 10
00 X 0 0 0
0 0 0 1 0 0 1
01 1 1 1 1
0 0 1 X 0 1 1
11 1 1 1 1
0 1 X X 1 0 1
10 1 1 1 1
1 X X X 1 1 1

Truth Table
4x2 Priority Encoder

D3 D2 D1 D0 X Y V D1D0
0 0 0 0 X X 0 D3D2 00 01 11 10
00 X 0 0 0
0 0 0 1 0 0 1
01 1 1 1 1
0 0 1 X 0 1 1
11 1 1 1 1
0 1 X X 1 0 1
10 1 1 1 1
1 X X X 1 1 1

Truth Table X = D 3 + D2
4x2 Priority Encoder

D3 D2 D1 D0 X Y V D1D0
0 0 0 0 X X 0 D3D2 00 01 11 10
00 X 0 1 1
0 0 0 1 0 0 1
01 0 0 0 0
0 0 1 X 0 1 1
11 1 1 1 1
0 1 X X 1 0 1
10 1 1 1 1
1 X X X 1 1 1

Truth Table
4x2 Priority Encoder

D3 D2 D1 D0 X Y V D1D0
0 0 0 0 X X 0 D3D2 00 01 11 10
00 X 0 1 1
0 0 0 1 0 0 1
01 0 0 0 0
0 0 1 X 0 1 1
11 1 1 1 1
0 1 X X 1 0 1
10 1 1 1 1
1 X X X 1 1 1

Truth Table Y = D3 + D’2D1


4x2 Priority Encoder

D3 D2 D1 D0 X Y V D1D0
0 0 0 0 X X 0 D3D2 00 01 11 10
00 0 1 1 1
0 0 0 1 0 0 1
01 1 1 1 1
0 0 1 X 0 1 1
11 1 1 1 1
0 1 X X 1 0 1
10 1 1 1 1
1 X X X 1 1 1

Truth Table
4x2 Priority Encoder

D3 D2 D1 D0 X Y V D1D0
0 0 0 0 X X 0 D3D2 00 01 11 10
00 0 1 1 1
0 0 0 1 0 0 1
01 1 1 1 1
0 0 1 X 0 1 1
11 1 1 1 1
0 1 X X 1 0 1
10 1 1 1 1
1 X X X 1 1 1

Truth Table V = D 3 + D 2 + D1 + D0
4x2 Priority Encoder

X = D 3 + D2

Y = D3 + D’2D1

V = D 3 + D 2 + D1 + D0
BCD to Excess-3 Code Converter
● Using decoders and encoders, design an excess-3 code converter that takes
as input a BCD number, and generates an excess-3 output.
BCD to Input Output

A B C D W X Y Z
Excess-3
0 0 0 0 0 0 1 1
Code
0 0 0 1 0 1 0 0
Converter
0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0
BCD to Input Output

A B C D W X Y Z
Excess-3
0 0 0 0 0 0 1 1
Code
0 0 0 1 0 1 0 0
Converter
0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0
4x16 Decoder 16x4 Encoder
4x16 Decoder 16x4 Encoder
4x16 Decoder 16x4 Encoder
4x16 Decoder 16x4 Encoder
BCD to
Excess-3 Code
Converter

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