“computer. (0) Define and explain PUN and PDN, Either NAND gates or NOR gates ean be used for (11) ‘implementing Boolean finctions. Discuss which one ofthe two is better regarding the area to be implemented in complementary CMOS logic, explain in a few sentences ‘With the schema diagram, © Write a a greed pat & 00) eee not = oro) eee y A | ase } (@) What s the intended fimetion Othe Cre chown below? What isthe output voltage (04) ot ‘fange for this circuit? gies Vinh Yeah sv SY ey ; 3 6 10 | tay Buffer wo— 2g spo i scars 8 QZ CMOS Leaf Cell Design: For the CMOS logie gate Y “AID, do the following: (5) (Draw the logic diagram ee (ii) draw the transistor-level schematic =< Gil) size the transistors to have the same tesistance as a unit inverter iv) find the Euter path for both the p and n-MOS networks (0) draw the stick diagram layout using the standard colour ( (vi) estimate the total area in units of 7 and for 180-nm technology \ ae (Wil) estimate the gate and diffusion capacitances for the gate, Label them om ——— — your layout Page lof aiediagyun, Draw electrically equivakent : toe cas coecl nplonsenr? Dw tho bai 3 ‘chemate, What logic equation fie the Elmore (10) 40)” Draw the Elejore RC model diagram. Write down the delay equation forthe Elm re RC model. (0) fn.y0ur answers to this question you may assume (13) * All delays are in units of + An inverter gate has g= 1, p= 1 A rrinput NAND pate hiss «= (7 + 23, p —n J Ateinput NOR gate has = n+ ty, 6p * A b-inpat MUX gate has y= 3, 1 A Rin XOR or XNOR gus has p=, pg sich ptt XOR orXNOR site has p= 6 bg ape OTP oC logical effort to esimatc heey 8 the path from input A to ‘put OUT in the Figure below F, our | a ce PLD? Classify PLD, Write short mole on PAL and GA cn (0) What is OPALie? How 0 sk DoBraR in OPLAje? The GAL. fey PLD, What do the 16" and “g> WCALTOVE rap ee OME (V8 isa popuar (06) (©) What are the basic Alifferences between cornbinat . \, ‘ four bits bidirectional a WM ee ol’Y») Ars: For PMas ANN wo pleratadHe : Poy Mfros Fer Pma NAN D Pe = = [ Vip Re, Ra i : Ba “Oa” ip ~ ee a Wa Wa B aw 7 upp ko, fO- BR e AD 2 t-R rt cl 3 ; Was Woz BA4Dr D Woe Ss tt en thes Need Her tt PeiDi pie oe z 2Re , ee Tecnology ale r a9 4 Bie ® See St alata me Ce 24 | et Cet ‘6 a rae Full Se la f so Wa= | ln ; y GND Saal fe tae i aco yg boar WR =, e menny np WA width size of transi tn. feted | Ps AWD MR “ Ei | mM DP svn size < ea exe. So negare ding do gitea, NAND arte aplaras .” wb beffr jr Bh Cras bz =o =} A= #01 /3 A+ACD=-F >= 2a a GO eae eee DB@) Aor 1012) = ABE F0)-5 SP ‘) 4 A @ oPz 18 = 5 Gareas) -p a8 5 PD — amcor Tut aT RETO Aor —> max bF— AND2@ inverter Avo | DRL a gece ome rn We oR 2C # \/ 25 \, om orp 15 a oO otc fe bt CATES oe Cae an = AOL jo= A+rBCD OAL /% = P: CBX GD) O begs Otw 2Bie 119 uly Semen aE Tas SVL ESC alee peer re ee a pis Pas i a . 3 os cal life ila ‘ool GND ; awh lke beffan Gv a buffer el. ; oe = cS ‘e72ET w (2/0) Pre C.(008, Leaf cel aig. 7 c* Y= WFBED Diy deyo Ss ie a bngd seh hanate @® Sham + Fi@o ed 5 a oa oie Pros Arhn-ftes foulPo dif fuam ogmecy , nt diffeaien geen 6) Bie) akea\ A) al ale” = = 404 Fg. -2 (vy) 40) 6x = 9A = (ep Nm jhe ~ 9p mm— = 90x10 % A Ae Prrea= 40X48 X (% xi?) Poe SPS ail oe EP = 1SssS onCr ee ‘89 (nly Sematary Enos wf a ~ Ble) bg capacitance O¢ vith f ole . 2 nagnesn | Ly Diffuows ea poerfance form etree el ant Vop ON ND. aM pal ee earten = [oat - nen we yates = “ie gin, te Ce Tanisha a sg ar Schernatrt patoate =% ; = —__— —_— +e plas (bade 5 -7Vbetat no 0G) RAC Ombre dof et 19 Duly Semesery ae A Cae we A ) trons Engineering y= oa ohera ae va mstPld 2 Peg” (LN Rr. dle URE Devices ohw6 + note: & tea Fregno . buat Je vy pe feed i