Hello and welcome to this presentation of the STM32L4

Analog-to-Digital Converter block. It will cover the main

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The analog-to-digital converters inside STM32 products
allow the microcontroller to accept an analog value like a
sensor output and convert the signal into the digital
domain. There are up to three ADCs and 16 to 24 analog
inputs depending on the device. The ADC module itself
is a 12-bit successive approximation converter with
additional oversampling hardware. Under certain
conditions, the oversampled output can have a 16-bit
result. The sampling speed is more than five mega
samples per second. Each ADC module integrates three
analog watchdogs. The data can be made available
either through DMA movement or interrupts. This ADC is
designed for low power and high performance. There are
a number of triggering mechanisms and the data
management can be configured to minimize the CPU
workload.

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Up to 3 analog-to-digital converters are integrated inside
STM32L4x6 products. The input channel is connected to
up to 24 GPIO channels capable of converting signals in
either Single-end or Differential mode. The ADCs can
convert signals in excess of 5 mega samples per
second. There are several functional modes which will
be explained later. There are also several different
triggering methods. In order to offload the CPU, the ADC
has 3 analog watchdogs for monitoring thresholds. The
ADC also offers oversampling to extend the number of
bits presented in the final conversion value. For power-
sensitive applications, the ADC offers a number of low-
power features.

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This slide shows the general block diagram for each
analog-to-digital converters embedded in the STM32L4.

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The STM32L4’s ADCs support a Deep power-down
mode. When the ADC is not used, it can be disconnected
by a power switch to further reduce the leakage current.
Auto-delayed mode makes the ADC wait until the last
conversion data is read before starting the next
conversion. This avoids unnecessary conversions and
thus reduces power consumption. The power
consumption is in function of the sampling frequency. For
low sampling rates, the current consumption is reduced
almost proportionally.

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The ADC supports up to 5.33 mega samples per second
of conversion. By using dual interleaved mode, it can be
extended to ten mega samples par second. The ADC
includes the oversampling hardware which accumulates
data and then divides without CPU help. The
oversampler can accommodate from 2 to 256 times
samples and right shift from one to eight binary digits.
The sequencer allows the user to convert up to 16
channels in any desired order. Also each channel can
have different sampling period. The ADC offers an auto
calibration mechanism. It is recommended to run the
calibration on the application if the reference voltage
changes more than 10% so this would include emerging
from RESET or from a low power state where the analog
voltage supply has been removed and reinstated.

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The ADC needs a minimum of 2.5 clock cycles for the
sampling and 12.5 clock cycles for conversion. With an
80 MHz ADC clock, it can achieve 5.33 mega samples
per second. For higher speed sampling, it is possible to
reduce the resolution down to 6 bits then the sampling
speed can go up to 8.88 mega samples per second.

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The sampling time can be programmed individually for
each input channel of the analog-to-digital converters.
The sampling times listed in this slide in ADC clock
cycles are available. Longer sample times ensure that
signals having a higher impedance are correctly
converted.

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The ADCs have a selectable clock source. When the
system needs to run synchronously, the AHB clock
source is the best selection. If a slow CPU speed is
required, but the ADC needs a higher sampling rate, the
dedicated ADC clock can be selected.

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AD converter supports several conversion modes:
• Single mode, which converts only one channel, in
single-shot or continuous mode.
• Scan mode, which converts a complete set of pre-
defined programmed input channels, in single-shot or
continuous mode.
• Discontinuous mode, converts only a single channel
at each trigger signal from the list of pre-defined
programmed input channels.

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The ADCs support hardware oversampling. They can
sample by 2, 4, 8, 16, 32, 64, 128 and 256 times without
CPU support. The converted data is accumulated in a
register and the output can be processed by the data
shifter and the truncater.
12-bit data can be extended to be presented as 16-bit
data. This functionality can be used as an averaging
function or for data rate reduction and signal-to-noise
ratio improvement as well as for basic filtering.

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Each ADC has three integrated analog watchdogs with
high and low threshold settings. The ADC conversion
value is compared to this window threshold, if the result
exceeds the threshold, an interrupt or external signal can
be generated or a timer can be immediately stopped
without CPU intervention.

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The ADC conversion result is stored in a 16-bit data
register. The system can use CPU polling, interrupts or
DMA to make use of the conversion data. An overrun flag
can be generated if data is not read before the next
conversion data is ready. For injected channel
conversions, 4 dedicated data registers are available.

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An injected conversion is used to interrupt the regular
conversion, then insert up to 4 channel conversions.
Once an injected conversion is finished, the regular
conversion sequence can be resumed. The injected
conversion result is stored in dedicated data registers.
Flags and interrupts are available for the end of
conversion or end of sequence. The choices for an
injected channel can be reprogrammed on the fly. Even if
a regular or injected conversion is in progress, you can
add a different channel to the queue so that next injected
channel can be different from the previous one.

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Each ADC can generate 9 different interrupts: ADC
Ready, end of conversion, end of sequence, end of
injected conversion, end of injected sequence, analog
watch dog, end of sampling, data overrun and the
overflow of the injected sequence context queue.
DMA requests can be generated at each end of
conversion when the ADC output data is ready.
The ADCs are active in Run, Sleep, Low-power run and
Low-power sleep modes. In Stop0, Stop 1 or Stop 2
mode, the ADCs are not available but the contents of
their registers are kept. In Standby or Shutdown mode,
the ADCs are powered-down and must be reinitialized
when returning to a higher power state. There is a Deep
power-down mode in each ADC itself which reduces
leakage by turning off an on-chip power switch. This is
the recommended mode whenever an ADC is not used.
The following table shows performance parameters for
the ADC.

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These peripherals may need to be specifically configured
for correct use with the ADCs. Please refer to the
corresponding peripheral training modules for more
information.

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The STM32L4 embeds up to three ADCs. ADC 1 and
ADC 2 can be configured to work together in Dual mode,
so that each analog-to-digital conversion can be
synchronized between the two modules. ADC 3 works as
a standalone converter.
Several application notes dedicated to analog-to-digital
converters are available. To learn more about ADCs, you
can visit a wide range of web pages discussing
successive approximation analog-to-digital converters.

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