INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2023, VOL. 69, NO. 3, PP.

425-430
Manuscript received May 25, 2023; revised July, 2023. DOI: 10.24425/ijet.2023.144379

ADC Emulation on FPGA

Huma Tabassum, Krishna Prathik BV, and Sujatha S Hiremath

Abstract—Analog-to-Digital Converters (ADCs) are devices

that transform analog signals into digital signals and are used
in various applications such as audio recording, data acquisition,
and measurement systems [1]. Prior to the development of actual
chip, there is a need for prototyping, testing and verifying
the performance of ADCs in different scenarios. Analog macros
cannot be tested on an FPGA. In order to ensure the macros
function properly, the emulation of the ADC is done first. This
is a digital module and can be designed in System Verilog. This
paper demonstrates the design of the module on FPGA for Analog
to Digital Converter (ADC) emulation. The emulation is done
specific to the ADC macro which has programmable resolutions
of 12/10/8/6 bit.
Keywords—ADC; resolution; FPGA; sampling; conversion

I. INTRODUCTION

T HE emulation of the ADC on FPGA is done to mimic

the behaviour of the ADC on FPGA. This is useful
when testing the entire microcontroller on FPGA. The module
developed in this paper can be used in place of the actual ADC,
for testing the functionality, since the ADC is an analog macro
and cannot be implemented on FPGA. The ADC which is
emulated operates in different phases which include sampling
of data and conversion of analog to digital data. The data can
be output either in serial or parallel fashion. The ADC can
also be configured to operate in different resolution modes.
The resolution is set by the controller.
Fig. 1. Design Flowchart
II. THEORY
The module that performs the ADC emulation is designed
according to Fig. 1. The signals required by the ADC are
obtained first. The ADC emulation module controller is then
designed taking into consideration the different modes of
operation of the ADC and the number of clock cycles required
for each mode. There are different types of ADCs such as
Continuous Time Pipelined ADC, which is an architecture
that combine pipelining with continuous time operation [2].
The ADC considered in our design is a typical Successive
Approximation Register ADC.

A. ADC Controller Interface

An ADC controller interfaces between the analog input
sources and the ADC, providing configuration, control, and
synchronization functionalities [3]. The ADC and the con-
troller are interfaced through several signals. See Fig. 2 Fig. 2. ADC-Controller Interface
• clock signal: The clock signal is required by the ADC and
is output by the controller.

Authors are with RV College of Engineering, India (e-mail:

humatabassum812@gmail.com, bvkrishnap2001@gmail.com, sujathah@
rvce.edu.in).

© The Author(s). This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0,
https://creativecommons.org/licenses/by/4.0/), which permits use, distribution, and reproduction in any medium, provided that the Article is properly cited.
226 HUMA TABASSUM, KRISHNA PRATHIK BV, SUJATHA S HIREMATH

• adc enable: When the enable signal goes high, the ADC • READY STATE: The next state that the ADC enters
is enabled and switched on. is the ready state. In this state, the adc pre end of
• asynchronous sampling enable: The ADC operates in two conversion and the adc end of conversion signals are set
modes. This signal decides which mode the ADC operates high simultaneously on the first posedge of clock after
in. This signal has to be held constant during sampling. the deassertion of reset signal. The ADC enters the
• start of conversion: This signal indicates the start of sampling mode and starts to respond to control signals.
conversion. The controller checks the start of conversion • WAIT FOR SOC: This phase is also referred toas
signal on the positive edge of the clock. It enters the the sampling phase. During this phase, the ADC samples
conversion phase on the immediate posedge after the start the data. The end of sampling is indicated by the start
of conversion is detected. of conversion signal going high. The adc pre end of
• select resolution: The 2 bit signal selects either 6,8,10 conversion and the adc end of conversion signals remain
or 12 bit resolution. low.
• reset adc: This active high signal is used to reset the • CONVERT STATE: ADC enters the conversion phase on
adc. first posedge of clock after it receives high on thestart
• adc data output: This is the parallel digital data output of of conversion signal. The conversion phase lasts for N-
the ADC. cycles, where N is the resolution of the ADC.
• adc serial output: This signal is the serial output of the • PRE END OF CONVERSION STATE: During this state,
digital data. the ADC pre end of conversion signal goes high. This
• adc end of conversion: This signal depicts the end of signal has to go high 1 clock cycle before the adc end
conversion. of conversion is set high. ADC remains in this state only
• adc pre end of conversion: This signal is driven high for one clock cycle.
one clock cycle before the end of conversion signal. • END OF CONVERSION STATE: In this state, the adc
end of conversion is set high. This indicates that the ADC
has completed the conversion of analog data. On the
B. Finite State Machine Design
same posedge of clock when this signal goes high, the
The ADC Emulation controller module is designed based parallel data outputs are available on the data output bus.
on a finite state machine. A finite state machine (FSM) is
a mathematical model used to represent systems that exhibit C. Data Output modes of the ADC
distinct states and transition between them based on inputs.
It consists of a finite number of states, transitions, and events • Parallel mode: In this mode, the data is output in parallel
[4]. The different states depict the phases through which the form i.e. all the bits of data are output at the same time [2].
ADC moves when it is required to convert data. See Fig. 3. The data is output only after the entire conversion cycle
completes. The data is output on the negative edge of the
clock. The size of adc data output depends on the
resolution set. If the resolution is set to 12 bits, the adc
data output is of 12 bits.
• Serial mode: In this mode, the data is output in serial form
i.e. the bits are output one after the other [2]. As soon as
a bit is obtained after conversion, it is output.The bits
are made available on the adc serial output and data is
output from the most significant bit first to the least
significant bit in the end.

D. Sampling modes of the ADC

• Instantaneous Sampling Mode: This mode is enabled
when the asynchronous sampling enable is high. In this
mode the end of sampling defined by deassertion of
asynchronous trigger asynchronous sample. In this mode
there is a one clock cycle gap between the start of
Fig. 3. FSM Design
conversion and when the start of conversion signal goes
high. The number of clock cycles taken to convert the data
Transition from one state to another occurs based on signals
depends on the resolution set. If the resolution set is ’N’,
recieved.
the number of clock cycles taken is ’N+1’ [5]. For serial
• RESET STATE: Reset phase can be entered with logic ’H’ output mode, the first two clock cycles after start of
on reset when module is enabled. In the reset state,all conversion goes high, no output is produced. The next ’N’
activities are aborted, and the serial and the parallel cycles will produce the output.
outputs are driven low.
ADC EMULATION ON FPGA 227

• Typical SAR Mode of Operation This mode is enabled the output for 12 bit resolution of ADC. After the ADC is
when the asynchronous sampling enable is low. Here, the enabled, enough time is given for the warmup process. The start
sampling ends on the negative edge of the clock after of conversion is the input signal depicting the end of sampling
the positive edge on which the start of conversion was and start of conversion of data. On the first posedge of clock
detected high. This is the typical mode of operation. In this after the start of conversion signal goes high, the pre end of
mode the start of conversion and end of samplingare conversion and the end of conversion signals go low. Since
defined by the same start of conversion signal unlike the ADC is of 12 bit resolution, it takes 12 clock cyclesfor data
instantaneous sampling mode where a seperate signal was conversion as seen in the waveform. The conversion starts on
present to signify the end of sampling. the immediate next posedge of clock after start of conversion is
detected. The pre end of conversion and the end of conversion
E. Resolution of the ADC signals go high after 11 and 12 clock cycles respectively. The
parallel data output appears as soon as the conversion ends, i.e.
Analog-to-Digital Converter resolution is used to describe on the same posedge of clock when end of conversion signal
or measure the performance of an ADC [5]. The resolution of goes high.
an A/D converter (ADC) is specified in bits. The resolution
of the converter indicates the number of discrete values it
can produce over the range of analog values. A resolution
is the smallest voltage increment corresponding to a 1 LSB
change [6]. It is an important specification for ADC because
it determines the smallest analog input signal that an ADC can
resolve. It determines the magnitude of the quantization error
and therefore gives the maximum possible average signal-to-
noise ratio for an ideal ADC without oversampling [6].
TABLE I
Select Resolution of the ADC

select resolution number of bits of resolution Fig. 5. Output waveform for 10 bit resolution of ADC
2’b11 12
2’b10 10 Figure 5 shows the output for 10 bit resolution of ADC.
2’b01 8 Here, the ADC takes 10 clock cycles for conversion of data. The
2’b00 6 parallel data output appears after 10 clock cycles and the data is
continuously driven on the bus until the next converted data is
Table I highlights the value of the select resolution signal available. To set ADC resolution as 10, the selectresolution bits
which will produce the required resolution. The ADC used in are set to value 2. The serial data output also appears because the
this project can provide 4 resolution values. The resolution can enable serial bit is set to 1.
be set using the select resolution signal.

III. SIMULATION AND RESULTS

A. Outputs for different resolutions
The simulation of the System Verilog code was carriedout
to obtain the waveforms. Different modes of operation,
resolution and data output formats were simulated.

Fig. 6. Output waveform for 8 bit resolution of ADC

The waveform in Figure 6 shows the output for 8 bit resolution

of ADC. Here, the ADC takes 8 clock cycles for conversion of
data. The parallel data output appears after 8 clock cycles and the
data is continuously driven on the bus until the next converted data
is available. In order to set the resolution of ADC as 8 bits, the
select resolution bits are set to value 1. The serial data output also
Fig. 4. Output waveform for 12-b i t resolution of ADC appears because the enable serial bit has been set to 1. Serial
output starts appearing 1 clock cycle after the start of conversion.
The different resolutions of ADC include: 12 bit, 10bit, The last converted bit appears one clock cycle after the end of
8 bit and 6 bit. The above waveform in the figure 4 shows conversion bit is set high.
228 J. KHONRANG, M. SOMPHRUEK, P. DUANGNAKHORN, A. SIRI, K. BOONLOM

Fig. 7. Output waveform for 6 bit resolution of ADC Fig. 9. Burst mode of operation of ADC

The waveform in Figure 7 shows the output for 6 bit C. RTL Schematic of the design
resolution of ADC. Here, the ADC takes 6 clock cycles for
conversion of data. The number of start of conversion bits
shown in the waveform is one, hence one conversion occurs.
The parallel data output appears after 6 clock cycles and the
data is continuously driven on the bus until the next converted
data is available. In order to set the resolution of ADC as 6 bits,
the select resolution bits are set to value 0.

B. Normal and Burst mode of operation

Fig. 10. RTL Schematic of the Design

The RTL schematic provides a higher-level abstraction of the

design, illustrating the behavior and interconnections of the
registers and combinational logic [6]. It serves as a valuable
tool for comprehending and visualizing the design’s structure
and functionality prior to synthesis and implementation on the
target device. As seen in the above figure 10, every block within
the design represents a module or component, such as
multiplexers, gates, and flops. The interconnections between
these blocks represent the signals and buses responsible for
Fig. 8. Normal mode of operation of ADC carrying data and control information [6].

In normal mode of operation, the start of conversion bit

D. Synthesis of the design
has to be set manually for each conversion. Whereas in burst
mode, few software triggers have to be enabled which cause a
series of start of conversion bits to appear one after the other.
The waveform in figure 8 shows the ADC working in normal
mode for the initial half period and in burst mode for the next
half period. ADC is disabled for a while between the two
transitions.
The figure 9 shows the burst mode of data conversion. In
burst mode of operation, a series of start of conversion signals Fig. 11. Synthesized Design
appear one after the other. The minimum time difference
between the two start of conversion signals is 12 clock cycles. The synthesized design is the outcome of applying the
In this mode, the resolution is always set to 12 by assigning synthesis process to the RTL representation of a digital design.
the select resolution bits a value 3. Serial data is disabled and The synthesized design reflects the design at a reduced level
only parallel data appears on the bus. A series of converted data of abstraction in comparison to the RTL description [7]. As
outputs can be observed in the waveform along with the end of depicted in Figure 11, the synthesized design encompasses
conversion and the pre end of conversion signals. gates, flip-flops, and various digital components, constituting
ADC EMULATION ON FPGA 229

the logical representation of the design. It incorporates details analog input to digital. The FSM has 6 states- Reset, Ready,
regarding the interconnections among these elements and their Wait for Start of conversion (Sampling state), Conversion state,
respective logical functions. Synthesizing the design enables Pre-end of conversion state and the End of conversion state.
the evaluation of its estimated performance characteristics and The functioning of the design is verified from the sim-ulated
facilitates the analysis of logic utilization [8]. output waveforms. The waveforms show the outputs for
different configurations, different resolutions, normal and
E. Logic Utilization of the design burst mode of operation. The RTL schematic of the design
is obtained which is followed by synthesis using Vivado tool.
Artix 7 was chosen as the board. The logic utilization and
power consumption information is obtained. Fininally, the
bitstream is generated and the code is dumped on FPGA to
verify its functionality. The LUT utilization is 38, the number
of flip flops needed is 41 and the input output pin utilisation
is 20. The dynamic power utilization is 0.543W which is 87%
Fig. 12. Logic Utilization of the Design of the total power utilized and the static power utilization is
0.082W which contributes to 13% of the total power.
After running synthesis of the design, a project summary As a future scope of the work, the controller design can be
is obtained. The resource utilization of the design is shown extended to include different types of ADCs. The code can be
in the figure 12. The Look Up Table (LUT) serves as the enhanced to reduce the amount of logic cells used. The power
fundamental component of an FPGA, possessing the capability consumption of the design can also be reduced by using low
to implement any logic function involving N Boolean variables power techniques.
[9]. The LUT utilization of the design is 38, the number of flip
flops needed is 41 and the input output pin utilisation is 20. The ACKNOWLEDGMENT
LUTs and the flip flops used in teh design form 1 percent of We would like to express our gratitude to each and everyone,
the total LUT count and the input output pin utilisation is 7 who provided valuable input, insights, and assistance at every
percent of the total availability stage of the project. Their contributions were crucial to the
success of this work, and we are deeply grateful for their hard
F. Power Utilization of the design work and dedication.

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