Semiconductor LM324 Datasheet-Hoja de Datos
Semiconductor LM324 Datasheet-Hoja de Datos
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1
LM324, LM324A, LM324E, SOIC−14
D SUFFIX
TSSOP−14
DTB SUFFIX
LM224, LM2902, LM2902E, CASE 751A CASE 948G
LM2902V, NCV2902
The LM324 series are low−cost, quad operational amplifiers with
true differential inputs. They have several distinct advantages over PIN CONNECTIONS
standard operational amplifier types in single supply applications. Out 1 1 14 Out 4
The quad amplifier can operate at supply voltages as low as 3.0 V or 2 13
−
as high as 32 V with quiescent currents about one−fifth of those Inputs 1 −
4 Inputs 4
3 + + 12
associated with the MC1741 (on a per amplifier basis). The common
mode input range includes the negative supply, thereby eliminating VCC 4 11 VEE, GND
the necessity for external biasing components in many applications. 5
+ +
10
The
Inputs 2 2 3 Inputs 3
output voltage range also includes the negative power supply voltage. 6 − − 9
ESD RATINGS
Rating HBM MM Unit
ESD Protection at any Pin (Human Body Model − HBM, Machine Model − MM)
NCV2902 (Note 3) 2000 200 V
LM324E, LM2902E 2000 200 V
LM324DG/DR2G, LM2902DG/DR2G 200 100 V
All Other Devices 2000 200 V
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
Characteristics Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VIO mV
VCC = 5.0 V to 30 V
VICR = 0 V to
VCC −1.7 V,
VO = 1.4 V, RS = 0 Ω
TA = 25C − 2.0 5.0 − 2.0 3.0 − 2.0 7.0 − 2.0 7.0 − 2.0 7.0
TA = Thigh (Note 4) − − 7.0 − − 5.0 − − 9.0 − − 10 − − 13
TA = Tlow (Note 4) − − 7.0 − − 5.0 − − 9.0 − − 10 − − 10
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25C, unless otherwise noted.)
LM224 LM324A LM324, LM324E LM2902, LM2902E LM2902V/NCV2902
Characteristics Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Output Voltage − VOH V
High Limit
VCC = 5.0 V, RL = 3.3 3.5 − 3.3 3.5 − 3.3 3.5 − 3.3 3.5 − 3.3 3.5 −
2.0 kΩ, TA = 25C
VCC = 30 V 26 − − 26 − − 26 − − 26 − − 26 − −
RL = 2.0 kΩ
(TA = Thigh to Tlow)
(Note 7)
VCC = 30 V 27 28 − 27 28 − 27 28 − 27 28 − 27 28 −
RL = 10 kΩ
(TA = Thigh to Tlow)
(Note 7)
Output Voltage − VOL − 5.0 20 − 5.0 20 − 5.0 20 − 5.0 100 − 5.0 100 mV
Low Limit,
VCC = 5.0 V,
RL = 10 kΩ,
TA = Thigh to Tlow
(Note 7)
Output Source Current IO + mA
(VID = +1.0 V,
VCC = 15 V)
TA = 25C 20 40 − 20 40 − 20 40 − 20 40 − 20 40 −
TA = Thigh to Tlow 10 20 − 10 20 − 10 20 − 10 20 − 10 20 −
(Note 7)
Output Sink Current IO − mA
(VID = −1.0 V, 10 20 − 10 20 − 10 20 − 10 20 − 10 20 −
VCC = 15 V)
TA = 25C
TA = Thigh to Tlow 5.0 8.0 − 5.0 8.0 − 5.0 8.0 − 5.0 8.0 − 5.0 8.0 −
(Note 7)
(VID = −1.0 V, 12 50 − 12 50 − 12 50 − − − − − − − µA
VO = 200 mV,
TA = 25C)
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
Bias Circuitry
Common to Four
Output Amplifiers
VCC
Q15
Q16 Q14 Q22
Q13
40 k
Q19
Q18 Q20
Inputs
Q11
Q9
- Q17 Q21
Q6Q7 Q25
Q2 Q5 Q1
2.4 k
Q8 Q10
Q3 Q4 Q26
2.0 k
VEE/GND
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
CIRCUIT DESCRIPTION
The LM324 series is made using four internally VCC = 15 Vdc RL = 2.0 kΩ TA = 25C
compensated, two−stage operational amplifiers. The first
stage of each consists of differential input devices Q20
and Q18 with input buffer transistors Q21 and Q17 and
the differential to single ended converter Q3 and Q4. The
first stage performs not only the first stage gain function
1.0
but also performs the level shifting and transconductance
reduction functions. By reducing the transconductance, a
smaller compensation capacitor (only 5.0 pF) can be
employed, thus saving chip area. The transconductance
reduction is accomplished by splitting the collectors of
5.0 µs/DIV
Q20 and Q18.
Another feature of this input stage is that the input
Figure 2. Large Signal Voltage Follower Response
common mode range can include the negative supply or
ground, in single supply operation, without saturating Each amplifier is biased from an internal−voltage
either the input devices or the differential to single−ended regulator which has a low temperature coefficient thus
converter. The second stage consists of a standard current giving each amplifier good temperature characteristics as
source load amplifier stage. well as excellent power supply rejection.
3.0 V to VCC(max)
VCC
VCC
1 1.5 V to VCC(max)
1
2
2
3
3
4 1.5 V to VEE(max)
4
VEE
Single
VEE/GND Split Supplies
Supply
Figure 3.
70 70
60 60
Phase Margin
50 50
PHASE MARGIN
GAIN MARGIN
40 40
30 30
Gain Margin
20 20
10 10
0 0
1.0 10 100 1000 10000
LOAD CAPACITANCE (pF)
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
20
120
18
16 100 VCC = 15 V VEE = GND TA = 25C
A VOL, LARGE-SIGNAL
VI , INPUT VOLTAGE
14 550
450
VO, OUTPUT VOLTAGE
10 RI = 1.0 kΩ RF = 100 kΩ
Output
400
8.0
350
6.0
300
4.0 VCC = 30 V
250 VEE = GND
2.0 TA = 25C
200
CL = 50 pF
0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
1.0 10 100 1000
f, FREQUENCY (kHz) t, TIME (µs)
2.4
2.1 TA = 25C RL = ∞
90
ICC , POWER SUPPLY CURRENT
1.8
I IB, INPUT BIAS CURRENT
1.5
1.2
0.9 80
0.6
0.3
0 70
0 5.0 10 15 20 25 30 35 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V)
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
50 k
R1
5.0 k
VCC VCC 10 k VCC
R2 Vref -
- 1/4 VO
1/4 VO LM324
LM324
MC1403 + 1
+
2.5 V 1 fo = 2 u RC
Vref = VCC
2 For: fo = 1.0 kHz
R R = 16 kΩ
VO = 2.5 V 1 + R1
R2 R C C = 0.01 µF
C
1R R2
e1 +
1/4 C R Hysteresis
LM324
- VOH
R1 VO
Vref +
- 1/4
a R1 1/4 LM324
R1 LM324 eo VO
Vin -
+ VOL
b R1 VinLVinH
1R R1
- VinL = (VOL - Vref) + Vref
1/4
LM324 C Vref
+ R1 +
R R1
e2 VinH = (VOH - Vref) + Vref
R1 + R2
R1
eo = C (1 + a + b) (e2 - e1) H = R1 + R2 (VOH - VOL)
Figure 13. High Impedance Differential Amplifier Figure 14. Comparator with Hysteresis
R
1
fo =
2 u RC
R 100 k
R1 = QR
C1 1
Vin R2 C C R1 Vref = VCC
- R2 = TBP 2
1/4 R
LM324 - 100 k
1/4 R3 = TN R2
+ -
LM324 1/4
+ LM324 C1 = 10C
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
R1 + RC R2 R1 1
f = if R3 =
4 CRf R1 R2 + R1 Vref = 2 VCC
Vref
Figure 16. Function Generator Figure 17. Multiple Feedback Bandpass Filter
For less than 10% error from operational amplifier, Qo fo < 0.1
BW
where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
ORDERING INFORMATION
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V,
MARKING DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
14 14 14 14
LM324ADG AWLYWW LMx24DG LM2902DG
*
LM2902VDG AWLYWW
AWLYWW AWLYWW
1 1 1 1
14 14
LMx24EG LM2902EG
AWLYWW AWLYWW
1 1
TSSOP−14
DTB SUFFIX
CASE 948G
14 14 14 14
1 1 1 1
x = 2 or 3
A = Assembly
Location WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or ▪ = Pb−Free Package
(Note: Microdot may be in either
location)
*This marking diagram also applies to NCV2902.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
1
SCALE 1:1 NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D A 2. CONTROLLING DIMENSION: INCHES.
148 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
E AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
H 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW
DATUM PLANE H WITH THE LEADS CONSTRAINED
PERPENDICULAR TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
1 7 LEADS UNCONSTRAINED.
NOTE 8 b2 c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
B
TOP VIEW END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
NOTE 5 CORNERS).
A2
A INCHES MILLIMETERS
NOTE 3 DIM MIN MAX MIN MAX
A −−−− 0.210 −−− 5.33
L A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
SEATING b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
PLANE
A1 C 0.008 0.014 0.20 0.36
C M D 0.735 0.775 18.67 19.69
D1 D1 0.005 −−−− 0.13 −−−
eB E 0.300 0.325 7.62 8.26
e E1 0.240 0.280 6.10 7.11
14X b END VIEW e 0.100 BSC 2.54 BSC
NOTE 6 eB −−−− 0.430 −−− 10.92
SIDE VIEW 0.010 M C M B M L 0.115 0.150 2.92 3.81
M −−−− 10 −−− 10
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2 1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its produc
STYLE 1:
PIN 1. COLLECTOR STYLE 2: STYLE 3: STYLE 4:
2. BASE CANCELLED CANCELLED PIN 1. DRAIN
3. EMITTER 2. SOURCE
4. NO 3. GATE
CONNECTION 4. NO
5. EMITTER CONNECTION
6. BASE 5. GATE
7. COLLECTOR 6. SOURCE
8. COLLECTOR 7. DRAIN
9. BASE 8. DRAIN
10. EMITTER 9. SOURCE
11. NO 10. GATE
CONNECTION 11. NO
12. EMITTER CONNECTION
13. BASE 12. GATE
14. COLLECTOR 13. SOURCE
14. DRAIN
STYLE 5:
PIN 1. GATE STYLE 6: STYLE 7: STYLE 8:
2. DRAIN PIN 1. COMMON CATHODE PIN 1. NO CONNECTION PIN 1. NO CONNECTION
3. SOURCE 2. ANODE/CATHODE 2. ANODE 2. CATHODE
4. NO CONNECTION 3. ANODE/CATHODE 3. ANODE 3. CATHODE
5. SOURCE 4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
6. DRAIN 5. ANODE/CATHODE 5. ANODE 5. CATHODE
7. GATE 6. NO CONNECTION 6. NO CONNECTION 6. NO CONNECTION
8. GATE 7. ANODE/CATHODE 7. ANODE 7. CATHODE
9. DRAIN 8. ANODE/CATHODE 8. ANODE 8. CATHODE
10. SOURCE 9. ANODE/CATHODE 9. ANODE 9. CATHODE
11. NO CONNECTION 10. NO CONNECTION 10. NO CONNECTION 10. NO CONNECTION
12. SOURCE 11. ANODE/CATHODE 11. ANODE 11. CATHODE
13. DRAIN 12. ANODE/CATHODE 12. ANODE 12. CATHODE
14. GATE 13. NO CONNECTION 13. NO CONNECTION 13. NO CONNECTION
14. COMMON ANODE 14. COMMON 14. COMMON ANODE
CATHODE
STYLE 9:
PIN 1. COMMON CATHODE STYLE 10: STYLE 11: STYLE 12:
2. ANODE/CATHODE PIN 1. COMMON PIN 1. CATHODE PIN 1. COMMON CATHODE
3. ANODE/CATHODE CATHODE 2. CATHODE 2. COMMON ANODE
4. NO CONNECTION 2. ANODE/CATHODE 3. CATHODE 3. ANODE/CATHODE
5. ANODE/CATHODE 3. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE
6. ANODE/CATHODE 4. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE
7. COMMON ANODE 5. ANODE/CATHODE 6. CATHODE 6. COMMON ANODE
8. COMMON ANODE 6. NO CONNECTION 7. CATHODE 7. COMMON CATHODE
9. ANODE/CATHODE 7. COMMON ANODE 8. ANODE 8. ANODE/CATHODE
10. ANODE/CATHODE 8. COMMON 9. ANODE 9. ANODE/CATHODE
11. NO CONNECTION CATHODE 10. ANODE 10. ANODE/CATHODE
12. ANODE/CATHODE 9. ANODE/CATHODE 11. ANODE 11. ANODE/CATHODE
13. ANODE/CATHODE 10. ANODE/CATHODE 12. ANODE 12. ANODE/CATHODE
14. COMMON CATHODE 11. ANODE/CATHODE 13. ANODE 13. ANODE/CATHODE
12. ANODE/CATHODE 14. ANODE 14. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its produc
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
14 CASE 751A−03
ISSUE L
1
SCALE 1:1 DATE 03 FEB 2016
D AB NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERSINCHES
13Xb DIM A MIN
A1 A3 MAXMIN MAX
0.25 M B M
0.25 M C A S B S b D E 1.35 1.75 0.054 0.068
eH 0.10 0.25 0.004 0.010
h L M 0.19 0.25 0.008 0.010
DETAIL A 0.35 0.49 0.014 0.019
h 8.55 8.75 0.337 0.344
A X 45 ° 3.80 4.00 0.150 0.157
1.27 BSC 0.050 BSC
5.806.20 0.228 0.244
0.250.50 0.010 0.019
0.10 0.401.25 0.016 0.049
e A1 M 0 °7 ° 0 °7 °
SEATING
CPLANE
GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG AWLYWW
1
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and
soldering details, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
STYLE 1:
PIN 1. COMMON CATHODE STYLE 2: STYLE 3: STYLE 4:
2. ANODE/CATHODE CANCELLED PIN 1. NO CONNECTION PIN 1. NO CONNECTION
3. ANODE/CATHODE 2. ANODE 2. CATHODE
4. NO CONNECTION 3. ANODE 3. CATHODE
5. ANODE/CATHODE 4. NO CONNECTION 4. NO CONNECTION
6. NO CONNECTION 5. ANODE 5. CATHODE
7. ANODE/CATHODE 6. NO CONNECTION 6. NO CONNECTION
8. ANODE/CATHODE 7. ANODE 7. CATHODE
9. ANODE/CATHODE 8. ANODE 8. CATHODE
10. NO CONNECTION 9. ANODE 9. CATHODE
11. ANODE/CATHODE 10. NO CONNECTION 10. NO CONNECTION
12. ANODE/CATHODE 11. ANODE 11. CATHODE
13. NO CONNECTION 12. ANODE 12. CATHODE
14. COMMON ANODE 13. NO CONNECTION 13. NO CONNECTION
14. COMMON CATHODE 14. COMMON ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onse
TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1 14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
14 8
0.25 (0.010) 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
M NOT EXCEED 0.25 (0.010) PER SIDE.
B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
L PROTRUSION. ALLOWABLE DAMBAR
−U− N PROTRUSION SHALL BE 0.08 (0.003) TOTAL
PIN 1 IDENT.
F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
1
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE
0.15 (0.006) T U S A K −W−.
1 1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
0.65 ▪ = Pb−Free Package
PITCH
(Note: Microdot may be in either
location)
14X
14X
*This information is generic. Please refer to
0.36 device data sheet for actual part marking.
1.26
DIMENSIONS: MILLIMETERS Pb−Free indicator, “G” or microdot “▪”, may
or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER: Electronic versions are uncontrolled except when accessed directly from the Document Repository.
98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION:
TSSOP−14 WB PAGE 1 OF 1