Analog and Digital Electronics

Dr. K.M. Ravi Eswar,

Assistant professor, Dept. EEE, SRM IST, KTR
 Sequential Circuits

Every digital system is likely to have combinational circuits,

most systems encountered in practice also include storage
elements, which require that the system be described in term
of sequential logic.

2
Synchronous Clocked Sequential Circuit

A sequential circuit may use many flip-flops to store as many

bits as necessary. The outputs can come either from the
combinational circuit or from the flip-flops or both.

3
a, Flip-flop always have a clock
Latches doesn’t have a clock signal
signal
Flip-flop can be build from Latches Latches can be build from gates
 Latches --SR Latch
The SR latch is a circuit with two cross-coupled NOR gates or
two cross-coupled NAND gates. It has two inputs labeled S
for set and R for reset.

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SR Latch with NAND Gates

6
 SR Latch with Control Input

The operation of the basic SR latch can be modified by

providing an additional control input that determines when
the state of the latch can be changed. In Fig. 5-5, it consists
of the basic SR latch and two additional NAND gates.

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 D Latch

One way to eliminate the undesirable condition of the

indeterminate state in SR latch is to ensure that inputs S
and R are never equal to 1 at the same time in Fig 5-5. This
is done in the D latch.

1
0
Graphic Symbols for latches
A latch is designated by a rectangular block with inputs on
the left and outputs on the right. One output designates the
normal output, and the other designates the complement
output.

1
2
 Flip-Flops

The state of a latch or flip-flop is switched by a change in

the control input. This momentary change is called a trigger
and the transition it cause is said to trigger the flip-flop. The
D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic 1
level. As long as the pulse input remains in the level, any
changes in the data input will change the output and the
state of the latch.

1
3
Clock Response in Latch

In Fig (a) a positive level response in the control input

allows changes, in the output when the D input changes
while the clock pulse stays at logic 1.

1
4
Clock Response in Flip-Flop

1
5
S-R Flip Flop

• The SET-RESET flip flop is designed with the help of two NOR gates and
also two NAND gates. These flip flops are also called S-R Latch.
• S-R Flip Flop using NOR Gate The design of such a flip flop includes two
inputs, called the SET [S] and RESET [R].
• There are also two outputs, Q and Q’.
• From the diagram it is evident that the flip flop has mainly four
states. They are S=1, R=0—Q=1, Q’=0 This state is also called the SET
state.
• S=0, R=1—Q=0, Q’=1 This state is known as the RESET state. In both
the states you can see that the outputs are just compliments of each
other and that the value of Q follows the value of S.
• S=0, R=0—Q & Q’ = Remember If both the values of S and R are
switched to 0, then the circuit remembers the value of S and R in
their previous state.
• S=1, R=1—Q=0, Q’=0 [Invalid] This is an invalid state because the
values of both Q and Q’ are 0. They are supposed to be compliments
of each other. Normally, this state must be avoided.
S-R Flip Flop using NAND Gate
• Like the NOR Gate S-R flip flop, this one also has four states. They are S=1,
R=0—Q=0, Q’=1 This state is also called the SET state.
• S=0, R=1—Q=1, Q’=0 This state is known as the RESET state. In both the
states you can see that the outputs are just compliments of each other and
that the value of Q follows the compliment value of S.
• S=0, R=0—Q=1, & Q’ =1 [Invalid] If both the values of S and R are switched
to 0 it is an invalid state because the values of both Q and Q’ are 1. They
are supposed to be compliments of each other. Normally, this state must
be avoided.
• S=1, R=1—Q & Q’= Remember If both the values of S and R are switched to
1, then the circuit remembers the value of S and R in their previous state.
Gated SR Latch
• The basic latch changes its state when the input
signals change

• It is hard to control when these input signals will

change and thus it is hard to know when the latch may
change its state.

• We want to have something like an Enable input

• In this case it is called the “Clock” input because it is

desirable for the state changes to be synchronized
Circuit Diagram for the Gated SR Flip-Flop

[ Figure 5.5a from the textbook ]

Circuit Diagram for the Gated SR Flip-Flop

This is the “gate”

of the gated latch
Circuit Diagram for the Gated SR Flip-Flop

Notice that these

are complements
of each other
Circuit Diagram and Characteristic Table
for the Gated SR Flip-Flop

[ Figure 5.5a-b from the textbook ]

Circuit Diagram and Graphical Symbol
for the Gated SR Flip-Flop

[ Figure 5.5a,c from the textbook ]

Timing Diagram for the Gated SR Flip-Flop

[ Figure 5.5c from the textbook ]

Gated SR Flip-Flop with NAND gates

S
Q

Clk

Q
R

[ Figure 5.6 from the textbook ]

Gated SR Flip-Flop with NAND gates

S
Q

Clk

Q
R

In this case the “gate” is

constructed using NAND
gates! Not AND gates.
 Edge-Triggered Flip-Flops
• In basic master-slave flip-flops, master is enabled during the entire period the control
input is 1.
• This can result in 0’s and 1’s catching.
• To avoid this, signals on information lines are restricted from changing during the time the
master is enabled.
• Also a delay in the output since master’s state is established during the positive edge and
transferred to the slave on the negative edge of clock.
• Edge-triggered flip-flops use just one of the edges of the clock signal.
• This is referred to as the triggering edge.
• Response to triggering edge at the output of the flip-flop is almost immediate
(depends only on propagation delay times).
• Once triggering occurs, flip-flop is unresponsive to information input changes until
the next triggering edge.
Edge-Triggered SR Flip-Flops
1. C = 0. Regardless of input at D,
outputs of gates 2,3 are 1. So 𝑆 =
𝑅 = 1. State of latch is held.
2. Assume D = 0: Output of gate 4 is 1,
output of gate 1 is 0. When C goes to
1: all inputs to gate 3 are 1, output
changes to 0. Output of gate 2
remains at 1 since output of gate 1 is
0. So 𝑆 = 1, 𝑅 = 0. Output of gate 3
(0) is fed to input of gate 4. Output
of gate 4, gate 1 not affected by
changes to D.
3. Assume C = 0, D = 1. Outputs of
gates 2,3, are 1. Output of gate 4 is
0, output of gate 1 is 1. When C goes
𝑆 𝑅 Latch to 1: output of gate 2 is 0, output of
gate 3 remains at 1. So 𝑆 = 0, 𝑅 =
1. Output from gate 2 is input to
gates 1, 3 so their outputs remain at
1. Changes in D have no affect on
state of flip-flop while C = 1.
Edge-Triggered SR Flip-Flops
Timing Diagram

During setup and hold times 𝑡𝑠𝑢 , 𝑡ℎ with respect to the

triggering edge of the clock, D input must not change.
 Negative-Edge Triggered D Flip-Flop
• A falling edge (high to low transition) of control signal is used to sample
the D input line.
• Simply place inverter at the control input of the flip-flop.
JK flipflop
T-flipflop
Edge triggered D flipflop
Edge triggered SR flipflop
Positive-Edge Triggered T-Flip-Flop
 Characteristic Equations
• Next state table: Shows the value of the next state of the flip-flop for
each combination of values to the present state of the flip-flops and their
information lines.
• The algebraic description of the next-state table of a flip-flop is called the
characteristic equation of the flip-flop.
• Obtained by constructing the K-map for 𝑄 + in terms of the present
state and information input variables.
Next State Tables
Characteristic Equations
 T Flip Flop

• This is a much simpler version of the J-K flip flop. Both the J and K inputs
are connected together and thus are also called a single input J-K flip flop.
• When clock pulse is given to the flip flop, the output begins to toggle.
Here also the restriction on the pulse width can be eliminated with a
masterslave or edge-triggered construction.
 Flip-Flop Solution

• Use edge-triggering instead of master-slave

• An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
• Edge-triggered flip-flops can be built directly
at the electronic circuit level, or
• A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.
 Edge-Triggered D Flip-Flop
D D Q S Q
Q
C
• The edge-triggered C C Q R Q Q
D flip-flop is the
same as the master-
slave D flip-flop
• It can be formed by:
– Replacing the first clocked S-R latch with a clocked D latch or
– Adding a D input and inverter to a master-slave S-R flip-flop
• The delay of the S-R master-slave flip-flop can be avoided since
the 1s-catching behavior is not present with D replacing S and R
inputs
• The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
• It is called a negative-edge triggered flip-flop
 Positive-Edge Triggered D Flip-Flop
D D Q S Q Q
C
C C Q R Q Q

• Formed by
adding inverter
to clock input

• Q changes to the value on D applied at the positive clock edge within timing constraints to be
specified
• Our choice as the standard flip-flop for most sequential circuits

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Edge-Triggered FF Operation

55
Edge-Triggered FF Operation

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Edge-Triggered FF Operation

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Edge-Triggered FF Operation

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 RS FLIP FLOP JK FLIP FLOP
Truth Table Excitation Table Truth Table Excitation Table
S R Qn+1 Qn Qn+1 S R J K Qn+1 Qn Qn+1 J K

0 0 Qn 0 0 0 X 0 0 Qn 0 0 0 X
0 1 0 0 1 1 0 0 1 0 0 1 1 X
1 0 1 1 0 0 1 1 0 1 1 0 X 1
1 1 X 1 1 X 0 1 1 Qn’ 1 1 X 0

D FLIP FLOP

Truth Table Excitation Table

D Qn Qn+1 Qn Qn+1 D

0 0 0 0 0 0

0 1 0 0 1 1

1 0 1 1 0 0

1 1 1 1 1 1

T FLIP FLOP
Truth Table Excitation Table
T Qn Qn+1 Qn Qn+1 T

0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
• A sequential circuit has one input and one output. The
state diagram is shown in figure. Design the sequential
circuit with a) D-FF b) T-FF c) RS-FF d) JK-FF

• a) T-FF
• A sequential circuit has one input and one
output. The state diagram is shown in figure.
Design the sequential circuit with a) D-FF b) T-FF
c) RS-FF d) JK-FF

• a) RS-FF
• A sequential circuit has one input and one
output. The state diagram is shown in figure.
Design the sequential circuit with a) D-FF b) T-
FF c) RS-FF d) JK-FF

• a) JK-FF
• The unused states are taken as don’t cares
ANALYSIS PROBLEMS
• Construct the transition table, state table, state diagram for
the Moore sequential circuit given
• Construct the transition table, state table, state diagram for the sequential
circuit given
Comparisons
Definitions:

State Table:
The relationship that exists among the inputs, outputs, present states and next states can be
specified by either the state table or the state diagram

Transition Table:
Transition table is table of states and transition, useful to analyze an asynchronous circuit from
the circuit diagram

Flow Table:
In a flow table the states are named by letter symbols