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Master Slave Flip Flop

The document discusses master-slave flip-flops, which are pulse-triggered flip-flops consisting of a master and a slave section that store binary symbols. It explains the operation of master-slave SR and JK flip-flops, highlighting their behavior during control signal transitions and the potential for metastability. Additionally, it covers edge-triggered flip-flops, their timing characteristics, and the concept of registers, including different methods of data transfer such as parallel and serial communication.

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14 views23 pages

Master Slave Flip Flop

The document discusses master-slave flip-flops, which are pulse-triggered flip-flops consisting of a master and a slave section that store binary symbols. It explains the operation of master-slave SR and JK flip-flops, highlighting their behavior during control signal transitions and the potential for metastability. Additionally, it covers edge-triggered flip-flops, their timing characteristics, and the concept of registers, including different methods of data transfer such as parallel and serial communication.

Uploaded by

Prash
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© © All Rights Reserved
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Master Slave Flip Flop

Master-Slave Flip-Flops
(Pulse Triggered Flip-Flops)
• Aside from latches, two categories of flip-flops.
– Master-slave flip-flops (pulse-triggered flip-flops)
– Edge-triggered flip-flops
• Latches have immediate output response
(known as transparency)
• May be undesirable:
– May be necessary to sense the current state of a
flip-flop while allowing new state information to
be entered.
Master-Slave SR Flip-Flop
• Two sections, each capable of storing a binary symbol.
• First section is referred to as the master and the second
section as the slave.
• Information is entered into the master on one edge or level of
a control signal and is transferred to the slave on the next
edge or level of the control signal.
• Each section is a latch.
Master-Slave SR Flip-Flop

• C = 0:
– Master is disabled. Any changes to S,R ignored.
– Slave is enabled. Is in the same state as the master.
• C = 1:
– Slave is disabled (retains state of master)
– Master is enabled, responds to inputs. Changes in state of master are not reflected in disabled
slave.
• C = 0:
– Master is disabled.
– Slave is enabled and takes on new state of the master.
• Important: For short periods during rising and falling edges, both master and slave are
Master-Slave SR Flip-Flop

Slave only takes on state


Pulse of the master at
symbol
indicates
master Postponed output
enabled indicator: output
when C = 1 change postponed until
and state of end of pulse
master
transferred If S, R = 1 when control
to slave at signal goes from high to
the end of low we are in an
the pulse unpredicable state. Can
period. cause metastable state.
Timing Diagram for
Master-Slave SR flip-flop
Master-Slave JK Flip-Flop
• The output state of a master-slave SR flip-flop
is undefined upon returning the control input
to 0 when S = R = 1.
– Necessary to avoid this condition.
• Master-slave JK flip-flop allows its two
information input lines to be simultaneously 1.
– Results in toggling the output of the flip flop.
Master-Slave JK Flip-Flop

• Assume in 1-state, C = 0, J = K = 1.
– Due to feedback, the output of the J-gate is 0, output of K-gate is 1.
– If clock is changed to C = 1 then master is reset.
• Assume in 0-state, C = 0, J = K = 1.
– Due to feedback, the output of the J-gate is 1, output of K-gate is 0.
– If clock is changed to C = 1 then master is set.
• 1 on J input line, 0 on K input line sets the flip-flop.
– If in 1-state, unchanged b/c S,R set to 0.
– If in 0-state, S set to 1, R set to 0.
• 0 on J input, 1 on K input line resets the flip-flop. Why?
Master-Slave JK Flip-Flop
Timing Diagram for
Master-Slave JK Flip-Flop
0’s and 1’s Catching
• The master is enabled during the entire period the control-signal is 1.
• If the slave latch is in its 1-state, then a logic-1 on K-input line causes
the master-latch to reset. Slave becomes reset when control signal
returns to 0.
• This is known as 0’s catching (2nd pulse).
– Note: if a subsequent 1-signal on J input line and C is still 1, master does
not become set again (due to feedback not changing).
• If slave latch is in 0-state, logic-1 on J input line while control signal is
1 causes the master latch to be set and slave will be set upon
occurrence of the falling edge.
• This is known as 1’s catching (3rd pulse).
• In many applications, 0’s and 1’s catching behavior is undesirable.
Normally recommended that the J and K input values should be held
fixed during the entire interval the master is enabled.
• Any changes in J, K must occur while the control signal is 0.
0’s Catching

• Assume in 1-state
• gets set to 1 briefly.
– Master gets reset, Slave will become reset when Clock goes to 0.
• goes to 0.
• goes to 1. What happens?
• Nothing! Slave will still become reset when Clock goes to 0.
• Why?
Edge-Triggered Flip-Flops
• In basic master-slave flip-flops, master is enabled during the entire
period the control input is 1.
– This can result in 0’s and 1’s catching.
– To avoid this, signals on information lines are restricted from changing
during the time the master is enabled.
– Also a delay in the output since master’s state is established during the
positive edge and transferred to the slave on the negative edge of clock.
• Edge-triggered flip-flops use just one of the edges of the clock signal.
– This is referred to as the triggering edge.
• Response to triggering edge at the output of the flip-flop is almost
immediate (depends only on propagation delay times).
• Once triggering occurs, flip-flop is unresponsive to information input
changes until the next triggering edge.
Edge-Triggered Flip-Flops
1. C = 0. Regardless of input at D,
outputs of gates 2,3 are 1. So State of
latch is held.
2. Assume D = 0: Output of gate 4 is 1,
output of gate 1 is 0. When C goes to
1: all inputs to gate 3 are 1, output
changes to 0. Output of gate 2
remains at 1 since output of gate 1 is
0. So . Output of gate 3 (0) is fed to
input of gate 4. Output of gate 4,
gate 1 not affected by changes to D.
3. Assume C = 0, D = 1. Outputs of gates
2,3, are 1. Output of gate 4 is 0,
output of gate 1 is 1. When C goes to
Latch 1: output of gate 2 is 0, output of
gate 3 remains at 1. So . Output from
gate 2 is input to gates 1, 3 so their
outputs remain at 1. Changes in D
have no affect on state of flip-flop
while C = 1.
Edge-Triggered Flip-Flops
Timing Diagram

During setup and hold times with respect to the triggering


edge of the clock, D input must not change.
Negative-Edge Triggered D Flip-Flop
• A falling edge (high to low transition) of
control signal is used to sample the D input
line.
• Simply place inverter at the control input of
the flip-flop.
Positive-Edge Triggered T-Flip-Flop
Characteristic Equations
• Next state table: Shows the value of the next state
of the flip-flop for each combination of values to
the present state of the flip-flops and their
information lines.
• The algebraic description of the next-state table of
a flip-flop is called the characteristic equation of
the flip-flop.
• Obtained by constructing the K-map for in terms
of the present state and information input
variables.
Next State Tables
Characteristic Equations
Registers
• A collection of flip-flops taken as an entity.
• Function: Hold information within a digital system
so that it is available to the logic elements during
the computing process.
• Each combination of stored information is known as
the state or content of the register.
• Shift register: Registers that are capable of moving
information upon the occurrence of a clock-signal.
– Unidirectional
– bidirectional
Registers
• Two basic ways in which information can be
entered/outputted
– Parallel: All 0/1 symbols handled simultaneously. Require
as many lines as symbols being transferred.
– Serial: Involves the symbol-by-symbol availability of
information in a time sequence.
• Four possible ways registers can transfer information:
– Serial-in/serial-out
– Serial-in/parallel-out
– Parallel-in/parallel-out
– Parallel-in/serial-out

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