Logic and Computer Design Fundamentals

Chapter 6 – Sequential Circuits

Part 1 – Storage Elements and Sequential Circuit Analysis

Charles Kime & Thomas Kaminski

© 2004 Pearson Education, Inc.

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Overview
 Part 1 - Storage Elements and Analysis
• Introduction to sequential circuits
• Types of sequential circuits
• Storage elements
 Latches
 Flip-flops
• Sequential circuit analysis
 State tables
 State diagrams
• Circuit and System Timing
 Part 2 - Sequential Circuit Design
• Specification
• Assignment of State Codes
• Implementation

Chapter 6 - Part 1 2
 Introduction to Sequential Circuits

Inputs Outputs

 A Sequential Combina-tional

Logic
circuit contains:
Storage

• Storage elements: Elements

Latches or Flip-Flops Next

• Combinatorial Logic: State State

 Implements a multiple-output
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State, are
signals from storage elements.
 The remaining outputs, Next State are
inputs to storage elements.
Introduction to Sequential Circuits

Inputs Outputs
Combina-tional

Logic
Storage

Elements
 Combinatorial Logic Next
• Next state function State State
Next State = f(Inputs, State)
• Output function (Mealy)
Outputs = g(Inputs, State)
• Output function (Moore)
Outputs = h(State)
 Output function type depends on specification and affects the
design significantly
Types of Sequential Circuits
 Depends on the times at which:
• storage elements observe their inputs, and
• storage elements change their state
 Synchronous
• Behavior defined from knowledge of its signals at discrete
instances of time
• Storage elements observe inputs and can change state only in
relation to a timing signal (clock pulses from a clock)
 Asynchronous
• Behavior defined from knowledge of inputs an any instant of
time and the order in continuous time in which inputs change
• If clock just regarded as another input, all circuits are
asynchronous!
• Nevertheless, the synchronous abstraction makes complex
designs tractable!
Synchronous Clocked Sequential Circuit

Inputs Combinational Outputs

circuit Flip Flops

Next
Present
state
state

Timing signal

(clock)
Clock
Clock

aa periodic
periodic external
external event
event (input)
(input) Clock
synchronizes when current state changes happen
synchronizes when current state changes happen
keeps system well-behaved
keeps system well-behaved
makes it easier to design and build large systems
makes it easier to design and build large systems
Basic (NOR) S – R Latch
● SR latch is made from two cross-coupled NORs
● Usually S=0 and R=0
● When Q = 1, the SR-Latch is in the Set state
● When Q = 0, the SR-Latch is in the Reset state
● S=1 and R=1 generates illogical results
Basic (NOR) S – R Latch

 Cross-coupling two R (reset)

Q
NOR gates gives the
S – R Latch:
 Which has the time Q
S (set)
sequence
behavior:
Time R S Q Q Comment

0 0 ? ? Stored state unknown

0 1 1 0 “Set” Q to 1

0 0 1 0 Now Q “remembers” 1

1 0 0 1 “Reset” Q to 0

0 0 0 1 Now Q “remembers” 0

1 1 0 0 Both go low

0 0 ? ? Unstable!
Basic (NAND) S – R Latch

● SR latch is made from two cross-coupled NANDs

● Sometimes called S R latch
● Usually S=1 and R=1
● S=0 and R=0 generates illogical results
Basic (NAND) S – R Latch
 “Cross-Coupling” S (set)
Q
two NAND gates gives
the S -R Latch:
 Which has the time Q
R (reset)
sequence behavior:
Time R S Q Q Comment

1 1 ? ? Stored state unknown

1 0 1 0 “Set” Q to 1

 S = 0, R = 0 is 1 1 1 0 Now Q “remembers” 1

0 1 0 1 “Reset” Q to 0
forbidden as 1 1 0 1 Now Q “remembers” 0
input pattern 0 0 1 1 Both go high

1 1 ? ? Unstable!

Chapter 6 - Part 1 10
Clocked S - R Latch
 Adding two NAND S
gates to the basic Q

S - R NAND latch
C
gives the clocked
S – R latch: Q
R

 Has a time sequence behavior similar to the basic S-R

latch except that the S and R inputs are only observed
when the line C is high.
 C means “control” or “clock”.
 Clocked S - R Latch (continued)

 The Clocked S-R Latch can be described by a table:

Q(t) S R Q(t+1) Comment
S
Q 0 0 0 0 No change
C 0 0 1 0 Clear Q
0 1 0 1 Set Q
Q
R 0 1 1 ??? Indeterminate
 The table describes 1 0 0 1 No change
1 0 1 0 Clear Q
what happens after the 1 1 0 1 Set Q
clock [at time (t+1)] 1 1 1 ??? Indeterminate
based on:
• current inputs (S,R) and
• current state Q(t).

Chapter 6 - Part 1 12
 Clocked S - R Latch (continued)

Avoid uncontrolled latch changes

C = 0 disables all latch state changes

Control signal enables data change when C = 1

D Latch

 Adding an inverter D

to the S-R Latch, Q

gives the D Latch: C

 Note that there are Q

no “indeterminate”
states! The graphic symbol for a
Q D Q(t+1) Comment D Latch is:
0 0 0 No change D Q

0 1 1 Set Q

1 0 0 Clear Q
C Q
1 1 1 No Change
Flip-Flops

 The latch timing problem

 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage elements
 Direct inputs to flip-flops
 Flip-flop timing

Chapter 6 - Part 1 15
The Latch Timing Problem

 In a sequential circuit, paths may exist through

combinational logic:
• From one storage element to another
• From a storage element back to the same storage
element
 The combinational logic between a latch output
and a latch input may be as simple as an
interconnect
 For a clocked D-latch, the output Q depends on
the input D whenever the clock input C has
value 1

Chapter 6 - Part 1 16
 The Latch Timing Problem (continued)
 Consider the following circuit:

D Q Y

 Suppose that initially Y = 0. Clock C Q

Clock

Y
 As long as C = 1, the value of Y continues to change!
 The changes are based on the delay present on the loop
through the connection from Y back to Y.
 This behavior is clearly unacceptable.
 Desired behavior: Y changes only once per clock pulse

Chapter 6 - Part 1 17
The Latch Timing Problem (continued)

 A solution to the latch timing problem is

to break the closed path from Y to Y
within the storage element
 The commonly-used, path-breaking
solutions replace the clocked D-latch
with:
• a master-slave flip-flop
• an edge-triggered flip-flop

Chapter 6 - Part 1 18
S-R Master-Slave Flip-Flop
 Consists of two clocked
S S S
Q
S-R latches in series C
Q Q

C C
with the clock on the
R R
second latch inverted Q R Q Q

 The input is observed

by the first latch with C = 1
 The output is changed by the second latch with C = 0
 The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
 The behavior demonstrated by the example with D
driven by Y given previously is prevented since the
clock must change from 1 to 0 before a change in Y
based on D can occur.

Chapter 6 - Part 1 19
Flip-Flop Problem
 The change in the flip-flop output is delayed by
the pulse width which makes the circuit slower or
 S and/or R are permitted to change while C = 1
• Suppose Q = 0 and S goes to 1 and then back to 0 with
R remaining at 0
 The master latch sets to 1
 A 1 is transferred to the slave
• Suppose Q = 0 and S goes to 1 and back to 0 and R
goes to 1 and back to 0
 The master latch sets and then resets
 A 0 is transferred to the slave
• This behavior is called 1s catching

Chapter 6 - Part 1 20
Flip-Flop Solution

 Use edge-triggering instead of master-slave

 An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
 Edge-triggered flip-flops can be built directly at
the electronic circuit level, or
 A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.

Chapter 6 - Part 1 21
 Edge-Triggered D Flip-Flop
 The edge-triggered
D D S
D flip-flop is the Q Q Q

same as the master- C

C C
slave D flip-flop Q R Q Q

 It can be formed by:

• Replacing the first clocked S-R latch with a clocked D latch or
• Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be
avoided since the 1s-catching behavior is not present
with D replacing S and R inputs
 The change of the D flip-flop output is associated with
the negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
Chapter 6 - Part 1 22
Positive-Edge Triggered D Flip-Flop
 Formed by
D D Q S
Q
adding inverter
Q

to clock input C C
Q R Q Q

 Q changes to the value on D applied at the

positive clock edge within timing constraints to
be specified
 Our choice as the standard flip-flop for most
sequential circuits

Chapter 6 - Part 1 23
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Chapter 6 - Part 1 24