DSD Assignment 1

Solution

1. Verilog code for the flip-flop with a positive-edge clock and

synchronous set.
a) Testbench
//prob1
module flop (clk, d, s, q);
input clk, d, s;
output q;
reg q;
always @(posedge clk)
begin
if (s)
q <= 1’b1;
else
q <= d;
end
endmodule

//tstb
module flop_tb;
reg clk,d,s;
wire q;

flop flop_tst(clk, d, s, q);

always #5 clk <= ~clk;

 initial begin
clk=0;
$monitor("time=%02d s=%01b clk=%01b d=%01b q=%01b",$time, s,
clk, d, q);

#2 s=1;d=1;
#2 s=1;d=0;
#2 s=0;
#2 d=1;
#2 d=0;
#7 d=1;
#30 $finish;
end

endmodule
b) Truth table
clk d s Q

x 1 1

0 0 0

1 0 1

c) Simulation
2. Verilog code for the flip-flop with a positive-edge clock and clock
enable.
a) Testbench
//prob2
module flop1 (clk, d, ce, q);
input clk, d, ce;
output q;
reg q;
always @(posedge clk)
begin
if (ce)
q <= d;
end
endmodule

//tstbnch
module flop1_tb;
reg clk, d, ce;
wire q;

flop1 flop1_tst(clk, d, ce,q);

always #3 clk <= ~clk;

initial begin
clk=0; ce=0;
$monitor("time=%02d ce=%01b clk=%01b d=%01b
q=%01b",$time, ce, clk, d, q);
#1 d=0;
#3 d=1;
 #5 ce=1;
#1 d=0;
#3 d=1;
#1 d=0;
#5 $finish;
end

endmodule
 b) Truth table
clk d ce q

0 1 0

1 1 1

x 0 Q0
( unchanged)

c) Simulation
3. Verilog code for a 4-bit register with a positive-edge clock,
asynchronous set and clock enable.
a) Testbench
//prob3
module rg4b (clk, d, ce, pre, q);
input clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(posedge clk or posedge pre)
begin
if (pre)
q <= 4'b1111;

else if (ce)
q <= d;
end
endmodule

//tstb
module rg4b_tb();
reg clk, ce, pr;
reg [3:0] d;
wire [3:0] q;
integer i;

rg4b rg4b_tst(clk, d, ce, pr, q);

always #3 clk <= ~clk;
initial begin
#1 d=4'b0000;
 #1 ce=1;
#1 pr=0;
#100 $finish;
end
initial begin
clk=0; pr=1;
$monitor("time=%02d pr=%01b clk=%01b ce=%01b
d=%04b q=%04b",$time, pr, clk, ce, d, q);

for(i=0;i<16;i=i+1) begin

#6 d=d+4'b0001;
end
#55 $finish;
end
endmodule
b) Truth table
clk d ce pre q
poseedge x x 1 1111
poseedge 0000 1 0 0000
poseedge 0001 1 0 0001
poseedge 0010 1 0 0010
poseedge 0011 1 0 0011
poseedge 0100 1 0 0100
poseedge 0101 1 0 0101
poseedge 0110 1 0 0110
poseedge 0111 1 0 0111
poseedge 1000 1 0 1000
poseedge 1001 1 0 1001
poseedge 1010 1 0 1010
poseedge 1011 1 0 1011
poseedge 1100 1 0 1100
poseedge 1101 1 0 1101
poseedge 1110 1 0 1110
poseedge 1111 1 0 1111
c) Simulation
4. Following is the Verilog code for a latch with a positive gate.
a) Testbench
//prob 4
module latch (g, d, q);
input g, d;
output q;
reg q;
always @(g or d)
begin
if (g)
q <= d;
end
endmodule

//tstbh
module latch_tb();
reg g, d;
reg [2:0] dlay; // 3bits dlay
reg [1:0] dlay2; // 2bits dlay
wire q;
integer i;

//instantiate design and connect design ports with TB signals

latch latch_tst(g,d,q);

// initializ stimulus
initial begin
$monitor("time=%02d g=%01b d=%01b q=%01b", $time,
g,d,q);
 d=0;g=0;

for (i=0;i<6;i=i+1)begin
dlay=$random;
dlay2=$random;
#(dlay) g<=~g;
#(dlay2) d<=i; //d rndly took the least bit from i
end
end
endmodule
 b) Truth table
g d q
1 1 1
1 0 0
0 x Q0 (unchanged)

c) Simulation
5. Verilog code for a latch with a positive gate and an asynchronous clear.
a) Testbench
//prob 5
module latch1 (clr,g, d, q);
input clr,g, d;
output q;
reg q;
always @(g or d) begin
if (clr)
q <= 0;

else if (g)
q <= d;

end

endmodule

//tstbh
module latch1_tb();
reg g, d, clr;
reg [2:0] dlay; // 3bits dlay
reg [1:0] dlay2; // 2bits dlay
wire q;
integer i;

//instantiate design and connect design ports with TB signals

latch1 latch_tst(clr,g,d,q);

// initializ stimulus
 initial begin
$monitor("time=%02d clr=%01b g=%01b d=%01b q=%01b",
$time,clr,g,d,q);

d=0;g=0;clr=1;

#10 clr=0;
for (i=0;i<6;i=i+1)begin
dlay=$random;
dlay2=$random;
#(dlay) g<=~g;
#(dlay2) d<=i; //d rndly took the least bit from i
end
end
endmodule
 a) Truth table
g clr d q
x 1 x 0
1 0 0 0
1 0 1 1
0 0 x Q0

b) Simulation
6. Verilog code for the flip-flop with a positive-edge clock and
synchronous set.
a) Testbench
//prob 6
module latch4b (pr, g, d, q);
input g, pr;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(g or d or pr)
begin
if (pr)
q <= 4'b1111;
else if (~g)
q <= d;
end
endmodule
//tstbh
module latch4b_tb();
reg g, pr;
reg [3:0] d;
reg [3:0] rndvar; // 4bits random variable
reg [2:0] dlay; // 3bits dlay
reg [1:0] dlay2; // 2bits dlay
wire[3:0] q;
integer i;

//instantiate design and connect design ports with TB signals

latch4b latch_tst(pr,g,d,q);
 // initializ stimulus
initial begin
$monitor("time=%02d pr=%01b g=%01b d=%04b q=%04b",
$time,pr,g,d,q);

d=0;g=0;pr=1;

#10 pr=0;
for (i=0;i<32;i=i+1)begin
rndvar=$random; // initializ 4 bits random
variable
dlay=$random;
dlay2=$random;
#(dlay) g<=~g;
#(dlay2) d<=rndvar; //d takes the random
variable
end
end
endmodule
b) Truth table
pre g d q
1 x x 1111
0 1 x q0
0 0 0000 0000
0 0 0001 0001
0 0 0010 0010
0 0 0011 0011
0 0 0100 0100
0 0 0101 0101
0 0 0110 0110
0 0 0111 0111
0 0 1000 1000
0 0 1001 1001
0 0 1010 1010
0 0 1011 1011
0 0 1100 1100
0 0 1101 1101
0 0 1110 1110
0 0 1111 1111
c) Simulation
7. Verilog code for a 4-bit unsigned down counter with synchronous set.
a) Testbench
//prob 7
module d_counter (clk, s, q);
input clk, s;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4'b1111;
else
tmp <= tmp - 1'b1;
end
assign q = tmp;
endmodule

//tstb
module main;
reg clk, s;
wire [0:3] q;
d_counter dctb(clk,s,q);
always #3 clk <= ~clk;
initial begin
clk=0; s=1;

$monitor("time=%02d clk=%01b s=%01b q=%04b",$time,

clk, s, q);
#9 s=0;
#100 $finish;
end
endmodule
b) Truth table
clk s tmp q
posedge 0 (before x x
s=1)
posedge 1 1111 1111
posedge 0 1111 1110
posedge 0 1110 1101
posedge 0 1101 1100
posedge 0 1100 1011
posedge 0 1011 1010
posedge 0 1010 1001
posedge 0 1001 1000
posedge 0 1000 0111
posedge 0 0111 0110
posedge 0 0110 0101
posedge 0 0101 0100
posedge 0 0100 0011
posedge 0 0011 0010
posedge 0 0010 0001
posedge 0 0001 0000
c) Simulation
8. Verilog code for a 4-bit unsigned up counter with an asynchronous
load from the primary input.
a) Testbench
// prob 8
module lcounter (clk, load, d, q);
input clk, load;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1'b1;
end
assign q = tmp;
endmodule

//tstbh
module lct_tb();
reg clk, load;
reg [3:0] d;
reg [3:0] dlay4b;
wire[3:0] q;
integer i;

//instantiate design and connect design ports with TB signals

lcounter lct_tst(clk, load, d, q);
 always #3 clk <= ~clk;

// initializ stimulus
initial begin //rndly set load aftr some dlay
for (i=0;i<5;i=i+1)begin
dlay4b=$random;
#(dlay4b) load<=1;
#1 load<=0;
end
end
initial begin
clk=0;
$monitor("time=%02d clk=%01b load=%01b d=%04b
q=%04b", $time,clk,load,d,q);
d<=4'b1010; //preset load with 1010
#150 $finish;
end

endmodule
b) Truth table
load clk d tmp q
1 x 1010 1010 1010
0 posedge 1010 1010 1011
0 posedge 1010 1011 1100
0 posedge 1010 1100 1101
0 posedge 1010 1101 1110
0 posedge 1010 1110 1111
0 posedge 1010 1111 0000
0 posedge 1010 0000 0001
0 posedge 1010 0001 0010
0 posedge 1010 0010 0011
0 posedge 1010 0011 0100
0 posedge 1010 0100 0101
0 posedge 1010 0101 0110
0 posedge 1010 0110 0111
0 posedge 1010 0111 1000
0 posedge 1010 1000 1001
0 posedge 1010 1001 1010
c) Simulation
9. Verilog code for a 4-bit unsigned up counter with an asynchronous
clear and a clock enable.
a) Testbench
//prob9
module ascounter (clk, clr, ce, q);
input clk, clr, ce;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4'b0000;
else if (ce)
tmp <= tmp + 1'b1;
end
assign q = tmp;
endmodule

//tstb

module ascounter_tb();
reg clk, clr, ce;
reg [3:0] dlay2b;
wire [3:0] q;
integer i;

ascounter ascounter_tst(clk, clr, ce, q);

always #3 clk <= ~clk;
initial begin
#1 ce=1;
 #1 clr=0;
#100 $finish;
end
initial begin
clk=0; clr=1;
$monitor("time=%02d clr=%01b clk=%01b ce=%01b
q=%04b",$time, clr, clk, ce, q);

for(i=0;i<31;i=i+1) begin //rndly toggl3 ce aft3r a while

dlay2b=$random;
#(dlay2b) ce<=~ce;
end
end
endmodule
b) Truth table
clr ce clk tmp q
1 x x 0000 0000
0 0 x q0 q0
0 1 posedge 0000 0001
0 1 posedge 0001 0010
0 1 posedge 0010 0011
0 1 posedge 0011 0100
0 1 posedge 0100 0101
0 1 posedge 0101 0110
0 1 posedge 0110 0111
0 1 posedge 0111 1000
0 1 posedge 1000 1001
0 1 posedge 1001 1010
0 1 posedge 1010 1011
0 1 posedge 1011 1100
0 1 posedge 1100 1101
0 1 posedge 1101 1110
0 1 posedge 1110 1111
c) Simulation
10. Verilog code for a 4-bit unsigned up/down counter with an
asynchronous clear.
a) Testbench
//prob 10
module udcounter (clk, clr, up_down, q);
input clk, clr, up_down;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4'b0000;
else if (up_down)
tmp <= tmp + 1'b1;
else
tmp <= tmp - 1'b1;
end
assign q = tmp;
endmodule

//tstb

module udcounter_tb();
reg clk, clr, up_down;
reg [3:0] dlay4b;
wire [3:0] q;
integer i;

udcounter udcounter_tst(clk, clr, up_down, q);

always #3 clk <= ~clk;
 initial begin
#1 up_down=1;
#1 clr=0;
#100 $finish;
end
initial begin
clk=0; clr=1;
$monitor("time=%02d clr=%01b clk=%01b up_down=%01b
q=%04b",$time, clr, clk, up_down, q);

for(i=0;i<31;i=i+1) begin //rndly toggl3 up_down aft3r a

while
dlay4b=$random;
#(dlay4b) up_down<=~up_down;
end
end
endmodule
b) Truth table
clr clk up_down temp q
1 x x 0000 0000
0 posedge 1 0000 0001
0 posedge 1 0001 0010
0 posedge 1 0010 0011
0 posedge 1 0011 0100
0 posedge 1 0100 0101
0 posedge 1 0101 0110
0 posedge 1 0110 0111
0 posedge 1 0111 1000
0 posedge 1 1000 1001
0 posedge 1 1001 1010
0 posedge 1 1010 1011
0 posedge 1 1011 1100
0 posedge 1 1100 1101
0 posedge 1 1101 1110
0 posedge 1 1110 1111
0 posedge 1 1111 0000
0 posedge 0 0000 1111
0 posedge 0 1111 1110
0 posedge 0 1110 1101
0 posedge 0 1101 1100
0 posedge 0 1100 1011
0 posedge 0 1011 1010
0 posedge 0 1010 1001
0 posedge 0 1001 1000
0 posedge 0 1000 0111
0 posedge 0 0111 0110
0 posedge 0 0110 0101
0 posedge 0 0101 0100
0 posedge 0 0100 0011
0 posedge 0 0011 0010
0 posedge 0 0010 0001
0 posedge 0 0001 0000
c) Simulation