DIGITAL SYSTEM DESIGN

Assignment - 1

Done by:Sabika Fatima

CMS:429648
Problem 1:
(a) Write a Verilog module for a half adder and implement a test bench
to verify the truth table.
module half_adder(
input A, B,
output Sum, Carry
);
assign Sum = A ^ B; // XOR for sum
assign Carry = A & B; // AND for carry
endmodule
module
tb_half_adder;
reg A, B;
wire Sum, Carry;

half_adder uut (
.A(A),
.B(B),
.Sum(Sum),
.Carry(Carry)
);

initial begin
$dumpfile("half_adder_tb.vcd");
$dumpvars(0, tb_half_adder);

// Test all input

combinations A = 0; B = 0;
#10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;

$display("Test Completed");
$finish;
end

endmodule

SIMULATION:
(b)Implement a 2-to-1 MUX using behavioral Verilog.

module mux_2to1(
input wire A, B,
input wire Sel,
output reg Y
);
always @(*) begin
if (Sel)
Y = B;
else
Y = A;
end
endmodule

module
tb_mux_2to1;
reg A, B,
Sel; wire Y;
mux_2to1 uut
(
.A(A),
.B(B),
.Sel(Sel),
.Y(Y)
 );

initial begin
$dumpfile("mux_2to1_tb.vcd");
$dumpvars(0,
tb_mux_2to1); A = 0; B =
0; Sel = 0; #10;
A = 0; B = 1; Sel = 0; #10;
A = 1; B = 0; Sel = 0; #10;
A = 1; B = 1; Sel = 0; #10;
A = 0; B = 0; Sel = 1; #10;
A = 0; B = 1; Sel = 1; #10;
A = 1; B = 0; Sel = 1; #10;
A = 1; B = 1; Sel = 1; #10;

$display("Test Completed");
$finish;
end

initial begin
$monitor("At time %0t: A = %b, B = %b, Sel = %b, Y =
%b", $time, A, B, Sel, Y);
end
endmodul
e
Problem 2:
(a) Write a 4-bit synchronous up counter with an enable signal.
Create Test bench for 16 cycles.

module counter_4bit(
input wire clk,
input wire rst,
input wire
enable,
output reg [3:0] count );
always @(posedge clk or posedge rst)
begin if (rst)
count <=
4'b0000; else if
(enable)
count <= count + 1;
end
endmodul
e
 module tb_counter_4bit;
reg clk, rst,
enable; wire [3:0]
count; counter_4bit
uut (
.clk(clk),
.rst(rst),
.enable(enable),
.count(count)
);
always #5 clk = ~clk;
initial begin
$dumpfile("counter_4bit_tb.vcd");
$dumpvars(0, tb_counter_4bit);
clk = 0; rst = 1; enable = 0; #10;
rst = 0; enable = 1;
#160;
$display("Test Completed");
$finish;
end
initial begin
$monitor("At time %0t: rst = %b, enable = %b, count
= %b", $time, rst, enable,
count); end
endmodule
(b) Implement an 8bit up/down counter.

module
up_down_counter( inpu
t clk,
input rst,
input load,
input
enable,
input
up_down,
input [7:0]
load_value, output
reg [7:0] count
);
always @(posedge clk or posedge rst)
begin if (rst)
count <= 8'b0;
else if (load)
count <= load_value;
else if (enable) begin
if (up_down)
count <= count +
1; else
count <= count - 1;
end
end
endmodule
module tb_up_down_counter;
reg clk, rst, load, enable,
up_down; reg [7:0] load_value;
wire [7:0] count;
up_down_counter uut (
.clk(clk),
.rst(rst),
.load(load),
.enable(enable),
.up_down(up_down),
.load_value(load_value),
.count(count)
);

always #5 clk = ~clk;

initial begin
clk = 0;
rst = 1;
load = 0;
enable = 0;
up_down = 1;
load_value =
8'b00000000; #10 rst =
0;
#10 load = 1; load_value =
8'b00001111; #10 load = 0;
#10 enable = 1; up_down = 1;
#100;
#10 up_down = 0;
#100;
#10 enable = 0;
#20;
$stop
; end
endmodule
Problem 3:
(a) Verilog code for a 4-bit shift register with a load input and
serial input for shifting, along with a testbench.

module shift_register (
input clk, // Clock
input input rst, //
Reset input input load,
// Load input
input w, // Serial input for
shifting input [3:0] load_value, //
Load value
output reg [3:0] q // 4-bit shift register output
);

always @(posedge clk or posedge rst)

begin if (rst)
q <= 4'b0000; // Reset to 0
else if (load)
 q <= load_value; // Load the value
els
e q <= {q[2:0], w}; // Shift left and insert new bit
end
endmodule

module tb_shift_register;
reg clk, rst, load,
w; reg [3:0]
load_value;
wire [3:0] q;
shift_register uut (
.clk(clk),
.rst(rst),
.load(load),
.w(w),
.load_value(load_value),
.q(q)
);

always #5 clk = ~clk;

initial begin
clk = 0;
rst = 1;
load = 0;
w = 0;
load_value = 4'b0000;
 #10 rst = 0;
#10 load = 1; load_value =
4'b1010; #10 load = 0;
#10 w = 1;
#10 w = 0;
#10 w = 1;
#10 w = 1;
#50;
$stop;
end
endmodule
Problem 3:
(a) Modify the 4-bit shift register to support N-bit shifting using
a parameterized design.

module shift_register_n #(parameter N = 4)(

input clk, reset, load, w,
input [N-1:0] load_value,
output reg [N-1:0] q
);

always @(posedge clk or posedge reset)

begin if (reset)
q <= {N{1'b0}};
else if (load)
q <= load_value;
else
q <= {q[N-2:0], w};
end
endmodul
e
 module tb_shift_register_n;
parameter N = 8;
reg clk, reset, load, w;
reg [N-1:0] load_value;
wire [N-1:0] q;

shift_register_n #(N) uut (.clk(clk), .reset(reset),

.load(load), .w(w), .load_value(load_value), .q(

q)); always #5 clk = ~clk;

initial begin
clk = 0; reset = 1; load = 0; w = 0; load_value =
8'b10101010; #10;
reset = 0; load = 1; #10;
load = 0;
w = 1; #10;
w = 0; #10;
w = 1; #10;
w = 1; #10;
$finish;
end
endmodule