FPGA Based Design EE-410T

Spring-2023
CLO1 CLO2 CLO3 Total

Comments:

Assignment No: 02 Date of Submission:

April-16-2023
Experiment Title:
Design of 128 KB RAM and FIFO module along with test
bench
Submitted By:
Ahmad Mukhtar
Batch: Teacher:
BSEE 20-24 Mr. Muhammad
Shahid Nazir
Semester Section:
6th Electronics

Department of Electrical
Engineering
Contents
1 Objectives: .................................................................................................................................... 3
2 Introduction: .................................................................................................................................. 3
3 Procedure ..................................................................................................................................... 3
4 Results: ......................................................................................................................................... 3
4.1 Main RAM module:................................................................................................................. 3
4.2 RAM Test bench .................................................................................................................... 4
4.3 Test bench of Ram modules using Tasks ............................................................................... 4
4.4 .................................................................................................................................................... 5
4.4.1 To make a text file that is filled with random data: ........................................................... 5
4.4.2 To make a text file that is filled with random data: ........................................................... 6
4.4.3 To write data in from the text file and update the write signal: ......................................... 6
4.4.4 To read data from the text file and update the read signal; .............................................. 6
4.4.5 To compare the two text files and see if they equal: ........................................................ 7
4.5 Console View: ........................................................................................................................ 7
4.6 Output 128 KB RAM: .............................................................................................................. 8
4.7 Write and Read Output files: .................................................................................................. 8
4.8 Compare data ........................................................................................................................ 8
4.9 Output files: ............................................................................................................................ 9
4.10 Discussion and Conclusion: ................................................................................................... 9
5 FIFO Module ............................................................................................................................... 10
5.1 Procedure: ........................................................................................................................... 10
5.2 Block Diagram: ..................................................................................................................... 10
5.3 Task No. 1............................................................................................................................ 11
5.3.1 (Main FIFO module) ...................................................................................................... 11
5.3.2 Testbench FIFO Module:............................................................................................... 11
5.3.3 Results .......................................................................................................................... 12
5.4 Task No.2 (Updated code using two Instances): .................................................................. 12
5.4.1 Block Diagram:.............................................................................................................. 12
5.4.2 Main FIFO Module: ....................................................................................................... 13
5.4.3 RAM Controller: ............................................................................................................ 13
5.4.4 General RAM Module: ................................................................................................... 14
5.4.5 Test bench FIFO Module:.............................................................................................. 14
5.4.6 Results: ......................................................................................................................... 15
5.4.7 Discussion and Conclusion: .......................................................................................... 15
6 References: ................................................................................................................................. 15
1 Objectives:
 To make 128 KB RAM module along with test bench
 To make 128 KB FIFO module

2 Introduction:
Random-access memory is a form of computer memory that can be read and changed in
any order, typically used to store working data and machine code. A random-access
memory device allows data items to be read or written in almost the same amount of time
irrespective of the physical location of data inside the memory.

FIFO is an approach for handling program work requests from queues or stacks so that
the oldest request is handled first. In hardware, it is either an array of flops or read/write
memory that stores data from one clock domain and on request supplies the same data
to other clock domains following FIFO logic

3 Procedure
 Assigned RAM: 128KB
 The memory was filled with write only commands and the data wrote was random.
 The read function was enabled, and the read function requested random addresses.
 Read and write data was dumped into output text files.
 Different task modules were used to implement the RAM testbench.

4 Results:
4.1 Main RAM module:
4.2 RAM Test bench

Simulation of ram module

In which first 50 address of memory first written then we read it

4.3 Test bench of Ram modules using Tasks

Tasks

4.4

4.4.1 To make a text file that is filled with random data:

4.4.2 To make a text file that is filled with random data:

4.4.3 To write data in from the text file and update the write signal:

4.4.4 To read data from the text file and update the read signal;
4.4.5 To compare the two text files and see if they equal:

4.5 Console View:

4.6 Output 128 KB RAM:

4.7 Write and Read Output files:

4.8 Compare data

4.9 Output files:

4.10 Discussion and Conclusion:

The RAM provided is 128 KB. The RAM module is identified and activated. Parameters are set
for specific RAM. Random data is stored in RAM and read when the read function is active. Read and
write data are stored in different output files respectively. The two sets of data are compared using the
compare function and the data is saved in an output file named compare_data.txt as described in the
results section. Various problem modules are used in the RAM section as described in Section 4.
Briefly, the data file is written to the specified RAM and the results confirm that 128 KB of RAM can
be used properly.
5 FIFO Module
5.1 Procedure:

FIFO is an approach for handling program work requests from queues or stacks so that
the oldest request is handled first. In hardware, it is either an array of flops or read/write
memory that stores data from one clock domain and on request supplies the same data
to other clock domains following FIFO logic. Hence, we first store some data into a text file.
We want that when we have a read signal the date input first comes out first.
 To achieve that, a RAM module was used that stores the data is written in the file.
 Read and write pointers were used that are basically the address of the read and write
location.
 Code writes into FIFO when it is empty and Write signal is enabled
 FIFO has some data and Read signal is enabled. If FIFO is full then we cannot write into it and
if FIFO is empty, we cannot read from it.
 A combinational logic is used to control the values from RAM. The read and write pointers are
fed as the addr_r and addr_w respectively.

5.2 Block Diagram:

Figure 1: Block Diagram for FIFO module

5.3 Task No. 1

5.3.1 (Main FIFO module)

5.3.2 Testbench FIFO Module:

5.3.3 Results

5.4 Task No.2 (Updated code using two Instances):

5.4.1 Block Diagram:

Figure 2: Block Diagram for FIFO module using RAM controller

5.4.2 Main FIFO Module:

5.4.3 RAM Controller:

5.4.4 General RAM Module:

5.4.5 Test bench FIFO Module:

5.4.6 Results:

Updated FIFO 128 KB output(RAM controller used)

Zoomed Version:

5.4.7 Discussion and Conclusion:

In the test bench, the data is written to the FIFO and not stored in RAM. Data is read from the FIFO
module using the point function. The FIFO generates a full_signal when data is written from the
waveform, and an empty_signal is generated when data is read.
An under_signal is generated when data is read from an empty FIFO, and an over_signal is
generated when the FIFO is fully written. All results have been verified and implemented successfully
and waveforms are attached in the results section for reference.

To complete the second task, the FIFO module is updated and the ram controller module is defined.
The ram manager and general ram module are called and the update FIFO is called in the update
FIFO top module. Waves for both FIFOs are given in the results of section 5.3.3 for a simple FIFO
using RAM and 5.4.6 for a FIFO using a RAM control module. In short, all the modules work and
the code is tested successfully.

6 References:
 [1]
“ModelSim ® Tutorial.” [Online]. Available: https://www.microsemi.com/document-
portal/doc_view/131618-modelsim-tutorial.

 [1]
“ISE In-Depth Tutorial,” 2011. [Online]. Available:
https://www.xilinx.com/htmldocs/xilinx13_3/ise_tutorial_ug695.pdf
 [1]
“ISE 10.1 Quick Start Tutorial.” Accessed: Apr. 20, 2022. [Online]. Available:
https://www.eng.auburn.edu/~strouce/class/elec4200/qst.pdf