TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

• High-Performance Operation: TIBPAL16L8’

C SUFFIX . . . J OR N PACKAGE
fmax (no feedback) M SUFFIX . . . J PACKAGE
TIBPAL16R’-7C Series . . . 100 MHz Min
(TOP VIEW)
TIBPAL16R’-10M Series . . . 62.5 MHz Min
fmax (internal feedback)
I 1 20 VCC
TIBPAL16R’-7C Series . . . 100 MHz Min
I 2 19 O
TIBPAL16R’-10M Series . . . 62.5 MHz Min
I 3 18 I/O
fmax (external feedback)
I 4 17 I/O
TIBPAL16R’-7C Series . . . 74 MHz Min
I 5 16 I/O
TIBPAL16R’-10M Series . . . 52.5 MHz Min
I 6 15 I/O
Propagation Delay
I 7 14 I/O
TIBPAL16L’-7C Series . . . 7 ns Max
I 8 13 I/O
TIBPAL16L’-10M Series . . . 10 ns Max
I 9 12 O
• Functionally Equivalent, but Faster than, GND 10 11 I
Existing 20-Pin PLDs
• Preload Capability on Output Registers TIBPAL16L8’
Simplifies Testing C SUFFIX . . . FN PACKAGE

• Power-Up Clear on Registered Devices (All

M SUFFIX . . . FK PACKAGE
(TOP VIEW)
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)

VCC
•

O
I
I
I
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic 3 2 1 20 19
I 4 18 I/O
and Ceramic DIPs
I 5 17 I/O
• Security Fuse Prevents Duplication I 6 16 I/O

• Dependable Texas Instruments Quality and

I 7 15 I/O
I/O
I 8 14
Reliability 9 10 11 12 13
I/O
I

I/O
O
GND
I 3-STATE REGISTERED
DEVICE PORT
INPUTS O OUTPUTS Q OUTPUTS
S
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
Pin assignments in operating mode
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0

description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.

PRODUCTION DATA information is current as of publication date. Copyright  1992, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

TIBPAL16R4’ TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE C SUFFIX . . . FN PACKAGE
M SUFFIX . . . J PACKAGE M SUFFIX . . . FK PACKAGE

(TOP VIEW) (TOP VIEW)

VCC
CLK

I/O
CLK 1 20 VCC

I
I
I 2 19 I/O
I 3 18 I/O 3 2 1 20 19
I 4 18 I/O
I 4 17 Q I Q
5 17
I 5 16 Q I Q
6 16
I 6 15 Q I Q
7 15
I 7 14 Q Q
I 8 14
I 8 13 I/O 9 10 11 12 13
I 9 12 I/O

OE
I

I/O
I/O
GND
GND 10 11 OE

TIBPAL16R6’ TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE C SUFFIX . . . FN PACKAGE
M SUFFIX . . . J PACKAGE M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)

VCC
CLK

I/O
CLK 1 20 VCC

I
I
I 2 19 I/O
I 3 2 1 20 19
3 18 Q I 4 18 Q
I 4 17 Q I 5 17 Q
I 5 16 Q I 6 16 Q
I 6 15 Q I 7 15 Q
I 7 14 Q I 8 14 Q
I 8 13 Q 9 10 11 12 13
I 9 12 I/O
OE
I

I/O
Q
GND

GND 10 11 OE

TIBPAL16R8’ TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE C SUFFIX . . . FN PACKAGE
M SUFFIX . . . J PACKAGE M SUFFIX . . . FK PACKAGE
(TOP VIEW) (TOP VIEW)
VCC
CLK

CLK 1 20 VCC
Q
I
I

I 2 19 Q
I 3 18 Q 3 2 1 20 19
I 4 18 Q
I 4 17 Q I Q
5 17
I 5 16 Q Q
I 6 16
I 6 15 Q I 7 15 Q
I 7 14 Q I 8 14 Q
I 8 13 Q 9 10 11 12 13
I 9 12 Q
OE
I

Q
Q
GND

GND 10 11 OE

Pin assignments in operating mode

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C, TIBPAL16R4-7C
TIBPAL16L8-10M, TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

functional block diagrams (positive logic)

TIBPAL16L8’

& EN ≥ 1
32 X 64 7 O

7 O

16 x 7 I/O
10 16
I
7 I/O

6 16 7 I/O

7 I/O

7 I/O

7 I/O

TIBPAL16R4’

OE EN 2
CLK C1

& 8 ≥1 I=0 2 Q
32 X 64 1D
8 Q

8 Q
16 x
8 16
I Q
8
4
EN ≥ 1
4 16 7 I/O

7 I/O

7 I/O

7 I/O

4
4

denotes fused inputs

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

functional block diagrams (positive logic)

TIBPAL16R6’

OE EN 2
CLK C1

& 8 ≥1 I=0 2 Q
32 X 64 1D
8 Q

8 Q
16 x
8 16
I Q
8
6
8 Q
2 16
8 Q

EN ≥ 1
7 I/O

7 I/O

2
6

TIBPAL16R8’

OE EN 2
CLK C1

& 8 ≥1 I=0 2 Q
32 X 64 1D
8 Q

8 Q
16 x
8 16
I Q
8

8 Q
8 16
8 Q

8 Q

8 Q

8
denotes fused inputs

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C
TIBPAL16L8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

logic diagram (positive logic)

1
I
Increment
First
Fuse
Numbers 0 4 8 12 16 20 24 28 31
0
32
64
96 19
128 O
160
192
224
2
I
256
288
320
352 18
384 I/O
416
448
480
3
I
512
544
576
608 17
640 I/O
672
704
736
4
I
768
800
832
864 16
896 I/O
928
960
992
5
I
1024
1056
1088
1120 15
1152 I/O
1184
1216
1248
6
I
1280
1312
1344
1376 14
1408 I/O
1440
1472
1504
7
I
1536
1568
1600
1632 13
1664 I/O
1696
1728
1760
8
I
1792
1824
1856
1888 12
1920 O
1952
1984
2016
9 11
I I

Fuse number = First fuse number + Increment

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TIBPAL16R4-7C
TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

logic diagram (positive logic)

1
CLK
Increment
First
Fuse
Numbers 0 4 8 12 16 20 24 28 31
0
32
64
96 19
128 I/O
160
192
224
2
I
256
288
320
352 18
384 I/O
416
448
480
3
I
512
544
576
608
I=0 17
640 1D Q
672
704
736 C1
4
I
768
800
832
864
I=0 16
896 1D Q
928
960
992 C1
5
I
1024
1056
1088
1120
I=0 15
1152 1D Q
1184
1216
1248 C1
6
I
1280
1312
1344
1376
I=0 14
1408 1D Q
1440
1472
1504 C1
7
I
1536
1568
1600
1632 13
1664 I/O
1696
1728
1760
8
I
1792
1824
1856
1888 12
1920 I/O
1952
1984
2016
9
I 11
OE
Fuse number = First fuse number + Increment

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16R6-7C
TIBPAL16R6-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

logic diagram (positive logic)

1
CLK
Increment
First
Fuse
Numbers 0 4 8 12 16 20 24 28 31
0
32
64
96 19
128 I/O
160
192
224
2
I
256
288
320
352
I=0 18
384 1D Q
416
448
480 C1
3
I
512
544
576
608
I=0 17
640 1D Q
672
704
736 C1
4
I
768
800
832
864
I=0 16
896 1D Q
928
960
992 C1
5
I
1024
1056
1088
1120
I=0 15
1152 1D Q
1184
1216
1248 C1
6
I
1280
1312
1344
1376
I=0 14
1408 1D Q
1440
1472
1504 C1
7
I
1536
1568
1600
1632
I=0 13
1664 1D Q
1696
1728
1760 C1
8
I
1792
1824
1856
1888 12
1920 I/O
1952
1984
2016
9
I 11
OE
Fuse number = First fuse number + Increment

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TIBPAL16R8-7C
TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

logic diagram (positive logic)

1
CLK
Increment
First
Fuse
Numbers 0 4 8 12 16 20 24 28 31
0
32
64
96
I=0 19
128 1D Q
160
192
224 C1
2
I
256
288
320
352
I=0 18
384 1D Q
416
448
480 C1
3
I
512
544
576
608
I=0 17
640 1D Q
672
704
736 C1
4
I
768
800
832
864
I=0 16
896 1D Q
928
960
992 C1
5
I
1024
1056
1088
1120
I=0 15
1152 1D Q
1184
1216
1248 C1
6
I
1280
1312
1344
1376
I=0 14
1408 1D Q
1440
1472
1504 C1
7
I
1536
1568
1600
1632
I=0 13
1664 1D Q
1696
1728
1760 C1
8
I
1792
1824
1856
1888
I=0 12
1920 1D Q
1952
1984
2016 C1
9
I 11
OE
Fuse number = First fuse number + Increment

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current – 3.2 mA
IOL Low-level output current 24 mA
fclock Clock frequency 0 100 MHz
High 5
tw Pulse duration, clock (see Note 2) ns
Low 5
tsu Setup time, input or feedback before clock↑ 7 ns
th Hold time, input or feedback after clock↑ 0 ns
TA Operating free-air temperature 0 25 75 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK VCC = 4.75 V, II = – 18 mA –0.8 – 1.5 V
VOH VCC = 4.75 V, IOH = – 3.2 mA 2.4 3.2 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
IOZH‡ VCC = 5.25 V, VO = 2.7 V 100 µA
IOZL‡ VCC = 5.25 V, VO = 0.4 V –100 µA
II VCC = 5.25 V, VI = 5.5 V 100 µA
IIH‡ VCC = 5.25 V, VI = 2.7 V 25 µA
IIL‡ VCC = 5.25 V, VI = 0.4 V –80 –250 µA
IOS§ VCC = 5.25 V, VO = 0.5 V – 30 –70 –130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 160 180 mA
Ci f = 1 MHz, VI = 2 V 5 pF
Co f = 1 MHz, VO = 2 V 6 pF
Cclk f = 1 MHz, VCLK = 2 V 6 pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITION MIN TYP† MAX UNIT
(INPUT) (OUTPUT)
without feedback 100
with internal feedback
fmax‡ 100 MHz
(counter configuration)
with external feedback 74
1 or 2 outputs switching 3 5.5 7
tpd I, I/O O, I/O ns
8 outputs switching R1 = 200 Ω, 3 6 7.5
tpd CLK↑ Q R2 = 390 Ω, 2 4 6.5 ns
tpd§ CLK↑ Feedback input See Figure 6 3 ns
ten OE↓ Q 4 7.5 ns
tdis OE↑ Q 4 7.5 ns
ten I, I/O O, I/O 6 9 ns
tdis I, I/O O, I/O 6 9 ns
tsk(o)¶ Skew between registered outputs 0.5 ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ See section for fmax specifications.
§ This parameter applies to TIBPAL16R4’ and TIBPAL16R6’ only (see Figure 4 for illustration) and is calculated from the measured fmax with internal
feedback in the counter configuration.
¶ This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs
are switching in the same direction.

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –2 mA
IOL Low-level output current 12 mA
fclock† Clock frequency 0 62.5 MHz
High 8
tw Pulse duration, clock (see Note 2) ns
Low 8
tsu† Setup time, input or feedback before clock↑ 10 ns
th† Hold time, input or feedback after clock↑ 0 ns
TA Operating free-air temperature –55 25 125 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK VCC = 4.5 V, II = – 18 mA –0.8 – 1.5 V
VOH VCC = 4.5 V, IOH = – 2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V
IOZH‡ VCC = 5.5 V, VO = 2.7 V 100 µA
0, Q outputs – 0.1
IOZL‡ VCC = 5.5 V, VO = 0.4 V mA
I/O ports – 0.25
II VCC = 5.5 V, VI = 5.5 V 1 mA
I/O ports 100
IIH All others
VCC = 5.5 V, VI = 2.7 V 25 µA

IIL‡ VCC = 5.5 V, VI = 0.4 V – 0.08 – 0.25 mA

IOS§ VCC = 5.5 V, VO = 0.5 V – 30 –70 – 130 mA
ICC VCC = 5.5 V, VI = GND, Outputs open 140 200 mA
Ci f = 1 MHz, VI = 2 V 5 pF
Co f = 1 MHz, VO = 2 V 6 pF
Cclk/oe f = 1 MHz, VCLK/OE = 2 V 6 pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006C – D3115, MAY 1988 – REVISED OCTOBER 1990

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITION MIN TYP† MAX UNIT
(INPUT) (OUTPUT)
without feedback 62.5
with internal feedback
fmax‡ 62.5 MHz
(counter configuration)
with external feedback 52.5
tpd I, I/O O, I/O R1 = 390 Ω, 2 6 10 ns
tpd CLK↑ Q R2 = 750 Ω, 1 4 9 ns
tpd§ CLK↑ Feedback input See Figure 6 5 ns
ten OE↓ Q 1 4 10 ns
tdis OE↑ Q 1 4 10 ns
ten I, I/O O, I/O 2 6 12 ns
tdis I, I/O O, I/O 1 6 10 ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ See section for fmax specifications. fmax with external feedback is not production tested but is calculated from the equation found in the fmax
section.
§ This parameter applies to TIBPAL16R4’ and TIBPAL16R6’ only (see Figure 4 for illustration) and is calculated from the measured fmax with internal
feedback in the counter configuration.

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.

preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
VIHH
Pin 11
VIL
tsu td
td tw
VIH
Pin 1
VIL

VIH VOH
Registered I/O Input Output
VIL VOL

Figure 1. Preload Waveforms

NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

power-up reset (see Figure 2)

Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
VCC 4V 5V

tpd†
(600 ns TYP, 1000 ns MAX)
VOH
Active Low
Registered Output 1.5 V
VOL

tsu‡
VIH
CLK 1.5 V 1.5 V
VIL
tw

† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡ This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

fmax SPECIFICATIONS

fmax without feedback, see Figure 3

In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th).
However, the minimum fmax is determined by the minimum clock period (tw high + tw low).
Thus, f max without feedback + (t whigh
1
) t wlow)
or (t
su
1
)
t ).
h
CLK

LOGIC C1
ARRAY

1D

tsu + th
or
tw high + tw low

Figure 3. fmax Without Feedback

fmax with internal feedback, see Figure 4

This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, f max with internal feedback + (t su )t
1
CLK to FB) . * *
pd

Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK

LOGIC C1
ARRAY

1D

tsu tpd CLK - to - FB

Figure 4. fmax With Internal Feedback

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

fmax SPECIFICATIONS

fmax with external feedback, see Figure 5

This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(tsu + tpd CLK-to-Q).
Thus, f max with external feedback +
(t su t )
1
CLK to Q). * *
pd
CLK

LOGIC C1 NEXT DEVICE

ARRAY

1D

tsu tpd CLK - to - Q tsu

Figure 5. fmax With External Feedback

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

PARAMETER MEASUREMENT INFORMATION

5V

S1
R1
From Output Test
Under Test Point

CL R2
(see Note A)

LOAD CIRCUIT FOR

3-STATE OUTPUTS

(3.5 V) [3 V]
(3.5 V) [3 V] High-Level
Timing Pulse 1.5 V 1.5 V
Input 1.5 V (0.3 V) [0]
(0.3 V) [0] tw
tsu th
(3.5 V) [3 V] (3.5 V) [3 V]
Data Low-Level
Input 1.5 V 1.5 V 1.5 V 1.5 V
Pulse
(0.3 V) [0] (0.3 V) [0]

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS
(3.5 V) [3 V]
Output
(3.5 V) [3 V] Control 1.5 V 1.5 V
Input 1.5 V 1.5 V (low-level
enabling) (0.3 V) [0]
(0.3 V) [0]
ten
tpd tpd tdis
In-Phase VOH
≈ 3.3 V
Output 1.5 V 1.5 V Waveform 1 1.5 V VOL +0.5 V
VOL S1 Closed
tpd (see Note B) VOL
tpd tdis
VOH ten
Out-of-Phase
1.5 V 1.5 V Waveform 2 VOH
Output
(see Note D) VOL S1 Open
(see Note B) 1.5 V VOH –0.5 V

VOLTAGE WAVEFORMS ≈0V

PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ), PRR ≤ 1 MHz,
tr = tf = 2 ns, duty cycle = 50%; For M suffix, use the voltage levels indicated in brackets [ ], PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty
cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.

Figure 6. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

TYPICAL CHARACTERISTICS
SUPPLY CURRENT PROPAGATION DELAY TIME
vs vs
FREE - AIR TEMPERATURE SUPPLY VOLTAGE
220 8

7
200

Propagation Delay Time – ns

6
I CC – Supply Current – mA

tPHL (I, I/O to O, I/O)

180
5
tPLH (I, I/O to O, I/O)

160 4 tPHL (CLK to Q)

3
140 tPLH (CLK to Q)

2 TA = 25 ° C
CL = 50 pF
120 R1 = 200 Ω
1 R2 = 390 Ω
1 Output Switching
100 0
–75 –50 –25 0 25 50 75 100 125 4.5 4.75 5 5.25 5.5
TA – Free - Air Temperature – ° C VCC – Supply Voltage – V

Figure 7 Figure 8

PROPAGATION DELAY TIME PROPAGATION DELAY TIME

vs vs
FREE - AIR TEMPERATURE LOAD CAPACITANCE
8 16
VCC = 5 V
TA = 25 ° C
7 14 R1 = 200 Ω
tPHL (I, I/O to O, I/O) R2 = 390 Ω
Propagation Delay Time – ns

Propagation Delay Time – ns

6 12 1 Output Switching

5 tPLH (I, I/O to O, I/O) 10

4 tPHL (CLK to Q) 8
tPLH (CLK to Q)
3 6 tPHL (CLK to Q)
tPLH (CLK to Q)
tPHL (I, I/O to O, I/O)
2 VCC = 5 V 4
CL = 50 pF tPLH (I, I/O to O, I/O)
R1 = 200 Ω
1 R2 = 390 Ω 2
1 Output Switching
0 0
–75 –50 –25 0 25 50 75 100 125 0 100 200 300 400 500 600
TA – Free - Air Temperature – ° C CL – Load Capacitance – pF

Figure 9 Figure 10

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs PROPAGATION DELAY TIME†
FREQUENCY vs
8 - BIT COUNTER MODE NUMBER OF OUTPUTS SWITCHING
1000 0.8

– Skew Between Outputs Switching – ns

VCC = 5 V VCC = 5 V
TA = 25 ° C
0.7 R1 = 200 Ω
R2 = 390 Ω
P – Power Dissipation – mW

900 0.6 CL = 50 pF
TA = 0 ° C 8-Bit Counter

0.5

TA = 25 ° C
800 0.4
TA = 80 ° C
0.3

700 0.2
D

t skew
0.1

600 0
1 4 10 40 100 2 3 4 5 6 7 8
F – Frequency – MHz Number of Outputs Switching

Figure 11 Figure 12

PROPAGATION DELAY TIME

vs
NUMBER OF OUTPUTS SWITCHING
8

7
tPHL (I, I/O to O, I/O)
Propagation Delay Time – ns

5 tPLH (I, I/O to O, I/O)

4 tPHL (CLK to Q)

3 tPLH (CLK to Q)

2 VCC = 5 V
TA = 25 ° C
1 CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
0
0 1 2 3 4 5 6 7 8
Number of Outputs Switching

Figure 13
†Outputs switching in the same direction (t
PLH compared to tPLH/tPHL to tPHL)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

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D0892
1992 Texas Instruments Incorporated

Printed in U.S.A. SRPS006D

 PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2005

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
5962-85155172A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515517RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515517SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC
5962-85155182A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515518RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515518SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC
5962-85155192A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515519RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515519SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC
5962-85155202A LIFEBUY LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515520RA LIFEBUY CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515520SA LIFEBUY CFP W 20 1 None Call TI Level-NC-NC-NC
TIBPAL16L8-10MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
TIBPAL16L8-10MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
TIBPAL16L8-10MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC
TIBPAL16L8-7CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM
TIBPAL16L8-7CN ACTIVE PDIP N 20 20 None Call TI Level-NC-NC-NC
TIBPAL16R4-10MFKB LIFEBUY LCCC FK 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R4-10MJB LIFEBUY CDIP J 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R4-10MWB LIFEBUY CFP W 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R4-7CFN OBSOLETE PLCC FN 20 None Call TI Call TI
TIBPAL16R4-7CN OBSOLETE PDIP N 20 None Call TI Call TI
TIBPAL16R6-10MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R6-10MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R6-10MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R6-7CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM
TIBPAL16R6-7CN NRND PDIP N 20 20 None Call TI Level-NC-NC-NC
TIBPAL16R8-10MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R8-10MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R8-10MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC
TIBPAL16R8-7CFN OBSOLETE PLCC FN 20 None Call TI Call TI
TIBPAL16R8-7CN OBSOLETE PDIP N 20 None Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2005

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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information may not be available for release.

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to Customer on an annual basis.

Addendum-Page 2
 IMPORTANT NOTICE

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Products Applications
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DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
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