Template For Lab 3 SoC

This laboratory work report summarizes two projects completed using an online cloud service: 1) A D-flip-flop circuit was designed and tested with input test vectors. 2) A mod-M counter was designed to count from 0 to M-1 with a configurable M value and number of bits N. Both circuits were simulated and waveforms were produced.

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Template For Lab 3 SoC

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TOSONAMi

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Kharkov National University of Radioelectronics

Centre for Education in English

Course: “System-on-chip”

Laboratory Work
Report #3

Student: Teacher:
Gr. КІУКІі-16-3 Prof. Eugenia Litvinova
Name

Kharkov 2020
Task of the Lab#3:
Using cloud service http://www.edaplayground.com create the following
projects.
You can login this service using Facebook or Google account.

Example 1. D-flip-flop
Use the following test data:
d <="1011";
d <="1101";
d <="1001";

-- Testbench automatically generated online library IEEE;

-- at https://vhdl.lapinoo.net use IEEE.STD_LOGIC_1164.all;
-- Generation date : 25.9.2020 19:25:04 UTC
entity flop is
library ieee; port (clk: in STD_LOGIC;
use ieee.std_logic_1164.all; d: in STD_LOGIC_VECTOR (3 downto 0) ;
q: out STD_LOGIC_VECTOR (3 downto 0)) ;
entity tb_flop is end;
end tb_flop;
architecture synth of flop is
architecture tb of tb_flop is begin
process (clk) begin
component flop if clk'event and clk ='1' then
port (clk : in std_logic; q <= d;
d : in std_logic_vector (3 downto 0); end if;
q : out std_logic_vector (3 downto 0)); end process;
end component; end;

signal clk : std_logic;

signal d : std_logic_vector (3 downto 0);
signal q : std_logic_vector (3 downto 0);

constant TbPeriod : time := 100 ns; -- EDIT

Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';

begin

dut : flop
port map (clk => clk,
d => d,
q => q);

-- Clock generation
TbClock <= not TbClock after TbPeriod/2
when TbSimEnded /= '1' else '0';

clk <= TbClock;

stimuli : process
begin
d <= (others => '0');
wait for 10 * TbPeriod;
d <="1010";
wait for 10 * TbPeriod;
d <="1111";
wait for 10 * TbPeriod;

-- Stop the clock and hence terminate the

simulation
TbSimEnded <= '1';
wait;
end process;

end tb;

Add Results and waveform.

Example 2. mod-M counter

Use the following test data:
M = 8;
N = 4;

-- modMCounter_tb.vhd -- modMCounter.vhd

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

entity modMCounter_tb is entity modMCounter is

end modMCounter_tb; generic (
M : integer := 5; -- count from 0 to M-1
architecture arch of modMCounter_tb is N : integer := 3 -- N bits required to
constant M : integer := 10; count upto M i.e. 2**N >= M
constant N : integer := 4; );
constant T : time := 20 ns;
port(
signal clk, reset : std_logic; -- input clk, reset : in std_logic;
signal complete_tick : std_logic; -- output complete_tick : out std_logic;
signal count : std_logic_vector(N-1 downto 0); count : out std_logic_vector(N-1 downto
-- output 0)
begin );
end modMCounter;
modMCounter_unit : entity
work.modMCounter architecture arch of modMCounter is
generic map (M => M, N => N) signal count_reg, count_next : unsigned(N-1
port map (clk=>clk, reset=>reset, downto 0);
complete_tick=>complete_tick, begin
count=>count); process(clk, reset)
begin
if reset = '1' then
-- continuous clock count_reg <= (others=>'0');
process elsif clk'event and clk='1' then
begin count_reg <= count_next;
clk <= '0'; else -- note that else block is not required
wait for T/2; count_reg <= count_reg;
clk <= '1';
wait for T/2; end if;
end process;
clk <= '0';
wait for T/2; -- set count_next to 0 when maximum count
clk <= '1'; is reached i.e. (M-1)
wait for T/2; -- otherwise increase the count
count_next <= (others=>'0') when
clk <= '0'; count_reg=(M-1) else (count_reg+1);
wait for T/2;
clk <= '1'; -- Generate 'tick' on each maximum count
wait for T/2; complete_tick <= '1' when count_reg = (M-1)
else '0';
clk <= '0';
wait for T/2; count <= std_logic_vector(count_reg); --
clk <= '1'; assign value to output port
wait for T/2; end arch;