DEPARTMENT OF BIOMEDICAL ENGINEERING Experiment No.

3
Semester B.E. Semester VII– Biomedical Engineering
Subject Basics of VLSI
Subject Professor In- Prof. Geetha Narayanan
charge
Laboratory VLSI Laboratory (Online)
Student Name Apurva Malkari
Roll Number 22105A0015
Grade and Subject
Teacher’s Signature

Experiment Design of asynchronous circuits in VHDL and compare with synchronous circuit design
Problem Design a blood cell counter using VHDL
statement
Resources Hardware: Software: Xilinx ISE 9.2i/14.7
/ IBM PC Compatible Computer System
Apparatus
Required
Objectives Basic idea of VHDL and coding for sequential circuits. Design for various circuits
(Skill Set / Design for asynchronous circuits using structural design
Knowledge
Tested /
Imparted)
About different sequential circuits in VHDL
Theory of
Operation
Procedure Students need to study the interface between the image processing and VHDL Code.
Students will write program synchronous circuit like Counter/Shift registers. Design asynchronous
circuit using Flip Flop

Program Counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity counter is
Port ( clk,rst : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
signal temp:STD_LOGIC_vector(3 downto 0);
begin
Process (clk,rst)
begin
if rst='0' then temp<="0000";
elsif(clk'event and clk='0') then
temp<= temp+'1';
end if;
end process;
q<=temp;
end Behavioral;

Test Bench
-- Code your testbench here
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT counter
PORT(
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);
-- Clock period definitions
 constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: counter PORT MAP (
clk => clk,
rst => rst,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 1 ns;
wait for clk_period*2;
rst<='0';
wait for 1 ns;
rst<='1';
wait for 10 ns;

wait;
end process;
END;
https://www.edaplayground.com/x/HCFz

TFF
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF is
 Port ( pr,clr,clk,T : in STD_LOGIC;
Q : out STD_LOGIC);
end TFF;
architecture Behavioral of TFF is
signal temp:std_logic;
begin
process (clk)
begin
if (clk'event and clk='0') then
if pr='0' then temp<='1';
elsif clr='0' then temp<='0';
elsif T='0' then temp<=temp;
else temp<= not temp;
end if;
end if;
end process;
Q<=temp;
end Behavioral;
Test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TFFTB IS
END TFFTB;
ARCHITECTURE behavior OF TFFTB IS

COMPONENT TFF
PORT(
pr : IN std_logic;
clr : IN std_logic;
clk : IN std_logic;
T : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;

--Inputs
signal pr : std_logic := '0';
signal clr : std_logic := '0';
signal clk : std_logic := '0';
signal T : std_logic := '0';
--Outputs
 signal Q : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TFF PORT MAP (
pr => pr,
clr => clr,
clk => clk,
T => T,
Q => Q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period;
clk <= '1';
wait for clk_period;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 1ns;
wait for clk_period*1;
pr<='0'; wait for 5 ns;
clr<='0'; wait for 5 ns;
pr<='1'; wait for 5 ns;
clr<='1'; wait for 5 ns;
T<='0'; wait for 5 ns;
T<='1'; wait for 10 ns;
clr<='0'; wait for 5 ns;
clr<='1'; wait for 5 ns;
T<='1'; wait for 10 ns;
wait;
end process;
END;
https://www.edaplayground.com/x/Jpb9
JK FF
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JKFF is
Port ( clk,clr,pr,J,K : in STD_LOGIC;
Q : out STD_LOGIC);
end JKFF;
architecture Behavioral of JKFF is
signal temp:STD_LOGIC;
begin
process(clk,clr,pr,J,K)
begin
if (pr='0')then temp<='1';
elsif (clr='0')then temp<='0';
elsif(clk'event and clk='1') then
if (J='0' and K='0') then temp<=temp;
elsif (J='0' and K='1') then temp<='0';
elsif (J='1' and K='0') then temp<='1';
else temp<= not temp;
end if;
end if;
end process;
Q<=temp;
end Behavioral;
Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY JKFFTB IS
END JKFFTB;
ARCHITECTURE behavior OF JKFFTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT JKFF
PORT(
clk : IN std_logic;
clr : IN std_logic;
pr : IN std_logic;
J : IN std_logic;
K : IN std_logic;
Q : OUT std_logic
 );
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal clr : std_logic := '0';
signal pr : std_logic := '0';
signal J : std_logic := '0';
signal K : std_logic := '0';
--Outputs
signal Q : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: JKFF PORT MAP (
clk => clk,
clr => clr,
pr => pr,
J => J,
K => K,
Q => Q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period;
clk <= '1';
wait for clk_period;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 1 ns;
wait for clk_period*1;
pr<='0';
wait for 5 ns;
 clr<='0';
wait for 5 ns;
pr<='1';
wait for 5 ns;
clr<='1';
wait for 5 ns;
J<='0';
wait for 5 ns;
K<='0';
wait for 5 ns;
J<='0';
wait for 5 ns;
K<='1';
wait for 5 ns;
J<='1';
wait for 5 ns;
K<='0';
wait for 5 ns;
J<='1';
wait for 5 ns;
K<='1';
wait for 5 ns;
clr<='0';
wait for 5 ns;
clr<='1';
wait for 5 ns;
J<='1';
wait for 5 ns;
K<='1';
wait for 5 ns;
wait;
end process;
END;
https://www.edaplayground.com/x/c3S4

Results
Counter

TFF
 JK FF

Reflections Designing an asynchronous circuit in VHDL requires careful attention to metastability, timing
analysis, hazards, and modularity, with extensive simulation and testing to ensure reliable
operation. For a blood cell counter, key considerations include accuracy in distinguishing cell
types, processing speed, regular calibration, an intuitive user interface, hygiene and safety for
handling biological samples, and efficient data handling for storing and integrating results.