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Switchinng Theory and Logic Design Feb 2022

This document contains 10 questions related to switching theory and logic design for a exam. The questions cover topics like: 1) Generating a Hamming code and performing BCD subtraction 2) Simplifying Boolean expressions and implementing with NAND gates 3) Minimizing Boolean expressions using Quine-McCluskey method and discussing K-maps 4) Designing BCD to excess-3 code converters and full adders 5) Realizing Boolean functions using multiplexers and designing octal to binary encoders 6) Designing BCD to excess-3 code converters using PAL and comparing PLDs 7) Explaining the operation of parallel-in parallel-out shift registers

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62 views2 pages

Switchinng Theory and Logic Design Feb 2022

This document contains 10 questions related to switching theory and logic design for a exam. The questions cover topics like: 1) Generating a Hamming code and performing BCD subtraction 2) Simplifying Boolean expressions and implementing with NAND gates 3) Minimizing Boolean expressions using Quine-McCluskey method and discussing K-maps 4) Designing BCD to excess-3 code converters and full adders 5) Realizing Boolean functions using multiplexers and designing octal to binary encoders 6) Designing BCD to excess-3 code converters using PAL and comparing PLDs 7) Explaining the operation of parallel-in parallel-out shift registers

Uploaded by

panda pavan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Code No: R2021042 R20 SET - 1

II B. Tech I Semester Regular Examinations, Feb/March - 2022


SWITCHINNG THEORY AND LOGIC DESIGN
(Com to ECE, EIE, ECT)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions each Question from each unit
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~~

1 a) Given the 8-bit data word 01011011, generate the 12 bit composite word for the [6M]
Hamming code that corrects and detects single errors.
b) Carry out BCD subtraction for (57) – (50) using 10’s complement method. [4M]
c) Express the decimal 324 in Gray code form. [4M]

Or
2 a) Simplify the following expression Y=(A+B)(A+C')(B'+C') and implement using [6M]
NAND gates.
b) Draw the pin diagram and obtain truth table for the following: [8M]
(i) IC 7400
(ii) IC 7408
3 a) Minimize the expression using Quine-McCluskey method [10M]
Y = ̅ B C D + ̅ B ̅ D + A B ̅ 
 + A B ̅ D + A  ̅ D + ̅  C 
b) What are the advantages and disadvantages of K-maps? [4M]

Or
4 a) Design and implement BCD to Excess-3 code converter. [10M]
b) Draw and explain the operation of a full adder circuit using two half adder [4M]
circuits.

5 a) Using 8:1 multiplexer realize the Boolean function: [7M]


T= f(w,x,y,z)= Ʃ(0,1,2,4,5,7,8,9,12,13)
b) Design an octal to binary encoder. [7M]

Or
6 a) Design a BCD to excess-3 code converter using PAL. [10M]
b) Compare the three combinational PLDs – PROM, PLA and PAL. [4M]

7 a) Draw the logic diagram of a parallel-in, Parallel-out shift register and explain its [6M]
operation.
b) Explain the working of a master-slave JK flip flop and state its advantages. [8M]

Or
8 a) Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D [8M]
flip-flops.
b) Write short notes on the following: [6M]
(i) IC 7474
(ii) IC 7493
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Code No: R2021042 R20 SET - 1

9 a) Explain the capabilities and limitations of finite state machines. [6M]


b) Explain about state diagrams & state tables. [8M]

Or
10 a) Convert the following Mealy machine into equivalent Moore machine. Draw the [12M]
state transition diagrams for both.
N.S
P.S A B
state o/p state o/p
Q1 Q1 1 Q2 0
Q2 Q4 1 Q4 1
Q3 Q2 1 Q3 1
Q4 Q3 0 Q1 1
b) When are two states said to be equivalent states? [2M]

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