Scribd
Upload
17 views6 pages

DCS Questions

Uploaded by

ayush.jaiswal382004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
17 views6 pages

DCS Questions

Uploaded by

ayush.jaiswal382004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

END TERM DXAMINATION

THIRD SEMESTER Exam Roll Na.


Paper Code: ECC-207 |B.TCH) Dat
Subject: Dit Logic &s
7S
Time: 3 Hours
Note: Attept fie questions in all
DEeCEMBER-
esign 2024 Computer
Maxtmum Mark: 60
including
compulsory. Select one question from
Q.
no.1 which in
each Anit.
Q1 Attempt all Questions
(a) Convert (1111000100)2 to gray, XS-3 and BCD. (4)
(b) Implement half adder using NAND gate only. (4)
(c) What is race around condition in flip-flops? How can it is
overcome?
(4]
(d Differentiate bctween Ring and Johnson counter. (3
(c) What is an Input-Output processor (1OP), and how does it
contribute to the efficiency of I/O operations? (3)
(0 Differentiate between RISC and CISC. (2
UNIT-I

Q2 (a) Simplify the following b0olean function using Quine


MeCluskey Method. (6)
SA,B,C,D)- Dm (1, 2, 4, 5, 7, 8, 10, 11, 12, 14).
Find a minimal SOP using K-Map and draw the circuit of
(b) (4)
minimal cxpression.
f{A,B,C,D} = Om (1, 3, 4, 5, 9, 10, 11) + d (6,8).
the
03 (a) Design a 4-bit magnitude comparator circuit. Provide
truth table for the comparator. (5)
(b) Design a 16-to-1 multiplexer using 8-to-1 multiplexers.
Provide the logic diagram and truth table for your design.
(5)
UNIT-I

Design a
Q4 (a) Explain the concept of a modulus counter. JK flip
synchronous counter with a modulus of 9 using
(5)
flops. serial-in-parallel-out (SIPO) shift register
(b) How does a parallel-in-serial-out (PISO) shift register?
differ from a shift register
Consider a 4-bit serial-in, serial-out (SISO)
a clock signal that
with an initial state of 1101. Assume input
triggers the shift opcration on cach rising cdge. The the shift
Illustrate the state transitions of
data is 1010.
the output after
register for each clock cycle, showing
clock cycles, what will be
each shift operation. After four
(5)
the final state of the shift register?

P.T.0.

2024,12,252
[-2-]

Q5 (a) Design
a detector which detects 1100 (non
Sequence
Overlapping) IrOm ary gvern sequence. Implement usin D
flip flop.
Describe the (5)
(b) architecture of a Programmable Array Logic
(PAL) device. How doCs t
structure and functionality?dilier from a PLA in terms of
(5)
UNIT-III

laitn the role of the control unit, ALU, and registers in


Q6 (a) the CPU. How do they work Logether to execute
instructions?
(5)
(b) Describe arithmetic micro-opcrations in the contexL of
computer organization. Provide examples of arithmetic
operations and how they are performed at the micro
operation level. (5)

Define asscmbly language and describe its relationship


Q7 (a)
with machinc language. (5)
Explain the concept of microprogrammed control in
(b)
computer architecture. How does it differ from hardwired
control, and what are its advantages? (5)

UNIT-IV

Discuss the principles of cache napping., including direct


Q8 (a)
mapped, set-associative, and fully associative cachne
mapping. (5)
(b) Describe the rolc of direct memory access (DMA) in input
output operations. (5)

Q9 (a) Define virtual mcmory. How does virtual nernory address


the limitations of physical memory? (5)
(b) Discuss the binary subtraction process and describe how
borrow is handled in binarv subtraction (5)

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy