October University for Modern Sciences and Arts (MSA)

October University for Modern Sciences & Arts

Final Exam
(Model Answer)

Faculty Engineering
Department Electrical Communication and Electronics
Module Code ECE 445/ ECE 561
Module Title VLSI Design
Semester Spring 2019
Time Allowed 3 hours
Total Mark 40
No. of Pages Six (including the cover page)
Material provided None
Equipment permitted Non programmable calculator
Additional Instructions All Answers must be in English otherwise it will not be
considered.

No books, paper or electronic devices are permitted to be brought into the

examination room other than those specified above.

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October University for Modern Sciences and Arts (MSA)

Faculty of Engineering
Module Code: ECE 445/ ECE 561
Module Title: VLSI Design
Semester: Spring 2019

Model Answer:

Question 1: (ILOs: A5, B1, B2, and B3) (10 Marks)

A library ieee; 5 pts
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity RAM is
port( Clk, RE , WE, RST : in std_logic;
RAM_IN_Out: inout std_logic_vector (7 downto 0);
RAM_ADD: in std_logic_vector(6 downto 0)); 1 pts
end RAM;

Architecture behav of RAM is

type ram_type is array (0 to 127) of std_logic_vector (7 downto 0);
signal tmp_ram: ram_type;
0.5 pts
Begin

X <= RE&WE ; 1 pts

Process(Clk , RST)
begin
IF( RST = '1') then
For I in 0 to 127 loop
tmp_ram (i) <= (others => ‘0’) ;
End loop ; 1 pts
Elseif rising_edge (Clk) then
Case X IS
WHEN "00" =>
RAM_in_out <= tmp_ram(conv_integer(RAM_ADD));
WHEN "11" =>
tmp_ram(conv_integer(RAM_ADD)) <= RAM_IN_Out; 1.5 pts
RAM_in_out <= (RAM_out'range => 'Z');
WHEN OTHERS =>
RAM_in_out <= (RAM_out'range => 'Z');
END Case;
end if;
end process;
end behav;

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October University for Modern Sciences and Arts (MSA)

B Library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 0.5 pts 5 pts
use IEEE.STD_LOGIC_UNSIGNED.ALL;

GENERIC ( N : NATURAL RANGE 0 TO 16 := 4);

entity Comparator is
PORT(Data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
CLK, RST : IN STD_LOGIC; 1 pts
Load_OUT : OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0));
end Comparator;

Architecture Behavioral of Comparator is

TYPE DATA IS ARRAY (0 TO 7) of STD_LOGIC_VECTOR(4 DOWNTO 0);
CONSTANT X : DATA := ( "00100" , "10001" , "10101" , "01101" , "11110" , "00001" , "10100",
"00110");
signal out_temp: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
1 pts
Begin
Process(Data)
Variable J : STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
Begin
For I IN 0 to 7 loop
IF Data> X(I) then 1.5 pts
J :=J+'1';
END IF;
END loop;
out_temp <= J;
J:= (OTHERS => '0');
END Process;
Process (CLK , RST)
Begin
IF RST = '0' THEN
Load_out <= (OTHERS => '0');
ELSIF RISING_EDGE(CLK) THEN 1 pts
load_out <= out_temp;
end if;
END process;
END Behavioral;

Question 2: (ILOs: A5, B1, B2, B3, C3 and C4 ) (10 Marks)

A library IEEE; 4 pts
use IEEE.STD_LOGIC_1164.ALL; 0.5 pts
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity C_DIV is
PORT ( CLK, SEL : IN STD_LOGIC ;
CDIV : OUT STD_LOGIC );
end C_DIV; 0.5 pts

architecture Behavioral of C_DIV is

signal T: STD_LOGIC; 0.5 pts
begin

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October University for Modern Sciences and Arts (MSA)

process (clk)
variable I : integer := 0 ; 0.25 pts
begin
I := I+1;
IF (( (I = 3) and ( sel = '1') ) OR ( (I = 5) and ( sel = '0')) ) THEN
1.25 pts
T <= NOT ( T) ; I := 0 ;
END IF;
END PROCESS;
DIV <= T ;
END Behavioral;
Waveform 1 pts
B = + 3 − 0.25 6 pts
Expected no. of bits that represent the integer part of the output = 6 bits

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 0.5 pts
USE IEEE.STD_LOGIC_SIGNED.ALL;

entity FIR_TEST is
PORT ( D : IN std_logic_vectore (3 DOWNTO 0);
RST , CLK : IN STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)); 1 pts
end FIR_TEST;

Architecture Behavioral of FIR_TEST is

TYPE SHIFT IS ARRAY (1 TO 3) OF STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL Z : SHIFT;
0.5 pts
Begin
PROCESS ( RST, CLK ) 0.5 pts
BEGIN
IF RST = '0' THEN
FOR J IN 3 DOWNTO 1 LOOP
Z(J) <= (OTHERS => '0'); 1 pts
END LOOP;
FIR_OUT <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
FOR J IN 3 DOWNTO 1 LOOP
IF J = 1 THEN
Z(J) <= D; 1 pts
ELSE
Z(J)<= Z(J-1);
END IF ;
END LOOP;

FIR_OUT <= (D(3)&D(3)&D&”000”) +

(Z(1)(3)&Z(1)&”0000”) + (Z(1)(3)&Z(1)(3)&Z(1)&”000”)
- (Z(3)(3)&Z(3)(3)&Z(3)(3)&Z(3)(3)&Z(3)&”0”); 1.5 pts
END IF;
END PROCESS;
End Behavioral ;

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October University for Modern Sciences and Arts (MSA)

Question 3: (ILOs: A3, B1, B2, B3 and C2 ) (9 Marks)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP is
PORT (Data_In : IN OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 ); 2 pts
MCLK , RESET : IN STD_LOGIC
Result_O: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) );
end TOP;

Architecture structure of TOP is

Component FIR_TEST
PORT ( D : IN std_logic_vectore (3 DOWNTO 0);
RST , CLK : IN STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)); 1 pts
end Component;

GENERIC ( N : NATURAL RANGE 0 TO 16 := 4);

Component Comparator is
PORT(Data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
CLK, RST : IN STD_LOGIC;
1 pts
Load_OUT : OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0));
end Component;

COMPONENT C_DIV
PORT (CLK, SEL : IN STD_LOGIC ; 1 pts
CDIV : OUT STD_LOGIC);
end COMPONENT ;

SIGNAL X : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL S1 , S2 : STD_LOGIC ; 1 pts

Begin

F_FIR : C_DIV PORT MAP ( MCLK , 0 , S1) ;

F_Comp : C_DIV PORT MAP ( MCLK , 1 , S2);
FIR1 : FIR_TEST PORT MAP (X, RESET, S1, '0'&Result_O (8 downto 0)); 3 pts
Comp: Comparator PORT MAP (Data_In, S2, RESET, X);

End Structure;

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October University for Modern Sciences and Arts (MSA)

Question 4: (ILOs: A1, A2, B3, C1, and C4 ) (11 Marks)

A i 2 pts

ii 2 pts

iii 8 transistors are required 1 pts

B 3 pts

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode so we use heavily doped well and substrate contacts / taps

C = + + 3 pts

The End, best wishes, Dr. Hatem Zakaria

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