October University for Modern Sciences and Arts (MSA)

October University for Modern Sciences & Arts

Final Exam
(Model Answer)

Faculty Engineering
Department Electrical Communication and Electronics
Module Code ECE 445/ ECE 561
Module Title VLSI Design
Semester Fall 2018
Time Allowed 3 hours
Total Mark 40
No. of Pages Six (including the cover page)
Material provided None
Equipment permitted Non programmable calculator
Additional Instructions All Answers must be in English otherwise it will not be
considered.

No books, paper or electronic devices are permitted to be brought into the

examination room other than those specified above.

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October University for Modern Sciences and Arts (MSA)

Faculty of Engineering
Module Code: ECE 445/ ECE 561
Module Title: VLSI Design
Semester: Fall 2018

Model Answer:

Question 1: (13 Marks)

A State if the following statements are ( ) or ( ) and justify your answer ‘Note: Negation is not the
answer’:
i CMOS transmission gates are superior to n-MOS pass transistors because they can output 1 pts
strong ones and strong zeroes. ( )
ii Low power consumption of MOS transistor allows for their very high integration 1 pts
density compared to BJT transistors. ( )
iii Polysilicon is better than metal for self-aligned gates. ( ) 1 pts
It doesn’t melt during later processing
B Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
5 pts
USE IEEE.STD_LOGIC_USIGNED.ALL; 0.5 pts
ENTITY STACK IS
PORT ( SADD : INOUT STD_LOGIC_VECTOR (4 downto 0);
SIN : in STD_LOGIC_VECTOR (12 downto 0);
SOUT : out unsigned ( 11 downto 0);
PO , PU , CLK : in std_logic );
1 pts
end stack;

architecture STACK of stack is

type stack_data is array ( 0 to 2**5 -1 ) OF STD_LOGIC_VECTOR ( 12 DOWNTO 0);
SIGNAL A : STACK_DATA; 0.5 pts
SIGNAL SEL : STD_LOGIC_VECTOR (1 DOWNTO 0);

BEGIN
SEL <= PO&PU ; 1 pts
PROCESS ( CLK )
BEGIN
IF RISING_EDGE(CLK) THEN 0.5 pts
CASE SEL IS
WHEN "10" => A (CONV_INTEGER(SADD +1)) <= SIN;
SADD <= SADD +1;
SOUT <= (OTHERS => 'Z');
1.5 pts
WHEN "01" => SOUT <= A(CONV_INTEGER(SADD));
SADD <= SADD-1;
WHEN OTHERS => SOUT <= (OTHERS=>'X');
END CASE;
END IF;
END PROCESS;
END STACK;

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October University for Modern Sciences and Arts (MSA)

library IEEE; 5 pts

C use IEEE.STD_LOGIC_1164.ALL; 0.5 pts
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity C_DIV is
PORT ( CLK, SEL : IN STD_LOGIC ; 1 pts
DIV : OUT STD_LOGIC );
end C_DIV;

architecture Behavioral of C_DIV is 0.5 pts

signal T: STD_LOGIC;

begin 0.5 pts

process ( clk)
variable I : integer := 0 ; 0.5 pts
begin
I := I+1;
IF (( (I = 12) and ( sel = '1') ) OR ( (I = 6) and ( sel = '0')) ) THEN 2 pts
T <= NOT ( T) ; I := 0 ;
END IF;
END PROCESS;
DIV <= T ;
END Behavioral;

Question 2: (7 Marks)
Din + 0.625 DINZ-2- 0.283 DinZ-4
0.283 ≈ ¼ + 1/32 = Z-2 + Z-5 1 pts
-4
0.625 ≈ 1/16 Z
Expected no. of bits that represent the integer part of the output = 6 bits

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 0.5 pts
USE IEEE.STD_LOGIC_SIGNED.ALL;

entity FIR_TEST is
PORT ( D : IN std_logic_vector ( 3 DOWNTO 0);
RST , CLK : IN STD_LOGIC;
1 pts
F : OUT STD_LOGIC_VECTOR (12 DOWNTO 0));
end FIR_TEST;

Architecture Behavioral of FIR_TEST is

TYPE SHIFT IS ARRAY (1 TO 4) OF STD_LOGIC_VECTOR( 3 DOWNTO 0); 0.5 pts
SIGNAL Z : SHIFT; 0.5 pts

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Begin
PROCESS ( RST, CLK ) 0.5 pts
BEGIN
IF RST = '1' THEN
FOR J IN 4 DOWNTO 1 LOOP
Z(J) <= (OTHERS => '0'); 1 pts
END LOOP;
FIR_OUT <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
FOR J IN 4 DOWNTO 1 LOOP
IF J = 1 THEN
Z(J) <= DIN; 1 pts
ELSE
Z(J)<= Z(J-1);
END IF ;
END LOOP;

FIR_OUT <= (DIN(4)&DIN(4)&DIN(4)&DIN&”000000”) +

(Z(2)(4)&Z(2)(4)&Z(2)(4)&Z(2)(4)&Z(2)&”00000”) +
(Z(2)(4)&Z(2)(4)&Z(2)(4)&Z(2)(4)&Z(2)(4)&Z(2)(4)&Z(2)&”000”)- 1 pts
(Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)&”0000”) -
(Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)(4)&Z(4)&”0”)

END IF;
END PROCESS;
End Behavioral ;

Question 3: (10 Marks)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP is
PORT ( ADD : IN OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
DATA : IN OUT STD_LOGIC_VECTOR ( 5 DOWNTO 0 ); 2 pts
POP , PUSH , MCLK , RESET : IN STD_LOGIC
TOP_O1 , TOP_O2 : OUT STD_LOGIC_VECTOR ( 12 DOWNTO 0 ) );
end TOP;

architecture TOP of TOP is

COMPONENT FIR
PORT ( D : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0); 1 pts
CLK , RST: IN STD_LOGIC ;
F: OUT STD_LOGIC_VECTOR ( 12 DOWNTO 0));
END COMPONENT;

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October University for Modern Sciences and Arts (MSA)

COMPONENT STACK
PORT ( SADD : INOUT STD_LOGIC_VECTOR (4 downto 0); 1 pts
SIN : in STD_LOGIC_VECTOR (12 downto 0);
SOUT : out unsigned ( 12 downto 0);
PO , PU , CLK : in std_logic );
end COMPONENT;

COMPONENT C_DIV
PORT ( CLK, SEL : IN STD_LOGIC ; 1 pts
CDIV : OUT STD_LOGIC );
end COMPONENT ;

SIGNAL X : STD_LOGIC_VECTOR ( 12 DOWNTO 0); 1 pts

SIGNAL S1 , S2 : STD_LOGIC ;

Begin

F_DIF1 : C_DIV PORT MAP ( MCLK , 0 , S1) ;

F_DIV2 : C_DIV PORT MAP ( MCLK , 1 , S2); 4 pts
FIR1 : FIR PORT MAP ( DATA (3 downto 0), S1 , RESET , X);
STACK1: STACK PORT MAP ( ADD , X , TOP_O1 , PUSH , POP , S2 );

TOP_O2 <= X ;
END TOP;
Question 4: (10 Marks)
A i 2 pts

ii 2 pts

iii 8 Transistors. 1 pts

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October University for Modern Sciences and Arts (MSA)

B 3 pts

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called Shottky
Diode so we use heavily doped well and substrate contacts / taps

C 2 pts
The logic Function is
– = + + .

The End, best wishes, Dr. Hatem Zakaria

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