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‫الفرقة الثانية‬
Q1. What is control signals and How shall be supplied?
1) A program is sequence of steps.
2) Each step contains some arithmetic or logical operations.
3) For each step, a new set of control signals is needed.
4) A hardware segment accepts the code and issues the control signals.
5) Instead of rewriting the hardware for each new program.
6) Interpreter used to interpret each instruction and generate control signals.
Q2. Compare between programming in hardware and software.
Hardware:
✓ The system accepts data and control signals to produce results.
✓ A hardwired program: is inflexible.

Software:
✓ Instead of rewriting the hardware for each new program.
✓ An interpreter interprets each instruction and generates control
signals.

1 Assembly
Q3. State the Top-Level Computer Component

Small number of storage units store information's temporary in ALU.

Registers
Access to registers is much faster than access to memory locations.
IR Instruction Register: Contains instruction that is being executed.
Program Counter: Contains the address of the next instruction to be
PC
executed.
Memory Address Register: Specifies the address in memory for the
MAR
next read or write.
Memory Buffer Register: Contains data to be written/ receives
MBR
into/from memory.
I/O AR I/O Address Register: Specifies a particular I/O device.
I/O Buffer Register: Exchange data between an I/O module and the
I/OBR
CPU.

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Q4. Using figure show what is OpCode and how can affect AC
(accumulator)?
✓ Both instruction and data are 16 bits long.
✓ The instruction format provides 4 bits for the OpCode.
✓ OpCode is abbreviation of Operation Code.
✓ OpCode may be as many 24 = 16 different.
✓ Other for memory can be addressed 212 = 4096 (4K)
1) 0001 = load AC from Memory.
2) 0010 = Store AC to memory.
3) 0101= Add to AC from memory.

Q5. Trace the status of memory and CPU registers when adding two words
resides in memory at address 940 and address 941, and store the result
in address 941.

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Q6. What is the basic instruction cycle? Write short notes about each
instruction cycle?

✓ The fetch instruction is loaded into register (IR).

✓ The PC holds the address of the next instruction to fetch.
1) Processor fetch instruction from memory location pointed to by PC.
2) Load instructions into IR.
3) Processor interprets instruction and perform required actions.
Q7. What are four types of execute cycle?
Processor – memory Data transfer between CPU and memory.
Processor – I/O Data transfer between CPU and I/O.
Data processing Some arithmetic or logical operation on data.
Control e.g. Jump Alteration of sequence of operations.

Q8. What is Interrupt? Interrupt handler? ISR?

1) Interrupt:
✓ A signal to processor indicating an event that needs immediate attention.
✓ Signal alerts (request) to the processor to interrupt (temporary) the
currently executing code.
✓ The processor resume normal activities after the interrupt handler finishes.
2) Interrupt handler:
✓ Responds of processor by suspending the current activities, saving its state
and execute the function.
3) ISR
✓ Interrupt Service Routine Is interrupt handler.
✓ Is a software process invoked by an interrupt request from a hardware
device to handle request and sends it to the CPU.

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Q9. What are classes of interrupts?

Arithmetic overflow - Division by zero, illegal machine

Program
instruction, outside user allowed memory space.
Timer by the processor allow operating system to perform
Timer
certain functions.
I/O By I/O controller.
Hardware Failure Such power Failure – Memory error.

Q10. Graph full instruction cycle – state diagram.

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Q11. Using the next example program show how transfer control vial
interrupts (Program Flow Control)

✓ Label 1, 2, 3 refer to sequence of instructions do not involve I/O.

✓ WRITE calls are to the I/O Program.
✓ I/O contains 3 sections:
1) Label 4: prepare actual code (e.g. copy data to buffer).
2) I/O Commands: Actual code commands without interrupt.
3) Label 5: complete the operation (setting flags).

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Q12. Describe Instruction cycle with interrupts.

✓ Add to instruction cycle.

✓ Processor checks for interrupt. (indicate by interrupt signal)
✓ If no interrupt, fetch next instruction.
✓ If interrupt pending:
1) Suspend execution of current program.
2) Save context.
3) Set PC to start address of interrupt handler routine.
4) Process interrupt.
5) Restore context and continue interrupted program.

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Q13. Using the next program compare between Timing Short and long
I/O Wait

Short long

Q14. True or False:

1- Low priority interrupts can be interrupted by higher priority interrupts.
[True]
2- When higher priority interrupt has been processed processor returns to
previous interrupt. [True]

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Q15. Graph a figure that shows different types of multiple interrupts.

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Q16. What is the computer main component (units) how can connect?
Three basic types (processor, memory, I/O) communicate with each
other.
The collection of paths connecting the various modules called the
interconnection structure.
The design of this structure will depend on the exchanges among
modules.
Q17. Describe Memory connections.
Receives and sends data.
Receives addresses (of locations).
Receives control signals.
1. Read
2. Write
3. Timing
Q18. Describe Input/output connections.
Similar to memory from computer’s viewpoint. [True]

I/O module may control more than one external device.

Refer to each interface of an external device as a port. (with unique
address)

I/O module may be able to:

1- Send interrupt signals to the processor.
2- Receive control signals from computer.
3- Send control signals to peripherals.
4- Receive addresses from computer.
❖ Output:
1. Receive data from computer.
2. Send data to peripheral.
❖ Input:
1. Send data to computer.
2. Receive data from peripheral.
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Q19. Describe CPU connections.

Read instructions and data.

Writes out data after processing.

Send control signals to control the overall operation of the system.

It also receives (acts) interrupt signals.

Q20. What are Buses? State its characteristic. Types.
A communication pathway connecting two or more devices.

A key characteristic:
1) Shared transmission medium. ‫وسيلة نقل مشتركة‬
2) Multiple devices connect to the bus, and a signal transmitted by any
one device is available for reception by all other devices attached to
the bus.
3) If two devices transmit during the same time period, their signals will
overlap and become garbled ‫مشوهه‬.
4) Thus, only one device at a time can successfully transmit.
5) A communication pathway connecting two or more devices.
6) Usually broadcast.
7) Often grouped a number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
8) Power lines may not be shown

Types: Control - Address - Data

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Q21. What is the difference between Data bus, Address bus, and control
bus?
Data Bus Address bus Control Signal

There is no difference Identify the source and Memory read / write signal
between data and destination of data. Interrupt signal
instruction. At this level. 8080 has 16-bit address Clock signals.
Width determine bus Responsible for directing the
performance. 64K address. flow of instructions and data
within the CPU
May consists of 32, 64,
128
Each line can carry only
1 bit at a time.
If the data bus is 32 and
each instruction is 64
bits long then the
processor must access
the memory twice.

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Q22. What are different control lines?
1) Memory write (data on bus written into address location).

2) Memory read (data from address placed on bus).

3) I/O write (data on bus to output address port).

4) I/O read (data from address port placed on bus).

5) Transfer ACK (data have been accepted from or placed on the bus).

6) Bus request (module need to gain control of bus).

7) Bus grant (module has been granted control of bus).

8) Interrupt request (interrupt is pending).

9) Interrupt ACK (interrupt has been recognize).

10) Clock: synchronize operations.

11) Reset: initialize all modules.

Q23. Describe RAM components.

❖ RAM: (combining latches with decoder)

Latches: create circuitry that can remember.

Decoder: create a way of individual memory locations to be

selected.

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