TPSM82901

SLVSG68 – NOVEMBER 2022

TPSM82901, 1-A, 3-V to 17-V, High Efficiency and Low IQ Buck Converter Module in a
MicroSiPTM Package with an Integrated Inductor

1 Features 3 Description
• High efficiency for wide duty cycle and load range The TPSM82901 is a highly efficient, small, and
– IQ: 4-µA typical flexible synchronous step-down DC-DC converter
– 62-mΩ high-side and 22-mΩ low-side RDS(ON) MicroSiP package module that is easy to use. A
• 3-mm × 2.8-mm × 1.6-mm MicroSiP™ package selectable switching frequency of 2.5 MHz or 1.0 MHz
• Up to 1-A continuous output current allows the use of small components and provides fast
• ±0.9% feedback voltage accuracy across temp transient response. The device supports high VOUT
(–40°C to 125°C) accuracy of ± 1% with the DCS-Control topology. The
• Configurable output voltage options: wide input voltage range of 3 V to 17 V supports a
– VFB external divider: 0.6 V to 5.5 V variety of nominal inputs, like 12-V supply rails, single-
– VSET internal divider: 16 options between 0.4 V cell or multi-cell Li-Ion, and 5-V or 3.3-V rails.
and 5.5 V The TPSM82901 can automatically enter power save
• DCS-Control topology with 100% mode mode (if auto PFM/PWM is selected) at light loads to
• Flexibility through MODE/S-CONF pin maintain high efficiency. Additionally, to provide high
– 2.5-MHz or 1.0-MHz switching frequency efficiency at very small loads, the device has a low
– Forced PWM or auto (PFM) power save mode typical quiescent current of 4 µA. AEE, if enabled,
with dynamic mode change option provides high efficiency across VIN, VOUT, and load
– Automatic efficiency enhancement (AEE) current. The device includes a MODE/Smart-CONF
– Output discharge on/off input to set the internal/external divider, switching
• Highly flexible and easy to use frequency, output voltage discharge, and automatic
– Optimized pinout for single-layer routing power save mode or forced PWM operation.
– Precise enable input
The device is available in small 11-pin MicroSiP
– Power-good output
package measuring 3.0 mm × 2.8 mm × 1.6 mm with
– Adjustable soft start and tracking
an integrated 1-μH inductor.
• No external bootstrap capacitor required
• Create a custom design using the TPSM82901 Package Information
using the WEBENCH® Power Designer PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPSM82901 SIS (uSiP, 11) 3.00 mm × 2.80 mm
2 Applications
• Data center and enterprise computing (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Wired networking
• Wireless infrastructure
• Factory automation and control
• Test and measurement
VIN VOUT 100%
TPSM8290x
3V t 17V 0.6V t 5.5V
90%
VIN VOUT
80%

EN GND C2 70%
C1
R1 22…F
Efficiency (%)

10…F 60%
FB/
SS/TR
VSET 50%

MODE/ R2 40%
PG
S-CONF
C3 R3 30%
VIN=17V
20% VIN=15V
VIN=12V
VIN=9V
10% VIN=6V
VIN=3V
0
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1

Simplified Schematic IOUT (A)

Efficiency Versus Output Current (1.2 VO at 2.5

MHz, Auto PFM/PWM)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................14
2 Applications..................................................................... 1 8 Application and Implementation.................................. 17
3 Description.......................................................................1 8.1 Application Information............................................. 17
4 Revision History.............................................................. 2 8.2 Typical Application with Adjustable Output Voltage.. 17
5 Pin Configuration and Functions...................................3 8.3 Typical Application with Setable VO Using VSET .... 29
6 Specifications.................................................................. 4 8.4 Power Supply Recommendations.............................32
6.1 Absolute Maximum Ratings........................................ 4 8.5 Layout....................................................................... 32
6.2 ESD Ratings............................................................... 4 9 Device and Documentation Support............................35
6.3 Recommended Operating Conditions.........................4 9.1 Device Support......................................................... 35
6.4 Thermal Information....................................................5 9.2 Receiving Notification of Documentation Updates....35
6.5 Electrical Characteristics.............................................5 9.3 Support Resources................................................... 35
6.6 Typical Characteristics................................................ 7 9.4 Trademarks............................................................... 35
7 Detailed Description........................................................8 9.5 Electrostatic Discharge Caution................................35
7.1 Overview..................................................................... 8 9.6 Glossary....................................................................35
7.2 Functional Block Diagram........................................... 8 10 Mechanical, Packaging, and Orderable
7.3 Feature Description.....................................................9 Information.................................................................... 36

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
November 2022 * Initial Release

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5 Pin Configuration and Functions

VIN 1 10 VOUT

VIN 2 9 VOUT

EN 3 11
GND 8 SW/NC
GND

MODE/S-CONF 4 7 FB/VSET

SS/TR 5 6 PG

Figure 5-1. 11-Pin SIS MicroSiP™ Package (Top View, Device Pins Face Down)

Table 5-1. Pin Functions

Pin
I/O Description
Name Number
Power supply input pin. Ensure the input capacitor is connected as close as possible between
VIN 1, 2 I
the VIN and GND pins.
Enable input pin. Connect to logic low to disable the device. Pull high to enable the device. Do
EN 3 I
not leave this pin unconnected.
Device mode selection (auto PFM/PWM or forced PWM operation) and SmartConfig™
MODE/
4 I application. Connect high, low, or to a resistor to configure the device according to Table 7-2.
S-CONF
Do not leave this pin unconnected.
Soft start/tracking pin. An external capacitor connected from this pin to GND defines the rise
SS/TR 5 I time for the internal reference voltage. The pin can also be used as an input for tracking and
sequencing. The pin can be left floating for the fastest ramp-up time.
Open-drain power-good output. High = VOUT is ready. Low = VOUT is below nominal regulation.
PG 6 O
This pin requires a pullup resistor.
Depends on device configuration (see Section 7.3.1)
• FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
FB/VSET 7 I • VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage
according to Table 7-3.

SW/NC 8 NC Switch pin of the converter. Do not connect, leave floating.

VOUT 9, 10 O Output voltage pin. Connect directly to the positive pin of the output capacitor.
Ground pin. It must be connected directly to the common ground plane. It must be soldered to
GND 11 —
achieve appropriate power dissipation and mechanical reliability.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN –0.3 18
EN, PG –0.3 18
Voltage(2) V
MODE/S-CONF –0.3 18
FB/VSET, SS/TR, VOUT –0.3 6
TJ Junction temperature –55 125 °C
Peak reflow case temperature 260 °C
Maximum number of reflows allowed 3
Mechanical
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 1500 G
shock
Mechanical
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz 20 G
vibration
Tstg Storage temperature –55 125 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/
±500
JEDEC JS-002, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage range 3.0 17 V
VO Output voltage range 0.4 5.5 V
CI Effective input capacitance 3 10 µF
CO Effective output capacitance (2.5MHz selection) 10 22 100 (1) µF
CO Effective output capacitance (1.0MHz selection) 6 22 50 (1) µF
IOUT Output current 0 1 A
ISINK_PG Sink current at PG-Pin 1 mA
TJ Junction temperature (2) -40 125 °C

(1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitor.
(2) Operating lifetime is derated at junction temperatures greater than 125°C.

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6.4 Thermal Information

TPSM8290x
THERMAL METRIC(1) uSIP11-Pin UNIT
JEDEC PCB TPSM8290xEVM-188
RθJA Junction-to-ambient thermal resistance 58.2 48.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.5 °C/W
RθJB Junction-to-board thermal resistance 26.9 °C/W
ΨJT Junction-to-top characterization parameter 0.3 0.8 °C/W
ΨJB Junction-to-board characterization parameter 26.6 27.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 26.0 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

VI = 3 V to 17 V, TJ = -40°C to +125°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
Operating Quiescent Current (Power
IQ_PSM Iout = 0 mA, device not switching 4 µA
Save Mode)
Operating Quiescent Current (PWM VIN=12 V, VOUT=1.2 V; Iout = 0 mA,
IQ_PWM 8 mA
Mode) device switching
ISD Shutdown current into VIN pin EN = 0 V 0.27 3.5 µA
Under Voltage Lock-Out VIN rising 2.85 2.925 3.0 V
VUVLO
Under Voltage Lock-Out VIN falling 2.7 2.775 2.85 V
VUVLO_HYS Under Voltage Lock-Out Hysteresis Hysteresis 150 mV
CONTROL & INTERFACE
ILKG EN Input leakage current EN = 12 V 10 300 nA
High-Level Input Voltage at MODE/S-
VIH_MODE 1.0 V
CONF-Pin
Thermal Shutdown Threshold TJ rising 170
TSD °C
Thermal Shutdown Hysteresis Hysteresis 20
VIH High-level input voltage at EN-Pin 0.97 1.0 1.03 V
VIL Low-level input voltage at EN-Pin 0.87 0.9 0.93 V
Smart-Enable Internal Pulldown
REN_PD EN = LOW 0.5 MΩ
Resistor
VFB rising, referenced to VFB nominal 93.5% 96% 99%
VPG Power good threshold VFB falling, referenced to VFB nominal 88.5% 93% 96%
Hysteresis 1.5% 3.5% 6%
VPG_OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V
IPG_LKG Input leakage current into PG pin VPG = 5 V 15 550 nA
tPG_DLY Power good delay time VFB falling 32 µs
RSET S-CONF/VSET Resistor Tolerance –4 +4 %
Maximum Capacitance connected to
CSET 30 pF
S-CONF/VSET Pins
POWER SWITCHES
ILKG_SW Leakage current into SW-Pin VSW = VOS = 5.5 V 2 7 µA
High-side FET on resistance VIN > 4 V, ISW = 500 mA 62 111
RDS_ON mΩ
Low-side FET on resistance VIN > 4 V, ISW = 500 mA 22 40

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6.5 Electrical Characteristics (continued)

VI = 3 V to 17 V, TJ = -40°C to +125°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-side FET current limit TPSM82901 2.6 3.4 4.3 A
ILIM
Low-side FET current limit TPSM82901 2.4 2.8 3.2 A
ILIM_SINK Low-side FET sink current limit 1.3 1.7 2.5 A
fSW Switching frequency 2.5-MHz selection 2.5 MHz
TON(MIN) Minimum On-time 50 ns
fSW Switching frequency 1.0-MHz selection 1.0 MHz
D Dutycycle 1
RPD Dropout resistance 100% mode, VIN > 4 V 100 mΩ
OUTPUT
VSET Configuration selected. TJ =
VO_Reg1 Output Voltage Regulation –0.9% +0.9%
25°C.
VSET Configuration selected. 0 °C<
VO_Reg2 Output Voltage Regulation –1.1% +1.1%
TJ < 85°C
VSET Configuration selected. –40°C <
VO_Reg3 Output Voltage Regulation –1.25% +1.25%
TJ < 125°C
VFB Feedback Regulation Voltage Adjustable Configuration selected 0.6 V
VFB_Reg1 Feedback Voltage Regulation FB-Option selected. TJ = 25°C. –0.6% +0.6%
VFB_Reg2 Feedback Voltage Regulation FB-Option selected. 0°C < TJ < 85°C. –0.65% +0.65%
FB-Option selected. –40°C < TJ <
VFB_Reg3 Feedback Voltage Regulation –0.9% +0.9%
125°C
IFB Input leakage current into FB pin Adjustable configuration, VFB = 0.6 V 1 70 nA
IO = 0 mA, time from EN=HIGH
Start-up delay time until start switching, Adjustable 600 1400 µs
Configuration selected
Tdelay IO = 0 mA, time from EN=HIGH until
start switching, VSET Configuration
Start-up delay time 650 1850 µs
selected. The typical value is based on
the first option of VSET configuration.
IO = 0 mA after Tdelay, from 1st
TSS Soft-Start time switching pulse until target VO; TR/SS- 150 200 µs
Pin = OPEN
ISS SS/TR source current 2.3 2.5 2.7 µA
Tracking Gain, Adjustable
VFB/VSS/TR 0.75
Configuration
VFB/VSS/TR Tracking Gain tolerance ±8 mV
Discharge = ON - Option Selected, EN
RDISCH Active Discharge Resistance 7.5 20 Ω
= LOW,

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6.6 Typical Characteristics

9 80
-40C 17V
0C 12V
8 25C 70 6V
125C 3V
7
60
Input Current (uA)

Input Current (uA)

6
50
5
40
4
30
3

20
2

1 10

0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120125
VIN (V) Temperature (C)

Figure 6-1. Typical Quiescent Current vs VIN Figure 6-2. Maximum Quiescent Current vs
Temperature
1 0.85
-40C -40C
-25C
25C 0C
85C 0.8 25C
125C 85C
0.8 125C

Vout Accuracy VFEB (± %)

0.75
Input Current (uA)

0.7
0.6

0.65

0.4
0.6

0.55
0.2

0.5

0 0.45
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VIN (V) VIN (V)

Figure 6-3. Typical Shutdown Current Figure 6-4. Output Voltage Accuracy – VFEB
Selected

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7 Detailed Description
7.1 Overview
The TPSM82901 synchronous step-down converter MicroSiP package module is based on DCS-Control (Direct
Control with Seamless Transition into power save mode). DCS-Control is an advanced regulation topology
that combines the advantages of hysteretic, voltage mode, and current mode control. This control loop takes
information about output voltage changes and feeds it directly to a fast comparator stage. The control loop
sets the switching frequency, which is constant for steady-state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low-ESR capacitors.
7.2 Functional Block Diagram
PG VIN

VI
Ref –
1.0 V
+ HS Limit
EN

VO

Device Control Power Control

Internal/External
and Logic
FB Divider
/VSET
Resistor-to-Digital Gate
Power Save Mode
Driver
Forced PWM
VFB Smart-Enable 100% Mode
Ref-System
SS/TR UVLO
Start-up Handling
SmartConfigTM
PG-Control
Thermal Shutdown
Resistor-to-
MODE Digital
/S-CONF
MODE Detection LS Limit

VOUT
VO VOS Direct
VI
Control
TON Timer
VFB –
+ VO
Device VREF DCS-ControlTM
Control

GND

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7.3 Feature Description

7.3.1 Mode Selection and Device Configuration (MODE/S-CONF)
With MODE/S-CONF (SmartConfig application), this device features an input with two functions. It can be used
to customize the device behavior in two ways:
• Select the device mode (FPWM or auto PFM/PWM with AEE operation) traditionally with a HIGH- or LOW-
level.
• Select the device configuration (switching frequency, internal/external feedback, output discharge, and
PFM/PWM mode) by connecting a single resistor to the MODE/S-CONF pin.
The device interprets this pin during the start-up sequence after the internal OTP readout and before it starts
switching in soft start. If the device reads a HIGH- or LOW-level, the dynamic mode change is active and
PFM/PWM mode can be changed during operation. If the device reads a resistor value, there is no further
interpretation during operation and device mode or other configurations cannot be changed afterward.

Note
The MODE/S-CONF pin must not be left floating. Connect the pin high, low, or to a resistor to
configure the device according to Table 7-2.

EN and UVLO

Precise PG to High
OTP S-CONF VSET
Enable Softstart Switching
Readout Readout Readout
Detection Operation

No Interpretation of Resistor-to-Digitial
MODE/S-CONF or VSET Readout and MODE-Pin Toggling Detection
Interpretation

VOUT

Figure 7-1. Interpretation of S-CONF and VSET Flow

CAUTION
For each operating mode and switching frequency, the following VOUT range is recommended:
Table 7-1. Recommended VOUT Ranges with Respect to MODE and FSW
Mode FSW (MHz) VOUT

Auto PFM/PWM 1 MHz 0.4 V < VOUT < 2.0 V

Forced PWM 1 MHz 0.4 V < VOUT < 2.0 V

Auto PFM/PWM with AEE 2.5 MHz 0.4 V < VOUT< 5.5 V

Forced PWM 2.5 MHz 2.0 V < VOUT < 5.5 V

Failure to follow the recommended VOUT ranges causes the device to malfunction.

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Table 7-2. SmartConfig™ Application Setting Table

Level Or Resistor Value [Ω] FB/VSET- Output Mode (Auto or Forced Dynamic Mode
# (1) FSW (MHz)
Pin Discharge PWM) Change
Setting Options by Level
Auto PFM/PWM with
1 GND external FB 2.5 yes
AEE active
2 HIGH (>VIH_MODE) external FB 2.5 yes Forced PWM
Setting Options by Resistor
Auto PFM/PWM with
3 7.15 k external FB 2.5 no
AEE
4 8.87 k external FB 2.5 no Forced PWM
5 11.0 k external FB 1 yes Auto PFM/PWM
6 13.7 k external FB 1 yes Forced PWM
7 16.9 k external FB 1 no Auto PFM/PWM
8 21.0 k external FB 1 no Forced PWM
Auto PFM/PWM with
9 26.1 k VSET 2.5 yes
AEE not active
10 32.4 k VSET 2.5 yes Forced PWM
Auto PFM/PWM with
11 40.2 k VSET 2.5 no
AEE
12 49.9 k VSET 2.5 no Forced PWM
13 61.9 k VSET 1 yes Auto PFM/PWM
14 76.8 k VSET 1 yes Forced PWM
15 95.3 k VSET 1 no Auto PFM/PWM
16 118 k VSET 1 no Forced PWM

(1) E96 Resistor Series, 1% Accuracy, Temperature Coefficient better or equal than ±200 ppm/°C

7.3.2 Adjustable VO Operation (External Voltage Divider)

The TPSM82901 can be programmed by the MODE/S-CONF pin to either classical configuration where the
FB/VSET pin is used as the feedback pin, sensing VO through an external resistive divider. The TPSM82901 can
also be programmed to 16 different fixed output voltages. These are set through an external resistor between the
FB/VSET pin and GND. In this configuration, VO is directly sensed at the VOS internal terminal connection of the
device.
If the device is configured to operate in classical adjustable VO operation, the FB/VSET pin is used as
the feedback pin and needs to sense VO through an external divider network. Figure 7-2 shows the typical
schematic for this configuration.
VIN VOUT
TPSM8290x
3V t 17V 0.6V t 5.5V
VIN VOUT

EN GND C2
C1
R1 22…F
10…F
FB/
SS/TR
VSET

MODE/ R2
PG
S-CONF
C3 R3

Figure 7-2. Adjustable VO Operation Schematic

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7.3.3 Setable VO Operation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, VO is sensed only through the internal VOS connection by an
internal resistor divider. The target VO is programmed by an external resistor connected between the VSET pin
and GND. Figure 7-3 shows the typical schematic for this configuration.
VIN VOUT
TPSM8290x
3V t 17V 0.4V t 5.5V
VIN VOUT

EN GND C2
C1
10…F 22…F
FB/
SS/TR
VSET

MODE/ R2
PG
S-CONF
C3 R3

Figure 7-3. Setable VO Operation Schematic

Table 7-3. VSET Selection Table

# Resistor Value [Ω] Target VO [V]
1 GND 1.2
2 4.64 k 0.4
3 5.76 k 0.6
4 7.15 k 0.8
5 8.87 k 1.0
6 11.0 k 1.1
7 13.7 k 1.3
8 16.9 k 1.35
9 21.0 k 1.8
10 26.1 k 1.9
11 40.2 k 2.5
12 61.9 k 3.8
13 76.8 k 5.0
14 95.3 k 5.1
15 118.0 k 5.5
16 249.00 k or larger/Open 3.3

7.3.4 Soft Start/Tracking (SS/TR)

With the SS/TR pin, it is possible to adjust the soft-start behavior and track an external voltage. See Section
8.2.2.4 for operation details.
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and makes sure there is a controlled output voltage rise time. It also prevents unwanted voltage drops
from high impedance power sources or batteries. When EN is set high to start operation, the device starts
switching after a delay, then the internal reference, and hence VO, rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving the SS/TR pin unconnected provides the fastest start-up, limited internally (the pin must not be pulled
LOW externally).

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If the device is set to shut down (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor
pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new start-up
sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used to track a primary voltage. The output voltage follows this voltage up
and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current.
7.3.5 Smart Enable with Precise Threshold
The voltage applied at the enable pin of the TPSM82901 is compared to a fixed threshold rising voltage, allowing
the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve
a power-up delay.
The precise enable input allows the user to program the undervoltage lockout by adding a resistor divider to the
input of the enable pin.
The enable input threshold for a falling edge is lower than the rising edge threshold. The TPSM82901 starts
operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must
not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side
and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.
An internal resistor pulls the EN pin to GND when the device is disabled and avoids floating the pin after the
device is enabled, the pulldown is removed. This prevents an uncontrolled start-up of the device in case the EN
pin cannot be driven to a low level safely. With EN low, the device is in shutdown mode. The device is turned
on with EN set to a high level. The pulldown control circuit disconnects the pulldown resistor on the EN pin after
the internal control logic and the reference have been powered up. With EN set to a low level, the device enters
shutdown mode and the pulldown resistor is activated again.
7.3.6 Power Good (PG)
The TPSM82901 has a built-in power-good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin
is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.
PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN must
remain present for the PG pin to stay low.
If the power-good output is not used, it is recommended to tie to GND or leave it open.
Table 7-4. Power Good Indicator Functional Table
Logic Signals
PG Status
VI EN Pin Thermal Shutdown VO
VO on target High Impedance
No
HIGH VO < target LOW
VI > UVLO
Yes x LOW
LOW x x LOW
1.8 V< VI < UVLO x x x LOW
VI < 1.8 V x x x Undefined

7.3.7 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both
the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
7.3.8 Current Limit And Short Circuit Protection
The TPSM82901 is protected against overload and short circuit events. If the inductor current exceeds the
high-side FET current limit (ILIMH), the high-side switch is turned off and the low-side switch is turned on to
ramp down the inductor current. The high-side FET turns on again only if the current in the low-side FET has
decreased below the low-side FET current limit threshold.

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Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given as Equation 1:

VL
Ipeak (typ ) = ILIMH + ´ tPD
L (1)

where
• ILIMH is the static high-side FET current limit as specified in the Electrical Characteristics.
• L is the effective inductance at the peak current (approximately 0.9 μH).
• VL is the voltage across the inductor (VIN – VOUT).
• tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:

V IN - V O U T
I p e a k ( ty p ) = I L I M H + ´ 50ns
L (2)

7.3.9 Thermal Shutdown

The junction temperature, TJ, of the device is monitored by an internal temperature sensor. If TJ rises and
exceeds the thermal shutdown threshold, TSD, the device shuts down. Both the high-side and low-side power
FETs are turned off and PG goes low. When TJ decreases below the hysteresis, the converter resumes normal
operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A
shutdown or re-start is only triggered during a switching cycle. See Section 7.4.3.

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7.4 Device Functional Modes

7.4.1 Pulse Width Modulation (PWM) Operation
The TPSM82901 has two operating modes: forced PWM mode discussed in this section and PWM/PFM as
discussed in Section 7.4.3.
With the MODE/S-CONF pin configured for PWM mode, the TPSM82901 operates with pulse width modulation
in continuous conduction mode (CCM) with a nominal switching frequency of 2.5 MHz/1.0 MHz. The frequency
variation in PWM is controlled and depends on VIN, VOUT, and the inductance. The on time in forced PWM mode
is given by Equation 3:

VOUT 1
TON u
VIN f sw (3)

7.4.2 AEE (Automatic Efficiency Enhancement)

When the MODE/S-CONF pin is configured for AEE mode, the TPSM82901 provides the highest efficiency
over the entire input voltage and output voltage range by automatically adjusting the switching frequency of the
converter. This is achieved by setting the predictive off time of the converter. The efficiency of a switched mode
converter is determined by the power losses during the conversion. The efficiency decreases if VOUT decreases,
VIN increases as shown in Equation 4, or both. In order to keep the efficiency high over the entire duty cycle
range (VOUT/VIN ratio), the switching frequency is adjusted while maintaining the ripple current.

VIN VOUT
Fsw ( MHz ) 10 u VOUT u
VIN 2 (4)

The AEE function in the TPSM82901 adjusts the on time (TON) in power save mode, depending on the input
voltage and the output voltage to maintain highest efficiency. The on time in steady-state operation can be
estimated as using Equation 5:

VIN
TON = 100 ´ [ns ]
VIN - VOUT (5)

Equation 6 shows the relationship among the inductor ripple current, switching frequency, and duty cycle.

V
1 ( OUT )
1 D VIN
'I L VOUT u ( ) VOUT u ( )
L u f SW L u f SW (6)

Efficiency increases by decreasing switching losses and preserving high efficiency for varying duty cycles, while
the ripple current amplitude remains low enough to deliver the full output current without reaching current limit.
The AEE feature provides an efficiency enhancement for various duty cycles, especially for lower VOUT values
where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates
for the very small duty cycles of high VIN to low VOUT conversion, which limits the control range in other
topologies.
7.4.3 Power Save Mode Operation (Auto PFM/PWM)
When the MODE/S-CONF pin is configured for power save mode (auto PFM/PWM), the device operates in
PWM mode as long the output current is higher than half of the ripple current of the inductor. To maintain high
efficiency at light loads, the device enters power save mode at the boundary to discontinuous conduction mode
(DCM). This happens if the output current becomes smaller than half of the ripple current of the inductor. The
power save mode is entered seamlessly when the load current decreases. This makes sure there is a high
efficiency in light load operation. The device remains in power save mode as long as the inductor current is
discontinuous.

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In power save mode, the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition in and out of power save mode is seamless in both directions.
In addition to adjusting the switching, the TPSM82901 adjusts the on time (TON) in power save mode,
depending on the input voltage and the output voltage to maintain the highest efficiency using the AEE function
when 2.5 MHz is selected as described in Section 7.4.2.
In power save mode, the TON time can be estimated using Equation 3 for 1 MHz and Equation 5 for 2.5 MHz
(given the AEE is enabled for 2.5 MHz).
For very small output voltages, an absolute minimum on time of about 50 ns is kept to limit switching losses.
The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the
typical peak inductor current in power save mode is approximated by Equation 7:

IL P S M ( peak ) =
(V IN - VO U T )
´ TO N
L (7)

There is a minimum off time that limits the duty cycle of the TPSM82901. When VIN decreases to typically 15%
above VOUT, the TPSM82901 does not enter power save mode, regardless of the load current. The device
maintains output regulation in PWM mode.
The output voltage ripple in power save mode is given by Equation 8:

L ´ VIN 2 æ 1 1 ö
DV = ç + ÷
200 ´ C è VIN - VOUT VOUT ø (8)

where
• L is the effective inductance (approximately 0.9 μF).
• C is the output effective capacitance.
7.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operating in PWM mode is given as D = VOUT/VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time
of typically 80 ns is reached, the TPSM82901 scales down its switching frequency while it approaches 100%
mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side switch stays turned
on as long as the output voltage is below the internal set point. This allows the conversion of small input to
output voltage differences (for example, getting longest operation time of battery-powered applications). In 100%
duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:

VIN (min) = VOUT + IOUT (RDS ( on ) + RL ) (9)

where
• IOUT is the output current.
• RDS(on) is the on-state resistance of the high-side FET.
• RL is the DC resistance of the inductor used (approximately 40 mΩ).
7.4.5 Output Discharge Function
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device
is being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active after the TPSM82901 has been enabled at least once since the supply voltage was applied.
The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as soon as the

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device is disabled, in thermal shutdown, or in undervoltage lockout. The minimum supply voltage required for the
discharge function to remain active typically is 2 V.
7.4.6 Starting into a Pre-Biased Load
The TPSM82901 is capable of starting into a pre-biased output. The device only starts switching when the
internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPSM82901 does not start switching unless the voltage at the
feedback pin drops to the target.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The TPSM82901 device is highly efficient, small, and flexible synchronous step-down DC-DC converter
MicroSiP package module that is easy to use. A wide input voltage range of 3 V to 17 V supports a wide
variety of inputs like 12-V supply rails, single-cell or multi-cell Li-Ion, and 5-V or 3.3-V rails.
8.2 Typical Application with Adjustable Output Voltage
VIN VOUT
TPSM8290x
3V t 17V 0.6V t 5.5V
VIN VOUT

EN GND C2
C1
R1 22…F
10…F
FB/
SS/TR
VSET

MODE/ R2
PG
S-CONF
C3 R3

Figure 8-1. Typical Application Circuit

8.2.1 Design Requirements

Table 8-1. List of Components
Reference Description Manufacturer
IC 17 V, 3-A Step-Down Converter TPSM8290x series; Texas Instruments
CIN 10 µF, 25 V, Ceramic, 0805 C3216X7R1E106M160AE, TDK
COUT 22 µF, 16 V, Ceramic, 0805 C2012X7S1A226M125AC, TDK
CSS Depends on soft start time; see Section 8.2.2.3.3. 16 V, Ceramic, X7R
R1 Depending on VOUT; see Section 8.2.2.2. Standard 1% metal film
R2 Depending on VOUT; see Section 8.2.2.2. Standard 1% metal film
R3 Depending on device setting, see Section 7.3.1. Standard 1% metal film

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM82901 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.

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In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Programming the Output Voltage
The output voltage of the TPSM82901 is adjustable. It can be programmed for output voltages from 0.6 V to 5.5
V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of
the output voltage is set by the selection of the resistor divider from Equation 10. It is recommended to choose
resistor values that allow a current of at least 2 μA, meaning the value of R2 must not exceed 400 kΩ. Lower
resistor values are recommended for highest accuracy and most robust design.

æ VOUT ö
R1 = R 2 ´ ç - 1÷
è VFB ø (10)

With typical VFB = 0.6 V, 1-MHz switching frequency is not recommended for VOUT > 1.8 V.
Table 8-2. Setting the Output Voltage
Nominal Output Voltage R1 R2 Exact Output Voltage
0.75 V 24.9 kΩ 100 kΩ 0.749 V
1.2 V 100 kΩ 100 kΩ 1.2 V
1.5 V 150 kΩ 100 kΩ 1.5 V
1.8 V 200 kΩ 100 kΩ 1.8 V
2.0 V 49.9 kΩ 21.5 kΩ 1.992 V
2.5 V 100 kΩ 31.6 kΩ 2.498 V
3.0 V 100 kΩ 24.9 kΩ 3.009 V
3.3 V 113 kΩ 24.9 kΩ 3.322 V
5.0 V 182 kΩ 24.9 kΩ 4.985 V

8.2.2.3 Capacitor Selection

8.2.2.3.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. Output capacitance above 100 µF needs to have a
ESR of ≥ 10 mΩ for stable operation. The architecture of the TPSM82901 allows the use of tiny ceramic output
capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and
are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation
with temperature, use X7R or X5R dielectric. Using a higher value has advantages like smaller voltage ripple
and a tighter DC output accuracy in power save mode (see the Optimizing the TPS62130/40/50/60 Output Filter
application report).
In power save mode, the output voltage ripple depends on the output capacitance, its ESR, ESL, and the peak
inductor current. Using ceramic capacitors provides small ESR, ESL, and low ripple. The output capacitor needs
to be as close as possible to the device.
For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance must be
observed.
8.2.2.3.2 Input Capacitor
For most applications, 10 µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
must be placed between VIN and GND as close as possible to those pins.

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Table 8-3. List of Capacitors

Type (1) Nominal Capacitance [µF] Voltage Rating [V] Size Manufacturer
C3216X7R1E106K160AB 10 25 0805 TDK
C2012X7S1A226M125AC 22 10 0805 TDK

(1) Lower of IRMS at 40°C rise or ISAT at 30% drop

8.2.2.3.3 Soft-Start Capacitor

A capacitor connected between SS/TR pin and GND allows a user-programmable start-up slope of the output
voltage.
ISS

SS/TR

to VREF

Figure 8-2. Soft-Start Operation Simplified Schematic

An internal constant current source is provided to charge the external capacitance. The capacitor required for a
given soft-start ramp time is given by:

I SS
CSS TSS u
VREF (11)

where
• CSS is the capacitance required at the SS/TR pin.
• TSS is the desired soft-start ramp time.
• ISS is the SS/TR source current, see the Electrical Characteristics.
• VREF is the feedback regulation voltage divided by tracking gain (VFB/0.75), see the Electrical Characteristics.
The fastest achievable typical ramp time is 150 µs even if the external Css capacitance is lower than 680 pF or
the pin is open.
8.2.2.4 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the
Electrical Characteristics.
ISS

SS/TR

to VREF

Figure 8-3. Tracking Operation Simplified Schematic

VFB 0.75 u VSS /TR (12)

When the SS/TR pin voltage is above 0.8 V, the internal voltage is clamped and the device goes to normal
regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage

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is inside the recommended operating conditions. For decreasing SS/TR pin voltage in PFM mode, the device
does not sink current from the output. The resulting decrease of the output voltage can therefore be slower than
the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the
voltage rating of the SS/TR pin, which is 6 V. The SS/TR pin is internally connected with a resistor to GND when
EN = 0.
If the input voltage drops below undervoltage lockout, the output voltage goes to zero, independent of the
tracking voltage. Figure 8-4 shows how to connect devices to get ratiometric and simultaneous sequencing by
using the tracking function.
Device 1
TPSM8290x
VIN=12V VOUT1
VIN VOUT

EN GND
10uF R1 22
F
SS/ FB/
TR VSET

MODE/
R2
PG
S-CONF
CSS R3

Device 2
TPSM8290x
VOUT2
VIN VOUT

EN GND
R7 22 F
10uF R4
SS/ FB/
TR VSET

MODE/ R5
PG
S-CONF
R8 R6

Figure 8-4. Schematic for Ratiometric and Simultaneous Start-Up

The resistive divider of R7 and R8 can be used to change the ramp rate of VOUT2 to be faster, slower, or the
same as VOUT1.
A sequential start-up is achieved by connecting the PG pin of VOUT of device 1 to the EN pin of device 2. PG
requires a pullup resistor. Ratiometric start-up sequence happens if both supplies are sharing the same soft-start
capacitor. Equation 11 gives the soft-start time, though the SS/TR current has to be doubled. Details about these
and other tracking and sequencing circuits are found in Sequencing and Tracking With the TPS621-Family and
TPS821-Family application report.

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Note
If the voltage at the FB pin is below its typical value of 0.6 V, the output voltage accuracy can have a
wider tolerance than specified. The current of 2.5 µA out of the SS/TR pin also has an influence on the
tracking function, especially for high resistive external voltage dividers on the SS/TR pin.

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8.2.3 Application Curves

100% 100%

90% 90%

80% 80%

70% 70%
Efficiency (%)

Efficiency (%)
60% 60%

50% 50%

40% 40%

30% 30%
VIN=17V VIN=17V
20% VIN=15V 20% VIN=15V
VIN=12V VIN=12V
VIN=9V VIN=9V
10% VIN=6V 10% VIN=6V
VIN=3V VIN=3V
0 0
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1 1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1
IOUT (A) IOUT (A)

Auto PFM/PWM Fsw = 1 MHz Auto PFM/PWM Fsw = 2.5 MHz

Figure 8-5. Efficiency vs Output Current Figure 8-6. Efficiency vs Output Current
VOUT = 1.2 V VOUT = 1.2 V
100% 100%

90% 90%

80% 80%

70% 70%
Efficiency (%)

Efficiency (%)

60% 60%

50% 50%

40% 40%

30% 30%
VIN=17V VIN=17V
20% VIN=15V 20% VIN=15V
VIN=12V VIN=12V
VIN=9V VIN=9V
10% VIN=6V 10% VIN=6V
VIN=3V VIN=3V
0 0
0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 0.7 1 1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1
IOUT (A) IOUT (A)

FPWM Fsw = 1 MHz Auto PFM/PWM Fsw = 1 MHz

Figure 8-7. Efficiency vs Output Current Figure 8-8. Efficiency vs Output Current
VOUT = 1.2 V VOUT = 1.8 V
100% 100%

90% 90%

80% 80%

70% 70%
Efficiency (%)

Efficiency (%)

60% 60%

50% 50%

40% 40%

30% 30%
VIN=17V VIN=17V
20% VIN=15V 20% VIN=15V
VIN=12V VIN=12V
VIN=9V VIN=9V
10% VIN=6V 10% VIN=6V
VIN=3V VIN=3V
0 0
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1 0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 0.7 1
IOUT (A) IOUT (A)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 1 MHz

Figure 8-9. Efficiency vs Output Current Figure 8-10. Efficiency vs Output Current
VOUT = 1.8 V VOUT = 1.8 V

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100% 100%

90% 90%

80% 80%

70% 70%
Efficiency (%)

Efficiency (%)
60% 60%

50% 50%

40% 40%

30% 30%

20% VIN=17V 20% VIN=17V

VIN=15V VIN=15V
VIN=12V VIN=12V
10% VIN=9V 10% VIN=9V
VIN=6V VIN=6V
0 0
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1 0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 0.7 1
IOUT (A) IOUT (A)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 2.5 MHz

Figure 8-11. Efficiency vs Output Current Figure 8-12. Efficiency vs Output Current
VOUT = 3.3 V VOUT = 3.3 V
100% 100%

90% 90%

80% 80%

70% 70%
Efficiency (%)

Efficiency (%)
60% 60%

50% 50%

40% 40%

30% 30%

20% 20%
VIN=17V VIN=17V
VIN=15V VIN=15V
10% VIN=12V 10% VIN=12V
VIN=9V VIN=9V
0 0
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1 0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 0.7 1
IOUT (A) IOUT (A)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 2.5 MHz

Figure 8-13. Efficiency vs Output Current Figure 8-14. Efficiency vs Output Current
VOUT = 5.5 V VOUT = 5.5 V
2 3.5
IOUT=1A IOUT=1A
IOUT=0.4A IOUT=0.4A
1.75 IOUT=0.1A IOUT=0.1A
3

1.5
2.5

1.25
Fsw (MHz)

Fsw (MHz)

2
1
1.5
0.75

1
0.5

0.25 0.5

0 0
2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18
VIN (V) VIN (V)

Auto PFM/PWM Fsw = 1 MHz Auto PFM/PWM Fsw = 2.5 MHz

Figure 8-15. Switching Frequency vs Input Voltage Figure 8-16. Switching Frequency vs Input Voltage
VOUT = 1.2 V VOUT = 1.2 V

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1.75 1.75
IOUT=1A IOUT=1A
IOUT=0.4A IOUT=0.4A
IOUT=0.1A IOUT=0.1A
1.5
1.5

1.25

1.25
Fsw (MHz)

Fsw (MHz)
1

0.75
1

0.5

0.75
0.25

0.5 0
2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18
VIN (V) VIN (V)

FPWM Fsw = 1 MHz Auto PFM/PWM Fsw = 1 MHz

Figure 8-17. Switching Frequency vs Input Voltage Figure 8-18. Switching Frequency vs Input Voltage
VOUT = 1.2 V VOUT = 1.8 V
4.5 1.5
IOUT=1A IOUT=1A
IOUT=0.4A IOUT=0.4A
4 IOUT=0.1A IOUT=0.1A

3.5
1.25

3
Fsw (MHz)

Fsw (MHz)
2.5
1
2

1.5

0.75
1

0.5

0 0.5
2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18
VIN (V) VIN (V)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 1 MHz

Figure 8-19. Switching Frequency vs Input Voltage Figure 8-20. Switching Frequency vs Input Voltage
VOUT = 1.8 V VOUT = 1.8 V
3.5 3.25
IOUT=1A IOUT=1A
IOUT=0.4A IOUT=0.4A
IOUT=0.1A IOUT=0.1A
3
3

2.5

2.75
Fsw (MHz)

Fsw (MHz)

1.5
2.5

2.25
0.5

0 2
5 7 9 11 13 15 17 18 4 6 8 10 12 14 16 18
VIN (V) VIN (V)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 2.5 MHz

Figure 8-21. Switching Frequency vs Input Voltage Figure 8-22. Switching Frequency vs Input Voltage
VOUT = 3.3 V VOUT = 3.3 V

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4 3.25
IOUT=1A IOUT=1A
IOUT=0.4A IOUT=0.4A
3.5 IOUT=0.1A IOUT=0.1A

3 3

2.5
Fsw (MHz)

Fsw (MHz)
2 2.75

1.5

1 2.5

0.5

0 2.25
8 10 12 14 16 18 8 10 12 14 16 18
VIN (V) VIN (V)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 2.5 MHz

Figure 8-23. Switching Frequency vs Input Voltage Figure 8-24. Switching Frequency vs Input Voltage
VOUT = 5.5 V VOUT = 5.5 V
1.8125
VIN=17V
VIN=15V
VIN=12V
1.81
VIN=9V
VIN=6V
VIN=3V
1.8075
VOUT (DC)

1.805

1.8025

1.8

1.7975

1.795
0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 0.7 1
IOUT (A) VIN = 12 V 1-MHz FPWM IO = 0 mA
FPWM Fsw = 1 MHz VOUT = 1.2 V TA = 25°C

Figure 8-25. Output Voltage vs Output Current Figure 8-26. Start-Up Timing
VOUT = 1.8 V

VIN = 12 V 1-MHz Auto IO = 1 A VIN = 12 V 2.5-MHz FPWM IO = 1 A

PFM/PWM VOUT = 5 V TA = 25°C
VOUT = 1.8 V TA = 25°C Figure 8-28. Start-Up Timing
Figure 8-27. Start-Up Timing

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VIN = 12 V 2.5-MHz IO = 1 A VIN = 12 V 1-MHz Auto IO = 1 A

PFM/PWM PFM/PWM
VOUT = 5 V TA = 25°C VOUT = 1.2 V TA = 25°C

Figure 8-29. Start-Up Timing Figure 8-30. Output Voltage Ripple

VIN = 12 V 1-MHz Auto IO = 0.1 A VIN = 12 V 2.5-MHz Auto IO = 1 A

PFM/PWM PFM/PWM
VOUT = 1.2 V TA = 25°C VOUT = 1.2 V TA = 25°C
Figure 8-31. Output Voltage Ripple Figure 8-32. Output Voltage Ripple

VIN = 12 V 2.5-MHz Auto IO = 0.1 A VIN = 12 V 2.5-MHz Auto IO = 1 A

PFM/PWM PFM/PWM
VOUT = 1.2 V TA = 25°C VOUT = 3.3 V TA = 25°C

Figure 8-33. Output Voltage Ripple Figure 8-34. Output Voltage Ripple

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VIN = 12 V 2.5-MHz FPWM IO = 0.1 A VIN = 12 V 2.5-MHz FPWM IO = 1 A

VOUT = 3.3 V TA = 25°C VOUT = 5.0 V TA = 25°C

Figure 8-35. Output Voltage Ripple Figure 8-36. Output Voltage Ripple

VIN = 12 V 2.5-MHz Auto PFM/PWM VIN = 12 V 1-MHz Auto IO = 0.1 A to 1 A

VOUT = 5.0 V IO = 1 A TA = 25°C PFM/PWM
VOUT = 1.2 V TA = 25°C
Figure 8-37. Output Voltage Ripple
Figure 8-38. PSM-to-PWM Transition

VIN = 12 V 1-MHz Auto IO = 5 mA to 1 A to 5 VIN = 12 V 1-MHz Auto IO = 5 mA to 1 A

PFM/PWM mA PFM/PWM
VOUT = 1.2 V TA = 25°C VOUT = 1.2 V TA = 25°C

Figure 8-39. Load Transient Response Figure 8-40. Load Transient Response – Rising
Edge

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VIN = 12 V 1-MHz Auto IO = 1 A to 5 mA VIN = 12 V IO = 5 mA to 1 A to 5 mA

PFM/PWM VOUT = 3.3 V 2.5-MHz Auto TA = 25°C
VOUT = 1.2 V TA = 25°C PFM/PWM

Figure 8-41. Load Transient Response – Falling Figure 8-42. Load Transient Response
Edge

VIN = 12 V 2.5-MHz FPWM IO = 5 mA to 1 A to 5 VIN = 12 V Output Discharge = Yes

mA VOUT = 1.2 V TA = 25°C
VOUT = 3.3 V TA = 25°C
Figure 8-44. Output Discharge Function – Enabled
Figure 8-43. Load Transient Response
1.6 1.6
VIN=15V VIN=15V
VIN=12V VIN=12V
1.4 VIN=9V 1.4 VIN=9V

1.2 1.2

1 1
IOUT (A)

IOUT (A)

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
25 35 45 55 65 75 85 95 105 115 125130 25 35 45 55 65 75 85 95 105 115 125130
Ambient Temperature ( °C ) Ambient Temperature ( °C )

Auto PFM/PWM Fsw = 2.5 MHz Auto PFM/PWM Fsw = 2.5 MHz

Figure 8-45. Thermal Derating VOUT = 1.2 V Figure 8-46. Thermal Derating VOUT = 3.3 V

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8.3 Typical Application with Setable VO Using VSET

VIN VOUT
TPSM8290x
3V t 17V 0.4V t 5.5V
VIN VOUT

EN GND C2
C1
10…F 22…F
FB/
SS/TR
VSET

MODE/ R2
PG
S-CONF
C3 R3

Figure 8-47. Typical Application Circuit (VSET)

8.3.1 Design Requirements

VSET allows the user to set the output voltage using only one resistor to ground on the FB/VSET pin. Table 7-3
shows the 16 available options.
8.3.2 Detailed Design Procedure
The VSET option needs to be selected using the MODE/S-CONF pin. After the device is configured to VSET
operation, VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by
an external resistor R2 connected between FB/VSET and GND.

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8.3.3 Application Curves

VIN = 12 V 1-MHz Auto IO = 1 A VIN = 12 V 1-MHz Auto IO = 100 mA

VOUT = 0.4 V PFM/PWM TA = 25°C VOUT = 0.4 V PFM/PWM TA = 25°C

Figure 8-48. Output Voltage Ripple Figure 8-49. Output Voltage Ripple

VIN = 12 V 1-MHz FPWM IO = 1 A VIN = 12 V 1-MHz FPWM IO = 100 mA

VOUT = 0.4 V TA = 25°C VOUT = 0.4 V TA = 25°C

Figure 8-50. Output Voltage Ripple Figure 8-51. Output Voltage Ripple
1.2 90%
-40C
-20C
1.15 0C 80%
25C
85C
125C 70%
1.1
) Accuracy VSET (

60%
1.05
Efficiency (%)

50%
1
40%
0.95
30%
Vout

0.9
%

VIN=17V
±

20% VIN=15V
VIN=12V
0.85 VIN=9V
10%
VIN=6V
VIN=3V
0.8
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1
VIN (V) IOUT (A)
VIN = 3 V–17 V Temp = –40°C to 150°C Auto PFM/PWM Fsw = 1 MHz
Figure 8-52. Output Voltage Accuracy – VSET Figure 8-53. Efficiency vs Output Current
Selected VOUT = 0.4 V

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90% 90%

80% 80%

70% 70%

60% 60%
Efficiency (%)

Efficiency (%)
50% 50%

40% 40%

30% 30%
VIN=17V VIN=17V
20% VIN=15V 20% VIN=15V
VIN=12V VIN=12V
VIN=9V VIN=9V
10% 10%
VIN=6V VIN=6V
VIN=3V VIN=3V
0 0
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1 0.0005 0.001 0.002 0.005 0.01 0.020.03 0.05 0.1 0.2 0.3 0.5 0.7 1
IOUT (A) IOUT (A)

Auto PFM/PWM Fsw = 2.5 MHz FPWM Fsw = 1 MHz

Figure 8-54. Efficiency vs Output Current Figure 8-55. Efficiency vs Output Current
VOUT = 0.4 V VOUT = 0.4 V
2 2.5
IOUT=1A IOUT=1A
IOUT=0.4A IOUT=0.4A
1.75 IOUT=0.1A IOUT=0.1A

2
1.5

1.25
1.5
Fsw (MHz)

Fsw (MHz)

1
0.75

0.5
0.5

0.25

0 0
2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18
VIN (V) VIN (V)

Auto PFM/PWM Fsw = 1 MHz Auto PFM/PWM Fsw = 2.5 MHz

Figure 8-56. Switching Frequency vs Input Voltage Figure 8-57. Switching Frequency vs Input Voltage
VOUT = 0.4 V VOUT = 0.4 V
1.75 1.23
IOUT=1A VIN=17V
IOUT=0.4A VIN=15V
IOUT=0.1A 1.225 VIN=12V
VIN=9V
1.5 VIN=6V
1.22 VIN=3V

1.215
1.25
VOUT (DC)
Fsw (MHz)

1.21

1
1.205

1.2
0.75

1.195

0.5 1.19
2 4 6 8 10 12 14 16 18 1E-52E-5 0.0001 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1
VIN (V) IOUT (A)

FPWM Fsw = 1 MHz Auto PFM/PWM Fsw = 1 MHz

Figure 8-58. Switching Frequency vs Input Voltage Figure 8-59. Output Voltage vs Output Current
VOUT = 0.4 V VOUT = 1.2 V

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5.6
VIN=17V
VIN=15V
VIN=12V
VIN=9V

5.55

VOUT (DC)
5.5

5.45

5.4
1E-6 1E-5 0.0001 0.001 0.01 0.05 0.2 0.5 1
IOUT (A)

Auto PFM/PWM Fsw = 2.5 MHz

Figure 8-60. Output Voltage vs Output Current

VOUT = 5.5 V

8.4 Power Supply Recommendations

The power supply to the TPSM82901 must have a current rating according to the supply voltage, output voltage,
and output current of the TPSM82901.
8.5 Layout
8.5.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPSM82901 demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation, bad thermal performance, and noise sensitivity.
• See Figure 8-61 for the recommended layout of the TPSM82901, which is designed for common external
ground connections. TI recommends placing all components as close as possible to the package pins. The
input and output capacitors placement specifically, must be closest to the VIN, VOUT, and GND pins of the
TPSM82901.
• Provide low capacitive paths (with respect to all other nodes) for traces with high dv/dt. Therefore, the input
and output capacitance must be placed as close as possible to the IC pins and parallel wiring over long
distances as well as narrow traces must be avoided. Loops which conduct an alternating current must outline
an area as small as possible, as this area is proportional to the energy radiated.
• Sensitive nodes like FB needs to be connected with short wires and not nearby high dv/dt signals. As it
carries information about the output voltage, it must be connected as close as possible to the actual output
voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1 and R2,
must be kept close to the module and connect directly to those pins and the system ground plane. The same
applies to VSET resistor if VSET is used to scale the output voltage.
• The package uses the pins for power dissipation. Thermal vias on the VIN, VOUT, and GND pins help to
spread the heat through the PCB.
• In case of the EN, and MODE/S-CONF need to be tied to the input supply voltage at VIN, the connection must
be made directly at the input capacitor as indicated in the schematics.
• The SW/NC pin must not be connected to any other traces. For best practice, this pin must be left floating. If
the pin is soldered to PCB copper, the pour needs to be: as small as possible, no inner layer connections, no
vias, electrically floating, and limited to the pin area as possible.
• Refer to Figure 8-61 for an example of component placement, routing and thermal design. The recommended
layout is implemented on the EVM and shown in its user's guide.

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8.5.2 Layout Example

Figure 8-61. Layout

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8.5.2.1 Thermal Considerations

Implementation of power converter modules with low-profile and fine-pitch such as MircoSiP packages typically
requires special attention to power dissipation and thermal rise. Many system-dependent issues such as
thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating
components affect the power-dissipation limits of a given component.
The TPSM82901 is designed for a maximum operating junction temperature (TJ) of 125°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given,
the size of the surrounding copper area and a proper thermal connection of the module can reduce the thermal
resistance. To get an improved thermal behavior, TI recommends to follow the following guidelines:
• Use a multi-layer PCB boards (at least four layers, with 1-oz or more copper).
• Use thermal vias on the GND pin to connect the GND top layer with the GND inner and bottom layers. This
helps dissipate the heat across layers.
• Generate as large a GND plane as allowable on the top and bottom layers, especially right near the package.
The exposed thermal pad of the device sits right at the middle of the package. This is ideal for thermal
dissipation. To take advantage of that, TI recommends the ground plan to cross through the package to
allow maximum ground plan connection with the exposed pad. See Figure 8-61 how the north ground pour is
connecting with the south ground pour as it crosses through the exposed pad of the package.
• Use thermal vias on the VIN and VOUT pins (as close as possible to the pin) and around input and output
capacitors to connect the VIN and VOUT top layer with the inner and bottom layers. This helps dissipate the
heat across layers as well as decreases the resistance drop on these traces.
• Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance and
helps on thermal dissipation.
• Introduce airflow in the system if possible.
• Refer to Figure 8-61 for an example of component placement, routing and thermal design.
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics application reports.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
The device is qualified for long term qualification with a 125°C junction temperature.

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9 Device and Documentation Support

9.1 Device Support
9.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.1.2 Development Support
9.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM82901 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
MicroSiP™, SmartConfig™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 7-Dec-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPSM82901SISR ACTIVE uSiP SIS 11 3000 RoHS & Green ENEPIG Level-2-260C-1 YEAR -40 to 125 TM2901 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSM82901SISR uSiP SIS 11 3000 330.0 12.4 3.1 3.1 1.75 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPSM82901SISR uSiP SIS 11 3000 383.0 353.0 58.0

Pack Materials-Page 2
 PACKAGE OUTLINE
SIS0011A SCALE 4.000
MicroSiP
TM
- 1.6 mm max height
MICRO SYSTEM IN PACKAGE

2.9
B
2.7
(0.05) A

PIN 1 INDEX &

MARKING AREA

PKG 3.1
DESIGNATED LASER 2.9
MARKING AREA 2.7
TEXT HEIGHT TO BE 2.3
150um MINIMUM

PICK AREA
NOTE 3

PKG
(0.1)
(0.1) 2.2
1.8

1.60 MAX

SEATING PLANE
0.08 C
0.34 MAX 2.1
EXPOSED 0.94 (0.1) TYP
THERMAL PAD 0.86

5 0.29
6 6X
0.21
0.1 C A B
2X 0.05 C

2.275 SYMM
11
2.84
2.76 4X 0.5
0.565
4X
0.485

10
1

PIN 1 ID SYMM 0.54

10X
(OPTIONAL) 0.46
0.1 C A B
0.05 C
4226726/B 07/2021
MicroSiP is a trademark of Texas Instruments
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
SIS0011A MicroSiP
TM
- 1.6 mm max height
MICRO SYSTEM IN PACKAGE

10X (0.55) (0.9)

(R0.05)
TYP

1 10

4X (0.5)
11 SYMM (2.9)
2X
(2.325) (2.4)

6X (0.25)

5 6

4X (0.575) ( 0.2) SYMM

TYP
(2.15)

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE:25X

(0.07) TYP
(0.05) ALL AROUND
ALL AROUND
SOLDER MASK
METAL UNDER OPENING
SOLDER MASK

SOLDER MASK METAL

OPENING

SOLDER MASK NON-SOLDER

DEFINED MASK DEFINED

SOLDER MASK DETAIL

4226726/B 07/2021

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented

www.ti.com
 EXAMPLE STENCIL DESIGN
SIS0011A MicroSiP
TM
- 1.6 mm max height
MICRO SYSTEM IN PACKAGE

SOLDER MASK
EDGE TYP
2X (0.8)
10X (0.55)

1
10

2X
(1.3)

4X (0.5) 11
2X SYMM
(2.325)

2X
(0.75)
6X (0.25)

4X
5 (0.575)

6
(R0.05) EXPOSED
TYP SYMM METAL
TYP
(2.15)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4226726/B 07/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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