7/31/23, 9:32 PM "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

Home
VLSI Basic STA & Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video Lectures a
More SI

VLSI Industry: Insight About Us Recommended Book Papers VLSI Jobs

VLSI Concepts
Subscribe To VL
Po

Comments

An online information center for all who have Interest in Semiconductor Industry.
Translate page

Select Langu

A Manual QA's Favorite IDE

An All-In-One Test Automation Solution

Katalon

Get great deals at Acer

Acer Mall - Exclusive St
Mall
Index
Search This Blo

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8

STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics
VLSI Basics

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Index Chapter

Extraction &
Introductio Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other 1: Di
DFM
n Corner) Modeling Layer Variation Topic
Chapter 2: S

Thursday, April 7, 2011 Chapter 3: C

Chapter 4: C

"Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) Chapter 5: C

Featured Post

STA & SI:: Chapter 2: Static Timing Analysis 10 Employee

2.1 2.2 2.3a 2.3b 2.3c 2.4a Workplace
Basic Concept Of Basic Concept of Setup-Hold Examples:S-H Employees func
Timing Paths Time Borrowing Timing Path Delay
Setup-Hold Violation Time/Violation making sure tha
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b incredibly impor
Interconnect Delay Delay - Wire Load Maximum Clock Calculate “Max Clock Freq”- Fix Setup-Hold
Fix Setup-Hold Violation-1
Models Model Frequency Examples Violation-2
2.6c 2.7a 2.7b 2.7c 2.8
Fix Setup-Hold Incr/Decr Delay Incr/Decr Delay 10 ways to fix Setup-Hold
Incr/Decr Delay Method-3
Violation-3 Method-1 Method-2 Violation.

Static Timing analysis is divided into several parts:

Part1 -> Timing Paths Part2 - Part5b ->

> Time Borrowing Examples to
Part3a -> Basic Concept Of Setup and Hold calculate the

Part3b -> Basic Concept of Setup and Hold Violation “Maximum Clock

Part3c -> Practical Examples for Setup and Hold Time / Violation Part4a -> Frequency” for

Delay - Timing Path Delay different circuits.

Part4b -> Delay - Interconnect Delay Models Part4c -> Part 6a -> How to

Delay - Wire Load Model solve Setup and

Part5a -> Maximum Clock Frequency Hold Violation

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 1/
7/31/23, 9:32 PM "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
(basic example)

Videos

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 2/
7/31/23, 9:32 PM "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

Home PartVLSI
6b -> Basic
Continue of STA
How to
& solve
SI Setup and Hold &
Extraction Violation
DFM (Advance examples)
Low Power Physical Design Vlsi Interview Questions Video
Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI
VLVL
Jobs

Part 8 -> 10 ways to fix Setup and Hold Violation.

Its been long time, people are asking about Setup and Hold time blog. Finally time come for that. :) The way

we will discuss this concept in the following manner

1. What is SetUp and Hold time?

2. Definition of Setup and Hold.
3. Setup and Hold Violation.
4. How to calculate the Setup and Hold violation in a design?
Total Pageviews
I saw that lots of people are confused with respect to this concept. And the reason of this are

1. They know the definition but don't know the origin or say concept behind Setup and Hold timing.
11,721,
2. They know the formula for calculating setup and hold violation but don't know how this formula come in picture.
3. They become confuse by few of the terminology like capture path delay, launch path delay, previous clock cycle, current clock cycle, data path delay, slew,
setup slew, hold slew, min and max concept, slowest path and fastest path, min and max corner, best and worst case etc during the explanation of Setup and Popular Posts
Hold Timings/Violation.
"Timing Path
I hope I can clarify your confusion. Let me explain this and if you face any problem let me know. Timing Analy
basic (Part 1)
What is Setup and Hold time?
Basic of Timi
Analysis in P
To understand the origin of the Setup and Hold time concepts first understand it with respect to a System as shown in the fig. An Input DIN and external clock Design
CLK are buffered and passes through combinational logic before they reach a synchronous input and a clock input of a D flipflop (positive edge triggered). Now
to capture the data correctly at D flip flop, data should be present at the time of positive edge of clock signal at the C pin ( to know the detail just read basis "Setup and H
: Static Timin
of D flipflop). (STA) basic (
Note: here we are assuming D flip flop is ideal so Zero hold and setup time for this.
"Examples O
and Hold tim
Timing Analy
basic (Part 3

"Setup and H
Violation" : St
Timing Analy
basic (Part 3

10 Ways to fi
and HOLD vi
Static Timing
(STA) Basic (

Delay - "Wire
SetUp and Hold Time of a System Model" : Stati
Analysis (ST
(Part 4c)
There may be only 2 condition.
"Time Borrow
Tpd DIN > Tpd Clk Static Timing
(STA) basic (
For capture the data at the same time when Clock signal (positive clock edge) reaches at pin C, you have to apply the input Data
at pin DIN "Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK. Delay - "Inter
In other word, at DIN pin, Data should be stable "Ts(in)" time before the positive clock edge at CLK pin. Delay Models
Timing Analy
This Time "Ts(in)" is know as Setup time of the System. basic (Part 4
Tpd DIN < Tpd Clk
Maximum Cl
For capture the data at the same time when clock signal (positive clock edge) reaches at pin C, input Data at pin DIN should not Frequency :
change before "Th(in)= (Tpd Clk) - (Tpd DIN)" time. If it will change, positive clock edge at pin C will capture the next data. Timing Analy
basic (Part 5
In other word, at DIN pin, Data should be stable "Th(in)" time after the positive clock edge at CLK pin.
This time "Th(in)" is know as Hold Time of the System.
EDN Feed
From the above condition it looks like that both the condition can't exist at the same time and you are right. But we have to consider few more things in
this. Macro model
engineers sim
Worst case and best case (Max delay and min delay) circuits and s
Because of environment condition or because of PVT, we can do this analysis for the worst case ( max delay) and best case ( min Automate ES
delay) also. protection ve
for complex I
Shortest Path or Longest path ( Min Delay and Max delay)
Formal-base
If combinational logic has multiple paths, the we have to do this analysis for the shortest path ( min delay) and longest path ( max methodology
digital design
delay) also. verification ti
So we can say that above condition can be like this. Getting in sy
UVM sequen
Tpd DIN (max) > Tpd Clk (min)
Get those clo
SetUp time == Tpd DIN (max) - Tpd Clk (min) domains in s

Tpd DIN (min) < Tpd Clk (max)

Hold time == Tpd Clk (max) - Tpd DIN (min)

For example for combinational logic delays are Followers

Data path (max, min) = (5ns, 4 ns)

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 3/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
Clock path (max, min) = (4.5ns, 4.1ns) Followers
Home
(74 VLSI Basic STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video
Then Setup time= 5-4.1=0.9ns
Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI

Jobs

Now similar type of explanation we can give for a D flip flop. There is a combinational logic between C and Q , between D and Q of the Flipflop.

Positive Edge Triggered D flip-

There are different ways for making the D flip flop. Like by JK flipflop, master slave flipflop, Using 2 D type latches etc. Since the internal circuitry is
different for each type of Flipflop, the Setup and Hold time is different for every Flipflop.

Definition:
Setup Time:
Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the
clock. This applies to synchronous circuits such as the flip-flop.
Or In short I can say that the amount of time the Synchronous input (D) must be stable before the active edge of the Clock. The Time
when input data is available and stable before the clock pulse is applied is called Setup time.
Hold time:
Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This
applies to synchronous circuits such as the flip-flop.
Or in short I can say that the amount of time the synchronous input (D) must be stable after the active edge of clock. The Time
after clock pulse where data input is held stable is called hold time.

Setup and Hold Violation:

In simple language-
If Setup time is Ts for a flip-flop and if data is not stable before Ts time from active edge of the clock, there is a Setup violation at that flipflop. So if data is
changing in the non-shaded area ( in the above figure) before active clock edge, then it's a Setup violation.
And If hold time is Th for a flip flop and if data is not stable after Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is
changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.

How to calculate the setup and hold violation in a design.. please see the next blog.

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 4/1
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

Home VLSI Basic STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video

Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI

Jobs

Posted by VLSI Expert at 3:09 PM

87 comments:
Unknown April 20, 2011 at 5:41 PM

this is really useful... thank you very much...

Really looking forward for your future posts...

Reply

VLSI Expert April 21, 2011 at 10:27 AM

Thanks for such comments. I will update you once there will be any new post. you can also subscribe to my blog or by twitter account to get a regular update.

Reply

Anonymous April 23, 2011 at 11:26 PM

Nice explanation with useful examples. Thanks!!

Reply

Anonymous July 6, 2011 at 12:25 AM

your work is really very helpful..

Reply

Anonymous July 14, 2011 at 11:14 PM

Thanks man ur work cleared most of my concepts....

Reply

Anonymous August 3, 2011 at 2:35 AM

it was like drinking water in the middle of the desert. so satisfying

Reply

your VLSI August 3, 2011 at 2:20 PM one

of the nice compliment I ever get.

thanks man

Reply

Anonymous August 11, 2011 at 2:50 AM

what is meaning of negative propagation delay ? and

how to obtain it?

Reply

naveen August 12, 2011 at 5:44 PM

Hey.. This blog is awesome. I was very confused with setup and hold time. I had to attend NVIDIA interview. Very happy tat i got to know this blog at the right
time. I was able to answer qns on setup and hold time violations. And i got selected.. Thanks a lotttttttttttt :)

Reply

Replies

saurabh gupta July 11, 2012 at 10:24 AM hi

naveen,

congrts for ur selection...can you tell me wat type of questions do they ask in interview and written and how shud i prepare for that??....

Reply

VLSI Expert August 16, 2011 at 11:52 AM

Hi Naveen,
Thanks for compliment.. and congrats for NVIDIA selection. i am happy for you.

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 5/1
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
Hi Anonymous- with respect to negative propagation delay.. I am going to post it in FAQ section. You will find that soon. Drop a mail to my mail id ... I will let
Home VLSI
you Basic
know as soon as I STA & SI
post their. Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video

Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI

Jobs

hi.. even i too have the same doubt about -ve propagation delay.. send
me also..

voonnasandeep@gmail.com

Reply

Ramkumar September 5, 2011 at 1:08 AM

Not a single textbook out there explains these things in such an easy to understand manner !!

Brilliant work :)
Reply

Anonymous October 8, 2011 at 3:38 AM

jbhjbbhjuh

Reply

avi October 8, 2011 at 3:45 AM

Hi when a Setup or Hold time violation happens the flip flop enters into metastable state and the output will be unpredictable. But there is a statement in the section
'Tpd DIN < Tpd CLK' saying that the if there is a hold time violation the next data will be sampled. Isn't the unpredictability of the output in the metastable state the
main problem?

Reply

Replies

SCN October 19, 2016 at 1:57 AM

Hey AVI that is the actual problem with the hold violation. Both the ways it is true next data will be sampled and data is unpredictable. during one clock
period only one data should be captured and you are expecting the data that is just launched in the previous stage. But due to hold time violation that is
data arriving very quickly the data that should be captured in the next clock will be captured in the present clock and you are unaware of the data that is
captured and you cannot how that will modify your circuit functionality.

Reply

joy December 7, 2011 at 11:35 AM

u r just great..............helpful blog,want to get more like this..................good job

Reply

Vee Eee Technologies December 8, 2011 at 5:48 PM

Thanks for sharing your info. I really appreciate your efforts and I will be waiting for your further write ups thanks once again.

Reply

pruthvi December 9, 2011 at 12:47 AM

THANKS for sharing your information..!

Reply

Amit December 15, 2011 at 12:26 AM hi

there,
your article on setup and hold time is superb ,finally reached here after searching over the net Reply

VLSI Expert December 15, 2011 at 11:13 AM

thanks all for appreciating my work.

Reply

Anonymous December 20, 2011 at 3:14 AM Great

work... crystal clear..

Reply

Anonymous February 20, 2012 at 1:52 AM

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 6/1
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
admin , i reaaly vey thankful to u.......i am trying to larn this all the stuffs from past 1 months but got cleared after reading ur blog....u r d best...keep adding
Home VLSI
more Basic
...also add some STA & SI onExtraction
more examples & freq
how to find max DFM of clockLow Power Physicalagain!
in STA.............................thanks Design Vlsi Interview Questions Video

Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI

Jobs

i feel very happy to get d concept very clearly. thanks to u for spending time in sharing all this. u r doing a great job especially for students like
me...thank u so much::)

Reply

koppad April 3, 2012 at 6:06 PM

God cudnt be everywer to clear doubts so created experts like you!

sir,so simple and so clear explanation.

ultimate destination for timing analysis.

Reply

siv April 3, 2012 at 6:09 PM 1

doubt, wat hapns if

Tpd DIN = Tpd Clk?

it was askd in d interview.

vil it be setup time or hold time vilolation?!

Reply

Replies

VLSI Expert April 4, 2012 at 10:20 AM

Hi Siv,

Its there in the blog itself.

See for setup following condition should met..
Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
for hold following

Now if TpdDIN = Tpd Clk -- Means data is not getting proper time to get stable before clock -- so this is the case of Setup Violation for sure.

for hold data should be stable after that (clock pulse)... and data can change only when next data will come (just to replace the previous one).. so if for
every data stream Tpd DIN == Tpd CLK -- then data remain stable for 1 clock pulse in general. And there should not be any hold violation.

I hope you get my point.

Unknown April 4, 2017 at 12:57 AM

In my opinion, if TpdDin = TpdClk Din signal should meet Ts and Th times of internal FF. So as we have ideal FF here Din and Clk can go
simultaneously without violation.

Please correct me if i'm wrong.

Reply

siv April 3, 2012 at 6:16 PM

vil ther be set up and hold time for latches?

as both input(D and clk pass thru same gates, unlike diff gates in FF) Reply

Replies

VLSI Expert April 4, 2012 at 10:22 AM

there are .. please check the basic knowledge from the previous part of this series.
Sometime later I will post a blog for setup and hold analysis for latches also.

siv April 4, 2012 at 11:32 AM

thanq u so much
i AM so curious to know MORE about u, plz tell, r u IIT PROFESSOR?

NTING IS AVAILABLE ABOUT U IN "ABOUT ME"

Reply

koppad April 12, 2012 at 7:56 PM

Sir, i Got job in LSI LOGIC, SOC design engineer.

Thank you so much for your blog. I wanted to know more about u plz.

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 7/1
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
Reply
Home VLSI Basic STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video
Lectures

VLSI Industry: Insight About Us Recommended Book Papers VLSI Jobs

VLSI Expert April 13, 2012 at 11:45 

First of all, congrats to you. What exactly you wanted to know about me? Please drop me a mail on my mail id.

Reply

siv April 12, 2012 at 7:57 PM

koppad and siv , both are me only.

Reply

rishitha April 13, 2012 at 11:09 AM

Thanks a lot sir.i read so many ebooks pdfs but nothing has given me this much clarity.can you please explain with different problems so that it will be easy for me
to attend for an interview

Reply

Replies

VLSI Expert April 13, 2012 at 11:44 AM

I will try .. in the mean time please read next 2 parts.. there you will get a lot of other example.

Reply

rishitha April 19, 2012 at 2:47 PM sir,

does your blog contains info regarding VERILOG and SYSTEM VERILOG also???i am working for a company fron past 1 year .I have done only one project in
vhdl.Now layoff started in my compny.I want to shift.So can please guide me

Reply

Replies

VLSI Expert April 24, 2012 at 11:39 AM

Hi Rishitha,

Right Now, there is no info regarding Verilog in my blog. There are plan for doing this .. but not in near future. But you can find a lot of info on other
blogs/website.

Reply

raviteja May 8, 2012 at 3:14 PM

This comment has been removed by the author.

Reply

raviteja May 8, 2012 at 3:17 PM Hi

Your Vlsi,

Your Blog is very useful to me..........,I am a fresher 2011 pass out searching for job in Backend(Vlsi physical design).I have taken training in Vlsi Physical
Design for Eight months if their are any fresher openings you please post in this blog or mail me at raviteja.vlsi@hotmail.com.........................,Really this blog is
very useful to me....,Before knowing this blog i was little confused with setup and hold time calculations but now it is clarified...., Thank You Very Much. ,

D.Raviteja

Reply

Replies

VLSI Expert May 28, 2012 at 7:34 AM

Hi Ravi,
Its very difficult to trace the opining for fresher/experienced people in the VLSI domain right now. So I can't promise you regarding this. But there are
several other sites where you can check and apply also.

Reply

Anonymous May 14, 2012 at 3:25 PM

thanks a lot.. this was a very useful article and really cleared away confusions Reply

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 8/1
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
Hi,
Home I VLSI
am notBasic
able to clearlySTA & SI the explaination
understand Extraction & DFM
given Low time.
for What is Setup Power Physical
Can you please Design
explain more in detailVlsi Interview
by giving numbersQuestions
along with Video
Lectures
waveforms for Tpd DIN and Tpd CLK.For example::

VLSI Industry: Insight About Us Recommended Book Papers VLSI Jobs

at 6ps, then as per the explaination we have to apply data at DPIN at 1 ps (7-6) before the positive edge which occurs at pin CLK which occurse at 2 ps. But the
data will be captured at 2ps and as Tpd DIN is 7ps it will reach D pin of the flop at 9ps.
2) Let us take only Tpd DIN = 7ps and Tpd = 6ps
>>>apply the input Data at pin DIN "Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK. At
which time the positive edge will occur so that we can apply the input data.
Please correct if i am wrong.
Thanks

Reply

Anonymous June 29, 2012 at 3:32 PM hi

superb explanation

Reply

Anonymous August 31, 2012 at 4:45 PM

You defined setup and hold time for a system. I want to know how setup and hold time is calculated for a flip flop ? Reply

Replies

VLSI Expert September 1, 2012 at 12:29 PM

flip-flop is also a system.. you can see that I have applied the same concept for D type of flipflop.

Darshan July 11, 2020 at 5:42 PM

Is library setup time and system setup time is different??

Reply

tamilan April 15, 2013 at 8:52 PM

Hi ,
I am a bit confused about the minimum and maximum conditions used for the below conditions. Tpd
DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

Kindly help to elucidate the reason for the selection of min and max values for the setup and hold times. Reply

Anonymous April 22, 2013 at 11:30 PM

This blog is simply mind blowing...all compact and easy to understand sections...thanx a lot dude..!! Reply

Anonymous April 27, 2013 at 3:25 PM

Thanks for your explanation. Before your notes, I was in a state of lack of clarity of setup and hold time, I know their definitions but I was unable to apply them
to the circuits. Now I got the clarity. I have a doubt. Why people always hide things of their knowledge. They always confuse us by saying definitions. They never say
any thing clearly like u. Thank you one more time. I hope u should continue this block for us.

Reply

Unknown May 12, 2013 at 6:35 AM

This comment has been removed by the author.

Reply

Anonymous May 12, 2013 at 6:39 AM

Hi Thanks for the concepts you have explained. It is awesome !!! I had an interview question like this: Which is more important - Set up time or hold time?

Reply

Replies

Anonymous May 12, 2013 at 6:46 AM

Can you give me an answer for that?

What happens to the system if the clock frequency is reduced?

VLSI Expert May 13, 2013 at 9:44 AM

Hi,

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 9/1
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 10/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
Please refer 6a,6b and 6c and also 5a and 5b. I am sure you will get the ans.
Home VLSI Basic
See I can ansSTA
here ..&but
SImy intension
Extraction
is that u& DFMfigure out
should Low yourPower
own with the Physical Design
help of basics. :) Still u Vlsi Interview Questions Video
Lectures
didn't get the ans.. ping me again.

Hareesh Vemulachedu June 28, 2013 at 7:28 AM HI

There is a mistake there .. corrected below

And If hold time is Th for a flip flop and if data is not stable ***** Before ***** Th time from active edge of the clock , there is a hold violation at that flipflop.
So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.

Reply

fullchipdesign October 2, 2013 at 7:58 PM This

doesn't look right?

Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min) Tpd
DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

It needs to other way round?

SetUp time == Tpd Clk (min) - Tpd DIN (max)

Reply

Unknown October 23, 2013 at 12:12 AM

Finally i got what exactley setup and hold time .Thanks a lott Sir

Reply

Unknown December 6, 2013 at 7:35 AM

Thanks a lot for the blog itz very needfull especially for beginners. Each and every concept explained in depth with different examples. Reply

Anonymous January 11, 2014 at 12:20 AM

Thanks very much,this stuff is very good for setup and hold time concept Reply

Anonymous January 19, 2014 at 10:56 AM

it was really helpful...topics were broadly covered and well explained..thnx Reply

Anonymous January 23, 2014 at 11:29 PM

Blogs like vlsi-expert, digitalelectronics, etc. are all owned and updated by Indians. You guys make us all so very proud!

This blog is simply incredible!!!

Reply

Anonymous February 23, 2014 at 11:18 PM

Hi! I must congratulate you for this wonderful blog that you've been maintaining, and must say that it's been of much help. However, I

find one thing confusing here.

I think the Setup and Hold time equations should be:

T(set-up)[max] = T(clock)[min] - T(data)[max]
T(hold)[max] = T(data)[min] - T(clock)[max]

The only difference between what I think and what's present in the above article is the sign of the result, but even that is quite significant!

In my equation, when the min. Clock time is larger than the max. Data time, we get a +ve Set-up time, like should usually be. Your equation, though yields a +ve
Set-up time when the max. Data time is larger than the min. Clock time, which instead looks like Set-up violation!

I will be extremely grateful to you if you could clarify this point to me and remove my confusion. I might have missed some point here. I'm sure many others must
have had this doubt, so your reply to this comment could benefit many, including me!

Thanks again, for your wonderful blog!

Reply

Replies

Anonymous February 24, 2014 at 2:49 AM

I think I've got the point here! Oh yes, I think I have!

The equation you've posted here is to calculate these times, and not validate. Yep, I've cracked it!! :) I will still

await your valuable comment here. Intezaar rahegaa aapke beshkeemati tippanee kaa! :)

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 11/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
VLSI Expert
Home VLSI Basic STA &February
SI 24, 2014 at 1:41 PM
Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video

Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI

Jobs

Tpd DIN (max) > Tpd Clk (min)

SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

i understand this equation

T(set-up)[max] = T(clock)[min] - T(data)[max]
T(hold)[max] = T(data)[min] - T(clock)[max]

Unknown July 20, 2016 at 10:50 PM

I don't get it. If T clock min is more than T data max, time the clock pulse takes to travel is always more than the time data takes to transfer. That means,
clock will always reach after the data is received. So the data should hold it's stability until clock is reached. How can this time be called setup time?
To get a positive setup time from this equation,
T(set-up)[max] = T(clock)[min] - T(data)[max]
is not possible since if clock's min delay is more than data's max delay, it will be a case of Hold time and not setup time. Please correct me
where I am wrong.

Reply

Anonymous August 29, 2014 at 7:35 AM

This comment has been removed by a blog administrator.

Reply

Anonymous August 29, 2014 at 2:20 PM

This comment has been removed by a blog administrator.

Reply

Anonymous August 29, 2014 at 8:52 PM

This comment has been removed by a blog administrator.

Reply

Anonymous August 31, 2014 at 9:51 AM

This comment has been removed by a blog administrator.

Reply

Anonymous September 1, 2014 at 1:30 PM

This comment has been removed by a blog administrator.

Reply

Anonymous September 1, 2014 at 1:53 PM

This comment has been removed by a blog administrator.

Reply

Anonymous September 2, 2014 at 11:45 PM

This comment has been removed by a blog administrator.

Reply

Anonymous September 3, 2014 at 2:19 AM

This comment has been removed by a blog administrator.

Reply

Anonymous September 4, 2014 at 11:39 AM

This comment has been removed by a blog administrator.

Reply

Anonymous September 4, 2014 at 9:01 PM

This comment has been removed by a blog administrator.

Reply

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 12/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 13/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts
Anonymous September 5, 2014 at 8:27 PM
Home VLSI Basic STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video
This comment has been removed by a blog administrator.
Lectures VLSI Industry: Insight About Us Recommended Book Papers VLSI
Reply

Jobs

This comment has been removed by a blog administrator.

Reply

Anonymous September 7, 2014 at 10:34 PM

This comment has been removed by a blog administrator.

Reply

Anonymous January 13, 2016 at 12:29 AM

Can you suggest a book for this topic??

Reply

Unknown July 26, 2016 at 3:44 PM

Dear sir
please that set up time and hold time is for i/p or o/p or both or is set up is for i/p or hold is for o/p Reply

Unknown September 21, 2016 at 8:45 PM

Hi , It was really helpful, do you have any email address where i can send question about this material? I have some doubts. Reply

Anonymous February 7, 2017 at 5:54 PM

hi sir pictures are not loading can u solve the issue

Reply

Unknown April 7, 2017 at 9:21 AM

I have come across your this blog today. It is amazing.

I just want you to explain Set up and Hold time terms in cases where we use pipeline, putting fipflops between consecutive logics, because I'm not able to relate this
explanation in that case.
Thanks.

Reply

Unknown September 6, 2017 at 4:19 PM Hi,

Great post, I have few doubts.
1. You have discussed about tpd din> tpd clk and the reverse..What if Tpd din = Tpd clk?
for, example..I am feeding a 1Mhz input to both clock and data input, both of them are in phase... practically it will go
to metastable state ... will Tpd din == Tpd clk will lead to both setup and hold violation ? 2 . Is it okay to have
negative (-ve) setup time and hold time?

Reply

Chandrachur July 7, 2019 at 12:49 AM

Sir, could you please explain the concept of negative setup and hold times ? Reply

Unknown May 3, 2021 at 10:44 AM

without drawing waverforms, you dont understand whats going on Reply

Enter Comment

Newer Post Home Older Post

Subscribe to: Post Comments (Atom)

Must Read Article

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 14/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 15/
7/31/23, 9:32 "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) |VLSI Concepts

Home VLSI Basic STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Video
Lectures

Vlsi expert group. Powered by Blogger.

https://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html 16/