Scribd
Upload
54 views7 pages

Mechatronics 4

Uploaded by

Ab An
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
54 views7 pages

Mechatronics 4

Uploaded by

Ab An
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

ADDIS ABABA SCIENCE AND TECHNOLOGY

UNIVERSITY
COLLEGE OF ELECTRICAL AND MECHANICAL
ENGINEERING
DEPARTMENT OF MECHANICAL ENGINEERING
MECHATRONICS SYSTEMS
ASSIGNMENT
5/7/2022 GC

Group Members ID

Abdu Anwarr ETS0007/12

Aymen Muhaba ETS0105/12

Mickael Derbe ETS0462/12

Submitted to: Mr. Dilbante

Submission date: 5/28/2022


ATM machine microprocessor

ATM machine has a lot of microprocessors but the main one is Zilog z80 microprocessor made
by USA company Zilog.

Zilog Z80 microprocessor:

The Zilog Z80 family of components are fourth-generation enhanced microprocessors with exceptional
computational power. They offer higher system throughput and more efficient memory utilization than
comparable second- and third-generation microprocessors. The speed offerings from 6–20 MHz suit a
wide range of applications which migrate software. The internal registers contain 208 bits of read/write
memory that are accessible to the programmer. These registers include two sets of six general purpose
registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition,
there are two sets of accumulator and flag registers. The CPU is easy to incorporate into a system since it
requires only a single +5V power source. All output signals are fully decoded and timed to control
standard memory or peripheral circuits; the Z80 CPU is supported by an extensive family of peripheral
controllers.

It has 8-bit data and 16-bit address.

SPECIFICATIONS
Type Microprocessor
CPU part number OEM/troy
Frequency 2.5GHz
Package 40-PIN
Socket DIP 40
Manufacturing process MOS LSI
Manufacturer ZILOG
Physical memory 64 KB
Data 8-bit width
Width 16-bit
Clock frequency 6MHz
EEPROM memory capacity 512B
SRAM memory capacity 16KB

ARCHTECTURE

Clock Generator—Generates system clock from an external crystal or clock input. The

external clock is divided by two or one and provided to both internal and external devices.

Bus State Controller—This logic performs all of the status and bus control activity

associated with both the CPU and some on-chip peripherals.

Interrupt Controller—This logic monitors and prioritizes the variety of internal and

external interrupts and traps to provide the correct responses from the CPU. To maintain

compatibility with the Z80® CPU, three different interrupts modes are supported.

Memory Management Unit—The MMU allows you to map the memory used by the CPU

into the 1-MB addressing range supported by the Z80180. The

organization of the MMU object code allows maintenance compatibility with the Z80

CPU, while offering access to an extended memory space.

Programmable Reload Timers (PRT)—This logic consists of two separate channels,

each containing a 16-bit counter (timer) and count reload register. The time base for the

counters is derived from the system clock (divided by 20) before reaching the counter.

PRT channel 1 provides an optional output to allow for waveform generation.

Asynchronous Serial Communication Interface (ASC)—The ASCI logic provides two

individual full-duplex UARTs. Each channel includes a programmable baud rate generator

and modem control signals.

DMA Controller—The DMA controller provides high speed transfers between memory
and I/O devices. Transfer operations supported are memory-to-memory, memory to/from

I/O, and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA

transfers can access the full 1 MB address range with a block length up to 64 KB, and can

cross over 64K boundaries.


CPU Register
The Z80 CPU contains 208 bits of read/write memory that are available to the program
mer. Figure 2 shows how this memory is configured to eighteen 8-bit registers and four
16-bit registers. All Z80 CPU’s registers are implemented using static RAM. The registers
include special purpose register, general purpose register, arithmetic logic register, instruction register.
special purpose register
Program Counter (PC). The program counter holds the 16-bit address of the current
instruction being fetched from memory.
Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of a stack
located anywhere in external system RAM memory. The external stack memory is organized as a last-in
first-out (LIFO) file. Data can be pushed onto the stack from specific
CPU registers or popped off of the stack to specific CPU registers through the execution of
PUSH and POP instructions. The data popped from the stack is always the most recent
data pushed onto it.
Two Index Registers (IX and IY). The two independent index registers hold a 16-bit base
address that is used in indexed addressing modes. In this mode, an index register is used as
a base to point to a region in memory from which data is to be stored or retrieved.
Interrupt Page Address (I) Register. The Z80 CPU can be operated in a mode in which
an indirect call to any memory location can be achieved in response to an interrupt.
Memory Refresh (R) Register. The Z80 CPU contains a memory refresh counter,
enabling dynamic memories to be used with the same ease as static memories. Seven bits
of this 8-bit register are automatically incremented after each instruction fetch.
general purpose register
Two matched sets of general-purpose registers, each set containing six 8-bit registers, can
be used individually as 8-bit registers or as 16-bit register pairs. One set is called BC, DE,
and HL while the complementary set is called BC', DE', and HL'. At any one time, the programmer can
select either set of registers to work through a single exchange command for
the entire set. In systems that require fast interrupt response, one set of general-purpose
registers and an Accumulator/Flag Register can be reserved for handling this fast routine.
One exchange command is executed to switch routines. This process greatly reduces interrupt service
time by eliminating the requirement for saving and retrieving register contents
in the external stack during interrupt or subroutine processing.
Arithmetic Logic Unit
The 8-bit arithmetic and logical instructions of the CPU are executed in the Arithmetic
Logic Unit (ALU). Internally, the ALU communicates with the registers and the external
data bus by using the internal data bus. these includes: Add, subtract AND, OR, NAND, NOR…
Instruction Register
As each instruction is fetched from memory, it is placed in the Instruction Register and
decoded. The control sections perform this function and then generates and supplies the
control signals necessary to read or write data from or to the registers, control the ALU,
and provide required external control signals.
System bus

Memory
The Z80 uses 8-bit bytes which are stored in memory. These bytes contain both the program that the
processor is executing and the data items that the program is working on. The processor uses 16-bit
addresses to access these bytes So there can be anything up to 64k(65,536) bytes of memory
Figure below shows the timing of memory read or write cycles other than an op code fetch
cycle. These cycles are generally three clock periods long unless wait states are requested
by memory through the WAIT signal. The MREQ signal and the RD signal are used the
same way as in a fetch cycle. In a memory write cycle, the MREQ also becomes active
when the address bus is stable so that it can be used directly as a chip enable for dynamic
memories. The WR line is active when the data on the data bus is stable so that it can be
used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore,
the WR signal goes inactive one-half T state before the address and data bus contents are
changed so that the overlap requirements for almost any type of semiconductor memory
type is met.

Input or Output Cycles


Figure 7 shows an I/O read or I/O write operation. During I/O operations, a single wait
state is automatically inserted. The reason for this single wait state insertion is that during
I/O operations, the period from when the IORQ signal goes active until the CPU must
sample the WAIT line is short. Without this extra state, sufficient time does not exist for an
I/O port to decode its address and activate the WAIT line if a wait is required. Addition
ally, without this wait state, it is difficult to design MOS I/O devices that can operate at
full CPU speed. During this wait state period, the WAIT request signal is sampled.
During a read I/O operation, the RD line is used to enable the addressed port onto the data
bus, just as in the case of a memory read. The WR line is used as a clock to the I/O port for
write operations.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy